2020-09-21 13:37:30 +08:00
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;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
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circuit el2_ifu_ifc_ctrl :
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module el2_ifu_ifc_ctrl :
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input clock : Clock
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input reset : UInt<1>
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2020-09-23 18:27:02 +08:00
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output io : {flip free_clk : UInt<1>, flip active_clk : UInt<1>, flip rst_l : UInt<1>, flip scan_mode : UInt<1>, flip ic_hit_f : UInt<1>, flip ifu_ic_mb_empty : UInt<1>, flip ifu_fb_consume1 : UInt<1>, flip ifu_fb_consume2 : UInt<1>, flip dec_tlu_flush_noredir_wb : UInt<1>, flip exu_flush_final : UInt<1>, flip exu_flush_path_final : UInt<31>, flip ifu_bp_hit_taken_f : UInt<1>, flip ifu_bp_btb_target_f : UInt<31>, flip ic_dma_active : UInt<1>, flip ic_write_stall : UInt<1>, flip dma_iccm_stall_any : UInt<1>, flip dec_tlu_mrac_ff : UInt<31>, ifc_fetch_addr_f : UInt<31>, ifc_fetch_addr_bf : UInt<31>, ifc_fetch_req_f : UInt<1>, ifu_pmu_fetch_stall : UInt<1>, ifc_fetch_uncacheable_bf : UInt<1>, ifc_fetch_req_bf : UInt<1>, ifc_fetch_req_bf_raw : UInt<1>, ifc_iccm_access_bf : UInt<1>, ifc_region_acc_fault_bf : UInt<1>, ifc_dma_access_ok : UInt<1>}
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2020-09-21 13:37:30 +08:00
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wire fetch_addr_bf : UInt<32>
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fetch_addr_bf <= UInt<1>("h00")
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wire fetch_addr_next : UInt<32>
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fetch_addr_next <= UInt<1>("h00")
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wire fb_write_ns : UInt<4>
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fb_write_ns <= UInt<1>("h00")
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2020-09-21 22:14:00 +08:00
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wire fb_write_f : UInt<4>
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fb_write_f <= UInt<1>("h00")
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2020-09-21 13:37:30 +08:00
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wire fb_full_f_ns : UInt<1>
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fb_full_f_ns <= UInt<1>("h00")
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wire fb_right : UInt<1>
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fb_right <= UInt<1>("h00")
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wire fb_right2 : UInt<1>
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fb_right2 <= UInt<1>("h00")
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wire fb_left : UInt<1>
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fb_left <= UInt<1>("h00")
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wire wfm : UInt<1>
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wfm <= UInt<1>("h00")
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wire idle : UInt<1>
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idle <= UInt<1>("h00")
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wire sel_last_addr_bf : UInt<1>
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sel_last_addr_bf <= UInt<1>("h00")
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wire sel_btb_addr_bf : UInt<1>
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sel_btb_addr_bf <= UInt<1>("h00")
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wire sel_next_addr_bf : UInt<1>
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sel_next_addr_bf <= UInt<1>("h00")
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wire miss_f : UInt<1>
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miss_f <= UInt<1>("h00")
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2020-09-23 18:27:02 +08:00
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wire miss_a : UInt<1> @[el2_ifu_ifc_ctrl.scala 53:20]
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2020-09-21 13:37:30 +08:00
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wire flush_fb : UInt<1>
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flush_fb <= UInt<1>("h00")
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wire mb_empty_mod : UInt<1>
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mb_empty_mod <= UInt<1>("h00")
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wire goto_idle : UInt<1>
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goto_idle <= UInt<1>("h00")
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wire leave_idle : UInt<1>
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leave_idle <= UInt<1>("h00")
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wire fetch_bf_en : UInt<1>
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fetch_bf_en <= UInt<1>("h00")
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wire line_wrap : UInt<1>
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2020-09-23 18:27:02 +08:00
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line_wrap <= UInt<1>("h00")
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2020-09-21 22:14:00 +08:00
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wire state : UInt<2>
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state <= UInt<1>("h00")
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2020-09-23 18:27:02 +08:00
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io.ifc_fetch_addr_f <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 64:23]
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io.ifc_fetch_addr_bf <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 65:24]
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io.ifc_fetch_req_f <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 66:22]
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io.ifu_pmu_fetch_stall <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 67:26]
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io.ifc_fetch_uncacheable_bf <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 68:31]
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io.ifc_fetch_req_bf <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 69:23]
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io.ifc_fetch_req_bf_raw <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 70:27]
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io.ifc_iccm_access_bf <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 71:25]
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io.ifc_region_acc_fault_bf <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 72:30]
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io.ifc_dma_access_ok <= UInt<1>("h00") @[el2_ifu_ifc_ctrl.scala 73:24]
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reg dma_iccm_stall_any_f : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 75:37]
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dma_iccm_stall_any_f <= io.dma_iccm_stall_any @[el2_ifu_ifc_ctrl.scala 75:37]
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node dma_stall = or(io.ic_dma_active, dma_iccm_stall_any_f) @[el2_ifu_ifc_ctrl.scala 76:36]
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reg _T : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 77:20]
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_T <= miss_f @[el2_ifu_ifc_ctrl.scala 77:20]
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miss_a <= _T @[el2_ifu_ifc_ctrl.scala 77:10]
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node _T_1 = not(io.exu_flush_final) @[el2_ifu_ifc_ctrl.scala 79:23]
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node _T_2 = not(io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 79:46]
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node _T_3 = not(io.ic_hit_f) @[el2_ifu_ifc_ctrl.scala 79:68]
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node _T_4 = or(_T_2, _T_3) @[el2_ifu_ifc_ctrl.scala 79:66]
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node _T_5 = and(_T_1, _T_4) @[el2_ifu_ifc_ctrl.scala 79:43]
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sel_last_addr_bf <= _T_5 @[el2_ifu_ifc_ctrl.scala 79:20]
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node _T_6 = not(io.exu_flush_final) @[el2_ifu_ifc_ctrl.scala 80:23]
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node _T_7 = and(_T_6, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 80:43]
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node _T_8 = and(_T_7, io.ifu_bp_hit_taken_f) @[el2_ifu_ifc_ctrl.scala 80:64]
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node _T_9 = and(_T_8, io.ic_hit_f) @[el2_ifu_ifc_ctrl.scala 80:88]
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sel_btb_addr_bf <= _T_9 @[el2_ifu_ifc_ctrl.scala 80:20]
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node _T_10 = not(io.exu_flush_final) @[el2_ifu_ifc_ctrl.scala 81:23]
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node _T_11 = and(_T_10, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 81:43]
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node _T_12 = not(io.ifu_bp_hit_taken_f) @[el2_ifu_ifc_ctrl.scala 81:66]
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node _T_13 = and(_T_11, _T_12) @[el2_ifu_ifc_ctrl.scala 81:64]
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node _T_14 = and(_T_13, io.ic_hit_f) @[el2_ifu_ifc_ctrl.scala 81:89]
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sel_next_addr_bf <= _T_14 @[el2_ifu_ifc_ctrl.scala 81:20]
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node _T_15 = add(io.ifc_fetch_addr_f, UInt<2>("h02")) @[el2_ifu_ifc_ctrl.scala 84:42]
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node _T_16 = tail(_T_15, 1) @[el2_ifu_ifc_ctrl.scala 84:42]
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node _T_17 = bits(line_wrap, 0, 0) @[el2_ifu_ifc_ctrl.scala 85:25]
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node _T_18 = bits(io.ifc_fetch_addr_f, 0, 0) @[el2_ifu_ifc_ctrl.scala 85:53]
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node _T_19 = mux(_T_17, UInt<1>("h00"), _T_18) @[el2_ifu_ifc_ctrl.scala 85:8]
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node _T_20 = or(_T_16, _T_19) @[el2_ifu_ifc_ctrl.scala 84:48]
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fetch_addr_next <= _T_20 @[el2_ifu_ifc_ctrl.scala 84:19]
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node _T_21 = bits(io.exu_flush_final, 0, 0) @[el2_ifu_ifc_ctrl.scala 89:56]
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node _T_22 = bits(sel_last_addr_bf, 0, 0) @[el2_ifu_ifc_ctrl.scala 90:46]
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node _T_23 = bits(sel_btb_addr_bf, 0, 0) @[el2_ifu_ifc_ctrl.scala 91:45]
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node _T_24 = bits(sel_next_addr_bf, 0, 0) @[el2_ifu_ifc_ctrl.scala 92:46]
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node _T_25 = mux(_T_21, io.exu_flush_path_final, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_26 = mux(_T_22, io.ifc_fetch_addr_f, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_27 = mux(_T_23, io.ifu_bp_btb_target_f, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_28 = mux(_T_24, fetch_addr_next, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_29 = or(_T_25, _T_26) @[Mux.scala 27:72]
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node _T_30 = or(_T_29, _T_27) @[Mux.scala 27:72]
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node _T_31 = or(_T_30, _T_28) @[Mux.scala 27:72]
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wire _T_32 : UInt<32> @[Mux.scala 27:72]
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_T_32 <= _T_31 @[Mux.scala 27:72]
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io.ifc_fetch_addr_bf <= _T_32 @[el2_ifu_ifc_ctrl.scala 89:24]
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node _T_33 = or(io.exu_flush_final, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 95:88]
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reg _T_34 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
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when _T_33 : @[Reg.scala 28:19]
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_T_34 <= io.ifc_fetch_addr_bf @[Reg.scala 28:23]
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2020-09-21 22:14:00 +08:00
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skip @[Reg.scala 28:19]
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2020-09-23 18:27:02 +08:00
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io.ifc_fetch_addr_f <= _T_34 @[el2_ifu_ifc_ctrl.scala 95:23]
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node _T_35 = not(idle) @[el2_ifu_ifc_ctrl.scala 97:30]
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io.ifc_fetch_req_bf_raw <= _T_35 @[el2_ifu_ifc_ctrl.scala 97:27]
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reg _T_36 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 99:32]
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_T_36 <= io.ifc_fetch_addr_bf @[el2_ifu_ifc_ctrl.scala 99:32]
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io.ifc_fetch_req_f <= _T_36 @[el2_ifu_ifc_ctrl.scala 99:22]
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node _T_37 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctrl.scala 101:91]
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node _T_38 = not(_T_37) @[el2_ifu_ifc_ctrl.scala 101:70]
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node _T_39 = and(fb_full_f_ns, _T_38) @[el2_ifu_ifc_ctrl.scala 101:68]
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node _T_40 = not(_T_39) @[el2_ifu_ifc_ctrl.scala 101:53]
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node _T_41 = and(io.ifc_fetch_req_bf_raw, _T_40) @[el2_ifu_ifc_ctrl.scala 101:51]
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node _T_42 = not(dma_stall) @[el2_ifu_ifc_ctrl.scala 102:5]
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node _T_43 = and(_T_41, _T_42) @[el2_ifu_ifc_ctrl.scala 101:114]
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node _T_44 = not(io.ic_write_stall) @[el2_ifu_ifc_ctrl.scala 102:18]
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node _T_45 = and(_T_43, _T_44) @[el2_ifu_ifc_ctrl.scala 102:16]
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node _T_46 = not(io.dec_tlu_flush_noredir_wb) @[el2_ifu_ifc_ctrl.scala 102:39]
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node _T_47 = and(_T_45, _T_46) @[el2_ifu_ifc_ctrl.scala 102:37]
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io.ifc_fetch_req_bf <= _T_47 @[el2_ifu_ifc_ctrl.scala 101:23]
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node _T_48 = not(io.ic_hit_f) @[el2_ifu_ifc_ctrl.scala 104:34]
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node _T_49 = and(io.ifc_fetch_req_f, _T_48) @[el2_ifu_ifc_ctrl.scala 104:32]
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node _T_50 = not(io.exu_flush_final) @[el2_ifu_ifc_ctrl.scala 104:49]
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node _T_51 = and(_T_49, _T_50) @[el2_ifu_ifc_ctrl.scala 104:47]
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miss_f <= _T_51 @[el2_ifu_ifc_ctrl.scala 104:10]
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node _T_52 = and(io.exu_flush_final, io.dec_tlu_flush_noredir_wb) @[el2_ifu_ifc_ctrl.scala 106:35]
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goto_idle <= _T_52 @[el2_ifu_ifc_ctrl.scala 106:13]
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node _T_53 = or(io.ifu_ic_mb_empty, io.exu_flush_final) @[el2_ifu_ifc_ctrl.scala 108:39]
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node _T_54 = not(dma_stall) @[el2_ifu_ifc_ctrl.scala 108:63]
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node _T_55 = and(_T_53, _T_54) @[el2_ifu_ifc_ctrl.scala 108:61]
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node _T_56 = not(miss_f) @[el2_ifu_ifc_ctrl.scala 108:76]
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node _T_57 = and(_T_55, _T_56) @[el2_ifu_ifc_ctrl.scala 108:74]
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node _T_58 = not(miss_a) @[el2_ifu_ifc_ctrl.scala 108:86]
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node _T_59 = and(_T_57, _T_58) @[el2_ifu_ifc_ctrl.scala 108:84]
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mb_empty_mod <= _T_59 @[el2_ifu_ifc_ctrl.scala 108:16]
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node _T_60 = not(io.dec_tlu_flush_noredir_wb) @[el2_ifu_ifc_ctrl.scala 110:38]
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node _T_61 = and(io.exu_flush_final, _T_60) @[el2_ifu_ifc_ctrl.scala 110:36]
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node _T_62 = and(_T_61, idle) @[el2_ifu_ifc_ctrl.scala 110:67]
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leave_idle <= _T_62 @[el2_ifu_ifc_ctrl.scala 110:14]
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node _T_63 = bits(state, 1, 1) @[el2_ifu_ifc_ctrl.scala 112:29]
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node _T_64 = not(_T_63) @[el2_ifu_ifc_ctrl.scala 112:23]
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node _T_65 = bits(state, 0, 0) @[el2_ifu_ifc_ctrl.scala 112:40]
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node _T_66 = and(_T_64, _T_65) @[el2_ifu_ifc_ctrl.scala 112:33]
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node _T_67 = and(_T_66, miss_f) @[el2_ifu_ifc_ctrl.scala 112:44]
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node _T_68 = not(goto_idle) @[el2_ifu_ifc_ctrl.scala 112:55]
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node _T_69 = and(_T_67, _T_68) @[el2_ifu_ifc_ctrl.scala 112:53]
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node _T_70 = bits(state, 1, 1) @[el2_ifu_ifc_ctrl.scala 113:11]
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node _T_71 = not(mb_empty_mod) @[el2_ifu_ifc_ctrl.scala 113:17]
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node _T_72 = and(_T_70, _T_71) @[el2_ifu_ifc_ctrl.scala 113:15]
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node _T_73 = not(goto_idle) @[el2_ifu_ifc_ctrl.scala 113:33]
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node _T_74 = and(_T_72, _T_73) @[el2_ifu_ifc_ctrl.scala 113:31]
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node next_state_1 = or(_T_69, _T_74) @[el2_ifu_ifc_ctrl.scala 112:67]
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node _T_75 = not(goto_idle) @[el2_ifu_ifc_ctrl.scala 115:23]
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node _T_76 = and(_T_75, leave_idle) @[el2_ifu_ifc_ctrl.scala 115:34]
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node _T_77 = bits(state, 0, 0) @[el2_ifu_ifc_ctrl.scala 115:56]
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node _T_78 = not(goto_idle) @[el2_ifu_ifc_ctrl.scala 115:62]
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node _T_79 = and(_T_77, _T_78) @[el2_ifu_ifc_ctrl.scala 115:60]
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node next_state_0 = or(_T_76, _T_79) @[el2_ifu_ifc_ctrl.scala 115:48]
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node _T_80 = cat(next_state_0, next_state_0) @[Cat.scala 29:58]
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reg _T_81 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 117:19]
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_T_81 <= _T_80 @[el2_ifu_ifc_ctrl.scala 117:19]
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state <= _T_81 @[el2_ifu_ifc_ctrl.scala 117:9]
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flush_fb <= io.exu_flush_final @[el2_ifu_ifc_ctrl.scala 119:12]
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node _T_82 = not(io.ifu_fb_consume2) @[el2_ifu_ifc_ctrl.scala 121:38]
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node _T_83 = and(io.ifu_fb_consume1, _T_82) @[el2_ifu_ifc_ctrl.scala 121:36]
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node _T_84 = not(io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 121:61]
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node _T_85 = or(_T_84, miss_f) @[el2_ifu_ifc_ctrl.scala 121:81]
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node _T_86 = and(_T_83, _T_85) @[el2_ifu_ifc_ctrl.scala 121:58]
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node _T_87 = and(io.ifu_fb_consume2, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 122:25]
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node _T_88 = or(_T_86, _T_87) @[el2_ifu_ifc_ctrl.scala 121:92]
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fb_right <= _T_88 @[el2_ifu_ifc_ctrl.scala 121:12]
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node _T_89 = not(io.ifc_fetch_req_f) @[el2_ifu_ifc_ctrl.scala 124:39]
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node _T_90 = or(_T_89, miss_f) @[el2_ifu_ifc_ctrl.scala 124:59]
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node _T_91 = and(io.ifu_fb_consume2, _T_90) @[el2_ifu_ifc_ctrl.scala 124:36]
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fb_right2 <= _T_91 @[el2_ifu_ifc_ctrl.scala 124:13]
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node _T_92 = or(io.ifu_fb_consume1, io.ifu_fb_consume2) @[el2_ifu_ifc_ctrl.scala 125:56]
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node _T_93 = not(_T_92) @[el2_ifu_ifc_ctrl.scala 125:35]
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node _T_94 = and(io.ifc_fetch_req_f, _T_93) @[el2_ifu_ifc_ctrl.scala 125:33]
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node _T_95 = not(miss_f) @[el2_ifu_ifc_ctrl.scala 125:80]
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node _T_96 = and(_T_94, _T_95) @[el2_ifu_ifc_ctrl.scala 125:78]
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fb_left <= _T_96 @[el2_ifu_ifc_ctrl.scala 125:11]
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node _T_97 = not(flush_fb) @[el2_ifu_ifc_ctrl.scala 128:6]
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node _T_98 = and(_T_97, fb_right) @[el2_ifu_ifc_ctrl.scala 128:16]
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node _T_99 = bits(_T_98, 0, 0) @[el2_ifu_ifc_ctrl.scala 128:28]
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node _T_100 = bits(fb_write_f, 3, 1) @[el2_ifu_ifc_ctrl.scala 128:62]
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node _T_101 = cat(UInt<1>("h00"), _T_100) @[Cat.scala 29:58]
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node _T_102 = not(flush_fb) @[el2_ifu_ifc_ctrl.scala 129:6]
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node _T_103 = and(_T_102, fb_right2) @[el2_ifu_ifc_ctrl.scala 129:16]
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node _T_104 = bits(_T_103, 0, 0) @[el2_ifu_ifc_ctrl.scala 129:29]
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node _T_105 = bits(fb_write_f, 3, 2) @[el2_ifu_ifc_ctrl.scala 129:63]
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node _T_106 = cat(UInt<2>("h00"), _T_105) @[Cat.scala 29:58]
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node _T_107 = not(flush_fb) @[el2_ifu_ifc_ctrl.scala 130:6]
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node _T_108 = and(_T_107, fb_left) @[el2_ifu_ifc_ctrl.scala 130:16]
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node _T_109 = bits(_T_108, 0, 0) @[el2_ifu_ifc_ctrl.scala 130:27]
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node _T_110 = bits(fb_write_f, 2, 0) @[el2_ifu_ifc_ctrl.scala 130:51]
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node _T_111 = cat(_T_110, UInt<1>("h00")) @[Cat.scala 29:58]
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node _T_112 = not(flush_fb) @[el2_ifu_ifc_ctrl.scala 131:6]
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node _T_113 = not(fb_right) @[el2_ifu_ifc_ctrl.scala 131:18]
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node _T_114 = and(_T_112, _T_113) @[el2_ifu_ifc_ctrl.scala 131:16]
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node _T_115 = not(fb_right2) @[el2_ifu_ifc_ctrl.scala 131:30]
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node _T_116 = and(_T_114, _T_115) @[el2_ifu_ifc_ctrl.scala 131:28]
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node _T_117 = not(fb_left) @[el2_ifu_ifc_ctrl.scala 131:43]
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node _T_118 = and(_T_116, _T_117) @[el2_ifu_ifc_ctrl.scala 131:41]
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node _T_119 = bits(_T_118, 0, 0) @[el2_ifu_ifc_ctrl.scala 131:53]
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node _T_120 = bits(fb_write_f, 3, 0) @[el2_ifu_ifc_ctrl.scala 131:73]
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node _T_121 = mux(io.exu_flush_final, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_122 = mux(_T_99, _T_101, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_123 = mux(_T_104, _T_106, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_124 = mux(_T_109, _T_111, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_125 = mux(_T_119, _T_120, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_126 = or(_T_121, _T_122) @[Mux.scala 27:72]
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node _T_127 = or(_T_126, _T_123) @[Mux.scala 27:72]
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node _T_128 = or(_T_127, _T_124) @[Mux.scala 27:72]
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node _T_129 = or(_T_128, _T_125) @[Mux.scala 27:72]
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wire _T_130 : UInt<4> @[Mux.scala 27:72]
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_T_130 <= _T_129 @[Mux.scala 27:72]
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fb_write_ns <= _T_130 @[el2_ifu_ifc_ctrl.scala 127:15]
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reg _T_131 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 134:26]
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_T_131 <= fb_write_ns @[el2_ifu_ifc_ctrl.scala 134:26]
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fb_full_f_ns <= _T_131 @[el2_ifu_ifc_ctrl.scala 134:16]
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node _T_132 = eq(state, UInt<2>("h00")) @[el2_ifu_ifc_ctrl.scala 136:17]
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idle <= _T_132 @[el2_ifu_ifc_ctrl.scala 136:8]
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node _T_133 = eq(state, UInt<2>("h03")) @[el2_ifu_ifc_ctrl.scala 137:16]
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wfm <= _T_133 @[el2_ifu_ifc_ctrl.scala 137:7]
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node _T_134 = bits(fb_write_ns, 3, 3) @[el2_ifu_ifc_ctrl.scala 139:30]
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fb_full_f_ns <= _T_134 @[el2_ifu_ifc_ctrl.scala 139:16]
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reg fb_full_f : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctrl.scala 140:26]
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fb_full_f <= fb_full_f_ns @[el2_ifu_ifc_ctrl.scala 140:26]
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node _T_135 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctrl.scala 143:26]
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node _T_136 = or(_T_135, io.exu_flush_final) @[el2_ifu_ifc_ctrl.scala 143:47]
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node _T_137 = not(_T_136) @[el2_ifu_ifc_ctrl.scala 143:5]
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node _T_138 = and(fb_full_f, _T_137) @[el2_ifu_ifc_ctrl.scala 142:75]
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node _T_139 = or(_T_138, dma_stall) @[el2_ifu_ifc_ctrl.scala 143:70]
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node _T_140 = and(io.ifc_fetch_req_bf_raw, _T_139) @[el2_ifu_ifc_ctrl.scala 142:60]
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node _T_141 = or(wfm, _T_140) @[el2_ifu_ifc_ctrl.scala 142:33]
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io.ifu_pmu_fetch_stall <= _T_141 @[el2_ifu_ifc_ctrl.scala 142:26]
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node _T_142 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
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node _T_143 = bits(_T_142, 31, 28) @[el2_lib.scala 203:25]
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node iccm_acc_in_region_bf = eq(_T_143, UInt<4>("h0e")) @[el2_lib.scala 203:47]
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node _T_144 = bits(_T_142, 31, 16) @[el2_lib.scala 206:14]
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node iccm_acc_in_range_bf = eq(_T_144, UInt<16>("h0ee00")) @[el2_lib.scala 206:29]
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io.ifc_iccm_access_bf <= iccm_acc_in_range_bf @[el2_ifu_ifc_ctrl.scala 149:25]
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node _T_145 = bits(io.ifc_fetch_addr_bf, 30, 27) @[el2_ifu_ifc_ctrl.scala 150:78]
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node _T_146 = cat(_T_145, UInt<1>("h00")) @[Cat.scala 29:58]
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node _T_147 = dshr(io.dec_tlu_mrac_ff, _T_146) @[el2_ifu_ifc_ctrl.scala 150:53]
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node _T_148 = bits(_T_147, 0, 0) @[el2_ifu_ifc_ctrl.scala 150:53]
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node _T_149 = not(_T_148) @[el2_ifu_ifc_ctrl.scala 150:34]
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io.ifc_fetch_uncacheable_bf <= _T_149 @[el2_ifu_ifc_ctrl.scala 150:31]
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2020-09-21 13:37:30 +08:00
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