68 lines
2.8 KiB
Coq
68 lines
2.8 KiB
Coq
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module dmi_wrapper_module(
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input clock,
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input reset,
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input io_trst_n,
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input io_tck,
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input io_tms,
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input io_tdi,
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output io_tdo,
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output io_tdoEnable,
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input io_core_rst_n,
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input io_core_clk,
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input [31:0] io_jtag_id,
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input [31:0] io_rd_data,
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output [31:0] io_reg_wr_data,
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output [6:0] io_reg_wr_addr,
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output io_reg_en,
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output io_reg_wr_en,
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output io_dmi_hard_reset
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);
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wire dwrap_trst_n; // @[dmi_wrapper.scala 45:21]
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wire dwrap_tck; // @[dmi_wrapper.scala 45:21]
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wire dwrap_tms; // @[dmi_wrapper.scala 45:21]
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wire dwrap_tdi; // @[dmi_wrapper.scala 45:21]
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wire dwrap_tdo; // @[dmi_wrapper.scala 45:21]
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wire dwrap_tdoEnable; // @[dmi_wrapper.scala 45:21]
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wire dwrap_core_rst_n; // @[dmi_wrapper.scala 45:21]
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wire dwrap_core_clk; // @[dmi_wrapper.scala 45:21]
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wire [30:0] dwrap_jtag_id; // @[dmi_wrapper.scala 45:21]
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wire [31:0] dwrap_rd_data; // @[dmi_wrapper.scala 45:21]
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wire [31:0] dwrap_reg_wr_data; // @[dmi_wrapper.scala 45:21]
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wire [6:0] dwrap_reg_wr_addr; // @[dmi_wrapper.scala 45:21]
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wire dwrap_reg_en; // @[dmi_wrapper.scala 45:21]
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wire dwrap_reg_wr_en; // @[dmi_wrapper.scala 45:21]
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wire dwrap_dmi_hard_reset; // @[dmi_wrapper.scala 45:21]
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dmi_wrapper dwrap ( // @[dmi_wrapper.scala 45:21]
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.trst_n(dwrap_trst_n),
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.tck(dwrap_tck),
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.tms(dwrap_tms),
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.tdi(dwrap_tdi),
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.tdo(dwrap_tdo),
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.tdoEnable(dwrap_tdoEnable),
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.core_rst_n(dwrap_core_rst_n),
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.core_clk(dwrap_core_clk),
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.jtag_id(dwrap_jtag_id),
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.rd_data(dwrap_rd_data),
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.reg_wr_data(dwrap_reg_wr_data),
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.reg_wr_addr(dwrap_reg_wr_addr),
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.reg_en(dwrap_reg_en),
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.reg_wr_en(dwrap_reg_wr_en),
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.dmi_hard_reset(dwrap_dmi_hard_reset)
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);
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assign io_tdo = dwrap_tdo; // @[dmi_wrapper.scala 46:12]
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assign io_tdoEnable = dwrap_tdoEnable; // @[dmi_wrapper.scala 46:12]
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assign io_reg_wr_data = dwrap_reg_wr_data; // @[dmi_wrapper.scala 46:12]
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assign io_reg_wr_addr = dwrap_reg_wr_addr; // @[dmi_wrapper.scala 46:12]
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assign io_reg_en = dwrap_reg_en; // @[dmi_wrapper.scala 46:12]
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assign io_reg_wr_en = dwrap_reg_wr_en; // @[dmi_wrapper.scala 46:12]
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assign io_dmi_hard_reset = dwrap_dmi_hard_reset; // @[dmi_wrapper.scala 46:12]
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assign dwrap_trst_n = io_trst_n; // @[dmi_wrapper.scala 46:12]
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assign dwrap_tck = io_tck; // @[dmi_wrapper.scala 46:12]
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assign dwrap_tms = io_tms; // @[dmi_wrapper.scala 46:12]
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assign dwrap_tdi = io_tdi; // @[dmi_wrapper.scala 46:12]
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assign dwrap_core_rst_n = io_core_rst_n; // @[dmi_wrapper.scala 46:12]
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assign dwrap_core_clk = io_core_clk; // @[dmi_wrapper.scala 46:12]
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assign dwrap_jtag_id = io_jtag_id[30:0]; // @[dmi_wrapper.scala 46:12]
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assign dwrap_rd_data = io_rd_data; // @[dmi_wrapper.scala 46:12]
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endmodule
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