2020-09-07 16:27:29 +08:00
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;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
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circuit el2_ifu_bp_ctl :
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module el2_ifu_bp_ctl :
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input clock : Clock
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input reset : UInt<1>
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2020-09-24 13:58:56 +08:00
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output io : {flip clk : UInt<1>, flip active_clk : UInt<1>, flip rst_l : UInt<1>, flip ic_hit_f : UInt<1>, flip ifc_fetch_addr_f : UInt<32>, flip ifc_fetch_req_f : UInt<1>, flip dec_tlu_br0_r_pkt : {valid : UInt<1>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, way : UInt<1>, middle : UInt<1>}, flip exu_i0_br_fghr_r : UInt<8>, flip exu_i0_br_index_r : UInt<7>, flip dec_tlu_flush_lower_wb : UInt<1>, flip dec_tlu_flush_leak_one_wb : UInt<1>, flip dec_tlu_bpred_disable : UInt<1>, flip exu_mp_pkt : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, valid : UInt<1>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<32>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}, flip exu_mp_eghr : UInt<8>, flip exu_mp_fghr : UInt<8>, flip exu_mp_index : UInt<7>, flip exu_mp_btag : UInt<5>, flip exu_flush_final : UInt<1>, ifu_bp_hit_taken_f : UInt<1>, ifu_bp_btb_target_f : UInt<31>, ifu_bp_inst_mask_f : UInt<1>, ifu_bp_fghr_f : UInt<8>, ifu_bp_way_f : UInt<2>, ifu_bp_ret_f : UInt<2>, ifu_bp_hist1_f : UInt<2>, ifu_bp_hist0_f : UInt<2>, ifu_bp_pc4_f : UInt<2>, ifu_bp_valid_f : UInt<2>, ifu_bp_poffset_f : UInt<12>}
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2020-09-07 16:27:29 +08:00
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2020-09-28 13:28:50 +08:00
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io.ifu_bp_hit_taken_f <= UInt<1>("h00") @[el2_ifu_bp_ctl.scala 44:25]
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io.ifu_bp_btb_target_f <= UInt<1>("h00") @[el2_ifu_bp_ctl.scala 45:26]
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io.ifu_bp_inst_mask_f <= UInt<1>("h00") @[el2_ifu_bp_ctl.scala 46:25]
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io.ifu_bp_fghr_f <= UInt<1>("h00") @[el2_ifu_bp_ctl.scala 47:20]
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io.ifu_bp_way_f <= UInt<1>("h00") @[el2_ifu_bp_ctl.scala 48:19]
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io.ifu_bp_ret_f <= UInt<1>("h00") @[el2_ifu_bp_ctl.scala 49:19]
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io.ifu_bp_hist1_f <= UInt<1>("h00") @[el2_ifu_bp_ctl.scala 50:21]
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io.ifu_bp_hist0_f <= UInt<1>("h00") @[el2_ifu_bp_ctl.scala 51:21]
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io.ifu_bp_pc4_f <= UInt<1>("h00") @[el2_ifu_bp_ctl.scala 52:19]
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io.ifu_bp_valid_f <= UInt<1>("h00") @[el2_ifu_bp_ctl.scala 53:21]
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io.ifu_bp_poffset_f <= UInt<1>("h00") @[el2_ifu_bp_ctl.scala 54:23]
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2020-09-24 13:58:56 +08:00
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wire leak_one_f : UInt<1>
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leak_one_f <= UInt<1>("h00")
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2020-09-28 13:28:50 +08:00
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node _T = not(leak_one_f) @[el2_ifu_bp_ctl.scala 69:43]
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node exu_mp_valid = and(io.exu_mp_pkt.misp, _T) @[el2_ifu_bp_ctl.scala 69:41]
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2020-09-24 13:58:56 +08:00
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wire bht_dir_f : UInt<2>
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bht_dir_f <= UInt<1>("h00")
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wire dec_tlu_error_wb : UInt<1>
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dec_tlu_error_wb <= UInt<1>("h00")
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wire btb_error_addr_wb : UInt<7>
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btb_error_addr_wb <= UInt<1>("h00")
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wire btb_bank0_rd_data_way0_f : UInt<22>
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btb_bank0_rd_data_way0_f <= UInt<1>("h00")
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wire btb_bank0_rd_data_way1_f : UInt<22>
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btb_bank0_rd_data_way1_f <= UInt<1>("h00")
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wire btb_bank0_rd_data_way0_p1_f : UInt<22>
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btb_bank0_rd_data_way0_p1_f <= UInt<1>("h00")
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wire btb_bank0_rd_data_way1_p1_f : UInt<22>
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btb_bank0_rd_data_way1_p1_f <= UInt<1>("h00")
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2020-09-25 15:15:14 +08:00
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wire eoc_mask : UInt<1>
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eoc_mask <= UInt<1>("h00")
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wire btb_lru_b0_f : UInt<256>
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btb_lru_b0_f <= UInt<1>("h00")
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2020-09-24 13:58:56 +08:00
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wire dec_tlu_way_wb : UInt<1>
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dec_tlu_way_wb <= UInt<1>("h00")
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node _T_1 = bits(io.ifc_fetch_addr_f, 9, 2) @[el2_lib.scala 182:12]
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node _T_2 = bits(io.ifc_fetch_addr_f, 17, 10) @[el2_lib.scala 182:46]
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node _T_3 = xor(_T_1, _T_2) @[el2_lib.scala 182:42]
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node _T_4 = bits(io.ifc_fetch_addr_f, 25, 18) @[el2_lib.scala 182:80]
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node btb_rd_addr_f = xor(_T_3, _T_4) @[el2_lib.scala 182:76]
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2020-09-28 13:28:50 +08:00
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node _T_5 = add(io.ifc_fetch_addr_f, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 108:45]
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node fetch_addr_p1_f = tail(_T_5, 1) @[el2_ifu_bp_ctl.scala 108:45]
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2020-09-24 13:58:56 +08:00
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node _T_6 = bits(fetch_addr_p1_f, 9, 2) @[el2_lib.scala 182:12]
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node _T_7 = bits(fetch_addr_p1_f, 17, 10) @[el2_lib.scala 182:46]
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node _T_8 = xor(_T_6, _T_7) @[el2_lib.scala 182:42]
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node _T_9 = bits(fetch_addr_p1_f, 25, 18) @[el2_lib.scala 182:80]
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node btb_rd_addr_p1_f = xor(_T_8, _T_9) @[el2_lib.scala 182:76]
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2020-09-28 13:28:50 +08:00
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node _T_10 = bits(bht_dir_f, 0, 0) @[el2_ifu_bp_ctl.scala 113:33]
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node _T_11 = not(_T_10) @[el2_ifu_bp_ctl.scala 113:23]
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node _T_12 = bits(bht_dir_f, 0, 0) @[el2_ifu_bp_ctl.scala 113:46]
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2020-09-24 13:58:56 +08:00
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node btb_sel_f = cat(_T_11, _T_12) @[Cat.scala 29:58]
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2020-09-28 13:28:50 +08:00
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node _T_13 = bits(io.ifc_fetch_addr_f, 1, 1) @[el2_ifu_bp_ctl.scala 116:46]
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node _T_14 = bits(io.ifc_fetch_addr_f, 1, 1) @[el2_ifu_bp_ctl.scala 116:70]
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node _T_15 = not(_T_14) @[el2_ifu_bp_ctl.scala 116:50]
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2020-09-24 13:58:56 +08:00
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node fetch_start_f = cat(_T_13, _T_15) @[Cat.scala 29:58]
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2020-09-28 13:28:50 +08:00
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node _T_16 = eq(btb_error_addr_wb, btb_rd_addr_f) @[el2_ifu_bp_ctl.scala 119:72]
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node branch_error_collision_f = and(dec_tlu_error_wb, _T_16) @[el2_ifu_bp_ctl.scala 119:51]
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node _T_17 = eq(btb_error_addr_wb, btb_rd_addr_p1_f) @[el2_ifu_bp_ctl.scala 120:75]
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node branch_error_collision_p1_f = and(dec_tlu_error_wb, _T_17) @[el2_ifu_bp_ctl.scala 120:54]
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node branch_error_bank_conflict_f = and(branch_error_collision_f, dec_tlu_error_wb) @[el2_ifu_bp_ctl.scala 123:63]
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node branch_error_bank_conflict_p1_f = and(branch_error_collision_p1_f, dec_tlu_error_wb) @[el2_ifu_bp_ctl.scala 124:69]
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node _T_18 = bits(io.ifc_fetch_addr_f, 14, 10) @[el2_lib.scala 175:32]
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node _T_19 = bits(io.ifc_fetch_addr_f, 19, 15) @[el2_lib.scala 175:32]
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node _T_20 = bits(io.ifc_fetch_addr_f, 24, 20) @[el2_lib.scala 175:32]
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wire _T_21 : UInt<5>[3] @[el2_lib.scala 175:24]
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_T_21[0] <= _T_18 @[el2_lib.scala 175:24]
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_T_21[1] <= _T_19 @[el2_lib.scala 175:24]
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_T_21[2] <= _T_20 @[el2_lib.scala 175:24]
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node _T_22 = xor(_T_21[0], _T_21[1]) @[el2_lib.scala 175:111]
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node fetch_rd_tag_f = xor(_T_22, _T_21[2]) @[el2_lib.scala 175:111]
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node _T_23 = bits(fetch_addr_p1_f, 14, 10) @[el2_lib.scala 175:32]
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node _T_24 = bits(fetch_addr_p1_f, 19, 15) @[el2_lib.scala 175:32]
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node _T_25 = bits(fetch_addr_p1_f, 24, 20) @[el2_lib.scala 175:32]
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wire _T_26 : UInt<5>[3] @[el2_lib.scala 175:24]
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_T_26[0] <= _T_23 @[el2_lib.scala 175:24]
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_T_26[1] <= _T_24 @[el2_lib.scala 175:24]
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_T_26[2] <= _T_25 @[el2_lib.scala 175:24]
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node _T_27 = xor(_T_26[0], _T_26[1]) @[el2_lib.scala 175:111]
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node fetch_rd_tag_p1_f = xor(_T_27, _T_26[2]) @[el2_lib.scala 175:111]
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node _T_28 = eq(io.exu_mp_btag, fetch_rd_tag_f) @[el2_ifu_bp_ctl.scala 129:46]
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node _T_29 = and(_T_28, exu_mp_valid) @[el2_ifu_bp_ctl.scala 129:66]
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node _T_30 = and(_T_29, io.ifc_fetch_req_f) @[el2_ifu_bp_ctl.scala 129:81]
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node _T_31 = eq(io.exu_mp_index, btb_rd_addr_f) @[el2_ifu_bp_ctl.scala 129:117]
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node fetch_mp_collision_f = and(_T_30, _T_31) @[el2_ifu_bp_ctl.scala 129:102]
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node _T_32 = eq(io.exu_mp_btag, fetch_rd_tag_p1_f) @[el2_ifu_bp_ctl.scala 130:49]
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node _T_33 = and(_T_32, exu_mp_valid) @[el2_ifu_bp_ctl.scala 130:72]
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node _T_34 = and(_T_33, io.ifc_fetch_req_f) @[el2_ifu_bp_ctl.scala 130:87]
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node _T_35 = eq(io.exu_mp_index, btb_rd_addr_p1_f) @[el2_ifu_bp_ctl.scala 130:123]
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node fetch_mp_collision_p1_f = and(_T_34, _T_35) @[el2_ifu_bp_ctl.scala 130:108]
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reg leak_one_f_d1 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_bp_ctl.scala 132:30]
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leak_one_f_d1 <= leak_one_f @[el2_ifu_bp_ctl.scala 132:30]
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reg dec_tlu_way_wb_f : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_bp_ctl.scala 133:33]
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dec_tlu_way_wb_f <= dec_tlu_way_wb @[el2_ifu_bp_ctl.scala 133:33]
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reg exu_mp_way_f : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_bp_ctl.scala 134:29]
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exu_mp_way_f <= io.exu_mp_pkt.way @[el2_ifu_bp_ctl.scala 134:29]
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reg exu_flush_final_d1 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_bp_ctl.scala 135:35]
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exu_flush_final_d1 <= io.exu_flush_final @[el2_ifu_bp_ctl.scala 135:35]
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node _T_36 = and(io.dec_tlu_flush_leak_one_wb, io.dec_tlu_flush_lower_wb) @[el2_ifu_bp_ctl.scala 137:47]
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node _T_37 = and(leak_one_f_d1, io.dec_tlu_flush_lower_wb) @[el2_ifu_bp_ctl.scala 137:93]
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node _T_38 = or(_T_36, _T_37) @[el2_ifu_bp_ctl.scala 137:76]
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leak_one_f <= _T_38 @[el2_ifu_bp_ctl.scala 137:14]
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node _T_39 = bits(btb_bank0_rd_data_way0_f, 0, 0) @[el2_ifu_bp_ctl.scala 140:50]
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node _T_40 = bits(btb_bank0_rd_data_way0_f, 21, 17) @[el2_ifu_bp_ctl.scala 140:82]
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node _T_41 = eq(_T_40, fetch_rd_tag_f) @[el2_ifu_bp_ctl.scala 140:97]
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node _T_42 = and(_T_39, _T_41) @[el2_ifu_bp_ctl.scala 140:55]
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node _T_43 = and(dec_tlu_way_wb_f, branch_error_bank_conflict_f) @[el2_ifu_bp_ctl.scala 141:22]
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node _T_44 = not(_T_43) @[el2_ifu_bp_ctl.scala 141:3]
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node _T_45 = and(_T_42, _T_44) @[el2_ifu_bp_ctl.scala 140:117]
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node _T_46 = and(_T_45, io.ifc_fetch_req_f) @[el2_ifu_bp_ctl.scala 141:54]
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node _T_47 = not(leak_one_f) @[el2_ifu_bp_ctl.scala 141:77]
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node tag_match_way0_f = and(_T_46, _T_47) @[el2_ifu_bp_ctl.scala 141:75]
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node _T_48 = bits(btb_bank0_rd_data_way1_f, 0, 0) @[el2_ifu_bp_ctl.scala 143:50]
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node _T_49 = bits(btb_bank0_rd_data_way1_f, 21, 17) @[el2_ifu_bp_ctl.scala 143:82]
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node _T_50 = eq(_T_49, fetch_rd_tag_f) @[el2_ifu_bp_ctl.scala 143:97]
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node _T_51 = and(_T_48, _T_50) @[el2_ifu_bp_ctl.scala 143:55]
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node _T_52 = and(dec_tlu_way_wb_f, branch_error_bank_conflict_f) @[el2_ifu_bp_ctl.scala 144:22]
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node _T_53 = not(_T_52) @[el2_ifu_bp_ctl.scala 144:3]
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node _T_54 = and(_T_51, _T_53) @[el2_ifu_bp_ctl.scala 143:117]
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node _T_55 = and(_T_54, io.ifc_fetch_req_f) @[el2_ifu_bp_ctl.scala 144:54]
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node _T_56 = not(leak_one_f) @[el2_ifu_bp_ctl.scala 144:77]
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node tag_match_way1_f = and(_T_55, _T_56) @[el2_ifu_bp_ctl.scala 144:75]
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node _T_57 = bits(btb_bank0_rd_data_way0_p1_f, 0, 0) @[el2_ifu_bp_ctl.scala 146:56]
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node _T_58 = bits(btb_bank0_rd_data_way0_p1_f, 21, 17) @[el2_ifu_bp_ctl.scala 146:91]
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node _T_59 = eq(_T_58, fetch_rd_tag_p1_f) @[el2_ifu_bp_ctl.scala 146:106]
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node _T_60 = and(_T_57, _T_59) @[el2_ifu_bp_ctl.scala 146:61]
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node _T_61 = and(dec_tlu_way_wb_f, branch_error_bank_conflict_f) @[el2_ifu_bp_ctl.scala 147:24]
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node _T_62 = not(_T_61) @[el2_ifu_bp_ctl.scala 147:5]
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node _T_63 = and(_T_60, _T_62) @[el2_ifu_bp_ctl.scala 146:129]
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node _T_64 = and(_T_63, io.ifc_fetch_req_f) @[el2_ifu_bp_ctl.scala 147:56]
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node _T_65 = not(leak_one_f) @[el2_ifu_bp_ctl.scala 147:79]
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node tag_match_way0_p1_f = and(_T_64, _T_65) @[el2_ifu_bp_ctl.scala 147:77]
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node _T_66 = bits(btb_bank0_rd_data_way1_p1_f, 0, 0) @[el2_ifu_bp_ctl.scala 149:56]
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node _T_67 = bits(btb_bank0_rd_data_way1_p1_f, 21, 17) @[el2_ifu_bp_ctl.scala 149:91]
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node _T_68 = eq(_T_67, fetch_rd_tag_p1_f) @[el2_ifu_bp_ctl.scala 149:106]
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node _T_69 = and(_T_66, _T_68) @[el2_ifu_bp_ctl.scala 149:61]
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node _T_70 = and(dec_tlu_way_wb_f, branch_error_bank_conflict_f) @[el2_ifu_bp_ctl.scala 150:24]
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node _T_71 = not(_T_70) @[el2_ifu_bp_ctl.scala 150:5]
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node _T_72 = and(_T_69, _T_71) @[el2_ifu_bp_ctl.scala 149:129]
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node _T_73 = and(_T_72, io.ifc_fetch_req_f) @[el2_ifu_bp_ctl.scala 150:56]
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node _T_74 = not(leak_one_f) @[el2_ifu_bp_ctl.scala 150:79]
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node tag_match_way1_p1_f = and(_T_73, _T_74) @[el2_ifu_bp_ctl.scala 150:77]
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node _T_75 = bits(btb_bank0_rd_data_way0_f, 3, 3) @[el2_ifu_bp_ctl.scala 153:84]
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node _T_76 = bits(btb_bank0_rd_data_way0_f, 4, 4) @[el2_ifu_bp_ctl.scala 153:117]
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node _T_77 = xor(_T_75, _T_76) @[el2_ifu_bp_ctl.scala 153:91]
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node _T_78 = and(tag_match_way0_f, _T_77) @[el2_ifu_bp_ctl.scala 153:56]
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node _T_79 = bits(btb_bank0_rd_data_way0_f, 3, 3) @[el2_ifu_bp_ctl.scala 154:50]
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node _T_80 = bits(btb_bank0_rd_data_way0_f, 4, 4) @[el2_ifu_bp_ctl.scala 154:83]
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node _T_81 = xor(_T_79, _T_80) @[el2_ifu_bp_ctl.scala 154:57]
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node _T_82 = not(_T_81) @[el2_ifu_bp_ctl.scala 154:24]
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node _T_83 = and(tag_match_way0_f, _T_82) @[el2_ifu_bp_ctl.scala 154:22]
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node tag_match_way0_expanded_f = cat(_T_78, _T_83) @[Cat.scala 29:58]
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node _T_84 = bits(btb_bank0_rd_data_way1_f, 3, 3) @[el2_ifu_bp_ctl.scala 156:84]
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node _T_85 = bits(btb_bank0_rd_data_way1_f, 4, 4) @[el2_ifu_bp_ctl.scala 156:117]
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node _T_86 = xor(_T_84, _T_85) @[el2_ifu_bp_ctl.scala 156:91]
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node _T_87 = and(tag_match_way1_f, _T_86) @[el2_ifu_bp_ctl.scala 156:56]
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node _T_88 = bits(btb_bank0_rd_data_way1_f, 3, 3) @[el2_ifu_bp_ctl.scala 157:50]
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node _T_89 = bits(btb_bank0_rd_data_way1_f, 4, 4) @[el2_ifu_bp_ctl.scala 157:83]
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node _T_90 = xor(_T_88, _T_89) @[el2_ifu_bp_ctl.scala 157:57]
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node _T_91 = not(_T_90) @[el2_ifu_bp_ctl.scala 157:24]
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node _T_92 = and(tag_match_way1_f, _T_91) @[el2_ifu_bp_ctl.scala 157:22]
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node tag_match_way1_expanded_f = cat(_T_87, _T_92) @[Cat.scala 29:58]
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node _T_93 = bits(btb_bank0_rd_data_way0_p1_f, 3, 3) @[el2_ifu_bp_ctl.scala 160:93]
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node _T_94 = bits(btb_bank0_rd_data_way0_p1_f, 4, 4) @[el2_ifu_bp_ctl.scala 160:129]
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node _T_95 = xor(_T_93, _T_94) @[el2_ifu_bp_ctl.scala 160:100]
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node _T_96 = and(tag_match_way0_p1_f, _T_95) @[el2_ifu_bp_ctl.scala 160:62]
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node _T_97 = bits(btb_bank0_rd_data_way0_p1_f, 3, 3) @[el2_ifu_bp_ctl.scala 161:56]
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node _T_98 = bits(btb_bank0_rd_data_way0_p1_f, 4, 4) @[el2_ifu_bp_ctl.scala 161:92]
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node _T_99 = xor(_T_97, _T_98) @[el2_ifu_bp_ctl.scala 161:63]
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node _T_100 = not(_T_99) @[el2_ifu_bp_ctl.scala 161:27]
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node _T_101 = and(tag_match_way0_p1_f, _T_100) @[el2_ifu_bp_ctl.scala 161:25]
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node tag_match_way0_expanded_p1_f = cat(_T_96, _T_101) @[Cat.scala 29:58]
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node _T_102 = bits(btb_bank0_rd_data_way1_p1_f, 3, 3) @[el2_ifu_bp_ctl.scala 163:93]
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node _T_103 = bits(btb_bank0_rd_data_way1_p1_f, 4, 4) @[el2_ifu_bp_ctl.scala 163:129]
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node _T_104 = xor(_T_102, _T_103) @[el2_ifu_bp_ctl.scala 163:100]
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node _T_105 = and(tag_match_way1_p1_f, _T_104) @[el2_ifu_bp_ctl.scala 163:62]
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node _T_106 = bits(btb_bank0_rd_data_way1_p1_f, 3, 3) @[el2_ifu_bp_ctl.scala 164:56]
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node _T_107 = bits(btb_bank0_rd_data_way1_p1_f, 4, 4) @[el2_ifu_bp_ctl.scala 164:92]
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node _T_108 = xor(_T_106, _T_107) @[el2_ifu_bp_ctl.scala 164:63]
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node _T_109 = not(_T_108) @[el2_ifu_bp_ctl.scala 164:27]
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node _T_110 = and(tag_match_way1_p1_f, _T_109) @[el2_ifu_bp_ctl.scala 164:25]
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node tag_match_way1_expanded_p1_f = cat(_T_105, _T_110) @[Cat.scala 29:58]
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node wayhit_f = or(tag_match_way0_expanded_f, tag_match_way1_expanded_f) @[el2_ifu_bp_ctl.scala 166:44]
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node wayhit_p1_f = or(tag_match_way0_expanded_p1_f, tag_match_way1_expanded_p1_f) @[el2_ifu_bp_ctl.scala 168:50]
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node _T_111 = bits(tag_match_way0_expanded_f, 0, 0) @[el2_ifu_bp_ctl.scala 171:65]
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node _T_112 = bits(_T_111, 0, 0) @[el2_ifu_bp_ctl.scala 171:69]
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node _T_113 = bits(tag_match_way1_expanded_f, 0, 0) @[el2_ifu_bp_ctl.scala 172:30]
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node _T_114 = bits(_T_113, 0, 0) @[el2_ifu_bp_ctl.scala 172:34]
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node _T_115 = mux(_T_112, btb_bank0_rd_data_way0_f, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_116 = mux(_T_114, btb_bank0_rd_data_way1_f, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_117 = or(_T_115, _T_116) @[Mux.scala 27:72]
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2020-09-25 15:15:14 +08:00
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wire btb_bank0e_rd_data_f : UInt<22> @[Mux.scala 27:72]
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2020-09-28 13:28:50 +08:00
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btb_bank0e_rd_data_f <= _T_117 @[Mux.scala 27:72]
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node _T_118 = bits(tag_match_way0_expanded_f, 1, 1) @[el2_ifu_bp_ctl.scala 174:65]
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node _T_119 = bits(_T_118, 0, 0) @[el2_ifu_bp_ctl.scala 174:69]
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node _T_120 = bits(tag_match_way1_expanded_f, 1, 1) @[el2_ifu_bp_ctl.scala 175:30]
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node _T_121 = bits(_T_120, 0, 0) @[el2_ifu_bp_ctl.scala 175:34]
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node _T_122 = mux(_T_119, btb_bank0_rd_data_way0_f, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_123 = mux(_T_121, btb_bank0_rd_data_way1_f, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_124 = or(_T_122, _T_123) @[Mux.scala 27:72]
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2020-09-25 15:15:14 +08:00
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wire btb_bank0o_rd_data_f : UInt<22> @[Mux.scala 27:72]
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2020-09-28 13:28:50 +08:00
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btb_bank0o_rd_data_f <= _T_124 @[Mux.scala 27:72]
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node _T_125 = bits(tag_match_way0_expanded_p1_f, 0, 0) @[el2_ifu_bp_ctl.scala 177:71]
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node _T_126 = bits(_T_125, 0, 0) @[el2_ifu_bp_ctl.scala 177:75]
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node _T_127 = bits(tag_match_way1_expanded_p1_f, 1, 1) @[el2_ifu_bp_ctl.scala 178:33]
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node _T_128 = bits(_T_127, 0, 0) @[el2_ifu_bp_ctl.scala 178:37]
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node _T_129 = mux(_T_126, btb_bank0_rd_data_way0_p1_f, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_130 = mux(_T_128, btb_bank0_rd_data_way1_p1_f, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_131 = or(_T_129, _T_130) @[Mux.scala 27:72]
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2020-09-25 15:15:14 +08:00
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wire btb_bank0e_rd_data_p1_f : UInt<22> @[Mux.scala 27:72]
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2020-09-28 13:28:50 +08:00
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btb_bank0e_rd_data_p1_f <= _T_131 @[Mux.scala 27:72]
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node _T_132 = bits(io.ifc_fetch_addr_f, 1, 1) @[el2_ifu_bp_ctl.scala 181:60]
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node _T_133 = not(_T_132) @[el2_ifu_bp_ctl.scala 181:40]
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node _T_134 = bits(io.ifc_fetch_addr_f, 1, 1) @[el2_ifu_bp_ctl.scala 182:60]
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node _T_135 = mux(_T_133, btb_bank0e_rd_data_f, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_136 = mux(_T_134, btb_bank0o_rd_data_f, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_137 = or(_T_135, _T_136) @[Mux.scala 27:72]
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2020-09-25 15:15:14 +08:00
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wire btb_vbank0_rd_data_f : UInt<22> @[Mux.scala 27:72]
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2020-09-28 13:28:50 +08:00
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btb_vbank0_rd_data_f <= _T_137 @[Mux.scala 27:72]
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node _T_138 = bits(io.ifc_fetch_addr_f, 1, 1) @[el2_ifu_bp_ctl.scala 184:60]
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node _T_139 = not(_T_138) @[el2_ifu_bp_ctl.scala 184:40]
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node _T_140 = bits(io.ifc_fetch_addr_f, 1, 1) @[el2_ifu_bp_ctl.scala 185:60]
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node _T_141 = mux(_T_139, btb_bank0o_rd_data_f, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_142 = mux(_T_140, btb_bank0e_rd_data_p1_f, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_143 = or(_T_141, _T_142) @[Mux.scala 27:72]
|
2020-09-25 15:15:14 +08:00
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wire btb_vbank1_rd_data_f : UInt<22> @[Mux.scala 27:72]
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2020-09-28 13:28:50 +08:00
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btb_vbank1_rd_data_f <= _T_143 @[Mux.scala 27:72]
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node mp_wrindex_dec = dshl(UInt<1>("h00"), io.exu_mp_index) @[el2_ifu_bp_ctl.scala 188:38]
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node fetch_wrindex_dec = dshl(UInt<1>("h00"), btb_rd_addr_f) @[el2_ifu_bp_ctl.scala 189:41]
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node fetch_wrindex_p1_dec = dshl(UInt<1>("h00"), btb_rd_addr_p1_f) @[el2_ifu_bp_ctl.scala 190:44]
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node _T_144 = bits(exu_mp_valid, 0, 0) @[Bitwise.scala 72:15]
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node _T_145 = mux(_T_144, UInt<256>("h0ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff"), UInt<256>("h00")) @[Bitwise.scala 72:12]
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node mp_wrlru_b0 = and(mp_wrindex_dec, _T_145) @[el2_ifu_bp_ctl.scala 191:36]
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node _T_146 = bits(io.ifc_fetch_addr_f, 1, 1) @[el2_ifu_bp_ctl.scala 193:49]
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node _T_147 = bits(_T_146, 0, 0) @[el2_ifu_bp_ctl.scala 193:53]
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node _T_148 = not(_T_147) @[el2_ifu_bp_ctl.scala 193:29]
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node _T_149 = bits(io.ifc_fetch_addr_f, 1, 1) @[el2_ifu_bp_ctl.scala 194:24]
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node _T_150 = bits(_T_149, 0, 0) @[el2_ifu_bp_ctl.scala 194:28]
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node _T_151 = bits(wayhit_p1_f, 0, 0) @[el2_ifu_bp_ctl.scala 194:51]
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node _T_152 = bits(wayhit_f, 1, 1) @[el2_ifu_bp_ctl.scala 194:64]
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node _T_153 = cat(_T_151, _T_152) @[Cat.scala 29:58]
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node _T_154 = mux(_T_148, wayhit_f, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_155 = mux(_T_150, _T_153, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_156 = or(_T_154, _T_155) @[Mux.scala 27:72]
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wire _T_157 : UInt<2> @[Mux.scala 27:72]
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_T_157 <= _T_156 @[Mux.scala 27:72]
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node _T_158 = cat(eoc_mask, UInt<1>("h01")) @[Cat.scala 29:58]
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node bht_valid_f = and(_T_157, _T_158) @[el2_ifu_bp_ctl.scala 194:71]
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node _T_159 = bits(bht_valid_f, 0, 0) @[el2_ifu_bp_ctl.scala 195:38]
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node _T_160 = bits(bht_valid_f, 1, 1) @[el2_ifu_bp_ctl.scala 195:53]
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node _T_161 = or(_T_159, _T_160) @[el2_ifu_bp_ctl.scala 195:42]
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node _T_162 = and(_T_161, io.ifc_fetch_req_f) @[el2_ifu_bp_ctl.scala 195:58]
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node _T_163 = not(leak_one_f) @[el2_ifu_bp_ctl.scala 195:81]
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node lru_update_valid_f = and(_T_162, _T_163) @[el2_ifu_bp_ctl.scala 195:79]
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node _T_164 = bits(lru_update_valid_f, 0, 0) @[Bitwise.scala 72:15]
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node _T_165 = mux(_T_164, UInt<256>("h0ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff"), UInt<256>("h00")) @[Bitwise.scala 72:12]
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node fetch_wrlru_b0 = and(fetch_wrindex_dec, _T_165) @[el2_ifu_bp_ctl.scala 197:42]
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node _T_166 = bits(lru_update_valid_f, 0, 0) @[Bitwise.scala 72:15]
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node _T_167 = mux(_T_166, UInt<256>("h0ffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff"), UInt<256>("h00")) @[Bitwise.scala 72:12]
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node fetch_wrlru_p1_b0 = and(fetch_wrindex_p1_dec, _T_167) @[el2_ifu_bp_ctl.scala 198:48]
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node _T_168 = not(mp_wrlru_b0) @[el2_ifu_bp_ctl.scala 200:25]
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node _T_169 = not(fetch_wrlru_b0) @[el2_ifu_bp_ctl.scala 200:40]
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node btb_lru_b0_hold = and(_T_168, _T_169) @[el2_ifu_bp_ctl.scala 200:38]
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node _T_170 = bits(io.exu_mp_pkt.way, 0, 0) @[el2_ifu_bp_ctl.scala 204:45]
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node _T_171 = not(_T_170) @[el2_ifu_bp_ctl.scala 204:33]
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node _T_172 = bits(tag_match_way0_f, 0, 0) @[el2_ifu_bp_ctl.scala 205:22]
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node _T_173 = bits(tag_match_way0_p1_f, 0, 0) @[el2_ifu_bp_ctl.scala 206:25]
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node _T_174 = mux(_T_171, mp_wrlru_b0, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_175 = mux(_T_172, fetch_wrlru_b0, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_176 = mux(_T_173, fetch_wrlru_p1_b0, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_177 = or(_T_174, _T_175) @[Mux.scala 27:72]
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node _T_178 = or(_T_177, _T_176) @[Mux.scala 27:72]
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wire _T_179 : UInt<256> @[Mux.scala 27:72]
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_T_179 <= _T_178 @[Mux.scala 27:72]
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node _T_180 = and(btb_lru_b0_hold, btb_lru_b0_f) @[el2_ifu_bp_ctl.scala 206:71]
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node btb_lru_b0_ns = or(_T_179, _T_180) @[el2_ifu_bp_ctl.scala 206:53]
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node _T_181 = bits(fetch_mp_collision_f, 0, 0) @[el2_ifu_bp_ctl.scala 208:37]
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node _T_182 = and(fetch_wrindex_dec, btb_lru_b0_f) @[el2_ifu_bp_ctl.scala 208:78]
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node _T_183 = orr(_T_182) @[el2_ifu_bp_ctl.scala 208:94]
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node btb_lru_rd_f = mux(_T_181, exu_mp_way_f, _T_183) @[el2_ifu_bp_ctl.scala 208:25]
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node _T_184 = bits(fetch_mp_collision_p1_f, 0, 0) @[el2_ifu_bp_ctl.scala 209:43]
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node _T_185 = and(fetch_wrindex_p1_dec, btb_lru_b0_f) @[el2_ifu_bp_ctl.scala 209:87]
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node _T_186 = orr(_T_185) @[el2_ifu_bp_ctl.scala 209:103]
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node btb_lru_rd_p1_f = mux(_T_184, exu_mp_way_f, _T_186) @[el2_ifu_bp_ctl.scala 209:28]
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node _T_187 = bits(io.ifc_fetch_addr_f, 1, 1) @[el2_ifu_bp_ctl.scala 211:53]
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node _T_188 = eq(_T_187, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 211:33]
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node _T_189 = cat(btb_lru_rd_f, btb_lru_rd_f) @[Cat.scala 29:58]
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node _T_190 = bits(io.ifc_fetch_addr_f, 1, 1) @[el2_ifu_bp_ctl.scala 212:24]
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node _T_191 = bits(_T_190, 0, 0) @[el2_ifu_bp_ctl.scala 212:28]
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node _T_192 = cat(btb_lru_rd_p1_f, btb_lru_rd_f) @[Cat.scala 29:58]
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node _T_193 = mux(_T_188, _T_189, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_194 = mux(_T_191, _T_192, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_195 = or(_T_193, _T_194) @[Mux.scala 27:72]
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2020-09-25 15:15:14 +08:00
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wire btb_vlru_rd_f : UInt @[Mux.scala 27:72]
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2020-09-28 13:28:50 +08:00
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btb_vlru_rd_f <= _T_195 @[Mux.scala 27:72]
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node _T_196 = bits(io.ifc_fetch_addr_f, 1, 1) @[el2_ifu_bp_ctl.scala 214:66]
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node _T_197 = bits(_T_196, 0, 0) @[el2_ifu_bp_ctl.scala 214:70]
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node _T_198 = not(_T_197) @[el2_ifu_bp_ctl.scala 214:46]
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node _T_199 = bits(io.ifc_fetch_addr_f, 1, 1) @[el2_ifu_bp_ctl.scala 215:24]
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node _T_200 = bits(_T_199, 0, 0) @[el2_ifu_bp_ctl.scala 215:28]
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node _T_201 = bits(tag_match_way1_expanded_p1_f, 0, 0) @[el2_ifu_bp_ctl.scala 215:68]
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node _T_202 = bits(tag_match_way1_expanded_f, 1, 1) @[el2_ifu_bp_ctl.scala 215:97]
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node _T_203 = cat(_T_201, _T_202) @[Cat.scala 29:58]
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node _T_204 = mux(_T_198, tag_match_way1_expanded_f, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_205 = mux(_T_200, _T_203, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_206 = or(_T_204, _T_205) @[Mux.scala 27:72]
|
2020-09-25 19:25:33 +08:00
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wire tag_match_vway1_expanded_f : UInt<2> @[Mux.scala 27:72]
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2020-09-28 13:28:50 +08:00
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tag_match_vway1_expanded_f <= _T_206 @[Mux.scala 27:72]
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node _T_207 = not(bht_valid_f) @[el2_ifu_bp_ctl.scala 217:47]
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node _T_208 = and(_T_207, btb_vlru_rd_f) @[el2_ifu_bp_ctl.scala 217:58]
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node way_raw = or(tag_match_vway1_expanded_f, _T_208) @[el2_ifu_bp_ctl.scala 217:44]
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node _T_209 = or(io.ifc_fetch_req_f, exu_mp_valid) @[el2_ifu_bp_ctl.scala 219:75]
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node _T_210 = bits(_T_209, 0, 0) @[el2_ifu_bp_ctl.scala 219:90]
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reg _T_211 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
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when _T_210 : @[Reg.scala 28:19]
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_T_211 <= btb_lru_b0_ns @[Reg.scala 28:23]
|
2020-09-25 19:25:33 +08:00
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skip @[Reg.scala 28:19]
|
2020-09-28 13:28:50 +08:00
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btb_lru_b0_f <= _T_211 @[el2_ifu_bp_ctl.scala 219:16]
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node _T_212 = bits(io.ifc_fetch_addr_f, 5, 3) @[el2_ifu_bp_ctl.scala 221:37]
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node eoc_near = andr(_T_212) @[el2_ifu_bp_ctl.scala 221:62]
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node _T_213 = eq(eoc_near, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 222:15]
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node _T_214 = bits(io.ifc_fetch_addr_f, 2, 1) @[el2_ifu_bp_ctl.scala 222:47]
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node _T_215 = orr(_T_214) @[el2_ifu_bp_ctl.scala 222:56]
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node _T_216 = eq(_T_215, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 222:27]
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node _T_217 = or(_T_213, _T_216) @[el2_ifu_bp_ctl.scala 222:25]
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eoc_mask <= _T_217 @[el2_ifu_bp_ctl.scala 222:12]
|
2020-09-25 19:25:33 +08:00
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wire btb_sel_data_f : UInt<17>
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btb_sel_data_f <= UInt<1>("h00")
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wire hist1_raw : UInt<2>
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|
hist1_raw <= UInt<1>("h00")
|
2020-09-28 13:28:50 +08:00
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node btb_rd_tgt_f = bits(btb_sel_data_f, 16, 5) @[el2_ifu_bp_ctl.scala 225:36]
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node btb_rd_pc4_f = bits(btb_sel_data_f, 4, 4) @[el2_ifu_bp_ctl.scala 226:36]
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node btb_rd_call_f = bits(btb_sel_data_f, 2, 2) @[el2_ifu_bp_ctl.scala 227:37]
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node btb_rd_ret_f = bits(btb_sel_data_f, 1, 1) @[el2_ifu_bp_ctl.scala 228:36]
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node _T_218 = bits(btb_sel_f, 1, 1) @[el2_ifu_bp_ctl.scala 230:40]
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node _T_219 = bits(_T_218, 0, 0) @[el2_ifu_bp_ctl.scala 230:44]
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node _T_220 = bits(btb_vbank1_rd_data_f, 16, 1) @[el2_ifu_bp_ctl.scala 230:76]
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node _T_221 = cat(_T_220, UInt<1>("h00")) @[Cat.scala 29:58]
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node _T_222 = bits(btb_sel_f, 0, 0) @[el2_ifu_bp_ctl.scala 231:14]
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node _T_223 = bits(_T_222, 0, 0) @[el2_ifu_bp_ctl.scala 231:18]
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node _T_224 = bits(btb_vbank1_rd_data_f, 16, 1) @[el2_ifu_bp_ctl.scala 231:50]
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node _T_225 = cat(_T_224, UInt<1>("h00")) @[Cat.scala 29:58]
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node _T_226 = mux(_T_219, _T_221, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_227 = mux(_T_223, _T_225, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_228 = or(_T_226, _T_227) @[Mux.scala 27:72]
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wire _T_229 : UInt<17> @[Mux.scala 27:72]
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|
_T_229 <= _T_228 @[Mux.scala 27:72]
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|
btb_sel_data_f <= _T_229 @[el2_ifu_bp_ctl.scala 230:18]
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node _T_230 = and(bht_valid_f, hist1_raw) @[el2_ifu_bp_ctl.scala 233:39]
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node _T_231 = orr(_T_230) @[el2_ifu_bp_ctl.scala 233:52]
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node _T_232 = and(_T_231, io.ifc_fetch_req_f) @[el2_ifu_bp_ctl.scala 233:56]
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node _T_233 = not(leak_one_f_d1) @[el2_ifu_bp_ctl.scala 233:79]
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node _T_234 = and(_T_232, _T_233) @[el2_ifu_bp_ctl.scala 233:77]
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node _T_235 = not(io.dec_tlu_bpred_disable) @[el2_ifu_bp_ctl.scala 233:96]
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node ifu_bp_hit_taken_f = and(_T_234, _T_235) @[el2_ifu_bp_ctl.scala 233:94]
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node _T_236 = bits(btb_vbank1_rd_data_f, 2, 2) @[el2_ifu_bp_ctl.scala 235:52]
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node _T_237 = bits(btb_vbank1_rd_data_f, 1, 1) @[el2_ifu_bp_ctl.scala 235:81]
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node _T_238 = or(_T_236, _T_237) @[el2_ifu_bp_ctl.scala 235:59]
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node _T_239 = bits(btb_vbank0_rd_data_f, 2, 2) @[el2_ifu_bp_ctl.scala 236:25]
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node _T_240 = bits(btb_vbank0_rd_data_f, 1, 1) @[el2_ifu_bp_ctl.scala 236:54]
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node _T_241 = or(_T_239, _T_240) @[el2_ifu_bp_ctl.scala 236:32]
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|
node bht_force_taken_f = cat(_T_238, _T_241) @[Cat.scala 29:58]
|
2020-09-25 19:25:33 +08:00
|
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|
wire bht_bank1_rd_data_f : UInt<2>
|
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|
bht_bank1_rd_data_f <= UInt<1>("h00")
|
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wire bht_bank0_rd_data_f : UInt<2>
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|
bht_bank0_rd_data_f <= UInt<1>("h00")
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|
wire bht_bank0_rd_data_p1_f : UInt<2>
|
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|
bht_bank0_rd_data_p1_f <= UInt<1>("h00")
|
2020-09-28 13:28:50 +08:00
|
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|
node _T_242 = bits(io.ifc_fetch_addr_f, 1, 1) @[el2_ifu_bp_ctl.scala 244:60]
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node _T_243 = bits(_T_242, 0, 0) @[el2_ifu_bp_ctl.scala 244:64]
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node _T_244 = eq(_T_243, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 244:40]
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node _T_245 = bits(io.ifc_fetch_addr_f, 1, 1) @[el2_ifu_bp_ctl.scala 245:60]
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node _T_246 = bits(_T_245, 0, 0) @[el2_ifu_bp_ctl.scala 245:64]
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node _T_247 = mux(_T_244, bht_bank0_rd_data_f, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_248 = mux(_T_246, bht_bank1_rd_data_f, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_249 = or(_T_247, _T_248) @[Mux.scala 27:72]
|
2020-09-25 19:25:33 +08:00
|
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|
wire bht_vbank0_rd_data_f : UInt<2> @[Mux.scala 27:72]
|
2020-09-28 13:28:50 +08:00
|
|
|
bht_vbank0_rd_data_f <= _T_249 @[Mux.scala 27:72]
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node _T_250 = bits(io.ifc_fetch_addr_f, 1, 1) @[el2_ifu_bp_ctl.scala 247:60]
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node _T_251 = bits(_T_250, 0, 0) @[el2_ifu_bp_ctl.scala 247:64]
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node _T_252 = eq(_T_251, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 247:40]
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node _T_253 = bits(io.ifc_fetch_addr_f, 1, 1) @[el2_ifu_bp_ctl.scala 248:60]
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node _T_254 = bits(_T_253, 0, 0) @[el2_ifu_bp_ctl.scala 248:64]
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node _T_255 = mux(_T_252, bht_bank1_rd_data_f, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_256 = mux(_T_254, bht_bank0_rd_data_p1_f, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_257 = or(_T_255, _T_256) @[Mux.scala 27:72]
|
2020-09-25 19:25:33 +08:00
|
|
|
wire bht_vbank1_rd_data_f : UInt<2> @[Mux.scala 27:72]
|
2020-09-28 13:28:50 +08:00
|
|
|
bht_vbank1_rd_data_f <= _T_257 @[Mux.scala 27:72]
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node _T_258 = bits(bht_force_taken_f, 1, 1) @[el2_ifu_bp_ctl.scala 249:38]
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node _T_259 = bits(bht_vbank1_rd_data_f, 1, 1) @[el2_ifu_bp_ctl.scala 249:64]
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node _T_260 = or(_T_258, _T_259) @[el2_ifu_bp_ctl.scala 249:42]
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node _T_261 = bits(bht_valid_f, 1, 1) @[el2_ifu_bp_ctl.scala 249:82]
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node _T_262 = and(_T_260, _T_261) @[el2_ifu_bp_ctl.scala 249:69]
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node _T_263 = bits(bht_force_taken_f, 0, 0) @[el2_ifu_bp_ctl.scala 250:41]
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node _T_264 = bits(bht_vbank0_rd_data_f, 1, 1) @[el2_ifu_bp_ctl.scala 250:67]
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node _T_265 = or(_T_263, _T_264) @[el2_ifu_bp_ctl.scala 250:45]
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node _T_266 = bits(bht_valid_f, 0, 0) @[el2_ifu_bp_ctl.scala 250:85]
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node _T_267 = and(_T_265, _T_266) @[el2_ifu_bp_ctl.scala 250:72]
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node _T_268 = cat(_T_262, _T_267) @[Cat.scala 29:58]
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bht_dir_f <= _T_268 @[el2_ifu_bp_ctl.scala 249:13]
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node _T_269 = bits(btb_sel_f, 1, 1) @[el2_ifu_bp_ctl.scala 252:59]
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node _T_270 = and(ifu_bp_hit_taken_f, _T_269) @[el2_ifu_bp_ctl.scala 252:48]
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node _T_271 = not(ifu_bp_hit_taken_f) @[el2_ifu_bp_ctl.scala 252:66]
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node ifu_bp_inst_mask_f = or(_T_270, _T_271) @[el2_ifu_bp_ctl.scala 252:64]
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node _T_272 = bits(bht_vbank1_rd_data_f, 1, 1) @[el2_ifu_bp_ctl.scala 255:60]
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node _T_273 = bits(bht_vbank0_rd_data_f, 1, 1) @[el2_ifu_bp_ctl.scala 255:85]
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node _T_274 = cat(_T_272, _T_273) @[Cat.scala 29:58]
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|
node _T_275 = or(bht_force_taken_f, _T_274) @[el2_ifu_bp_ctl.scala 255:34]
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|
hist1_raw <= _T_275 @[el2_ifu_bp_ctl.scala 255:13]
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node _T_276 = bits(bht_vbank1_rd_data_f, 0, 0) @[el2_ifu_bp_ctl.scala 257:43]
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node _T_277 = bits(bht_vbank0_rd_data_f, 0, 0) @[el2_ifu_bp_ctl.scala 257:68]
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node hist0_raw = cat(_T_276, _T_277) @[Cat.scala 29:58]
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|
node _T_278 = bits(bht_valid_f, 1, 1) @[el2_ifu_bp_ctl.scala 259:30]
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node _T_279 = bits(btb_vbank1_rd_data_f, 4, 4) @[el2_ifu_bp_ctl.scala 259:56]
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|
node _T_280 = and(_T_278, _T_279) @[el2_ifu_bp_ctl.scala 259:34]
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|
node _T_281 = bits(bht_valid_f, 0, 0) @[el2_ifu_bp_ctl.scala 260:14]
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node _T_282 = bits(btb_vbank0_rd_data_f, 4, 4) @[el2_ifu_bp_ctl.scala 260:40]
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|
node _T_283 = and(_T_281, _T_282) @[el2_ifu_bp_ctl.scala 260:18]
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|
node pc4_raw = cat(_T_280, _T_283) @[Cat.scala 29:58]
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|
node _T_284 = bits(bht_valid_f, 1, 1) @[el2_ifu_bp_ctl.scala 262:31]
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|
node _T_285 = bits(btb_vbank1_rd_data_f, 2, 2) @[el2_ifu_bp_ctl.scala 262:58]
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|
node _T_286 = not(_T_285) @[el2_ifu_bp_ctl.scala 262:37]
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node _T_287 = and(_T_284, _T_286) @[el2_ifu_bp_ctl.scala 262:35]
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|
node _T_288 = bits(btb_vbank1_rd_data_f, 1, 1) @[el2_ifu_bp_ctl.scala 262:87]
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|
node _T_289 = and(_T_287, _T_288) @[el2_ifu_bp_ctl.scala 262:65]
|
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|
node _T_290 = bits(bht_valid_f, 0, 0) @[el2_ifu_bp_ctl.scala 263:32]
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|
node _T_291 = bits(btb_vbank0_rd_data_f, 2, 2) @[el2_ifu_bp_ctl.scala 263:59]
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|
node _T_292 = not(_T_291) @[el2_ifu_bp_ctl.scala 263:38]
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|
node _T_293 = and(_T_290, _T_292) @[el2_ifu_bp_ctl.scala 263:36]
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|
node _T_294 = bits(btb_vbank0_rd_data_f, 1, 1) @[el2_ifu_bp_ctl.scala 263:88]
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|
node _T_295 = and(_T_293, _T_294) @[el2_ifu_bp_ctl.scala 263:66]
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|
|
node pret_raw = cat(_T_289, _T_295) @[Cat.scala 29:58]
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|
node _T_296 = bits(bht_valid_f, 1, 1) @[el2_ifu_bp_ctl.scala 266:31]
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|
node _T_297 = bits(bht_valid_f, 0, 0) @[el2_ifu_bp_ctl.scala 266:49]
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|
node num_valids = add(_T_296, _T_297) @[el2_ifu_bp_ctl.scala 266:35]
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|
node _T_298 = and(btb_sel_f, bht_dir_f) @[el2_ifu_bp_ctl.scala 268:28]
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|
|
|
node final_h = andr(_T_298) @[el2_ifu_bp_ctl.scala 268:41]
|
2020-09-25 19:25:33 +08:00
|
|
|
wire fghr : UInt<8>
|
|
|
|
|
fghr <= UInt<1>("h00")
|
2020-09-28 13:28:50 +08:00
|
|
|
node _T_299 = eq(num_valids, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 271:41]
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|
node _T_300 = bits(_T_299, 0, 0) @[el2_ifu_bp_ctl.scala 271:49]
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|
node _T_301 = bits(fghr, 5, 0) @[el2_ifu_bp_ctl.scala 271:65]
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|
node _T_302 = cat(_T_301, UInt<1>("h00")) @[Cat.scala 29:58]
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|
node _T_303 = cat(_T_302, final_h) @[Cat.scala 29:58]
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|
node _T_304 = eq(num_valids, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 272:16]
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|
node _T_305 = bits(_T_304, 0, 0) @[el2_ifu_bp_ctl.scala 272:24]
|
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|
|
node _T_306 = bits(fghr, 6, 0) @[el2_ifu_bp_ctl.scala 272:40]
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|
node _T_307 = cat(_T_306, final_h) @[Cat.scala 29:58]
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|
node _T_308 = eq(num_valids, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 273:16]
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|
node _T_309 = bits(_T_308, 0, 0) @[el2_ifu_bp_ctl.scala 273:24]
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|
node _T_310 = bits(fghr, 7, 0) @[el2_ifu_bp_ctl.scala 273:40]
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|
node _T_311 = mux(_T_300, _T_303, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_312 = mux(_T_305, _T_307, UInt<1>("h00")) @[Mux.scala 27:72]
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|
node _T_313 = mux(_T_309, _T_310, UInt<1>("h00")) @[Mux.scala 27:72]
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|
node _T_314 = or(_T_311, _T_312) @[Mux.scala 27:72]
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|
node _T_315 = or(_T_314, _T_313) @[Mux.scala 27:72]
|
2020-09-25 19:25:33 +08:00
|
|
|
wire merged_ghr : UInt<8> @[Mux.scala 27:72]
|
2020-09-28 13:28:50 +08:00
|
|
|
merged_ghr <= _T_315 @[Mux.scala 27:72]
|
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|
node _T_316 = bits(exu_flush_final_d1, 0, 0) @[el2_ifu_bp_ctl.scala 277:46]
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node _T_317 = not(exu_flush_final_d1) @[el2_ifu_bp_ctl.scala 278:6]
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node _T_318 = and(_T_317, io.ifc_fetch_req_f) @[el2_ifu_bp_ctl.scala 278:26]
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node _T_319 = and(_T_318, io.ic_hit_f) @[el2_ifu_bp_ctl.scala 278:47]
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node _T_320 = not(leak_one_f_d1) @[el2_ifu_bp_ctl.scala 278:63]
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node _T_321 = and(_T_319, _T_320) @[el2_ifu_bp_ctl.scala 278:61]
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node _T_322 = bits(_T_321, 0, 0) @[el2_ifu_bp_ctl.scala 278:79]
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node _T_323 = not(exu_flush_final_d1) @[el2_ifu_bp_ctl.scala 279:6]
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node _T_324 = and(io.ifc_fetch_req_f, io.ic_hit_f) @[el2_ifu_bp_ctl.scala 279:49]
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node _T_325 = not(leak_one_f_d1) @[el2_ifu_bp_ctl.scala 279:65]
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node _T_326 = and(_T_324, _T_325) @[el2_ifu_bp_ctl.scala 279:63]
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node _T_327 = not(_T_326) @[el2_ifu_bp_ctl.scala 279:28]
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node _T_328 = and(_T_323, _T_327) @[el2_ifu_bp_ctl.scala 279:26]
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node _T_329 = bits(_T_328, 0, 0) @[el2_ifu_bp_ctl.scala 279:82]
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node _T_330 = mux(_T_316, io.exu_mp_fghr, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_331 = mux(_T_322, merged_ghr, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_332 = mux(_T_329, fghr, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_333 = or(_T_330, _T_331) @[Mux.scala 27:72]
|
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|
node _T_334 = or(_T_333, _T_332) @[Mux.scala 27:72]
|
2020-09-25 19:25:33 +08:00
|
|
|
wire fghr_ns : UInt<8> @[Mux.scala 27:72]
|
2020-09-28 13:28:50 +08:00
|
|
|
fghr_ns <= _T_334 @[Mux.scala 27:72]
|
|
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|
|
reg _T_335 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_bp_ctl.scala 281:18]
|
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|
|
_T_335 <= fghr_ns @[el2_ifu_bp_ctl.scala 281:18]
|
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|
|
fghr <= _T_335 @[el2_ifu_bp_ctl.scala 281:8]
|
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|
io.ifu_bp_fghr_f <= fghr @[el2_ifu_bp_ctl.scala 282:20]
|
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|
|
|
io.ifu_bp_way_f <= way_raw @[el2_ifu_bp_ctl.scala 284:19]
|
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|
|
io.ifu_bp_hist1_f <= hist1_raw @[el2_ifu_bp_ctl.scala 285:21]
|
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|
|
io.ifu_bp_hist0_f <= hist0_raw @[el2_ifu_bp_ctl.scala 286:21]
|
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|
|
io.ifu_bp_pc4_f <= pc4_raw @[el2_ifu_bp_ctl.scala 287:19]
|
|
|
|
|
node _T_336 = bits(io.dec_tlu_bpred_disable, 0, 0) @[Bitwise.scala 72:15]
|
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|
|
node _T_337 = mux(_T_336, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
|
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|
node _T_338 = not(_T_337) @[el2_ifu_bp_ctl.scala 289:36]
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|
node _T_339 = and(bht_valid_f, _T_338) @[el2_ifu_bp_ctl.scala 289:34]
|
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|
|
io.ifu_bp_valid_f <= _T_339 @[el2_ifu_bp_ctl.scala 289:21]
|
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|
|
io.ifu_bp_ret_f <= pret_raw @[el2_ifu_bp_ctl.scala 290:19]
|
|
|
|
|
node _T_340 = bits(bht_dir_f, 0, 0) @[el2_ifu_bp_ctl.scala 292:30]
|
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|
|
node _T_341 = bits(fetch_start_f, 0, 0) @[el2_ifu_bp_ctl.scala 292:50]
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|
node _T_342 = eq(_T_341, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 292:36]
|
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|
|
node _T_343 = and(_T_340, _T_342) @[el2_ifu_bp_ctl.scala 292:34]
|
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|
node _T_344 = bits(bht_dir_f, 0, 0) @[el2_ifu_bp_ctl.scala 292:68]
|
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|
node _T_345 = eq(_T_344, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 292:58]
|
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|
node _T_346 = bits(fetch_start_f, 0, 0) @[el2_ifu_bp_ctl.scala 292:87]
|
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|
|
node _T_347 = and(_T_345, _T_346) @[el2_ifu_bp_ctl.scala 292:72]
|
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|
|
node _T_348 = or(_T_343, _T_347) @[el2_ifu_bp_ctl.scala 292:55]
|
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|
|
node _T_349 = bits(bht_dir_f, 0, 0) @[el2_ifu_bp_ctl.scala 293:15]
|
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|
|
|
node _T_350 = bits(fetch_start_f, 0, 0) @[el2_ifu_bp_ctl.scala 293:34]
|
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|
|
node _T_351 = and(_T_349, _T_350) @[el2_ifu_bp_ctl.scala 293:19]
|
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|
|
node _T_352 = bits(bht_dir_f, 0, 0) @[el2_ifu_bp_ctl.scala 293:52]
|
|
|
|
|
node _T_353 = eq(_T_352, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 293:42]
|
|
|
|
|
node _T_354 = bits(fetch_start_f, 0, 0) @[el2_ifu_bp_ctl.scala 293:72]
|
|
|
|
|
node _T_355 = eq(_T_354, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 293:58]
|
|
|
|
|
node _T_356 = and(_T_353, _T_355) @[el2_ifu_bp_ctl.scala 293:56]
|
|
|
|
|
node _T_357 = or(_T_351, _T_356) @[el2_ifu_bp_ctl.scala 293:39]
|
|
|
|
|
node bloc_f = cat(_T_348, _T_357) @[Cat.scala 29:58]
|
|
|
|
|
node _T_358 = bits(bht_dir_f, 0, 0) @[el2_ifu_bp_ctl.scala 295:31]
|
|
|
|
|
node _T_359 = eq(_T_358, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 295:21]
|
|
|
|
|
node _T_360 = bits(io.ifc_fetch_addr_f, 0, 0) @[el2_ifu_bp_ctl.scala 295:56]
|
|
|
|
|
node _T_361 = and(_T_359, _T_360) @[el2_ifu_bp_ctl.scala 295:35]
|
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|
|
node _T_362 = eq(btb_rd_pc4_f, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 295:62]
|
|
|
|
|
node use_fa_plus = and(_T_361, _T_362) @[el2_ifu_bp_ctl.scala 295:60]
|
|
|
|
|
node _T_363 = bits(fetch_start_f, 0, 0) @[el2_ifu_bp_ctl.scala 297:40]
|
|
|
|
|
node _T_364 = bits(btb_sel_f, 0, 0) @[el2_ifu_bp_ctl.scala 297:55]
|
|
|
|
|
node _T_365 = and(_T_363, _T_364) @[el2_ifu_bp_ctl.scala 297:44]
|
|
|
|
|
node btb_fg_crossing_f = and(_T_365, btb_rd_pc4_f) @[el2_ifu_bp_ctl.scala 297:59]
|
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|
|
|
node _T_366 = bits(bloc_f, 1, 1) @[el2_ifu_bp_ctl.scala 298:40]
|
|
|
|
|
node bp_total_branch_offset_f = xor(_T_366, btb_rd_pc4_f) @[el2_ifu_bp_ctl.scala 298:43]
|
|
|
|
|
node _T_367 = not(ifu_bp_hit_taken_f) @[el2_ifu_bp_ctl.scala 300:89]
|
|
|
|
|
node _T_368 = and(io.ifc_fetch_req_f, _T_367) @[el2_ifu_bp_ctl.scala 300:87]
|
|
|
|
|
node _T_369 = and(_T_368, io.ic_hit_f) @[el2_ifu_bp_ctl.scala 300:109]
|
|
|
|
|
node _T_370 = bits(_T_369, 0, 0) @[el2_ifu_bp_ctl.scala 300:124]
|
2020-09-25 19:25:33 +08:00
|
|
|
reg ifc_fetch_adder_prior : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
2020-09-28 13:28:50 +08:00
|
|
|
when _T_370 : @[Reg.scala 28:19]
|
2020-09-25 19:25:33 +08:00
|
|
|
ifc_fetch_adder_prior <= io.ifc_fetch_addr_f @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
2020-09-28 13:28:50 +08:00
|
|
|
node _T_371 = bits(use_fa_plus, 0, 0) @[el2_ifu_bp_ctl.scala 303:45]
|
|
|
|
|
node _T_372 = bits(btb_fg_crossing_f, 0, 0) @[el2_ifu_bp_ctl.scala 304:23]
|
|
|
|
|
node _T_373 = eq(btb_fg_crossing_f, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 305:6]
|
|
|
|
|
node _T_374 = eq(use_fa_plus, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 305:27]
|
|
|
|
|
node _T_375 = and(_T_373, _T_374) @[el2_ifu_bp_ctl.scala 305:25]
|
|
|
|
|
node _T_376 = bits(_T_375, 0, 0) @[el2_ifu_bp_ctl.scala 305:41]
|
|
|
|
|
node _T_377 = bits(io.ifc_fetch_addr_f, 31, 2) @[el2_ifu_bp_ctl.scala 305:68]
|
|
|
|
|
node _T_378 = mux(_T_371, fetch_addr_p1_f, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_379 = mux(_T_372, ifc_fetch_adder_prior, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_380 = mux(_T_376, _T_377, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_381 = or(_T_378, _T_379) @[Mux.scala 27:72]
|
|
|
|
|
node _T_382 = or(_T_381, _T_380) @[Mux.scala 27:72]
|
2020-09-25 19:25:33 +08:00
|
|
|
wire adder_pc_in_f : UInt @[Mux.scala 27:72]
|
2020-09-28 13:28:50 +08:00
|
|
|
adder_pc_in_f <= _T_382 @[Mux.scala 27:72]
|
|
|
|
|
node _T_383 = bits(adder_pc_in_f, 31, 2) @[el2_ifu_bp_ctl.scala 307:58]
|
|
|
|
|
node _T_384 = cat(_T_383, bp_total_branch_offset_f) @[Cat.scala 29:58]
|
|
|
|
|
node _T_385 = cat(_T_384, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
|
|
|
node _T_386 = cat(btb_rd_tgt_f, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
|
|
|
node _T_387 = bits(_T_385, 12, 1) @[el2_lib.scala 199:24]
|
|
|
|
|
node _T_388 = bits(_T_386, 12, 1) @[el2_lib.scala 199:40]
|
|
|
|
|
node _T_389 = add(_T_387, _T_388) @[el2_lib.scala 199:31]
|
|
|
|
|
node _T_390 = bits(_T_385, 31, 13) @[el2_lib.scala 200:20]
|
|
|
|
|
node _T_391 = add(_T_390, UInt<1>("h01")) @[el2_lib.scala 200:27]
|
|
|
|
|
node _T_392 = tail(_T_391, 1) @[el2_lib.scala 200:27]
|
|
|
|
|
node _T_393 = bits(_T_385, 31, 13) @[el2_lib.scala 201:20]
|
|
|
|
|
node _T_394 = add(_T_393, UInt<1>("h01")) @[el2_lib.scala 201:27]
|
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|
|
|
node _T_395 = tail(_T_394, 1) @[el2_lib.scala 201:27]
|
|
|
|
|
node _T_396 = bits(_T_386, 12, 12) @[el2_lib.scala 202:22]
|
|
|
|
|
node _T_397 = bits(_T_389, 12, 12) @[el2_lib.scala 203:38]
|
|
|
|
|
node _T_398 = eq(_T_397, UInt<1>("h00")) @[el2_lib.scala 203:27]
|
|
|
|
|
node _T_399 = xor(_T_396, _T_398) @[el2_lib.scala 203:25]
|
|
|
|
|
node _T_400 = bits(_T_399, 0, 0) @[el2_lib.scala 203:63]
|
|
|
|
|
node _T_401 = bits(_T_385, 31, 13) @[el2_lib.scala 203:75]
|
|
|
|
|
node _T_402 = eq(_T_396, UInt<1>("h00")) @[el2_lib.scala 204:8]
|
|
|
|
|
node _T_403 = bits(_T_389, 12, 12) @[el2_lib.scala 204:26]
|
|
|
|
|
node _T_404 = and(_T_402, _T_403) @[el2_lib.scala 204:14]
|
|
|
|
|
node _T_405 = bits(_T_404, 0, 0) @[el2_lib.scala 204:51]
|
|
|
|
|
node _T_406 = bits(_T_389, 12, 12) @[el2_lib.scala 205:26]
|
|
|
|
|
node _T_407 = eq(_T_406, UInt<1>("h00")) @[el2_lib.scala 205:15]
|
|
|
|
|
node _T_408 = and(_T_396, _T_407) @[el2_lib.scala 205:13]
|
|
|
|
|
node _T_409 = bits(_T_408, 0, 0) @[el2_lib.scala 205:51]
|
|
|
|
|
node _T_410 = mux(_T_400, _T_401, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_411 = mux(_T_405, _T_392, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_412 = mux(_T_409, _T_395, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_413 = or(_T_410, _T_411) @[Mux.scala 27:72]
|
|
|
|
|
node _T_414 = or(_T_413, _T_412) @[Mux.scala 27:72]
|
|
|
|
|
wire _T_415 : UInt<19> @[Mux.scala 27:72]
|
|
|
|
|
_T_415 <= _T_414 @[Mux.scala 27:72]
|
|
|
|
|
node _T_416 = bits(_T_389, 11, 0) @[el2_lib.scala 205:83]
|
|
|
|
|
node _T_417 = cat(_T_415, _T_416) @[Cat.scala 29:58]
|
|
|
|
|
node bp_btb_target_adder_f = cat(_T_417, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
|
|
|
wire rets_out : UInt<32>[8] @[el2_ifu_bp_ctl.scala 308:22]
|
|
|
|
|
rets_out[0] <= UInt<1>("h00") @[el2_ifu_bp_ctl.scala 309:12]
|
|
|
|
|
rets_out[1] <= UInt<1>("h00") @[el2_ifu_bp_ctl.scala 309:12]
|
|
|
|
|
rets_out[2] <= UInt<1>("h00") @[el2_ifu_bp_ctl.scala 309:12]
|
|
|
|
|
rets_out[3] <= UInt<1>("h00") @[el2_ifu_bp_ctl.scala 309:12]
|
|
|
|
|
rets_out[4] <= UInt<1>("h00") @[el2_ifu_bp_ctl.scala 309:12]
|
|
|
|
|
rets_out[5] <= UInt<1>("h00") @[el2_ifu_bp_ctl.scala 309:12]
|
|
|
|
|
rets_out[6] <= UInt<1>("h00") @[el2_ifu_bp_ctl.scala 309:12]
|
|
|
|
|
rets_out[7] <= UInt<1>("h00") @[el2_ifu_bp_ctl.scala 309:12]
|
|
|
|
|
node _T_418 = not(btb_rd_call_f) @[el2_ifu_bp_ctl.scala 312:49]
|
|
|
|
|
node _T_419 = and(btb_rd_ret_f, _T_418) @[el2_ifu_bp_ctl.scala 312:47]
|
|
|
|
|
node _T_420 = bits(rets_out[0], 0, 0) @[el2_ifu_bp_ctl.scala 312:77]
|
|
|
|
|
node _T_421 = and(_T_419, _T_420) @[el2_ifu_bp_ctl.scala 312:64]
|
|
|
|
|
node _T_422 = bits(_T_421, 0, 0) @[el2_ifu_bp_ctl.scala 312:82]
|
|
|
|
|
node _T_423 = bits(rets_out[0], 31, 1) @[el2_ifu_bp_ctl.scala 313:16]
|
|
|
|
|
node _T_424 = bits(bp_btb_target_adder_f, 31, 1) @[el2_ifu_bp_ctl.scala 313:44]
|
|
|
|
|
node _T_425 = mux(_T_422, _T_423, _T_424) @[el2_ifu_bp_ctl.scala 312:32]
|
|
|
|
|
io.ifu_bp_btb_target_f <= _T_425 @[el2_ifu_bp_ctl.scala 312:26]
|
|
|
|
|
node _T_426 = bits(adder_pc_in_f, 31, 2) @[el2_ifu_bp_ctl.scala 316:56]
|
|
|
|
|
node _T_427 = cat(_T_426, bp_total_branch_offset_f) @[Cat.scala 29:58]
|
|
|
|
|
node _T_428 = cat(_T_427, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
|
|
|
node _T_429 = mux(UInt<1>("h00"), UInt<11>("h07ff"), UInt<11>("h00")) @[Bitwise.scala 72:12]
|
|
|
|
|
node _T_430 = not(btb_rd_pc4_f) @[el2_ifu_bp_ctl.scala 316:113]
|
|
|
|
|
node _T_431 = cat(_T_429, _T_430) @[Cat.scala 29:58]
|
|
|
|
|
node _T_432 = cat(_T_431, UInt<1>("h00")) @[Cat.scala 29:58]
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node _T_433 = bits(_T_428, 12, 1) @[el2_lib.scala 199:24]
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node _T_434 = bits(_T_432, 12, 1) @[el2_lib.scala 199:40]
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node _T_435 = add(_T_433, _T_434) @[el2_lib.scala 199:31]
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node _T_436 = bits(_T_428, 31, 13) @[el2_lib.scala 200:20]
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node _T_437 = add(_T_436, UInt<1>("h01")) @[el2_lib.scala 200:27]
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node _T_438 = tail(_T_437, 1) @[el2_lib.scala 200:27]
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node _T_439 = bits(_T_428, 31, 13) @[el2_lib.scala 201:20]
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node _T_440 = add(_T_439, UInt<1>("h01")) @[el2_lib.scala 201:27]
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node _T_441 = tail(_T_440, 1) @[el2_lib.scala 201:27]
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node _T_442 = bits(_T_432, 12, 12) @[el2_lib.scala 202:22]
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node _T_443 = bits(_T_435, 12, 12) @[el2_lib.scala 203:38]
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node _T_444 = eq(_T_443, UInt<1>("h00")) @[el2_lib.scala 203:27]
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node _T_445 = xor(_T_442, _T_444) @[el2_lib.scala 203:25]
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node _T_446 = bits(_T_445, 0, 0) @[el2_lib.scala 203:63]
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node _T_447 = bits(_T_428, 31, 13) @[el2_lib.scala 203:75]
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node _T_448 = eq(_T_442, UInt<1>("h00")) @[el2_lib.scala 204:8]
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node _T_449 = bits(_T_435, 12, 12) @[el2_lib.scala 204:26]
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node _T_450 = and(_T_448, _T_449) @[el2_lib.scala 204:14]
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node _T_451 = bits(_T_450, 0, 0) @[el2_lib.scala 204:51]
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node _T_452 = bits(_T_435, 12, 12) @[el2_lib.scala 205:26]
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node _T_453 = eq(_T_452, UInt<1>("h00")) @[el2_lib.scala 205:15]
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node _T_454 = and(_T_442, _T_453) @[el2_lib.scala 205:13]
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node _T_455 = bits(_T_454, 0, 0) @[el2_lib.scala 205:51]
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node _T_456 = mux(_T_446, _T_447, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_457 = mux(_T_451, _T_438, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_458 = mux(_T_455, _T_441, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_459 = or(_T_456, _T_457) @[Mux.scala 27:72]
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node _T_460 = or(_T_459, _T_458) @[Mux.scala 27:72]
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wire _T_461 : UInt<19> @[Mux.scala 27:72]
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_T_461 <= _T_460 @[Mux.scala 27:72]
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node _T_462 = bits(_T_435, 11, 0) @[el2_lib.scala 205:83]
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node _T_463 = cat(_T_461, _T_462) @[Cat.scala 29:58]
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node bp_rs_call_target_f = cat(_T_463, UInt<1>("h00")) @[Cat.scala 29:58]
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node _T_464 = not(btb_rd_ret_f) @[el2_ifu_bp_ctl.scala 318:33]
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node _T_465 = and(btb_rd_call_f, _T_464) @[el2_ifu_bp_ctl.scala 318:31]
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node rs_push = and(_T_465, ifu_bp_hit_taken_f) @[el2_ifu_bp_ctl.scala 318:47]
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|
node _T_466 = not(btb_rd_call_f) @[el2_ifu_bp_ctl.scala 319:31]
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node _T_467 = and(btb_rd_ret_f, _T_466) @[el2_ifu_bp_ctl.scala 319:29]
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node rs_pop = and(_T_467, ifu_bp_hit_taken_f) @[el2_ifu_bp_ctl.scala 319:46]
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|
node _T_468 = not(rs_push) @[el2_ifu_bp_ctl.scala 320:17]
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|
node _T_469 = not(rs_pop) @[el2_ifu_bp_ctl.scala 320:28]
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|
node rs_hold = and(_T_468, _T_469) @[el2_ifu_bp_ctl.scala 320:26]
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|
|
node rsenable_0 = eq(rs_hold, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 322:60]
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|
|
node rsenable_1 = or(rs_push, rs_pop) @[el2_ifu_bp_ctl.scala 322:119]
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|
node rsenable_2 = or(rs_push, rs_pop) @[el2_ifu_bp_ctl.scala 322:119]
|
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|
|
node rsenable_3 = or(rs_push, rs_pop) @[el2_ifu_bp_ctl.scala 322:119]
|
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|
|
node rsenable_4 = or(rs_push, rs_pop) @[el2_ifu_bp_ctl.scala 322:119]
|
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|
|
node rsenable_5 = or(rs_push, rs_pop) @[el2_ifu_bp_ctl.scala 322:119]
|
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|
|
node rsenable_6 = or(rs_push, rs_pop) @[el2_ifu_bp_ctl.scala 322:119]
|
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|
|
node _T_470 = bits(rs_push, 0, 0) @[el2_ifu_bp_ctl.scala 325:23]
|
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|
|
node _T_471 = bits(bp_rs_call_target_f, 31, 1) @[el2_ifu_bp_ctl.scala 325:56]
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|
|
node _T_472 = cat(_T_471, UInt<1>("h01")) @[Cat.scala 29:58]
|
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|
|
node _T_473 = bits(rs_pop, 0, 0) @[el2_ifu_bp_ctl.scala 325:76]
|
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|
|
node _T_474 = mux(_T_470, _T_472, UInt<1>("h00")) @[Mux.scala 27:72]
|
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|
|
node _T_475 = mux(_T_473, rets_out[1], UInt<1>("h00")) @[Mux.scala 27:72]
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|
|
node _T_476 = or(_T_474, _T_475) @[Mux.scala 27:72]
|
|
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|
|
wire rets_in_0 : UInt<32> @[Mux.scala 27:72]
|
|
|
|
|
rets_in_0 <= _T_476 @[Mux.scala 27:72]
|
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|
|
node _T_477 = bits(rs_push, 0, 0) @[el2_ifu_bp_ctl.scala 327:26]
|
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|
|
node _T_478 = bits(rs_pop, 0, 0) @[el2_ifu_bp_ctl.scala 327:56]
|
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|
|
node _T_479 = mux(_T_477, rets_out[0], UInt<1>("h00")) @[Mux.scala 27:72]
|
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|
node _T_480 = mux(_T_478, rets_out[2], UInt<1>("h00")) @[Mux.scala 27:72]
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|
|
node _T_481 = or(_T_479, _T_480) @[Mux.scala 27:72]
|
|
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|
|
wire rets_in_1 : UInt<32> @[Mux.scala 27:72]
|
|
|
|
|
rets_in_1 <= _T_481 @[Mux.scala 27:72]
|
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|
|
node _T_482 = bits(rs_push, 0, 0) @[el2_ifu_bp_ctl.scala 327:26]
|
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|
|
node _T_483 = bits(rs_pop, 0, 0) @[el2_ifu_bp_ctl.scala 327:56]
|
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|
|
node _T_484 = mux(_T_482, rets_out[1], UInt<1>("h00")) @[Mux.scala 27:72]
|
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|
|
node _T_485 = mux(_T_483, rets_out[3], UInt<1>("h00")) @[Mux.scala 27:72]
|
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|
|
node _T_486 = or(_T_484, _T_485) @[Mux.scala 27:72]
|
|
|
|
|
wire rets_in_2 : UInt<32> @[Mux.scala 27:72]
|
|
|
|
|
rets_in_2 <= _T_486 @[Mux.scala 27:72]
|
|
|
|
|
node _T_487 = bits(rs_push, 0, 0) @[el2_ifu_bp_ctl.scala 327:26]
|
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|
|
node _T_488 = bits(rs_pop, 0, 0) @[el2_ifu_bp_ctl.scala 327:56]
|
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|
|
node _T_489 = mux(_T_487, rets_out[2], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
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|
|
node _T_490 = mux(_T_488, rets_out[4], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_491 = or(_T_489, _T_490) @[Mux.scala 27:72]
|
|
|
|
|
wire rets_in_3 : UInt<32> @[Mux.scala 27:72]
|
|
|
|
|
rets_in_3 <= _T_491 @[Mux.scala 27:72]
|
|
|
|
|
node _T_492 = bits(rs_push, 0, 0) @[el2_ifu_bp_ctl.scala 327:26]
|
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|
|
|
node _T_493 = bits(rs_pop, 0, 0) @[el2_ifu_bp_ctl.scala 327:56]
|
|
|
|
|
node _T_494 = mux(_T_492, rets_out[3], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_495 = mux(_T_493, rets_out[5], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
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|
|
node _T_496 = or(_T_494, _T_495) @[Mux.scala 27:72]
|
|
|
|
|
wire rets_in_4 : UInt<32> @[Mux.scala 27:72]
|
|
|
|
|
rets_in_4 <= _T_496 @[Mux.scala 27:72]
|
|
|
|
|
node _T_497 = bits(rs_push, 0, 0) @[el2_ifu_bp_ctl.scala 327:26]
|
|
|
|
|
node _T_498 = bits(rs_pop, 0, 0) @[el2_ifu_bp_ctl.scala 327:56]
|
|
|
|
|
node _T_499 = mux(_T_497, rets_out[4], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_500 = mux(_T_498, rets_out[6], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_501 = or(_T_499, _T_500) @[Mux.scala 27:72]
|
|
|
|
|
wire rets_in_5 : UInt<32> @[Mux.scala 27:72]
|
|
|
|
|
rets_in_5 <= _T_501 @[Mux.scala 27:72]
|
|
|
|
|
node _T_502 = bits(rs_push, 0, 0) @[el2_ifu_bp_ctl.scala 327:26]
|
|
|
|
|
node _T_503 = bits(rs_pop, 0, 0) @[el2_ifu_bp_ctl.scala 327:56]
|
|
|
|
|
node _T_504 = mux(_T_502, rets_out[5], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_505 = mux(_T_503, rets_out[7], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_506 = or(_T_504, _T_505) @[Mux.scala 27:72]
|
|
|
|
|
wire rets_in_6 : UInt<32> @[Mux.scala 27:72]
|
|
|
|
|
rets_in_6 <= _T_506 @[Mux.scala 27:72]
|
|
|
|
|
node _T_507 = bits(rsenable_0, 0, 0) @[el2_ifu_bp_ctl.scala 328:84]
|
|
|
|
|
reg _T_508 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_507 : @[Reg.scala 28:19]
|
|
|
|
|
_T_508 <= rets_in_0 @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
node _T_509 = bits(rsenable_1, 0, 0) @[el2_ifu_bp_ctl.scala 328:84]
|
|
|
|
|
reg _T_510 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_509 : @[Reg.scala 28:19]
|
|
|
|
|
_T_510 <= rets_in_1 @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
node _T_511 = bits(rsenable_2, 0, 0) @[el2_ifu_bp_ctl.scala 328:84]
|
|
|
|
|
reg _T_512 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_511 : @[Reg.scala 28:19]
|
|
|
|
|
_T_512 <= rets_in_2 @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
node _T_513 = bits(rsenable_3, 0, 0) @[el2_ifu_bp_ctl.scala 328:84]
|
|
|
|
|
reg _T_514 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_513 : @[Reg.scala 28:19]
|
|
|
|
|
_T_514 <= rets_in_3 @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
node _T_515 = bits(rsenable_4, 0, 0) @[el2_ifu_bp_ctl.scala 328:84]
|
|
|
|
|
reg _T_516 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_515 : @[Reg.scala 28:19]
|
|
|
|
|
_T_516 <= rets_in_4 @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
node _T_517 = bits(rsenable_5, 0, 0) @[el2_ifu_bp_ctl.scala 328:84]
|
|
|
|
|
reg _T_518 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_517 : @[Reg.scala 28:19]
|
|
|
|
|
_T_518 <= rets_in_5 @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
node _T_519 = bits(rsenable_6, 0, 0) @[el2_ifu_bp_ctl.scala 328:84]
|
|
|
|
|
reg _T_520 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_519 : @[Reg.scala 28:19]
|
|
|
|
|
_T_520 <= rets_in_6 @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
node _T_521 = bits(rs_push, 0, 0) @[el2_ifu_bp_ctl.scala 328:84]
|
|
|
|
|
reg _T_522 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_521 : @[Reg.scala 28:19]
|
|
|
|
|
_T_522 <= rets_out[6] @[Reg.scala 28:23]
|
|
|
|
|
skip @[Reg.scala 28:19]
|
|
|
|
|
rets_out[0] <= _T_508 @[el2_ifu_bp_ctl.scala 328:12]
|
|
|
|
|
rets_out[1] <= _T_510 @[el2_ifu_bp_ctl.scala 328:12]
|
|
|
|
|
rets_out[2] <= _T_512 @[el2_ifu_bp_ctl.scala 328:12]
|
|
|
|
|
rets_out[3] <= _T_514 @[el2_ifu_bp_ctl.scala 328:12]
|
|
|
|
|
rets_out[4] <= _T_516 @[el2_ifu_bp_ctl.scala 328:12]
|
|
|
|
|
rets_out[5] <= _T_518 @[el2_ifu_bp_ctl.scala 328:12]
|
|
|
|
|
rets_out[6] <= _T_520 @[el2_ifu_bp_ctl.scala 328:12]
|
|
|
|
|
rets_out[7] <= _T_522 @[el2_ifu_bp_ctl.scala 328:12]
|
|
|
|
|
node _T_523 = or(io.dec_tlu_br0_r_pkt.br_start_error, io.dec_tlu_br0_r_pkt.br_error) @[el2_ifu_bp_ctl.scala 330:50]
|
|
|
|
|
dec_tlu_error_wb <= _T_523 @[el2_ifu_bp_ctl.scala 330:20]
|
|
|
|
|
btb_error_addr_wb <= io.exu_i0_br_index_r @[el2_ifu_bp_ctl.scala 331:21]
|
|
|
|
|
dec_tlu_way_wb <= io.dec_tlu_br0_r_pkt.way @[el2_ifu_bp_ctl.scala 332:18]
|
|
|
|
|
node _T_524 = eq(dec_tlu_error_wb, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 333:35]
|
|
|
|
|
node btb_valid = and(exu_mp_valid, _T_524) @[el2_ifu_bp_ctl.scala 333:32]
|
|
|
|
|
node _T_525 = or(io.exu_mp_pkt.pcall, io.exu_mp_pkt.pja) @[el2_ifu_bp_ctl.scala 336:89]
|
|
|
|
|
node _T_526 = or(io.exu_mp_pkt.pret, io.exu_mp_pkt.pja) @[el2_ifu_bp_ctl.scala 336:113]
|
|
|
|
|
node _T_527 = cat(_T_525, _T_526) @[Cat.scala 29:58]
|
|
|
|
|
node _T_528 = cat(_T_527, btb_valid) @[Cat.scala 29:58]
|
|
|
|
|
node _T_529 = cat(io.exu_mp_pkt.pc4, io.exu_mp_pkt.boffset) @[Cat.scala 29:58]
|
|
|
|
|
node _T_530 = cat(io.exu_mp_btag, io.exu_mp_pkt.toffset) @[Cat.scala 29:58]
|
|
|
|
|
node _T_531 = cat(_T_530, _T_529) @[Cat.scala 29:58]
|
|
|
|
|
node btb_wr_data = cat(_T_531, _T_528) @[Cat.scala 29:58]
|
|
|
|
|
node exu_mp_valid_write = and(exu_mp_valid, io.exu_mp_pkt.ataken) @[el2_ifu_bp_ctl.scala 337:41]
|
2020-09-07 16:27:29 +08:00
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