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quasar/el2_ifu_aln_ctl.fir

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Aligner done
2020-09-23 18:27:02 +08:00
;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
circuit el2_ifu_aln_ctl :
ALN 1st attempt
2020-10-01 17:48:07 +08:00
module el2_ifu_compress_ctl :
input clock : Clock
input reset : Reset
output io : {flip din : UInt<16>, dout : UInt<32>}
Aligner
2020-10-07 17:21:03 +08:00
wire out : UInt<1>[32] @[el2_ifu_compress_ctl.scala 14:17]
out[0] <= UInt<1>("h00") @[el2_ifu_compress_ctl.scala 15:7]
out[1] <= UInt<1>("h00") @[el2_ifu_compress_ctl.scala 15:7]
out[2] <= UInt<1>("h00") @[el2_ifu_compress_ctl.scala 15:7]
out[3] <= UInt<1>("h00") @[el2_ifu_compress_ctl.scala 15:7]
out[4] <= UInt<1>("h00") @[el2_ifu_compress_ctl.scala 15:7]
out[5] <= UInt<1>("h00") @[el2_ifu_compress_ctl.scala 15:7]
out[6] <= UInt<1>("h00") @[el2_ifu_compress_ctl.scala 15:7]
out[7] <= UInt<1>("h00") @[el2_ifu_compress_ctl.scala 15:7]
out[8] <= UInt<1>("h00") @[el2_ifu_compress_ctl.scala 15:7]
out[9] <= UInt<1>("h00") @[el2_ifu_compress_ctl.scala 15:7]
out[10] <= UInt<1>("h00") @[el2_ifu_compress_ctl.scala 15:7]
out[11] <= UInt<1>("h00") @[el2_ifu_compress_ctl.scala 15:7]
out[12] <= UInt<1>("h00") @[el2_ifu_compress_ctl.scala 15:7]
out[13] <= UInt<1>("h00") @[el2_ifu_compress_ctl.scala 15:7]
out[14] <= UInt<1>("h00") @[el2_ifu_compress_ctl.scala 15:7]
out[15] <= UInt<1>("h00") @[el2_ifu_compress_ctl.scala 15:7]
out[16] <= UInt<1>("h00") @[el2_ifu_compress_ctl.scala 15:7]
out[17] <= UInt<1>("h00") @[el2_ifu_compress_ctl.scala 15:7]
out[18] <= UInt<1>("h00") @[el2_ifu_compress_ctl.scala 15:7]
out[19] <= UInt<1>("h00") @[el2_ifu_compress_ctl.scala 15:7]
out[20] <= UInt<1>("h00") @[el2_ifu_compress_ctl.scala 15:7]
out[21] <= UInt<1>("h00") @[el2_ifu_compress_ctl.scala 15:7]
out[22] <= UInt<1>("h00") @[el2_ifu_compress_ctl.scala 15:7]
out[23] <= UInt<1>("h00") @[el2_ifu_compress_ctl.scala 15:7]
out[24] <= UInt<1>("h00") @[el2_ifu_compress_ctl.scala 15:7]
out[25] <= UInt<1>("h00") @[el2_ifu_compress_ctl.scala 15:7]
out[26] <= UInt<1>("h00") @[el2_ifu_compress_ctl.scala 15:7]
out[27] <= UInt<1>("h00") @[el2_ifu_compress_ctl.scala 15:7]
out[28] <= UInt<1>("h00") @[el2_ifu_compress_ctl.scala 15:7]
out[29] <= UInt<1>("h00") @[el2_ifu_compress_ctl.scala 15:7]
out[30] <= UInt<1>("h00") @[el2_ifu_compress_ctl.scala 15:7]
out[31] <= UInt<1>("h00") @[el2_ifu_compress_ctl.scala 15:7]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T = bits(io.din, 15, 15) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:90]
node _T_2 = eq(_T_1, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_3 = bits(io.din, 13, 13) @[el2_ifu_compress_ctl.scala 12:90]
node _T_4 = eq(_T_3, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_5 = bits(io.din, 10, 10) @[el2_ifu_compress_ctl.scala 12:71]
node _T_6 = bits(io.din, 6, 6) @[el2_ifu_compress_ctl.scala 12:90]
node _T_7 = eq(_T_6, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_8 = bits(io.din, 5, 5) @[el2_ifu_compress_ctl.scala 12:90]
node _T_9 = eq(_T_8, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_10 = bits(io.din, 0, 0) @[el2_ifu_compress_ctl.scala 12:71]
node _T_11 = and(_T, _T_2) @[el2_ifu_compress_ctl.scala 12:110]
node _T_12 = and(_T_11, _T_4) @[el2_ifu_compress_ctl.scala 12:110]
node _T_13 = and(_T_12, _T_5) @[el2_ifu_compress_ctl.scala 12:110]
node _T_14 = and(_T_13, _T_7) @[el2_ifu_compress_ctl.scala 12:110]
node _T_15 = and(_T_14, _T_9) @[el2_ifu_compress_ctl.scala 12:110]
node _T_16 = and(_T_15, _T_10) @[el2_ifu_compress_ctl.scala 12:110]
node _T_17 = bits(io.din, 15, 15) @[el2_ifu_compress_ctl.scala 12:71]
node _T_18 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:90]
node _T_19 = eq(_T_18, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_20 = bits(io.din, 13, 13) @[el2_ifu_compress_ctl.scala 12:90]
node _T_21 = eq(_T_20, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_22 = bits(io.din, 11, 11) @[el2_ifu_compress_ctl.scala 12:90]
node _T_23 = eq(_T_22, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_24 = bits(io.din, 10, 10) @[el2_ifu_compress_ctl.scala 12:71]
node _T_25 = bits(io.din, 0, 0) @[el2_ifu_compress_ctl.scala 12:71]
node _T_26 = and(_T_17, _T_19) @[el2_ifu_compress_ctl.scala 12:110]
node _T_27 = and(_T_26, _T_21) @[el2_ifu_compress_ctl.scala 12:110]
node _T_28 = and(_T_27, _T_23) @[el2_ifu_compress_ctl.scala 12:110]
node _T_29 = and(_T_28, _T_24) @[el2_ifu_compress_ctl.scala 12:110]
node _T_30 = and(_T_29, _T_25) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node _T_31 = or(_T_16, _T_30) @[el2_ifu_compress_ctl.scala 17:53]
out[30] <= _T_31 @[el2_ifu_compress_ctl.scala 17:11]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_32 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:90]
node _T_33 = eq(_T_32, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_34 = bits(io.din, 12, 12) @[el2_ifu_compress_ctl.scala 12:71]
node _T_35 = bits(io.din, 11, 11) @[el2_ifu_compress_ctl.scala 12:90]
node _T_36 = eq(_T_35, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_37 = bits(io.din, 10, 10) @[el2_ifu_compress_ctl.scala 12:90]
node _T_38 = eq(_T_37, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_39 = bits(io.din, 9, 9) @[el2_ifu_compress_ctl.scala 12:90]
node _T_40 = eq(_T_39, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_41 = bits(io.din, 8, 8) @[el2_ifu_compress_ctl.scala 12:90]
node _T_42 = eq(_T_41, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_43 = bits(io.din, 7, 7) @[el2_ifu_compress_ctl.scala 12:90]
node _T_44 = eq(_T_43, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_45 = bits(io.din, 6, 6) @[el2_ifu_compress_ctl.scala 12:90]
node _T_46 = eq(_T_45, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_47 = bits(io.din, 5, 5) @[el2_ifu_compress_ctl.scala 12:90]
node _T_48 = eq(_T_47, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_49 = bits(io.din, 4, 4) @[el2_ifu_compress_ctl.scala 12:90]
node _T_50 = eq(_T_49, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_51 = bits(io.din, 3, 3) @[el2_ifu_compress_ctl.scala 12:90]
node _T_52 = eq(_T_51, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_53 = bits(io.din, 2, 2) @[el2_ifu_compress_ctl.scala 12:90]
node _T_54 = eq(_T_53, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_55 = bits(io.din, 1, 1) @[el2_ifu_compress_ctl.scala 12:71]
node _T_56 = and(_T_33, _T_34) @[el2_ifu_compress_ctl.scala 12:110]
node _T_57 = and(_T_56, _T_36) @[el2_ifu_compress_ctl.scala 12:110]
node _T_58 = and(_T_57, _T_38) @[el2_ifu_compress_ctl.scala 12:110]
node _T_59 = and(_T_58, _T_40) @[el2_ifu_compress_ctl.scala 12:110]
node _T_60 = and(_T_59, _T_42) @[el2_ifu_compress_ctl.scala 12:110]
node _T_61 = and(_T_60, _T_44) @[el2_ifu_compress_ctl.scala 12:110]
node _T_62 = and(_T_61, _T_46) @[el2_ifu_compress_ctl.scala 12:110]
node _T_63 = and(_T_62, _T_48) @[el2_ifu_compress_ctl.scala 12:110]
node _T_64 = and(_T_63, _T_50) @[el2_ifu_compress_ctl.scala 12:110]
node _T_65 = and(_T_64, _T_52) @[el2_ifu_compress_ctl.scala 12:110]
node _T_66 = and(_T_65, _T_54) @[el2_ifu_compress_ctl.scala 12:110]
node _T_67 = and(_T_66, _T_55) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
out[20] <= _T_67 @[el2_ifu_compress_ctl.scala 19:11]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_68 = bits(io.din, 15, 15) @[el2_ifu_compress_ctl.scala 12:71]
node _T_69 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:90]
node _T_70 = eq(_T_69, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_71 = bits(io.din, 13, 13) @[el2_ifu_compress_ctl.scala 12:90]
node _T_72 = eq(_T_71, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_73 = bits(io.din, 11, 11) @[el2_ifu_compress_ctl.scala 12:90]
node _T_74 = eq(_T_73, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_75 = bits(io.din, 0, 0) @[el2_ifu_compress_ctl.scala 12:71]
node _T_76 = and(_T_68, _T_70) @[el2_ifu_compress_ctl.scala 12:110]
node _T_77 = and(_T_76, _T_72) @[el2_ifu_compress_ctl.scala 12:110]
node _T_78 = and(_T_77, _T_74) @[el2_ifu_compress_ctl.scala 12:110]
node _T_79 = and(_T_78, _T_75) @[el2_ifu_compress_ctl.scala 12:110]
node _T_80 = bits(io.din, 15, 15) @[el2_ifu_compress_ctl.scala 12:71]
node _T_81 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:90]
node _T_82 = eq(_T_81, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_83 = bits(io.din, 13, 13) @[el2_ifu_compress_ctl.scala 12:90]
node _T_84 = eq(_T_83, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_85 = bits(io.din, 10, 10) @[el2_ifu_compress_ctl.scala 12:90]
node _T_86 = eq(_T_85, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_87 = bits(io.din, 0, 0) @[el2_ifu_compress_ctl.scala 12:71]
node _T_88 = and(_T_80, _T_82) @[el2_ifu_compress_ctl.scala 12:110]
node _T_89 = and(_T_88, _T_84) @[el2_ifu_compress_ctl.scala 12:110]
node _T_90 = and(_T_89, _T_86) @[el2_ifu_compress_ctl.scala 12:110]
node _T_91 = and(_T_90, _T_87) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node _T_92 = or(_T_79, _T_91) @[el2_ifu_compress_ctl.scala 21:46]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_93 = bits(io.din, 15, 15) @[el2_ifu_compress_ctl.scala 12:71]
node _T_94 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:90]
node _T_95 = eq(_T_94, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_96 = bits(io.din, 13, 13) @[el2_ifu_compress_ctl.scala 12:90]
node _T_97 = eq(_T_96, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_98 = bits(io.din, 6, 6) @[el2_ifu_compress_ctl.scala 12:71]
node _T_99 = bits(io.din, 0, 0) @[el2_ifu_compress_ctl.scala 12:71]
node _T_100 = and(_T_93, _T_95) @[el2_ifu_compress_ctl.scala 12:110]
node _T_101 = and(_T_100, _T_97) @[el2_ifu_compress_ctl.scala 12:110]
node _T_102 = and(_T_101, _T_98) @[el2_ifu_compress_ctl.scala 12:110]
node _T_103 = and(_T_102, _T_99) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node _T_104 = or(_T_92, _T_103) @[el2_ifu_compress_ctl.scala 21:80]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_105 = bits(io.din, 15, 15) @[el2_ifu_compress_ctl.scala 12:71]
node _T_106 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:90]
node _T_107 = eq(_T_106, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_108 = bits(io.din, 13, 13) @[el2_ifu_compress_ctl.scala 12:90]
node _T_109 = eq(_T_108, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_110 = bits(io.din, 5, 5) @[el2_ifu_compress_ctl.scala 12:71]
node _T_111 = bits(io.din, 0, 0) @[el2_ifu_compress_ctl.scala 12:71]
node _T_112 = and(_T_105, _T_107) @[el2_ifu_compress_ctl.scala 12:110]
node _T_113 = and(_T_112, _T_109) @[el2_ifu_compress_ctl.scala 12:110]
node _T_114 = and(_T_113, _T_110) @[el2_ifu_compress_ctl.scala 12:110]
node _T_115 = and(_T_114, _T_111) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node _T_116 = or(_T_104, _T_115) @[el2_ifu_compress_ctl.scala 21:113]
out[14] <= _T_116 @[el2_ifu_compress_ctl.scala 21:11]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_117 = bits(io.din, 15, 15) @[el2_ifu_compress_ctl.scala 12:71]
node _T_118 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:90]
node _T_119 = eq(_T_118, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_120 = bits(io.din, 13, 13) @[el2_ifu_compress_ctl.scala 12:90]
node _T_121 = eq(_T_120, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_122 = bits(io.din, 11, 11) @[el2_ifu_compress_ctl.scala 12:71]
node _T_123 = bits(io.din, 10, 10) @[el2_ifu_compress_ctl.scala 12:90]
node _T_124 = eq(_T_123, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_125 = bits(io.din, 0, 0) @[el2_ifu_compress_ctl.scala 12:71]
node _T_126 = and(_T_117, _T_119) @[el2_ifu_compress_ctl.scala 12:110]
node _T_127 = and(_T_126, _T_121) @[el2_ifu_compress_ctl.scala 12:110]
node _T_128 = and(_T_127, _T_122) @[el2_ifu_compress_ctl.scala 12:110]
node _T_129 = and(_T_128, _T_124) @[el2_ifu_compress_ctl.scala 12:110]
node _T_130 = and(_T_129, _T_125) @[el2_ifu_compress_ctl.scala 12:110]
node _T_131 = bits(io.din, 15, 15) @[el2_ifu_compress_ctl.scala 12:71]
node _T_132 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:90]
node _T_133 = eq(_T_132, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_134 = bits(io.din, 13, 13) @[el2_ifu_compress_ctl.scala 12:90]
node _T_135 = eq(_T_134, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_136 = bits(io.din, 11, 11) @[el2_ifu_compress_ctl.scala 12:71]
node _T_137 = bits(io.din, 6, 6) @[el2_ifu_compress_ctl.scala 12:71]
node _T_138 = bits(io.din, 0, 0) @[el2_ifu_compress_ctl.scala 12:71]
node _T_139 = and(_T_131, _T_133) @[el2_ifu_compress_ctl.scala 12:110]
node _T_140 = and(_T_139, _T_135) @[el2_ifu_compress_ctl.scala 12:110]
node _T_141 = and(_T_140, _T_136) @[el2_ifu_compress_ctl.scala 12:110]
node _T_142 = and(_T_141, _T_137) @[el2_ifu_compress_ctl.scala 12:110]
node _T_143 = and(_T_142, _T_138) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node _T_144 = or(_T_130, _T_143) @[el2_ifu_compress_ctl.scala 23:50]
node _T_145 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 23:95]
node _T_146 = bits(io.din, 0, 0) @[el2_ifu_compress_ctl.scala 23:108]
node _T_147 = eq(_T_146, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 23:101]
node _T_148 = and(_T_145, _T_147) @[el2_ifu_compress_ctl.scala 23:99]
node _T_149 = or(_T_144, _T_148) @[el2_ifu_compress_ctl.scala 23:86]
out[13] <= _T_149 @[el2_ifu_compress_ctl.scala 23:11]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_150 = bits(io.din, 15, 15) @[el2_ifu_compress_ctl.scala 12:71]
node _T_151 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:90]
node _T_152 = eq(_T_151, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_153 = bits(io.din, 13, 13) @[el2_ifu_compress_ctl.scala 12:90]
node _T_154 = eq(_T_153, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_155 = bits(io.din, 6, 6) @[el2_ifu_compress_ctl.scala 12:71]
node _T_156 = bits(io.din, 5, 5) @[el2_ifu_compress_ctl.scala 12:71]
node _T_157 = bits(io.din, 0, 0) @[el2_ifu_compress_ctl.scala 12:71]
node _T_158 = and(_T_150, _T_152) @[el2_ifu_compress_ctl.scala 12:110]
node _T_159 = and(_T_158, _T_154) @[el2_ifu_compress_ctl.scala 12:110]
node _T_160 = and(_T_159, _T_155) @[el2_ifu_compress_ctl.scala 12:110]
node _T_161 = and(_T_160, _T_156) @[el2_ifu_compress_ctl.scala 12:110]
node _T_162 = and(_T_161, _T_157) @[el2_ifu_compress_ctl.scala 12:110]
node _T_163 = bits(io.din, 15, 15) @[el2_ifu_compress_ctl.scala 12:71]
node _T_164 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:90]
node _T_165 = eq(_T_164, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_166 = bits(io.din, 13, 13) @[el2_ifu_compress_ctl.scala 12:90]
node _T_167 = eq(_T_166, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_168 = bits(io.din, 11, 11) @[el2_ifu_compress_ctl.scala 12:90]
node _T_169 = eq(_T_168, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_170 = bits(io.din, 0, 0) @[el2_ifu_compress_ctl.scala 12:71]
node _T_171 = and(_T_163, _T_165) @[el2_ifu_compress_ctl.scala 12:110]
node _T_172 = and(_T_171, _T_167) @[el2_ifu_compress_ctl.scala 12:110]
node _T_173 = and(_T_172, _T_169) @[el2_ifu_compress_ctl.scala 12:110]
node _T_174 = and(_T_173, _T_170) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node _T_175 = or(_T_162, _T_174) @[el2_ifu_compress_ctl.scala 25:47]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_176 = bits(io.din, 15, 15) @[el2_ifu_compress_ctl.scala 12:71]
node _T_177 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:90]
node _T_178 = eq(_T_177, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_179 = bits(io.din, 13, 13) @[el2_ifu_compress_ctl.scala 12:90]
node _T_180 = eq(_T_179, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_181 = bits(io.din, 10, 10) @[el2_ifu_compress_ctl.scala 12:90]
node _T_182 = eq(_T_181, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_183 = bits(io.din, 0, 0) @[el2_ifu_compress_ctl.scala 12:71]
node _T_184 = and(_T_176, _T_178) @[el2_ifu_compress_ctl.scala 12:110]
node _T_185 = and(_T_184, _T_180) @[el2_ifu_compress_ctl.scala 12:110]
node _T_186 = and(_T_185, _T_182) @[el2_ifu_compress_ctl.scala 12:110]
node _T_187 = and(_T_186, _T_183) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node _T_188 = or(_T_175, _T_187) @[el2_ifu_compress_ctl.scala 25:81]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_189 = bits(io.din, 15, 15) @[el2_ifu_compress_ctl.scala 12:90]
node _T_190 = eq(_T_189, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_191 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:90]
node _T_192 = eq(_T_191, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_193 = bits(io.din, 1, 1) @[el2_ifu_compress_ctl.scala 12:71]
node _T_194 = and(_T_190, _T_192) @[el2_ifu_compress_ctl.scala 12:110]
node _T_195 = and(_T_194, _T_193) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node _T_196 = or(_T_188, _T_195) @[el2_ifu_compress_ctl.scala 25:115]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_197 = bits(io.din, 15, 15) @[el2_ifu_compress_ctl.scala 12:71]
node _T_198 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:71]
node _T_199 = bits(io.din, 13, 13) @[el2_ifu_compress_ctl.scala 12:71]
node _T_200 = and(_T_197, _T_198) @[el2_ifu_compress_ctl.scala 12:110]
node _T_201 = and(_T_200, _T_199) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node _T_202 = or(_T_196, _T_201) @[el2_ifu_compress_ctl.scala 26:26]
out[12] <= _T_202 @[el2_ifu_compress_ctl.scala 25:11]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_203 = bits(io.din, 15, 15) @[el2_ifu_compress_ctl.scala 12:71]
node _T_204 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:90]
node _T_205 = eq(_T_204, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_206 = bits(io.din, 6, 6) @[el2_ifu_compress_ctl.scala 12:90]
node _T_207 = eq(_T_206, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_208 = bits(io.din, 5, 5) @[el2_ifu_compress_ctl.scala 12:90]
node _T_209 = eq(_T_208, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_210 = bits(io.din, 4, 4) @[el2_ifu_compress_ctl.scala 12:90]
node _T_211 = eq(_T_210, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_212 = bits(io.din, 3, 3) @[el2_ifu_compress_ctl.scala 12:90]
node _T_213 = eq(_T_212, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_214 = bits(io.din, 2, 2) @[el2_ifu_compress_ctl.scala 12:90]
node _T_215 = eq(_T_214, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_216 = and(_T_203, _T_205) @[el2_ifu_compress_ctl.scala 12:110]
node _T_217 = and(_T_216, _T_207) @[el2_ifu_compress_ctl.scala 12:110]
node _T_218 = and(_T_217, _T_209) @[el2_ifu_compress_ctl.scala 12:110]
node _T_219 = and(_T_218, _T_211) @[el2_ifu_compress_ctl.scala 12:110]
node _T_220 = and(_T_219, _T_213) @[el2_ifu_compress_ctl.scala 12:110]
node _T_221 = and(_T_220, _T_215) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node _T_222 = bits(io.din, 0, 0) @[el2_ifu_compress_ctl.scala 28:62]
node _T_223 = eq(_T_222, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 28:55]
node _T_224 = and(_T_221, _T_223) @[el2_ifu_compress_ctl.scala 28:53]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_225 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:90]
node _T_226 = eq(_T_225, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_227 = bits(io.din, 13, 13) @[el2_ifu_compress_ctl.scala 12:71]
node _T_228 = and(_T_226, _T_227) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node _T_229 = or(_T_224, _T_228) @[el2_ifu_compress_ctl.scala 28:67]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_230 = bits(io.din, 15, 15) @[el2_ifu_compress_ctl.scala 12:71]
node _T_231 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:71]
node _T_232 = bits(io.din, 0, 0) @[el2_ifu_compress_ctl.scala 12:71]
node _T_233 = and(_T_230, _T_231) @[el2_ifu_compress_ctl.scala 12:110]
node _T_234 = and(_T_233, _T_232) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node _T_235 = or(_T_229, _T_234) @[el2_ifu_compress_ctl.scala 28:88]
out[6] <= _T_235 @[el2_ifu_compress_ctl.scala 28:10]
node _T_236 = bits(io.din, 15, 15) @[el2_ifu_compress_ctl.scala 30:20]
node _T_237 = bits(io.din, 0, 0) @[el2_ifu_compress_ctl.scala 30:33]
node _T_238 = eq(_T_237, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 30:26]
node _T_239 = and(_T_236, _T_238) @[el2_ifu_compress_ctl.scala 30:24]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_240 = bits(io.din, 15, 15) @[el2_ifu_compress_ctl.scala 12:71]
node _T_241 = bits(io.din, 11, 11) @[el2_ifu_compress_ctl.scala 12:71]
node _T_242 = bits(io.din, 10, 10) @[el2_ifu_compress_ctl.scala 12:71]
node _T_243 = and(_T_240, _T_241) @[el2_ifu_compress_ctl.scala 12:110]
node _T_244 = and(_T_243, _T_242) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node _T_245 = or(_T_239, _T_244) @[el2_ifu_compress_ctl.scala 30:39]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_246 = bits(io.din, 13, 13) @[el2_ifu_compress_ctl.scala 12:71]
node _T_247 = bits(io.din, 8, 8) @[el2_ifu_compress_ctl.scala 12:90]
node _T_248 = eq(_T_247, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_249 = and(_T_246, _T_248) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node _T_250 = or(_T_245, _T_249) @[el2_ifu_compress_ctl.scala 30:63]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_251 = bits(io.din, 13, 13) @[el2_ifu_compress_ctl.scala 12:71]
node _T_252 = bits(io.din, 7, 7) @[el2_ifu_compress_ctl.scala 12:71]
node _T_253 = and(_T_251, _T_252) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node _T_254 = or(_T_250, _T_253) @[el2_ifu_compress_ctl.scala 30:83]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_255 = bits(io.din, 13, 13) @[el2_ifu_compress_ctl.scala 12:71]
node _T_256 = bits(io.din, 9, 9) @[el2_ifu_compress_ctl.scala 12:71]
node _T_257 = and(_T_255, _T_256) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node _T_258 = or(_T_254, _T_257) @[el2_ifu_compress_ctl.scala 30:102]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_259 = bits(io.din, 13, 13) @[el2_ifu_compress_ctl.scala 12:71]
node _T_260 = bits(io.din, 10, 10) @[el2_ifu_compress_ctl.scala 12:71]
node _T_261 = and(_T_259, _T_260) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node _T_262 = or(_T_258, _T_261) @[el2_ifu_compress_ctl.scala 31:22]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_263 = bits(io.din, 13, 13) @[el2_ifu_compress_ctl.scala 12:71]
node _T_264 = bits(io.din, 11, 11) @[el2_ifu_compress_ctl.scala 12:71]
node _T_265 = and(_T_263, _T_264) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node _T_266 = or(_T_262, _T_265) @[el2_ifu_compress_ctl.scala 31:42]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_267 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:90]
node _T_268 = eq(_T_267, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_269 = bits(io.din, 13, 13) @[el2_ifu_compress_ctl.scala 12:71]
node _T_270 = and(_T_268, _T_269) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node _T_271 = or(_T_266, _T_270) @[el2_ifu_compress_ctl.scala 31:62]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_272 = bits(io.din, 15, 15) @[el2_ifu_compress_ctl.scala 12:71]
node _T_273 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:71]
node _T_274 = and(_T_272, _T_273) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node _T_275 = or(_T_271, _T_274) @[el2_ifu_compress_ctl.scala 31:83]
out[5] <= _T_275 @[el2_ifu_compress_ctl.scala 30:10]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_276 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:90]
node _T_277 = eq(_T_276, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_278 = bits(io.din, 11, 11) @[el2_ifu_compress_ctl.scala 12:90]
node _T_279 = eq(_T_278, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_280 = bits(io.din, 10, 10) @[el2_ifu_compress_ctl.scala 12:90]
node _T_281 = eq(_T_280, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_282 = bits(io.din, 9, 9) @[el2_ifu_compress_ctl.scala 12:90]
node _T_283 = eq(_T_282, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_284 = bits(io.din, 8, 8) @[el2_ifu_compress_ctl.scala 12:90]
node _T_285 = eq(_T_284, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_286 = bits(io.din, 7, 7) @[el2_ifu_compress_ctl.scala 12:90]
node _T_287 = eq(_T_286, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_288 = and(_T_277, _T_279) @[el2_ifu_compress_ctl.scala 12:110]
node _T_289 = and(_T_288, _T_281) @[el2_ifu_compress_ctl.scala 12:110]
node _T_290 = and(_T_289, _T_283) @[el2_ifu_compress_ctl.scala 12:110]
node _T_291 = and(_T_290, _T_285) @[el2_ifu_compress_ctl.scala 12:110]
node _T_292 = and(_T_291, _T_287) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node _T_293 = bits(io.din, 0, 0) @[el2_ifu_compress_ctl.scala 33:59]
node _T_294 = eq(_T_293, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 33:52]
node _T_295 = and(_T_292, _T_294) @[el2_ifu_compress_ctl.scala 33:50]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_296 = bits(io.din, 15, 15) @[el2_ifu_compress_ctl.scala 12:90]
node _T_297 = eq(_T_296, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_298 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:90]
node _T_299 = eq(_T_298, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_300 = and(_T_297, _T_299) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node _T_301 = bits(io.din, 0, 0) @[el2_ifu_compress_ctl.scala 33:96]
node _T_302 = eq(_T_301, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 33:89]
node _T_303 = and(_T_300, _T_302) @[el2_ifu_compress_ctl.scala 33:87]
node _T_304 = or(_T_295, _T_303) @[el2_ifu_compress_ctl.scala 33:65]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_305 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:90]
node _T_306 = eq(_T_305, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_307 = bits(io.din, 6, 6) @[el2_ifu_compress_ctl.scala 12:71]
node _T_308 = and(_T_306, _T_307) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node _T_309 = bits(io.din, 0, 0) @[el2_ifu_compress_ctl.scala 34:32]
node _T_310 = eq(_T_309, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 34:25]
node _T_311 = and(_T_308, _T_310) @[el2_ifu_compress_ctl.scala 34:23]
node _T_312 = or(_T_304, _T_311) @[el2_ifu_compress_ctl.scala 33:102]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_313 = bits(io.din, 15, 15) @[el2_ifu_compress_ctl.scala 12:90]
node _T_314 = eq(_T_313, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_315 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:71]
node _T_316 = bits(io.din, 0, 0) @[el2_ifu_compress_ctl.scala 12:71]
node _T_317 = and(_T_314, _T_315) @[el2_ifu_compress_ctl.scala 12:110]
node _T_318 = and(_T_317, _T_316) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node _T_319 = or(_T_312, _T_318) @[el2_ifu_compress_ctl.scala 34:38]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_320 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:90]
node _T_321 = eq(_T_320, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_322 = bits(io.din, 5, 5) @[el2_ifu_compress_ctl.scala 12:71]
node _T_323 = and(_T_321, _T_322) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node _T_324 = bits(io.din, 0, 0) @[el2_ifu_compress_ctl.scala 34:91]
node _T_325 = eq(_T_324, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 34:84]
node _T_326 = and(_T_323, _T_325) @[el2_ifu_compress_ctl.scala 34:82]
node _T_327 = or(_T_319, _T_326) @[el2_ifu_compress_ctl.scala 34:62]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_328 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:90]
node _T_329 = eq(_T_328, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_330 = bits(io.din, 4, 4) @[el2_ifu_compress_ctl.scala 12:71]
node _T_331 = and(_T_329, _T_330) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node _T_332 = bits(io.din, 0, 0) @[el2_ifu_compress_ctl.scala 35:32]
node _T_333 = eq(_T_332, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 35:25]
node _T_334 = and(_T_331, _T_333) @[el2_ifu_compress_ctl.scala 35:23]
node _T_335 = or(_T_327, _T_334) @[el2_ifu_compress_ctl.scala 34:97]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_336 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:90]
node _T_337 = eq(_T_336, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_338 = bits(io.din, 3, 3) @[el2_ifu_compress_ctl.scala 12:71]
node _T_339 = and(_T_337, _T_338) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node _T_340 = bits(io.din, 0, 0) @[el2_ifu_compress_ctl.scala 35:67]
node _T_341 = eq(_T_340, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 35:60]
node _T_342 = and(_T_339, _T_341) @[el2_ifu_compress_ctl.scala 35:58]
node _T_343 = or(_T_335, _T_342) @[el2_ifu_compress_ctl.scala 35:38]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_344 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:90]
node _T_345 = eq(_T_344, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_346 = bits(io.din, 2, 2) @[el2_ifu_compress_ctl.scala 12:71]
node _T_347 = and(_T_345, _T_346) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node _T_348 = bits(io.din, 0, 0) @[el2_ifu_compress_ctl.scala 35:102]
node _T_349 = eq(_T_348, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 35:95]
node _T_350 = and(_T_347, _T_349) @[el2_ifu_compress_ctl.scala 35:93]
node _T_351 = or(_T_343, _T_350) @[el2_ifu_compress_ctl.scala 35:73]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_352 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:90]
node _T_353 = eq(_T_352, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_354 = bits(io.din, 13, 13) @[el2_ifu_compress_ctl.scala 12:90]
node _T_355 = eq(_T_354, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_356 = bits(io.din, 0, 0) @[el2_ifu_compress_ctl.scala 12:71]
node _T_357 = and(_T_353, _T_355) @[el2_ifu_compress_ctl.scala 12:110]
node _T_358 = and(_T_357, _T_356) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node _T_359 = or(_T_351, _T_358) @[el2_ifu_compress_ctl.scala 35:108]
out[4] <= _T_359 @[el2_ifu_compress_ctl.scala 33:10]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_360 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:90]
node _T_361 = eq(_T_360, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_362 = bits(io.din, 13, 13) @[el2_ifu_compress_ctl.scala 12:71]
node _T_363 = and(_T_361, _T_362) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
out[3] <= _T_363 @[el2_ifu_compress_ctl.scala 38:10]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_364 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:90]
node _T_365 = eq(_T_364, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_366 = bits(io.din, 12, 12) @[el2_ifu_compress_ctl.scala 12:71]
node _T_367 = bits(io.din, 11, 11) @[el2_ifu_compress_ctl.scala 12:71]
node _T_368 = bits(io.din, 6, 6) @[el2_ifu_compress_ctl.scala 12:90]
node _T_369 = eq(_T_368, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_370 = bits(io.din, 5, 5) @[el2_ifu_compress_ctl.scala 12:90]
node _T_371 = eq(_T_370, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_372 = bits(io.din, 4, 4) @[el2_ifu_compress_ctl.scala 12:90]
node _T_373 = eq(_T_372, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_374 = bits(io.din, 3, 3) @[el2_ifu_compress_ctl.scala 12:90]
node _T_375 = eq(_T_374, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_376 = bits(io.din, 2, 2) @[el2_ifu_compress_ctl.scala 12:90]
node _T_377 = eq(_T_376, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_378 = bits(io.din, 1, 1) @[el2_ifu_compress_ctl.scala 12:71]
node _T_379 = and(_T_365, _T_366) @[el2_ifu_compress_ctl.scala 12:110]
node _T_380 = and(_T_379, _T_367) @[el2_ifu_compress_ctl.scala 12:110]
node _T_381 = and(_T_380, _T_369) @[el2_ifu_compress_ctl.scala 12:110]
node _T_382 = and(_T_381, _T_371) @[el2_ifu_compress_ctl.scala 12:110]
node _T_383 = and(_T_382, _T_373) @[el2_ifu_compress_ctl.scala 12:110]
node _T_384 = and(_T_383, _T_375) @[el2_ifu_compress_ctl.scala 12:110]
node _T_385 = and(_T_384, _T_377) @[el2_ifu_compress_ctl.scala 12:110]
node _T_386 = and(_T_385, _T_378) @[el2_ifu_compress_ctl.scala 12:110]
node _T_387 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:90]
node _T_388 = eq(_T_387, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_389 = bits(io.din, 12, 12) @[el2_ifu_compress_ctl.scala 12:71]
node _T_390 = bits(io.din, 10, 10) @[el2_ifu_compress_ctl.scala 12:71]
node _T_391 = bits(io.din, 6, 6) @[el2_ifu_compress_ctl.scala 12:90]
node _T_392 = eq(_T_391, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_393 = bits(io.din, 5, 5) @[el2_ifu_compress_ctl.scala 12:90]
node _T_394 = eq(_T_393, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_395 = bits(io.din, 4, 4) @[el2_ifu_compress_ctl.scala 12:90]
node _T_396 = eq(_T_395, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_397 = bits(io.din, 3, 3) @[el2_ifu_compress_ctl.scala 12:90]
node _T_398 = eq(_T_397, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_399 = bits(io.din, 2, 2) @[el2_ifu_compress_ctl.scala 12:90]
node _T_400 = eq(_T_399, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_401 = bits(io.din, 1, 1) @[el2_ifu_compress_ctl.scala 12:71]
node _T_402 = and(_T_388, _T_389) @[el2_ifu_compress_ctl.scala 12:110]
node _T_403 = and(_T_402, _T_390) @[el2_ifu_compress_ctl.scala 12:110]
node _T_404 = and(_T_403, _T_392) @[el2_ifu_compress_ctl.scala 12:110]
node _T_405 = and(_T_404, _T_394) @[el2_ifu_compress_ctl.scala 12:110]
node _T_406 = and(_T_405, _T_396) @[el2_ifu_compress_ctl.scala 12:110]
node _T_407 = and(_T_406, _T_398) @[el2_ifu_compress_ctl.scala 12:110]
node _T_408 = and(_T_407, _T_400) @[el2_ifu_compress_ctl.scala 12:110]
node _T_409 = and(_T_408, _T_401) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node _T_410 = or(_T_386, _T_409) @[el2_ifu_compress_ctl.scala 40:59]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_411 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:90]
node _T_412 = eq(_T_411, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_413 = bits(io.din, 12, 12) @[el2_ifu_compress_ctl.scala 12:71]
node _T_414 = bits(io.din, 9, 9) @[el2_ifu_compress_ctl.scala 12:71]
node _T_415 = bits(io.din, 6, 6) @[el2_ifu_compress_ctl.scala 12:90]
node _T_416 = eq(_T_415, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_417 = bits(io.din, 5, 5) @[el2_ifu_compress_ctl.scala 12:90]
node _T_418 = eq(_T_417, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_419 = bits(io.din, 4, 4) @[el2_ifu_compress_ctl.scala 12:90]
node _T_420 = eq(_T_419, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_421 = bits(io.din, 3, 3) @[el2_ifu_compress_ctl.scala 12:90]
node _T_422 = eq(_T_421, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_423 = bits(io.din, 2, 2) @[el2_ifu_compress_ctl.scala 12:90]
node _T_424 = eq(_T_423, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_425 = bits(io.din, 1, 1) @[el2_ifu_compress_ctl.scala 12:71]
node _T_426 = and(_T_412, _T_413) @[el2_ifu_compress_ctl.scala 12:110]
node _T_427 = and(_T_426, _T_414) @[el2_ifu_compress_ctl.scala 12:110]
node _T_428 = and(_T_427, _T_416) @[el2_ifu_compress_ctl.scala 12:110]
node _T_429 = and(_T_428, _T_418) @[el2_ifu_compress_ctl.scala 12:110]
node _T_430 = and(_T_429, _T_420) @[el2_ifu_compress_ctl.scala 12:110]
node _T_431 = and(_T_430, _T_422) @[el2_ifu_compress_ctl.scala 12:110]
node _T_432 = and(_T_431, _T_424) @[el2_ifu_compress_ctl.scala 12:110]
node _T_433 = and(_T_432, _T_425) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node _T_434 = or(_T_410, _T_433) @[el2_ifu_compress_ctl.scala 40:107]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_435 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:90]
node _T_436 = eq(_T_435, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_437 = bits(io.din, 12, 12) @[el2_ifu_compress_ctl.scala 12:71]
node _T_438 = bits(io.din, 8, 8) @[el2_ifu_compress_ctl.scala 12:71]
node _T_439 = bits(io.din, 6, 6) @[el2_ifu_compress_ctl.scala 12:90]
node _T_440 = eq(_T_439, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_441 = bits(io.din, 5, 5) @[el2_ifu_compress_ctl.scala 12:90]
node _T_442 = eq(_T_441, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_443 = bits(io.din, 4, 4) @[el2_ifu_compress_ctl.scala 12:90]
node _T_444 = eq(_T_443, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_445 = bits(io.din, 3, 3) @[el2_ifu_compress_ctl.scala 12:90]
node _T_446 = eq(_T_445, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_447 = bits(io.din, 2, 2) @[el2_ifu_compress_ctl.scala 12:90]
node _T_448 = eq(_T_447, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_449 = bits(io.din, 1, 1) @[el2_ifu_compress_ctl.scala 12:71]
node _T_450 = and(_T_436, _T_437) @[el2_ifu_compress_ctl.scala 12:110]
node _T_451 = and(_T_450, _T_438) @[el2_ifu_compress_ctl.scala 12:110]
node _T_452 = and(_T_451, _T_440) @[el2_ifu_compress_ctl.scala 12:110]
node _T_453 = and(_T_452, _T_442) @[el2_ifu_compress_ctl.scala 12:110]
node _T_454 = and(_T_453, _T_444) @[el2_ifu_compress_ctl.scala 12:110]
node _T_455 = and(_T_454, _T_446) @[el2_ifu_compress_ctl.scala 12:110]
node _T_456 = and(_T_455, _T_448) @[el2_ifu_compress_ctl.scala 12:110]
node _T_457 = and(_T_456, _T_449) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node _T_458 = or(_T_434, _T_457) @[el2_ifu_compress_ctl.scala 41:50]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_459 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:90]
node _T_460 = eq(_T_459, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_461 = bits(io.din, 12, 12) @[el2_ifu_compress_ctl.scala 12:71]
node _T_462 = bits(io.din, 7, 7) @[el2_ifu_compress_ctl.scala 12:71]
node _T_463 = bits(io.din, 6, 6) @[el2_ifu_compress_ctl.scala 12:90]
node _T_464 = eq(_T_463, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_465 = bits(io.din, 5, 5) @[el2_ifu_compress_ctl.scala 12:90]
node _T_466 = eq(_T_465, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_467 = bits(io.din, 4, 4) @[el2_ifu_compress_ctl.scala 12:90]
node _T_468 = eq(_T_467, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_469 = bits(io.din, 3, 3) @[el2_ifu_compress_ctl.scala 12:90]
node _T_470 = eq(_T_469, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_471 = bits(io.din, 2, 2) @[el2_ifu_compress_ctl.scala 12:90]
node _T_472 = eq(_T_471, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_473 = bits(io.din, 1, 1) @[el2_ifu_compress_ctl.scala 12:71]
node _T_474 = and(_T_460, _T_461) @[el2_ifu_compress_ctl.scala 12:110]
node _T_475 = and(_T_474, _T_462) @[el2_ifu_compress_ctl.scala 12:110]
node _T_476 = and(_T_475, _T_464) @[el2_ifu_compress_ctl.scala 12:110]
node _T_477 = and(_T_476, _T_466) @[el2_ifu_compress_ctl.scala 12:110]
node _T_478 = and(_T_477, _T_468) @[el2_ifu_compress_ctl.scala 12:110]
node _T_479 = and(_T_478, _T_470) @[el2_ifu_compress_ctl.scala 12:110]
node _T_480 = and(_T_479, _T_472) @[el2_ifu_compress_ctl.scala 12:110]
node _T_481 = and(_T_480, _T_473) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node _T_482 = or(_T_458, _T_481) @[el2_ifu_compress_ctl.scala 41:94]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_483 = bits(io.din, 15, 15) @[el2_ifu_compress_ctl.scala 12:71]
node _T_484 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:90]
node _T_485 = eq(_T_484, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_486 = bits(io.din, 12, 12) @[el2_ifu_compress_ctl.scala 12:90]
node _T_487 = eq(_T_486, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_488 = bits(io.din, 6, 6) @[el2_ifu_compress_ctl.scala 12:90]
node _T_489 = eq(_T_488, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_490 = bits(io.din, 5, 5) @[el2_ifu_compress_ctl.scala 12:90]
node _T_491 = eq(_T_490, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_492 = bits(io.din, 4, 4) @[el2_ifu_compress_ctl.scala 12:90]
node _T_493 = eq(_T_492, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_494 = bits(io.din, 3, 3) @[el2_ifu_compress_ctl.scala 12:90]
node _T_495 = eq(_T_494, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_496 = bits(io.din, 2, 2) @[el2_ifu_compress_ctl.scala 12:90]
node _T_497 = eq(_T_496, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_498 = and(_T_483, _T_485) @[el2_ifu_compress_ctl.scala 12:110]
node _T_499 = and(_T_498, _T_487) @[el2_ifu_compress_ctl.scala 12:110]
node _T_500 = and(_T_499, _T_489) @[el2_ifu_compress_ctl.scala 12:110]
node _T_501 = and(_T_500, _T_491) @[el2_ifu_compress_ctl.scala 12:110]
node _T_502 = and(_T_501, _T_493) @[el2_ifu_compress_ctl.scala 12:110]
node _T_503 = and(_T_502, _T_495) @[el2_ifu_compress_ctl.scala 12:110]
node _T_504 = and(_T_503, _T_497) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node _T_505 = bits(io.din, 0, 0) @[el2_ifu_compress_ctl.scala 42:103]
node _T_506 = eq(_T_505, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 42:96]
node _T_507 = and(_T_504, _T_506) @[el2_ifu_compress_ctl.scala 42:94]
node _T_508 = or(_T_482, _T_507) @[el2_ifu_compress_ctl.scala 42:49]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_509 = bits(io.din, 15, 15) @[el2_ifu_compress_ctl.scala 12:90]
node _T_510 = eq(_T_509, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_511 = bits(io.din, 13, 13) @[el2_ifu_compress_ctl.scala 12:71]
node _T_512 = bits(io.din, 8, 8) @[el2_ifu_compress_ctl.scala 12:90]
node _T_513 = eq(_T_512, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_514 = and(_T_510, _T_511) @[el2_ifu_compress_ctl.scala 12:110]
node _T_515 = and(_T_514, _T_513) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node _T_516 = or(_T_508, _T_515) @[el2_ifu_compress_ctl.scala 42:109]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_517 = bits(io.din, 15, 15) @[el2_ifu_compress_ctl.scala 12:90]
node _T_518 = eq(_T_517, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_519 = bits(io.din, 13, 13) @[el2_ifu_compress_ctl.scala 12:71]
node _T_520 = bits(io.din, 7, 7) @[el2_ifu_compress_ctl.scala 12:71]
node _T_521 = and(_T_518, _T_519) @[el2_ifu_compress_ctl.scala 12:110]
node _T_522 = and(_T_521, _T_520) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node _T_523 = or(_T_516, _T_522) @[el2_ifu_compress_ctl.scala 43:26]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_524 = bits(io.din, 15, 15) @[el2_ifu_compress_ctl.scala 12:90]
node _T_525 = eq(_T_524, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_526 = bits(io.din, 13, 13) @[el2_ifu_compress_ctl.scala 12:71]
node _T_527 = bits(io.din, 9, 9) @[el2_ifu_compress_ctl.scala 12:71]
node _T_528 = and(_T_525, _T_526) @[el2_ifu_compress_ctl.scala 12:110]
node _T_529 = and(_T_528, _T_527) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node _T_530 = or(_T_523, _T_529) @[el2_ifu_compress_ctl.scala 43:48]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_531 = bits(io.din, 15, 15) @[el2_ifu_compress_ctl.scala 12:90]
node _T_532 = eq(_T_531, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_533 = bits(io.din, 13, 13) @[el2_ifu_compress_ctl.scala 12:71]
node _T_534 = bits(io.din, 10, 10) @[el2_ifu_compress_ctl.scala 12:71]
node _T_535 = and(_T_532, _T_533) @[el2_ifu_compress_ctl.scala 12:110]
node _T_536 = and(_T_535, _T_534) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node _T_537 = or(_T_530, _T_536) @[el2_ifu_compress_ctl.scala 43:70]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_538 = bits(io.din, 15, 15) @[el2_ifu_compress_ctl.scala 12:90]
node _T_539 = eq(_T_538, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_540 = bits(io.din, 13, 13) @[el2_ifu_compress_ctl.scala 12:71]
node _T_541 = bits(io.din, 11, 11) @[el2_ifu_compress_ctl.scala 12:71]
node _T_542 = and(_T_539, _T_540) @[el2_ifu_compress_ctl.scala 12:110]
node _T_543 = and(_T_542, _T_541) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node _T_544 = or(_T_537, _T_543) @[el2_ifu_compress_ctl.scala 43:93]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_545 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:90]
node _T_546 = eq(_T_545, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_547 = bits(io.din, 13, 13) @[el2_ifu_compress_ctl.scala 12:71]
node _T_548 = and(_T_546, _T_547) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node _T_549 = or(_T_544, _T_548) @[el2_ifu_compress_ctl.scala 44:26]
out[2] <= _T_549 @[el2_ifu_compress_ctl.scala 40:10]
out[1] <= UInt<1>("h01") @[el2_ifu_compress_ctl.scala 46:10]
out[0] <= UInt<1>("h01") @[el2_ifu_compress_ctl.scala 48:10]
node rs2d = bits(io.din, 6, 2) @[el2_ifu_compress_ctl.scala 50:20]
node rdd = bits(io.din, 11, 7) @[el2_ifu_compress_ctl.scala 51:19]
node _T_550 = bits(io.din, 9, 7) @[el2_ifu_compress_ctl.scala 52:34]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node rdpd = cat(UInt<2>("h01"), _T_550) @[Cat.scala 29:58]
Aligner
2020-10-07 17:21:03 +08:00
node _T_551 = bits(io.din, 4, 2) @[el2_ifu_compress_ctl.scala 53:35]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node rs2pd = cat(UInt<2>("h01"), _T_551) @[Cat.scala 29:58]
node _T_552 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:90]
node _T_553 = eq(_T_552, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_554 = bits(io.din, 6, 6) @[el2_ifu_compress_ctl.scala 12:71]
node _T_555 = bits(io.din, 1, 1) @[el2_ifu_compress_ctl.scala 12:71]
node _T_556 = and(_T_553, _T_554) @[el2_ifu_compress_ctl.scala 12:110]
node _T_557 = and(_T_556, _T_555) @[el2_ifu_compress_ctl.scala 12:110]
node _T_558 = bits(io.din, 15, 15) @[el2_ifu_compress_ctl.scala 12:90]
node _T_559 = eq(_T_558, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_560 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:71]
node _T_561 = bits(io.din, 11, 11) @[el2_ifu_compress_ctl.scala 12:71]
node _T_562 = bits(io.din, 0, 0) @[el2_ifu_compress_ctl.scala 12:71]
node _T_563 = and(_T_559, _T_560) @[el2_ifu_compress_ctl.scala 12:110]
node _T_564 = and(_T_563, _T_561) @[el2_ifu_compress_ctl.scala 12:110]
node _T_565 = and(_T_564, _T_562) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node _T_566 = or(_T_557, _T_565) @[el2_ifu_compress_ctl.scala 55:33]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_567 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:90]
node _T_568 = eq(_T_567, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_569 = bits(io.din, 5, 5) @[el2_ifu_compress_ctl.scala 12:71]
node _T_570 = bits(io.din, 1, 1) @[el2_ifu_compress_ctl.scala 12:71]
node _T_571 = and(_T_568, _T_569) @[el2_ifu_compress_ctl.scala 12:110]
node _T_572 = and(_T_571, _T_570) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node _T_573 = or(_T_566, _T_572) @[el2_ifu_compress_ctl.scala 55:58]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_574 = bits(io.din, 15, 15) @[el2_ifu_compress_ctl.scala 12:90]
node _T_575 = eq(_T_574, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_576 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:71]
node _T_577 = bits(io.din, 10, 10) @[el2_ifu_compress_ctl.scala 12:71]
node _T_578 = bits(io.din, 0, 0) @[el2_ifu_compress_ctl.scala 12:71]
node _T_579 = and(_T_575, _T_576) @[el2_ifu_compress_ctl.scala 12:110]
node _T_580 = and(_T_579, _T_577) @[el2_ifu_compress_ctl.scala 12:110]
node _T_581 = and(_T_580, _T_578) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node _T_582 = or(_T_573, _T_581) @[el2_ifu_compress_ctl.scala 55:79]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_583 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:90]
node _T_584 = eq(_T_583, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_585 = bits(io.din, 4, 4) @[el2_ifu_compress_ctl.scala 12:71]
node _T_586 = bits(io.din, 1, 1) @[el2_ifu_compress_ctl.scala 12:71]
node _T_587 = and(_T_584, _T_585) @[el2_ifu_compress_ctl.scala 12:110]
node _T_588 = and(_T_587, _T_586) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node _T_589 = or(_T_582, _T_588) @[el2_ifu_compress_ctl.scala 55:104]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_590 = bits(io.din, 15, 15) @[el2_ifu_compress_ctl.scala 12:90]
node _T_591 = eq(_T_590, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_592 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:71]
node _T_593 = bits(io.din, 9, 9) @[el2_ifu_compress_ctl.scala 12:71]
node _T_594 = bits(io.din, 0, 0) @[el2_ifu_compress_ctl.scala 12:71]
node _T_595 = and(_T_591, _T_592) @[el2_ifu_compress_ctl.scala 12:110]
node _T_596 = and(_T_595, _T_593) @[el2_ifu_compress_ctl.scala 12:110]
node _T_597 = and(_T_596, _T_594) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node _T_598 = or(_T_589, _T_597) @[el2_ifu_compress_ctl.scala 56:24]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_599 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:90]
node _T_600 = eq(_T_599, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_601 = bits(io.din, 3, 3) @[el2_ifu_compress_ctl.scala 12:71]
node _T_602 = bits(io.din, 1, 1) @[el2_ifu_compress_ctl.scala 12:71]
node _T_603 = and(_T_600, _T_601) @[el2_ifu_compress_ctl.scala 12:110]
node _T_604 = and(_T_603, _T_602) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node _T_605 = or(_T_598, _T_604) @[el2_ifu_compress_ctl.scala 56:48]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_606 = bits(io.din, 15, 15) @[el2_ifu_compress_ctl.scala 12:90]
node _T_607 = eq(_T_606, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_608 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:71]
node _T_609 = bits(io.din, 8, 8) @[el2_ifu_compress_ctl.scala 12:90]
node _T_610 = eq(_T_609, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_611 = bits(io.din, 0, 0) @[el2_ifu_compress_ctl.scala 12:71]
node _T_612 = and(_T_607, _T_608) @[el2_ifu_compress_ctl.scala 12:110]
node _T_613 = and(_T_612, _T_610) @[el2_ifu_compress_ctl.scala 12:110]
node _T_614 = and(_T_613, _T_611) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node _T_615 = or(_T_605, _T_614) @[el2_ifu_compress_ctl.scala 56:69]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_616 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:90]
node _T_617 = eq(_T_616, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_618 = bits(io.din, 2, 2) @[el2_ifu_compress_ctl.scala 12:71]
node _T_619 = bits(io.din, 1, 1) @[el2_ifu_compress_ctl.scala 12:71]
node _T_620 = and(_T_617, _T_618) @[el2_ifu_compress_ctl.scala 12:110]
node _T_621 = and(_T_620, _T_619) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node _T_622 = or(_T_615, _T_621) @[el2_ifu_compress_ctl.scala 56:94]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_623 = bits(io.din, 15, 15) @[el2_ifu_compress_ctl.scala 12:90]
node _T_624 = eq(_T_623, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_625 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:71]
node _T_626 = bits(io.din, 7, 7) @[el2_ifu_compress_ctl.scala 12:71]
node _T_627 = bits(io.din, 0, 0) @[el2_ifu_compress_ctl.scala 12:71]
node _T_628 = and(_T_624, _T_625) @[el2_ifu_compress_ctl.scala 12:110]
node _T_629 = and(_T_628, _T_626) @[el2_ifu_compress_ctl.scala 12:110]
node _T_630 = and(_T_629, _T_627) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node _T_631 = or(_T_622, _T_630) @[el2_ifu_compress_ctl.scala 57:22]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_632 = bits(io.din, 15, 15) @[el2_ifu_compress_ctl.scala 12:90]
node _T_633 = eq(_T_632, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_634 = bits(io.din, 1, 1) @[el2_ifu_compress_ctl.scala 12:71]
node _T_635 = and(_T_633, _T_634) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node _T_636 = or(_T_631, _T_635) @[el2_ifu_compress_ctl.scala 57:46]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_637 = bits(io.din, 15, 15) @[el2_ifu_compress_ctl.scala 12:90]
node _T_638 = eq(_T_637, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_639 = bits(io.din, 13, 13) @[el2_ifu_compress_ctl.scala 12:90]
node _T_640 = eq(_T_639, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_641 = bits(io.din, 0, 0) @[el2_ifu_compress_ctl.scala 12:71]
node _T_642 = and(_T_638, _T_640) @[el2_ifu_compress_ctl.scala 12:110]
node _T_643 = and(_T_642, _T_641) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node rdrd = or(_T_636, _T_643) @[el2_ifu_compress_ctl.scala 57:65]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_644 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:90]
node _T_645 = eq(_T_644, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_646 = bits(io.din, 12, 12) @[el2_ifu_compress_ctl.scala 12:71]
node _T_647 = bits(io.din, 11, 11) @[el2_ifu_compress_ctl.scala 12:71]
node _T_648 = bits(io.din, 1, 1) @[el2_ifu_compress_ctl.scala 12:71]
node _T_649 = and(_T_645, _T_646) @[el2_ifu_compress_ctl.scala 12:110]
node _T_650 = and(_T_649, _T_647) @[el2_ifu_compress_ctl.scala 12:110]
node _T_651 = and(_T_650, _T_648) @[el2_ifu_compress_ctl.scala 12:110]
node _T_652 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:90]
node _T_653 = eq(_T_652, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_654 = bits(io.din, 12, 12) @[el2_ifu_compress_ctl.scala 12:71]
node _T_655 = bits(io.din, 10, 10) @[el2_ifu_compress_ctl.scala 12:71]
node _T_656 = bits(io.din, 1, 1) @[el2_ifu_compress_ctl.scala 12:71]
node _T_657 = and(_T_653, _T_654) @[el2_ifu_compress_ctl.scala 12:110]
node _T_658 = and(_T_657, _T_655) @[el2_ifu_compress_ctl.scala 12:110]
node _T_659 = and(_T_658, _T_656) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node _T_660 = or(_T_651, _T_659) @[el2_ifu_compress_ctl.scala 59:38]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_661 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:90]
node _T_662 = eq(_T_661, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_663 = bits(io.din, 12, 12) @[el2_ifu_compress_ctl.scala 12:71]
node _T_664 = bits(io.din, 9, 9) @[el2_ifu_compress_ctl.scala 12:71]
node _T_665 = bits(io.din, 1, 1) @[el2_ifu_compress_ctl.scala 12:71]
node _T_666 = and(_T_662, _T_663) @[el2_ifu_compress_ctl.scala 12:110]
node _T_667 = and(_T_666, _T_664) @[el2_ifu_compress_ctl.scala 12:110]
node _T_668 = and(_T_667, _T_665) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node _T_669 = or(_T_660, _T_668) @[el2_ifu_compress_ctl.scala 59:63]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_670 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:90]
node _T_671 = eq(_T_670, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_672 = bits(io.din, 12, 12) @[el2_ifu_compress_ctl.scala 12:71]
node _T_673 = bits(io.din, 8, 8) @[el2_ifu_compress_ctl.scala 12:71]
node _T_674 = bits(io.din, 1, 1) @[el2_ifu_compress_ctl.scala 12:71]
node _T_675 = and(_T_671, _T_672) @[el2_ifu_compress_ctl.scala 12:110]
node _T_676 = and(_T_675, _T_673) @[el2_ifu_compress_ctl.scala 12:110]
node _T_677 = and(_T_676, _T_674) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node _T_678 = or(_T_669, _T_677) @[el2_ifu_compress_ctl.scala 59:87]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_679 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:90]
node _T_680 = eq(_T_679, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_681 = bits(io.din, 12, 12) @[el2_ifu_compress_ctl.scala 12:71]
node _T_682 = bits(io.din, 7, 7) @[el2_ifu_compress_ctl.scala 12:71]
node _T_683 = bits(io.din, 1, 1) @[el2_ifu_compress_ctl.scala 12:71]
node _T_684 = and(_T_680, _T_681) @[el2_ifu_compress_ctl.scala 12:110]
node _T_685 = and(_T_684, _T_682) @[el2_ifu_compress_ctl.scala 12:110]
node _T_686 = and(_T_685, _T_683) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node _T_687 = or(_T_678, _T_686) @[el2_ifu_compress_ctl.scala 60:27]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_688 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:90]
node _T_689 = eq(_T_688, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_690 = bits(io.din, 12, 12) @[el2_ifu_compress_ctl.scala 12:90]
node _T_691 = eq(_T_690, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_692 = bits(io.din, 6, 6) @[el2_ifu_compress_ctl.scala 12:90]
node _T_693 = eq(_T_692, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_694 = bits(io.din, 5, 5) @[el2_ifu_compress_ctl.scala 12:90]
node _T_695 = eq(_T_694, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_696 = bits(io.din, 4, 4) @[el2_ifu_compress_ctl.scala 12:90]
node _T_697 = eq(_T_696, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_698 = bits(io.din, 3, 3) @[el2_ifu_compress_ctl.scala 12:90]
node _T_699 = eq(_T_698, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_700 = bits(io.din, 2, 2) @[el2_ifu_compress_ctl.scala 12:90]
node _T_701 = eq(_T_700, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_702 = bits(io.din, 1, 1) @[el2_ifu_compress_ctl.scala 12:71]
node _T_703 = and(_T_689, _T_691) @[el2_ifu_compress_ctl.scala 12:110]
node _T_704 = and(_T_703, _T_693) @[el2_ifu_compress_ctl.scala 12:110]
node _T_705 = and(_T_704, _T_695) @[el2_ifu_compress_ctl.scala 12:110]
node _T_706 = and(_T_705, _T_697) @[el2_ifu_compress_ctl.scala 12:110]
node _T_707 = and(_T_706, _T_699) @[el2_ifu_compress_ctl.scala 12:110]
node _T_708 = and(_T_707, _T_701) @[el2_ifu_compress_ctl.scala 12:110]
node _T_709 = and(_T_708, _T_702) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node _T_710 = or(_T_687, _T_709) @[el2_ifu_compress_ctl.scala 60:51]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_711 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:90]
node _T_712 = eq(_T_711, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_713 = bits(io.din, 12, 12) @[el2_ifu_compress_ctl.scala 12:71]
node _T_714 = bits(io.din, 6, 6) @[el2_ifu_compress_ctl.scala 12:71]
node _T_715 = bits(io.din, 1, 1) @[el2_ifu_compress_ctl.scala 12:71]
node _T_716 = and(_T_712, _T_713) @[el2_ifu_compress_ctl.scala 12:110]
node _T_717 = and(_T_716, _T_714) @[el2_ifu_compress_ctl.scala 12:110]
node _T_718 = and(_T_717, _T_715) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node _T_719 = or(_T_710, _T_718) @[el2_ifu_compress_ctl.scala 60:89]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_720 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:90]
node _T_721 = eq(_T_720, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_722 = bits(io.din, 12, 12) @[el2_ifu_compress_ctl.scala 12:71]
node _T_723 = bits(io.din, 5, 5) @[el2_ifu_compress_ctl.scala 12:71]
node _T_724 = bits(io.din, 1, 1) @[el2_ifu_compress_ctl.scala 12:71]
node _T_725 = and(_T_721, _T_722) @[el2_ifu_compress_ctl.scala 12:110]
node _T_726 = and(_T_725, _T_723) @[el2_ifu_compress_ctl.scala 12:110]
node _T_727 = and(_T_726, _T_724) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node _T_728 = or(_T_719, _T_727) @[el2_ifu_compress_ctl.scala 61:27]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_729 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:90]
node _T_730 = eq(_T_729, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_731 = bits(io.din, 12, 12) @[el2_ifu_compress_ctl.scala 12:71]
node _T_732 = bits(io.din, 4, 4) @[el2_ifu_compress_ctl.scala 12:71]
node _T_733 = bits(io.din, 1, 1) @[el2_ifu_compress_ctl.scala 12:71]
node _T_734 = and(_T_730, _T_731) @[el2_ifu_compress_ctl.scala 12:110]
node _T_735 = and(_T_734, _T_732) @[el2_ifu_compress_ctl.scala 12:110]
node _T_736 = and(_T_735, _T_733) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node _T_737 = or(_T_728, _T_736) @[el2_ifu_compress_ctl.scala 61:51]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_738 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:90]
node _T_739 = eq(_T_738, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_740 = bits(io.din, 12, 12) @[el2_ifu_compress_ctl.scala 12:71]
node _T_741 = bits(io.din, 3, 3) @[el2_ifu_compress_ctl.scala 12:71]
node _T_742 = bits(io.din, 1, 1) @[el2_ifu_compress_ctl.scala 12:71]
node _T_743 = and(_T_739, _T_740) @[el2_ifu_compress_ctl.scala 12:110]
node _T_744 = and(_T_743, _T_741) @[el2_ifu_compress_ctl.scala 12:110]
node _T_745 = and(_T_744, _T_742) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node _T_746 = or(_T_737, _T_745) @[el2_ifu_compress_ctl.scala 61:75]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_747 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:90]
node _T_748 = eq(_T_747, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_749 = bits(io.din, 12, 12) @[el2_ifu_compress_ctl.scala 12:71]
node _T_750 = bits(io.din, 2, 2) @[el2_ifu_compress_ctl.scala 12:71]
node _T_751 = bits(io.din, 1, 1) @[el2_ifu_compress_ctl.scala 12:71]
node _T_752 = and(_T_748, _T_749) @[el2_ifu_compress_ctl.scala 12:110]
node _T_753 = and(_T_752, _T_750) @[el2_ifu_compress_ctl.scala 12:110]
node _T_754 = and(_T_753, _T_751) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node _T_755 = or(_T_746, _T_754) @[el2_ifu_compress_ctl.scala 61:99]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_756 = bits(io.din, 15, 15) @[el2_ifu_compress_ctl.scala 12:90]
node _T_757 = eq(_T_756, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_758 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:90]
node _T_759 = eq(_T_758, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_760 = bits(io.din, 13, 13) @[el2_ifu_compress_ctl.scala 12:90]
node _T_761 = eq(_T_760, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_762 = bits(io.din, 0, 0) @[el2_ifu_compress_ctl.scala 12:71]
node _T_763 = and(_T_757, _T_759) @[el2_ifu_compress_ctl.scala 12:110]
node _T_764 = and(_T_763, _T_761) @[el2_ifu_compress_ctl.scala 12:110]
node _T_765 = and(_T_764, _T_762) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node _T_766 = or(_T_755, _T_765) @[el2_ifu_compress_ctl.scala 62:27]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_767 = bits(io.din, 15, 15) @[el2_ifu_compress_ctl.scala 12:90]
node _T_768 = eq(_T_767, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_769 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:90]
node _T_770 = eq(_T_769, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_771 = bits(io.din, 1, 1) @[el2_ifu_compress_ctl.scala 12:71]
node _T_772 = and(_T_768, _T_770) @[el2_ifu_compress_ctl.scala 12:110]
node _T_773 = and(_T_772, _T_771) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node rdrs1 = or(_T_766, _T_773) @[el2_ifu_compress_ctl.scala 62:54]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_774 = bits(io.din, 15, 15) @[el2_ifu_compress_ctl.scala 12:71]
node _T_775 = bits(io.din, 6, 6) @[el2_ifu_compress_ctl.scala 12:71]
node _T_776 = bits(io.din, 1, 1) @[el2_ifu_compress_ctl.scala 12:71]
node _T_777 = and(_T_774, _T_775) @[el2_ifu_compress_ctl.scala 12:110]
node _T_778 = and(_T_777, _T_776) @[el2_ifu_compress_ctl.scala 12:110]
node _T_779 = bits(io.din, 15, 15) @[el2_ifu_compress_ctl.scala 12:71]
node _T_780 = bits(io.din, 5, 5) @[el2_ifu_compress_ctl.scala 12:71]
node _T_781 = bits(io.din, 1, 1) @[el2_ifu_compress_ctl.scala 12:71]
node _T_782 = and(_T_779, _T_780) @[el2_ifu_compress_ctl.scala 12:110]
node _T_783 = and(_T_782, _T_781) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node _T_784 = or(_T_778, _T_783) @[el2_ifu_compress_ctl.scala 64:34]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_785 = bits(io.din, 15, 15) @[el2_ifu_compress_ctl.scala 12:71]
node _T_786 = bits(io.din, 4, 4) @[el2_ifu_compress_ctl.scala 12:71]
node _T_787 = bits(io.din, 1, 1) @[el2_ifu_compress_ctl.scala 12:71]
node _T_788 = and(_T_785, _T_786) @[el2_ifu_compress_ctl.scala 12:110]
node _T_789 = and(_T_788, _T_787) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node _T_790 = or(_T_784, _T_789) @[el2_ifu_compress_ctl.scala 64:54]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_791 = bits(io.din, 15, 15) @[el2_ifu_compress_ctl.scala 12:71]
node _T_792 = bits(io.din, 3, 3) @[el2_ifu_compress_ctl.scala 12:71]
node _T_793 = bits(io.din, 1, 1) @[el2_ifu_compress_ctl.scala 12:71]
node _T_794 = and(_T_791, _T_792) @[el2_ifu_compress_ctl.scala 12:110]
node _T_795 = and(_T_794, _T_793) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node _T_796 = or(_T_790, _T_795) @[el2_ifu_compress_ctl.scala 64:74]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_797 = bits(io.din, 15, 15) @[el2_ifu_compress_ctl.scala 12:71]
node _T_798 = bits(io.din, 2, 2) @[el2_ifu_compress_ctl.scala 12:71]
node _T_799 = bits(io.din, 1, 1) @[el2_ifu_compress_ctl.scala 12:71]
node _T_800 = and(_T_797, _T_798) @[el2_ifu_compress_ctl.scala 12:110]
node _T_801 = and(_T_800, _T_799) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node _T_802 = or(_T_796, _T_801) @[el2_ifu_compress_ctl.scala 64:94]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_803 = bits(io.din, 15, 15) @[el2_ifu_compress_ctl.scala 12:71]
node _T_804 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:71]
node _T_805 = bits(io.din, 1, 1) @[el2_ifu_compress_ctl.scala 12:71]
node _T_806 = and(_T_803, _T_804) @[el2_ifu_compress_ctl.scala 12:110]
node _T_807 = and(_T_806, _T_805) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node rs2rs2 = or(_T_802, _T_807) @[el2_ifu_compress_ctl.scala 64:114]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_808 = bits(io.din, 15, 15) @[el2_ifu_compress_ctl.scala 12:71]
node _T_809 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:90]
node _T_810 = eq(_T_809, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_811 = bits(io.din, 13, 13) @[el2_ifu_compress_ctl.scala 12:90]
node _T_812 = eq(_T_811, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_813 = bits(io.din, 0, 0) @[el2_ifu_compress_ctl.scala 12:71]
node _T_814 = and(_T_808, _T_810) @[el2_ifu_compress_ctl.scala 12:110]
node _T_815 = and(_T_814, _T_812) @[el2_ifu_compress_ctl.scala 12:110]
node rdprd = and(_T_815, _T_813) @[el2_ifu_compress_ctl.scala 12:110]
node _T_816 = bits(io.din, 15, 15) @[el2_ifu_compress_ctl.scala 12:71]
node _T_817 = bits(io.din, 13, 13) @[el2_ifu_compress_ctl.scala 12:90]
node _T_818 = eq(_T_817, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_819 = bits(io.din, 0, 0) @[el2_ifu_compress_ctl.scala 12:71]
node _T_820 = and(_T_816, _T_818) @[el2_ifu_compress_ctl.scala 12:110]
node _T_821 = and(_T_820, _T_819) @[el2_ifu_compress_ctl.scala 12:110]
node _T_822 = bits(io.din, 15, 15) @[el2_ifu_compress_ctl.scala 12:71]
node _T_823 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:71]
node _T_824 = bits(io.din, 0, 0) @[el2_ifu_compress_ctl.scala 12:71]
node _T_825 = and(_T_822, _T_823) @[el2_ifu_compress_ctl.scala 12:110]
node _T_826 = and(_T_825, _T_824) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node _T_827 = or(_T_821, _T_826) @[el2_ifu_compress_ctl.scala 68:36]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_828 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:71]
node _T_829 = bits(io.din, 1, 1) @[el2_ifu_compress_ctl.scala 12:90]
node _T_830 = eq(_T_829, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_831 = and(_T_828, _T_830) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node _T_832 = bits(io.din, 0, 0) @[el2_ifu_compress_ctl.scala 68:85]
node _T_833 = eq(_T_832, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 68:78]
node _T_834 = and(_T_831, _T_833) @[el2_ifu_compress_ctl.scala 68:76]
node rdprs1 = or(_T_827, _T_834) @[el2_ifu_compress_ctl.scala 68:57]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_835 = bits(io.din, 15, 15) @[el2_ifu_compress_ctl.scala 12:71]
node _T_836 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:90]
node _T_837 = eq(_T_836, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_838 = bits(io.din, 13, 13) @[el2_ifu_compress_ctl.scala 12:90]
node _T_839 = eq(_T_838, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_840 = bits(io.din, 11, 11) @[el2_ifu_compress_ctl.scala 12:71]
node _T_841 = bits(io.din, 10, 10) @[el2_ifu_compress_ctl.scala 12:71]
node _T_842 = bits(io.din, 0, 0) @[el2_ifu_compress_ctl.scala 12:71]
node _T_843 = and(_T_835, _T_837) @[el2_ifu_compress_ctl.scala 12:110]
node _T_844 = and(_T_843, _T_839) @[el2_ifu_compress_ctl.scala 12:110]
node _T_845 = and(_T_844, _T_840) @[el2_ifu_compress_ctl.scala 12:110]
node _T_846 = and(_T_845, _T_841) @[el2_ifu_compress_ctl.scala 12:110]
node _T_847 = and(_T_846, _T_842) @[el2_ifu_compress_ctl.scala 12:110]
node _T_848 = bits(io.din, 15, 15) @[el2_ifu_compress_ctl.scala 12:71]
node _T_849 = bits(io.din, 1, 1) @[el2_ifu_compress_ctl.scala 12:90]
node _T_850 = eq(_T_849, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_851 = and(_T_848, _T_850) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node _T_852 = bits(io.din, 0, 0) @[el2_ifu_compress_ctl.scala 70:75]
node _T_853 = eq(_T_852, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 70:68]
node _T_854 = and(_T_851, _T_853) @[el2_ifu_compress_ctl.scala 70:66]
node rs2prs2 = or(_T_847, _T_854) @[el2_ifu_compress_ctl.scala 70:47]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_855 = bits(io.din, 15, 15) @[el2_ifu_compress_ctl.scala 12:90]
node _T_856 = eq(_T_855, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_857 = bits(io.din, 1, 1) @[el2_ifu_compress_ctl.scala 12:90]
node _T_858 = eq(_T_857, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_859 = and(_T_856, _T_858) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node _T_860 = bits(io.din, 0, 0) @[el2_ifu_compress_ctl.scala 72:42]
node _T_861 = eq(_T_860, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 72:35]
node rs2prd = and(_T_859, _T_861) @[el2_ifu_compress_ctl.scala 72:33]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_862 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:90]
node _T_863 = eq(_T_862, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_864 = bits(io.din, 1, 1) @[el2_ifu_compress_ctl.scala 12:90]
node _T_865 = eq(_T_864, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_866 = and(_T_863, _T_865) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node _T_867 = bits(io.din, 0, 0) @[el2_ifu_compress_ctl.scala 74:43]
node _T_868 = eq(_T_867, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 74:36]
node uimm9_2 = and(_T_866, _T_868) @[el2_ifu_compress_ctl.scala 74:34]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_869 = bits(io.din, 15, 15) @[el2_ifu_compress_ctl.scala 12:90]
node _T_870 = eq(_T_869, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_871 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:71]
node _T_872 = bits(io.din, 1, 1) @[el2_ifu_compress_ctl.scala 12:90]
node _T_873 = eq(_T_872, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_874 = and(_T_870, _T_871) @[el2_ifu_compress_ctl.scala 12:110]
node _T_875 = and(_T_874, _T_873) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node _T_876 = bits(io.din, 0, 0) @[el2_ifu_compress_ctl.scala 76:48]
node _T_877 = eq(_T_876, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 76:41]
node ulwimm6_2 = and(_T_875, _T_877) @[el2_ifu_compress_ctl.scala 76:39]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_878 = bits(io.din, 15, 15) @[el2_ifu_compress_ctl.scala 12:90]
node _T_879 = eq(_T_878, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_880 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:71]
node _T_881 = bits(io.din, 1, 1) @[el2_ifu_compress_ctl.scala 12:71]
node _T_882 = and(_T_879, _T_880) @[el2_ifu_compress_ctl.scala 12:110]
node ulwspimm7_2 = and(_T_882, _T_881) @[el2_ifu_compress_ctl.scala 12:110]
node _T_883 = bits(io.din, 15, 15) @[el2_ifu_compress_ctl.scala 12:90]
node _T_884 = eq(_T_883, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_885 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:71]
node _T_886 = bits(io.din, 13, 13) @[el2_ifu_compress_ctl.scala 12:71]
node _T_887 = bits(io.din, 11, 11) @[el2_ifu_compress_ctl.scala 12:90]
node _T_888 = eq(_T_887, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_889 = bits(io.din, 10, 10) @[el2_ifu_compress_ctl.scala 12:90]
node _T_890 = eq(_T_889, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_891 = bits(io.din, 9, 9) @[el2_ifu_compress_ctl.scala 12:90]
node _T_892 = eq(_T_891, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_893 = bits(io.din, 8, 8) @[el2_ifu_compress_ctl.scala 12:71]
node _T_894 = bits(io.din, 7, 7) @[el2_ifu_compress_ctl.scala 12:90]
node _T_895 = eq(_T_894, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_896 = and(_T_884, _T_885) @[el2_ifu_compress_ctl.scala 12:110]
node _T_897 = and(_T_896, _T_886) @[el2_ifu_compress_ctl.scala 12:110]
node _T_898 = and(_T_897, _T_888) @[el2_ifu_compress_ctl.scala 12:110]
node _T_899 = and(_T_898, _T_890) @[el2_ifu_compress_ctl.scala 12:110]
node _T_900 = and(_T_899, _T_892) @[el2_ifu_compress_ctl.scala 12:110]
node _T_901 = and(_T_900, _T_893) @[el2_ifu_compress_ctl.scala 12:110]
node rdeq2 = and(_T_901, _T_895) @[el2_ifu_compress_ctl.scala 12:110]
node _T_902 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:90]
node _T_903 = eq(_T_902, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_904 = bits(io.din, 12, 12) @[el2_ifu_compress_ctl.scala 12:71]
node _T_905 = bits(io.din, 11, 11) @[el2_ifu_compress_ctl.scala 12:71]
node _T_906 = bits(io.din, 6, 6) @[el2_ifu_compress_ctl.scala 12:90]
node _T_907 = eq(_T_906, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_908 = bits(io.din, 5, 5) @[el2_ifu_compress_ctl.scala 12:90]
node _T_909 = eq(_T_908, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_910 = bits(io.din, 4, 4) @[el2_ifu_compress_ctl.scala 12:90]
node _T_911 = eq(_T_910, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_912 = bits(io.din, 3, 3) @[el2_ifu_compress_ctl.scala 12:90]
node _T_913 = eq(_T_912, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_914 = bits(io.din, 2, 2) @[el2_ifu_compress_ctl.scala 12:90]
node _T_915 = eq(_T_914, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_916 = bits(io.din, 1, 1) @[el2_ifu_compress_ctl.scala 12:71]
node _T_917 = and(_T_903, _T_904) @[el2_ifu_compress_ctl.scala 12:110]
node _T_918 = and(_T_917, _T_905) @[el2_ifu_compress_ctl.scala 12:110]
node _T_919 = and(_T_918, _T_907) @[el2_ifu_compress_ctl.scala 12:110]
node _T_920 = and(_T_919, _T_909) @[el2_ifu_compress_ctl.scala 12:110]
node _T_921 = and(_T_920, _T_911) @[el2_ifu_compress_ctl.scala 12:110]
node _T_922 = and(_T_921, _T_913) @[el2_ifu_compress_ctl.scala 12:110]
node _T_923 = and(_T_922, _T_915) @[el2_ifu_compress_ctl.scala 12:110]
node _T_924 = and(_T_923, _T_916) @[el2_ifu_compress_ctl.scala 12:110]
node _T_925 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:90]
node _T_926 = eq(_T_925, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_927 = bits(io.din, 12, 12) @[el2_ifu_compress_ctl.scala 12:71]
node _T_928 = bits(io.din, 10, 10) @[el2_ifu_compress_ctl.scala 12:71]
node _T_929 = bits(io.din, 6, 6) @[el2_ifu_compress_ctl.scala 12:90]
node _T_930 = eq(_T_929, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_931 = bits(io.din, 5, 5) @[el2_ifu_compress_ctl.scala 12:90]
node _T_932 = eq(_T_931, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_933 = bits(io.din, 4, 4) @[el2_ifu_compress_ctl.scala 12:90]
node _T_934 = eq(_T_933, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_935 = bits(io.din, 3, 3) @[el2_ifu_compress_ctl.scala 12:90]
node _T_936 = eq(_T_935, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_937 = bits(io.din, 2, 2) @[el2_ifu_compress_ctl.scala 12:90]
node _T_938 = eq(_T_937, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_939 = bits(io.din, 1, 1) @[el2_ifu_compress_ctl.scala 12:71]
node _T_940 = and(_T_926, _T_927) @[el2_ifu_compress_ctl.scala 12:110]
node _T_941 = and(_T_940, _T_928) @[el2_ifu_compress_ctl.scala 12:110]
node _T_942 = and(_T_941, _T_930) @[el2_ifu_compress_ctl.scala 12:110]
node _T_943 = and(_T_942, _T_932) @[el2_ifu_compress_ctl.scala 12:110]
node _T_944 = and(_T_943, _T_934) @[el2_ifu_compress_ctl.scala 12:110]
node _T_945 = and(_T_944, _T_936) @[el2_ifu_compress_ctl.scala 12:110]
node _T_946 = and(_T_945, _T_938) @[el2_ifu_compress_ctl.scala 12:110]
node _T_947 = and(_T_946, _T_939) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node _T_948 = or(_T_924, _T_947) @[el2_ifu_compress_ctl.scala 82:53]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_949 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:90]
node _T_950 = eq(_T_949, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_951 = bits(io.din, 12, 12) @[el2_ifu_compress_ctl.scala 12:71]
node _T_952 = bits(io.din, 9, 9) @[el2_ifu_compress_ctl.scala 12:71]
node _T_953 = bits(io.din, 6, 6) @[el2_ifu_compress_ctl.scala 12:90]
node _T_954 = eq(_T_953, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_955 = bits(io.din, 5, 5) @[el2_ifu_compress_ctl.scala 12:90]
node _T_956 = eq(_T_955, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_957 = bits(io.din, 4, 4) @[el2_ifu_compress_ctl.scala 12:90]
node _T_958 = eq(_T_957, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_959 = bits(io.din, 3, 3) @[el2_ifu_compress_ctl.scala 12:90]
node _T_960 = eq(_T_959, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_961 = bits(io.din, 2, 2) @[el2_ifu_compress_ctl.scala 12:90]
node _T_962 = eq(_T_961, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_963 = bits(io.din, 1, 1) @[el2_ifu_compress_ctl.scala 12:71]
node _T_964 = and(_T_950, _T_951) @[el2_ifu_compress_ctl.scala 12:110]
node _T_965 = and(_T_964, _T_952) @[el2_ifu_compress_ctl.scala 12:110]
node _T_966 = and(_T_965, _T_954) @[el2_ifu_compress_ctl.scala 12:110]
node _T_967 = and(_T_966, _T_956) @[el2_ifu_compress_ctl.scala 12:110]
node _T_968 = and(_T_967, _T_958) @[el2_ifu_compress_ctl.scala 12:110]
node _T_969 = and(_T_968, _T_960) @[el2_ifu_compress_ctl.scala 12:110]
node _T_970 = and(_T_969, _T_962) @[el2_ifu_compress_ctl.scala 12:110]
node _T_971 = and(_T_970, _T_963) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node _T_972 = or(_T_948, _T_971) @[el2_ifu_compress_ctl.scala 82:93]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_973 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:90]
node _T_974 = eq(_T_973, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_975 = bits(io.din, 12, 12) @[el2_ifu_compress_ctl.scala 12:71]
node _T_976 = bits(io.din, 8, 8) @[el2_ifu_compress_ctl.scala 12:71]
node _T_977 = bits(io.din, 6, 6) @[el2_ifu_compress_ctl.scala 12:90]
node _T_978 = eq(_T_977, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_979 = bits(io.din, 5, 5) @[el2_ifu_compress_ctl.scala 12:90]
node _T_980 = eq(_T_979, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_981 = bits(io.din, 4, 4) @[el2_ifu_compress_ctl.scala 12:90]
node _T_982 = eq(_T_981, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_983 = bits(io.din, 3, 3) @[el2_ifu_compress_ctl.scala 12:90]
node _T_984 = eq(_T_983, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_985 = bits(io.din, 2, 2) @[el2_ifu_compress_ctl.scala 12:90]
node _T_986 = eq(_T_985, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_987 = bits(io.din, 1, 1) @[el2_ifu_compress_ctl.scala 12:71]
node _T_988 = and(_T_974, _T_975) @[el2_ifu_compress_ctl.scala 12:110]
node _T_989 = and(_T_988, _T_976) @[el2_ifu_compress_ctl.scala 12:110]
node _T_990 = and(_T_989, _T_978) @[el2_ifu_compress_ctl.scala 12:110]
node _T_991 = and(_T_990, _T_980) @[el2_ifu_compress_ctl.scala 12:110]
node _T_992 = and(_T_991, _T_982) @[el2_ifu_compress_ctl.scala 12:110]
node _T_993 = and(_T_992, _T_984) @[el2_ifu_compress_ctl.scala 12:110]
node _T_994 = and(_T_993, _T_986) @[el2_ifu_compress_ctl.scala 12:110]
node _T_995 = and(_T_994, _T_987) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node _T_996 = or(_T_972, _T_995) @[el2_ifu_compress_ctl.scala 83:42]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_997 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:90]
node _T_998 = eq(_T_997, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_999 = bits(io.din, 12, 12) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1000 = bits(io.din, 7, 7) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1001 = bits(io.din, 6, 6) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1002 = eq(_T_1001, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1003 = bits(io.din, 5, 5) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1004 = eq(_T_1003, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1005 = bits(io.din, 4, 4) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1006 = eq(_T_1005, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1007 = bits(io.din, 3, 3) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1008 = eq(_T_1007, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1009 = bits(io.din, 2, 2) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1010 = eq(_T_1009, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1011 = bits(io.din, 1, 1) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1012 = and(_T_998, _T_999) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1013 = and(_T_1012, _T_1000) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1014 = and(_T_1013, _T_1002) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1015 = and(_T_1014, _T_1004) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1016 = and(_T_1015, _T_1006) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1017 = and(_T_1016, _T_1008) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1018 = and(_T_1017, _T_1010) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1019 = and(_T_1018, _T_1011) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node _T_1020 = or(_T_996, _T_1019) @[el2_ifu_compress_ctl.scala 83:81]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_1021 = bits(io.din, 15, 15) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1022 = eq(_T_1021, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1023 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1024 = eq(_T_1023, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1025 = bits(io.din, 13, 13) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1026 = and(_T_1022, _T_1024) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1027 = and(_T_1026, _T_1025) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node rdeq1 = or(_T_1020, _T_1027) @[el2_ifu_compress_ctl.scala 84:42]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_1028 = bits(io.din, 15, 15) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1029 = eq(_T_1028, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1030 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1031 = bits(io.din, 13, 13) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1032 = bits(io.din, 11, 11) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1033 = eq(_T_1032, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1034 = bits(io.din, 10, 10) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1035 = eq(_T_1034, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1036 = bits(io.din, 9, 9) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1037 = eq(_T_1036, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1038 = bits(io.din, 8, 8) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1039 = bits(io.din, 7, 7) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1040 = eq(_T_1039, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1041 = and(_T_1029, _T_1030) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1042 = and(_T_1041, _T_1031) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1043 = and(_T_1042, _T_1033) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1044 = and(_T_1043, _T_1035) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1045 = and(_T_1044, _T_1037) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1046 = and(_T_1045, _T_1038) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1047 = and(_T_1046, _T_1040) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1048 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1049 = bits(io.din, 1, 1) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1050 = and(_T_1048, _T_1049) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node _T_1051 = or(_T_1047, _T_1050) @[el2_ifu_compress_ctl.scala 86:53]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_1052 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1053 = eq(_T_1052, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1054 = bits(io.din, 1, 1) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1055 = eq(_T_1054, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1056 = and(_T_1053, _T_1055) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node _T_1057 = bits(io.din, 0, 0) @[el2_ifu_compress_ctl.scala 86:100]
node _T_1058 = eq(_T_1057, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 86:93]
node _T_1059 = and(_T_1056, _T_1058) @[el2_ifu_compress_ctl.scala 86:91]
node rs1eq2 = or(_T_1051, _T_1059) @[el2_ifu_compress_ctl.scala 86:71]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_1060 = bits(io.din, 15, 15) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1061 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1062 = bits(io.din, 0, 0) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1063 = and(_T_1060, _T_1061) @[el2_ifu_compress_ctl.scala 12:110]
node sbroffset8_1 = and(_T_1063, _T_1062) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1064 = bits(io.din, 15, 15) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1065 = eq(_T_1064, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1066 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1067 = bits(io.din, 13, 13) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1068 = bits(io.din, 11, 11) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1069 = eq(_T_1068, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1070 = bits(io.din, 10, 10) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1071 = eq(_T_1070, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1072 = bits(io.din, 9, 9) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1073 = eq(_T_1072, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1074 = bits(io.din, 8, 8) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1075 = bits(io.din, 7, 7) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1076 = eq(_T_1075, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1077 = and(_T_1065, _T_1066) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1078 = and(_T_1077, _T_1067) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1079 = and(_T_1078, _T_1069) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1080 = and(_T_1079, _T_1071) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1081 = and(_T_1080, _T_1073) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1082 = and(_T_1081, _T_1074) @[el2_ifu_compress_ctl.scala 12:110]
node simm9_4 = and(_T_1082, _T_1076) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1083 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1084 = eq(_T_1083, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1085 = bits(io.din, 13, 13) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1086 = eq(_T_1085, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1087 = bits(io.din, 11, 11) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1088 = bits(io.din, 10, 10) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1089 = eq(_T_1088, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1090 = bits(io.din, 0, 0) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1091 = and(_T_1084, _T_1086) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1092 = and(_T_1091, _T_1087) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1093 = and(_T_1092, _T_1089) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1094 = and(_T_1093, _T_1090) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1095 = bits(io.din, 15, 15) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1096 = eq(_T_1095, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1097 = bits(io.din, 13, 13) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1098 = eq(_T_1097, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1099 = bits(io.din, 0, 0) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1100 = and(_T_1096, _T_1098) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1101 = and(_T_1100, _T_1099) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node simm5_0 = or(_T_1094, _T_1101) @[el2_ifu_compress_ctl.scala 92:45]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_1102 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1103 = eq(_T_1102, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1104 = bits(io.din, 13, 13) @[el2_ifu_compress_ctl.scala 12:71]
node sjaloffset11_1 = and(_T_1103, _T_1104) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1105 = bits(io.din, 15, 15) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1106 = eq(_T_1105, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1107 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1108 = bits(io.din, 13, 13) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1109 = bits(io.din, 7, 7) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1110 = and(_T_1106, _T_1107) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1111 = and(_T_1110, _T_1108) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1112 = and(_T_1111, _T_1109) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1113 = bits(io.din, 15, 15) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1114 = eq(_T_1113, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1115 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1116 = bits(io.din, 13, 13) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1117 = bits(io.din, 8, 8) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1118 = eq(_T_1117, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1119 = and(_T_1114, _T_1115) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1120 = and(_T_1119, _T_1116) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1121 = and(_T_1120, _T_1118) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node _T_1122 = or(_T_1112, _T_1121) @[el2_ifu_compress_ctl.scala 96:44]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_1123 = bits(io.din, 15, 15) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1124 = eq(_T_1123, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1125 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1126 = bits(io.din, 13, 13) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1127 = bits(io.din, 9, 9) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1128 = and(_T_1124, _T_1125) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1129 = and(_T_1128, _T_1126) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1130 = and(_T_1129, _T_1127) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node _T_1131 = or(_T_1122, _T_1130) @[el2_ifu_compress_ctl.scala 96:70]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_1132 = bits(io.din, 15, 15) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1133 = eq(_T_1132, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1134 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1135 = bits(io.din, 13, 13) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1136 = bits(io.din, 10, 10) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1137 = and(_T_1133, _T_1134) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1138 = and(_T_1137, _T_1135) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1139 = and(_T_1138, _T_1136) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node _T_1140 = or(_T_1131, _T_1139) @[el2_ifu_compress_ctl.scala 96:95]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_1141 = bits(io.din, 15, 15) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1142 = eq(_T_1141, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1143 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1144 = bits(io.din, 13, 13) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1145 = bits(io.din, 11, 11) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1146 = and(_T_1142, _T_1143) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1147 = and(_T_1146, _T_1144) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1148 = and(_T_1147, _T_1145) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node sluimm17_12 = or(_T_1140, _T_1148) @[el2_ifu_compress_ctl.scala 96:121]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_1149 = bits(io.din, 15, 15) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1150 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1151 = eq(_T_1150, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1152 = bits(io.din, 13, 13) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1153 = eq(_T_1152, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1154 = bits(io.din, 11, 11) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1155 = eq(_T_1154, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1156 = bits(io.din, 0, 0) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1157 = and(_T_1149, _T_1151) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1158 = and(_T_1157, _T_1153) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1159 = and(_T_1158, _T_1155) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1160 = and(_T_1159, _T_1156) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1161 = bits(io.din, 15, 15) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1162 = eq(_T_1161, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1163 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1164 = eq(_T_1163, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1165 = bits(io.din, 1, 1) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1166 = and(_T_1162, _T_1164) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1167 = and(_T_1166, _T_1165) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node uimm5_0 = or(_T_1160, _T_1167) @[el2_ifu_compress_ctl.scala 98:45]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_1168 = bits(io.din, 15, 15) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1169 = bits(io.din, 1, 1) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1170 = eq(_T_1169, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1171 = and(_T_1168, _T_1170) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node _T_1172 = bits(io.din, 0, 0) @[el2_ifu_compress_ctl.scala 100:44]
node _T_1173 = eq(_T_1172, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 100:37]
node uswimm6_2 = and(_T_1171, _T_1173) @[el2_ifu_compress_ctl.scala 100:35]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_1174 = bits(io.din, 15, 15) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1175 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1176 = bits(io.din, 1, 1) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1177 = and(_T_1174, _T_1175) @[el2_ifu_compress_ctl.scala 12:110]
node uswspimm7_2 = and(_T_1177, _T_1176) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1178 = cat(out[2], out[1]) @[Cat.scala 29:58]
node _T_1179 = cat(_T_1178, out[0]) @[Cat.scala 29:58]
node _T_1180 = cat(out[4], out[3]) @[Cat.scala 29:58]
node _T_1181 = cat(out[6], out[5]) @[Cat.scala 29:58]
node _T_1182 = cat(_T_1181, _T_1180) @[Cat.scala 29:58]
node l1_6 = cat(_T_1182, _T_1179) @[Cat.scala 29:58]
node _T_1183 = cat(out[8], out[7]) @[Cat.scala 29:58]
node _T_1184 = cat(out[11], out[10]) @[Cat.scala 29:58]
node _T_1185 = cat(_T_1184, out[9]) @[Cat.scala 29:58]
node _T_1186 = cat(_T_1185, _T_1183) @[Cat.scala 29:58]
Aligner
2020-10-07 17:21:03 +08:00
node _T_1187 = bits(rdrd, 0, 0) @[el2_ifu_compress_ctl.scala 106:81]
node _T_1188 = bits(rdprd, 0, 0) @[el2_ifu_compress_ctl.scala 107:9]
node _T_1189 = bits(rs2prd, 0, 0) @[el2_ifu_compress_ctl.scala 107:30]
node _T_1190 = bits(rdeq1, 0, 0) @[el2_ifu_compress_ctl.scala 107:51]
node _T_1191 = bits(rdeq2, 0, 0) @[el2_ifu_compress_ctl.scala 107:75]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_1192 = mux(_T_1187, rdd, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1193 = mux(_T_1188, rdpd, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1194 = mux(_T_1189, rs2pd, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1195 = mux(_T_1190, UInt<5>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1196 = mux(_T_1191, UInt<5>("h02"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1197 = or(_T_1192, _T_1193) @[Mux.scala 27:72]
node _T_1198 = or(_T_1197, _T_1194) @[Mux.scala 27:72]
node _T_1199 = or(_T_1198, _T_1195) @[Mux.scala 27:72]
node _T_1200 = or(_T_1199, _T_1196) @[Mux.scala 27:72]
wire _T_1201 : UInt<5> @[Mux.scala 27:72]
_T_1201 <= _T_1200 @[Mux.scala 27:72]
Aligner
2020-10-07 17:21:03 +08:00
node l1_11 = or(_T_1186, _T_1201) @[el2_ifu_compress_ctl.scala 106:64]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_1202 = cat(out[14], out[13]) @[Cat.scala 29:58]
node l1_14 = cat(_T_1202, out[12]) @[Cat.scala 29:58]
node _T_1203 = cat(out[16], out[15]) @[Cat.scala 29:58]
node _T_1204 = cat(out[19], out[18]) @[Cat.scala 29:58]
node _T_1205 = cat(_T_1204, out[17]) @[Cat.scala 29:58]
node _T_1206 = cat(_T_1205, _T_1203) @[Cat.scala 29:58]
Aligner
2020-10-07 17:21:03 +08:00
node _T_1207 = bits(rdrs1, 0, 0) @[el2_ifu_compress_ctl.scala 111:85]
node _T_1208 = bits(rdprs1, 0, 0) @[el2_ifu_compress_ctl.scala 112:12]
node _T_1209 = bits(rs1eq2, 0, 0) @[el2_ifu_compress_ctl.scala 112:33]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_1210 = mux(_T_1207, rdd, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1211 = mux(_T_1208, rdpd, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1212 = mux(_T_1209, UInt<5>("h02"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1213 = or(_T_1210, _T_1211) @[Mux.scala 27:72]
node _T_1214 = or(_T_1213, _T_1212) @[Mux.scala 27:72]
wire _T_1215 : UInt<5> @[Mux.scala 27:72]
_T_1215 <= _T_1214 @[Mux.scala 27:72]
Aligner
2020-10-07 17:21:03 +08:00
node l1_19 = or(_T_1206, _T_1215) @[el2_ifu_compress_ctl.scala 111:67]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_1216 = cat(out[21], out[20]) @[Cat.scala 29:58]
node _T_1217 = cat(out[24], out[23]) @[Cat.scala 29:58]
node _T_1218 = cat(_T_1217, out[22]) @[Cat.scala 29:58]
node _T_1219 = cat(_T_1218, _T_1216) @[Cat.scala 29:58]
Aligner
2020-10-07 17:21:03 +08:00
node _T_1220 = bits(rs2rs2, 0, 0) @[el2_ifu_compress_ctl.scala 114:86]
node _T_1221 = bits(rs2prs2, 0, 0) @[el2_ifu_compress_ctl.scala 115:13]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_1222 = mux(_T_1220, rs2d, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1223 = mux(_T_1221, rs2pd, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1224 = or(_T_1222, _T_1223) @[Mux.scala 27:72]
wire _T_1225 : UInt<5> @[Mux.scala 27:72]
_T_1225 <= _T_1224 @[Mux.scala 27:72]
Aligner
2020-10-07 17:21:03 +08:00
node l1_24 = or(_T_1219, _T_1225) @[el2_ifu_compress_ctl.scala 114:67]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_1226 = cat(out[27], out[26]) @[Cat.scala 29:58]
node _T_1227 = cat(_T_1226, out[25]) @[Cat.scala 29:58]
node _T_1228 = cat(out[29], out[28]) @[Cat.scala 29:58]
node _T_1229 = cat(out[31], out[30]) @[Cat.scala 29:58]
node _T_1230 = cat(_T_1229, _T_1228) @[Cat.scala 29:58]
node l1_31 = cat(_T_1230, _T_1227) @[Cat.scala 29:58]
node _T_1231 = cat(l1_14, l1_11) @[Cat.scala 29:58]
node _T_1232 = cat(_T_1231, l1_6) @[Cat.scala 29:58]
node _T_1233 = cat(l1_31, l1_24) @[Cat.scala 29:58]
node _T_1234 = cat(_T_1233, l1_19) @[Cat.scala 29:58]
node l1 = cat(_T_1234, _T_1232) @[Cat.scala 29:58]
Aligner
2020-10-07 17:21:03 +08:00
node _T_1235 = bits(io.din, 12, 12) @[el2_ifu_compress_ctl.scala 121:26]
node _T_1236 = bits(io.din, 6, 2) @[el2_ifu_compress_ctl.scala 121:38]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node simm5d = cat(_T_1235, _T_1236) @[Cat.scala 29:58]
Aligner
2020-10-07 17:21:03 +08:00
node _T_1237 = bits(io.din, 10, 7) @[el2_ifu_compress_ctl.scala 122:26]
node _T_1238 = bits(io.din, 12, 11) @[el2_ifu_compress_ctl.scala 122:40]
node _T_1239 = bits(io.din, 5, 5) @[el2_ifu_compress_ctl.scala 122:55]
node _T_1240 = bits(io.din, 6, 6) @[el2_ifu_compress_ctl.scala 122:66]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_1241 = cat(_T_1239, _T_1240) @[Cat.scala 29:58]
node _T_1242 = cat(_T_1237, _T_1238) @[Cat.scala 29:58]
node uimm9d = cat(_T_1242, _T_1241) @[Cat.scala 29:58]
Aligner
2020-10-07 17:21:03 +08:00
node _T_1243 = bits(io.din, 12, 12) @[el2_ifu_compress_ctl.scala 123:26]
node _T_1244 = bits(io.din, 4, 3) @[el2_ifu_compress_ctl.scala 123:38]
node _T_1245 = bits(io.din, 5, 5) @[el2_ifu_compress_ctl.scala 123:51]
node _T_1246 = bits(io.din, 2, 2) @[el2_ifu_compress_ctl.scala 123:62]
node _T_1247 = bits(io.din, 6, 6) @[el2_ifu_compress_ctl.scala 123:73]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_1248 = cat(_T_1246, _T_1247) @[Cat.scala 29:58]
node _T_1249 = cat(_T_1243, _T_1244) @[Cat.scala 29:58]
node _T_1250 = cat(_T_1249, _T_1245) @[Cat.scala 29:58]
node simm9d = cat(_T_1250, _T_1248) @[Cat.scala 29:58]
Aligner
2020-10-07 17:21:03 +08:00
node _T_1251 = bits(io.din, 5, 5) @[el2_ifu_compress_ctl.scala 124:28]
node _T_1252 = bits(io.din, 12, 10) @[el2_ifu_compress_ctl.scala 124:39]
node _T_1253 = bits(io.din, 6, 6) @[el2_ifu_compress_ctl.scala 124:54]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_1254 = cat(_T_1251, _T_1252) @[Cat.scala 29:58]
node ulwimm6d = cat(_T_1254, _T_1253) @[Cat.scala 29:58]
Aligner
2020-10-07 17:21:03 +08:00
node _T_1255 = bits(io.din, 3, 2) @[el2_ifu_compress_ctl.scala 125:30]
node _T_1256 = bits(io.din, 12, 12) @[el2_ifu_compress_ctl.scala 125:43]
node _T_1257 = bits(io.din, 6, 4) @[el2_ifu_compress_ctl.scala 125:55]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_1258 = cat(_T_1255, _T_1256) @[Cat.scala 29:58]
node ulwspimm7d = cat(_T_1258, _T_1257) @[Cat.scala 29:58]
Aligner
2020-10-07 17:21:03 +08:00
node _T_1259 = bits(io.din, 12, 12) @[el2_ifu_compress_ctl.scala 126:26]
node _T_1260 = bits(io.din, 6, 2) @[el2_ifu_compress_ctl.scala 126:38]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node uimm5d = cat(_T_1259, _T_1260) @[Cat.scala 29:58]
Aligner
2020-10-07 17:21:03 +08:00
node _T_1261 = bits(io.din, 12, 12) @[el2_ifu_compress_ctl.scala 127:27]
node _T_1262 = bits(io.din, 8, 8) @[el2_ifu_compress_ctl.scala 127:39]
node _T_1263 = bits(io.din, 10, 9) @[el2_ifu_compress_ctl.scala 127:50]
node _T_1264 = bits(io.din, 6, 6) @[el2_ifu_compress_ctl.scala 127:64]
node _T_1265 = bits(io.din, 7, 7) @[el2_ifu_compress_ctl.scala 127:75]
node _T_1266 = bits(io.din, 2, 2) @[el2_ifu_compress_ctl.scala 127:86]
node _T_1267 = bits(io.din, 11, 11) @[el2_ifu_compress_ctl.scala 127:97]
node _T_1268 = bits(io.din, 5, 4) @[el2_ifu_compress_ctl.scala 128:11]
node _T_1269 = bits(io.din, 3, 3) @[el2_ifu_compress_ctl.scala 128:24]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_1270 = cat(_T_1268, _T_1269) @[Cat.scala 29:58]
node _T_1271 = cat(_T_1266, _T_1267) @[Cat.scala 29:58]
node _T_1272 = cat(_T_1271, _T_1270) @[Cat.scala 29:58]
node _T_1273 = cat(_T_1264, _T_1265) @[Cat.scala 29:58]
node _T_1274 = cat(_T_1261, _T_1262) @[Cat.scala 29:58]
node _T_1275 = cat(_T_1274, _T_1263) @[Cat.scala 29:58]
node _T_1276 = cat(_T_1275, _T_1273) @[Cat.scala 29:58]
node sjald_1 = cat(_T_1276, _T_1272) @[Cat.scala 29:58]
Aligner
2020-10-07 17:21:03 +08:00
node _T_1277 = bits(io.din, 12, 12) @[el2_ifu_compress_ctl.scala 129:32]
wire _T_1278 : UInt<1>[9] @[el2_lib.scala 161:48]
_T_1278[0] <= _T_1277 @[el2_lib.scala 161:48]
_T_1278[1] <= _T_1277 @[el2_lib.scala 161:48]
_T_1278[2] <= _T_1277 @[el2_lib.scala 161:48]
_T_1278[3] <= _T_1277 @[el2_lib.scala 161:48]
_T_1278[4] <= _T_1277 @[el2_lib.scala 161:48]
_T_1278[5] <= _T_1277 @[el2_lib.scala 161:48]
_T_1278[6] <= _T_1277 @[el2_lib.scala 161:48]
_T_1278[7] <= _T_1277 @[el2_lib.scala 161:48]
_T_1278[8] <= _T_1277 @[el2_lib.scala 161:48]
node _T_1279 = cat(_T_1278[0], _T_1278[1]) @[Cat.scala 29:58]
node _T_1280 = cat(_T_1279, _T_1278[2]) @[Cat.scala 29:58]
node _T_1281 = cat(_T_1280, _T_1278[3]) @[Cat.scala 29:58]
node _T_1282 = cat(_T_1281, _T_1278[4]) @[Cat.scala 29:58]
node _T_1283 = cat(_T_1282, _T_1278[5]) @[Cat.scala 29:58]
node _T_1284 = cat(_T_1283, _T_1278[6]) @[Cat.scala 29:58]
node _T_1285 = cat(_T_1284, _T_1278[7]) @[Cat.scala 29:58]
node sjald_12 = cat(_T_1285, _T_1278[8]) @[Cat.scala 29:58]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node sjald = cat(sjald_12, sjald_1) @[Cat.scala 29:58]
Aligner
2020-10-07 17:21:03 +08:00
node _T_1286 = bits(io.din, 12, 12) @[el2_ifu_compress_ctl.scala 131:36]
wire _T_1287 : UInt<1>[15] @[el2_lib.scala 161:48]
_T_1287[0] <= _T_1286 @[el2_lib.scala 161:48]
_T_1287[1] <= _T_1286 @[el2_lib.scala 161:48]
_T_1287[2] <= _T_1286 @[el2_lib.scala 161:48]
_T_1287[3] <= _T_1286 @[el2_lib.scala 161:48]
_T_1287[4] <= _T_1286 @[el2_lib.scala 161:48]
_T_1287[5] <= _T_1286 @[el2_lib.scala 161:48]
_T_1287[6] <= _T_1286 @[el2_lib.scala 161:48]
_T_1287[7] <= _T_1286 @[el2_lib.scala 161:48]
_T_1287[8] <= _T_1286 @[el2_lib.scala 161:48]
_T_1287[9] <= _T_1286 @[el2_lib.scala 161:48]
_T_1287[10] <= _T_1286 @[el2_lib.scala 161:48]
_T_1287[11] <= _T_1286 @[el2_lib.scala 161:48]
_T_1287[12] <= _T_1286 @[el2_lib.scala 161:48]
_T_1287[13] <= _T_1286 @[el2_lib.scala 161:48]
_T_1287[14] <= _T_1286 @[el2_lib.scala 161:48]
node _T_1288 = cat(_T_1287[0], _T_1287[1]) @[Cat.scala 29:58]
node _T_1289 = cat(_T_1288, _T_1287[2]) @[Cat.scala 29:58]
node _T_1290 = cat(_T_1289, _T_1287[3]) @[Cat.scala 29:58]
node _T_1291 = cat(_T_1290, _T_1287[4]) @[Cat.scala 29:58]
node _T_1292 = cat(_T_1291, _T_1287[5]) @[Cat.scala 29:58]
node _T_1293 = cat(_T_1292, _T_1287[6]) @[Cat.scala 29:58]
node _T_1294 = cat(_T_1293, _T_1287[7]) @[Cat.scala 29:58]
node _T_1295 = cat(_T_1294, _T_1287[8]) @[Cat.scala 29:58]
node _T_1296 = cat(_T_1295, _T_1287[9]) @[Cat.scala 29:58]
node _T_1297 = cat(_T_1296, _T_1287[10]) @[Cat.scala 29:58]
node _T_1298 = cat(_T_1297, _T_1287[11]) @[Cat.scala 29:58]
node _T_1299 = cat(_T_1298, _T_1287[12]) @[Cat.scala 29:58]
node _T_1300 = cat(_T_1299, _T_1287[13]) @[Cat.scala 29:58]
node _T_1301 = cat(_T_1300, _T_1287[14]) @[Cat.scala 29:58]
node _T_1302 = bits(io.din, 6, 2) @[el2_ifu_compress_ctl.scala 131:49]
node sluimmd = cat(_T_1301, _T_1302) @[Cat.scala 29:58]
node _T_1303 = bits(l1, 31, 20) @[el2_ifu_compress_ctl.scala 133:17]
node _T_1304 = bits(simm5_0, 0, 0) @[el2_ifu_compress_ctl.scala 134:23]
node _T_1305 = bits(simm5d, 5, 5) @[el2_ifu_compress_ctl.scala 134:49]
wire _T_1306 : UInt<1>[7] @[el2_lib.scala 161:48]
_T_1306[0] <= _T_1305 @[el2_lib.scala 161:48]
_T_1306[1] <= _T_1305 @[el2_lib.scala 161:48]
_T_1306[2] <= _T_1305 @[el2_lib.scala 161:48]
_T_1306[3] <= _T_1305 @[el2_lib.scala 161:48]
_T_1306[4] <= _T_1305 @[el2_lib.scala 161:48]
_T_1306[5] <= _T_1305 @[el2_lib.scala 161:48]
_T_1306[6] <= _T_1305 @[el2_lib.scala 161:48]
node _T_1307 = cat(_T_1306[0], _T_1306[1]) @[Cat.scala 29:58]
node _T_1308 = cat(_T_1307, _T_1306[2]) @[Cat.scala 29:58]
node _T_1309 = cat(_T_1308, _T_1306[3]) @[Cat.scala 29:58]
node _T_1310 = cat(_T_1309, _T_1306[4]) @[Cat.scala 29:58]
node _T_1311 = cat(_T_1310, _T_1306[5]) @[Cat.scala 29:58]
node _T_1312 = cat(_T_1311, _T_1306[6]) @[Cat.scala 29:58]
node _T_1313 = bits(simm5d, 4, 0) @[el2_ifu_compress_ctl.scala 134:61]
node _T_1314 = cat(_T_1312, _T_1313) @[Cat.scala 29:58]
node _T_1315 = bits(uimm9_2, 0, 0) @[el2_ifu_compress_ctl.scala 135:23]
node _T_1316 = cat(UInt<2>("h00"), uimm9d) @[Cat.scala 29:58]
node _T_1317 = cat(_T_1316, UInt<2>("h00")) @[Cat.scala 29:58]
node _T_1318 = bits(simm9_4, 0, 0) @[el2_ifu_compress_ctl.scala 136:23]
node _T_1319 = bits(simm9d, 5, 5) @[el2_ifu_compress_ctl.scala 136:49]
wire _T_1320 : UInt<1>[3] @[el2_lib.scala 161:48]
_T_1320[0] <= _T_1319 @[el2_lib.scala 161:48]
_T_1320[1] <= _T_1319 @[el2_lib.scala 161:48]
_T_1320[2] <= _T_1319 @[el2_lib.scala 161:48]
node _T_1321 = cat(_T_1320[0], _T_1320[1]) @[Cat.scala 29:58]
node _T_1322 = cat(_T_1321, _T_1320[2]) @[Cat.scala 29:58]
node _T_1323 = bits(simm9d, 4, 0) @[el2_ifu_compress_ctl.scala 136:61]
node _T_1324 = cat(_T_1322, _T_1323) @[Cat.scala 29:58]
node _T_1325 = cat(_T_1324, UInt<4>("h00")) @[Cat.scala 29:58]
node _T_1326 = bits(ulwimm6_2, 0, 0) @[el2_ifu_compress_ctl.scala 137:25]
node _T_1327 = cat(UInt<5>("h00"), ulwimm6d) @[Cat.scala 29:58]
node _T_1328 = cat(_T_1327, UInt<2>("h00")) @[Cat.scala 29:58]
node _T_1329 = bits(ulwspimm7_2, 0, 0) @[el2_ifu_compress_ctl.scala 138:27]
node _T_1330 = cat(UInt<4>("h00"), ulwspimm7d) @[Cat.scala 29:58]
node _T_1331 = cat(_T_1330, UInt<2>("h00")) @[Cat.scala 29:58]
node _T_1332 = bits(uimm5_0, 0, 0) @[el2_ifu_compress_ctl.scala 139:23]
node _T_1333 = cat(UInt<6>("h00"), uimm5d) @[Cat.scala 29:58]
node _T_1334 = bits(sjaloffset11_1, 0, 0) @[el2_ifu_compress_ctl.scala 140:30]
node _T_1335 = bits(sjald, 19, 19) @[el2_ifu_compress_ctl.scala 140:47]
node _T_1336 = bits(sjald, 9, 0) @[el2_ifu_compress_ctl.scala 140:58]
node _T_1337 = bits(sjald, 10, 10) @[el2_ifu_compress_ctl.scala 140:70]
node _T_1338 = cat(_T_1335, _T_1336) @[Cat.scala 29:58]
node _T_1339 = cat(_T_1338, _T_1337) @[Cat.scala 29:58]
node _T_1340 = bits(sluimm17_12, 0, 0) @[el2_ifu_compress_ctl.scala 141:27]
node _T_1341 = bits(sluimmd, 19, 8) @[el2_ifu_compress_ctl.scala 141:42]
node _T_1342 = mux(_T_1304, _T_1314, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1343 = mux(_T_1315, _T_1317, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1344 = mux(_T_1318, _T_1325, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1345 = mux(_T_1326, _T_1328, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1346 = mux(_T_1329, _T_1331, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1347 = mux(_T_1332, _T_1333, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1348 = mux(_T_1334, _T_1339, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1349 = mux(_T_1340, _T_1341, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1350 = or(_T_1342, _T_1343) @[Mux.scala 27:72]
node _T_1351 = or(_T_1350, _T_1344) @[Mux.scala 27:72]
node _T_1352 = or(_T_1351, _T_1345) @[Mux.scala 27:72]
node _T_1353 = or(_T_1352, _T_1346) @[Mux.scala 27:72]
node _T_1354 = or(_T_1353, _T_1347) @[Mux.scala 27:72]
node _T_1355 = or(_T_1354, _T_1348) @[Mux.scala 27:72]
node _T_1356 = or(_T_1355, _T_1349) @[Mux.scala 27:72]
wire _T_1357 : UInt<12> @[Mux.scala 27:72]
_T_1357 <= _T_1356 @[Mux.scala 27:72]
node l2_31 = or(_T_1303, _T_1357) @[el2_ifu_compress_ctl.scala 133:25]
node _T_1358 = bits(l1, 19, 12) @[el2_ifu_compress_ctl.scala 143:17]
node _T_1359 = bits(sjaloffset11_1, 0, 0) @[el2_ifu_compress_ctl.scala 143:52]
node _T_1360 = bits(sjald, 19, 12) @[el2_ifu_compress_ctl.scala 143:65]
node _T_1361 = bits(sluimm17_12, 0, 0) @[el2_ifu_compress_ctl.scala 144:49]
node _T_1362 = bits(sluimmd, 7, 0) @[el2_ifu_compress_ctl.scala 144:64]
node _T_1363 = mux(_T_1359, _T_1360, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1364 = mux(_T_1361, _T_1362, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1365 = or(_T_1363, _T_1364) @[Mux.scala 27:72]
wire _T_1366 : UInt<8> @[Mux.scala 27:72]
_T_1366 <= _T_1365 @[Mux.scala 27:72]
node l2_19 = or(_T_1358, _T_1366) @[el2_ifu_compress_ctl.scala 143:25]
node _T_1367 = bits(l1, 11, 0) @[el2_ifu_compress_ctl.scala 145:32]
node _T_1368 = cat(l2_31, l2_19) @[Cat.scala 29:58]
node l2 = cat(_T_1368, _T_1367) @[Cat.scala 29:58]
node _T_1369 = bits(io.din, 12, 12) @[el2_ifu_compress_ctl.scala 147:25]
node _T_1370 = bits(io.din, 6, 6) @[el2_ifu_compress_ctl.scala 147:36]
node _T_1371 = bits(io.din, 5, 5) @[el2_ifu_compress_ctl.scala 147:46]
node _T_1372 = bits(io.din, 2, 2) @[el2_ifu_compress_ctl.scala 147:56]
node _T_1373 = bits(io.din, 11, 11) @[el2_ifu_compress_ctl.scala 147:66]
node _T_1374 = bits(io.din, 10, 10) @[el2_ifu_compress_ctl.scala 147:77]
node _T_1375 = bits(io.din, 4, 4) @[el2_ifu_compress_ctl.scala 147:88]
node _T_1376 = bits(io.din, 3, 3) @[el2_ifu_compress_ctl.scala 147:98]
node _T_1377 = cat(_T_1376, UInt<1>("h00")) @[Cat.scala 29:58]
node _T_1378 = cat(_T_1374, _T_1375) @[Cat.scala 29:58]
node _T_1379 = cat(_T_1378, _T_1377) @[Cat.scala 29:58]
node _T_1380 = cat(_T_1372, _T_1373) @[Cat.scala 29:58]
node _T_1381 = cat(_T_1369, _T_1370) @[Cat.scala 29:58]
node _T_1382 = cat(_T_1381, _T_1371) @[Cat.scala 29:58]
node _T_1383 = cat(_T_1382, _T_1380) @[Cat.scala 29:58]
node sbr8d = cat(_T_1383, _T_1379) @[Cat.scala 29:58]
node _T_1384 = bits(io.din, 5, 5) @[el2_ifu_compress_ctl.scala 148:28]
node _T_1385 = bits(io.din, 12, 10) @[el2_ifu_compress_ctl.scala 148:39]
node _T_1386 = bits(io.din, 6, 6) @[el2_ifu_compress_ctl.scala 148:54]
node _T_1387 = cat(_T_1386, UInt<2>("h00")) @[Cat.scala 29:58]
node _T_1388 = cat(_T_1384, _T_1385) @[Cat.scala 29:58]
node uswimm6d = cat(_T_1388, _T_1387) @[Cat.scala 29:58]
node _T_1389 = bits(io.din, 8, 7) @[el2_ifu_compress_ctl.scala 149:30]
node _T_1390 = bits(io.din, 12, 9) @[el2_ifu_compress_ctl.scala 149:42]
node _T_1391 = cat(_T_1389, _T_1390) @[Cat.scala 29:58]
node uswspimm7d = cat(_T_1391, UInt<2>("h00")) @[Cat.scala 29:58]
node _T_1392 = bits(l2, 31, 25) @[el2_ifu_compress_ctl.scala 151:17]
node _T_1393 = bits(sbroffset8_1, 0, 0) @[el2_ifu_compress_ctl.scala 151:50]
node _T_1394 = bits(sbr8d, 8, 8) @[el2_ifu_compress_ctl.scala 151:74]
wire _T_1395 : UInt<1>[4] @[el2_lib.scala 161:48]
_T_1395[0] <= _T_1394 @[el2_lib.scala 161:48]
_T_1395[1] <= _T_1394 @[el2_lib.scala 161:48]
_T_1395[2] <= _T_1394 @[el2_lib.scala 161:48]
_T_1395[3] <= _T_1394 @[el2_lib.scala 161:48]
node _T_1396 = cat(_T_1395[0], _T_1395[1]) @[Cat.scala 29:58]
node _T_1397 = cat(_T_1396, _T_1395[2]) @[Cat.scala 29:58]
node _T_1398 = cat(_T_1397, _T_1395[3]) @[Cat.scala 29:58]
node _T_1399 = bits(sbr8d, 7, 5) @[el2_ifu_compress_ctl.scala 151:84]
node _T_1400 = cat(_T_1398, _T_1399) @[Cat.scala 29:58]
node _T_1401 = bits(uswimm6_2, 0, 0) @[el2_ifu_compress_ctl.scala 152:15]
node _T_1402 = bits(uswimm6d, 6, 5) @[el2_ifu_compress_ctl.scala 152:44]
node _T_1403 = cat(UInt<5>("h00"), _T_1402) @[Cat.scala 29:58]
node _T_1404 = bits(uswspimm7_2, 0, 0) @[el2_ifu_compress_ctl.scala 152:64]
node _T_1405 = bits(uswspimm7d, 7, 5) @[el2_ifu_compress_ctl.scala 152:95]
node _T_1406 = cat(UInt<4>("h00"), _T_1405) @[Cat.scala 29:58]
node _T_1407 = mux(_T_1393, _T_1400, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1408 = mux(_T_1401, _T_1403, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1409 = mux(_T_1404, _T_1406, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1410 = or(_T_1407, _T_1408) @[Mux.scala 27:72]
node _T_1411 = or(_T_1410, _T_1409) @[Mux.scala 27:72]
wire _T_1412 : UInt<7> @[Mux.scala 27:72]
_T_1412 <= _T_1411 @[Mux.scala 27:72]
node l3_31 = or(_T_1392, _T_1412) @[el2_ifu_compress_ctl.scala 151:25]
node l3_24 = bits(l2, 24, 12) @[el2_ifu_compress_ctl.scala 154:17]
node _T_1413 = bits(l2, 11, 7) @[el2_ifu_compress_ctl.scala 156:17]
node _T_1414 = bits(sbroffset8_1, 0, 0) @[el2_ifu_compress_ctl.scala 156:49]
node _T_1415 = bits(sbr8d, 4, 1) @[el2_ifu_compress_ctl.scala 156:66]
node _T_1416 = bits(sbr8d, 8, 8) @[el2_ifu_compress_ctl.scala 156:78]
node _T_1417 = cat(_T_1415, _T_1416) @[Cat.scala 29:58]
node _T_1418 = bits(uswimm6_2, 0, 0) @[el2_ifu_compress_ctl.scala 157:15]
node _T_1419 = bits(uswimm6d, 4, 0) @[el2_ifu_compress_ctl.scala 157:31]
node _T_1420 = bits(uswspimm7_2, 0, 0) @[el2_ifu_compress_ctl.scala 158:17]
node _T_1421 = bits(uswspimm7d, 4, 0) @[el2_ifu_compress_ctl.scala 158:35]
node _T_1422 = mux(_T_1414, _T_1417, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1423 = mux(_T_1418, _T_1419, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1424 = mux(_T_1420, _T_1421, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_1425 = or(_T_1422, _T_1423) @[Mux.scala 27:72]
node _T_1426 = or(_T_1425, _T_1424) @[Mux.scala 27:72]
wire _T_1427 : UInt<5> @[Mux.scala 27:72]
_T_1427 <= _T_1426 @[Mux.scala 27:72]
node l3_11 = or(_T_1413, _T_1427) @[el2_ifu_compress_ctl.scala 156:24]
node _T_1428 = bits(l2, 6, 0) @[el2_ifu_compress_ctl.scala 160:39]
node _T_1429 = cat(l3_11, _T_1428) @[Cat.scala 29:58]
node _T_1430 = cat(l3_31, l3_24) @[Cat.scala 29:58]
node l3 = cat(_T_1430, _T_1429) @[Cat.scala 29:58]
node _T_1431 = bits(io.din, 13, 13) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1432 = eq(_T_1431, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1433 = bits(io.din, 12, 12) @[el2_ifu_compress_ctl.scala 12:90]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_1434 = eq(_T_1433, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
Aligner
2020-10-07 17:21:03 +08:00
node _T_1435 = bits(io.din, 11, 11) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1436 = bits(io.din, 1, 1) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1437 = and(_T_1432, _T_1434) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1438 = and(_T_1437, _T_1435) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1439 = and(_T_1438, _T_1436) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1440 = bits(io.din, 0, 0) @[el2_ifu_compress_ctl.scala 162:48]
node _T_1441 = eq(_T_1440, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 162:41]
node _T_1442 = and(_T_1439, _T_1441) @[el2_ifu_compress_ctl.scala 162:39]
node _T_1443 = bits(io.din, 13, 13) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1444 = eq(_T_1443, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1445 = bits(io.din, 12, 12) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1446 = eq(_T_1445, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1447 = bits(io.din, 6, 6) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1448 = bits(io.din, 1, 1) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1449 = and(_T_1444, _T_1446) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1450 = and(_T_1449, _T_1447) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1451 = and(_T_1450, _T_1448) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1452 = bits(io.din, 0, 0) @[el2_ifu_compress_ctl.scala 162:88]
node _T_1453 = eq(_T_1452, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 162:81]
node _T_1454 = and(_T_1451, _T_1453) @[el2_ifu_compress_ctl.scala 162:79]
node _T_1455 = or(_T_1442, _T_1454) @[el2_ifu_compress_ctl.scala 162:54]
node _T_1456 = bits(io.din, 15, 15) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1457 = eq(_T_1456, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1458 = bits(io.din, 13, 13) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1459 = eq(_T_1458, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1460 = bits(io.din, 11, 11) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1461 = bits(io.din, 1, 1) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1462 = eq(_T_1461, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1463 = and(_T_1457, _T_1459) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1464 = and(_T_1463, _T_1460) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1465 = and(_T_1464, _T_1462) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1466 = or(_T_1455, _T_1465) @[el2_ifu_compress_ctl.scala 162:94]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_1467 = bits(io.din, 13, 13) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1468 = eq(_T_1467, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
Aligner
2020-10-07 17:21:03 +08:00
node _T_1469 = bits(io.din, 12, 12) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1470 = eq(_T_1469, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1471 = bits(io.din, 5, 5) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1472 = bits(io.din, 1, 1) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1473 = and(_T_1468, _T_1470) @[el2_ifu_compress_ctl.scala 12:110]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_1474 = and(_T_1473, _T_1471) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node _T_1475 = and(_T_1474, _T_1472) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1476 = bits(io.din, 0, 0) @[el2_ifu_compress_ctl.scala 163:64]
node _T_1477 = eq(_T_1476, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 163:57]
node _T_1478 = and(_T_1475, _T_1477) @[el2_ifu_compress_ctl.scala 163:55]
node _T_1479 = or(_T_1466, _T_1478) @[el2_ifu_compress_ctl.scala 163:30]
node _T_1480 = bits(io.din, 13, 13) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1481 = eq(_T_1480, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1482 = bits(io.din, 12, 12) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1483 = eq(_T_1482, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1484 = bits(io.din, 10, 10) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1485 = bits(io.din, 1, 1) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1486 = and(_T_1481, _T_1483) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1487 = and(_T_1486, _T_1484) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1488 = and(_T_1487, _T_1485) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1489 = bits(io.din, 0, 0) @[el2_ifu_compress_ctl.scala 163:105]
node _T_1490 = eq(_T_1489, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 163:98]
node _T_1491 = and(_T_1488, _T_1490) @[el2_ifu_compress_ctl.scala 163:96]
node _T_1492 = or(_T_1479, _T_1491) @[el2_ifu_compress_ctl.scala 163:70]
node _T_1493 = bits(io.din, 15, 15) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1494 = eq(_T_1493, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1495 = bits(io.din, 13, 13) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1496 = eq(_T_1495, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1497 = bits(io.din, 6, 6) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1498 = bits(io.din, 1, 1) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1499 = eq(_T_1498, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1500 = and(_T_1494, _T_1496) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1501 = and(_T_1500, _T_1497) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1502 = and(_T_1501, _T_1499) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1503 = or(_T_1492, _T_1502) @[el2_ifu_compress_ctl.scala 163:111]
node _T_1504 = bits(io.din, 15, 15) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1505 = bits(io.din, 12, 12) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1506 = eq(_T_1505, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1507 = bits(io.din, 1, 1) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1508 = eq(_T_1507, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1509 = bits(io.din, 0, 0) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1510 = and(_T_1504, _T_1506) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1511 = and(_T_1510, _T_1508) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1512 = and(_T_1511, _T_1509) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1513 = or(_T_1503, _T_1512) @[el2_ifu_compress_ctl.scala 164:29]
node _T_1514 = bits(io.din, 13, 13) @[el2_ifu_compress_ctl.scala 12:90]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_1515 = eq(_T_1514, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
Aligner
2020-10-07 17:21:03 +08:00
node _T_1516 = bits(io.din, 12, 12) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1517 = eq(_T_1516, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1518 = bits(io.din, 9, 9) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1519 = bits(io.din, 1, 1) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1520 = and(_T_1515, _T_1517) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1521 = and(_T_1520, _T_1518) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1522 = and(_T_1521, _T_1519) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1523 = bits(io.din, 0, 0) @[el2_ifu_compress_ctl.scala 164:88]
node _T_1524 = eq(_T_1523, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 164:81]
node _T_1525 = and(_T_1522, _T_1524) @[el2_ifu_compress_ctl.scala 164:79]
node _T_1526 = or(_T_1513, _T_1525) @[el2_ifu_compress_ctl.scala 164:54]
node _T_1527 = bits(io.din, 12, 12) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1528 = eq(_T_1527, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1529 = bits(io.din, 6, 6) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1530 = bits(io.din, 1, 1) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1531 = eq(_T_1530, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1532 = bits(io.din, 0, 0) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1533 = and(_T_1528, _T_1529) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1534 = and(_T_1533, _T_1531) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1535 = and(_T_1534, _T_1532) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1536 = or(_T_1526, _T_1535) @[el2_ifu_compress_ctl.scala 164:94]
node _T_1537 = bits(io.din, 15, 15) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1538 = eq(_T_1537, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1539 = bits(io.din, 13, 13) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1540 = eq(_T_1539, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1541 = bits(io.din, 5, 5) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1542 = bits(io.din, 1, 1) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1543 = eq(_T_1542, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1544 = and(_T_1538, _T_1540) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1545 = and(_T_1544, _T_1541) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1546 = and(_T_1545, _T_1543) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1547 = or(_T_1536, _T_1546) @[el2_ifu_compress_ctl.scala 164:118]
node _T_1548 = bits(io.din, 13, 13) @[el2_ifu_compress_ctl.scala 12:90]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_1549 = eq(_T_1548, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
Aligner
2020-10-07 17:21:03 +08:00
node _T_1550 = bits(io.din, 12, 12) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1551 = eq(_T_1550, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1552 = bits(io.din, 8, 8) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1553 = bits(io.din, 1, 1) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1554 = and(_T_1549, _T_1551) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1555 = and(_T_1554, _T_1552) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1556 = and(_T_1555, _T_1553) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1557 = bits(io.din, 0, 0) @[el2_ifu_compress_ctl.scala 165:37]
node _T_1558 = eq(_T_1557, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 165:30]
node _T_1559 = and(_T_1556, _T_1558) @[el2_ifu_compress_ctl.scala 165:28]
node _T_1560 = or(_T_1547, _T_1559) @[el2_ifu_compress_ctl.scala 164:144]
node _T_1561 = bits(io.din, 12, 12) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1562 = eq(_T_1561, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1563 = bits(io.din, 5, 5) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1564 = bits(io.din, 1, 1) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1565 = eq(_T_1564, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1566 = bits(io.din, 0, 0) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1567 = and(_T_1562, _T_1563) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1568 = and(_T_1567, _T_1565) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1569 = and(_T_1568, _T_1566) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1570 = or(_T_1560, _T_1569) @[el2_ifu_compress_ctl.scala 165:43]
node _T_1571 = bits(io.din, 15, 15) @[el2_ifu_compress_ctl.scala 12:90]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_1572 = eq(_T_1571, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
Aligner
2020-10-07 17:21:03 +08:00
node _T_1573 = bits(io.din, 13, 13) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1574 = eq(_T_1573, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1575 = bits(io.din, 10, 10) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1576 = bits(io.din, 1, 1) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1577 = eq(_T_1576, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1578 = and(_T_1572, _T_1574) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1579 = and(_T_1578, _T_1575) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1580 = and(_T_1579, _T_1577) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1581 = or(_T_1570, _T_1580) @[el2_ifu_compress_ctl.scala 165:67]
node _T_1582 = bits(io.din, 13, 13) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1583 = eq(_T_1582, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1584 = bits(io.din, 12, 12) @[el2_ifu_compress_ctl.scala 12:90]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_1585 = eq(_T_1584, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
Aligner
2020-10-07 17:21:03 +08:00
node _T_1586 = bits(io.din, 7, 7) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1587 = bits(io.din, 1, 1) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1588 = and(_T_1583, _T_1585) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1589 = and(_T_1588, _T_1586) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1590 = and(_T_1589, _T_1587) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1591 = bits(io.din, 0, 0) @[el2_ifu_compress_ctl.scala 166:37]
node _T_1592 = eq(_T_1591, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 166:30]
node _T_1593 = and(_T_1590, _T_1592) @[el2_ifu_compress_ctl.scala 166:28]
node _T_1594 = or(_T_1581, _T_1593) @[el2_ifu_compress_ctl.scala 165:94]
node _T_1595 = bits(io.din, 12, 12) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1596 = bits(io.din, 11, 11) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1597 = bits(io.din, 10, 10) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1598 = eq(_T_1597, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1599 = bits(io.din, 1, 1) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1600 = eq(_T_1599, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1601 = bits(io.din, 0, 0) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1602 = and(_T_1595, _T_1596) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1603 = and(_T_1602, _T_1598) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1604 = and(_T_1603, _T_1600) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1605 = and(_T_1604, _T_1601) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1606 = or(_T_1594, _T_1605) @[el2_ifu_compress_ctl.scala 166:43]
node _T_1607 = bits(io.din, 15, 15) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1608 = eq(_T_1607, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1609 = bits(io.din, 13, 13) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1610 = eq(_T_1609, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1611 = bits(io.din, 9, 9) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1612 = bits(io.din, 1, 1) @[el2_ifu_compress_ctl.scala 12:90]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_1613 = eq(_T_1612, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
Aligner
2020-10-07 17:21:03 +08:00
node _T_1614 = and(_T_1608, _T_1610) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1615 = and(_T_1614, _T_1611) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1616 = and(_T_1615, _T_1613) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1617 = or(_T_1606, _T_1616) @[el2_ifu_compress_ctl.scala 166:71]
node _T_1618 = bits(io.din, 13, 13) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1619 = eq(_T_1618, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1620 = bits(io.din, 12, 12) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1621 = eq(_T_1620, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1622 = bits(io.din, 4, 4) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1623 = bits(io.din, 1, 1) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1624 = and(_T_1619, _T_1621) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1625 = and(_T_1624, _T_1622) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1626 = and(_T_1625, _T_1623) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1627 = bits(io.din, 0, 0) @[el2_ifu_compress_ctl.scala 167:37]
node _T_1628 = eq(_T_1627, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 167:30]
node _T_1629 = and(_T_1626, _T_1628) @[el2_ifu_compress_ctl.scala 167:28]
node _T_1630 = or(_T_1617, _T_1629) @[el2_ifu_compress_ctl.scala 166:97]
node _T_1631 = bits(io.din, 13, 13) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1632 = bits(io.din, 12, 12) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1633 = bits(io.din, 1, 1) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1634 = eq(_T_1633, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1635 = bits(io.din, 0, 0) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1636 = and(_T_1631, _T_1632) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1637 = and(_T_1636, _T_1634) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1638 = and(_T_1637, _T_1635) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1639 = or(_T_1630, _T_1638) @[el2_ifu_compress_ctl.scala 167:43]
node _T_1640 = bits(io.din, 15, 15) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1641 = eq(_T_1640, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1642 = bits(io.din, 13, 13) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1643 = eq(_T_1642, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1644 = bits(io.din, 8, 8) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1645 = bits(io.din, 1, 1) @[el2_ifu_compress_ctl.scala 12:90]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_1646 = eq(_T_1645, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
Aligner
2020-10-07 17:21:03 +08:00
node _T_1647 = and(_T_1641, _T_1643) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1648 = and(_T_1647, _T_1644) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1649 = and(_T_1648, _T_1646) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1650 = or(_T_1639, _T_1649) @[el2_ifu_compress_ctl.scala 167:67]
node _T_1651 = bits(io.din, 13, 13) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1652 = eq(_T_1651, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1653 = bits(io.din, 12, 12) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1654 = eq(_T_1653, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1655 = bits(io.din, 3, 3) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1656 = bits(io.din, 1, 1) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1657 = and(_T_1652, _T_1654) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1658 = and(_T_1657, _T_1655) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1659 = and(_T_1658, _T_1656) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1660 = bits(io.din, 0, 0) @[el2_ifu_compress_ctl.scala 168:37]
node _T_1661 = eq(_T_1660, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 168:30]
node _T_1662 = and(_T_1659, _T_1661) @[el2_ifu_compress_ctl.scala 168:28]
node _T_1663 = or(_T_1650, _T_1662) @[el2_ifu_compress_ctl.scala 167:93]
node _T_1664 = bits(io.din, 13, 13) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1665 = bits(io.din, 4, 4) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1666 = bits(io.din, 1, 1) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1667 = eq(_T_1666, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1668 = bits(io.din, 0, 0) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1669 = and(_T_1664, _T_1665) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1670 = and(_T_1669, _T_1667) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1671 = and(_T_1670, _T_1668) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1672 = or(_T_1663, _T_1671) @[el2_ifu_compress_ctl.scala 168:43]
node _T_1673 = bits(io.din, 13, 13) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1674 = eq(_T_1673, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1675 = bits(io.din, 12, 12) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1676 = eq(_T_1675, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1677 = bits(io.din, 2, 2) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1678 = bits(io.din, 1, 1) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1679 = and(_T_1674, _T_1676) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1680 = and(_T_1679, _T_1677) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1681 = and(_T_1680, _T_1678) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1682 = bits(io.din, 0, 0) @[el2_ifu_compress_ctl.scala 168:100]
node _T_1683 = eq(_T_1682, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 168:93]
node _T_1684 = and(_T_1681, _T_1683) @[el2_ifu_compress_ctl.scala 168:91]
node _T_1685 = or(_T_1672, _T_1684) @[el2_ifu_compress_ctl.scala 168:66]
node _T_1686 = bits(io.din, 15, 15) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1687 = eq(_T_1686, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_1688 = bits(io.din, 13, 13) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1689 = eq(_T_1688, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
Aligner
2020-10-07 17:21:03 +08:00
node _T_1690 = bits(io.din, 7, 7) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1691 = bits(io.din, 1, 1) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1692 = eq(_T_1691, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1693 = and(_T_1687, _T_1689) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1694 = and(_T_1693, _T_1690) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1695 = and(_T_1694, _T_1692) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1696 = or(_T_1685, _T_1695) @[el2_ifu_compress_ctl.scala 168:106]
node _T_1697 = bits(io.din, 13, 13) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1698 = bits(io.din, 3, 3) @[el2_ifu_compress_ctl.scala 12:71]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_1699 = bits(io.din, 1, 1) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1700 = eq(_T_1699, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1701 = bits(io.din, 0, 0) @[el2_ifu_compress_ctl.scala 12:71]
Aligner
2020-10-07 17:21:03 +08:00
node _T_1702 = and(_T_1697, _T_1698) @[el2_ifu_compress_ctl.scala 12:110]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_1703 = and(_T_1702, _T_1700) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1704 = and(_T_1703, _T_1701) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node _T_1705 = or(_T_1696, _T_1704) @[el2_ifu_compress_ctl.scala 169:29]
node _T_1706 = bits(io.din, 13, 13) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1707 = bits(io.din, 2, 2) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1708 = bits(io.din, 1, 1) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1709 = eq(_T_1708, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1710 = bits(io.din, 0, 0) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1711 = and(_T_1706, _T_1707) @[el2_ifu_compress_ctl.scala 12:110]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_1712 = and(_T_1711, _T_1709) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1713 = and(_T_1712, _T_1710) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node _T_1714 = or(_T_1705, _T_1713) @[el2_ifu_compress_ctl.scala 169:52]
node _T_1715 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1716 = bits(io.din, 13, 13) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1717 = eq(_T_1716, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1718 = bits(io.din, 1, 1) @[el2_ifu_compress_ctl.scala 12:90]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_1719 = eq(_T_1718, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
Aligner
2020-10-07 17:21:03 +08:00
node _T_1720 = and(_T_1715, _T_1717) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1721 = and(_T_1720, _T_1719) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1722 = or(_T_1714, _T_1721) @[el2_ifu_compress_ctl.scala 169:75]
node _T_1723 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1724 = eq(_T_1723, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1725 = bits(io.din, 12, 12) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1726 = eq(_T_1725, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1727 = bits(io.din, 1, 1) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1728 = eq(_T_1727, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1729 = bits(io.din, 0, 0) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1730 = and(_T_1724, _T_1726) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1731 = and(_T_1730, _T_1728) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1732 = and(_T_1731, _T_1729) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1733 = or(_T_1722, _T_1732) @[el2_ifu_compress_ctl.scala 169:98]
node _T_1734 = bits(io.din, 15, 15) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1735 = bits(io.din, 13, 13) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1736 = eq(_T_1735, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1737 = bits(io.din, 12, 12) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1738 = bits(io.din, 1, 1) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1739 = and(_T_1734, _T_1736) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1740 = and(_T_1739, _T_1737) @[el2_ifu_compress_ctl.scala 12:110]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
node _T_1741 = and(_T_1740, _T_1738) @[el2_ifu_compress_ctl.scala 12:110]
Aligner
2020-10-07 17:21:03 +08:00
node _T_1742 = bits(io.din, 0, 0) @[el2_ifu_compress_ctl.scala 170:63]
node _T_1743 = eq(_T_1742, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 170:56]
node _T_1744 = and(_T_1741, _T_1743) @[el2_ifu_compress_ctl.scala 170:54]
node _T_1745 = or(_T_1733, _T_1744) @[el2_ifu_compress_ctl.scala 170:29]
node _T_1746 = bits(io.din, 15, 15) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1747 = eq(_T_1746, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1748 = bits(io.din, 13, 13) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1749 = eq(_T_1748, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1750 = bits(io.din, 12, 12) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1751 = eq(_T_1750, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1752 = bits(io.din, 1, 1) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1753 = and(_T_1747, _T_1749) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1754 = and(_T_1753, _T_1751) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1755 = and(_T_1754, _T_1752) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1756 = bits(io.din, 0, 0) @[el2_ifu_compress_ctl.scala 170:105]
node _T_1757 = eq(_T_1756, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 170:98]
node _T_1758 = and(_T_1755, _T_1757) @[el2_ifu_compress_ctl.scala 170:96]
node _T_1759 = or(_T_1745, _T_1758) @[el2_ifu_compress_ctl.scala 170:69]
node _T_1760 = bits(io.din, 15, 15) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1761 = eq(_T_1760, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1762 = bits(io.din, 13, 13) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1763 = eq(_T_1762, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1764 = bits(io.din, 12, 12) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1765 = bits(io.din, 1, 1) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1766 = eq(_T_1765, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1767 = and(_T_1761, _T_1763) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1768 = and(_T_1767, _T_1764) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1769 = and(_T_1768, _T_1766) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1770 = or(_T_1759, _T_1769) @[el2_ifu_compress_ctl.scala 170:111]
node _T_1771 = bits(io.din, 14, 14) @[el2_ifu_compress_ctl.scala 12:71]
node _T_1772 = bits(io.din, 13, 13) @[el2_ifu_compress_ctl.scala 12:90]
node _T_1773 = eq(_T_1772, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 12:83]
node _T_1774 = and(_T_1771, _T_1773) @[el2_ifu_compress_ctl.scala 12:110]
node _T_1775 = bits(io.din, 0, 0) @[el2_ifu_compress_ctl.scala 171:59]
node _T_1776 = eq(_T_1775, UInt<1>("h00")) @[el2_ifu_compress_ctl.scala 171:52]
node _T_1777 = and(_T_1774, _T_1776) @[el2_ifu_compress_ctl.scala 171:50]
node legal = or(_T_1770, _T_1777) @[el2_ifu_compress_ctl.scala 171:30]
wire _T_1778 : UInt<1>[32] @[el2_lib.scala 161:48]
_T_1778[0] <= legal @[el2_lib.scala 161:48]
_T_1778[1] <= legal @[el2_lib.scala 161:48]
_T_1778[2] <= legal @[el2_lib.scala 161:48]
_T_1778[3] <= legal @[el2_lib.scala 161:48]
_T_1778[4] <= legal @[el2_lib.scala 161:48]
_T_1778[5] <= legal @[el2_lib.scala 161:48]
_T_1778[6] <= legal @[el2_lib.scala 161:48]
_T_1778[7] <= legal @[el2_lib.scala 161:48]
_T_1778[8] <= legal @[el2_lib.scala 161:48]
_T_1778[9] <= legal @[el2_lib.scala 161:48]
_T_1778[10] <= legal @[el2_lib.scala 161:48]
_T_1778[11] <= legal @[el2_lib.scala 161:48]
_T_1778[12] <= legal @[el2_lib.scala 161:48]
_T_1778[13] <= legal @[el2_lib.scala 161:48]
_T_1778[14] <= legal @[el2_lib.scala 161:48]
_T_1778[15] <= legal @[el2_lib.scala 161:48]
_T_1778[16] <= legal @[el2_lib.scala 161:48]
_T_1778[17] <= legal @[el2_lib.scala 161:48]
_T_1778[18] <= legal @[el2_lib.scala 161:48]
_T_1778[19] <= legal @[el2_lib.scala 161:48]
_T_1778[20] <= legal @[el2_lib.scala 161:48]
_T_1778[21] <= legal @[el2_lib.scala 161:48]
_T_1778[22] <= legal @[el2_lib.scala 161:48]
_T_1778[23] <= legal @[el2_lib.scala 161:48]
_T_1778[24] <= legal @[el2_lib.scala 161:48]
_T_1778[25] <= legal @[el2_lib.scala 161:48]
_T_1778[26] <= legal @[el2_lib.scala 161:48]
_T_1778[27] <= legal @[el2_lib.scala 161:48]
_T_1778[28] <= legal @[el2_lib.scala 161:48]
_T_1778[29] <= legal @[el2_lib.scala 161:48]
_T_1778[30] <= legal @[el2_lib.scala 161:48]
_T_1778[31] <= legal @[el2_lib.scala 161:48]
node _T_1779 = cat(_T_1778[0], _T_1778[1]) @[Cat.scala 29:58]
node _T_1780 = cat(_T_1779, _T_1778[2]) @[Cat.scala 29:58]
node _T_1781 = cat(_T_1780, _T_1778[3]) @[Cat.scala 29:58]
node _T_1782 = cat(_T_1781, _T_1778[4]) @[Cat.scala 29:58]
node _T_1783 = cat(_T_1782, _T_1778[5]) @[Cat.scala 29:58]
node _T_1784 = cat(_T_1783, _T_1778[6]) @[Cat.scala 29:58]
node _T_1785 = cat(_T_1784, _T_1778[7]) @[Cat.scala 29:58]
node _T_1786 = cat(_T_1785, _T_1778[8]) @[Cat.scala 29:58]
node _T_1787 = cat(_T_1786, _T_1778[9]) @[Cat.scala 29:58]
node _T_1788 = cat(_T_1787, _T_1778[10]) @[Cat.scala 29:58]
node _T_1789 = cat(_T_1788, _T_1778[11]) @[Cat.scala 29:58]
node _T_1790 = cat(_T_1789, _T_1778[12]) @[Cat.scala 29:58]
node _T_1791 = cat(_T_1790, _T_1778[13]) @[Cat.scala 29:58]
node _T_1792 = cat(_T_1791, _T_1778[14]) @[Cat.scala 29:58]
node _T_1793 = cat(_T_1792, _T_1778[15]) @[Cat.scala 29:58]
node _T_1794 = cat(_T_1793, _T_1778[16]) @[Cat.scala 29:58]
node _T_1795 = cat(_T_1794, _T_1778[17]) @[Cat.scala 29:58]
node _T_1796 = cat(_T_1795, _T_1778[18]) @[Cat.scala 29:58]
node _T_1797 = cat(_T_1796, _T_1778[19]) @[Cat.scala 29:58]
node _T_1798 = cat(_T_1797, _T_1778[20]) @[Cat.scala 29:58]
node _T_1799 = cat(_T_1798, _T_1778[21]) @[Cat.scala 29:58]
node _T_1800 = cat(_T_1799, _T_1778[22]) @[Cat.scala 29:58]
node _T_1801 = cat(_T_1800, _T_1778[23]) @[Cat.scala 29:58]
node _T_1802 = cat(_T_1801, _T_1778[24]) @[Cat.scala 29:58]
node _T_1803 = cat(_T_1802, _T_1778[25]) @[Cat.scala 29:58]
node _T_1804 = cat(_T_1803, _T_1778[26]) @[Cat.scala 29:58]
node _T_1805 = cat(_T_1804, _T_1778[27]) @[Cat.scala 29:58]
node _T_1806 = cat(_T_1805, _T_1778[28]) @[Cat.scala 29:58]
node _T_1807 = cat(_T_1806, _T_1778[29]) @[Cat.scala 29:58]
node _T_1808 = cat(_T_1807, _T_1778[30]) @[Cat.scala 29:58]
node _T_1809 = cat(_T_1808, _T_1778[31]) @[Cat.scala 29:58]
node _T_1810 = and(l3, _T_1809) @[el2_ifu_compress_ctl.scala 173:16]
io.dout <= _T_1810 @[el2_ifu_compress_ctl.scala 173:10]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
Aligner done
2020-09-23 18:27:02 +08:00
module el2_ifu_aln_ctl :
input clock : Clock
input reset : UInt<1>
ALN 1st attempt
2020-10-01 17:49:02 +08:00
output io : {flip scan_mode : UInt<1>, flip active_clk : Clock, flip ifu_async_error_start : UInt<1>, flip iccm_rd_ecc_double_err : UInt<1>, flip ic_access_fault_f : UInt<1>, flip ic_access_fault_type_f : UInt<2>, flip ifu_bp_fghr_f : UInt<8>, flip ifu_bp_btb_target_f : UInt<32>, flip ifu_bp_poffset_f : UInt<12>, flip ifu_bp_hist0_f : UInt<2>, flip ifu_bp_hist1_f : UInt<2>, flip ifu_bp_pc4_f : UInt<2>, flip ifu_bp_way_f : UInt<2>, flip ifu_bp_valid_f : UInt<2>, flip ifu_bp_ret_f : UInt<2>, flip exu_flush_final : UInt<1>, flip dec_i0_decode_d : UInt<1>, flip ifu_fetch_data_f : UInt<32>, flip ifu_fetch_val : UInt<2>, flip ifu_fetch_pc : UInt<32>, ifu_i0_valid : UInt<1>, ifu_i0_icaf : UInt<1>, ifu_i0_icaf_type : UInt<2>, ifu_i0_icaf_f1 : UInt<1>, ifu_i0_dbecc : UInt<1>, ifu_i0_instr : UInt<32>, ifu_i0_pc : UInt<32>, ifu_i0_pc4 : UInt<1>, ifu_fb_consume1 : UInt<1>, ifu_fb_consume2 : UInt<1>, ifu_i0_bp_index : UInt<7>, ifu_i0_bp_fghr : UInt<8>, ifu_i0_bp_btag : UInt<5>, ifu_pmu_instr_aligned : UInt<1>, ifu_i0_cinst : UInt<16>, i0_brp : {valid : UInt<1>, toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<32>, way : UInt<1>, ret : UInt<1>}}
Aligner done
2020-09-23 18:27:02 +08:00
wire error_stall_in : UInt<1>
error_stall_in <= UInt<1>("h00")
wire alignval : UInt<2>
alignval <= UInt<1>("h00")
wire q0final : UInt<16>
q0final <= UInt<1>("h00")
wire q1final : UInt<16>
q1final <= UInt<1>("h00")
wire wrptr_in : UInt<2>
wrptr_in <= UInt<1>("h00")
wire rdptr_in : UInt<2>
rdptr_in <= UInt<1>("h00")
wire f2val_in : UInt<2>
f2val_in <= UInt<1>("h00")
wire f1val_in : UInt<2>
f1val_in <= UInt<1>("h00")
wire f0val_in : UInt<2>
f0val_in <= UInt<1>("h00")
wire q2off_in : UInt<1>
q2off_in <= UInt<1>("h00")
wire q1off_in : UInt<1>
q1off_in <= UInt<1>("h00")
wire q0off_in : UInt<1>
q0off_in <= UInt<1>("h00")
wire sf0_valid : UInt<1>
sf0_valid <= UInt<1>("h00")
wire sf1_valid : UInt<1>
sf1_valid <= UInt<1>("h00")
wire f2_valid : UInt<1>
f2_valid <= UInt<1>("h00")
wire ifvalid : UInt<1>
ifvalid <= UInt<1>("h00")
wire shift_f2_f1 : UInt<1>
shift_f2_f1 <= UInt<1>("h00")
wire shift_f2_f0 : UInt<1>
shift_f2_f0 <= UInt<1>("h00")
wire shift_f1_f0 : UInt<1>
shift_f1_f0 <= UInt<1>("h00")
wire f0icaf : UInt<1>
f0icaf <= UInt<1>("h00")
wire f1icaf : UInt<1>
f1icaf <= UInt<1>("h00")
wire sf0val : UInt<2>
sf0val <= UInt<1>("h00")
wire sf1val : UInt<2>
sf1val <= UInt<1>("h00")
wire misc0 : UInt<54>
misc0 <= UInt<1>("h00")
wire misc1 : UInt<54>
misc1 <= UInt<1>("h00")
wire misc2 : UInt<54>
misc2 <= UInt<1>("h00")
wire brdata1 : UInt<12>
brdata1 <= UInt<1>("h00")
wire brdata0 : UInt<12>
brdata0 <= UInt<1>("h00")
wire brdata2 : UInt<12>
brdata2 <= UInt<1>("h00")
ALN 1st attempt
2020-10-01 17:49:02 +08:00
reg error_stall : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_aln_ctl.scala 89:54]
error_stall <= error_stall_in @[el2_ifu_aln_ctl.scala 89:54]
reg f0val : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_aln_ctl.scala 90:48]
f0val <= f0val_in @[el2_ifu_aln_ctl.scala 90:48]
node _T = or(error_stall, io.ifu_async_error_start) @[el2_ifu_aln_ctl.scala 91:34]
node _T_1 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 91:64]
node _T_2 = and(_T, _T_1) @[el2_ifu_aln_ctl.scala 91:62]
error_stall_in <= _T_2 @[el2_ifu_aln_ctl.scala 91:18]
node _T_3 = not(error_stall) @[el2_ifu_aln_ctl.scala 93:39]
node i0_shift = and(io.dec_i0_decode_d, _T_3) @[el2_ifu_aln_ctl.scala 93:37]
io.ifu_pmu_instr_aligned <= i0_shift @[el2_ifu_aln_ctl.scala 95:28]
node _T_4 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 97:34]
node _T_5 = bits(_T_4, 0, 0) @[el2_ifu_aln_ctl.scala 97:38]
node _T_6 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 97:64]
node _T_7 = not(_T_6) @[el2_ifu_aln_ctl.scala 97:58]
node _T_8 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 97:75]
node _T_9 = and(_T_7, _T_8) @[el2_ifu_aln_ctl.scala 97:68]
node _T_10 = bits(_T_9, 0, 0) @[el2_ifu_aln_ctl.scala 97:80]
Aligner done
2020-09-23 18:27:02 +08:00
node _T_11 = cat(q1final, q0final) @[Cat.scala 29:58]
node _T_12 = mux(_T_5, q0final, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_13 = mux(_T_10, _T_11, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_14 = or(_T_12, _T_13) @[Mux.scala 27:72]
wire aligndata : UInt<32> @[Mux.scala 27:72]
aligndata <= _T_14 @[Mux.scala 27:72]
ALN 1st attempt
2020-10-01 17:49:02 +08:00
inst decompressed of el2_ifu_compress_ctl @[el2_ifu_aln_ctl.scala 99:28]
ALN 1st attempt
2020-10-01 17:48:07 +08:00
decompressed.clock <= clock
decompressed.reset <= reset
ALN 1st attempt
2020-10-01 17:49:02 +08:00
decompressed.io.din <= aligndata @[el2_ifu_aln_ctl.scala 101:23]
io.ifu_i0_instr <= decompressed.io.dout @[el2_ifu_aln_ctl.scala 103:20]
node _T_15 = bits(aligndata, 15, 0) @[el2_ifu_aln_ctl.scala 106:31]
io.ifu_i0_cinst <= _T_15 @[el2_ifu_aln_ctl.scala 106:19]
Compressed
2020-09-27 04:49:55 +08:00
wire first4B : UInt<1>
first4B <= UInt<1>("h00")
ALN 1st attempt
2020-10-01 17:49:02 +08:00
node first2B = not(first4B) @[el2_ifu_aln_ctl.scala 111:17]
node _T_16 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 112:34]
node _T_17 = bits(_T_16, 0, 0) @[el2_ifu_aln_ctl.scala 112:38]
node _T_18 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 112:63]
node _T_19 = not(_T_18) @[el2_ifu_aln_ctl.scala 112:57]
node _T_20 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 112:74]
node _T_21 = and(_T_19, _T_20) @[el2_ifu_aln_ctl.scala 112:67]
node _T_22 = bits(_T_21, 0, 0) @[el2_ifu_aln_ctl.scala 112:79]
Aligner done
2020-09-23 18:27:02 +08:00
node _T_23 = cat(f1icaf, f0icaf) @[Cat.scala 29:58]
node _T_24 = mux(_T_17, f0icaf, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_25 = mux(_T_22, _T_23, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_26 = or(_T_24, _T_25) @[Mux.scala 27:72]
wire alignicaf : UInt<2> @[Mux.scala 27:72]
alignicaf <= _T_26 @[Mux.scala 27:72]
ALN 1st attempt
2020-10-01 17:49:02 +08:00
node _T_27 = bits(first4B, 0, 0) @[el2_ifu_aln_ctl.scala 114:39]
node _T_28 = orr(alignicaf) @[el2_ifu_aln_ctl.scala 114:59]
node _T_29 = bits(first2B, 0, 0) @[el2_ifu_aln_ctl.scala 114:72]
node _T_30 = bits(alignicaf, 0, 0) @[el2_ifu_aln_ctl.scala 114:91]
Compressed
2020-09-27 04:49:55 +08:00
node _T_31 = mux(_T_27, _T_28, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_32 = mux(_T_29, _T_30, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_33 = or(_T_31, _T_32) @[Mux.scala 27:72]
wire _T_34 : UInt<1> @[Mux.scala 27:72]
_T_34 <= _T_33 @[Mux.scala 27:72]
ALN 1st attempt
2020-10-01 17:49:02 +08:00
io.ifu_i0_icaf <= _T_34 @[el2_ifu_aln_ctl.scala 114:18]
node _T_35 = bits(first4B, 0, 0) @[el2_ifu_aln_ctl.scala 115:40]
node _T_36 = bits(alignval, 1, 1) @[el2_ifu_aln_ctl.scala 115:58]
node _T_37 = bits(first2B, 0, 0) @[el2_ifu_aln_ctl.scala 115:71]
node _T_38 = bits(alignval, 0, 0) @[el2_ifu_aln_ctl.scala 115:89]
Compressed
2020-09-27 04:49:55 +08:00
node _T_39 = mux(_T_35, _T_36, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_40 = mux(_T_37, _T_38, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_41 = or(_T_39, _T_40) @[Mux.scala 27:72]
wire _T_42 : UInt<1> @[Mux.scala 27:72]
_T_42 <= _T_41 @[Mux.scala 27:72]
ALN 1st attempt
2020-10-01 17:49:02 +08:00
io.ifu_i0_valid <= _T_42 @[el2_ifu_aln_ctl.scala 115:19]
io.ifu_i0_pc4 <= first4B @[el2_ifu_aln_ctl.scala 116:17]
node shift_2B = and(i0_shift, first2B) @[el2_ifu_aln_ctl.scala 118:27]
node shift_4B = and(i0_shift, first4B) @[el2_ifu_aln_ctl.scala 119:27]
node _T_43 = bits(shift_2B, 0, 0) @[el2_ifu_aln_ctl.scala 120:40]
node _T_44 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 120:55]
node _T_45 = bits(shift_4B, 0, 0) @[el2_ifu_aln_ctl.scala 120:69]
node _T_46 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 120:86]
node _T_47 = eq(_T_46, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 120:80]
node _T_48 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 120:97]
node _T_49 = and(_T_47, _T_48) @[el2_ifu_aln_ctl.scala 120:90]
Compressed
2020-09-27 04:49:55 +08:00
node _T_50 = mux(_T_43, _T_44, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_51 = mux(_T_45, _T_49, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_52 = or(_T_50, _T_51) @[Mux.scala 27:72]
Aligner done
2020-09-23 18:27:02 +08:00
wire f0_shift_2B : UInt<1> @[Mux.scala 27:72]
Compressed
2020-09-27 04:49:55 +08:00
f0_shift_2B <= _T_52 @[Mux.scala 27:72]
ALN 1st attempt
2020-10-01 17:49:02 +08:00
node _T_53 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 121:27]
node _T_54 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 121:39]
node _T_55 = eq(_T_54, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 121:33]
node _T_56 = and(_T_53, _T_55) @[el2_ifu_aln_ctl.scala 121:31]
node f1_shift_2B = and(_T_56, shift_4B) @[el2_ifu_aln_ctl.scala 121:43]
reg wrptr : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_aln_ctl.scala 123:48]
wrptr <= wrptr_in @[el2_ifu_aln_ctl.scala 123:48]
reg rdptr : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_aln_ctl.scala 124:48]
rdptr <= wrptr_in @[el2_ifu_aln_ctl.scala 124:48]
reg f2val : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_aln_ctl.scala 126:48]
f2val <= f2val_in @[el2_ifu_aln_ctl.scala 126:48]
reg f1val : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_aln_ctl.scala 127:48]
f1val <= f1val_in @[el2_ifu_aln_ctl.scala 127:48]
reg q2off : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_aln_ctl.scala 130:48]
q2off <= q2off_in @[el2_ifu_aln_ctl.scala 130:48]
reg q1off : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_aln_ctl.scala 131:48]
q1off <= q1off_in @[el2_ifu_aln_ctl.scala 131:48]
reg q0off : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_aln_ctl.scala 132:48]
q0off <= q0off_in @[el2_ifu_aln_ctl.scala 132:48]
node _T_57 = eq(sf0_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 134:29]
node _T_58 = eq(sf1_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 134:42]
node _T_59 = and(_T_57, _T_58) @[el2_ifu_aln_ctl.scala 134:40]
node _T_60 = eq(f2_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 134:55]
node _T_61 = and(_T_59, _T_60) @[el2_ifu_aln_ctl.scala 134:53]
node fetch_to_f0 = and(_T_61, ifvalid) @[el2_ifu_aln_ctl.scala 134:65]
node _T_62 = eq(sf0_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 135:29]
node _T_63 = eq(sf1_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 135:42]
node _T_64 = and(_T_62, _T_63) @[el2_ifu_aln_ctl.scala 135:40]
node _T_65 = and(_T_64, f2_valid) @[el2_ifu_aln_ctl.scala 135:53]
node _T_66 = and(_T_65, ifvalid) @[el2_ifu_aln_ctl.scala 135:65]
node _T_67 = eq(sf0_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 136:29]
node _T_68 = and(_T_67, sf1_valid) @[el2_ifu_aln_ctl.scala 136:40]
node _T_69 = eq(f2_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 136:55]
node _T_70 = and(_T_68, _T_69) @[el2_ifu_aln_ctl.scala 136:53]
node _T_71 = and(_T_70, ifvalid) @[el2_ifu_aln_ctl.scala 136:65]
node _T_72 = or(_T_66, _T_71) @[el2_ifu_aln_ctl.scala 135:77]
node _T_73 = eq(sf1_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 137:42]
node _T_74 = and(sf0_valid, _T_73) @[el2_ifu_aln_ctl.scala 137:40]
node _T_75 = eq(f2_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 137:55]
node _T_76 = and(_T_74, _T_75) @[el2_ifu_aln_ctl.scala 137:53]
node _T_77 = and(_T_76, ifvalid) @[el2_ifu_aln_ctl.scala 137:65]
node fetch_to_f1 = or(_T_72, _T_77) @[el2_ifu_aln_ctl.scala 136:77]
node _T_78 = eq(sf0_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 139:29]
node _T_79 = and(_T_78, sf1_valid) @[el2_ifu_aln_ctl.scala 139:40]
node _T_80 = and(_T_79, f2_valid) @[el2_ifu_aln_ctl.scala 139:53]
node _T_81 = and(_T_80, ifvalid) @[el2_ifu_aln_ctl.scala 139:65]
node _T_82 = and(sf0_valid, sf1_valid) @[el2_ifu_aln_ctl.scala 140:40]
node _T_83 = eq(f2_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 140:55]
node _T_84 = and(_T_82, _T_83) @[el2_ifu_aln_ctl.scala 140:53]
node _T_85 = and(_T_84, ifvalid) @[el2_ifu_aln_ctl.scala 140:65]
node f2_wr_en = or(_T_81, _T_85) @[el2_ifu_aln_ctl.scala 139:77]
node _T_86 = or(fetch_to_f1, shift_f2_f1) @[el2_ifu_aln_ctl.scala 143:36]
node f1_shift_wr_en = or(_T_86, f1_shift_2B) @[el2_ifu_aln_ctl.scala 143:50]
node _T_87 = or(fetch_to_f0, shift_f2_f0) @[el2_ifu_aln_ctl.scala 144:36]
node _T_88 = or(_T_87, shift_f1_f0) @[el2_ifu_aln_ctl.scala 144:50]
node _T_89 = or(_T_88, shift_2B) @[el2_ifu_aln_ctl.scala 144:64]
node f0_shift_wr_en = or(_T_89, shift_4B) @[el2_ifu_aln_ctl.scala 144:75]
node _T_90 = eq(rdptr, UInt<2>("h02")) @[el2_ifu_aln_ctl.scala 146:24]
node _T_91 = eq(rdptr, UInt<1>("h01")) @[el2_ifu_aln_ctl.scala 146:39]
node _T_92 = eq(rdptr, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 146:54]
Compressed
2020-09-27 04:49:55 +08:00
node _T_93 = cat(_T_90, _T_91) @[Cat.scala 29:58]
node qren = cat(_T_93, _T_92) @[Cat.scala 29:58]
ALN 1st attempt
2020-10-01 17:49:02 +08:00
node _T_94 = eq(wrptr, UInt<2>("h02")) @[el2_ifu_aln_ctl.scala 147:24]
node _T_95 = and(_T_94, ifvalid) @[el2_ifu_aln_ctl.scala 147:32]
node _T_96 = eq(wrptr, UInt<1>("h01")) @[el2_ifu_aln_ctl.scala 147:49]
node _T_97 = and(_T_96, ifvalid) @[el2_ifu_aln_ctl.scala 147:57]
node _T_98 = eq(wrptr, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 147:74]
node _T_99 = and(_T_98, ifvalid) @[el2_ifu_aln_ctl.scala 147:82]
Compressed
2020-09-27 04:49:55 +08:00
node _T_100 = cat(_T_95, _T_97) @[Cat.scala 29:58]
node qwen = cat(_T_100, _T_99) @[Cat.scala 29:58]
ALN 1st attempt
2020-10-01 17:49:02 +08:00
node _T_101 = bits(qren, 0, 0) @[el2_ifu_aln_ctl.scala 149:30]
node _T_102 = and(_T_101, io.ifu_fb_consume1) @[el2_ifu_aln_ctl.scala 149:34]
node _T_103 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 149:57]
node _T_104 = and(_T_102, _T_103) @[el2_ifu_aln_ctl.scala 149:55]
node _T_105 = bits(_T_104, 0, 0) @[el2_ifu_aln_ctl.scala 149:78]
node _T_106 = bits(qren, 1, 1) @[el2_ifu_aln_ctl.scala 150:30]
node _T_107 = and(_T_106, io.ifu_fb_consume1) @[el2_ifu_aln_ctl.scala 150:34]
node _T_108 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 150:57]
node _T_109 = and(_T_107, _T_108) @[el2_ifu_aln_ctl.scala 150:55]
node _T_110 = bits(_T_109, 0, 0) @[el2_ifu_aln_ctl.scala 150:78]
node _T_111 = bits(qren, 2, 2) @[el2_ifu_aln_ctl.scala 151:30]
node _T_112 = and(_T_111, io.ifu_fb_consume1) @[el2_ifu_aln_ctl.scala 151:34]
node _T_113 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 151:57]
node _T_114 = and(_T_112, _T_113) @[el2_ifu_aln_ctl.scala 151:55]
node _T_115 = bits(_T_114, 0, 0) @[el2_ifu_aln_ctl.scala 151:78]
node _T_116 = bits(qren, 0, 0) @[el2_ifu_aln_ctl.scala 152:30]
node _T_117 = and(_T_116, io.ifu_fb_consume2) @[el2_ifu_aln_ctl.scala 152:34]
node _T_118 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 152:57]
node _T_119 = and(_T_117, _T_118) @[el2_ifu_aln_ctl.scala 152:55]
node _T_120 = bits(_T_119, 0, 0) @[el2_ifu_aln_ctl.scala 152:78]
node _T_121 = bits(qren, 1, 1) @[el2_ifu_aln_ctl.scala 153:30]
node _T_122 = and(_T_121, io.ifu_fb_consume2) @[el2_ifu_aln_ctl.scala 153:34]
node _T_123 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 153:57]
node _T_124 = and(_T_122, _T_123) @[el2_ifu_aln_ctl.scala 153:55]
node _T_125 = bits(_T_124, 0, 0) @[el2_ifu_aln_ctl.scala 153:78]
node _T_126 = bits(qren, 2, 2) @[el2_ifu_aln_ctl.scala 154:30]
node _T_127 = and(_T_126, io.ifu_fb_consume2) @[el2_ifu_aln_ctl.scala 154:34]
node _T_128 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 154:57]
node _T_129 = and(_T_127, _T_128) @[el2_ifu_aln_ctl.scala 154:55]
node _T_130 = bits(_T_129, 0, 0) @[el2_ifu_aln_ctl.scala 154:78]
node _T_131 = eq(io.ifu_fb_consume1, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 155:26]
node _T_132 = eq(io.ifu_fb_consume2, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 155:48]
node _T_133 = and(_T_131, _T_132) @[el2_ifu_aln_ctl.scala 155:46]
node _T_134 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 155:70]
node _T_135 = and(_T_133, _T_134) @[el2_ifu_aln_ctl.scala 155:68]
node _T_136 = bits(_T_135, 0, 0) @[el2_ifu_aln_ctl.scala 155:91]
Compressed
2020-09-27 04:49:55 +08:00
node _T_137 = mux(_T_105, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_138 = mux(_T_110, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_139 = mux(_T_115, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_140 = mux(_T_120, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_141 = mux(_T_125, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_142 = mux(_T_130, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_143 = mux(_T_136, rdptr, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_144 = or(_T_137, _T_138) @[Mux.scala 27:72]
Aligner done
2020-09-23 18:27:02 +08:00
node _T_145 = or(_T_144, _T_139) @[Mux.scala 27:72]
Compressed
2020-09-27 04:49:55 +08:00
node _T_146 = or(_T_145, _T_140) @[Mux.scala 27:72]
node _T_147 = or(_T_146, _T_141) @[Mux.scala 27:72]
node _T_148 = or(_T_147, _T_142) @[Mux.scala 27:72]
node _T_149 = or(_T_148, _T_143) @[Mux.scala 27:72]
wire _T_150 : UInt @[Mux.scala 27:72]
_T_150 <= _T_149 @[Mux.scala 27:72]
ALN 1st attempt
2020-10-01 17:49:02 +08:00
rdptr_in <= _T_150 @[el2_ifu_aln_ctl.scala 149:12]
node _T_151 = bits(qwen, 0, 0) @[el2_ifu_aln_ctl.scala 157:30]
node _T_152 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 157:36]
node _T_153 = and(_T_151, _T_152) @[el2_ifu_aln_ctl.scala 157:34]
node _T_154 = bits(_T_153, 0, 0) @[el2_ifu_aln_ctl.scala 157:57]
node _T_155 = bits(qwen, 1, 1) @[el2_ifu_aln_ctl.scala 158:30]
node _T_156 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 158:36]
node _T_157 = and(_T_155, _T_156) @[el2_ifu_aln_ctl.scala 158:34]
node _T_158 = bits(_T_157, 0, 0) @[el2_ifu_aln_ctl.scala 158:57]
node _T_159 = bits(qwen, 2, 2) @[el2_ifu_aln_ctl.scala 159:30]
node _T_160 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 159:36]
node _T_161 = and(_T_159, _T_160) @[el2_ifu_aln_ctl.scala 159:34]
node _T_162 = bits(_T_161, 0, 0) @[el2_ifu_aln_ctl.scala 159:57]
node _T_163 = eq(ifvalid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 160:26]
node _T_164 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 160:37]
node _T_165 = and(_T_163, _T_164) @[el2_ifu_aln_ctl.scala 160:35]
node _T_166 = bits(_T_165, 0, 0) @[el2_ifu_aln_ctl.scala 160:58]
Compressed
2020-09-27 04:49:55 +08:00
node _T_167 = mux(_T_154, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_168 = mux(_T_158, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_169 = mux(_T_162, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_170 = mux(_T_166, wrptr, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_171 = or(_T_167, _T_168) @[Mux.scala 27:72]
node _T_172 = or(_T_171, _T_169) @[Mux.scala 27:72]
node _T_173 = or(_T_172, _T_170) @[Mux.scala 27:72]
wire _T_174 : UInt @[Mux.scala 27:72]
_T_174 <= _T_173 @[Mux.scala 27:72]
ALN 1st attempt
2020-10-01 17:49:02 +08:00
wrptr_in <= _T_174 @[el2_ifu_aln_ctl.scala 157:12]
node _T_175 = bits(qwen, 2, 2) @[el2_ifu_aln_ctl.scala 162:31]
node _T_176 = eq(_T_175, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 162:26]
node _T_177 = eq(rdptr, UInt<2>("h02")) @[el2_ifu_aln_ctl.scala 162:43]
node _T_178 = and(_T_176, _T_177) @[el2_ifu_aln_ctl.scala 162:35]
node _T_179 = bits(_T_178, 0, 0) @[el2_ifu_aln_ctl.scala 162:52]
node _T_180 = or(q2off, f0_shift_2B) @[el2_ifu_aln_ctl.scala 162:74]
node _T_181 = bits(qwen, 2, 2) @[el2_ifu_aln_ctl.scala 163:31]
node _T_182 = eq(_T_181, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 163:26]
node _T_183 = eq(rdptr, UInt<1>("h01")) @[el2_ifu_aln_ctl.scala 163:43]
node _T_184 = and(_T_182, _T_183) @[el2_ifu_aln_ctl.scala 163:35]
node _T_185 = bits(_T_184, 0, 0) @[el2_ifu_aln_ctl.scala 163:52]
node _T_186 = or(q2off, f1_shift_2B) @[el2_ifu_aln_ctl.scala 163:74]
node _T_187 = bits(qwen, 2, 2) @[el2_ifu_aln_ctl.scala 164:31]
node _T_188 = eq(_T_187, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 164:26]
node _T_189 = eq(rdptr, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 164:43]
node _T_190 = and(_T_188, _T_189) @[el2_ifu_aln_ctl.scala 164:35]
node _T_191 = bits(_T_190, 0, 0) @[el2_ifu_aln_ctl.scala 164:52]
Compressed
2020-09-27 04:49:55 +08:00
node _T_192 = mux(_T_179, _T_180, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_193 = mux(_T_185, _T_186, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_194 = mux(_T_191, q2off, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_195 = or(_T_192, _T_193) @[Mux.scala 27:72]
node _T_196 = or(_T_195, _T_194) @[Mux.scala 27:72]
wire _T_197 : UInt @[Mux.scala 27:72]
_T_197 <= _T_196 @[Mux.scala 27:72]
ALN 1st attempt
2020-10-01 17:49:02 +08:00
q2off_in <= _T_197 @[el2_ifu_aln_ctl.scala 162:12]
node _T_198 = bits(qwen, 1, 1) @[el2_ifu_aln_ctl.scala 166:31]
node _T_199 = eq(_T_198, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 166:26]
node _T_200 = eq(rdptr, UInt<1>("h01")) @[el2_ifu_aln_ctl.scala 166:43]
node _T_201 = and(_T_199, _T_200) @[el2_ifu_aln_ctl.scala 166:35]
node _T_202 = bits(_T_201, 0, 0) @[el2_ifu_aln_ctl.scala 166:52]
node _T_203 = or(q1off, f0_shift_2B) @[el2_ifu_aln_ctl.scala 166:74]
node _T_204 = bits(qwen, 1, 1) @[el2_ifu_aln_ctl.scala 167:31]
node _T_205 = eq(_T_204, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 167:26]
node _T_206 = eq(rdptr, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 167:43]
node _T_207 = and(_T_205, _T_206) @[el2_ifu_aln_ctl.scala 167:35]
node _T_208 = bits(_T_207, 0, 0) @[el2_ifu_aln_ctl.scala 167:52]
node _T_209 = or(q1off, f1_shift_2B) @[el2_ifu_aln_ctl.scala 167:74]
node _T_210 = bits(qwen, 1, 1) @[el2_ifu_aln_ctl.scala 168:31]
node _T_211 = eq(_T_210, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 168:26]
node _T_212 = eq(rdptr, UInt<2>("h02")) @[el2_ifu_aln_ctl.scala 168:43]
node _T_213 = and(_T_211, _T_212) @[el2_ifu_aln_ctl.scala 168:35]
node _T_214 = bits(_T_213, 0, 0) @[el2_ifu_aln_ctl.scala 168:52]
Compressed
2020-09-27 04:49:55 +08:00
node _T_215 = mux(_T_202, _T_203, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_216 = mux(_T_208, _T_209, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_217 = mux(_T_214, q1off, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_218 = or(_T_215, _T_216) @[Mux.scala 27:72]
node _T_219 = or(_T_218, _T_217) @[Mux.scala 27:72]
wire _T_220 : UInt @[Mux.scala 27:72]
_T_220 <= _T_219 @[Mux.scala 27:72]
ALN 1st attempt
2020-10-01 17:49:02 +08:00
q1off_in <= _T_220 @[el2_ifu_aln_ctl.scala 166:12]
node _T_221 = bits(qwen, 0, 0) @[el2_ifu_aln_ctl.scala 170:31]
node _T_222 = eq(_T_221, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 170:26]
node _T_223 = eq(rdptr, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 170:43]
node _T_224 = and(_T_222, _T_223) @[el2_ifu_aln_ctl.scala 170:35]
node _T_225 = bits(_T_224, 0, 0) @[el2_ifu_aln_ctl.scala 170:52]
node _T_226 = or(q0off, f0_shift_2B) @[el2_ifu_aln_ctl.scala 170:76]
node _T_227 = bits(qwen, 0, 0) @[el2_ifu_aln_ctl.scala 171:31]
node _T_228 = eq(_T_227, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 171:26]
node _T_229 = eq(rdptr, UInt<2>("h02")) @[el2_ifu_aln_ctl.scala 171:43]
node _T_230 = and(_T_228, _T_229) @[el2_ifu_aln_ctl.scala 171:35]
node _T_231 = bits(_T_230, 0, 0) @[el2_ifu_aln_ctl.scala 171:52]
node _T_232 = or(q0off, f1_shift_2B) @[el2_ifu_aln_ctl.scala 171:76]
node _T_233 = bits(qwen, 0, 0) @[el2_ifu_aln_ctl.scala 172:31]
node _T_234 = eq(_T_233, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 172:26]
node _T_235 = eq(rdptr, UInt<1>("h01")) @[el2_ifu_aln_ctl.scala 172:43]
node _T_236 = and(_T_234, _T_235) @[el2_ifu_aln_ctl.scala 172:35]
node _T_237 = bits(_T_236, 0, 0) @[el2_ifu_aln_ctl.scala 172:52]
Compressed
2020-09-27 04:49:55 +08:00
node _T_238 = mux(_T_225, _T_226, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_239 = mux(_T_231, _T_232, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_240 = mux(_T_237, q0off, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_241 = or(_T_238, _T_239) @[Mux.scala 27:72]
node _T_242 = or(_T_241, _T_240) @[Mux.scala 27:72]
wire _T_243 : UInt @[Mux.scala 27:72]
_T_243 <= _T_242 @[Mux.scala 27:72]
ALN 1st attempt
2020-10-01 17:49:02 +08:00
q0off_in <= _T_243 @[el2_ifu_aln_ctl.scala 170:12]
node _T_244 = eq(rdptr, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 174:31]
node _T_245 = eq(rdptr, UInt<1>("h01")) @[el2_ifu_aln_ctl.scala 175:31]
node _T_246 = eq(rdptr, UInt<2>("h02")) @[el2_ifu_aln_ctl.scala 176:31]
Compressed
2020-09-27 04:49:55 +08:00
node _T_247 = mux(_T_244, q0off, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_248 = mux(_T_245, q1off, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_249 = mux(_T_246, q2off, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_250 = or(_T_247, _T_248) @[Mux.scala 27:72]
node _T_251 = or(_T_250, _T_249) @[Mux.scala 27:72]
Aligner done
2020-09-23 18:27:02 +08:00
wire q0ptr : UInt @[Mux.scala 27:72]
Compressed
2020-09-27 04:49:55 +08:00
q0ptr <= _T_251 @[Mux.scala 27:72]
ALN 1st attempt
2020-10-01 17:49:02 +08:00
node _T_252 = eq(rdptr, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 178:32]
node _T_253 = eq(rdptr, UInt<1>("h01")) @[el2_ifu_aln_ctl.scala 178:57]
node _T_254 = eq(rdptr, UInt<2>("h02")) @[el2_ifu_aln_ctl.scala 178:83]
Compressed
2020-09-27 04:49:55 +08:00
node _T_255 = mux(_T_252, q1off, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_256 = mux(_T_253, q2off, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_257 = mux(_T_254, q0off, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_258 = or(_T_255, _T_256) @[Mux.scala 27:72]
node _T_259 = or(_T_258, _T_257) @[Mux.scala 27:72]
Aligner done
2020-09-23 18:27:02 +08:00
wire q1ptr : UInt @[Mux.scala 27:72]
Compressed
2020-09-27 04:49:55 +08:00
q1ptr <= _T_259 @[Mux.scala 27:72]
ALN 1st attempt
2020-10-01 17:49:02 +08:00
node _T_260 = eq(q0ptr, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 180:26]
Compressed
2020-09-27 04:49:55 +08:00
node q0sel = cat(q0ptr, _T_260) @[Cat.scala 29:58]
ALN 1st attempt
2020-10-01 17:49:02 +08:00
node _T_261 = eq(q1ptr, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 182:26]
Compressed
2020-09-27 04:49:55 +08:00
node q1sel = cat(q1ptr, _T_261) @[Cat.scala 29:58]
ALN 1st attempt
2020-10-01 17:49:02 +08:00
node _T_262 = bits(io.ifu_bp_btb_target_f, 31, 1) @[el2_ifu_aln_ctl.scala 185:48]
Compressed
2020-09-27 04:49:55 +08:00
node _T_263 = cat(_T_262, io.ifu_bp_poffset_f) @[Cat.scala 29:58]
node _T_264 = cat(_T_263, io.ifu_bp_fghr_f) @[Cat.scala 29:58]
node _T_265 = cat(io.iccm_rd_ecc_double_err, io.ic_access_fault_f) @[Cat.scala 29:58]
node _T_266 = cat(_T_265, io.ic_access_fault_type_f) @[Cat.scala 29:58]
node misc_data_in = cat(_T_266, _T_264) @[Cat.scala 29:58]
ALN 1st attempt
2020-10-01 17:49:02 +08:00
node _T_267 = bits(qren, 0, 0) @[el2_ifu_aln_ctl.scala 187:31]
node _T_268 = bits(_T_267, 0, 0) @[el2_ifu_aln_ctl.scala 187:41]
Compressed
2020-09-27 04:49:55 +08:00
node _T_269 = cat(misc1, misc0) @[Cat.scala 29:58]
ALN 1st attempt
2020-10-01 17:49:02 +08:00
node _T_270 = bits(qren, 1, 1) @[el2_ifu_aln_ctl.scala 188:27]
node _T_271 = bits(_T_270, 0, 0) @[el2_ifu_aln_ctl.scala 188:37]
Compressed
2020-09-27 04:49:55 +08:00
node _T_272 = cat(misc2, misc1) @[Cat.scala 29:58]
ALN 1st attempt
2020-10-01 17:49:02 +08:00
node _T_273 = bits(qren, 2, 2) @[el2_ifu_aln_ctl.scala 189:27]
node _T_274 = bits(_T_273, 0, 0) @[el2_ifu_aln_ctl.scala 189:37]
Compressed
2020-09-27 04:49:55 +08:00
node _T_275 = cat(misc0, misc2) @[Cat.scala 29:58]
node _T_276 = mux(_T_268, _T_269, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_277 = mux(_T_271, _T_272, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_278 = mux(_T_274, _T_275, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_279 = or(_T_276, _T_277) @[Mux.scala 27:72]
node _T_280 = or(_T_279, _T_278) @[Mux.scala 27:72]
Aligner done
2020-09-23 18:27:02 +08:00
wire misceff : UInt<108> @[Mux.scala 27:72]
Compressed
2020-09-27 04:49:55 +08:00
misceff <= _T_280 @[Mux.scala 27:72]
ALN 1st attempt
2020-10-01 17:49:02 +08:00
node misc1eff = bits(misceff, 107, 55) @[el2_ifu_aln_ctl.scala 191:25]
node misc0eff = bits(misceff, 54, 0) @[el2_ifu_aln_ctl.scala 192:25]
node f1dbecc = bits(misc1eff, 52, 52) @[el2_ifu_aln_ctl.scala 194:25]
node _T_281 = bits(misc1eff, 51, 51) @[el2_ifu_aln_ctl.scala 195:21]
f1icaf <= _T_281 @[el2_ifu_aln_ctl.scala 195:10]
node f1ictype = bits(misc1eff, 50, 49) @[el2_ifu_aln_ctl.scala 196:26]
node f1prett = bits(misc1eff, 48, 18) @[el2_ifu_aln_ctl.scala 197:25]
node f1poffset = bits(misc1eff, 19, 8) @[el2_ifu_aln_ctl.scala 198:27]
node f1fghr = bits(misc1eff, 7, 0) @[el2_ifu_aln_ctl.scala 199:24]
node f0dbecc = bits(misc0eff, 54, 54) @[el2_ifu_aln_ctl.scala 201:25]
node _T_282 = bits(misc0eff, 53, 53) @[el2_ifu_aln_ctl.scala 202:21]
f0icaf <= _T_282 @[el2_ifu_aln_ctl.scala 202:10]
node f0ictype = bits(misc0eff, 52, 51) @[el2_ifu_aln_ctl.scala 203:26]
node f0prett = bits(misc0eff, 50, 20) @[el2_ifu_aln_ctl.scala 204:25]
node f0poffset = bits(misc0eff, 19, 8) @[el2_ifu_aln_ctl.scala 205:27]
node f0fghr = bits(misc0eff, 7, 0) @[el2_ifu_aln_ctl.scala 206:24]
node _T_283 = bits(io.ifu_bp_hist1_f, 1, 1) @[el2_ifu_aln_ctl.scala 208:40]
node _T_284 = bits(io.ifu_bp_hist0_f, 1, 1) @[el2_ifu_aln_ctl.scala 208:61]
node _T_285 = bits(io.ifu_bp_pc4_f, 1, 1) @[el2_ifu_aln_ctl.scala 208:80]
node _T_286 = bits(io.ifu_bp_way_f, 1, 1) @[el2_ifu_aln_ctl.scala 208:99]
node _T_287 = bits(io.ifu_bp_valid_f, 1, 1) @[el2_ifu_aln_ctl.scala 208:120]
node _T_288 = bits(io.ifu_bp_ret_f, 1, 1) @[el2_ifu_aln_ctl.scala 209:20]
node _T_289 = bits(io.ifu_bp_hist1_f, 0, 0) @[el2_ifu_aln_ctl.scala 209:42]
node _T_290 = bits(io.ifu_bp_hist0_f, 0, 0) @[el2_ifu_aln_ctl.scala 209:63]
node _T_291 = bits(io.ifu_bp_pc4_f, 0, 0) @[el2_ifu_aln_ctl.scala 209:82]
node _T_292 = bits(io.ifu_bp_way_f, 0, 0) @[el2_ifu_aln_ctl.scala 209:101]
node _T_293 = bits(io.ifu_bp_valid_f, 0, 0) @[el2_ifu_aln_ctl.scala 210:22]
node _T_294 = bits(io.ifu_bp_ret_f, 0, 0) @[el2_ifu_aln_ctl.scala 210:41]
Compressed
2020-09-27 04:49:55 +08:00
node _T_295 = cat(_T_292, _T_293) @[Cat.scala 29:58]
node _T_296 = cat(_T_295, _T_294) @[Cat.scala 29:58]
node _T_297 = cat(_T_289, _T_290) @[Cat.scala 29:58]
node _T_298 = cat(_T_297, _T_291) @[Cat.scala 29:58]
node _T_299 = cat(_T_298, _T_296) @[Cat.scala 29:58]
node _T_300 = cat(_T_286, _T_287) @[Cat.scala 29:58]
node _T_301 = cat(_T_300, _T_288) @[Cat.scala 29:58]
node _T_302 = cat(_T_283, _T_284) @[Cat.scala 29:58]
node _T_303 = cat(_T_302, _T_285) @[Cat.scala 29:58]
node _T_304 = cat(_T_303, _T_301) @[Cat.scala 29:58]
node brdata_in = cat(_T_304, _T_299) @[Cat.scala 29:58]
ALN 1st attempt
2020-10-01 17:49:02 +08:00
node _T_305 = bits(qren, 0, 0) @[el2_ifu_aln_ctl.scala 212:33]
node _T_306 = bits(_T_305, 0, 0) @[el2_ifu_aln_ctl.scala 212:37]
Compressed
2020-09-27 04:49:55 +08:00
node _T_307 = cat(brdata1, brdata0) @[Cat.scala 29:58]
ALN 1st attempt
2020-10-01 17:49:02 +08:00
node _T_308 = bits(qren, 1, 1) @[el2_ifu_aln_ctl.scala 213:33]
node _T_309 = bits(_T_308, 0, 0) @[el2_ifu_aln_ctl.scala 213:37]
Compressed
2020-09-27 04:49:55 +08:00
node _T_310 = cat(brdata2, brdata1) @[Cat.scala 29:58]
ALN 1st attempt
2020-10-01 17:49:02 +08:00
node _T_311 = bits(qren, 2, 2) @[el2_ifu_aln_ctl.scala 214:33]
node _T_312 = bits(_T_311, 0, 0) @[el2_ifu_aln_ctl.scala 214:37]
Compressed
2020-09-27 04:49:55 +08:00
node _T_313 = cat(brdata0, brdata2) @[Cat.scala 29:58]
node _T_314 = mux(_T_306, _T_307, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_315 = mux(_T_309, _T_310, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_316 = mux(_T_312, _T_313, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_317 = or(_T_314, _T_315) @[Mux.scala 27:72]
node _T_318 = or(_T_317, _T_316) @[Mux.scala 27:72]
Aligner done
2020-09-23 18:27:02 +08:00
wire brdataeff : UInt<24> @[Mux.scala 27:72]
Compressed
2020-09-27 04:49:55 +08:00
brdataeff <= _T_318 @[Mux.scala 27:72]
ALN 1st attempt
2020-10-01 17:49:02 +08:00
node brdata0eff = bits(brdataeff, 11, 0) @[el2_ifu_aln_ctl.scala 216:43]
node brdata1eff = bits(brdataeff, 23, 12) @[el2_ifu_aln_ctl.scala 216:61]
Aligner done
2020-09-23 18:27:02 +08:00
wire q0 : UInt<32>
q0 <= UInt<1>("h00")
wire q1 : UInt<32>
q1 <= UInt<1>("h00")
wire q2 : UInt<32>
q2 <= UInt<1>("h00")
ALN 1st attempt
2020-10-01 17:49:02 +08:00
node _T_319 = bits(qren, 0, 0) @[el2_ifu_aln_ctl.scala 222:28]
node _T_320 = bits(_T_319, 0, 0) @[el2_ifu_aln_ctl.scala 222:32]
Compressed
2020-09-27 04:49:55 +08:00
node _T_321 = cat(q1, q0) @[Cat.scala 29:58]
ALN 1st attempt
2020-10-01 17:49:02 +08:00
node _T_322 = bits(qren, 1, 1) @[el2_ifu_aln_ctl.scala 223:27]
node _T_323 = bits(_T_322, 0, 0) @[el2_ifu_aln_ctl.scala 223:31]
Compressed
2020-09-27 04:49:55 +08:00
node _T_324 = cat(q2, q1) @[Cat.scala 29:58]
ALN 1st attempt
2020-10-01 17:49:02 +08:00
node _T_325 = bits(qren, 2, 2) @[el2_ifu_aln_ctl.scala 224:27]
node _T_326 = bits(_T_325, 0, 0) @[el2_ifu_aln_ctl.scala 224:31]
Compressed
2020-09-27 04:49:55 +08:00
node _T_327 = cat(q0, q2) @[Cat.scala 29:58]
node _T_328 = mux(_T_320, _T_321, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_329 = mux(_T_323, _T_324, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_330 = mux(_T_326, _T_327, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_331 = or(_T_328, _T_329) @[Mux.scala 27:72]
node _T_332 = or(_T_331, _T_330) @[Mux.scala 27:72]
Aligner done
2020-09-23 18:27:02 +08:00
wire qeff : UInt<64> @[Mux.scala 27:72]
Compressed
2020-09-27 04:49:55 +08:00
qeff <= _T_332 @[Mux.scala 27:72]
ALN 1st attempt
2020-10-01 17:49:02 +08:00
node q1eff = bits(qeff, 63, 32) @[el2_ifu_aln_ctl.scala 225:29]
node q0eff = bits(qeff, 31, 0) @[el2_ifu_aln_ctl.scala 225:42]
node _T_333 = bits(q0sel, 0, 0) @[el2_ifu_aln_ctl.scala 226:37]
node _T_334 = bits(_T_333, 0, 0) @[el2_ifu_aln_ctl.scala 226:41]
node _T_335 = bits(q0sel, 1, 1) @[el2_ifu_aln_ctl.scala 226:68]
node _T_336 = bits(_T_335, 0, 0) @[el2_ifu_aln_ctl.scala 226:72]
node _T_337 = bits(brdata0eff, 11, 6) @[el2_ifu_aln_ctl.scala 226:92]
Compressed
2020-09-27 04:49:55 +08:00
node _T_338 = mux(_T_334, brdata0eff, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_339 = mux(_T_336, _T_337, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_340 = or(_T_338, _T_339) @[Mux.scala 27:72]
Aligner done
2020-09-23 18:27:02 +08:00
wire brdata0final : UInt<12> @[Mux.scala 27:72]
Compressed
2020-09-27 04:49:55 +08:00
brdata0final <= _T_340 @[Mux.scala 27:72]
ALN 1st attempt
2020-10-01 17:49:02 +08:00
node _T_341 = bits(q1sel, 0, 0) @[el2_ifu_aln_ctl.scala 228:37]
node _T_342 = bits(_T_341, 0, 0) @[el2_ifu_aln_ctl.scala 228:41]
node _T_343 = bits(q1sel, 1, 1) @[el2_ifu_aln_ctl.scala 228:68]
node _T_344 = bits(_T_343, 0, 0) @[el2_ifu_aln_ctl.scala 228:72]
node _T_345 = bits(brdata1eff, 11, 6) @[el2_ifu_aln_ctl.scala 228:92]
Compressed
2020-09-27 04:49:55 +08:00
node _T_346 = mux(_T_342, brdata1eff, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_347 = mux(_T_344, _T_345, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_348 = or(_T_346, _T_347) @[Mux.scala 27:72]
Aligner done
2020-09-23 18:27:02 +08:00
wire brdata1final : UInt<12> @[Mux.scala 27:72]
Compressed
2020-09-27 04:49:55 +08:00
brdata1final <= _T_348 @[Mux.scala 27:72]
ALN 1st attempt
2020-10-01 17:49:02 +08:00
node _T_349 = bits(brdata0final, 6, 6) @[el2_ifu_aln_ctl.scala 230:31]
node _T_350 = bits(brdata0final, 0, 0) @[el2_ifu_aln_ctl.scala 230:47]
Compressed
2020-09-27 04:49:55 +08:00
node f0ret = cat(_T_349, _T_350) @[Cat.scala 29:58]
ALN 1st attempt
2020-10-01 17:49:02 +08:00
node _T_351 = bits(brdata0final, 7, 7) @[el2_ifu_aln_ctl.scala 231:33]
node _T_352 = bits(brdata0final, 1, 1) @[el2_ifu_aln_ctl.scala 231:49]
Compressed
2020-09-27 04:49:55 +08:00
node f0brend = cat(_T_351, _T_352) @[Cat.scala 29:58]
ALN 1st attempt
2020-10-01 17:49:02 +08:00
node _T_353 = bits(brdata0final, 8, 8) @[el2_ifu_aln_ctl.scala 232:31]
node _T_354 = bits(brdata0final, 2, 2) @[el2_ifu_aln_ctl.scala 232:47]
Compressed
2020-09-27 04:49:55 +08:00
node f0way = cat(_T_353, _T_354) @[Cat.scala 29:58]
ALN 1st attempt
2020-10-01 17:49:02 +08:00
node _T_355 = bits(brdata0final, 9, 9) @[el2_ifu_aln_ctl.scala 233:31]
node _T_356 = bits(brdata0final, 3, 3) @[el2_ifu_aln_ctl.scala 233:47]
Compressed
2020-09-27 04:49:55 +08:00
node f0pc4 = cat(_T_355, _T_356) @[Cat.scala 29:58]
ALN 1st attempt
2020-10-01 17:49:02 +08:00
node _T_357 = bits(brdata0final, 10, 10) @[el2_ifu_aln_ctl.scala 234:33]
node _T_358 = bits(brdata0final, 4, 4) @[el2_ifu_aln_ctl.scala 234:50]
Compressed
2020-09-27 04:49:55 +08:00
node f0hist0 = cat(_T_357, _T_358) @[Cat.scala 29:58]
ALN 1st attempt
2020-10-01 17:49:02 +08:00
node _T_359 = bits(brdata0final, 11, 11) @[el2_ifu_aln_ctl.scala 235:33]
node _T_360 = bits(brdata0final, 5, 5) @[el2_ifu_aln_ctl.scala 235:50]
Compressed
2020-09-27 04:49:55 +08:00
node f0hist1 = cat(_T_359, _T_360) @[Cat.scala 29:58]
ALN 1st attempt
2020-10-01 17:49:02 +08:00
node _T_361 = bits(brdata1final, 6, 6) @[el2_ifu_aln_ctl.scala 237:31]
node _T_362 = bits(brdata1final, 0, 0) @[el2_ifu_aln_ctl.scala 237:47]
Compressed
2020-09-27 04:49:55 +08:00
node f1ret = cat(_T_361, _T_362) @[Cat.scala 29:58]
ALN 1st attempt
2020-10-01 17:49:02 +08:00
node _T_363 = bits(brdata1final, 7, 7) @[el2_ifu_aln_ctl.scala 238:33]
node _T_364 = bits(brdata1final, 1, 1) @[el2_ifu_aln_ctl.scala 238:49]
Compressed
2020-09-27 04:49:55 +08:00
node f1brend = cat(_T_363, _T_364) @[Cat.scala 29:58]
ALN 1st attempt
2020-10-01 17:49:02 +08:00
node _T_365 = bits(brdata1final, 8, 8) @[el2_ifu_aln_ctl.scala 239:31]
node _T_366 = bits(brdata1final, 2, 2) @[el2_ifu_aln_ctl.scala 239:47]
Compressed
2020-09-27 04:49:55 +08:00
node f1way = cat(_T_365, _T_366) @[Cat.scala 29:58]
ALN 1st attempt
2020-10-01 17:49:02 +08:00
node _T_367 = bits(brdata1final, 9, 9) @[el2_ifu_aln_ctl.scala 240:31]
node _T_368 = bits(brdata1final, 3, 3) @[el2_ifu_aln_ctl.scala 240:47]
Compressed
2020-09-27 04:49:55 +08:00
node f1pc4 = cat(_T_367, _T_368) @[Cat.scala 29:58]
ALN 1st attempt
2020-10-01 17:49:02 +08:00
node _T_369 = bits(brdata1final, 10, 10) @[el2_ifu_aln_ctl.scala 241:33]
node _T_370 = bits(brdata1final, 4, 4) @[el2_ifu_aln_ctl.scala 241:50]
Compressed
2020-09-27 04:49:55 +08:00
node f1hist0 = cat(_T_369, _T_370) @[Cat.scala 29:58]
ALN 1st attempt
2020-10-01 17:49:02 +08:00
node _T_371 = bits(brdata1final, 11, 11) @[el2_ifu_aln_ctl.scala 242:33]
node _T_372 = bits(brdata1final, 5, 5) @[el2_ifu_aln_ctl.scala 242:50]
Compressed
2020-09-27 04:49:55 +08:00
node f1hist1 = cat(_T_371, _T_372) @[Cat.scala 29:58]
ALN 1st attempt
2020-10-01 17:49:02 +08:00
node _T_373 = bits(f2val, 0, 0) @[el2_ifu_aln_ctl.scala 246:20]
f2_valid <= _T_373 @[el2_ifu_aln_ctl.scala 246:12]
node _T_374 = bits(sf1val, 0, 0) @[el2_ifu_aln_ctl.scala 247:22]
sf1_valid <= _T_374 @[el2_ifu_aln_ctl.scala 247:13]
node _T_375 = bits(sf0val, 0, 0) @[el2_ifu_aln_ctl.scala 248:22]
sf0_valid <= _T_375 @[el2_ifu_aln_ctl.scala 248:13]
node _T_376 = bits(sf0val, 0, 0) @[el2_ifu_aln_ctl.scala 250:28]
node _T_377 = eq(_T_376, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 250:21]
node _T_378 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 250:39]
node consume_fb0 = and(_T_377, _T_378) @[el2_ifu_aln_ctl.scala 250:32]
node _T_379 = bits(sf1val, 0, 0) @[el2_ifu_aln_ctl.scala 251:28]
node _T_380 = eq(_T_379, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 251:21]
node _T_381 = bits(f1val, 0, 0) @[el2_ifu_aln_ctl.scala 251:39]
node consume_fb1 = and(_T_380, _T_381) @[el2_ifu_aln_ctl.scala 251:32]
node _T_382 = eq(consume_fb1, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 253:39]
node _T_383 = and(consume_fb0, _T_382) @[el2_ifu_aln_ctl.scala 253:37]
node _T_384 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 253:54]
node _T_385 = and(_T_383, _T_384) @[el2_ifu_aln_ctl.scala 253:52]
io.ifu_fb_consume1 <= _T_385 @[el2_ifu_aln_ctl.scala 253:22]
node _T_386 = and(consume_fb0, consume_fb1) @[el2_ifu_aln_ctl.scala 254:37]
node _T_387 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 254:54]
node _T_388 = and(_T_386, _T_387) @[el2_ifu_aln_ctl.scala 254:52]
io.ifu_fb_consume2 <= _T_388 @[el2_ifu_aln_ctl.scala 254:22]
node _T_389 = bits(io.ifu_fetch_val, 0, 0) @[el2_ifu_aln_ctl.scala 256:30]
ifvalid <= _T_389 @[el2_ifu_aln_ctl.scala 256:11]
node _T_390 = eq(sf0_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 258:18]
node _T_391 = and(_T_390, sf1_valid) @[el2_ifu_aln_ctl.scala 258:29]
shift_f1_f0 <= _T_391 @[el2_ifu_aln_ctl.scala 258:15]
node _T_392 = eq(sf0_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 259:18]
node _T_393 = eq(sf1_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 259:31]
node _T_394 = and(_T_392, _T_393) @[el2_ifu_aln_ctl.scala 259:29]
node _T_395 = and(_T_394, f2_valid) @[el2_ifu_aln_ctl.scala 259:42]
shift_f2_f0 <= _T_395 @[el2_ifu_aln_ctl.scala 259:15]
node _T_396 = eq(sf0_valid, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 260:18]
node _T_397 = and(_T_396, sf1_valid) @[el2_ifu_aln_ctl.scala 260:29]
node _T_398 = and(_T_397, f2_valid) @[el2_ifu_aln_ctl.scala 260:42]
shift_f2_f1 <= _T_398 @[el2_ifu_aln_ctl.scala 260:15]
Aligner done
2020-09-23 18:27:02 +08:00
wire f0pc : UInt<31>
f0pc <= UInt<1>("h00")
wire f2pc : UInt<31>
f2pc <= UInt<1>("h00")
ALN 1st attempt
2020-10-01 17:49:02 +08:00
node _T_399 = add(f0pc, UInt<1>("h01")) @[el2_ifu_aln_ctl.scala 265:25]
node f0pc_plus1 = tail(_T_399, 1) @[el2_ifu_aln_ctl.scala 265:25]
Compressed
2020-09-27 04:49:55 +08:00
node _T_400 = bits(f1_shift_2B, 0, 0) @[Bitwise.scala 72:15]
Aligner done
2020-09-23 18:27:02 +08:00
node _T_401 = mux(_T_400, UInt<31>("h07fffffff"), UInt<31>("h00")) @[Bitwise.scala 72:12]
ALN 1st attempt
2020-10-01 17:49:02 +08:00
node _T_402 = and(_T_401, f0pc_plus1) @[el2_ifu_aln_ctl.scala 267:38]
node _T_403 = eq(f1_shift_2B, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 267:64]
Compressed
2020-09-27 04:49:55 +08:00
node _T_404 = bits(_T_403, 0, 0) @[Bitwise.scala 72:15]
node _T_405 = mux(_T_404, UInt<31>("h07fffffff"), UInt<31>("h00")) @[Bitwise.scala 72:12]
ALN 1st attempt
2020-10-01 17:49:02 +08:00
node _T_406 = and(_T_405, f0pc) @[el2_ifu_aln_ctl.scala 267:78]
node sf1pc = or(_T_402, _T_406) @[el2_ifu_aln_ctl.scala 267:52]
node _T_407 = bits(fetch_to_f1, 0, 0) @[el2_ifu_aln_ctl.scala 269:39]
node _T_408 = bits(shift_f2_f1, 0, 0) @[el2_ifu_aln_ctl.scala 270:39]
node _T_409 = eq(fetch_to_f1, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 271:28]
node _T_410 = eq(shift_f2_f1, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 271:43]
node _T_411 = and(_T_409, _T_410) @[el2_ifu_aln_ctl.scala 271:41]
node _T_412 = bits(_T_411, 0, 0) @[el2_ifu_aln_ctl.scala 271:57]
Compressed
2020-09-27 04:49:55 +08:00
node _T_413 = mux(_T_407, io.ifu_fetch_pc, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_414 = mux(_T_408, f2pc, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_415 = mux(_T_412, sf1pc, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_416 = or(_T_413, _T_414) @[Mux.scala 27:72]
node _T_417 = or(_T_416, _T_415) @[Mux.scala 27:72]
Aligner done
2020-09-23 18:27:02 +08:00
wire f1pc_in : UInt<32> @[Mux.scala 27:72]
Compressed
2020-09-27 04:49:55 +08:00
f1pc_in <= _T_417 @[Mux.scala 27:72]
ALN 1st attempt
2020-10-01 17:49:02 +08:00
node _T_418 = bits(fetch_to_f0, 0, 0) @[el2_ifu_aln_ctl.scala 273:39]
node _T_419 = bits(shift_f2_f0, 0, 0) @[el2_ifu_aln_ctl.scala 274:39]
node _T_420 = bits(shift_f1_f0, 0, 0) @[el2_ifu_aln_ctl.scala 275:39]
node _T_421 = eq(fetch_to_f0, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 276:28]
node _T_422 = eq(shift_f2_f0, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 276:43]
node _T_423 = and(_T_421, _T_422) @[el2_ifu_aln_ctl.scala 276:41]
node _T_424 = eq(shift_f1_f0, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 276:58]
node _T_425 = and(_T_423, _T_424) @[el2_ifu_aln_ctl.scala 276:56]
node _T_426 = bits(_T_425, 0, 0) @[el2_ifu_aln_ctl.scala 276:72]
Compressed
2020-09-27 04:49:55 +08:00
node _T_427 = mux(_T_418, io.ifu_fetch_pc, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_428 = mux(_T_419, f2pc, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_429 = mux(_T_420, sf1pc, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_430 = mux(_T_426, f0pc_plus1, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_431 = or(_T_427, _T_428) @[Mux.scala 27:72]
node _T_432 = or(_T_431, _T_429) @[Mux.scala 27:72]
node _T_433 = or(_T_432, _T_430) @[Mux.scala 27:72]
Aligner done
2020-09-23 18:27:02 +08:00
wire f0pc_in : UInt<32> @[Mux.scala 27:72]
Compressed
2020-09-27 04:49:55 +08:00
f0pc_in <= _T_433 @[Mux.scala 27:72]
ALN 1st attempt
2020-10-01 17:49:02 +08:00
node _T_434 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 278:40]
node _T_435 = and(f2_wr_en, _T_434) @[el2_ifu_aln_ctl.scala 278:38]
node _T_436 = bits(_T_435, 0, 0) @[el2_ifu_aln_ctl.scala 278:61]
node _T_437 = eq(f2_wr_en, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 279:6]
node _T_438 = eq(shift_f2_f1, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 279:21]
node _T_439 = and(_T_437, _T_438) @[el2_ifu_aln_ctl.scala 279:19]
node _T_440 = eq(shift_f2_f0, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 279:36]
node _T_441 = and(_T_439, _T_440) @[el2_ifu_aln_ctl.scala 279:34]
node _T_442 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 279:51]
node _T_443 = and(_T_441, _T_442) @[el2_ifu_aln_ctl.scala 279:49]
node _T_444 = bits(_T_443, 0, 0) @[el2_ifu_aln_ctl.scala 279:72]
Compressed
2020-09-27 04:49:55 +08:00
node _T_445 = mux(_T_436, io.ifu_fetch_val, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_446 = mux(_T_444, f2val, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_447 = or(_T_445, _T_446) @[Mux.scala 27:72]
wire _T_448 : UInt @[Mux.scala 27:72]
_T_448 <= _T_447 @[Mux.scala 27:72]
ALN 1st attempt
2020-10-01 17:49:02 +08:00
f2val_in <= _T_448 @[el2_ifu_aln_ctl.scala 278:12]
node _T_449 = bits(f1_shift_2B, 0, 0) @[el2_ifu_aln_ctl.scala 281:35]
node _T_450 = bits(f1val, 1, 1) @[el2_ifu_aln_ctl.scala 281:48]
node _T_451 = bits(f1_shift_2B, 0, 0) @[el2_ifu_aln_ctl.scala 281:66]
node _T_452 = eq(_T_451, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 281:53]
Compressed
2020-09-27 04:49:55 +08:00
node _T_453 = mux(_T_449, _T_450, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_454 = mux(_T_452, f1val, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_455 = or(_T_453, _T_454) @[Mux.scala 27:72]
wire _T_456 : UInt @[Mux.scala 27:72]
_T_456 <= _T_455 @[Mux.scala 27:72]
ALN 1st attempt
2020-10-01 17:49:02 +08:00
sf1val <= _T_456 @[el2_ifu_aln_ctl.scala 281:10]
node _T_457 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 283:40]
node _T_458 = and(fetch_to_f1, _T_457) @[el2_ifu_aln_ctl.scala 283:38]
node _T_459 = bits(_T_458, 0, 0) @[el2_ifu_aln_ctl.scala 283:61]
node _T_460 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 284:40]
node _T_461 = and(shift_f2_f1, _T_460) @[el2_ifu_aln_ctl.scala 284:38]
node _T_462 = bits(_T_461, 0, 0) @[el2_ifu_aln_ctl.scala 284:61]
node _T_463 = eq(fetch_to_f1, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 285:26]
node _T_464 = eq(shift_f2_f1, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 285:41]
node _T_465 = and(_T_463, _T_464) @[el2_ifu_aln_ctl.scala 285:39]
node _T_466 = eq(shift_f1_f0, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 285:56]
node _T_467 = and(_T_465, _T_466) @[el2_ifu_aln_ctl.scala 285:54]
node _T_468 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 285:71]
node _T_469 = and(_T_467, _T_468) @[el2_ifu_aln_ctl.scala 285:69]
node _T_470 = bits(_T_469, 0, 0) @[el2_ifu_aln_ctl.scala 285:92]
Compressed
2020-09-27 04:49:55 +08:00
node _T_471 = mux(_T_459, io.ifu_fetch_val, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_472 = mux(_T_462, f2val, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_473 = mux(_T_470, sf1val, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_474 = or(_T_471, _T_472) @[Mux.scala 27:72]
node _T_475 = or(_T_474, _T_473) @[Mux.scala 27:72]
wire _T_476 : UInt @[Mux.scala 27:72]
_T_476 <= _T_475 @[Mux.scala 27:72]
ALN 1st attempt
2020-10-01 17:49:02 +08:00
f1val_in <= _T_476 @[el2_ifu_aln_ctl.scala 283:12]
node _T_477 = bits(shift_2B, 0, 0) @[el2_ifu_aln_ctl.scala 287:31]
node _T_478 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 287:46]
node _T_479 = eq(shift_2B, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 287:52]
node _T_480 = eq(shift_4B, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 287:64]
node _T_481 = and(_T_479, _T_480) @[el2_ifu_aln_ctl.scala 287:62]
node _T_482 = bits(_T_481, 0, 0) @[el2_ifu_aln_ctl.scala 287:75]
Compressed
2020-09-27 04:49:55 +08:00
node _T_483 = mux(_T_477, _T_478, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_484 = mux(_T_482, f0val, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_485 = or(_T_483, _T_484) @[Mux.scala 27:72]
wire _T_486 : UInt @[Mux.scala 27:72]
_T_486 <= _T_485 @[Mux.scala 27:72]
ALN 1st attempt
2020-10-01 17:49:02 +08:00
f0val <= _T_486 @[el2_ifu_aln_ctl.scala 287:9]
node _T_487 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 289:40]
node _T_488 = and(fetch_to_f0, _T_487) @[el2_ifu_aln_ctl.scala 289:38]
node _T_489 = bits(_T_488, 0, 0) @[el2_ifu_aln_ctl.scala 289:61]
node _T_490 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 290:40]
node _T_491 = and(shift_f2_f0, _T_490) @[el2_ifu_aln_ctl.scala 290:38]
node _T_492 = bits(_T_491, 0, 0) @[el2_ifu_aln_ctl.scala 290:61]
node _T_493 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 291:40]
node _T_494 = and(shift_f1_f0, _T_493) @[el2_ifu_aln_ctl.scala 291:38]
node _T_495 = bits(_T_494, 0, 0) @[el2_ifu_aln_ctl.scala 291:67]
node _T_496 = eq(fetch_to_f0, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 292:26]
node _T_497 = eq(shift_f2_f0, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 292:41]
node _T_498 = and(_T_496, _T_497) @[el2_ifu_aln_ctl.scala 292:39]
node _T_499 = eq(shift_f1_f0, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 292:56]
node _T_500 = and(_T_498, _T_499) @[el2_ifu_aln_ctl.scala 292:54]
node _T_501 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 292:71]
node _T_502 = and(_T_500, _T_501) @[el2_ifu_aln_ctl.scala 292:69]
node _T_503 = bits(_T_502, 0, 0) @[el2_ifu_aln_ctl.scala 292:92]
Compressed
2020-09-27 04:49:55 +08:00
node _T_504 = mux(_T_489, io.ifu_fetch_val, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_505 = mux(_T_492, f2val, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_506 = mux(_T_495, sf1val, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_507 = mux(_T_503, sf0val, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_508 = or(_T_504, _T_505) @[Mux.scala 27:72]
node _T_509 = or(_T_508, _T_506) @[Mux.scala 27:72]
node _T_510 = or(_T_509, _T_507) @[Mux.scala 27:72]
wire _T_511 : UInt @[Mux.scala 27:72]
_T_511 <= _T_510 @[Mux.scala 27:72]
ALN 1st attempt
2020-10-01 17:49:02 +08:00
f0val_in <= _T_511 @[el2_ifu_aln_ctl.scala 289:12]
node _T_512 = bits(q0sel, 0, 0) @[el2_ifu_aln_ctl.scala 294:29]
node _T_513 = bits(_T_512, 0, 0) @[el2_ifu_aln_ctl.scala 294:33]
node _T_514 = bits(q0sel, 1, 1) @[el2_ifu_aln_ctl.scala 294:53]
node _T_515 = bits(_T_514, 0, 0) @[el2_ifu_aln_ctl.scala 294:57]
node _T_516 = bits(q0eff, 31, 16) @[el2_ifu_aln_ctl.scala 294:70]
Compressed
2020-09-27 04:49:55 +08:00
node _T_517 = mux(_T_513, q0eff, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_518 = mux(_T_515, _T_516, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_519 = or(_T_517, _T_518) @[Mux.scala 27:72]
wire _T_520 : UInt<32> @[Mux.scala 27:72]
_T_520 <= _T_519 @[Mux.scala 27:72]
ALN 1st attempt
2020-10-01 17:49:02 +08:00
q0final <= _T_520 @[el2_ifu_aln_ctl.scala 294:11]
node _T_521 = bits(q1sel, 0, 0) @[el2_ifu_aln_ctl.scala 296:29]
node _T_522 = bits(_T_521, 0, 0) @[el2_ifu_aln_ctl.scala 296:33]
node _T_523 = bits(q1eff, 15, 0) @[el2_ifu_aln_ctl.scala 296:46]
node _T_524 = bits(q1sel, 1, 1) @[el2_ifu_aln_ctl.scala 296:59]
node _T_525 = bits(_T_524, 0, 0) @[el2_ifu_aln_ctl.scala 296:63]
node _T_526 = bits(q1eff, 31, 16) @[el2_ifu_aln_ctl.scala 296:76]
Compressed
2020-09-27 04:49:55 +08:00
node _T_527 = mux(_T_522, _T_523, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_528 = mux(_T_525, _T_526, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_529 = or(_T_527, _T_528) @[Mux.scala 27:72]
wire _T_530 : UInt<16> @[Mux.scala 27:72]
_T_530 <= _T_529 @[Mux.scala 27:72]
ALN 1st attempt
2020-10-01 17:49:02 +08:00
q1final <= _T_530 @[el2_ifu_aln_ctl.scala 296:11]
node _T_531 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 298:30]
node _T_532 = bits(_T_531, 0, 0) @[el2_ifu_aln_ctl.scala 298:34]
node _T_533 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 298:54]
node _T_534 = eq(_T_533, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 298:48]
node _T_535 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 298:65]
node _T_536 = and(_T_534, _T_535) @[el2_ifu_aln_ctl.scala 298:58]
node _T_537 = bits(f1val, 0, 0) @[el2_ifu_aln_ctl.scala 298:82]
Compressed
2020-09-27 04:49:55 +08:00
node _T_538 = cat(_T_537, UInt<1>("h01")) @[Cat.scala 29:58]
node _T_539 = mux(_T_532, UInt<2>("h03"), UInt<1>("h00")) @[Mux.scala 27:72]
node _T_540 = mux(_T_536, _T_538, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_541 = or(_T_539, _T_540) @[Mux.scala 27:72]
wire _T_542 : UInt<2> @[Mux.scala 27:72]
_T_542 <= _T_541 @[Mux.scala 27:72]
ALN 1st attempt
2020-10-01 17:49:02 +08:00
alignval <= _T_542 @[el2_ifu_aln_ctl.scala 298:12]
node _T_543 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 300:35]
node _T_544 = bits(_T_543, 0, 0) @[el2_ifu_aln_ctl.scala 300:39]
Compressed
2020-09-27 04:49:55 +08:00
node _T_545 = bits(f0dbecc, 0, 0) @[Bitwise.scala 72:15]
node _T_546 = mux(_T_545, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
ALN 1st attempt
2020-10-01 17:49:02 +08:00
node _T_547 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 300:73]
node _T_548 = eq(_T_547, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 300:67]
node _T_549 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 300:84]
node _T_550 = and(_T_548, _T_549) @[el2_ifu_aln_ctl.scala 300:77]
node _T_551 = bits(_T_550, 0, 0) @[el2_ifu_aln_ctl.scala 300:89]
Compressed
2020-09-27 04:49:55 +08:00
node _T_552 = cat(f1dbecc, f0dbecc) @[Cat.scala 29:58]
node _T_553 = mux(_T_544, _T_546, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_554 = mux(_T_551, _T_552, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_555 = or(_T_553, _T_554) @[Mux.scala 27:72]
Aligner done
2020-09-23 18:27:02 +08:00
wire aligndbecc : UInt<2> @[Mux.scala 27:72]
Compressed
2020-09-27 04:49:55 +08:00
aligndbecc <= _T_555 @[Mux.scala 27:72]
ALN 1st attempt
2020-10-01 17:49:02 +08:00
node _T_556 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 302:35]
node _T_557 = bits(_T_556, 0, 0) @[el2_ifu_aln_ctl.scala 302:45]
node _T_558 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 302:65]
node _T_559 = eq(_T_558, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 302:59]
node _T_560 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 302:76]
node _T_561 = and(_T_559, _T_560) @[el2_ifu_aln_ctl.scala 302:69]
node _T_562 = bits(_T_561, 0, 0) @[el2_ifu_aln_ctl.scala 302:81]
node _T_563 = bits(f1brend, 0, 0) @[el2_ifu_aln_ctl.scala 302:100]
node _T_564 = bits(f0brend, 0, 0) @[el2_ifu_aln_ctl.scala 302:111]
Compressed
2020-09-27 04:49:55 +08:00
node _T_565 = cat(_T_563, _T_564) @[Cat.scala 29:58]
node _T_566 = mux(_T_557, f0brend, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_567 = mux(_T_562, _T_565, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_568 = or(_T_566, _T_567) @[Mux.scala 27:72]
Aligner done
2020-09-23 18:27:02 +08:00
wire alignbrend : UInt<2> @[Mux.scala 27:72]
Compressed
2020-09-27 04:49:55 +08:00
alignbrend <= _T_568 @[Mux.scala 27:72]
ALN 1st attempt
2020-10-01 17:49:02 +08:00
node _T_569 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 304:33]
node _T_570 = bits(_T_569, 0, 0) @[el2_ifu_aln_ctl.scala 304:43]
node _T_571 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 304:61]
node _T_572 = eq(_T_571, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 304:55]
node _T_573 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 304:72]
node _T_574 = and(_T_572, _T_573) @[el2_ifu_aln_ctl.scala 304:65]
node _T_575 = bits(_T_574, 0, 0) @[el2_ifu_aln_ctl.scala 304:77]
node _T_576 = bits(f1pc4, 0, 0) @[el2_ifu_aln_ctl.scala 304:94]
node _T_577 = bits(f0pc4, 0, 0) @[el2_ifu_aln_ctl.scala 304:103]
Compressed
2020-09-27 04:49:55 +08:00
node _T_578 = cat(_T_576, _T_577) @[Cat.scala 29:58]
node _T_579 = mux(_T_570, f0pc4, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_580 = mux(_T_575, _T_578, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_581 = or(_T_579, _T_580) @[Mux.scala 27:72]
Aligner done
2020-09-23 18:27:02 +08:00
wire alignpc4 : UInt<2> @[Mux.scala 27:72]
Compressed
2020-09-27 04:49:55 +08:00
alignpc4 <= _T_581 @[Mux.scala 27:72]
ALN 1st attempt
2020-10-01 17:49:02 +08:00
node _T_582 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 306:33]
node _T_583 = bits(_T_582, 0, 0) @[el2_ifu_aln_ctl.scala 306:43]
node _T_584 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 306:61]
node _T_585 = eq(_T_584, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 306:55]
node _T_586 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 306:72]
node _T_587 = and(_T_585, _T_586) @[el2_ifu_aln_ctl.scala 306:65]
node _T_588 = bits(_T_587, 0, 0) @[el2_ifu_aln_ctl.scala 306:77]
node _T_589 = bits(f1ret, 0, 0) @[el2_ifu_aln_ctl.scala 306:94]
node _T_590 = bits(f0ret, 0, 0) @[el2_ifu_aln_ctl.scala 306:103]
Compressed
2020-09-27 04:49:55 +08:00
node _T_591 = cat(_T_589, _T_590) @[Cat.scala 29:58]
node _T_592 = mux(_T_583, f0ret, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_593 = mux(_T_588, _T_591, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_594 = or(_T_592, _T_593) @[Mux.scala 27:72]
Aligner done
2020-09-23 18:27:02 +08:00
wire alignret : UInt<2> @[Mux.scala 27:72]
Compressed
2020-09-27 04:49:55 +08:00
alignret <= _T_594 @[Mux.scala 27:72]
ALN 1st attempt
2020-10-01 17:49:02 +08:00
node _T_595 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 308:33]
node _T_596 = bits(_T_595, 0, 0) @[el2_ifu_aln_ctl.scala 308:43]
node _T_597 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 308:61]
node _T_598 = eq(_T_597, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 308:55]
node _T_599 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 308:72]
node _T_600 = and(_T_598, _T_599) @[el2_ifu_aln_ctl.scala 308:65]
node _T_601 = bits(_T_600, 0, 0) @[el2_ifu_aln_ctl.scala 308:77]
node _T_602 = bits(f1way, 0, 0) @[el2_ifu_aln_ctl.scala 308:94]
node _T_603 = bits(f0way, 0, 0) @[el2_ifu_aln_ctl.scala 308:103]
Compressed
2020-09-27 04:49:55 +08:00
node _T_604 = cat(_T_602, _T_603) @[Cat.scala 29:58]
node _T_605 = mux(_T_596, f0way, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_606 = mux(_T_601, _T_604, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_607 = or(_T_605, _T_606) @[Mux.scala 27:72]
Aligner done
2020-09-23 18:27:02 +08:00
wire alignway : UInt<2> @[Mux.scala 27:72]
Compressed
2020-09-27 04:49:55 +08:00
alignway <= _T_607 @[Mux.scala 27:72]
ALN 1st attempt
2020-10-01 17:49:02 +08:00
node _T_608 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 310:35]
node _T_609 = bits(_T_608, 0, 0) @[el2_ifu_aln_ctl.scala 310:45]
node _T_610 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 310:65]
node _T_611 = eq(_T_610, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 310:59]
node _T_612 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 310:76]
node _T_613 = and(_T_611, _T_612) @[el2_ifu_aln_ctl.scala 310:69]
node _T_614 = bits(_T_613, 0, 0) @[el2_ifu_aln_ctl.scala 310:81]
node _T_615 = bits(f1hist1, 0, 0) @[el2_ifu_aln_ctl.scala 310:100]
node _T_616 = bits(f0hist1, 0, 0) @[el2_ifu_aln_ctl.scala 310:111]
Compressed
2020-09-27 04:49:55 +08:00
node _T_617 = cat(_T_615, _T_616) @[Cat.scala 29:58]
node _T_618 = mux(_T_609, f0hist1, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_619 = mux(_T_614, _T_617, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_620 = or(_T_618, _T_619) @[Mux.scala 27:72]
Aligner done
2020-09-23 18:27:02 +08:00
wire alignhist1 : UInt<2> @[Mux.scala 27:72]
Compressed
2020-09-27 04:49:55 +08:00
alignhist1 <= _T_620 @[Mux.scala 27:72]
ALN 1st attempt
2020-10-01 17:49:02 +08:00
node _T_621 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 312:35]
node _T_622 = bits(_T_621, 0, 0) @[el2_ifu_aln_ctl.scala 312:45]
node _T_623 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 312:65]
node _T_624 = eq(_T_623, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 312:59]
node _T_625 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 312:76]
node _T_626 = and(_T_624, _T_625) @[el2_ifu_aln_ctl.scala 312:69]
node _T_627 = bits(_T_626, 0, 0) @[el2_ifu_aln_ctl.scala 312:81]
node _T_628 = bits(f1hist0, 0, 0) @[el2_ifu_aln_ctl.scala 312:100]
node _T_629 = bits(f0hist0, 0, 0) @[el2_ifu_aln_ctl.scala 312:111]
Compressed
2020-09-27 04:49:55 +08:00
node _T_630 = cat(_T_628, _T_629) @[Cat.scala 29:58]
node _T_631 = mux(_T_622, f0hist0, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_632 = mux(_T_627, _T_630, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_633 = or(_T_631, _T_632) @[Mux.scala 27:72]
Aligner done
2020-09-23 18:27:02 +08:00
wire alignhist0 : UInt<2> @[Mux.scala 27:72]
Compressed
2020-09-27 04:49:55 +08:00
alignhist0 <= _T_633 @[Mux.scala 27:72]
ALN 1st attempt
2020-10-01 17:49:02 +08:00
node _T_634 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 314:27]
node _T_635 = eq(_T_634, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 314:21]
node _T_636 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 314:38]
node alignfromf1 = and(_T_635, _T_636) @[el2_ifu_aln_ctl.scala 314:31]
Aligner done
2020-09-23 18:27:02 +08:00
wire f1pc : UInt<31>
f1pc <= UInt<1>("h00")
ALN 1st attempt
2020-10-01 17:49:02 +08:00
node _T_637 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 318:33]
node _T_638 = bits(_T_637, 0, 0) @[el2_ifu_aln_ctl.scala 318:43]
node _T_639 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 318:67]
node _T_640 = eq(_T_639, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 318:61]
node _T_641 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 318:78]
node _T_642 = and(_T_640, _T_641) @[el2_ifu_aln_ctl.scala 318:71]
node _T_643 = bits(_T_642, 0, 0) @[el2_ifu_aln_ctl.scala 318:83]
Compressed
2020-09-27 04:49:55 +08:00
node _T_644 = mux(_T_638, f0pc_plus1, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_645 = mux(_T_643, f1pc, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_646 = or(_T_644, _T_645) @[Mux.scala 27:72]
Aligner done
2020-09-23 18:27:02 +08:00
wire secondpc : UInt<31> @[Mux.scala 27:72]
Compressed
2020-09-27 04:49:55 +08:00
secondpc <= _T_646 @[Mux.scala 27:72]
ALN 1st attempt
2020-10-01 17:49:02 +08:00
io.ifu_i0_pc <= f0pc @[el2_ifu_aln_ctl.scala 320:16]
node _T_647 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 324:47]
node _T_648 = eq(_T_647, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 324:41]
node _T_649 = and(first4B, _T_648) @[el2_ifu_aln_ctl.scala 324:39]
node _T_650 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 324:58]
node _T_651 = and(_T_649, _T_650) @[el2_ifu_aln_ctl.scala 324:51]
node _T_652 = bits(alignicaf, 0, 0) @[el2_ifu_aln_ctl.scala 324:74]
node _T_653 = eq(_T_652, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 324:64]
node _T_654 = and(_T_651, _T_653) @[el2_ifu_aln_ctl.scala 324:62]
node _T_655 = bits(aligndbecc, 0, 0) @[el2_ifu_aln_ctl.scala 324:91]
node _T_656 = eq(_T_655, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 324:80]
node _T_657 = and(_T_654, _T_656) @[el2_ifu_aln_ctl.scala 324:78]
node _T_658 = bits(_T_657, 0, 0) @[el2_ifu_aln_ctl.scala 324:96]
node _T_659 = mux(_T_658, f1ictype, f0ictype) @[el2_ifu_aln_ctl.scala 324:29]
io.ifu_i0_icaf_type <= _T_659 @[el2_ifu_aln_ctl.scala 324:23]
node _T_660 = bits(alignicaf, 1, 1) @[el2_ifu_aln_ctl.scala 326:27]
node _T_661 = bits(aligndbecc, 1, 1) @[el2_ifu_aln_ctl.scala 326:43]
node icaf_eff = or(_T_660, _T_661) @[el2_ifu_aln_ctl.scala 326:31]
node _T_662 = and(first4B, icaf_eff) @[el2_ifu_aln_ctl.scala 328:32]
node _T_663 = and(_T_662, alignfromf1) @[el2_ifu_aln_ctl.scala 328:43]
io.ifu_i0_icaf_f1 <= _T_663 @[el2_ifu_aln_ctl.scala 328:21]
node _T_664 = bits(first4B, 0, 0) @[el2_ifu_aln_ctl.scala 330:40]
node _T_665 = orr(aligndbecc) @[el2_ifu_aln_ctl.scala 330:59]
node _T_666 = bits(first2B, 0, 0) @[el2_ifu_aln_ctl.scala 330:72]
node _T_667 = bits(aligndbecc, 0, 0) @[el2_ifu_aln_ctl.scala 330:90]
Compressed
2020-09-27 04:49:55 +08:00
node _T_668 = mux(_T_664, _T_665, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_669 = mux(_T_666, _T_667, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_670 = or(_T_668, _T_669) @[Mux.scala 27:72]
wire _T_671 : UInt<1> @[Mux.scala 27:72]
_T_671 <= _T_670 @[Mux.scala 27:72]
ALN 1st attempt
2020-10-01 17:49:02 +08:00
io.ifu_i0_dbecc <= _T_671 @[el2_ifu_aln_ctl.scala 330:19]
Aligner
2020-10-07 17:21:03 +08:00
node _T_672 = bits(f0pc, 8, 1) @[el2_lib.scala 186:12]
node _T_673 = bits(f0pc, 16, 9) @[el2_lib.scala 186:50]
node _T_674 = xor(_T_672, _T_673) @[el2_lib.scala 186:46]
node _T_675 = bits(f0pc, 24, 17) @[el2_lib.scala 186:88]
node firstpc_hash = xor(_T_674, _T_675) @[el2_lib.scala 186:84]
node _T_676 = bits(secondpc, 8, 1) @[el2_lib.scala 186:12]
node _T_677 = bits(secondpc, 16, 9) @[el2_lib.scala 186:50]
node _T_678 = xor(_T_676, _T_677) @[el2_lib.scala 186:46]
node _T_679 = bits(secondpc, 24, 17) @[el2_lib.scala 186:88]
node secondpc_hash = xor(_T_678, _T_679) @[el2_lib.scala 186:84]
node _T_680 = bits(f0pc, 13, 9) @[el2_lib.scala 177:32]
node _T_681 = bits(f0pc, 18, 14) @[el2_lib.scala 177:32]
node _T_682 = bits(f0pc, 23, 19) @[el2_lib.scala 177:32]
wire _T_683 : UInt<5>[3] @[el2_lib.scala 177:24]
_T_683[0] <= _T_680 @[el2_lib.scala 177:24]
_T_683[1] <= _T_681 @[el2_lib.scala 177:24]
_T_683[2] <= _T_682 @[el2_lib.scala 177:24]
node _T_684 = xor(_T_683[0], _T_683[1]) @[el2_lib.scala 177:111]
node firstbrtag_hash = xor(_T_684, _T_683[2]) @[el2_lib.scala 177:111]
node _T_685 = bits(secondpc, 13, 9) @[el2_lib.scala 177:32]
node _T_686 = bits(secondpc, 18, 14) @[el2_lib.scala 177:32]
node _T_687 = bits(secondpc, 23, 19) @[el2_lib.scala 177:32]
wire _T_688 : UInt<5>[3] @[el2_lib.scala 177:24]
_T_688[0] <= _T_685 @[el2_lib.scala 177:24]
_T_688[1] <= _T_686 @[el2_lib.scala 177:24]
_T_688[2] <= _T_687 @[el2_lib.scala 177:24]
node _T_689 = xor(_T_688[0], _T_688[1]) @[el2_lib.scala 177:111]
node secondbrtag_hash = xor(_T_689, _T_688[2]) @[el2_lib.scala 177:111]
ALN 1st attempt
2020-10-01 17:49:02 +08:00
node _T_690 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 340:42]
node _T_691 = and(first2B, _T_690) @[el2_ifu_aln_ctl.scala 340:30]
node _T_692 = bits(alignbrend, 1, 1) @[el2_ifu_aln_ctl.scala 340:70]
node _T_693 = and(first4B, _T_692) @[el2_ifu_aln_ctl.scala 340:58]
node _T_694 = or(_T_691, _T_693) @[el2_ifu_aln_ctl.scala 340:47]
node _T_695 = bits(alignval, 1, 1) @[el2_ifu_aln_ctl.scala 340:96]
node _T_696 = and(first4B, _T_695) @[el2_ifu_aln_ctl.scala 340:86]
node _T_697 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 340:112]
node _T_698 = and(_T_696, _T_697) @[el2_ifu_aln_ctl.scala 340:100]
node _T_699 = or(_T_694, _T_698) @[el2_ifu_aln_ctl.scala 340:75]
io.i0_brp.valid <= _T_699 @[el2_ifu_aln_ctl.scala 340:19]
node _T_700 = bits(alignret, 0, 0) @[el2_ifu_aln_ctl.scala 342:39]
node _T_701 = and(first2B, _T_700) @[el2_ifu_aln_ctl.scala 342:29]
node _T_702 = bits(alignret, 1, 1) @[el2_ifu_aln_ctl.scala 342:65]
node _T_703 = and(first4B, _T_702) @[el2_ifu_aln_ctl.scala 342:55]
node _T_704 = or(_T_701, _T_703) @[el2_ifu_aln_ctl.scala 342:44]
io.i0_brp.ret <= _T_704 @[el2_ifu_aln_ctl.scala 342:17]
node _T_705 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 344:45]
node _T_706 = or(first2B, _T_705) @[el2_ifu_aln_ctl.scala 344:33]
node _T_707 = bits(_T_706, 0, 0) @[el2_ifu_aln_ctl.scala 344:50]
node _T_708 = bits(alignway, 0, 0) @[el2_ifu_aln_ctl.scala 344:66]
node _T_709 = bits(alignway, 1, 1) @[el2_ifu_aln_ctl.scala 344:80]
node _T_710 = mux(_T_707, _T_708, _T_709) @[el2_ifu_aln_ctl.scala 344:23]
io.i0_brp.way <= _T_710 @[el2_ifu_aln_ctl.scala 344:17]
node _T_711 = bits(alignhist1, 0, 0) @[el2_ifu_aln_ctl.scala 345:46]
node _T_712 = and(first2B, _T_711) @[el2_ifu_aln_ctl.scala 345:34]
node _T_713 = bits(alignhist1, 1, 1) @[el2_ifu_aln_ctl.scala 345:74]
node _T_714 = and(first4B, _T_713) @[el2_ifu_aln_ctl.scala 345:62]
node _T_715 = or(_T_712, _T_714) @[el2_ifu_aln_ctl.scala 345:51]
node _T_716 = bits(alignhist0, 0, 0) @[el2_ifu_aln_ctl.scala 346:26]
node _T_717 = and(first2B, _T_716) @[el2_ifu_aln_ctl.scala 346:14]
node _T_718 = bits(alignhist0, 1, 1) @[el2_ifu_aln_ctl.scala 346:54]
node _T_719 = and(first4B, _T_718) @[el2_ifu_aln_ctl.scala 346:42]
node _T_720 = or(_T_717, _T_719) @[el2_ifu_aln_ctl.scala 346:31]
Compressed
2020-09-27 04:49:55 +08:00
node _T_721 = cat(_T_715, _T_720) @[Cat.scala 29:58]
ALN 1st attempt
2020-10-01 17:49:02 +08:00
io.i0_brp.hist <= _T_721 @[el2_ifu_aln_ctl.scala 345:18]
node _T_722 = and(first4B, alignfromf1) @[el2_ifu_aln_ctl.scala 348:37]
node _T_723 = bits(_T_722, 0, 0) @[el2_ifu_aln_ctl.scala 348:52]
node _T_724 = mux(_T_723, f1poffset, f0poffset) @[el2_ifu_aln_ctl.scala 348:27]
io.i0_brp.toffset <= _T_724 @[el2_ifu_aln_ctl.scala 348:21]
node _T_725 = and(first4B, alignfromf1) @[el2_ifu_aln_ctl.scala 350:35]
node _T_726 = bits(_T_725, 0, 0) @[el2_ifu_aln_ctl.scala 350:50]
node _T_727 = mux(_T_726, f1prett, f0prett) @[el2_ifu_aln_ctl.scala 350:25]
io.i0_brp.prett <= _T_727 @[el2_ifu_aln_ctl.scala 350:19]
node _T_728 = bits(alignval, 1, 1) @[el2_ifu_aln_ctl.scala 352:51]
node _T_729 = and(first4B, _T_728) @[el2_ifu_aln_ctl.scala 352:41]
node _T_730 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 352:67]
node _T_731 = and(_T_729, _T_730) @[el2_ifu_aln_ctl.scala 352:55]
io.i0_brp.br_start_error <= _T_731 @[el2_ifu_aln_ctl.scala 352:29]
node _T_732 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 354:57]
node _T_733 = or(first2B, _T_732) @[el2_ifu_aln_ctl.scala 354:45]
node _T_734 = bits(_T_733, 0, 0) @[el2_ifu_aln_ctl.scala 354:62]
node _T_735 = bits(f0pc, 1, 1) @[el2_ifu_aln_ctl.scala 354:77]
node _T_736 = bits(secondpc, 1, 1) @[el2_ifu_aln_ctl.scala 354:90]
node _T_737 = mux(_T_734, _T_735, _T_736) @[el2_ifu_aln_ctl.scala 354:35]
io.i0_brp.bank <= _T_737 @[el2_ifu_aln_ctl.scala 354:29]
node _T_738 = bits(alignpc4, 0, 0) @[el2_ifu_aln_ctl.scala 356:39]
node _T_739 = and(first2B, _T_738) @[el2_ifu_aln_ctl.scala 356:29]
node _T_740 = bits(alignpc4, 1, 1) @[el2_ifu_aln_ctl.scala 356:65]
node _T_741 = and(first4B, _T_740) @[el2_ifu_aln_ctl.scala 356:55]
node i0_brp_pc4 = or(_T_739, _T_741) @[el2_ifu_aln_ctl.scala 356:44]
node _T_742 = and(io.i0_brp.valid, i0_brp_pc4) @[el2_ifu_aln_ctl.scala 358:42]
node _T_743 = and(_T_742, first2B) @[el2_ifu_aln_ctl.scala 358:56]
node _T_744 = not(i0_brp_pc4) @[el2_ifu_aln_ctl.scala 358:89]
node _T_745 = and(io.i0_brp.valid, _T_744) @[el2_ifu_aln_ctl.scala 358:87]
node _T_746 = and(_T_745, first4B) @[el2_ifu_aln_ctl.scala 358:101]
node _T_747 = or(_T_743, _T_746) @[el2_ifu_aln_ctl.scala 358:68]
io.i0_brp.br_error <= _T_747 @[el2_ifu_aln_ctl.scala 358:22]
node _T_748 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 361:50]
node _T_749 = or(first2B, _T_748) @[el2_ifu_aln_ctl.scala 361:38]
node _T_750 = bits(_T_749, 0, 0) @[el2_ifu_aln_ctl.scala 361:55]
node _T_751 = mux(_T_750, firstpc_hash, secondpc_hash) @[el2_ifu_aln_ctl.scala 361:28]
io.ifu_i0_bp_index <= _T_751 @[el2_ifu_aln_ctl.scala 361:22]
node _T_752 = and(first4B, alignfromf1) @[el2_ifu_aln_ctl.scala 363:37]
node _T_753 = bits(_T_752, 0, 0) @[el2_ifu_aln_ctl.scala 363:52]
node _T_754 = mux(_T_753, f1fghr, f0fghr) @[el2_ifu_aln_ctl.scala 363:27]
io.ifu_i0_bp_fghr <= _T_754 @[el2_ifu_aln_ctl.scala 363:21]
node _T_755 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 365:49]
node _T_756 = or(first2B, _T_755) @[el2_ifu_aln_ctl.scala 365:37]
node _T_757 = bits(_T_756, 0, 0) @[el2_ifu_aln_ctl.scala 365:54]
node _T_758 = mux(_T_757, firstbrtag_hash, secondbrtag_hash) @[el2_ifu_aln_ctl.scala 365:27]
io.ifu_i0_bp_btag <= _T_758 @[el2_ifu_aln_ctl.scala 365:21]
node _T_759 = bits(qwen, 2, 2) @[el2_ifu_aln_ctl.scala 367:44]
Aligner done
2020-09-23 18:27:02 +08:00
reg _T_760 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_759 : @[Reg.scala 28:19]
Compressed
2020-09-27 04:49:55 +08:00
_T_760 <= brdata_in @[Reg.scala 28:23]
Aligner done
2020-09-23 18:27:02 +08:00
skip @[Reg.scala 28:19]
ALN 1st attempt
2020-10-01 17:49:02 +08:00
brdata2 <= _T_760 @[el2_ifu_aln_ctl.scala 367:11]
node _T_761 = bits(qwen, 1, 1) @[el2_ifu_aln_ctl.scala 368:44]
Aligner done
2020-09-23 18:27:02 +08:00
reg _T_762 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_761 : @[Reg.scala 28:19]
Compressed
2020-09-27 04:49:55 +08:00
_T_762 <= brdata_in @[Reg.scala 28:23]
Aligner done
2020-09-23 18:27:02 +08:00
skip @[Reg.scala 28:19]
ALN 1st attempt
2020-10-01 17:49:02 +08:00
brdata1 <= _T_762 @[el2_ifu_aln_ctl.scala 368:11]
node _T_763 = bits(qwen, 0, 0) @[el2_ifu_aln_ctl.scala 369:44]
Aligner done
2020-09-23 18:27:02 +08:00
reg _T_764 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_763 : @[Reg.scala 28:19]
Compressed
2020-09-27 04:49:55 +08:00
_T_764 <= brdata_in @[Reg.scala 28:23]
Aligner done
2020-09-23 18:27:02 +08:00
skip @[Reg.scala 28:19]
ALN 1st attempt
2020-10-01 17:49:02 +08:00
brdata0 <= _T_764 @[el2_ifu_aln_ctl.scala 369:11]
node _T_765 = bits(qwen, 2, 2) @[el2_ifu_aln_ctl.scala 371:45]
Aligner done
2020-09-23 18:27:02 +08:00
reg _T_766 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_765 : @[Reg.scala 28:19]
Compressed
2020-09-27 04:49:55 +08:00
_T_766 <= misc_data_in @[Reg.scala 28:23]
Aligner done
2020-09-23 18:27:02 +08:00
skip @[Reg.scala 28:19]
ALN 1st attempt
2020-10-01 17:49:02 +08:00
misc2 <= _T_766 @[el2_ifu_aln_ctl.scala 371:9]
node _T_767 = bits(qwen, 1, 1) @[el2_ifu_aln_ctl.scala 372:45]
Aligner done
2020-09-23 18:27:02 +08:00
reg _T_768 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_767 : @[Reg.scala 28:19]
Compressed
2020-09-27 04:49:55 +08:00
_T_768 <= misc_data_in @[Reg.scala 28:23]
Aligner done
2020-09-23 18:27:02 +08:00
skip @[Reg.scala 28:19]
ALN 1st attempt
2020-10-01 17:49:02 +08:00
misc1 <= _T_768 @[el2_ifu_aln_ctl.scala 372:9]
node _T_769 = bits(qwen, 0, 0) @[el2_ifu_aln_ctl.scala 373:45]
Aligner done
2020-09-23 18:27:02 +08:00
reg _T_770 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_769 : @[Reg.scala 28:19]
Compressed
2020-09-27 04:49:55 +08:00
_T_770 <= misc_data_in @[Reg.scala 28:23]
Aligner done
2020-09-23 18:27:02 +08:00
skip @[Reg.scala 28:19]
ALN 1st attempt
2020-10-01 17:49:02 +08:00
misc0 <= _T_770 @[el2_ifu_aln_ctl.scala 373:9]
node _T_771 = bits(qwen, 2, 2) @[el2_ifu_aln_ctl.scala 375:49]
Aligner done
2020-09-23 18:27:02 +08:00
reg _T_772 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_771 : @[Reg.scala 28:19]
Compressed
2020-09-27 04:49:55 +08:00
_T_772 <= io.ifu_fetch_data_f @[Reg.scala 28:23]
Aligner done
2020-09-23 18:27:02 +08:00
skip @[Reg.scala 28:19]
ALN 1st attempt
2020-10-01 17:49:02 +08:00
q2 <= _T_772 @[el2_ifu_aln_ctl.scala 375:6]
node _T_773 = bits(qwen, 1, 1) @[el2_ifu_aln_ctl.scala 376:49]
Aligner done
2020-09-23 18:27:02 +08:00
reg _T_774 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_773 : @[Reg.scala 28:19]
Compressed
2020-09-27 04:49:55 +08:00
_T_774 <= io.ifu_fetch_data_f @[Reg.scala 28:23]
Aligner done
2020-09-23 18:27:02 +08:00
skip @[Reg.scala 28:19]
ALN 1st attempt
2020-10-01 17:49:02 +08:00
q1 <= _T_774 @[el2_ifu_aln_ctl.scala 376:6]
node _T_775 = bits(qwen, 0, 0) @[el2_ifu_aln_ctl.scala 377:49]
Aligner done
2020-09-23 18:27:02 +08:00
reg _T_776 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_775 : @[Reg.scala 28:19]
Compressed
2020-09-27 04:49:55 +08:00
_T_776 <= io.ifu_fetch_data_f @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
ALN 1st attempt
2020-10-01 17:49:02 +08:00
q0 <= _T_776 @[el2_ifu_aln_ctl.scala 377:6]
node _T_777 = bits(f2_wr_en, 0, 0) @[el2_ifu_aln_ctl.scala 379:52]
Compressed
2020-09-27 04:49:55 +08:00
reg _T_778 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_777 : @[Reg.scala 28:19]
_T_778 <= io.ifu_fetch_pc @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
ALN 1st attempt
2020-10-01 17:49:02 +08:00
f2pc <= _T_778 @[el2_ifu_aln_ctl.scala 379:8]
node _T_779 = bits(f1_shift_wr_en, 0, 0) @[el2_ifu_aln_ctl.scala 380:50]
Compressed
2020-09-27 04:49:55 +08:00
reg _T_780 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_779 : @[Reg.scala 28:19]
_T_780 <= f1pc_in @[Reg.scala 28:23]
skip @[Reg.scala 28:19]
ALN 1st attempt
2020-10-01 17:49:02 +08:00
f2pc <= _T_780 @[el2_ifu_aln_ctl.scala 380:8]
node _T_781 = bits(f0_shift_wr_en, 0, 0) @[el2_ifu_aln_ctl.scala 381:50]
Compressed
2020-09-27 04:49:55 +08:00
reg _T_782 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_781 : @[Reg.scala 28:19]
_T_782 <= f0pc_in @[Reg.scala 28:23]
Aligner done
2020-09-23 18:27:02 +08:00
skip @[Reg.scala 28:19]
ALN 1st attempt
2020-10-01 17:49:02 +08:00
f2pc <= _T_782 @[el2_ifu_aln_ctl.scala 381:8]
Aligner done
2020-09-23 18:27:02 +08:00