2020-10-06 22:30:06 +08:00
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;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
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circuit el2_ifu_iccm_mem :
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module el2_ifu_iccm_mem :
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input clock : Clock
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input reset : UInt<1>
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2020-10-08 14:44:49 +08:00
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output io : {flip clk_override : UInt<1>, flip iccm_wren : UInt<1>, flip iccm_rden : UInt<1>, flip iccm_rw_addr : UInt<15>, flip iccm_buf_correct_ecc : UInt<1>, flip iccm_correction_state : UInt<1>, flip iccm_wr_size : UInt<3>, flip iccm_wr_data : UInt<78>, iccm_rd_data : UInt<64>, iccm_rd_data_ecc : UInt<78>, flip scan_mode : UInt<1>, iccm_bank_addr : UInt[4]}
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2020-10-06 22:30:06 +08:00
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io.iccm_rd_data <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 22:19]
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io.iccm_rd_data_ecc <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 23:23]
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node _T = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 24:38]
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node _T_1 = eq(_T, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 24:43]
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node _T_2 = bits(_T_1, 0, 0) @[el2_ifu_iccm_mem.scala 24:51]
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node addr_inc = mux(_T_2, UInt<2>("h02"), UInt<2>("h01")) @[el2_ifu_iccm_mem.scala 24:21]
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node _T_3 = bits(io.iccm_rw_addr, 14, 0) @[el2_ifu_iccm_mem.scala 25:38]
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node _T_4 = add(_T_3, addr_inc) @[el2_ifu_iccm_mem.scala 25:54]
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node addr_bank_inc = tail(_T_4, 1) @[el2_ifu_iccm_mem.scala 25:54]
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wire iccm_bank_wr_data : UInt<39>[4] @[el2_ifu_iccm_mem.scala 27:35]
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node _T_5 = bits(io.iccm_wr_data, 38, 0) @[el2_ifu_iccm_mem.scala 29:50]
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iccm_bank_wr_data[0] <= _T_5 @[el2_ifu_iccm_mem.scala 29:32]
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node _T_6 = bits(io.iccm_wr_data, 77, 39) @[el2_ifu_iccm_mem.scala 30:54]
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iccm_bank_wr_data[1] <= _T_6 @[el2_ifu_iccm_mem.scala 30:36]
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node _T_7 = bits(io.iccm_wr_data, 38, 0) @[el2_ifu_iccm_mem.scala 29:50]
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iccm_bank_wr_data[2] <= _T_7 @[el2_ifu_iccm_mem.scala 29:32]
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node _T_8 = bits(io.iccm_wr_data, 77, 39) @[el2_ifu_iccm_mem.scala 30:54]
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iccm_bank_wr_data[3] <= _T_8 @[el2_ifu_iccm_mem.scala 30:36]
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2020-10-08 14:27:32 +08:00
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node _T_9 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 33:82]
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node _T_10 = eq(_T_9, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 33:100]
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node _T_11 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 33:122]
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node _T_12 = eq(_T_11, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 33:140]
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node _T_13 = or(_T_10, _T_12) @[el2_ifu_iccm_mem.scala 33:107]
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node wren_bank_0 = and(io.iccm_wren, _T_13) @[el2_ifu_iccm_mem.scala 33:64]
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node _T_14 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 33:82]
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node _T_15 = eq(_T_14, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 33:100]
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node _T_16 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 33:122]
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node _T_17 = eq(_T_16, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 33:140]
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node _T_18 = or(_T_15, _T_17) @[el2_ifu_iccm_mem.scala 33:107]
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node wren_bank_1 = and(io.iccm_wren, _T_18) @[el2_ifu_iccm_mem.scala 33:64]
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node _T_19 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 33:82]
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node _T_20 = eq(_T_19, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 33:100]
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node _T_21 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 33:122]
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node _T_22 = eq(_T_21, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 33:140]
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node _T_23 = or(_T_20, _T_22) @[el2_ifu_iccm_mem.scala 33:107]
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node wren_bank_2 = and(io.iccm_wren, _T_23) @[el2_ifu_iccm_mem.scala 33:64]
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node _T_24 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 33:82]
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node _T_25 = eq(_T_24, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 33:100]
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node _T_26 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 33:122]
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node _T_27 = eq(_T_26, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 33:140]
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node _T_28 = or(_T_25, _T_27) @[el2_ifu_iccm_mem.scala 33:107]
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node wren_bank_3 = and(io.iccm_wren, _T_28) @[el2_ifu_iccm_mem.scala 33:64]
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2020-10-08 15:38:19 +08:00
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node _T_29 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 35:81]
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node _T_30 = eq(_T_29, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 35:99]
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node _T_31 = and(io.iccm_rden, _T_30) @[el2_ifu_iccm_mem.scala 35:64]
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node _T_32 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 35:121]
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node _T_33 = eq(_T_32, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 35:139]
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node rden_bank_0 = or(_T_31, _T_33) @[el2_ifu_iccm_mem.scala 35:106]
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node _T_34 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 35:81]
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node _T_35 = eq(_T_34, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 35:99]
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node _T_36 = and(io.iccm_rden, _T_35) @[el2_ifu_iccm_mem.scala 35:64]
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node _T_37 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 35:121]
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node _T_38 = eq(_T_37, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 35:139]
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node rden_bank_1 = or(_T_36, _T_38) @[el2_ifu_iccm_mem.scala 35:106]
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node _T_39 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 35:81]
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node _T_40 = eq(_T_39, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 35:99]
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node _T_41 = and(io.iccm_rden, _T_40) @[el2_ifu_iccm_mem.scala 35:64]
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node _T_42 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 35:121]
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node _T_43 = eq(_T_42, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 35:139]
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node rden_bank_2 = or(_T_41, _T_43) @[el2_ifu_iccm_mem.scala 35:106]
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node _T_44 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 35:81]
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node _T_45 = eq(_T_44, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 35:99]
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node _T_46 = and(io.iccm_rden, _T_45) @[el2_ifu_iccm_mem.scala 35:64]
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node _T_47 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 35:121]
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node _T_48 = eq(_T_47, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 35:139]
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node rden_bank_3 = or(_T_46, _T_48) @[el2_ifu_iccm_mem.scala 35:106]
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node _T_49 = or(wren_bank_0, rden_bank_0) @[el2_ifu_iccm_mem.scala 36:72]
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node iccm_clken_0 = or(_T_49, io.clk_override) @[el2_ifu_iccm_mem.scala 36:87]
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node _T_50 = or(wren_bank_1, rden_bank_1) @[el2_ifu_iccm_mem.scala 36:72]
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node iccm_clken_1 = or(_T_50, io.clk_override) @[el2_ifu_iccm_mem.scala 36:87]
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node _T_51 = or(wren_bank_2, rden_bank_2) @[el2_ifu_iccm_mem.scala 36:72]
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node iccm_clken_2 = or(_T_51, io.clk_override) @[el2_ifu_iccm_mem.scala 36:87]
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node _T_52 = or(wren_bank_3, rden_bank_3) @[el2_ifu_iccm_mem.scala 36:72]
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node iccm_clken_3 = or(_T_52, io.clk_override) @[el2_ifu_iccm_mem.scala 36:87]
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2020-10-08 16:26:24 +08:00
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wire addr_bank : UInt<12>[4] @[el2_ifu_iccm_mem.scala 38:23]
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node _T_53 = bits(wren_bank_0, 0, 0) @[el2_ifu_iccm_mem.scala 39:68]
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node _T_54 = bits(io.iccm_rw_addr, 14, 3) @[el2_ifu_iccm_mem.scala 39:91]
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node _T_55 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 40:23]
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node _T_56 = eq(_T_55, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 40:41]
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node _T_57 = bits(addr_bank_inc, 14, 3) @[el2_ifu_iccm_mem.scala 40:62]
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node _T_58 = bits(io.iccm_rw_addr, 14, 3) @[el2_ifu_iccm_mem.scala 40:112]
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node _T_59 = mux(_T_56, _T_57, _T_58) @[el2_ifu_iccm_mem.scala 40:8]
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node _T_60 = mux(_T_53, _T_54, _T_59) @[el2_ifu_iccm_mem.scala 39:54]
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addr_bank[0] <= _T_60 @[el2_ifu_iccm_mem.scala 39:48]
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node _T_61 = bits(wren_bank_1, 0, 0) @[el2_ifu_iccm_mem.scala 39:68]
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node _T_62 = bits(io.iccm_rw_addr, 14, 3) @[el2_ifu_iccm_mem.scala 39:91]
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node _T_63 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 40:23]
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node _T_64 = eq(_T_63, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 40:41]
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node _T_65 = bits(addr_bank_inc, 14, 3) @[el2_ifu_iccm_mem.scala 40:62]
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node _T_66 = bits(io.iccm_rw_addr, 14, 3) @[el2_ifu_iccm_mem.scala 40:112]
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node _T_67 = mux(_T_64, _T_65, _T_66) @[el2_ifu_iccm_mem.scala 40:8]
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node _T_68 = mux(_T_61, _T_62, _T_67) @[el2_ifu_iccm_mem.scala 39:54]
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addr_bank[1] <= _T_68 @[el2_ifu_iccm_mem.scala 39:48]
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node _T_69 = bits(wren_bank_2, 0, 0) @[el2_ifu_iccm_mem.scala 39:68]
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node _T_70 = bits(io.iccm_rw_addr, 14, 3) @[el2_ifu_iccm_mem.scala 39:91]
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node _T_71 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 40:23]
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node _T_72 = eq(_T_71, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 40:41]
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node _T_73 = bits(addr_bank_inc, 14, 3) @[el2_ifu_iccm_mem.scala 40:62]
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node _T_74 = bits(io.iccm_rw_addr, 14, 3) @[el2_ifu_iccm_mem.scala 40:112]
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node _T_75 = mux(_T_72, _T_73, _T_74) @[el2_ifu_iccm_mem.scala 40:8]
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node _T_76 = mux(_T_69, _T_70, _T_75) @[el2_ifu_iccm_mem.scala 39:54]
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addr_bank[2] <= _T_76 @[el2_ifu_iccm_mem.scala 39:48]
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node _T_77 = bits(wren_bank_3, 0, 0) @[el2_ifu_iccm_mem.scala 39:68]
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node _T_78 = bits(io.iccm_rw_addr, 14, 3) @[el2_ifu_iccm_mem.scala 39:91]
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node _T_79 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 40:23]
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node _T_80 = eq(_T_79, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 40:41]
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node _T_81 = bits(addr_bank_inc, 14, 3) @[el2_ifu_iccm_mem.scala 40:62]
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node _T_82 = bits(io.iccm_rw_addr, 14, 3) @[el2_ifu_iccm_mem.scala 40:112]
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node _T_83 = mux(_T_80, _T_81, _T_82) @[el2_ifu_iccm_mem.scala 40:8]
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node _T_84 = mux(_T_77, _T_78, _T_83) @[el2_ifu_iccm_mem.scala 39:54]
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addr_bank[3] <= _T_84 @[el2_ifu_iccm_mem.scala 39:48]
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2020-10-08 16:34:16 +08:00
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smem _T_85 : UInt<39>[4096], undefined @[el2_ifu_iccm_mem.scala 43:59]
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smem _T_86 : UInt<39>[4096], undefined @[el2_ifu_iccm_mem.scala 43:59]
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smem _T_87 : UInt<39>[4096], undefined @[el2_ifu_iccm_mem.scala 43:59]
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smem _T_88 : UInt<39>[4096], undefined @[el2_ifu_iccm_mem.scala 43:59]
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2020-10-08 16:26:24 +08:00
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node _T_89 = and(iccm_clken_0, wren_bank_0) @[el2_ifu_iccm_mem.scala 47:68]
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node _T_90 = and(iccm_clken_1, wren_bank_1) @[el2_ifu_iccm_mem.scala 47:68]
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node _T_91 = and(iccm_clken_2, wren_bank_2) @[el2_ifu_iccm_mem.scala 47:68]
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node _T_92 = and(iccm_clken_3, wren_bank_3) @[el2_ifu_iccm_mem.scala 47:68]
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wire write_vec : UInt<1>[4] @[el2_ifu_iccm_mem.scala 47:51]
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write_vec[0] <= _T_89 @[el2_ifu_iccm_mem.scala 47:51]
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write_vec[1] <= _T_90 @[el2_ifu_iccm_mem.scala 47:51]
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write_vec[2] <= _T_91 @[el2_ifu_iccm_mem.scala 47:51]
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write_vec[3] <= _T_92 @[el2_ifu_iccm_mem.scala 47:51]
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node _T_93 = eq(wren_bank_0, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 48:72]
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node _T_94 = and(iccm_clken_0, _T_93) @[el2_ifu_iccm_mem.scala 48:70]
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node _T_95 = eq(wren_bank_1, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 48:72]
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node _T_96 = and(iccm_clken_1, _T_95) @[el2_ifu_iccm_mem.scala 48:70]
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node _T_97 = eq(wren_bank_2, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 48:72]
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node _T_98 = and(iccm_clken_2, _T_97) @[el2_ifu_iccm_mem.scala 48:70]
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node _T_99 = eq(wren_bank_3, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 48:72]
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node _T_100 = and(iccm_clken_3, _T_99) @[el2_ifu_iccm_mem.scala 48:70]
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wire read_enable : UInt<1>[4] @[el2_ifu_iccm_mem.scala 48:53]
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read_enable[0] <= _T_94 @[el2_ifu_iccm_mem.scala 48:53]
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read_enable[1] <= _T_96 @[el2_ifu_iccm_mem.scala 48:53]
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read_enable[2] <= _T_98 @[el2_ifu_iccm_mem.scala 48:53]
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read_enable[3] <= _T_100 @[el2_ifu_iccm_mem.scala 48:53]
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wire iccm_bank_dout : UInt<39>[4] @[el2_ifu_iccm_mem.scala 50:28]
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when write_vec[0] : @[el2_ifu_iccm_mem.scala 54:54]
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infer mport _T_101 = _T_85[addr_bank[0]], clock @[el2_ifu_iccm_mem.scala 54:66]
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_T_101 <= iccm_bank_wr_data[0] @[el2_ifu_iccm_mem.scala 54:81]
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skip @[el2_ifu_iccm_mem.scala 54:54]
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when write_vec[1] : @[el2_ifu_iccm_mem.scala 54:54]
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infer mport _T_102 = _T_86[addr_bank[1]], clock @[el2_ifu_iccm_mem.scala 54:66]
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_T_102 <= iccm_bank_wr_data[1] @[el2_ifu_iccm_mem.scala 54:81]
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skip @[el2_ifu_iccm_mem.scala 54:54]
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when write_vec[2] : @[el2_ifu_iccm_mem.scala 54:54]
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infer mport _T_103 = _T_87[addr_bank[2]], clock @[el2_ifu_iccm_mem.scala 54:66]
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_T_103 <= iccm_bank_wr_data[2] @[el2_ifu_iccm_mem.scala 54:81]
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skip @[el2_ifu_iccm_mem.scala 54:54]
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when write_vec[3] : @[el2_ifu_iccm_mem.scala 54:54]
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infer mport _T_104 = _T_88[addr_bank[3]], clock @[el2_ifu_iccm_mem.scala 54:66]
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_T_104 <= iccm_bank_wr_data[3] @[el2_ifu_iccm_mem.scala 54:81]
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skip @[el2_ifu_iccm_mem.scala 54:54]
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2020-10-08 16:37:41 +08:00
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wire _T_105 : UInt @[el2_ifu_iccm_mem.scala 56:72]
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_T_105 is invalid @[el2_ifu_iccm_mem.scala 56:72]
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when read_enable[0] : @[el2_ifu_iccm_mem.scala 56:72]
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_T_105 <= addr_bank[0] @[el2_ifu_iccm_mem.scala 56:72]
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node _T_106 = or(_T_105, UInt<12>("h00")) @[el2_ifu_iccm_mem.scala 56:72]
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node _T_107 = bits(_T_106, 11, 0) @[el2_ifu_iccm_mem.scala 56:72]
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read mport _T_108 = _T_85[_T_107], clock @[el2_ifu_iccm_mem.scala 56:72]
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skip @[el2_ifu_iccm_mem.scala 56:72]
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iccm_bank_dout[0] <= _T_108 @[el2_ifu_iccm_mem.scala 56:53]
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wire _T_109 : UInt @[el2_ifu_iccm_mem.scala 56:72]
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_T_109 is invalid @[el2_ifu_iccm_mem.scala 56:72]
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when read_enable[1] : @[el2_ifu_iccm_mem.scala 56:72]
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_T_109 <= addr_bank[1] @[el2_ifu_iccm_mem.scala 56:72]
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node _T_110 = or(_T_109, UInt<12>("h00")) @[el2_ifu_iccm_mem.scala 56:72]
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node _T_111 = bits(_T_110, 11, 0) @[el2_ifu_iccm_mem.scala 56:72]
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read mport _T_112 = _T_86[_T_111], clock @[el2_ifu_iccm_mem.scala 56:72]
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skip @[el2_ifu_iccm_mem.scala 56:72]
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iccm_bank_dout[1] <= _T_112 @[el2_ifu_iccm_mem.scala 56:53]
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wire _T_113 : UInt @[el2_ifu_iccm_mem.scala 56:72]
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_T_113 is invalid @[el2_ifu_iccm_mem.scala 56:72]
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when read_enable[2] : @[el2_ifu_iccm_mem.scala 56:72]
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_T_113 <= addr_bank[2] @[el2_ifu_iccm_mem.scala 56:72]
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node _T_114 = or(_T_113, UInt<12>("h00")) @[el2_ifu_iccm_mem.scala 56:72]
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node _T_115 = bits(_T_114, 11, 0) @[el2_ifu_iccm_mem.scala 56:72]
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read mport _T_116 = _T_87[_T_115], clock @[el2_ifu_iccm_mem.scala 56:72]
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skip @[el2_ifu_iccm_mem.scala 56:72]
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iccm_bank_dout[2] <= _T_116 @[el2_ifu_iccm_mem.scala 56:53]
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wire _T_117 : UInt @[el2_ifu_iccm_mem.scala 56:72]
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_T_117 is invalid @[el2_ifu_iccm_mem.scala 56:72]
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when read_enable[3] : @[el2_ifu_iccm_mem.scala 56:72]
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_T_117 <= addr_bank[3] @[el2_ifu_iccm_mem.scala 56:72]
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node _T_118 = or(_T_117, UInt<12>("h00")) @[el2_ifu_iccm_mem.scala 56:72]
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node _T_119 = bits(_T_118, 11, 0) @[el2_ifu_iccm_mem.scala 56:72]
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read mport _T_120 = _T_88[_T_119], clock @[el2_ifu_iccm_mem.scala 56:72]
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skip @[el2_ifu_iccm_mem.scala 56:72]
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iccm_bank_dout[3] <= _T_120 @[el2_ifu_iccm_mem.scala 56:53]
|
2020-10-08 16:26:24 +08:00
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io.iccm_bank_addr[0] <= addr_bank[0] @[el2_ifu_iccm_mem.scala 61:21]
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io.iccm_bank_addr[1] <= addr_bank[1] @[el2_ifu_iccm_mem.scala 61:21]
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io.iccm_bank_addr[2] <= addr_bank[2] @[el2_ifu_iccm_mem.scala 61:21]
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io.iccm_bank_addr[3] <= addr_bank[3] @[el2_ifu_iccm_mem.scala 61:21]
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2020-10-06 22:30:06 +08:00
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wire redundant_valid : UInt<2>
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|
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redundant_valid <= UInt<1>("h00")
|
2020-10-08 16:26:24 +08:00
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wire redundant_address : UInt<14>[2] @[el2_ifu_iccm_mem.scala 67:31]
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redundant_address[0] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 68:21]
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redundant_address[1] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 68:21]
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2020-10-08 16:37:41 +08:00
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node _T_121 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 70:67]
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node _T_122 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 70:90]
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node _T_123 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 70:128]
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node _T_124 = eq(_T_122, _T_123) @[el2_ifu_iccm_mem.scala 70:105]
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node _T_125 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 70:163]
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node _T_126 = eq(_T_125, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 70:169]
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node _T_127 = and(_T_124, _T_126) @[el2_ifu_iccm_mem.scala 70:145]
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node _T_128 = and(_T_121, _T_127) @[el2_ifu_iccm_mem.scala 70:71]
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node _T_129 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 71:22]
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node _T_130 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 71:60]
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node _T_131 = eq(_T_129, _T_130) @[el2_ifu_iccm_mem.scala 71:37]
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node _T_132 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 71:93]
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node _T_133 = eq(_T_132, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 71:99]
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node _T_134 = and(_T_131, _T_133) @[el2_ifu_iccm_mem.scala 71:77]
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node _T_135 = or(_T_128, _T_134) @[el2_ifu_iccm_mem.scala 70:179]
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node _T_136 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 70:67]
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node _T_137 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 70:90]
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node _T_138 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 70:128]
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node _T_139 = eq(_T_137, _T_138) @[el2_ifu_iccm_mem.scala 70:105]
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node _T_140 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 70:163]
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node _T_141 = eq(_T_140, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 70:169]
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node _T_142 = and(_T_139, _T_141) @[el2_ifu_iccm_mem.scala 70:145]
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node _T_143 = and(_T_136, _T_142) @[el2_ifu_iccm_mem.scala 70:71]
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node _T_144 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 71:22]
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node _T_145 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 71:60]
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node _T_146 = eq(_T_144, _T_145) @[el2_ifu_iccm_mem.scala 71:37]
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node _T_147 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 71:93]
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node _T_148 = eq(_T_147, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 71:99]
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node _T_149 = and(_T_146, _T_148) @[el2_ifu_iccm_mem.scala 71:77]
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node _T_150 = or(_T_143, _T_149) @[el2_ifu_iccm_mem.scala 70:179]
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node _T_151 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 70:67]
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node _T_152 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 70:90]
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node _T_153 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 70:128]
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node _T_154 = eq(_T_152, _T_153) @[el2_ifu_iccm_mem.scala 70:105]
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node _T_155 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 70:163]
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node _T_156 = eq(_T_155, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 70:169]
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node _T_157 = and(_T_154, _T_156) @[el2_ifu_iccm_mem.scala 70:145]
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node _T_158 = and(_T_151, _T_157) @[el2_ifu_iccm_mem.scala 70:71]
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node _T_159 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 71:22]
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node _T_160 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 71:60]
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node _T_161 = eq(_T_159, _T_160) @[el2_ifu_iccm_mem.scala 71:37]
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node _T_162 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 71:93]
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node _T_163 = eq(_T_162, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 71:99]
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node _T_164 = and(_T_161, _T_163) @[el2_ifu_iccm_mem.scala 71:77]
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node _T_165 = or(_T_158, _T_164) @[el2_ifu_iccm_mem.scala 70:179]
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node _T_166 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 70:67]
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node _T_167 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 70:90]
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node _T_168 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 70:128]
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node _T_169 = eq(_T_167, _T_168) @[el2_ifu_iccm_mem.scala 70:105]
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node _T_170 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 70:163]
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node _T_171 = eq(_T_170, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 70:169]
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node _T_172 = and(_T_169, _T_171) @[el2_ifu_iccm_mem.scala 70:145]
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node _T_173 = and(_T_166, _T_172) @[el2_ifu_iccm_mem.scala 70:71]
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node _T_174 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 71:22]
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|
node _T_175 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 71:60]
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|
node _T_176 = eq(_T_174, _T_175) @[el2_ifu_iccm_mem.scala 71:37]
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node _T_177 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 71:93]
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node _T_178 = eq(_T_177, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 71:99]
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node _T_179 = and(_T_176, _T_178) @[el2_ifu_iccm_mem.scala 71:77]
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node _T_180 = or(_T_173, _T_179) @[el2_ifu_iccm_mem.scala 70:179]
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node _T_181 = cat(_T_180, _T_165) @[Cat.scala 29:58]
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node _T_182 = cat(_T_181, _T_150) @[Cat.scala 29:58]
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node sel_red1 = cat(_T_182, _T_135) @[Cat.scala 29:58]
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node _T_183 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 72:67]
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|
node _T_184 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 72:90]
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node _T_185 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 72:128]
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node _T_186 = eq(_T_184, _T_185) @[el2_ifu_iccm_mem.scala 72:105]
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node _T_187 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 72:163]
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node _T_188 = eq(_T_187, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 72:169]
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node _T_189 = and(_T_186, _T_188) @[el2_ifu_iccm_mem.scala 72:145]
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node _T_190 = and(_T_183, _T_189) @[el2_ifu_iccm_mem.scala 72:71]
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|
node _T_191 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 73:22]
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|
node _T_192 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 73:60]
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node _T_193 = eq(_T_191, _T_192) @[el2_ifu_iccm_mem.scala 73:37]
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node _T_194 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 73:93]
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|
node _T_195 = eq(_T_194, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 73:99]
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node _T_196 = and(_T_193, _T_195) @[el2_ifu_iccm_mem.scala 73:77]
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node _T_197 = or(_T_190, _T_196) @[el2_ifu_iccm_mem.scala 72:179]
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|
node _T_198 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 72:67]
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|
node _T_199 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 72:90]
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|
node _T_200 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 72:128]
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|
node _T_201 = eq(_T_199, _T_200) @[el2_ifu_iccm_mem.scala 72:105]
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|
node _T_202 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 72:163]
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|
node _T_203 = eq(_T_202, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 72:169]
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|
node _T_204 = and(_T_201, _T_203) @[el2_ifu_iccm_mem.scala 72:145]
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|
node _T_205 = and(_T_198, _T_204) @[el2_ifu_iccm_mem.scala 72:71]
|
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|
node _T_206 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 73:22]
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|
node _T_207 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 73:60]
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|
node _T_208 = eq(_T_206, _T_207) @[el2_ifu_iccm_mem.scala 73:37]
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|
node _T_209 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 73:93]
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|
node _T_210 = eq(_T_209, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 73:99]
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|
node _T_211 = and(_T_208, _T_210) @[el2_ifu_iccm_mem.scala 73:77]
|
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|
node _T_212 = or(_T_205, _T_211) @[el2_ifu_iccm_mem.scala 72:179]
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|
node _T_213 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 72:67]
|
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|
|
node _T_214 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 72:90]
|
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|
node _T_215 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 72:128]
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|
node _T_216 = eq(_T_214, _T_215) @[el2_ifu_iccm_mem.scala 72:105]
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|
node _T_217 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 72:163]
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|
node _T_218 = eq(_T_217, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 72:169]
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|
node _T_219 = and(_T_216, _T_218) @[el2_ifu_iccm_mem.scala 72:145]
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|
node _T_220 = and(_T_213, _T_219) @[el2_ifu_iccm_mem.scala 72:71]
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|
node _T_221 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 73:22]
|
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|
|
node _T_222 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 73:60]
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|
|
node _T_223 = eq(_T_221, _T_222) @[el2_ifu_iccm_mem.scala 73:37]
|
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|
node _T_224 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 73:93]
|
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|
node _T_225 = eq(_T_224, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 73:99]
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|
node _T_226 = and(_T_223, _T_225) @[el2_ifu_iccm_mem.scala 73:77]
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|
node _T_227 = or(_T_220, _T_226) @[el2_ifu_iccm_mem.scala 72:179]
|
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|
node _T_228 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 72:67]
|
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|
node _T_229 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 72:90]
|
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|
node _T_230 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 72:128]
|
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|
node _T_231 = eq(_T_229, _T_230) @[el2_ifu_iccm_mem.scala 72:105]
|
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|
node _T_232 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 72:163]
|
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|
node _T_233 = eq(_T_232, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 72:169]
|
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|
node _T_234 = and(_T_231, _T_233) @[el2_ifu_iccm_mem.scala 72:145]
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node _T_235 = and(_T_228, _T_234) @[el2_ifu_iccm_mem.scala 72:71]
|
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node _T_236 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 73:22]
|
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|
node _T_237 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 73:60]
|
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|
node _T_238 = eq(_T_236, _T_237) @[el2_ifu_iccm_mem.scala 73:37]
|
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|
node _T_239 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 73:93]
|
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node _T_240 = eq(_T_239, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 73:99]
|
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node _T_241 = and(_T_238, _T_240) @[el2_ifu_iccm_mem.scala 73:77]
|
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node _T_242 = or(_T_235, _T_241) @[el2_ifu_iccm_mem.scala 72:179]
|
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node _T_243 = cat(_T_242, _T_227) @[Cat.scala 29:58]
|
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|
node _T_244 = cat(_T_243, _T_212) @[Cat.scala 29:58]
|
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|
|
node sel_red0 = cat(_T_244, _T_197) @[Cat.scala 29:58]
|
2020-10-08 16:26:24 +08:00
|
|
|
reg sel_red0_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 75:27]
|
|
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|
|
sel_red0_q <= sel_red0 @[el2_ifu_iccm_mem.scala 75:27]
|
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|
|
reg sel_red1_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 76:27]
|
|
|
|
|
sel_red1_q <= sel_red1 @[el2_ifu_iccm_mem.scala 76:27]
|
|
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|
|
wire redundant_data : UInt<39>[2] @[el2_ifu_iccm_mem.scala 77:28]
|
|
|
|
|
redundant_data[0] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 78:18]
|
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|
|
redundant_data[1] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 78:18]
|
2020-10-08 16:37:41 +08:00
|
|
|
node _T_245 = bits(sel_red1_q, 0, 0) @[el2_ifu_iccm_mem.scala 80:47]
|
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|
|
node _T_246 = bits(_T_245, 0, 0) @[el2_ifu_iccm_mem.scala 80:51]
|
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|
node _T_247 = bits(sel_red0_q, 0, 0) @[el2_ifu_iccm_mem.scala 81:47]
|
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|
node _T_248 = bits(_T_247, 0, 0) @[el2_ifu_iccm_mem.scala 81:51]
|
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|
node _T_249 = bits(sel_red0_q, 0, 0) @[el2_ifu_iccm_mem.scala 82:47]
|
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|
node _T_250 = not(_T_249) @[el2_ifu_iccm_mem.scala 82:36]
|
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|
node _T_251 = bits(sel_red1_q, 0, 0) @[el2_ifu_iccm_mem.scala 82:64]
|
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|
node _T_252 = not(_T_251) @[el2_ifu_iccm_mem.scala 82:53]
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|
node _T_253 = and(_T_250, _T_252) @[el2_ifu_iccm_mem.scala 82:51]
|
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node _T_254 = bits(_T_253, 0, 0) @[el2_ifu_iccm_mem.scala 82:69]
|
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node _T_255 = mux(_T_246, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72]
|
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|
node _T_256 = mux(_T_248, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72]
|
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|
node _T_257 = mux(_T_254, iccm_bank_dout[0], UInt<1>("h00")) @[Mux.scala 27:72]
|
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|
node _T_258 = or(_T_255, _T_256) @[Mux.scala 27:72]
|
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|
|
node _T_259 = or(_T_258, _T_257) @[Mux.scala 27:72]
|
2020-10-06 22:30:06 +08:00
|
|
|
wire iccm_bank_dout_fn_0 : UInt<39> @[Mux.scala 27:72]
|
2020-10-08 16:37:41 +08:00
|
|
|
iccm_bank_dout_fn_0 <= _T_259 @[Mux.scala 27:72]
|
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|
|
node _T_260 = bits(sel_red1_q, 1, 1) @[el2_ifu_iccm_mem.scala 80:47]
|
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|
node _T_261 = bits(_T_260, 0, 0) @[el2_ifu_iccm_mem.scala 80:51]
|
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|
node _T_262 = bits(sel_red0_q, 1, 1) @[el2_ifu_iccm_mem.scala 81:47]
|
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|
node _T_263 = bits(_T_262, 0, 0) @[el2_ifu_iccm_mem.scala 81:51]
|
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|
node _T_264 = bits(sel_red0_q, 1, 1) @[el2_ifu_iccm_mem.scala 82:47]
|
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|
|
node _T_265 = not(_T_264) @[el2_ifu_iccm_mem.scala 82:36]
|
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|
node _T_266 = bits(sel_red1_q, 1, 1) @[el2_ifu_iccm_mem.scala 82:64]
|
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|
|
node _T_267 = not(_T_266) @[el2_ifu_iccm_mem.scala 82:53]
|
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|
|
node _T_268 = and(_T_265, _T_267) @[el2_ifu_iccm_mem.scala 82:51]
|
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|
|
node _T_269 = bits(_T_268, 0, 0) @[el2_ifu_iccm_mem.scala 82:69]
|
|
|
|
|
node _T_270 = mux(_T_261, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_271 = mux(_T_263, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_272 = mux(_T_269, iccm_bank_dout[1], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_273 = or(_T_270, _T_271) @[Mux.scala 27:72]
|
|
|
|
|
node _T_274 = or(_T_273, _T_272) @[Mux.scala 27:72]
|
2020-10-06 22:30:06 +08:00
|
|
|
wire iccm_bank_dout_fn_1 : UInt<39> @[Mux.scala 27:72]
|
2020-10-08 16:37:41 +08:00
|
|
|
iccm_bank_dout_fn_1 <= _T_274 @[Mux.scala 27:72]
|
|
|
|
|
node _T_275 = bits(sel_red1_q, 2, 2) @[el2_ifu_iccm_mem.scala 80:47]
|
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|
|
node _T_276 = bits(_T_275, 0, 0) @[el2_ifu_iccm_mem.scala 80:51]
|
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|
|
node _T_277 = bits(sel_red0_q, 2, 2) @[el2_ifu_iccm_mem.scala 81:47]
|
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|
|
node _T_278 = bits(_T_277, 0, 0) @[el2_ifu_iccm_mem.scala 81:51]
|
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|
|
node _T_279 = bits(sel_red0_q, 2, 2) @[el2_ifu_iccm_mem.scala 82:47]
|
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|
|
|
node _T_280 = not(_T_279) @[el2_ifu_iccm_mem.scala 82:36]
|
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|
|
node _T_281 = bits(sel_red1_q, 2, 2) @[el2_ifu_iccm_mem.scala 82:64]
|
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|
|
|
node _T_282 = not(_T_281) @[el2_ifu_iccm_mem.scala 82:53]
|
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|
|
node _T_283 = and(_T_280, _T_282) @[el2_ifu_iccm_mem.scala 82:51]
|
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|
|
node _T_284 = bits(_T_283, 0, 0) @[el2_ifu_iccm_mem.scala 82:69]
|
|
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|
|
node _T_285 = mux(_T_276, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_286 = mux(_T_278, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_287 = mux(_T_284, iccm_bank_dout[2], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_288 = or(_T_285, _T_286) @[Mux.scala 27:72]
|
|
|
|
|
node _T_289 = or(_T_288, _T_287) @[Mux.scala 27:72]
|
2020-10-06 22:30:06 +08:00
|
|
|
wire iccm_bank_dout_fn_2 : UInt<39> @[Mux.scala 27:72]
|
2020-10-08 16:37:41 +08:00
|
|
|
iccm_bank_dout_fn_2 <= _T_289 @[Mux.scala 27:72]
|
|
|
|
|
node _T_290 = bits(sel_red1_q, 3, 3) @[el2_ifu_iccm_mem.scala 80:47]
|
|
|
|
|
node _T_291 = bits(_T_290, 0, 0) @[el2_ifu_iccm_mem.scala 80:51]
|
|
|
|
|
node _T_292 = bits(sel_red0_q, 3, 3) @[el2_ifu_iccm_mem.scala 81:47]
|
|
|
|
|
node _T_293 = bits(_T_292, 0, 0) @[el2_ifu_iccm_mem.scala 81:51]
|
|
|
|
|
node _T_294 = bits(sel_red0_q, 3, 3) @[el2_ifu_iccm_mem.scala 82:47]
|
|
|
|
|
node _T_295 = not(_T_294) @[el2_ifu_iccm_mem.scala 82:36]
|
|
|
|
|
node _T_296 = bits(sel_red1_q, 3, 3) @[el2_ifu_iccm_mem.scala 82:64]
|
|
|
|
|
node _T_297 = not(_T_296) @[el2_ifu_iccm_mem.scala 82:53]
|
|
|
|
|
node _T_298 = and(_T_295, _T_297) @[el2_ifu_iccm_mem.scala 82:51]
|
|
|
|
|
node _T_299 = bits(_T_298, 0, 0) @[el2_ifu_iccm_mem.scala 82:69]
|
|
|
|
|
node _T_300 = mux(_T_291, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_301 = mux(_T_293, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_302 = mux(_T_299, iccm_bank_dout[3], UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_303 = or(_T_300, _T_301) @[Mux.scala 27:72]
|
|
|
|
|
node _T_304 = or(_T_303, _T_302) @[Mux.scala 27:72]
|
2020-10-06 22:30:06 +08:00
|
|
|
wire iccm_bank_dout_fn_3 : UInt<39> @[Mux.scala 27:72]
|
2020-10-08 16:37:41 +08:00
|
|
|
iccm_bank_dout_fn_3 <= _T_304 @[Mux.scala 27:72]
|
2020-10-06 22:30:06 +08:00
|
|
|
wire redundant_lru : UInt<1>
|
|
|
|
|
redundant_lru <= UInt<1>("h00")
|
2020-10-08 16:37:41 +08:00
|
|
|
node _T_305 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 84:20]
|
|
|
|
|
node r0_addr_en = and(_T_305, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 84:35]
|
2020-10-08 16:26:24 +08:00
|
|
|
node r1_addr_en = and(redundant_lru, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 85:35]
|
2020-10-08 16:37:41 +08:00
|
|
|
node _T_306 = orr(sel_red0) @[el2_ifu_iccm_mem.scala 86:63]
|
|
|
|
|
node _T_307 = orr(sel_red1) @[el2_ifu_iccm_mem.scala 86:78]
|
|
|
|
|
node _T_308 = or(_T_306, _T_307) @[el2_ifu_iccm_mem.scala 86:67]
|
|
|
|
|
node _T_309 = and(_T_308, io.iccm_rden) @[el2_ifu_iccm_mem.scala 86:83]
|
|
|
|
|
node _T_310 = and(_T_309, io.iccm_correction_state) @[el2_ifu_iccm_mem.scala 86:98]
|
|
|
|
|
node redundant_lru_en = or(io.iccm_buf_correct_ecc, _T_310) @[el2_ifu_iccm_mem.scala 86:50]
|
|
|
|
|
node _T_311 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 87:55]
|
|
|
|
|
node _T_312 = orr(sel_red0) @[el2_ifu_iccm_mem.scala 87:84]
|
|
|
|
|
node _T_313 = mux(_T_312, UInt<1>("h01"), UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 87:74]
|
|
|
|
|
node redundant_lru_in = mux(io.iccm_buf_correct_ecc, _T_311, _T_313) @[el2_ifu_iccm_mem.scala 87:29]
|
|
|
|
|
reg _T_314 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
2020-10-06 22:30:06 +08:00
|
|
|
when redundant_lru_en : @[Reg.scala 28:19]
|
2020-10-08 16:37:41 +08:00
|
|
|
_T_314 <= redundant_lru_in @[Reg.scala 28:23]
|
2020-10-06 22:30:06 +08:00
|
|
|
skip @[Reg.scala 28:19]
|
2020-10-08 16:37:41 +08:00
|
|
|
redundant_lru <= _T_314 @[el2_ifu_iccm_mem.scala 88:17]
|
|
|
|
|
node _T_315 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 89:52]
|
|
|
|
|
reg _T_316 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
2020-10-06 22:30:06 +08:00
|
|
|
when r0_addr_en : @[Reg.scala 28:19]
|
2020-10-08 16:37:41 +08:00
|
|
|
_T_316 <= _T_315 @[Reg.scala 28:23]
|
2020-10-06 22:30:06 +08:00
|
|
|
skip @[Reg.scala 28:19]
|
2020-10-08 16:37:41 +08:00
|
|
|
redundant_address[0] <= _T_316 @[el2_ifu_iccm_mem.scala 89:24]
|
|
|
|
|
node _T_317 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 90:52]
|
|
|
|
|
node _T_318 = bits(r1_addr_en, 0, 0) @[el2_ifu_iccm_mem.scala 90:85]
|
|
|
|
|
reg _T_319 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_318 : @[Reg.scala 28:19]
|
|
|
|
|
_T_319 <= _T_317 @[Reg.scala 28:23]
|
2020-10-06 22:30:06 +08:00
|
|
|
skip @[Reg.scala 28:19]
|
2020-10-08 16:37:41 +08:00
|
|
|
redundant_address[1] <= _T_319 @[el2_ifu_iccm_mem.scala 90:24]
|
|
|
|
|
node _T_320 = bits(r1_addr_en, 0, 0) @[el2_ifu_iccm_mem.scala 91:57]
|
|
|
|
|
reg _T_321 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
|
|
|
|
when _T_320 : @[Reg.scala 28:19]
|
|
|
|
|
_T_321 <= UInt<1>("h01") @[Reg.scala 28:23]
|
2020-10-06 22:30:06 +08:00
|
|
|
skip @[Reg.scala 28:19]
|
2020-10-08 16:37:41 +08:00
|
|
|
reg _T_322 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
2020-10-06 22:30:06 +08:00
|
|
|
when r0_addr_en : @[Reg.scala 28:19]
|
2020-10-08 16:37:41 +08:00
|
|
|
_T_322 <= UInt<1>("h01") @[Reg.scala 28:23]
|
2020-10-06 22:30:06 +08:00
|
|
|
skip @[Reg.scala 28:19]
|
2020-10-08 16:37:41 +08:00
|
|
|
node _T_323 = cat(_T_321, _T_322) @[Cat.scala 29:58]
|
|
|
|
|
redundant_valid <= _T_323 @[el2_ifu_iccm_mem.scala 91:19]
|
|
|
|
|
node _T_324 = bits(io.iccm_rw_addr, 14, 2) @[el2_ifu_iccm_mem.scala 93:45]
|
|
|
|
|
node _T_325 = bits(redundant_address[0], 13, 1) @[el2_ifu_iccm_mem.scala 93:85]
|
|
|
|
|
node _T_326 = eq(_T_324, _T_325) @[el2_ifu_iccm_mem.scala 93:61]
|
|
|
|
|
node _T_327 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 94:22]
|
|
|
|
|
node _T_328 = bits(redundant_address[0], 0, 0) @[el2_ifu_iccm_mem.scala 94:48]
|
|
|
|
|
node _T_329 = and(_T_327, _T_328) @[el2_ifu_iccm_mem.scala 94:26]
|
|
|
|
|
node _T_330 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 94:70]
|
|
|
|
|
node _T_331 = eq(_T_330, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 94:75]
|
|
|
|
|
node _T_332 = or(_T_329, _T_331) @[el2_ifu_iccm_mem.scala 94:52]
|
|
|
|
|
node _T_333 = and(_T_326, _T_332) @[el2_ifu_iccm_mem.scala 93:102]
|
|
|
|
|
node _T_334 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 94:101]
|
|
|
|
|
node _T_335 = and(_T_333, _T_334) @[el2_ifu_iccm_mem.scala 94:84]
|
|
|
|
|
node _T_336 = and(_T_335, io.iccm_wren) @[el2_ifu_iccm_mem.scala 94:105]
|
|
|
|
|
node _T_337 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 95:6]
|
|
|
|
|
node _T_338 = and(_T_337, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 95:21]
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node redundant_data0_en = or(_T_336, _T_338) @[el2_ifu_iccm_mem.scala 94:121]
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node _T_339 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 96:49]
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node _T_340 = bits(redundant_address[0], 0, 0) @[el2_ifu_iccm_mem.scala 96:73]
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node _T_341 = and(_T_339, _T_340) @[el2_ifu_iccm_mem.scala 96:52]
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node _T_342 = bits(redundant_address[0], 0, 0) @[el2_ifu_iccm_mem.scala 96:100]
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node _T_343 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 96:122]
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node _T_344 = eq(_T_343, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 96:127]
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node _T_345 = and(_T_342, _T_344) @[el2_ifu_iccm_mem.scala 96:104]
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node _T_346 = or(_T_341, _T_345) @[el2_ifu_iccm_mem.scala 96:78]
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node _T_347 = bits(_T_346, 0, 0) @[el2_ifu_iccm_mem.scala 96:137]
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node _T_348 = bits(io.iccm_wr_data, 77, 39) @[el2_ifu_iccm_mem.scala 97:20]
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node _T_349 = bits(io.iccm_wr_data, 38, 0) @[el2_ifu_iccm_mem.scala 97:44]
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node redundant_data0_in = mux(_T_347, _T_348, _T_349) @[el2_ifu_iccm_mem.scala 96:31]
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node _T_350 = bits(redundant_data0_en, 0, 0) @[el2_ifu_iccm_mem.scala 98:78]
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reg _T_351 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
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when _T_350 : @[Reg.scala 28:19]
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_T_351 <= redundant_data0_in @[Reg.scala 28:23]
|
2020-10-06 22:30:06 +08:00
|
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skip @[Reg.scala 28:19]
|
2020-10-08 16:37:41 +08:00
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redundant_data[0] <= _T_351 @[el2_ifu_iccm_mem.scala 98:21]
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node _T_352 = bits(io.iccm_rw_addr, 14, 2) @[el2_ifu_iccm_mem.scala 100:45]
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node _T_353 = bits(redundant_address[1], 13, 1) @[el2_ifu_iccm_mem.scala 100:85]
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node _T_354 = eq(_T_352, _T_353) @[el2_ifu_iccm_mem.scala 100:61]
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node _T_355 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 101:22]
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node _T_356 = bits(redundant_address[1], 0, 0) @[el2_ifu_iccm_mem.scala 101:48]
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node _T_357 = and(_T_355, _T_356) @[el2_ifu_iccm_mem.scala 101:26]
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node _T_358 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 101:70]
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node _T_359 = eq(_T_358, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 101:75]
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node _T_360 = or(_T_357, _T_359) @[el2_ifu_iccm_mem.scala 101:52]
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node _T_361 = and(_T_354, _T_360) @[el2_ifu_iccm_mem.scala 100:102]
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node _T_362 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 101:101]
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node _T_363 = and(_T_361, _T_362) @[el2_ifu_iccm_mem.scala 101:84]
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node _T_364 = and(_T_363, io.iccm_wren) @[el2_ifu_iccm_mem.scala 101:105]
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node _T_365 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 102:6]
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node _T_366 = and(_T_365, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 102:21]
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node redundant_data1_en = or(_T_364, _T_366) @[el2_ifu_iccm_mem.scala 101:121]
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node _T_367 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 103:49]
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node _T_368 = bits(redundant_address[1], 0, 0) @[el2_ifu_iccm_mem.scala 103:73]
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node _T_369 = and(_T_367, _T_368) @[el2_ifu_iccm_mem.scala 103:52]
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node _T_370 = bits(redundant_address[1], 0, 0) @[el2_ifu_iccm_mem.scala 103:100]
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node _T_371 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 103:122]
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node _T_372 = eq(_T_371, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 103:127]
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node _T_373 = and(_T_370, _T_372) @[el2_ifu_iccm_mem.scala 103:104]
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node _T_374 = or(_T_369, _T_373) @[el2_ifu_iccm_mem.scala 103:78]
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node _T_375 = bits(_T_374, 0, 0) @[el2_ifu_iccm_mem.scala 103:137]
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node _T_376 = bits(io.iccm_wr_data, 77, 39) @[el2_ifu_iccm_mem.scala 104:20]
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node _T_377 = bits(io.iccm_wr_data, 38, 0) @[el2_ifu_iccm_mem.scala 104:44]
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node redundant_data1_in = mux(_T_375, _T_376, _T_377) @[el2_ifu_iccm_mem.scala 103:31]
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node _T_378 = bits(redundant_data1_en, 0, 0) @[el2_ifu_iccm_mem.scala 105:78]
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reg _T_379 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
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when _T_378 : @[Reg.scala 28:19]
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_T_379 <= redundant_data1_in @[Reg.scala 28:23]
|
2020-10-06 22:30:06 +08:00
|
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|
skip @[Reg.scala 28:19]
|
2020-10-08 16:37:41 +08:00
|
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|
redundant_data[1] <= _T_379 @[el2_ifu_iccm_mem.scala 105:21]
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node _T_380 = bits(io.iccm_rw_addr, 2, 0) @[el2_ifu_iccm_mem.scala 107:50]
|
2020-10-08 16:26:24 +08:00
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reg iccm_rd_addr_lo_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 107:34]
|
2020-10-08 16:37:41 +08:00
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iccm_rd_addr_lo_q <= _T_380 @[el2_ifu_iccm_mem.scala 107:34]
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node _T_381 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 108:48]
|
2020-10-08 16:26:24 +08:00
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reg iccm_rd_addr_hi_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 108:34]
|
2020-10-08 16:37:41 +08:00
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iccm_rd_addr_hi_q <= _T_381 @[el2_ifu_iccm_mem.scala 108:34]
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node _T_382 = eq(iccm_rd_addr_hi_q, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 110:86]
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node _T_383 = bits(iccm_bank_dout_fn_0, 31, 0) @[el2_ifu_iccm_mem.scala 110:115]
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node _T_384 = eq(iccm_rd_addr_hi_q, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 110:86]
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node _T_385 = bits(iccm_bank_dout_fn_1, 31, 0) @[el2_ifu_iccm_mem.scala 110:115]
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node _T_386 = eq(iccm_rd_addr_hi_q, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 110:86]
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node _T_387 = bits(iccm_bank_dout_fn_2, 31, 0) @[el2_ifu_iccm_mem.scala 110:115]
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node _T_388 = eq(iccm_rd_addr_hi_q, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 110:86]
|
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node _T_389 = bits(iccm_bank_dout_fn_3, 31, 0) @[el2_ifu_iccm_mem.scala 110:115]
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node _T_390 = mux(_T_382, _T_383, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_391 = mux(_T_384, _T_385, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_392 = mux(_T_386, _T_387, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_393 = mux(_T_388, _T_389, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_394 = or(_T_390, _T_391) @[Mux.scala 27:72]
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node _T_395 = or(_T_394, _T_392) @[Mux.scala 27:72]
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node _T_396 = or(_T_395, _T_393) @[Mux.scala 27:72]
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wire _T_397 : UInt<32> @[Mux.scala 27:72]
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_T_397 <= _T_396 @[Mux.scala 27:72]
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node _T_398 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 111:59]
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node _T_399 = eq(_T_398, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 111:77]
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node _T_400 = bits(iccm_bank_dout_fn_0, 31, 0) @[el2_ifu_iccm_mem.scala 111:106]
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node _T_401 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 111:59]
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node _T_402 = eq(_T_401, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 111:77]
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node _T_403 = bits(iccm_bank_dout_fn_1, 31, 0) @[el2_ifu_iccm_mem.scala 111:106]
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node _T_404 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 111:59]
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|
node _T_405 = eq(_T_404, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 111:77]
|
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|
node _T_406 = bits(iccm_bank_dout_fn_2, 31, 0) @[el2_ifu_iccm_mem.scala 111:106]
|
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|
node _T_407 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 111:59]
|
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|
node _T_408 = eq(_T_407, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 111:77]
|
|
|
|
|
node _T_409 = bits(iccm_bank_dout_fn_3, 31, 0) @[el2_ifu_iccm_mem.scala 111:106]
|
|
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|
|
node _T_410 = mux(_T_399, _T_400, UInt<1>("h00")) @[Mux.scala 27:72]
|
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|
node _T_411 = mux(_T_402, _T_403, UInt<1>("h00")) @[Mux.scala 27:72]
|
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|
node _T_412 = mux(_T_405, _T_406, UInt<1>("h00")) @[Mux.scala 27:72]
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|
node _T_413 = mux(_T_408, _T_409, UInt<1>("h00")) @[Mux.scala 27:72]
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|
node _T_414 = or(_T_410, _T_411) @[Mux.scala 27:72]
|
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|
node _T_415 = or(_T_414, _T_412) @[Mux.scala 27:72]
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|
node _T_416 = or(_T_415, _T_413) @[Mux.scala 27:72]
|
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wire _T_417 : UInt<32> @[Mux.scala 27:72]
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|
_T_417 <= _T_416 @[Mux.scala 27:72]
|
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|
|
node iccm_rd_data_pre = cat(_T_397, _T_417) @[Cat.scala 29:58]
|
|
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|
|
node _T_418 = bits(iccm_rd_addr_lo_q, 0, 0) @[el2_ifu_iccm_mem.scala 112:43]
|
|
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|
|
node _T_419 = bits(_T_418, 0, 0) @[el2_ifu_iccm_mem.scala 112:53]
|
|
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|
|
node _T_420 = mux(UInt<1>("h00"), UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12]
|
|
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|
|
node _T_421 = bits(iccm_rd_data_pre, 63, 16) @[el2_ifu_iccm_mem.scala 112:89]
|
|
|
|
|
node _T_422 = cat(_T_420, _T_421) @[Cat.scala 29:58]
|
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|
|
node _T_423 = mux(_T_419, _T_422, iccm_rd_data_pre) @[el2_ifu_iccm_mem.scala 112:25]
|
|
|
|
|
io.iccm_rd_data <= _T_423 @[el2_ifu_iccm_mem.scala 112:19]
|
|
|
|
|
node _T_424 = eq(iccm_rd_addr_hi_q, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 113:85]
|
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|
node _T_425 = eq(iccm_rd_addr_hi_q, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 113:85]
|
|
|
|
|
node _T_426 = eq(iccm_rd_addr_hi_q, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 113:85]
|
|
|
|
|
node _T_427 = eq(iccm_rd_addr_hi_q, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 113:85]
|
|
|
|
|
node _T_428 = mux(_T_424, iccm_bank_dout_fn_0, UInt<1>("h00")) @[Mux.scala 27:72]
|
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|
node _T_429 = mux(_T_425, iccm_bank_dout_fn_1, UInt<1>("h00")) @[Mux.scala 27:72]
|
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|
|
node _T_430 = mux(_T_426, iccm_bank_dout_fn_2, UInt<1>("h00")) @[Mux.scala 27:72]
|
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|
|
node _T_431 = mux(_T_427, iccm_bank_dout_fn_3, UInt<1>("h00")) @[Mux.scala 27:72]
|
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|
|
|
node _T_432 = or(_T_428, _T_429) @[Mux.scala 27:72]
|
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|
node _T_433 = or(_T_432, _T_430) @[Mux.scala 27:72]
|
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|
node _T_434 = or(_T_433, _T_431) @[Mux.scala 27:72]
|
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|
|
wire _T_435 : UInt<39> @[Mux.scala 27:72]
|
|
|
|
|
_T_435 <= _T_434 @[Mux.scala 27:72]
|
|
|
|
|
node _T_436 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 114:61]
|
|
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|
node _T_437 = eq(_T_436, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 114:79]
|
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|
|
|
node _T_438 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 114:61]
|
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|
|
node _T_439 = eq(_T_438, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 114:79]
|
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|
|
|
node _T_440 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 114:61]
|
|
|
|
|
node _T_441 = eq(_T_440, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 114:79]
|
|
|
|
|
node _T_442 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 114:61]
|
|
|
|
|
node _T_443 = eq(_T_442, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 114:79]
|
|
|
|
|
node _T_444 = mux(_T_437, iccm_bank_dout_fn_0, UInt<1>("h00")) @[Mux.scala 27:72]
|
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|
node _T_445 = mux(_T_439, iccm_bank_dout_fn_1, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
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|
|
node _T_446 = mux(_T_441, iccm_bank_dout_fn_2, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
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|
|
node _T_447 = mux(_T_443, iccm_bank_dout_fn_3, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_448 = or(_T_444, _T_445) @[Mux.scala 27:72]
|
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|
node _T_449 = or(_T_448, _T_446) @[Mux.scala 27:72]
|
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|
|
|
node _T_450 = or(_T_449, _T_447) @[Mux.scala 27:72]
|
|
|
|
|
wire _T_451 : UInt<39> @[Mux.scala 27:72]
|
|
|
|
|
_T_451 <= _T_450 @[Mux.scala 27:72]
|
|
|
|
|
node _T_452 = cat(_T_435, _T_451) @[Cat.scala 29:58]
|
|
|
|
|
io.iccm_rd_data_ecc <= _T_452 @[el2_ifu_iccm_mem.scala 113:23]
|
2020-10-06 22:30:06 +08:00
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|
