2020-10-22 17:52:47 +08:00
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;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
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circuit el2_exu_alu_ctl :
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2020-11-18 18:42:14 +08:00
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extmodule gated_latch :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = gated_latch
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module rvclkhdr :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of gated_latch @[el2_lib.scala 474:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
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clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
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clkhdr.EN <= io.en @[el2_lib.scala 477:18]
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clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
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extmodule gated_latch_1 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = gated_latch
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module rvclkhdr_1 :
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input clock : Clock
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of gated_latch_1 @[el2_lib.scala 474:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
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clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
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clkhdr.EN <= io.en @[el2_lib.scala 477:18]
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clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
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2020-10-22 17:52:47 +08:00
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module el2_exu_alu_ctl :
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input clock : Clock
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2020-11-18 18:42:14 +08:00
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input reset : AsyncReset
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2020-11-24 18:49:49 +08:00
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output io : {flip scan_mode : UInt<1>, flip flush_upper_x : UInt<1>, flip flush_lower_r : UInt<1>, flip enable : UInt<1>, flip valid_in : UInt<1>, flip ap : {land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, flip csr_ren_in : UInt<1>, flip a_in : SInt<32>, flip b_in : UInt<32>, flip pc_in : UInt<31>, flip pp_in : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}, flip brimm_in : UInt<12>, result_ff : UInt<32>, flush_upper_out : UInt<1>, flush_final_out : UInt<1>, flush_path_out : UInt<31>, pc_ff : UInt<31>, pred_correct_out : UInt<1>, predict_p_out : {valid : UInt<1>, bits : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}}}
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2020-10-22 17:52:47 +08:00
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2020-11-18 18:42:14 +08:00
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node _T = bits(io.scan_mode, 0, 0) @[el2_exu_alu_ctl.scala 35:60]
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inst rvclkhdr of rvclkhdr @[el2_lib.scala 508:23]
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rvclkhdr.clock <= clock
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rvclkhdr.reset <= reset
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rvclkhdr.io.clk <= clock @[el2_lib.scala 510:18]
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rvclkhdr.io.en <= io.enable @[el2_lib.scala 511:17]
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rvclkhdr.io.scan_mode <= _T @[el2_lib.scala 512:24]
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reg _T_1 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
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_T_1 <= io.pc_in @[el2_lib.scala 514:16]
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io.pc_ff <= _T_1 @[el2_exu_alu_ctl.scala 35:12]
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2020-10-22 17:52:47 +08:00
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wire result : UInt<32>
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result <= UInt<1>("h00")
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2020-11-18 18:42:14 +08:00
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node _T_2 = bits(io.scan_mode, 0, 0) @[el2_exu_alu_ctl.scala 37:62]
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inst rvclkhdr_1 of rvclkhdr_1 @[el2_lib.scala 508:23]
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rvclkhdr_1.clock <= clock
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rvclkhdr_1.reset <= reset
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rvclkhdr_1.io.clk <= clock @[el2_lib.scala 510:18]
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rvclkhdr_1.io.en <= io.enable @[el2_lib.scala 511:17]
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rvclkhdr_1.io.scan_mode <= _T_2 @[el2_lib.scala 512:24]
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reg _T_3 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
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_T_3 <= result @[el2_lib.scala 514:16]
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io.result_ff <= _T_3 @[el2_exu_alu_ctl.scala 37:16]
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node _T_4 = bits(io.ap.sub, 0, 0) @[el2_exu_alu_ctl.scala 39:29]
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node _T_5 = not(io.b_in) @[el2_exu_alu_ctl.scala 39:37]
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node bm = mux(_T_4, _T_5, io.b_in) @[el2_exu_alu_ctl.scala 39:17]
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2020-10-22 17:52:47 +08:00
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wire aout : UInt<33>
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aout <= UInt<1>("h00")
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2020-11-18 18:42:14 +08:00
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node _T_6 = bits(io.ap.sub, 0, 0) @[el2_exu_alu_ctl.scala 42:25]
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node _T_7 = asUInt(io.a_in) @[Cat.scala 29:58]
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node _T_8 = cat(UInt<1>("h00"), _T_7) @[Cat.scala 29:58]
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node _T_9 = not(io.b_in) @[el2_exu_alu_ctl.scala 42:70]
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node _T_10 = cat(UInt<1>("h00"), _T_9) @[Cat.scala 29:58]
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node _T_11 = add(_T_8, _T_10) @[el2_exu_alu_ctl.scala 42:55]
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node _T_12 = tail(_T_11, 1) @[el2_exu_alu_ctl.scala 42:55]
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node _T_13 = cat(UInt<32>("h00"), io.ap.sub) @[Cat.scala 29:58]
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node _T_14 = add(_T_12, _T_13) @[el2_exu_alu_ctl.scala 42:80]
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node _T_15 = tail(_T_14, 1) @[el2_exu_alu_ctl.scala 42:80]
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node _T_16 = asUInt(io.a_in) @[Cat.scala 29:58]
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node _T_17 = cat(UInt<1>("h00"), _T_16) @[Cat.scala 29:58]
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node _T_18 = cat(UInt<1>("h00"), io.b_in) @[Cat.scala 29:58]
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node _T_19 = add(_T_17, _T_18) @[el2_exu_alu_ctl.scala 42:132]
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node _T_20 = tail(_T_19, 1) @[el2_exu_alu_ctl.scala 42:132]
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node _T_21 = cat(UInt<32>("h00"), io.ap.sub) @[Cat.scala 29:58]
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node _T_22 = add(_T_20, _T_21) @[el2_exu_alu_ctl.scala 42:157]
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node _T_23 = tail(_T_22, 1) @[el2_exu_alu_ctl.scala 42:157]
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node _T_24 = mux(_T_6, _T_15, _T_23) @[el2_exu_alu_ctl.scala 42:14]
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aout <= _T_24 @[el2_exu_alu_ctl.scala 42:8]
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node cout = bits(aout, 32, 32) @[el2_exu_alu_ctl.scala 43:18]
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node _T_25 = bits(io.a_in, 31, 31) @[el2_exu_alu_ctl.scala 45:22]
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2020-11-24 18:49:49 +08:00
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node _T_26 = eq(_T_25, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 45:14]
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2020-11-18 18:42:14 +08:00
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node _T_27 = bits(bm, 31, 31) @[el2_exu_alu_ctl.scala 45:32]
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2020-11-24 18:49:49 +08:00
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node _T_28 = eq(_T_27, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 45:29]
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2020-11-18 18:42:14 +08:00
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node _T_29 = and(_T_26, _T_28) @[el2_exu_alu_ctl.scala 45:27]
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node _T_30 = bits(aout, 31, 31) @[el2_exu_alu_ctl.scala 45:44]
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node _T_31 = and(_T_29, _T_30) @[el2_exu_alu_ctl.scala 45:37]
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node _T_32 = bits(io.a_in, 31, 31) @[el2_exu_alu_ctl.scala 45:61]
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node _T_33 = bits(bm, 31, 31) @[el2_exu_alu_ctl.scala 45:71]
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node _T_34 = and(_T_32, _T_33) @[el2_exu_alu_ctl.scala 45:66]
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node _T_35 = bits(aout, 31, 31) @[el2_exu_alu_ctl.scala 45:83]
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2020-11-24 18:49:49 +08:00
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node _T_36 = eq(_T_35, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 45:78]
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2020-11-18 18:42:14 +08:00
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node _T_37 = and(_T_34, _T_36) @[el2_exu_alu_ctl.scala 45:76]
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node ov = or(_T_31, _T_37) @[el2_exu_alu_ctl.scala 45:50]
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node _T_38 = asSInt(io.b_in) @[el2_exu_alu_ctl.scala 47:50]
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node eq = eq(io.a_in, _T_38) @[el2_exu_alu_ctl.scala 47:38]
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node ne = not(eq) @[el2_exu_alu_ctl.scala 48:29]
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node neg = bits(aout, 31, 31) @[el2_exu_alu_ctl.scala 49:34]
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2020-11-24 18:49:49 +08:00
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node _T_39 = eq(io.ap.unsign, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 50:30]
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2020-11-18 18:42:14 +08:00
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node _T_40 = xor(neg, ov) @[el2_exu_alu_ctl.scala 50:51]
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node _T_41 = and(_T_39, _T_40) @[el2_exu_alu_ctl.scala 50:44]
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2020-11-24 18:49:49 +08:00
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node _T_42 = eq(cout, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 50:78]
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2020-11-18 18:42:14 +08:00
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node _T_43 = and(io.ap.unsign, _T_42) @[el2_exu_alu_ctl.scala 50:76]
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node lt = or(_T_41, _T_43) @[el2_exu_alu_ctl.scala 50:58]
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2020-11-24 18:49:49 +08:00
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node ge = eq(lt, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 51:29]
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2020-11-18 18:42:14 +08:00
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node _T_44 = bits(io.csr_ren_in, 0, 0) @[el2_exu_alu_ctl.scala 55:19]
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node _T_45 = asSInt(io.b_in) @[el2_exu_alu_ctl.scala 55:50]
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node _T_46 = bits(io.ap.land, 0, 0) @[el2_exu_alu_ctl.scala 56:16]
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node _T_47 = asSInt(io.b_in) @[el2_exu_alu_ctl.scala 56:50]
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node _T_48 = and(io.a_in, _T_47) @[el2_exu_alu_ctl.scala 56:39]
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node _T_49 = asSInt(_T_48) @[el2_exu_alu_ctl.scala 56:39]
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node _T_50 = bits(io.ap.lor, 0, 0) @[el2_exu_alu_ctl.scala 57:15]
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node _T_51 = asSInt(io.b_in) @[el2_exu_alu_ctl.scala 57:50]
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node _T_52 = or(io.a_in, _T_51) @[el2_exu_alu_ctl.scala 57:39]
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node _T_53 = asSInt(_T_52) @[el2_exu_alu_ctl.scala 57:39]
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node _T_54 = bits(io.ap.lxor, 0, 0) @[el2_exu_alu_ctl.scala 58:16]
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node _T_55 = asSInt(io.b_in) @[el2_exu_alu_ctl.scala 58:50]
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node _T_56 = xor(io.a_in, _T_55) @[el2_exu_alu_ctl.scala 58:39]
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node _T_57 = asSInt(_T_56) @[el2_exu_alu_ctl.scala 58:39]
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wire _T_58 : SInt<32> @[Mux.scala 27:72]
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node _T_59 = asUInt(_T_45) @[Mux.scala 27:72]
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node _T_60 = asSInt(_T_59) @[Mux.scala 27:72]
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_T_58 <= _T_60 @[Mux.scala 27:72]
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wire _T_61 : SInt<32> @[Mux.scala 27:72]
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node _T_62 = asUInt(_T_49) @[Mux.scala 27:72]
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node _T_63 = asSInt(_T_62) @[Mux.scala 27:72]
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_T_61 <= _T_63 @[Mux.scala 27:72]
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wire _T_64 : SInt<32> @[Mux.scala 27:72]
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node _T_65 = asUInt(_T_53) @[Mux.scala 27:72]
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node _T_66 = asSInt(_T_65) @[Mux.scala 27:72]
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_T_64 <= _T_66 @[Mux.scala 27:72]
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wire _T_67 : SInt<32> @[Mux.scala 27:72]
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node _T_68 = asUInt(_T_57) @[Mux.scala 27:72]
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node _T_69 = asSInt(_T_68) @[Mux.scala 27:72]
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_T_67 <= _T_69 @[Mux.scala 27:72]
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node _T_70 = mux(_T_44, _T_58, asSInt(UInt<1>("h00"))) @[Mux.scala 27:72]
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node _T_71 = mux(_T_46, _T_61, asSInt(UInt<1>("h00"))) @[Mux.scala 27:72]
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node _T_72 = mux(_T_50, _T_64, asSInt(UInt<1>("h00"))) @[Mux.scala 27:72]
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node _T_73 = mux(_T_54, _T_67, asSInt(UInt<1>("h00"))) @[Mux.scala 27:72]
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node _T_74 = or(_T_70, _T_71) @[Mux.scala 27:72]
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node _T_75 = asSInt(_T_74) @[Mux.scala 27:72]
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node _T_76 = or(_T_75, _T_72) @[Mux.scala 27:72]
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node _T_77 = asSInt(_T_76) @[Mux.scala 27:72]
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node _T_78 = or(_T_77, _T_73) @[Mux.scala 27:72]
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node _T_79 = asSInt(_T_78) @[Mux.scala 27:72]
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wire lout : SInt<32> @[Mux.scala 27:72]
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node _T_80 = asUInt(_T_79) @[Mux.scala 27:72]
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node _T_81 = asSInt(_T_80) @[Mux.scala 27:72]
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lout <= _T_81 @[Mux.scala 27:72]
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node _T_82 = bits(io.ap.sll, 0, 0) @[el2_exu_alu_ctl.scala 61:15]
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node _T_83 = bits(io.b_in, 4, 0) @[el2_exu_alu_ctl.scala 61:60]
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node _T_84 = cat(UInt<1>("h00"), _T_83) @[Cat.scala 29:58]
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node _T_85 = sub(UInt<6>("h020"), _T_84) @[el2_exu_alu_ctl.scala 61:38]
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node _T_86 = tail(_T_85, 1) @[el2_exu_alu_ctl.scala 61:38]
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node _T_87 = bits(io.ap.srl, 0, 0) @[el2_exu_alu_ctl.scala 62:15]
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node _T_88 = bits(io.b_in, 4, 0) @[el2_exu_alu_ctl.scala 62:60]
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node _T_89 = cat(UInt<1>("h00"), _T_88) @[Cat.scala 29:58]
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node _T_90 = bits(io.ap.sra, 0, 0) @[el2_exu_alu_ctl.scala 63:15]
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|
|
|
|
node _T_91 = bits(io.b_in, 4, 0) @[el2_exu_alu_ctl.scala 63:60]
|
|
|
|
|
node _T_92 = cat(UInt<1>("h00"), _T_91) @[Cat.scala 29:58]
|
|
|
|
|
node _T_93 = mux(_T_82, _T_86, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_94 = mux(_T_87, _T_89, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_95 = mux(_T_90, _T_92, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_96 = or(_T_93, _T_94) @[Mux.scala 27:72]
|
|
|
|
|
node _T_97 = or(_T_96, _T_95) @[Mux.scala 27:72]
|
2020-10-22 17:52:47 +08:00
|
|
|
wire shift_amount : UInt<6> @[Mux.scala 27:72]
|
2020-11-18 18:42:14 +08:00
|
|
|
shift_amount <= _T_97 @[Mux.scala 27:72]
|
2020-10-22 17:52:47 +08:00
|
|
|
wire shift_mask : UInt<32>
|
|
|
|
|
shift_mask <= UInt<1>("h00")
|
2020-11-24 18:49:49 +08:00
|
|
|
wire _T_98 : UInt<1>[5] @[el2_lib.scala 162:48]
|
|
|
|
|
_T_98[0] <= io.ap.sll @[el2_lib.scala 162:48]
|
|
|
|
|
_T_98[1] <= io.ap.sll @[el2_lib.scala 162:48]
|
|
|
|
|
_T_98[2] <= io.ap.sll @[el2_lib.scala 162:48]
|
|
|
|
|
_T_98[3] <= io.ap.sll @[el2_lib.scala 162:48]
|
|
|
|
|
_T_98[4] <= io.ap.sll @[el2_lib.scala 162:48]
|
2020-11-18 18:42:14 +08:00
|
|
|
node _T_99 = cat(_T_98[0], _T_98[1]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_100 = cat(_T_99, _T_98[2]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_101 = cat(_T_100, _T_98[3]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_102 = cat(_T_101, _T_98[4]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_103 = bits(io.b_in, 4, 0) @[el2_exu_alu_ctl.scala 66:70]
|
|
|
|
|
node _T_104 = and(_T_102, _T_103) @[el2_exu_alu_ctl.scala 66:61]
|
|
|
|
|
node _T_105 = dshl(UInt<32>("h0ffffffff"), _T_104) @[el2_exu_alu_ctl.scala 66:39]
|
|
|
|
|
shift_mask <= _T_105 @[el2_exu_alu_ctl.scala 66:14]
|
2020-10-22 17:52:47 +08:00
|
|
|
wire shift_extend : UInt<63>
|
|
|
|
|
shift_extend <= UInt<1>("h00")
|
2020-11-24 18:49:49 +08:00
|
|
|
wire _T_106 : UInt<1>[31] @[el2_lib.scala 162:48]
|
|
|
|
|
_T_106[0] <= io.ap.sra @[el2_lib.scala 162:48]
|
|
|
|
|
_T_106[1] <= io.ap.sra @[el2_lib.scala 162:48]
|
|
|
|
|
_T_106[2] <= io.ap.sra @[el2_lib.scala 162:48]
|
|
|
|
|
_T_106[3] <= io.ap.sra @[el2_lib.scala 162:48]
|
|
|
|
|
_T_106[4] <= io.ap.sra @[el2_lib.scala 162:48]
|
|
|
|
|
_T_106[5] <= io.ap.sra @[el2_lib.scala 162:48]
|
|
|
|
|
_T_106[6] <= io.ap.sra @[el2_lib.scala 162:48]
|
|
|
|
|
_T_106[7] <= io.ap.sra @[el2_lib.scala 162:48]
|
|
|
|
|
_T_106[8] <= io.ap.sra @[el2_lib.scala 162:48]
|
|
|
|
|
_T_106[9] <= io.ap.sra @[el2_lib.scala 162:48]
|
|
|
|
|
_T_106[10] <= io.ap.sra @[el2_lib.scala 162:48]
|
|
|
|
|
_T_106[11] <= io.ap.sra @[el2_lib.scala 162:48]
|
|
|
|
|
_T_106[12] <= io.ap.sra @[el2_lib.scala 162:48]
|
|
|
|
|
_T_106[13] <= io.ap.sra @[el2_lib.scala 162:48]
|
|
|
|
|
_T_106[14] <= io.ap.sra @[el2_lib.scala 162:48]
|
|
|
|
|
_T_106[15] <= io.ap.sra @[el2_lib.scala 162:48]
|
|
|
|
|
_T_106[16] <= io.ap.sra @[el2_lib.scala 162:48]
|
|
|
|
|
_T_106[17] <= io.ap.sra @[el2_lib.scala 162:48]
|
|
|
|
|
_T_106[18] <= io.ap.sra @[el2_lib.scala 162:48]
|
|
|
|
|
_T_106[19] <= io.ap.sra @[el2_lib.scala 162:48]
|
|
|
|
|
_T_106[20] <= io.ap.sra @[el2_lib.scala 162:48]
|
|
|
|
|
_T_106[21] <= io.ap.sra @[el2_lib.scala 162:48]
|
|
|
|
|
_T_106[22] <= io.ap.sra @[el2_lib.scala 162:48]
|
|
|
|
|
_T_106[23] <= io.ap.sra @[el2_lib.scala 162:48]
|
|
|
|
|
_T_106[24] <= io.ap.sra @[el2_lib.scala 162:48]
|
|
|
|
|
_T_106[25] <= io.ap.sra @[el2_lib.scala 162:48]
|
|
|
|
|
_T_106[26] <= io.ap.sra @[el2_lib.scala 162:48]
|
|
|
|
|
_T_106[27] <= io.ap.sra @[el2_lib.scala 162:48]
|
|
|
|
|
_T_106[28] <= io.ap.sra @[el2_lib.scala 162:48]
|
|
|
|
|
_T_106[29] <= io.ap.sra @[el2_lib.scala 162:48]
|
|
|
|
|
_T_106[30] <= io.ap.sra @[el2_lib.scala 162:48]
|
2020-11-18 18:42:14 +08:00
|
|
|
node _T_107 = cat(_T_106[0], _T_106[1]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_108 = cat(_T_107, _T_106[2]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_109 = cat(_T_108, _T_106[3]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_110 = cat(_T_109, _T_106[4]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_111 = cat(_T_110, _T_106[5]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_112 = cat(_T_111, _T_106[6]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_113 = cat(_T_112, _T_106[7]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_114 = cat(_T_113, _T_106[8]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_115 = cat(_T_114, _T_106[9]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_116 = cat(_T_115, _T_106[10]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_117 = cat(_T_116, _T_106[11]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_118 = cat(_T_117, _T_106[12]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_119 = cat(_T_118, _T_106[13]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_120 = cat(_T_119, _T_106[14]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_121 = cat(_T_120, _T_106[15]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_122 = cat(_T_121, _T_106[16]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_123 = cat(_T_122, _T_106[17]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_124 = cat(_T_123, _T_106[18]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_125 = cat(_T_124, _T_106[19]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_126 = cat(_T_125, _T_106[20]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_127 = cat(_T_126, _T_106[21]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_128 = cat(_T_127, _T_106[22]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_129 = cat(_T_128, _T_106[23]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_130 = cat(_T_129, _T_106[24]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_131 = cat(_T_130, _T_106[25]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_132 = cat(_T_131, _T_106[26]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_133 = cat(_T_132, _T_106[27]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_134 = cat(_T_133, _T_106[28]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_135 = cat(_T_134, _T_106[29]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_136 = cat(_T_135, _T_106[30]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_137 = bits(io.a_in, 31, 31) @[el2_exu_alu_ctl.scala 69:61]
|
2020-11-24 18:49:49 +08:00
|
|
|
wire _T_138 : UInt<1>[31] @[el2_lib.scala 162:48]
|
|
|
|
|
_T_138[0] <= _T_137 @[el2_lib.scala 162:48]
|
|
|
|
|
_T_138[1] <= _T_137 @[el2_lib.scala 162:48]
|
|
|
|
|
_T_138[2] <= _T_137 @[el2_lib.scala 162:48]
|
|
|
|
|
_T_138[3] <= _T_137 @[el2_lib.scala 162:48]
|
|
|
|
|
_T_138[4] <= _T_137 @[el2_lib.scala 162:48]
|
|
|
|
|
_T_138[5] <= _T_137 @[el2_lib.scala 162:48]
|
|
|
|
|
_T_138[6] <= _T_137 @[el2_lib.scala 162:48]
|
|
|
|
|
_T_138[7] <= _T_137 @[el2_lib.scala 162:48]
|
|
|
|
|
_T_138[8] <= _T_137 @[el2_lib.scala 162:48]
|
|
|
|
|
_T_138[9] <= _T_137 @[el2_lib.scala 162:48]
|
|
|
|
|
_T_138[10] <= _T_137 @[el2_lib.scala 162:48]
|
|
|
|
|
_T_138[11] <= _T_137 @[el2_lib.scala 162:48]
|
|
|
|
|
_T_138[12] <= _T_137 @[el2_lib.scala 162:48]
|
|
|
|
|
_T_138[13] <= _T_137 @[el2_lib.scala 162:48]
|
|
|
|
|
_T_138[14] <= _T_137 @[el2_lib.scala 162:48]
|
|
|
|
|
_T_138[15] <= _T_137 @[el2_lib.scala 162:48]
|
|
|
|
|
_T_138[16] <= _T_137 @[el2_lib.scala 162:48]
|
|
|
|
|
_T_138[17] <= _T_137 @[el2_lib.scala 162:48]
|
|
|
|
|
_T_138[18] <= _T_137 @[el2_lib.scala 162:48]
|
|
|
|
|
_T_138[19] <= _T_137 @[el2_lib.scala 162:48]
|
|
|
|
|
_T_138[20] <= _T_137 @[el2_lib.scala 162:48]
|
|
|
|
|
_T_138[21] <= _T_137 @[el2_lib.scala 162:48]
|
|
|
|
|
_T_138[22] <= _T_137 @[el2_lib.scala 162:48]
|
|
|
|
|
_T_138[23] <= _T_137 @[el2_lib.scala 162:48]
|
|
|
|
|
_T_138[24] <= _T_137 @[el2_lib.scala 162:48]
|
|
|
|
|
_T_138[25] <= _T_137 @[el2_lib.scala 162:48]
|
|
|
|
|
_T_138[26] <= _T_137 @[el2_lib.scala 162:48]
|
|
|
|
|
_T_138[27] <= _T_137 @[el2_lib.scala 162:48]
|
|
|
|
|
_T_138[28] <= _T_137 @[el2_lib.scala 162:48]
|
|
|
|
|
_T_138[29] <= _T_137 @[el2_lib.scala 162:48]
|
|
|
|
|
_T_138[30] <= _T_137 @[el2_lib.scala 162:48]
|
2020-11-18 18:42:14 +08:00
|
|
|
node _T_139 = cat(_T_138[0], _T_138[1]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_140 = cat(_T_139, _T_138[2]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_141 = cat(_T_140, _T_138[3]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_142 = cat(_T_141, _T_138[4]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_143 = cat(_T_142, _T_138[5]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_144 = cat(_T_143, _T_138[6]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_145 = cat(_T_144, _T_138[7]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_146 = cat(_T_145, _T_138[8]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_147 = cat(_T_146, _T_138[9]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_148 = cat(_T_147, _T_138[10]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_149 = cat(_T_148, _T_138[11]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_150 = cat(_T_149, _T_138[12]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_151 = cat(_T_150, _T_138[13]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_152 = cat(_T_151, _T_138[14]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_153 = cat(_T_152, _T_138[15]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_154 = cat(_T_153, _T_138[16]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_155 = cat(_T_154, _T_138[17]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_156 = cat(_T_155, _T_138[18]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_157 = cat(_T_156, _T_138[19]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_158 = cat(_T_157, _T_138[20]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_159 = cat(_T_158, _T_138[21]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_160 = cat(_T_159, _T_138[22]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_161 = cat(_T_160, _T_138[23]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_162 = cat(_T_161, _T_138[24]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_163 = cat(_T_162, _T_138[25]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_164 = cat(_T_163, _T_138[26]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_165 = cat(_T_164, _T_138[27]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_166 = cat(_T_165, _T_138[28]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_167 = cat(_T_166, _T_138[29]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_168 = cat(_T_167, _T_138[30]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_169 = and(_T_136, _T_168) @[el2_exu_alu_ctl.scala 69:44]
|
2020-11-24 18:49:49 +08:00
|
|
|
wire _T_170 : UInt<1>[31] @[el2_lib.scala 162:48]
|
|
|
|
|
_T_170[0] <= io.ap.sll @[el2_lib.scala 162:48]
|
|
|
|
|
_T_170[1] <= io.ap.sll @[el2_lib.scala 162:48]
|
|
|
|
|
_T_170[2] <= io.ap.sll @[el2_lib.scala 162:48]
|
|
|
|
|
_T_170[3] <= io.ap.sll @[el2_lib.scala 162:48]
|
|
|
|
|
_T_170[4] <= io.ap.sll @[el2_lib.scala 162:48]
|
|
|
|
|
_T_170[5] <= io.ap.sll @[el2_lib.scala 162:48]
|
|
|
|
|
_T_170[6] <= io.ap.sll @[el2_lib.scala 162:48]
|
|
|
|
|
_T_170[7] <= io.ap.sll @[el2_lib.scala 162:48]
|
|
|
|
|
_T_170[8] <= io.ap.sll @[el2_lib.scala 162:48]
|
|
|
|
|
_T_170[9] <= io.ap.sll @[el2_lib.scala 162:48]
|
|
|
|
|
_T_170[10] <= io.ap.sll @[el2_lib.scala 162:48]
|
|
|
|
|
_T_170[11] <= io.ap.sll @[el2_lib.scala 162:48]
|
|
|
|
|
_T_170[12] <= io.ap.sll @[el2_lib.scala 162:48]
|
|
|
|
|
_T_170[13] <= io.ap.sll @[el2_lib.scala 162:48]
|
|
|
|
|
_T_170[14] <= io.ap.sll @[el2_lib.scala 162:48]
|
|
|
|
|
_T_170[15] <= io.ap.sll @[el2_lib.scala 162:48]
|
|
|
|
|
_T_170[16] <= io.ap.sll @[el2_lib.scala 162:48]
|
|
|
|
|
_T_170[17] <= io.ap.sll @[el2_lib.scala 162:48]
|
|
|
|
|
_T_170[18] <= io.ap.sll @[el2_lib.scala 162:48]
|
|
|
|
|
_T_170[19] <= io.ap.sll @[el2_lib.scala 162:48]
|
|
|
|
|
_T_170[20] <= io.ap.sll @[el2_lib.scala 162:48]
|
|
|
|
|
_T_170[21] <= io.ap.sll @[el2_lib.scala 162:48]
|
|
|
|
|
_T_170[22] <= io.ap.sll @[el2_lib.scala 162:48]
|
|
|
|
|
_T_170[23] <= io.ap.sll @[el2_lib.scala 162:48]
|
|
|
|
|
_T_170[24] <= io.ap.sll @[el2_lib.scala 162:48]
|
|
|
|
|
_T_170[25] <= io.ap.sll @[el2_lib.scala 162:48]
|
|
|
|
|
_T_170[26] <= io.ap.sll @[el2_lib.scala 162:48]
|
|
|
|
|
_T_170[27] <= io.ap.sll @[el2_lib.scala 162:48]
|
|
|
|
|
_T_170[28] <= io.ap.sll @[el2_lib.scala 162:48]
|
|
|
|
|
_T_170[29] <= io.ap.sll @[el2_lib.scala 162:48]
|
|
|
|
|
_T_170[30] <= io.ap.sll @[el2_lib.scala 162:48]
|
2020-11-18 18:42:14 +08:00
|
|
|
node _T_171 = cat(_T_170[0], _T_170[1]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_172 = cat(_T_171, _T_170[2]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_173 = cat(_T_172, _T_170[3]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_174 = cat(_T_173, _T_170[4]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_175 = cat(_T_174, _T_170[5]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_176 = cat(_T_175, _T_170[6]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_177 = cat(_T_176, _T_170[7]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_178 = cat(_T_177, _T_170[8]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_179 = cat(_T_178, _T_170[9]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_180 = cat(_T_179, _T_170[10]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_181 = cat(_T_180, _T_170[11]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_182 = cat(_T_181, _T_170[12]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_183 = cat(_T_182, _T_170[13]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_184 = cat(_T_183, _T_170[14]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_185 = cat(_T_184, _T_170[15]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_186 = cat(_T_185, _T_170[16]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_187 = cat(_T_186, _T_170[17]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_188 = cat(_T_187, _T_170[18]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_189 = cat(_T_188, _T_170[19]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_190 = cat(_T_189, _T_170[20]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_191 = cat(_T_190, _T_170[21]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_192 = cat(_T_191, _T_170[22]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_193 = cat(_T_192, _T_170[23]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_194 = cat(_T_193, _T_170[24]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_195 = cat(_T_194, _T_170[25]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_196 = cat(_T_195, _T_170[26]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_197 = cat(_T_196, _T_170[27]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_198 = cat(_T_197, _T_170[28]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_199 = cat(_T_198, _T_170[29]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_200 = cat(_T_199, _T_170[30]) @[Cat.scala 29:58]
|
|
|
|
|
node _T_201 = bits(io.a_in, 30, 0) @[el2_exu_alu_ctl.scala 69:99]
|
|
|
|
|
node _T_202 = and(_T_200, _T_201) @[el2_exu_alu_ctl.scala 69:90]
|
|
|
|
|
node _T_203 = or(_T_169, _T_202) @[el2_exu_alu_ctl.scala 69:68]
|
|
|
|
|
node _T_204 = asUInt(io.a_in) @[Cat.scala 29:58]
|
|
|
|
|
node _T_205 = cat(_T_203, _T_204) @[Cat.scala 29:58]
|
|
|
|
|
shift_extend <= _T_205 @[el2_exu_alu_ctl.scala 69:16]
|
2020-10-22 17:52:47 +08:00
|
|
|
wire shift_long : UInt<63>
|
|
|
|
|
shift_long <= UInt<1>("h00")
|
2020-11-18 18:42:14 +08:00
|
|
|
node _T_206 = bits(shift_amount, 4, 0) @[el2_exu_alu_ctl.scala 72:47]
|
|
|
|
|
node _T_207 = dshr(shift_extend, _T_206) @[el2_exu_alu_ctl.scala 72:32]
|
|
|
|
|
shift_long <= _T_207 @[el2_exu_alu_ctl.scala 72:14]
|
|
|
|
|
node _T_208 = bits(shift_long, 31, 0) @[el2_exu_alu_ctl.scala 74:27]
|
|
|
|
|
node _T_209 = bits(shift_mask, 31, 0) @[el2_exu_alu_ctl.scala 74:46]
|
|
|
|
|
node sout = and(_T_208, _T_209) @[el2_exu_alu_ctl.scala 74:34]
|
|
|
|
|
node _T_210 = or(io.ap.sll, io.ap.srl) @[el2_exu_alu_ctl.scala 77:41]
|
|
|
|
|
node sel_shift = or(_T_210, io.ap.sra) @[el2_exu_alu_ctl.scala 77:53]
|
|
|
|
|
node _T_211 = or(io.ap.add, io.ap.sub) @[el2_exu_alu_ctl.scala 78:41]
|
2020-11-24 18:49:49 +08:00
|
|
|
node _T_212 = eq(io.ap.slt, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 78:56]
|
2020-11-18 18:42:14 +08:00
|
|
|
node sel_adder = and(_T_211, _T_212) @[el2_exu_alu_ctl.scala 78:54]
|
2020-11-24 18:49:49 +08:00
|
|
|
node _T_213 = or(io.ap.jal, io.pp_in.bits.pcall) @[el2_exu_alu_ctl.scala 79:41]
|
|
|
|
|
node _T_214 = or(_T_213, io.pp_in.bits.pja) @[el2_exu_alu_ctl.scala 79:63]
|
|
|
|
|
node sel_pc = or(_T_214, io.pp_in.bits.pret) @[el2_exu_alu_ctl.scala 79:83]
|
2020-11-18 18:42:14 +08:00
|
|
|
node _T_215 = bits(io.ap.csr_imm, 0, 0) @[el2_exu_alu_ctl.scala 80:47]
|
|
|
|
|
node _T_216 = asSInt(io.b_in) @[el2_exu_alu_ctl.scala 80:63]
|
|
|
|
|
node csr_write_data = mux(_T_215, _T_216, io.a_in) @[el2_exu_alu_ctl.scala 80:32]
|
|
|
|
|
node slt_one = and(io.ap.slt, lt) @[el2_exu_alu_ctl.scala 82:40]
|
|
|
|
|
node _T_217 = cat(io.pc_in, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
|
|
|
node _T_218 = cat(io.brimm_in, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
|
|
|
node _T_219 = bits(_T_217, 12, 1) @[el2_lib.scala 208:24]
|
|
|
|
|
node _T_220 = bits(_T_218, 12, 1) @[el2_lib.scala 208:40]
|
|
|
|
|
node _T_221 = add(_T_219, _T_220) @[el2_lib.scala 208:31]
|
|
|
|
|
node _T_222 = bits(_T_217, 31, 13) @[el2_lib.scala 209:20]
|
|
|
|
|
node _T_223 = add(_T_222, UInt<1>("h01")) @[el2_lib.scala 209:27]
|
|
|
|
|
node _T_224 = tail(_T_223, 1) @[el2_lib.scala 209:27]
|
|
|
|
|
node _T_225 = bits(_T_217, 31, 13) @[el2_lib.scala 210:20]
|
|
|
|
|
node _T_226 = sub(_T_225, UInt<1>("h01")) @[el2_lib.scala 210:27]
|
|
|
|
|
node _T_227 = tail(_T_226, 1) @[el2_lib.scala 210:27]
|
|
|
|
|
node _T_228 = bits(_T_218, 12, 12) @[el2_lib.scala 211:22]
|
|
|
|
|
node _T_229 = bits(_T_221, 12, 12) @[el2_lib.scala 212:39]
|
|
|
|
|
node _T_230 = eq(_T_229, UInt<1>("h00")) @[el2_lib.scala 212:28]
|
|
|
|
|
node _T_231 = xor(_T_228, _T_230) @[el2_lib.scala 212:26]
|
|
|
|
|
node _T_232 = bits(_T_231, 0, 0) @[el2_lib.scala 212:64]
|
|
|
|
|
node _T_233 = bits(_T_217, 31, 13) @[el2_lib.scala 212:76]
|
2020-11-24 18:49:49 +08:00
|
|
|
node _T_234 = eq(_T_228, UInt<1>("h00")) @[el2_lib.scala 213:20]
|
|
|
|
|
node _T_235 = bits(_T_221, 12, 12) @[el2_lib.scala 213:39]
|
|
|
|
|
node _T_236 = and(_T_234, _T_235) @[el2_lib.scala 213:26]
|
|
|
|
|
node _T_237 = bits(_T_236, 0, 0) @[el2_lib.scala 213:64]
|
|
|
|
|
node _T_238 = bits(_T_221, 12, 12) @[el2_lib.scala 214:39]
|
|
|
|
|
node _T_239 = eq(_T_238, UInt<1>("h00")) @[el2_lib.scala 214:28]
|
|
|
|
|
node _T_240 = and(_T_228, _T_239) @[el2_lib.scala 214:26]
|
|
|
|
|
node _T_241 = bits(_T_240, 0, 0) @[el2_lib.scala 214:64]
|
2020-11-18 18:42:14 +08:00
|
|
|
node _T_242 = mux(_T_232, _T_233, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_243 = mux(_T_237, _T_224, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_244 = mux(_T_241, _T_227, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_245 = or(_T_242, _T_243) @[Mux.scala 27:72]
|
|
|
|
|
node _T_246 = or(_T_245, _T_244) @[Mux.scala 27:72]
|
|
|
|
|
wire _T_247 : UInt<19> @[Mux.scala 27:72]
|
|
|
|
|
_T_247 <= _T_246 @[Mux.scala 27:72]
|
2020-11-24 18:49:49 +08:00
|
|
|
node _T_248 = bits(_T_221, 11, 0) @[el2_lib.scala 214:94]
|
2020-11-18 18:42:14 +08:00
|
|
|
node _T_249 = cat(_T_247, _T_248) @[Cat.scala 29:58]
|
|
|
|
|
node pcout = cat(_T_249, UInt<1>("h00")) @[Cat.scala 29:58]
|
|
|
|
|
node _T_250 = bits(lout, 31, 0) @[el2_exu_alu_ctl.scala 88:24]
|
|
|
|
|
node _T_251 = cat(UInt<31>("h00"), slt_one) @[Cat.scala 29:58]
|
|
|
|
|
node _T_252 = or(_T_250, _T_251) @[el2_exu_alu_ctl.scala 88:31]
|
|
|
|
|
node _T_253 = bits(sel_shift, 0, 0) @[el2_exu_alu_ctl.scala 89:15]
|
|
|
|
|
node _T_254 = bits(sout, 31, 0) @[el2_exu_alu_ctl.scala 89:41]
|
|
|
|
|
node _T_255 = bits(sel_adder, 0, 0) @[el2_exu_alu_ctl.scala 90:15]
|
|
|
|
|
node _T_256 = bits(aout, 31, 0) @[el2_exu_alu_ctl.scala 90:41]
|
|
|
|
|
node _T_257 = bits(sel_pc, 0, 0) @[el2_exu_alu_ctl.scala 91:12]
|
|
|
|
|
node _T_258 = bits(io.ap.csr_write, 0, 0) @[el2_exu_alu_ctl.scala 92:21]
|
|
|
|
|
node _T_259 = bits(csr_write_data, 31, 0) @[el2_exu_alu_ctl.scala 92:51]
|
|
|
|
|
node _T_260 = mux(_T_253, _T_254, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_261 = mux(_T_255, _T_256, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_262 = mux(_T_257, pcout, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_263 = mux(_T_258, _T_259, UInt<1>("h00")) @[Mux.scala 27:72]
|
|
|
|
|
node _T_264 = or(_T_260, _T_261) @[Mux.scala 27:72]
|
|
|
|
|
node _T_265 = or(_T_264, _T_262) @[Mux.scala 27:72]
|
|
|
|
|
node _T_266 = or(_T_265, _T_263) @[Mux.scala 27:72]
|
|
|
|
|
wire _T_267 : UInt<32> @[Mux.scala 27:72]
|
|
|
|
|
_T_267 <= _T_266 @[Mux.scala 27:72]
|
|
|
|
|
node _T_268 = or(_T_252, _T_267) @[el2_exu_alu_ctl.scala 88:56]
|
|
|
|
|
result <= _T_268 @[el2_exu_alu_ctl.scala 88:16]
|
2020-11-24 18:49:49 +08:00
|
|
|
node _T_269 = or(io.ap.jal, io.pp_in.bits.pcall) @[el2_exu_alu_ctl.scala 96:45]
|
|
|
|
|
node _T_270 = or(_T_269, io.pp_in.bits.pja) @[el2_exu_alu_ctl.scala 97:25]
|
|
|
|
|
node any_jal = or(_T_270, io.pp_in.bits.pret) @[el2_exu_alu_ctl.scala 98:25]
|
2020-11-18 18:42:14 +08:00
|
|
|
node _T_271 = and(io.ap.beq, eq) @[el2_exu_alu_ctl.scala 101:40]
|
|
|
|
|
node _T_272 = and(io.ap.bne, ne) @[el2_exu_alu_ctl.scala 101:59]
|
|
|
|
|
node _T_273 = or(_T_271, _T_272) @[el2_exu_alu_ctl.scala 101:46]
|
|
|
|
|
node _T_274 = and(io.ap.blt, lt) @[el2_exu_alu_ctl.scala 101:85]
|
|
|
|
|
node _T_275 = or(_T_273, _T_274) @[el2_exu_alu_ctl.scala 101:72]
|
|
|
|
|
node _T_276 = and(io.ap.bge, ge) @[el2_exu_alu_ctl.scala 101:104]
|
|
|
|
|
node _T_277 = or(_T_275, _T_276) @[el2_exu_alu_ctl.scala 101:91]
|
|
|
|
|
node actual_taken = or(_T_277, any_jal) @[el2_exu_alu_ctl.scala 101:110]
|
|
|
|
|
node _T_278 = and(io.valid_in, io.ap.predict_nt) @[el2_exu_alu_ctl.scala 106:42]
|
|
|
|
|
node _T_279 = eq(actual_taken, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 106:63]
|
|
|
|
|
node _T_280 = and(_T_278, _T_279) @[el2_exu_alu_ctl.scala 106:61]
|
|
|
|
|
node _T_281 = eq(any_jal, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 106:79]
|
|
|
|
|
node _T_282 = and(_T_280, _T_281) @[el2_exu_alu_ctl.scala 106:77]
|
|
|
|
|
node _T_283 = and(io.valid_in, io.ap.predict_t) @[el2_exu_alu_ctl.scala 106:104]
|
|
|
|
|
node _T_284 = and(_T_283, actual_taken) @[el2_exu_alu_ctl.scala 106:123]
|
|
|
|
|
node _T_285 = eq(any_jal, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 106:141]
|
|
|
|
|
node _T_286 = and(_T_284, _T_285) @[el2_exu_alu_ctl.scala 106:139]
|
|
|
|
|
node _T_287 = or(_T_282, _T_286) @[el2_exu_alu_ctl.scala 106:89]
|
|
|
|
|
io.pred_correct_out <= _T_287 @[el2_exu_alu_ctl.scala 106:26]
|
|
|
|
|
node _T_288 = bits(any_jal, 0, 0) @[el2_exu_alu_ctl.scala 108:37]
|
|
|
|
|
node _T_289 = bits(aout, 31, 1) @[el2_exu_alu_ctl.scala 108:49]
|
|
|
|
|
node _T_290 = bits(pcout, 31, 1) @[el2_exu_alu_ctl.scala 108:62]
|
|
|
|
|
node _T_291 = mux(_T_288, _T_289, _T_290) @[el2_exu_alu_ctl.scala 108:28]
|
|
|
|
|
io.flush_path_out <= _T_291 @[el2_exu_alu_ctl.scala 108:22]
|
|
|
|
|
node _T_292 = eq(actual_taken, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 111:47]
|
|
|
|
|
node _T_293 = and(io.ap.predict_t, _T_292) @[el2_exu_alu_ctl.scala 111:45]
|
|
|
|
|
node _T_294 = and(io.ap.predict_nt, actual_taken) @[el2_exu_alu_ctl.scala 111:82]
|
|
|
|
|
node cond_mispredict = or(_T_293, _T_294) @[el2_exu_alu_ctl.scala 111:62]
|
2020-11-24 18:49:49 +08:00
|
|
|
node _T_295 = bits(aout, 31, 1) @[el2_exu_alu_ctl.scala 114:80]
|
|
|
|
|
node _T_296 = neq(io.pp_in.bits.prett, _T_295) @[el2_exu_alu_ctl.scala 114:72]
|
|
|
|
|
node target_mispredict = and(io.pp_in.bits.pret, _T_296) @[el2_exu_alu_ctl.scala 114:49]
|
2020-11-18 18:42:14 +08:00
|
|
|
node _T_297 = or(io.ap.jal, cond_mispredict) @[el2_exu_alu_ctl.scala 116:42]
|
|
|
|
|
node _T_298 = or(_T_297, target_mispredict) @[el2_exu_alu_ctl.scala 116:60]
|
|
|
|
|
node _T_299 = and(_T_298, io.valid_in) @[el2_exu_alu_ctl.scala 116:81]
|
|
|
|
|
node _T_300 = eq(io.flush_upper_x, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 116:97]
|
|
|
|
|
node _T_301 = and(_T_299, _T_300) @[el2_exu_alu_ctl.scala 116:95]
|
|
|
|
|
node _T_302 = eq(io.flush_lower_r, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 116:119]
|
|
|
|
|
node _T_303 = and(_T_301, _T_302) @[el2_exu_alu_ctl.scala 116:117]
|
|
|
|
|
io.flush_upper_out <= _T_303 @[el2_exu_alu_ctl.scala 116:26]
|
|
|
|
|
node _T_304 = or(io.ap.jal, cond_mispredict) @[el2_exu_alu_ctl.scala 118:42]
|
|
|
|
|
node _T_305 = or(_T_304, target_mispredict) @[el2_exu_alu_ctl.scala 118:60]
|
|
|
|
|
node _T_306 = and(_T_305, io.valid_in) @[el2_exu_alu_ctl.scala 118:81]
|
|
|
|
|
node _T_307 = eq(io.flush_upper_x, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 118:97]
|
|
|
|
|
node _T_308 = and(_T_306, _T_307) @[el2_exu_alu_ctl.scala 118:95]
|
|
|
|
|
node _T_309 = or(_T_308, io.flush_lower_r) @[el2_exu_alu_ctl.scala 118:117]
|
|
|
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io.flush_final_out <= _T_309 @[el2_exu_alu_ctl.scala 118:26]
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2020-10-22 17:52:47 +08:00
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wire newhist : UInt<2>
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newhist <= UInt<1>("h00")
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2020-11-24 18:49:49 +08:00
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node _T_310 = bits(io.pp_in.bits.hist, 1, 1) @[el2_exu_alu_ctl.scala 122:40]
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node _T_311 = bits(io.pp_in.bits.hist, 0, 0) @[el2_exu_alu_ctl.scala 122:65]
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node _T_312 = and(_T_310, _T_311) @[el2_exu_alu_ctl.scala 122:44]
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node _T_313 = bits(io.pp_in.bits.hist, 0, 0) @[el2_exu_alu_ctl.scala 122:92]
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node _T_314 = eq(_T_313, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 122:73]
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node _T_315 = and(_T_314, actual_taken) @[el2_exu_alu_ctl.scala 122:96]
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node _T_316 = or(_T_312, _T_315) @[el2_exu_alu_ctl.scala 122:70]
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node _T_317 = bits(io.pp_in.bits.hist, 1, 1) @[el2_exu_alu_ctl.scala 123:25]
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node _T_318 = eq(_T_317, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 123:6]
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node _T_319 = eq(actual_taken, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 123:31]
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node _T_320 = and(_T_318, _T_319) @[el2_exu_alu_ctl.scala 123:29]
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node _T_321 = bits(io.pp_in.bits.hist, 1, 1) @[el2_exu_alu_ctl.scala 123:68]
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node _T_322 = and(_T_321, actual_taken) @[el2_exu_alu_ctl.scala 123:72]
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node _T_323 = or(_T_320, _T_322) @[el2_exu_alu_ctl.scala 123:47]
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2020-11-18 18:42:14 +08:00
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node _T_324 = cat(_T_316, _T_323) @[Cat.scala 29:58]
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newhist <= _T_324 @[el2_exu_alu_ctl.scala 122:14]
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2020-11-24 18:49:49 +08:00
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io.predict_p_out.bits.way <= io.pp_in.bits.way @[el2_exu_alu_ctl.scala 125:30]
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io.predict_p_out.bits.pja <= io.pp_in.bits.pja @[el2_exu_alu_ctl.scala 125:30]
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io.predict_p_out.bits.pret <= io.pp_in.bits.pret @[el2_exu_alu_ctl.scala 125:30]
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io.predict_p_out.bits.pcall <= io.pp_in.bits.pcall @[el2_exu_alu_ctl.scala 125:30]
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io.predict_p_out.bits.prett <= io.pp_in.bits.prett @[el2_exu_alu_ctl.scala 125:30]
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io.predict_p_out.bits.br_start_error <= io.pp_in.bits.br_start_error @[el2_exu_alu_ctl.scala 125:30]
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io.predict_p_out.bits.br_error <= io.pp_in.bits.br_error @[el2_exu_alu_ctl.scala 125:30]
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io.predict_p_out.bits.toffset <= io.pp_in.bits.toffset @[el2_exu_alu_ctl.scala 125:30]
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io.predict_p_out.bits.hist <= io.pp_in.bits.hist @[el2_exu_alu_ctl.scala 125:30]
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io.predict_p_out.bits.pc4 <= io.pp_in.bits.pc4 @[el2_exu_alu_ctl.scala 125:30]
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io.predict_p_out.bits.boffset <= io.pp_in.bits.boffset @[el2_exu_alu_ctl.scala 125:30]
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io.predict_p_out.bits.ataken <= io.pp_in.bits.ataken @[el2_exu_alu_ctl.scala 125:30]
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io.predict_p_out.bits.misp <= io.pp_in.bits.misp @[el2_exu_alu_ctl.scala 125:30]
|
2020-11-18 18:42:14 +08:00
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io.predict_p_out.valid <= io.pp_in.valid @[el2_exu_alu_ctl.scala 125:30]
|
2020-11-24 18:49:49 +08:00
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node _T_325 = eq(io.flush_upper_x, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 126:38]
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node _T_326 = eq(io.flush_lower_r, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 126:58]
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node _T_327 = and(_T_325, _T_326) @[el2_exu_alu_ctl.scala 126:56]
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node _T_328 = or(cond_mispredict, target_mispredict) @[el2_exu_alu_ctl.scala 126:95]
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node _T_329 = and(_T_327, _T_328) @[el2_exu_alu_ctl.scala 126:76]
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io.predict_p_out.bits.misp <= _T_329 @[el2_exu_alu_ctl.scala 126:35]
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io.predict_p_out.bits.ataken <= actual_taken @[el2_exu_alu_ctl.scala 127:35]
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io.predict_p_out.bits.hist <= newhist @[el2_exu_alu_ctl.scala 128:35]
|
2020-10-22 17:52:47 +08:00
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