IMC started

src/main/scala/ifu/el2_ifu_mem_ctl.scala

@@ -340,7 +340,9 @@ class el2_ifu_mem_ctl extends Module with el2_lib {
   val ifu_bus_rdata_ff = WireInit(UInt(64.W), 0.U)
   val ic_miss_buff_half = WireInit(UInt(64.W), 0.U)
   val ic_wr_ecc = rvecc_encode_64(ifu_bus_rdata_ff)
-  io.ic_wr_ecc := ic_wr_ecc
+  val m1 = Module(new rvecc_encode_64())
+  m1.io.din := ifu_bus_rdata_ff
+  io.ic_wr_ecc := m1.io.ecc_out
   val ic_miss_buff_ecc = rvecc_encode_64(ic_miss_buff_half)
   io.ic_miss_buff_ecc := ic_miss_buff_ecc
   val ic_wr_16bytes_data = WireInit(UInt((ICACHE_BANKS_WAY * (if(ICACHE_ECC) 71 else 68)).W), 0.U)

src/main/scala/lib/el2_lib.scala

@@ -314,6 +314,43 @@ trait el2_lib extends param{
     (ecc_out,dout,single_ecc_error,double_ecc_error)
   }
 
+  class rvecc_encode_64 extends Module{    //Done for verification and testing
+    val io      =  IO(new Bundle{
+      val din     =  Input(UInt(64.W))
+      val ecc_out =  Output(UInt(7.W))
+    })
+    val mask0 = Array(1,1,0,1,1,0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0,1)
+    val mask1 = Array(1,0,1,1,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1,1)
+    val mask2 = Array(0,1,1,1,0,0,0,1,1,1,1,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,1,1,1,1)
+    val mask3 = Array(0,0,0,0,1,1,1,1,1,1,1,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0)
+    val mask4 = Array(0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0)
+    val mask5 = Array(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0)
+    val mask6 = Array(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1)
+
+    val w0 = Wire(Vec(35,UInt(1.W)))
+    val w1 = Wire(Vec(35,UInt(1.W)))
+    val w2 = Wire(Vec(35,UInt(1.W)))
+    val w3 = Wire(Vec(31,UInt(1.W)))
+    val w4 = Wire(Vec(31,UInt(1.W)))
+    val w5 = Wire(Vec(31,UInt(1.W)))
+    val w6 = Wire(Vec(7, UInt(1.W)))
+
+    var j = 0;var k = 0;var m = 0; var n =0;
+    var x = 0;var y = 0;var z = 0
+
+    for(i <- 0 to 63)
+    {
+      if(mask0(i)==1) {w0(j) := io.din(i); j = j +1 }
+      if(mask1(i)==1) {w1(k) := io.din(i); k = k +1 }
+      if(mask2(i)==1) {w2(m) := io.din(i); m = m +1 }
+      if(mask3(i)==1) {w3(n) := io.din(i); n = n +1 }
+      if(mask4(i)==1) {w4(x) := io.din(i); x = x +1 }
+      if(mask5(i)==1) {w5(y) := io.din(i); y = y +1 }
+      if(mask6(i)==1) {w6(z) := io.din(i); z = z +1 }
+    }
+    io.ecc_out := Cat((w6.asUInt.xorR),(w5.asUInt.xorR),(w4.asUInt.xorR),(w3.asUInt.xorR),(w2.asUInt.xorR),(w1.asUInt.xorR),(w0.asUInt.xorR))
+  }
+
   def rvecc_encode_64(din:UInt):UInt = {
     val mask0 = Array(1,1,0,1,1,0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0,1)
     val mask1 = Array(1,0,1,1,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1,1)