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PIC extrinsic updated in quasar

This commit is contained in:
​Laraib Khan 2020-12-18 10:27:40 +05:00
parent 1c41a85c25
commit 07a61a92cf
7 changed files with 18122 additions and 10419 deletions
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170
quasar.anno.json
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@ -1,30 +1,24 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~quasar|quasar>io_ic_sel_premux_data",
"sources":[
"~quasar|quasar>io_ic_rd_hit",
"~quasar|quasar>io_ifu_bus_clk_en",
"~quasar|quasar>io_mpc_reset_run_req",
"~quasar|quasar>io_dccm_rd_data_hi",
"~quasar|quasar>io_dccm_rd_data_lo",
"~quasar|quasar>io_core_id",
"~quasar|quasar>io_extintsrc_req"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~quasar|quasar>io_dccm_rd_addr_lo",
"sources":[
"~quasar|quasar>io_dccm_rd_data_hi",
"~quasar|quasar>io_dccm_rd_data_lo",
"~quasar|quasar>io_extintsrc_req",
"~quasar|quasar>io_mpc_reset_run_req"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~quasar|quasar>io_iccm_wr_data",
"sources":[
"~quasar|quasar>io_iccm_rd_data_ecc",
"~quasar|quasar>io_ic_rd_hit",
"~quasar|quasar>io_ic_rd_data",
"~quasar|quasar>io_ifu_axi_r_bits_id",
"~quasar|quasar>io_ifu_axi_r_valid",
"~quasar|quasar>io_ifu_bus_clk_en",
"~quasar|quasar>io_mpc_reset_run_req",
"~quasar|quasar>io_dccm_rd_data_hi",
"~quasar|quasar>io_dccm_rd_data_lo",
"~quasar|quasar>io_rst_vec",
"~quasar|quasar>io_nmi_vec",
"~quasar|quasar>io_core_id",
"~quasar|quasar>io_extintsrc_req"
]
},
@ -35,8 +29,6 @@
"~quasar|quasar>io_iccm_rd_data_ecc",
"~quasar|quasar>io_ic_rd_hit",
"~quasar|quasar>io_ic_rd_data",
"~quasar|quasar>io_ifu_axi_r_bits_id",
"~quasar|quasar>io_ifu_axi_r_valid",
"~quasar|quasar>io_ifu_bus_clk_en",
"~quasar|quasar>io_mpc_reset_run_req",
"~quasar|quasar>io_rst_vec",
@ -47,21 +39,6 @@
"~quasar|quasar>io_extintsrc_req"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~quasar|quasar>io_ic_sel_premux_data",
"sources":[
"~quasar|quasar>io_ic_rd_hit",
"~quasar|quasar>io_ifu_axi_r_bits_id",
"~quasar|quasar>io_ifu_axi_r_valid",
"~quasar|quasar>io_ifu_bus_clk_en",
"~quasar|quasar>io_mpc_reset_run_req",
"~quasar|quasar>io_dccm_rd_data_hi",
"~quasar|quasar>io_dccm_rd_data_lo",
"~quasar|quasar>io_core_id",
"~quasar|quasar>io_extintsrc_req"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~quasar|quasar>io_ic_rw_addr",
@ -78,13 +55,11 @@
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~quasar|quasar>io_iccm_wr_size",
"sink":"~quasar|quasar>io_iccm_wr_data",
"sources":[
"~quasar|quasar>io_iccm_rd_data_ecc",
"~quasar|quasar>io_ic_rd_hit",
"~quasar|quasar>io_ic_rd_data",
"~quasar|quasar>io_ifu_axi_r_bits_id",
"~quasar|quasar>io_ifu_axi_r_valid",
"~quasar|quasar>io_ifu_bus_clk_en",
"~quasar|quasar>io_mpc_reset_run_req",
"~quasar|quasar>io_dccm_rd_data_hi",
@ -95,16 +70,6 @@
"~quasar|quasar>io_extintsrc_req"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~quasar|quasar>io_dccm_rd_addr_hi",
"sources":[
"~quasar|quasar>io_dccm_rd_data_hi",
"~quasar|quasar>io_dccm_rd_data_lo",
"~quasar|quasar>io_extintsrc_req",
"~quasar|quasar>io_mpc_reset_run_req"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~quasar|quasar>io_iccm_rw_addr",
@ -112,8 +77,6 @@
"~quasar|quasar>io_iccm_rd_data_ecc",
"~quasar|quasar>io_ic_rd_hit",
"~quasar|quasar>io_ic_rd_data",
"~quasar|quasar>io_ifu_axi_r_bits_id",
"~quasar|quasar>io_ifu_axi_r_valid",
"~quasar|quasar>io_ifu_bus_clk_en",
"~quasar|quasar>io_mpc_reset_run_req",
"~quasar|quasar>io_rst_vec",
@ -124,6 +87,49 @@
"~quasar|quasar>io_extintsrc_req"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~quasar|quasar>io_ic_rd_en",
"sources":[
"~quasar|quasar>io_ic_rd_hit",
"~quasar|quasar>io_ic_rd_data",
"~quasar|quasar>io_ifu_bus_clk_en",
"~quasar|quasar>io_mpc_reset_run_req",
"~quasar|quasar>io_rst_vec",
"~quasar|quasar>io_nmi_vec",
"~quasar|quasar>io_core_id",
"~quasar|quasar>io_dccm_rd_data_hi",
"~quasar|quasar>io_dccm_rd_data_lo",
"~quasar|quasar>io_extintsrc_req"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~quasar|quasar>io_dccm_rd_addr_hi",
"sources":[
"~quasar|quasar>io_dccm_rd_data_hi",
"~quasar|quasar>io_dccm_rd_data_lo",
"~quasar|quasar>io_mpc_reset_run_req",
"~quasar|quasar>io_extintsrc_req"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~quasar|quasar>io_iccm_wren",
"sources":[
"~quasar|quasar>io_iccm_rd_data_ecc",
"~quasar|quasar>io_ic_rd_hit",
"~quasar|quasar>io_ic_rd_data",
"~quasar|quasar>io_ifu_bus_clk_en",
"~quasar|quasar>io_mpc_reset_run_req",
"~quasar|quasar>io_dccm_rd_data_hi",
"~quasar|quasar>io_dccm_rd_data_lo",
"~quasar|quasar>io_rst_vec",
"~quasar|quasar>io_nmi_vec",
"~quasar|quasar>io_core_id",
"~quasar|quasar>io_extintsrc_req"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~quasar|quasar>io_dccm_wren",
@ -140,8 +146,8 @@
"sources":[
"~quasar|quasar>io_dccm_rd_data_hi",
"~quasar|quasar>io_dccm_rd_data_lo",
"~quasar|quasar>io_extintsrc_req",
"~quasar|quasar>io_mpc_reset_run_req"
"~quasar|quasar>io_mpc_reset_run_req",
"~quasar|quasar>io_extintsrc_req"
]
},
{
@ -155,25 +161,6 @@
"~quasar|quasar>io_extintsrc_req"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~quasar|quasar>io_iccm_wren",
"sources":[
"~quasar|quasar>io_iccm_rd_data_ecc",
"~quasar|quasar>io_ic_rd_hit",
"~quasar|quasar>io_ic_rd_data",
"~quasar|quasar>io_ifu_axi_r_bits_id",
"~quasar|quasar>io_ifu_axi_r_valid",
"~quasar|quasar>io_ifu_bus_clk_en",
"~quasar|quasar>io_mpc_reset_run_req",
"~quasar|quasar>io_dccm_rd_data_hi",
"~quasar|quasar>io_dccm_rd_data_lo",
"~quasar|quasar>io_rst_vec",
"~quasar|quasar>io_nmi_vec",
"~quasar|quasar>io_core_id",
"~quasar|quasar>io_extintsrc_req"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~quasar|quasar>io_dccm_rden",
@ -194,19 +181,11 @@
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~quasar|quasar>io_ic_rd_en",
"sink":"~quasar|quasar>io_dccm_wr_addr_hi",
"sources":[
"~quasar|quasar>io_ic_rd_hit",
"~quasar|quasar>io_ic_rd_data",
"~quasar|quasar>io_ifu_axi_r_bits_id",
"~quasar|quasar>io_ifu_axi_r_valid",
"~quasar|quasar>io_ifu_bus_clk_en",
"~quasar|quasar>io_mpc_reset_run_req",
"~quasar|quasar>io_rst_vec",
"~quasar|quasar>io_nmi_vec",
"~quasar|quasar>io_core_id",
"~quasar|quasar>io_dccm_rd_data_hi",
"~quasar|quasar>io_dccm_rd_data_lo",
"~quasar|quasar>io_mpc_reset_run_req",
"~quasar|quasar>io_extintsrc_req"
]
},
@ -216,8 +195,6 @@
"sources":[
"~quasar|quasar>io_iccm_rd_data",
"~quasar|quasar>io_ic_rd_hit",
"~quasar|quasar>io_ifu_axi_r_bits_id",
"~quasar|quasar>io_ifu_axi_r_valid",
"~quasar|quasar>io_ifu_bus_clk_en",
"~quasar|quasar>io_mpc_reset_run_req",
"~quasar|quasar>io_dccm_rd_data_hi",
@ -228,12 +205,19 @@
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~quasar|quasar>io_dccm_wr_addr_hi",
"sink":"~quasar|quasar>io_iccm_wr_size",
"sources":[
"~quasar|quasar>io_iccm_rd_data_ecc",
"~quasar|quasar>io_ic_rd_hit",
"~quasar|quasar>io_ic_rd_data",
"~quasar|quasar>io_ifu_bus_clk_en",
"~quasar|quasar>io_mpc_reset_run_req",
"~quasar|quasar>io_dccm_rd_data_hi",
"~quasar|quasar>io_dccm_rd_data_lo",
"~quasar|quasar>io_extintsrc_req",
"~quasar|quasar>io_mpc_reset_run_req"
"~quasar|quasar>io_rst_vec",
"~quasar|quasar>io_nmi_vec",
"~quasar|quasar>io_core_id",
"~quasar|quasar>io_extintsrc_req"
]
},
{
@ -242,8 +226,8 @@
"sources":[
"~quasar|quasar>io_dccm_rd_data_hi",
"~quasar|quasar>io_dccm_rd_data_lo",
"~quasar|quasar>io_extintsrc_req",
"~quasar|quasar>io_mpc_reset_run_req"
"~quasar|quasar>io_mpc_reset_run_req",
"~quasar|quasar>io_extintsrc_req"
]
},
{
@ -252,8 +236,8 @@
"sources":[
"~quasar|quasar>io_dccm_rd_data_hi",
"~quasar|quasar>io_dccm_rd_data_lo",
"~quasar|quasar>io_extintsrc_req",
"~quasar|quasar>io_mpc_reset_run_req"
"~quasar|quasar>io_mpc_reset_run_req",
"~quasar|quasar>io_extintsrc_req"
]
},
{
@ -263,7 +247,7 @@
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"quasar.gated_latch",
"resourceId":"/vsrc/gated_latch.v"
"resourceId":"/vsrc/gated_latch.sv"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
@ -1239,7 +1223,7 @@
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar|csr_tlu>_T_755"
"target":"~quasar|csr_tlu>_T_745"
},
{
"class":"firrtl.options.TargetDirAnnotation",

17703
quasar.fir
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10026
quasar.v
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635
quasar_wrapper.fir
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@ -114324,7 +114324,8 @@ circuit quasar_wrapper :
pic_ctrl_inst.io.free_clk <= rvclkhdr.io.l1clk @[quasar.scala 211:29]
pic_ctrl_inst.io.active_clk <= rvclkhdr_1.io.l1clk @[quasar.scala 212:31]
pic_ctrl_inst.io.clk_override <= dec.io.dec_tlu_pic_clk_override @[quasar.scala 213:33]
pic_ctrl_inst.io.extintsrc_req <= io.extintsrc_req @[quasar.scala 214:34]
node _T_12 = cat(io.extintsrc_req, UInt<1>("h00")) @[Cat.scala 29:58]
pic_ctrl_inst.io.extintsrc_req <= _T_12 @[quasar.scala 214:34]
lsu.io.lsu_pic.picm_rd_data <= pic_ctrl_inst.io.lsu_pic.picm_rd_data @[quasar.scala 215:28]
pic_ctrl_inst.io.lsu_pic.picm_wr_data <= lsu.io.lsu_pic.picm_wr_data @[quasar.scala 215:28]
pic_ctrl_inst.io.lsu_pic.picm_wraddr <= lsu.io.lsu_pic.picm_wraddr @[quasar.scala 215:28]
@ -114597,322 +114598,322 @@ circuit quasar_wrapper :
io.dma_ahb.sig.in.hresp <= ahb_to_axi4.io.ahb.sig.in.hresp @[quasar.scala 269:28]
io.dma_ahb.sig.in.hready <= ahb_to_axi4.io.ahb.sig.in.hready @[quasar.scala 269:28]
io.dma_ahb.sig.in.hrdata <= ahb_to_axi4.io.ahb.sig.in.hrdata @[quasar.scala 269:28]
wire _T_12 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}} @[quasar.scala 271:36]
_T_12.r.bits.last <= UInt<1>("h00") @[quasar.scala 271:36]
_T_12.r.bits.resp <= UInt<2>("h00") @[quasar.scala 271:36]
_T_12.r.bits.data <= UInt<64>("h00") @[quasar.scala 271:36]
_T_12.r.bits.id <= UInt<1>("h00") @[quasar.scala 271:36]
_T_12.r.valid <= UInt<1>("h00") @[quasar.scala 271:36]
_T_12.r.ready <= UInt<1>("h00") @[quasar.scala 271:36]
_T_12.ar.bits.qos <= UInt<4>("h00") @[quasar.scala 271:36]
_T_12.ar.bits.prot <= UInt<3>("h00") @[quasar.scala 271:36]
_T_12.ar.bits.cache <= UInt<4>("h00") @[quasar.scala 271:36]
_T_12.ar.bits.lock <= UInt<1>("h00") @[quasar.scala 271:36]
_T_12.ar.bits.burst <= UInt<2>("h00") @[quasar.scala 271:36]
_T_12.ar.bits.size <= UInt<3>("h00") @[quasar.scala 271:36]
_T_12.ar.bits.len <= UInt<8>("h00") @[quasar.scala 271:36]
_T_12.ar.bits.region <= UInt<4>("h00") @[quasar.scala 271:36]
_T_12.ar.bits.addr <= UInt<32>("h00") @[quasar.scala 271:36]
_T_12.ar.bits.id <= UInt<1>("h00") @[quasar.scala 271:36]
_T_12.ar.valid <= UInt<1>("h00") @[quasar.scala 271:36]
_T_12.ar.ready <= UInt<1>("h00") @[quasar.scala 271:36]
_T_12.b.bits.id <= UInt<1>("h00") @[quasar.scala 271:36]
_T_12.b.bits.resp <= UInt<2>("h00") @[quasar.scala 271:36]
_T_12.b.valid <= UInt<1>("h00") @[quasar.scala 271:36]
_T_12.b.ready <= UInt<1>("h00") @[quasar.scala 271:36]
_T_12.w.bits.last <= UInt<1>("h00") @[quasar.scala 271:36]
_T_12.w.bits.strb <= UInt<8>("h00") @[quasar.scala 271:36]
_T_12.w.bits.data <= UInt<64>("h00") @[quasar.scala 271:36]
_T_12.w.valid <= UInt<1>("h00") @[quasar.scala 271:36]
_T_12.w.ready <= UInt<1>("h00") @[quasar.scala 271:36]
_T_12.aw.bits.qos <= UInt<4>("h00") @[quasar.scala 271:36]
_T_12.aw.bits.prot <= UInt<3>("h00") @[quasar.scala 271:36]
_T_12.aw.bits.cache <= UInt<4>("h00") @[quasar.scala 271:36]
_T_12.aw.bits.lock <= UInt<1>("h00") @[quasar.scala 271:36]
_T_12.aw.bits.burst <= UInt<2>("h00") @[quasar.scala 271:36]
_T_12.aw.bits.size <= UInt<3>("h00") @[quasar.scala 271:36]
_T_12.aw.bits.len <= UInt<8>("h00") @[quasar.scala 271:36]
_T_12.aw.bits.region <= UInt<4>("h00") @[quasar.scala 271:36]
_T_12.aw.bits.addr <= UInt<32>("h00") @[quasar.scala 271:36]
_T_12.aw.bits.id <= UInt<1>("h00") @[quasar.scala 271:36]
_T_12.aw.valid <= UInt<1>("h00") @[quasar.scala 271:36]
_T_12.aw.ready <= UInt<1>("h00") @[quasar.scala 271:36]
io.dma_axi.r.bits.last <= _T_12.r.bits.last @[quasar.scala 271:21]
io.dma_axi.r.bits.resp <= _T_12.r.bits.resp @[quasar.scala 271:21]
io.dma_axi.r.bits.data <= _T_12.r.bits.data @[quasar.scala 271:21]
io.dma_axi.r.bits.id <= _T_12.r.bits.id @[quasar.scala 271:21]
io.dma_axi.r.valid <= _T_12.r.valid @[quasar.scala 271:21]
_T_12.r.ready <= io.dma_axi.r.ready @[quasar.scala 271:21]
_T_12.ar.bits.qos <= io.dma_axi.ar.bits.qos @[quasar.scala 271:21]
_T_12.ar.bits.prot <= io.dma_axi.ar.bits.prot @[quasar.scala 271:21]
_T_12.ar.bits.cache <= io.dma_axi.ar.bits.cache @[quasar.scala 271:21]
_T_12.ar.bits.lock <= io.dma_axi.ar.bits.lock @[quasar.scala 271:21]
_T_12.ar.bits.burst <= io.dma_axi.ar.bits.burst @[quasar.scala 271:21]
_T_12.ar.bits.size <= io.dma_axi.ar.bits.size @[quasar.scala 271:21]
_T_12.ar.bits.len <= io.dma_axi.ar.bits.len @[quasar.scala 271:21]
_T_12.ar.bits.region <= io.dma_axi.ar.bits.region @[quasar.scala 271:21]
_T_12.ar.bits.addr <= io.dma_axi.ar.bits.addr @[quasar.scala 271:21]
_T_12.ar.bits.id <= io.dma_axi.ar.bits.id @[quasar.scala 271:21]
_T_12.ar.valid <= io.dma_axi.ar.valid @[quasar.scala 271:21]
io.dma_axi.ar.ready <= _T_12.ar.ready @[quasar.scala 271:21]
io.dma_axi.b.bits.id <= _T_12.b.bits.id @[quasar.scala 271:21]
io.dma_axi.b.bits.resp <= _T_12.b.bits.resp @[quasar.scala 271:21]
io.dma_axi.b.valid <= _T_12.b.valid @[quasar.scala 271:21]
_T_12.b.ready <= io.dma_axi.b.ready @[quasar.scala 271:21]
_T_12.w.bits.last <= io.dma_axi.w.bits.last @[quasar.scala 271:21]
_T_12.w.bits.strb <= io.dma_axi.w.bits.strb @[quasar.scala 271:21]
_T_12.w.bits.data <= io.dma_axi.w.bits.data @[quasar.scala 271:21]
_T_12.w.valid <= io.dma_axi.w.valid @[quasar.scala 271:21]
io.dma_axi.w.ready <= _T_12.w.ready @[quasar.scala 271:21]
_T_12.aw.bits.qos <= io.dma_axi.aw.bits.qos @[quasar.scala 271:21]
_T_12.aw.bits.prot <= io.dma_axi.aw.bits.prot @[quasar.scala 271:21]
_T_12.aw.bits.cache <= io.dma_axi.aw.bits.cache @[quasar.scala 271:21]
_T_12.aw.bits.lock <= io.dma_axi.aw.bits.lock @[quasar.scala 271:21]
_T_12.aw.bits.burst <= io.dma_axi.aw.bits.burst @[quasar.scala 271:21]
_T_12.aw.bits.size <= io.dma_axi.aw.bits.size @[quasar.scala 271:21]
_T_12.aw.bits.len <= io.dma_axi.aw.bits.len @[quasar.scala 271:21]
_T_12.aw.bits.region <= io.dma_axi.aw.bits.region @[quasar.scala 271:21]
_T_12.aw.bits.addr <= io.dma_axi.aw.bits.addr @[quasar.scala 271:21]
_T_12.aw.bits.id <= io.dma_axi.aw.bits.id @[quasar.scala 271:21]
_T_12.aw.valid <= io.dma_axi.aw.valid @[quasar.scala 271:21]
io.dma_axi.aw.ready <= _T_12.aw.ready @[quasar.scala 271:21]
wire _T_13 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}} @[quasar.scala 272:36]
_T_13.r.bits.last <= UInt<1>("h00") @[quasar.scala 272:36]
_T_13.r.bits.resp <= UInt<2>("h00") @[quasar.scala 272:36]
_T_13.r.bits.data <= UInt<64>("h00") @[quasar.scala 272:36]
_T_13.r.bits.id <= UInt<1>("h00") @[quasar.scala 272:36]
_T_13.r.valid <= UInt<1>("h00") @[quasar.scala 272:36]
_T_13.r.ready <= UInt<1>("h00") @[quasar.scala 272:36]
_T_13.ar.bits.qos <= UInt<4>("h00") @[quasar.scala 272:36]
_T_13.ar.bits.prot <= UInt<3>("h00") @[quasar.scala 272:36]
_T_13.ar.bits.cache <= UInt<4>("h00") @[quasar.scala 272:36]
_T_13.ar.bits.lock <= UInt<1>("h00") @[quasar.scala 272:36]
_T_13.ar.bits.burst <= UInt<2>("h00") @[quasar.scala 272:36]
_T_13.ar.bits.size <= UInt<3>("h00") @[quasar.scala 272:36]
_T_13.ar.bits.len <= UInt<8>("h00") @[quasar.scala 272:36]
_T_13.ar.bits.region <= UInt<4>("h00") @[quasar.scala 272:36]
_T_13.ar.bits.addr <= UInt<32>("h00") @[quasar.scala 272:36]
_T_13.ar.bits.id <= UInt<1>("h00") @[quasar.scala 272:36]
_T_13.ar.valid <= UInt<1>("h00") @[quasar.scala 272:36]
_T_13.ar.ready <= UInt<1>("h00") @[quasar.scala 272:36]
_T_13.b.bits.id <= UInt<1>("h00") @[quasar.scala 272:36]
_T_13.b.bits.resp <= UInt<2>("h00") @[quasar.scala 272:36]
_T_13.b.valid <= UInt<1>("h00") @[quasar.scala 272:36]
_T_13.b.ready <= UInt<1>("h00") @[quasar.scala 272:36]
_T_13.w.bits.last <= UInt<1>("h00") @[quasar.scala 272:36]
_T_13.w.bits.strb <= UInt<8>("h00") @[quasar.scala 272:36]
_T_13.w.bits.data <= UInt<64>("h00") @[quasar.scala 272:36]
_T_13.w.valid <= UInt<1>("h00") @[quasar.scala 272:36]
_T_13.w.ready <= UInt<1>("h00") @[quasar.scala 272:36]
_T_13.aw.bits.qos <= UInt<4>("h00") @[quasar.scala 272:36]
_T_13.aw.bits.prot <= UInt<3>("h00") @[quasar.scala 272:36]
_T_13.aw.bits.cache <= UInt<4>("h00") @[quasar.scala 272:36]
_T_13.aw.bits.lock <= UInt<1>("h00") @[quasar.scala 272:36]
_T_13.aw.bits.burst <= UInt<2>("h00") @[quasar.scala 272:36]
_T_13.aw.bits.size <= UInt<3>("h00") @[quasar.scala 272:36]
_T_13.aw.bits.len <= UInt<8>("h00") @[quasar.scala 272:36]
_T_13.aw.bits.region <= UInt<4>("h00") @[quasar.scala 272:36]
_T_13.aw.bits.addr <= UInt<32>("h00") @[quasar.scala 272:36]
_T_13.aw.bits.id <= UInt<1>("h00") @[quasar.scala 272:36]
_T_13.aw.valid <= UInt<1>("h00") @[quasar.scala 272:36]
_T_13.aw.ready <= UInt<1>("h00") @[quasar.scala 272:36]
_T_13.r.bits.last <= io.sb_axi.r.bits.last @[quasar.scala 272:21]
_T_13.r.bits.resp <= io.sb_axi.r.bits.resp @[quasar.scala 272:21]
_T_13.r.bits.data <= io.sb_axi.r.bits.data @[quasar.scala 272:21]
_T_13.r.bits.id <= io.sb_axi.r.bits.id @[quasar.scala 272:21]
_T_13.r.valid <= io.sb_axi.r.valid @[quasar.scala 272:21]
io.sb_axi.r.ready <= _T_13.r.ready @[quasar.scala 272:21]
io.sb_axi.ar.bits.qos <= _T_13.ar.bits.qos @[quasar.scala 272:21]
io.sb_axi.ar.bits.prot <= _T_13.ar.bits.prot @[quasar.scala 272:21]
io.sb_axi.ar.bits.cache <= _T_13.ar.bits.cache @[quasar.scala 272:21]
io.sb_axi.ar.bits.lock <= _T_13.ar.bits.lock @[quasar.scala 272:21]
io.sb_axi.ar.bits.burst <= _T_13.ar.bits.burst @[quasar.scala 272:21]
io.sb_axi.ar.bits.size <= _T_13.ar.bits.size @[quasar.scala 272:21]
io.sb_axi.ar.bits.len <= _T_13.ar.bits.len @[quasar.scala 272:21]
io.sb_axi.ar.bits.region <= _T_13.ar.bits.region @[quasar.scala 272:21]
io.sb_axi.ar.bits.addr <= _T_13.ar.bits.addr @[quasar.scala 272:21]
io.sb_axi.ar.bits.id <= _T_13.ar.bits.id @[quasar.scala 272:21]
io.sb_axi.ar.valid <= _T_13.ar.valid @[quasar.scala 272:21]
_T_13.ar.ready <= io.sb_axi.ar.ready @[quasar.scala 272:21]
_T_13.b.bits.id <= io.sb_axi.b.bits.id @[quasar.scala 272:21]
_T_13.b.bits.resp <= io.sb_axi.b.bits.resp @[quasar.scala 272:21]
_T_13.b.valid <= io.sb_axi.b.valid @[quasar.scala 272:21]
io.sb_axi.b.ready <= _T_13.b.ready @[quasar.scala 272:21]
io.sb_axi.w.bits.last <= _T_13.w.bits.last @[quasar.scala 272:21]
io.sb_axi.w.bits.strb <= _T_13.w.bits.strb @[quasar.scala 272:21]
io.sb_axi.w.bits.data <= _T_13.w.bits.data @[quasar.scala 272:21]
io.sb_axi.w.valid <= _T_13.w.valid @[quasar.scala 272:21]
_T_13.w.ready <= io.sb_axi.w.ready @[quasar.scala 272:21]
io.sb_axi.aw.bits.qos <= _T_13.aw.bits.qos @[quasar.scala 272:21]
io.sb_axi.aw.bits.prot <= _T_13.aw.bits.prot @[quasar.scala 272:21]
io.sb_axi.aw.bits.cache <= _T_13.aw.bits.cache @[quasar.scala 272:21]
io.sb_axi.aw.bits.lock <= _T_13.aw.bits.lock @[quasar.scala 272:21]
io.sb_axi.aw.bits.burst <= _T_13.aw.bits.burst @[quasar.scala 272:21]
io.sb_axi.aw.bits.size <= _T_13.aw.bits.size @[quasar.scala 272:21]
io.sb_axi.aw.bits.len <= _T_13.aw.bits.len @[quasar.scala 272:21]
io.sb_axi.aw.bits.region <= _T_13.aw.bits.region @[quasar.scala 272:21]
io.sb_axi.aw.bits.addr <= _T_13.aw.bits.addr @[quasar.scala 272:21]
io.sb_axi.aw.bits.id <= _T_13.aw.bits.id @[quasar.scala 272:21]
io.sb_axi.aw.valid <= _T_13.aw.valid @[quasar.scala 272:21]
_T_13.aw.ready <= io.sb_axi.aw.ready @[quasar.scala 272:21]
wire _T_14 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}} @[quasar.scala 273:36]
_T_14.r.bits.last <= UInt<1>("h00") @[quasar.scala 273:36]
_T_14.r.bits.resp <= UInt<2>("h00") @[quasar.scala 273:36]
_T_14.r.bits.data <= UInt<64>("h00") @[quasar.scala 273:36]
_T_14.r.bits.id <= UInt<3>("h00") @[quasar.scala 273:36]
_T_14.r.valid <= UInt<1>("h00") @[quasar.scala 273:36]
_T_14.r.ready <= UInt<1>("h00") @[quasar.scala 273:36]
_T_14.ar.bits.qos <= UInt<4>("h00") @[quasar.scala 273:36]
_T_14.ar.bits.prot <= UInt<3>("h00") @[quasar.scala 273:36]
_T_14.ar.bits.cache <= UInt<4>("h00") @[quasar.scala 273:36]
_T_14.ar.bits.lock <= UInt<1>("h00") @[quasar.scala 273:36]
_T_14.ar.bits.burst <= UInt<2>("h00") @[quasar.scala 273:36]
_T_14.ar.bits.size <= UInt<3>("h00") @[quasar.scala 273:36]
_T_14.ar.bits.len <= UInt<8>("h00") @[quasar.scala 273:36]
_T_14.ar.bits.region <= UInt<4>("h00") @[quasar.scala 273:36]
_T_14.ar.bits.addr <= UInt<32>("h00") @[quasar.scala 273:36]
_T_14.ar.bits.id <= UInt<3>("h00") @[quasar.scala 273:36]
_T_14.ar.valid <= UInt<1>("h00") @[quasar.scala 273:36]
_T_14.ar.ready <= UInt<1>("h00") @[quasar.scala 273:36]
_T_14.b.bits.id <= UInt<3>("h00") @[quasar.scala 273:36]
_T_14.b.bits.resp <= UInt<2>("h00") @[quasar.scala 273:36]
_T_14.b.valid <= UInt<1>("h00") @[quasar.scala 273:36]
_T_14.b.ready <= UInt<1>("h00") @[quasar.scala 273:36]
_T_14.w.bits.last <= UInt<1>("h00") @[quasar.scala 273:36]
_T_14.w.bits.strb <= UInt<8>("h00") @[quasar.scala 273:36]
_T_14.w.bits.data <= UInt<64>("h00") @[quasar.scala 273:36]
_T_14.w.valid <= UInt<1>("h00") @[quasar.scala 273:36]
_T_14.w.ready <= UInt<1>("h00") @[quasar.scala 273:36]
_T_14.aw.bits.qos <= UInt<4>("h00") @[quasar.scala 273:36]
_T_14.aw.bits.prot <= UInt<3>("h00") @[quasar.scala 273:36]
_T_14.aw.bits.cache <= UInt<4>("h00") @[quasar.scala 273:36]
_T_14.aw.bits.lock <= UInt<1>("h00") @[quasar.scala 273:36]
_T_14.aw.bits.burst <= UInt<2>("h00") @[quasar.scala 273:36]
_T_14.aw.bits.size <= UInt<3>("h00") @[quasar.scala 273:36]
_T_14.aw.bits.len <= UInt<8>("h00") @[quasar.scala 273:36]
_T_14.aw.bits.region <= UInt<4>("h00") @[quasar.scala 273:36]
_T_14.aw.bits.addr <= UInt<32>("h00") @[quasar.scala 273:36]
_T_14.aw.bits.id <= UInt<3>("h00") @[quasar.scala 273:36]
_T_14.aw.valid <= UInt<1>("h00") @[quasar.scala 273:36]
_T_14.aw.ready <= UInt<1>("h00") @[quasar.scala 273:36]
_T_14.r.bits.last <= io.ifu_axi.r.bits.last @[quasar.scala 273:21]
_T_14.r.bits.resp <= io.ifu_axi.r.bits.resp @[quasar.scala 273:21]
_T_14.r.bits.data <= io.ifu_axi.r.bits.data @[quasar.scala 273:21]
_T_14.r.bits.id <= io.ifu_axi.r.bits.id @[quasar.scala 273:21]
_T_14.r.valid <= io.ifu_axi.r.valid @[quasar.scala 273:21]
io.ifu_axi.r.ready <= _T_14.r.ready @[quasar.scala 273:21]
io.ifu_axi.ar.bits.qos <= _T_14.ar.bits.qos @[quasar.scala 273:21]
io.ifu_axi.ar.bits.prot <= _T_14.ar.bits.prot @[quasar.scala 273:21]
io.ifu_axi.ar.bits.cache <= _T_14.ar.bits.cache @[quasar.scala 273:21]
io.ifu_axi.ar.bits.lock <= _T_14.ar.bits.lock @[quasar.scala 273:21]
io.ifu_axi.ar.bits.burst <= _T_14.ar.bits.burst @[quasar.scala 273:21]
io.ifu_axi.ar.bits.size <= _T_14.ar.bits.size @[quasar.scala 273:21]
io.ifu_axi.ar.bits.len <= _T_14.ar.bits.len @[quasar.scala 273:21]
io.ifu_axi.ar.bits.region <= _T_14.ar.bits.region @[quasar.scala 273:21]
io.ifu_axi.ar.bits.addr <= _T_14.ar.bits.addr @[quasar.scala 273:21]
io.ifu_axi.ar.bits.id <= _T_14.ar.bits.id @[quasar.scala 273:21]
io.ifu_axi.ar.valid <= _T_14.ar.valid @[quasar.scala 273:21]
_T_14.ar.ready <= io.ifu_axi.ar.ready @[quasar.scala 273:21]
_T_14.b.bits.id <= io.ifu_axi.b.bits.id @[quasar.scala 273:21]
_T_14.b.bits.resp <= io.ifu_axi.b.bits.resp @[quasar.scala 273:21]
_T_14.b.valid <= io.ifu_axi.b.valid @[quasar.scala 273:21]
io.ifu_axi.b.ready <= _T_14.b.ready @[quasar.scala 273:21]
io.ifu_axi.w.bits.last <= _T_14.w.bits.last @[quasar.scala 273:21]
io.ifu_axi.w.bits.strb <= _T_14.w.bits.strb @[quasar.scala 273:21]
io.ifu_axi.w.bits.data <= _T_14.w.bits.data @[quasar.scala 273:21]
io.ifu_axi.w.valid <= _T_14.w.valid @[quasar.scala 273:21]
_T_14.w.ready <= io.ifu_axi.w.ready @[quasar.scala 273:21]
io.ifu_axi.aw.bits.qos <= _T_14.aw.bits.qos @[quasar.scala 273:21]
io.ifu_axi.aw.bits.prot <= _T_14.aw.bits.prot @[quasar.scala 273:21]
io.ifu_axi.aw.bits.cache <= _T_14.aw.bits.cache @[quasar.scala 273:21]
io.ifu_axi.aw.bits.lock <= _T_14.aw.bits.lock @[quasar.scala 273:21]
io.ifu_axi.aw.bits.burst <= _T_14.aw.bits.burst @[quasar.scala 273:21]
io.ifu_axi.aw.bits.size <= _T_14.aw.bits.size @[quasar.scala 273:21]
io.ifu_axi.aw.bits.len <= _T_14.aw.bits.len @[quasar.scala 273:21]
io.ifu_axi.aw.bits.region <= _T_14.aw.bits.region @[quasar.scala 273:21]
io.ifu_axi.aw.bits.addr <= _T_14.aw.bits.addr @[quasar.scala 273:21]
io.ifu_axi.aw.bits.id <= _T_14.aw.bits.id @[quasar.scala 273:21]
io.ifu_axi.aw.valid <= _T_14.aw.valid @[quasar.scala 273:21]
_T_14.aw.ready <= io.ifu_axi.aw.ready @[quasar.scala 273:21]
wire _T_15 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}} @[quasar.scala 274:36]
_T_15.r.bits.last <= UInt<1>("h00") @[quasar.scala 274:36]
_T_15.r.bits.resp <= UInt<2>("h00") @[quasar.scala 274:36]
_T_15.r.bits.data <= UInt<64>("h00") @[quasar.scala 274:36]
_T_15.r.bits.id <= UInt<3>("h00") @[quasar.scala 274:36]
_T_15.r.valid <= UInt<1>("h00") @[quasar.scala 274:36]
_T_15.r.ready <= UInt<1>("h00") @[quasar.scala 274:36]
_T_15.ar.bits.qos <= UInt<4>("h00") @[quasar.scala 274:36]
_T_15.ar.bits.prot <= UInt<3>("h00") @[quasar.scala 274:36]
_T_15.ar.bits.cache <= UInt<4>("h00") @[quasar.scala 274:36]
_T_15.ar.bits.lock <= UInt<1>("h00") @[quasar.scala 274:36]
_T_15.ar.bits.burst <= UInt<2>("h00") @[quasar.scala 274:36]
_T_15.ar.bits.size <= UInt<3>("h00") @[quasar.scala 274:36]
_T_15.ar.bits.len <= UInt<8>("h00") @[quasar.scala 274:36]
_T_15.ar.bits.region <= UInt<4>("h00") @[quasar.scala 274:36]
_T_15.ar.bits.addr <= UInt<32>("h00") @[quasar.scala 274:36]
_T_15.ar.bits.id <= UInt<3>("h00") @[quasar.scala 274:36]
_T_15.ar.valid <= UInt<1>("h00") @[quasar.scala 274:36]
_T_15.ar.ready <= UInt<1>("h00") @[quasar.scala 274:36]
_T_15.b.bits.id <= UInt<3>("h00") @[quasar.scala 274:36]
_T_15.b.bits.resp <= UInt<2>("h00") @[quasar.scala 274:36]
_T_15.b.valid <= UInt<1>("h00") @[quasar.scala 274:36]
_T_15.b.ready <= UInt<1>("h00") @[quasar.scala 274:36]
_T_15.w.bits.last <= UInt<1>("h00") @[quasar.scala 274:36]
_T_15.w.bits.strb <= UInt<8>("h00") @[quasar.scala 274:36]
_T_15.w.bits.data <= UInt<64>("h00") @[quasar.scala 274:36]
_T_15.w.valid <= UInt<1>("h00") @[quasar.scala 274:36]
_T_15.w.ready <= UInt<1>("h00") @[quasar.scala 274:36]
_T_15.aw.bits.qos <= UInt<4>("h00") @[quasar.scala 274:36]
_T_15.aw.bits.prot <= UInt<3>("h00") @[quasar.scala 274:36]
_T_15.aw.bits.cache <= UInt<4>("h00") @[quasar.scala 274:36]
_T_15.aw.bits.lock <= UInt<1>("h00") @[quasar.scala 274:36]
_T_15.aw.bits.burst <= UInt<2>("h00") @[quasar.scala 274:36]
_T_15.aw.bits.size <= UInt<3>("h00") @[quasar.scala 274:36]
_T_15.aw.bits.len <= UInt<8>("h00") @[quasar.scala 274:36]
_T_15.aw.bits.region <= UInt<4>("h00") @[quasar.scala 274:36]
_T_15.aw.bits.addr <= UInt<32>("h00") @[quasar.scala 274:36]
_T_15.aw.bits.id <= UInt<3>("h00") @[quasar.scala 274:36]
_T_15.aw.valid <= UInt<1>("h00") @[quasar.scala 274:36]
_T_15.aw.ready <= UInt<1>("h00") @[quasar.scala 274:36]
_T_15.r.bits.last <= io.lsu_axi.r.bits.last @[quasar.scala 274:21]
_T_15.r.bits.resp <= io.lsu_axi.r.bits.resp @[quasar.scala 274:21]
_T_15.r.bits.data <= io.lsu_axi.r.bits.data @[quasar.scala 274:21]
_T_15.r.bits.id <= io.lsu_axi.r.bits.id @[quasar.scala 274:21]
_T_15.r.valid <= io.lsu_axi.r.valid @[quasar.scala 274:21]
io.lsu_axi.r.ready <= _T_15.r.ready @[quasar.scala 274:21]
io.lsu_axi.ar.bits.qos <= _T_15.ar.bits.qos @[quasar.scala 274:21]
io.lsu_axi.ar.bits.prot <= _T_15.ar.bits.prot @[quasar.scala 274:21]
io.lsu_axi.ar.bits.cache <= _T_15.ar.bits.cache @[quasar.scala 274:21]
io.lsu_axi.ar.bits.lock <= _T_15.ar.bits.lock @[quasar.scala 274:21]
io.lsu_axi.ar.bits.burst <= _T_15.ar.bits.burst @[quasar.scala 274:21]
io.lsu_axi.ar.bits.size <= _T_15.ar.bits.size @[quasar.scala 274:21]
io.lsu_axi.ar.bits.len <= _T_15.ar.bits.len @[quasar.scala 274:21]
io.lsu_axi.ar.bits.region <= _T_15.ar.bits.region @[quasar.scala 274:21]
io.lsu_axi.ar.bits.addr <= _T_15.ar.bits.addr @[quasar.scala 274:21]
io.lsu_axi.ar.bits.id <= _T_15.ar.bits.id @[quasar.scala 274:21]
io.lsu_axi.ar.valid <= _T_15.ar.valid @[quasar.scala 274:21]
_T_15.ar.ready <= io.lsu_axi.ar.ready @[quasar.scala 274:21]
_T_15.b.bits.id <= io.lsu_axi.b.bits.id @[quasar.scala 274:21]
_T_15.b.bits.resp <= io.lsu_axi.b.bits.resp @[quasar.scala 274:21]
_T_15.b.valid <= io.lsu_axi.b.valid @[quasar.scala 274:21]
io.lsu_axi.b.ready <= _T_15.b.ready @[quasar.scala 274:21]
io.lsu_axi.w.bits.last <= _T_15.w.bits.last @[quasar.scala 274:21]
io.lsu_axi.w.bits.strb <= _T_15.w.bits.strb @[quasar.scala 274:21]
io.lsu_axi.w.bits.data <= _T_15.w.bits.data @[quasar.scala 274:21]
io.lsu_axi.w.valid <= _T_15.w.valid @[quasar.scala 274:21]
_T_15.w.ready <= io.lsu_axi.w.ready @[quasar.scala 274:21]
io.lsu_axi.aw.bits.qos <= _T_15.aw.bits.qos @[quasar.scala 274:21]
io.lsu_axi.aw.bits.prot <= _T_15.aw.bits.prot @[quasar.scala 274:21]
io.lsu_axi.aw.bits.cache <= _T_15.aw.bits.cache @[quasar.scala 274:21]
io.lsu_axi.aw.bits.lock <= _T_15.aw.bits.lock @[quasar.scala 274:21]
io.lsu_axi.aw.bits.burst <= _T_15.aw.bits.burst @[quasar.scala 274:21]
io.lsu_axi.aw.bits.size <= _T_15.aw.bits.size @[quasar.scala 274:21]
io.lsu_axi.aw.bits.len <= _T_15.aw.bits.len @[quasar.scala 274:21]
io.lsu_axi.aw.bits.region <= _T_15.aw.bits.region @[quasar.scala 274:21]
io.lsu_axi.aw.bits.addr <= _T_15.aw.bits.addr @[quasar.scala 274:21]
io.lsu_axi.aw.bits.id <= _T_15.aw.bits.id @[quasar.scala 274:21]
io.lsu_axi.aw.valid <= _T_15.aw.valid @[quasar.scala 274:21]
_T_15.aw.ready <= io.lsu_axi.aw.ready @[quasar.scala 274:21]
wire _T_13 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}} @[quasar.scala 271:36]
_T_13.r.bits.last <= UInt<1>("h00") @[quasar.scala 271:36]
_T_13.r.bits.resp <= UInt<2>("h00") @[quasar.scala 271:36]
_T_13.r.bits.data <= UInt<64>("h00") @[quasar.scala 271:36]
_T_13.r.bits.id <= UInt<1>("h00") @[quasar.scala 271:36]
_T_13.r.valid <= UInt<1>("h00") @[quasar.scala 271:36]
_T_13.r.ready <= UInt<1>("h00") @[quasar.scala 271:36]
_T_13.ar.bits.qos <= UInt<4>("h00") @[quasar.scala 271:36]
_T_13.ar.bits.prot <= UInt<3>("h00") @[quasar.scala 271:36]
_T_13.ar.bits.cache <= UInt<4>("h00") @[quasar.scala 271:36]
_T_13.ar.bits.lock <= UInt<1>("h00") @[quasar.scala 271:36]
_T_13.ar.bits.burst <= UInt<2>("h00") @[quasar.scala 271:36]
_T_13.ar.bits.size <= UInt<3>("h00") @[quasar.scala 271:36]
_T_13.ar.bits.len <= UInt<8>("h00") @[quasar.scala 271:36]
_T_13.ar.bits.region <= UInt<4>("h00") @[quasar.scala 271:36]
_T_13.ar.bits.addr <= UInt<32>("h00") @[quasar.scala 271:36]
_T_13.ar.bits.id <= UInt<1>("h00") @[quasar.scala 271:36]
_T_13.ar.valid <= UInt<1>("h00") @[quasar.scala 271:36]
_T_13.ar.ready <= UInt<1>("h00") @[quasar.scala 271:36]
_T_13.b.bits.id <= UInt<1>("h00") @[quasar.scala 271:36]
_T_13.b.bits.resp <= UInt<2>("h00") @[quasar.scala 271:36]
_T_13.b.valid <= UInt<1>("h00") @[quasar.scala 271:36]
_T_13.b.ready <= UInt<1>("h00") @[quasar.scala 271:36]
_T_13.w.bits.last <= UInt<1>("h00") @[quasar.scala 271:36]
_T_13.w.bits.strb <= UInt<8>("h00") @[quasar.scala 271:36]
_T_13.w.bits.data <= UInt<64>("h00") @[quasar.scala 271:36]
_T_13.w.valid <= UInt<1>("h00") @[quasar.scala 271:36]
_T_13.w.ready <= UInt<1>("h00") @[quasar.scala 271:36]
_T_13.aw.bits.qos <= UInt<4>("h00") @[quasar.scala 271:36]
_T_13.aw.bits.prot <= UInt<3>("h00") @[quasar.scala 271:36]
_T_13.aw.bits.cache <= UInt<4>("h00") @[quasar.scala 271:36]
_T_13.aw.bits.lock <= UInt<1>("h00") @[quasar.scala 271:36]
_T_13.aw.bits.burst <= UInt<2>("h00") @[quasar.scala 271:36]
_T_13.aw.bits.size <= UInt<3>("h00") @[quasar.scala 271:36]
_T_13.aw.bits.len <= UInt<8>("h00") @[quasar.scala 271:36]
_T_13.aw.bits.region <= UInt<4>("h00") @[quasar.scala 271:36]
_T_13.aw.bits.addr <= UInt<32>("h00") @[quasar.scala 271:36]
_T_13.aw.bits.id <= UInt<1>("h00") @[quasar.scala 271:36]
_T_13.aw.valid <= UInt<1>("h00") @[quasar.scala 271:36]
_T_13.aw.ready <= UInt<1>("h00") @[quasar.scala 271:36]
io.dma_axi.r.bits.last <= _T_13.r.bits.last @[quasar.scala 271:21]
io.dma_axi.r.bits.resp <= _T_13.r.bits.resp @[quasar.scala 271:21]
io.dma_axi.r.bits.data <= _T_13.r.bits.data @[quasar.scala 271:21]
io.dma_axi.r.bits.id <= _T_13.r.bits.id @[quasar.scala 271:21]
io.dma_axi.r.valid <= _T_13.r.valid @[quasar.scala 271:21]
_T_13.r.ready <= io.dma_axi.r.ready @[quasar.scala 271:21]
_T_13.ar.bits.qos <= io.dma_axi.ar.bits.qos @[quasar.scala 271:21]
_T_13.ar.bits.prot <= io.dma_axi.ar.bits.prot @[quasar.scala 271:21]
_T_13.ar.bits.cache <= io.dma_axi.ar.bits.cache @[quasar.scala 271:21]
_T_13.ar.bits.lock <= io.dma_axi.ar.bits.lock @[quasar.scala 271:21]
_T_13.ar.bits.burst <= io.dma_axi.ar.bits.burst @[quasar.scala 271:21]
_T_13.ar.bits.size <= io.dma_axi.ar.bits.size @[quasar.scala 271:21]
_T_13.ar.bits.len <= io.dma_axi.ar.bits.len @[quasar.scala 271:21]
_T_13.ar.bits.region <= io.dma_axi.ar.bits.region @[quasar.scala 271:21]
_T_13.ar.bits.addr <= io.dma_axi.ar.bits.addr @[quasar.scala 271:21]
_T_13.ar.bits.id <= io.dma_axi.ar.bits.id @[quasar.scala 271:21]
_T_13.ar.valid <= io.dma_axi.ar.valid @[quasar.scala 271:21]
io.dma_axi.ar.ready <= _T_13.ar.ready @[quasar.scala 271:21]
io.dma_axi.b.bits.id <= _T_13.b.bits.id @[quasar.scala 271:21]
io.dma_axi.b.bits.resp <= _T_13.b.bits.resp @[quasar.scala 271:21]
io.dma_axi.b.valid <= _T_13.b.valid @[quasar.scala 271:21]
_T_13.b.ready <= io.dma_axi.b.ready @[quasar.scala 271:21]
_T_13.w.bits.last <= io.dma_axi.w.bits.last @[quasar.scala 271:21]
_T_13.w.bits.strb <= io.dma_axi.w.bits.strb @[quasar.scala 271:21]
_T_13.w.bits.data <= io.dma_axi.w.bits.data @[quasar.scala 271:21]
_T_13.w.valid <= io.dma_axi.w.valid @[quasar.scala 271:21]
io.dma_axi.w.ready <= _T_13.w.ready @[quasar.scala 271:21]
_T_13.aw.bits.qos <= io.dma_axi.aw.bits.qos @[quasar.scala 271:21]
_T_13.aw.bits.prot <= io.dma_axi.aw.bits.prot @[quasar.scala 271:21]
_T_13.aw.bits.cache <= io.dma_axi.aw.bits.cache @[quasar.scala 271:21]
_T_13.aw.bits.lock <= io.dma_axi.aw.bits.lock @[quasar.scala 271:21]
_T_13.aw.bits.burst <= io.dma_axi.aw.bits.burst @[quasar.scala 271:21]
_T_13.aw.bits.size <= io.dma_axi.aw.bits.size @[quasar.scala 271:21]
_T_13.aw.bits.len <= io.dma_axi.aw.bits.len @[quasar.scala 271:21]
_T_13.aw.bits.region <= io.dma_axi.aw.bits.region @[quasar.scala 271:21]
_T_13.aw.bits.addr <= io.dma_axi.aw.bits.addr @[quasar.scala 271:21]
_T_13.aw.bits.id <= io.dma_axi.aw.bits.id @[quasar.scala 271:21]
_T_13.aw.valid <= io.dma_axi.aw.valid @[quasar.scala 271:21]
io.dma_axi.aw.ready <= _T_13.aw.ready @[quasar.scala 271:21]
wire _T_14 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}} @[quasar.scala 272:36]
_T_14.r.bits.last <= UInt<1>("h00") @[quasar.scala 272:36]
_T_14.r.bits.resp <= UInt<2>("h00") @[quasar.scala 272:36]
_T_14.r.bits.data <= UInt<64>("h00") @[quasar.scala 272:36]
_T_14.r.bits.id <= UInt<1>("h00") @[quasar.scala 272:36]
_T_14.r.valid <= UInt<1>("h00") @[quasar.scala 272:36]
_T_14.r.ready <= UInt<1>("h00") @[quasar.scala 272:36]
_T_14.ar.bits.qos <= UInt<4>("h00") @[quasar.scala 272:36]
_T_14.ar.bits.prot <= UInt<3>("h00") @[quasar.scala 272:36]
_T_14.ar.bits.cache <= UInt<4>("h00") @[quasar.scala 272:36]
_T_14.ar.bits.lock <= UInt<1>("h00") @[quasar.scala 272:36]
_T_14.ar.bits.burst <= UInt<2>("h00") @[quasar.scala 272:36]
_T_14.ar.bits.size <= UInt<3>("h00") @[quasar.scala 272:36]
_T_14.ar.bits.len <= UInt<8>("h00") @[quasar.scala 272:36]
_T_14.ar.bits.region <= UInt<4>("h00") @[quasar.scala 272:36]
_T_14.ar.bits.addr <= UInt<32>("h00") @[quasar.scala 272:36]
_T_14.ar.bits.id <= UInt<1>("h00") @[quasar.scala 272:36]
_T_14.ar.valid <= UInt<1>("h00") @[quasar.scala 272:36]
_T_14.ar.ready <= UInt<1>("h00") @[quasar.scala 272:36]
_T_14.b.bits.id <= UInt<1>("h00") @[quasar.scala 272:36]
_T_14.b.bits.resp <= UInt<2>("h00") @[quasar.scala 272:36]
_T_14.b.valid <= UInt<1>("h00") @[quasar.scala 272:36]
_T_14.b.ready <= UInt<1>("h00") @[quasar.scala 272:36]
_T_14.w.bits.last <= UInt<1>("h00") @[quasar.scala 272:36]
_T_14.w.bits.strb <= UInt<8>("h00") @[quasar.scala 272:36]
_T_14.w.bits.data <= UInt<64>("h00") @[quasar.scala 272:36]
_T_14.w.valid <= UInt<1>("h00") @[quasar.scala 272:36]
_T_14.w.ready <= UInt<1>("h00") @[quasar.scala 272:36]
_T_14.aw.bits.qos <= UInt<4>("h00") @[quasar.scala 272:36]
_T_14.aw.bits.prot <= UInt<3>("h00") @[quasar.scala 272:36]
_T_14.aw.bits.cache <= UInt<4>("h00") @[quasar.scala 272:36]
_T_14.aw.bits.lock <= UInt<1>("h00") @[quasar.scala 272:36]
_T_14.aw.bits.burst <= UInt<2>("h00") @[quasar.scala 272:36]
_T_14.aw.bits.size <= UInt<3>("h00") @[quasar.scala 272:36]
_T_14.aw.bits.len <= UInt<8>("h00") @[quasar.scala 272:36]
_T_14.aw.bits.region <= UInt<4>("h00") @[quasar.scala 272:36]
_T_14.aw.bits.addr <= UInt<32>("h00") @[quasar.scala 272:36]
_T_14.aw.bits.id <= UInt<1>("h00") @[quasar.scala 272:36]
_T_14.aw.valid <= UInt<1>("h00") @[quasar.scala 272:36]
_T_14.aw.ready <= UInt<1>("h00") @[quasar.scala 272:36]
_T_14.r.bits.last <= io.sb_axi.r.bits.last @[quasar.scala 272:21]
_T_14.r.bits.resp <= io.sb_axi.r.bits.resp @[quasar.scala 272:21]
_T_14.r.bits.data <= io.sb_axi.r.bits.data @[quasar.scala 272:21]
_T_14.r.bits.id <= io.sb_axi.r.bits.id @[quasar.scala 272:21]
_T_14.r.valid <= io.sb_axi.r.valid @[quasar.scala 272:21]
io.sb_axi.r.ready <= _T_14.r.ready @[quasar.scala 272:21]
io.sb_axi.ar.bits.qos <= _T_14.ar.bits.qos @[quasar.scala 272:21]
io.sb_axi.ar.bits.prot <= _T_14.ar.bits.prot @[quasar.scala 272:21]
io.sb_axi.ar.bits.cache <= _T_14.ar.bits.cache @[quasar.scala 272:21]
io.sb_axi.ar.bits.lock <= _T_14.ar.bits.lock @[quasar.scala 272:21]
io.sb_axi.ar.bits.burst <= _T_14.ar.bits.burst @[quasar.scala 272:21]
io.sb_axi.ar.bits.size <= _T_14.ar.bits.size @[quasar.scala 272:21]
io.sb_axi.ar.bits.len <= _T_14.ar.bits.len @[quasar.scala 272:21]
io.sb_axi.ar.bits.region <= _T_14.ar.bits.region @[quasar.scala 272:21]
io.sb_axi.ar.bits.addr <= _T_14.ar.bits.addr @[quasar.scala 272:21]
io.sb_axi.ar.bits.id <= _T_14.ar.bits.id @[quasar.scala 272:21]
io.sb_axi.ar.valid <= _T_14.ar.valid @[quasar.scala 272:21]
_T_14.ar.ready <= io.sb_axi.ar.ready @[quasar.scala 272:21]
_T_14.b.bits.id <= io.sb_axi.b.bits.id @[quasar.scala 272:21]
_T_14.b.bits.resp <= io.sb_axi.b.bits.resp @[quasar.scala 272:21]
_T_14.b.valid <= io.sb_axi.b.valid @[quasar.scala 272:21]
io.sb_axi.b.ready <= _T_14.b.ready @[quasar.scala 272:21]
io.sb_axi.w.bits.last <= _T_14.w.bits.last @[quasar.scala 272:21]
io.sb_axi.w.bits.strb <= _T_14.w.bits.strb @[quasar.scala 272:21]
io.sb_axi.w.bits.data <= _T_14.w.bits.data @[quasar.scala 272:21]
io.sb_axi.w.valid <= _T_14.w.valid @[quasar.scala 272:21]
_T_14.w.ready <= io.sb_axi.w.ready @[quasar.scala 272:21]
io.sb_axi.aw.bits.qos <= _T_14.aw.bits.qos @[quasar.scala 272:21]
io.sb_axi.aw.bits.prot <= _T_14.aw.bits.prot @[quasar.scala 272:21]
io.sb_axi.aw.bits.cache <= _T_14.aw.bits.cache @[quasar.scala 272:21]
io.sb_axi.aw.bits.lock <= _T_14.aw.bits.lock @[quasar.scala 272:21]
io.sb_axi.aw.bits.burst <= _T_14.aw.bits.burst @[quasar.scala 272:21]
io.sb_axi.aw.bits.size <= _T_14.aw.bits.size @[quasar.scala 272:21]
io.sb_axi.aw.bits.len <= _T_14.aw.bits.len @[quasar.scala 272:21]
io.sb_axi.aw.bits.region <= _T_14.aw.bits.region @[quasar.scala 272:21]
io.sb_axi.aw.bits.addr <= _T_14.aw.bits.addr @[quasar.scala 272:21]
io.sb_axi.aw.bits.id <= _T_14.aw.bits.id @[quasar.scala 272:21]
io.sb_axi.aw.valid <= _T_14.aw.valid @[quasar.scala 272:21]
_T_14.aw.ready <= io.sb_axi.aw.ready @[quasar.scala 272:21]
wire _T_15 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}} @[quasar.scala 273:36]
_T_15.r.bits.last <= UInt<1>("h00") @[quasar.scala 273:36]
_T_15.r.bits.resp <= UInt<2>("h00") @[quasar.scala 273:36]
_T_15.r.bits.data <= UInt<64>("h00") @[quasar.scala 273:36]
_T_15.r.bits.id <= UInt<3>("h00") @[quasar.scala 273:36]
_T_15.r.valid <= UInt<1>("h00") @[quasar.scala 273:36]
_T_15.r.ready <= UInt<1>("h00") @[quasar.scala 273:36]
_T_15.ar.bits.qos <= UInt<4>("h00") @[quasar.scala 273:36]
_T_15.ar.bits.prot <= UInt<3>("h00") @[quasar.scala 273:36]
_T_15.ar.bits.cache <= UInt<4>("h00") @[quasar.scala 273:36]
_T_15.ar.bits.lock <= UInt<1>("h00") @[quasar.scala 273:36]
_T_15.ar.bits.burst <= UInt<2>("h00") @[quasar.scala 273:36]
_T_15.ar.bits.size <= UInt<3>("h00") @[quasar.scala 273:36]
_T_15.ar.bits.len <= UInt<8>("h00") @[quasar.scala 273:36]
_T_15.ar.bits.region <= UInt<4>("h00") @[quasar.scala 273:36]
_T_15.ar.bits.addr <= UInt<32>("h00") @[quasar.scala 273:36]
_T_15.ar.bits.id <= UInt<3>("h00") @[quasar.scala 273:36]
_T_15.ar.valid <= UInt<1>("h00") @[quasar.scala 273:36]
_T_15.ar.ready <= UInt<1>("h00") @[quasar.scala 273:36]
_T_15.b.bits.id <= UInt<3>("h00") @[quasar.scala 273:36]
_T_15.b.bits.resp <= UInt<2>("h00") @[quasar.scala 273:36]
_T_15.b.valid <= UInt<1>("h00") @[quasar.scala 273:36]
_T_15.b.ready <= UInt<1>("h00") @[quasar.scala 273:36]
_T_15.w.bits.last <= UInt<1>("h00") @[quasar.scala 273:36]
_T_15.w.bits.strb <= UInt<8>("h00") @[quasar.scala 273:36]
_T_15.w.bits.data <= UInt<64>("h00") @[quasar.scala 273:36]
_T_15.w.valid <= UInt<1>("h00") @[quasar.scala 273:36]
_T_15.w.ready <= UInt<1>("h00") @[quasar.scala 273:36]
_T_15.aw.bits.qos <= UInt<4>("h00") @[quasar.scala 273:36]
_T_15.aw.bits.prot <= UInt<3>("h00") @[quasar.scala 273:36]
_T_15.aw.bits.cache <= UInt<4>("h00") @[quasar.scala 273:36]
_T_15.aw.bits.lock <= UInt<1>("h00") @[quasar.scala 273:36]
_T_15.aw.bits.burst <= UInt<2>("h00") @[quasar.scala 273:36]
_T_15.aw.bits.size <= UInt<3>("h00") @[quasar.scala 273:36]
_T_15.aw.bits.len <= UInt<8>("h00") @[quasar.scala 273:36]
_T_15.aw.bits.region <= UInt<4>("h00") @[quasar.scala 273:36]
_T_15.aw.bits.addr <= UInt<32>("h00") @[quasar.scala 273:36]
_T_15.aw.bits.id <= UInt<3>("h00") @[quasar.scala 273:36]
_T_15.aw.valid <= UInt<1>("h00") @[quasar.scala 273:36]
_T_15.aw.ready <= UInt<1>("h00") @[quasar.scala 273:36]
_T_15.r.bits.last <= io.ifu_axi.r.bits.last @[quasar.scala 273:21]
_T_15.r.bits.resp <= io.ifu_axi.r.bits.resp @[quasar.scala 273:21]
_T_15.r.bits.data <= io.ifu_axi.r.bits.data @[quasar.scala 273:21]
_T_15.r.bits.id <= io.ifu_axi.r.bits.id @[quasar.scala 273:21]
_T_15.r.valid <= io.ifu_axi.r.valid @[quasar.scala 273:21]
io.ifu_axi.r.ready <= _T_15.r.ready @[quasar.scala 273:21]
io.ifu_axi.ar.bits.qos <= _T_15.ar.bits.qos @[quasar.scala 273:21]
io.ifu_axi.ar.bits.prot <= _T_15.ar.bits.prot @[quasar.scala 273:21]
io.ifu_axi.ar.bits.cache <= _T_15.ar.bits.cache @[quasar.scala 273:21]
io.ifu_axi.ar.bits.lock <= _T_15.ar.bits.lock @[quasar.scala 273:21]
io.ifu_axi.ar.bits.burst <= _T_15.ar.bits.burst @[quasar.scala 273:21]
io.ifu_axi.ar.bits.size <= _T_15.ar.bits.size @[quasar.scala 273:21]
io.ifu_axi.ar.bits.len <= _T_15.ar.bits.len @[quasar.scala 273:21]
io.ifu_axi.ar.bits.region <= _T_15.ar.bits.region @[quasar.scala 273:21]
io.ifu_axi.ar.bits.addr <= _T_15.ar.bits.addr @[quasar.scala 273:21]
io.ifu_axi.ar.bits.id <= _T_15.ar.bits.id @[quasar.scala 273:21]
io.ifu_axi.ar.valid <= _T_15.ar.valid @[quasar.scala 273:21]
_T_15.ar.ready <= io.ifu_axi.ar.ready @[quasar.scala 273:21]
_T_15.b.bits.id <= io.ifu_axi.b.bits.id @[quasar.scala 273:21]
_T_15.b.bits.resp <= io.ifu_axi.b.bits.resp @[quasar.scala 273:21]
_T_15.b.valid <= io.ifu_axi.b.valid @[quasar.scala 273:21]
io.ifu_axi.b.ready <= _T_15.b.ready @[quasar.scala 273:21]
io.ifu_axi.w.bits.last <= _T_15.w.bits.last @[quasar.scala 273:21]
io.ifu_axi.w.bits.strb <= _T_15.w.bits.strb @[quasar.scala 273:21]
io.ifu_axi.w.bits.data <= _T_15.w.bits.data @[quasar.scala 273:21]
io.ifu_axi.w.valid <= _T_15.w.valid @[quasar.scala 273:21]
_T_15.w.ready <= io.ifu_axi.w.ready @[quasar.scala 273:21]
io.ifu_axi.aw.bits.qos <= _T_15.aw.bits.qos @[quasar.scala 273:21]
io.ifu_axi.aw.bits.prot <= _T_15.aw.bits.prot @[quasar.scala 273:21]
io.ifu_axi.aw.bits.cache <= _T_15.aw.bits.cache @[quasar.scala 273:21]
io.ifu_axi.aw.bits.lock <= _T_15.aw.bits.lock @[quasar.scala 273:21]
io.ifu_axi.aw.bits.burst <= _T_15.aw.bits.burst @[quasar.scala 273:21]
io.ifu_axi.aw.bits.size <= _T_15.aw.bits.size @[quasar.scala 273:21]
io.ifu_axi.aw.bits.len <= _T_15.aw.bits.len @[quasar.scala 273:21]
io.ifu_axi.aw.bits.region <= _T_15.aw.bits.region @[quasar.scala 273:21]
io.ifu_axi.aw.bits.addr <= _T_15.aw.bits.addr @[quasar.scala 273:21]
io.ifu_axi.aw.bits.id <= _T_15.aw.bits.id @[quasar.scala 273:21]
io.ifu_axi.aw.valid <= _T_15.aw.valid @[quasar.scala 273:21]
_T_15.aw.ready <= io.ifu_axi.aw.ready @[quasar.scala 273:21]
wire _T_16 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}} @[quasar.scala 274:36]
_T_16.r.bits.last <= UInt<1>("h00") @[quasar.scala 274:36]
_T_16.r.bits.resp <= UInt<2>("h00") @[quasar.scala 274:36]
_T_16.r.bits.data <= UInt<64>("h00") @[quasar.scala 274:36]
_T_16.r.bits.id <= UInt<3>("h00") @[quasar.scala 274:36]
_T_16.r.valid <= UInt<1>("h00") @[quasar.scala 274:36]
_T_16.r.ready <= UInt<1>("h00") @[quasar.scala 274:36]
_T_16.ar.bits.qos <= UInt<4>("h00") @[quasar.scala 274:36]
_T_16.ar.bits.prot <= UInt<3>("h00") @[quasar.scala 274:36]
_T_16.ar.bits.cache <= UInt<4>("h00") @[quasar.scala 274:36]
_T_16.ar.bits.lock <= UInt<1>("h00") @[quasar.scala 274:36]
_T_16.ar.bits.burst <= UInt<2>("h00") @[quasar.scala 274:36]
_T_16.ar.bits.size <= UInt<3>("h00") @[quasar.scala 274:36]
_T_16.ar.bits.len <= UInt<8>("h00") @[quasar.scala 274:36]
_T_16.ar.bits.region <= UInt<4>("h00") @[quasar.scala 274:36]
_T_16.ar.bits.addr <= UInt<32>("h00") @[quasar.scala 274:36]
_T_16.ar.bits.id <= UInt<3>("h00") @[quasar.scala 274:36]
_T_16.ar.valid <= UInt<1>("h00") @[quasar.scala 274:36]
_T_16.ar.ready <= UInt<1>("h00") @[quasar.scala 274:36]
_T_16.b.bits.id <= UInt<3>("h00") @[quasar.scala 274:36]
_T_16.b.bits.resp <= UInt<2>("h00") @[quasar.scala 274:36]
_T_16.b.valid <= UInt<1>("h00") @[quasar.scala 274:36]
_T_16.b.ready <= UInt<1>("h00") @[quasar.scala 274:36]
_T_16.w.bits.last <= UInt<1>("h00") @[quasar.scala 274:36]
_T_16.w.bits.strb <= UInt<8>("h00") @[quasar.scala 274:36]
_T_16.w.bits.data <= UInt<64>("h00") @[quasar.scala 274:36]
_T_16.w.valid <= UInt<1>("h00") @[quasar.scala 274:36]
_T_16.w.ready <= UInt<1>("h00") @[quasar.scala 274:36]
_T_16.aw.bits.qos <= UInt<4>("h00") @[quasar.scala 274:36]
_T_16.aw.bits.prot <= UInt<3>("h00") @[quasar.scala 274:36]
_T_16.aw.bits.cache <= UInt<4>("h00") @[quasar.scala 274:36]
_T_16.aw.bits.lock <= UInt<1>("h00") @[quasar.scala 274:36]
_T_16.aw.bits.burst <= UInt<2>("h00") @[quasar.scala 274:36]
_T_16.aw.bits.size <= UInt<3>("h00") @[quasar.scala 274:36]
_T_16.aw.bits.len <= UInt<8>("h00") @[quasar.scala 274:36]
_T_16.aw.bits.region <= UInt<4>("h00") @[quasar.scala 274:36]
_T_16.aw.bits.addr <= UInt<32>("h00") @[quasar.scala 274:36]
_T_16.aw.bits.id <= UInt<3>("h00") @[quasar.scala 274:36]
_T_16.aw.valid <= UInt<1>("h00") @[quasar.scala 274:36]
_T_16.aw.ready <= UInt<1>("h00") @[quasar.scala 274:36]
_T_16.r.bits.last <= io.lsu_axi.r.bits.last @[quasar.scala 274:21]
_T_16.r.bits.resp <= io.lsu_axi.r.bits.resp @[quasar.scala 274:21]
_T_16.r.bits.data <= io.lsu_axi.r.bits.data @[quasar.scala 274:21]
_T_16.r.bits.id <= io.lsu_axi.r.bits.id @[quasar.scala 274:21]
_T_16.r.valid <= io.lsu_axi.r.valid @[quasar.scala 274:21]
io.lsu_axi.r.ready <= _T_16.r.ready @[quasar.scala 274:21]
io.lsu_axi.ar.bits.qos <= _T_16.ar.bits.qos @[quasar.scala 274:21]
io.lsu_axi.ar.bits.prot <= _T_16.ar.bits.prot @[quasar.scala 274:21]
io.lsu_axi.ar.bits.cache <= _T_16.ar.bits.cache @[quasar.scala 274:21]
io.lsu_axi.ar.bits.lock <= _T_16.ar.bits.lock @[quasar.scala 274:21]
io.lsu_axi.ar.bits.burst <= _T_16.ar.bits.burst @[quasar.scala 274:21]
io.lsu_axi.ar.bits.size <= _T_16.ar.bits.size @[quasar.scala 274:21]
io.lsu_axi.ar.bits.len <= _T_16.ar.bits.len @[quasar.scala 274:21]
io.lsu_axi.ar.bits.region <= _T_16.ar.bits.region @[quasar.scala 274:21]
io.lsu_axi.ar.bits.addr <= _T_16.ar.bits.addr @[quasar.scala 274:21]
io.lsu_axi.ar.bits.id <= _T_16.ar.bits.id @[quasar.scala 274:21]
io.lsu_axi.ar.valid <= _T_16.ar.valid @[quasar.scala 274:21]
_T_16.ar.ready <= io.lsu_axi.ar.ready @[quasar.scala 274:21]
_T_16.b.bits.id <= io.lsu_axi.b.bits.id @[quasar.scala 274:21]
_T_16.b.bits.resp <= io.lsu_axi.b.bits.resp @[quasar.scala 274:21]
_T_16.b.valid <= io.lsu_axi.b.valid @[quasar.scala 274:21]
io.lsu_axi.b.ready <= _T_16.b.ready @[quasar.scala 274:21]
io.lsu_axi.w.bits.last <= _T_16.w.bits.last @[quasar.scala 274:21]
io.lsu_axi.w.bits.strb <= _T_16.w.bits.strb @[quasar.scala 274:21]
io.lsu_axi.w.bits.data <= _T_16.w.bits.data @[quasar.scala 274:21]
io.lsu_axi.w.valid <= _T_16.w.valid @[quasar.scala 274:21]
_T_16.w.ready <= io.lsu_axi.w.ready @[quasar.scala 274:21]
io.lsu_axi.aw.bits.qos <= _T_16.aw.bits.qos @[quasar.scala 274:21]
io.lsu_axi.aw.bits.prot <= _T_16.aw.bits.prot @[quasar.scala 274:21]
io.lsu_axi.aw.bits.cache <= _T_16.aw.bits.cache @[quasar.scala 274:21]
io.lsu_axi.aw.bits.lock <= _T_16.aw.bits.lock @[quasar.scala 274:21]
io.lsu_axi.aw.bits.burst <= _T_16.aw.bits.burst @[quasar.scala 274:21]
io.lsu_axi.aw.bits.size <= _T_16.aw.bits.size @[quasar.scala 274:21]
io.lsu_axi.aw.bits.len <= _T_16.aw.bits.len @[quasar.scala 274:21]
io.lsu_axi.aw.bits.region <= _T_16.aw.bits.region @[quasar.scala 274:21]
io.lsu_axi.aw.bits.addr <= _T_16.aw.bits.addr @[quasar.scala 274:21]
io.lsu_axi.aw.bits.id <= _T_16.aw.bits.id @[quasar.scala 274:21]
io.lsu_axi.aw.valid <= _T_16.aw.valid @[quasar.scala 274:21]
_T_16.aw.ready <= io.lsu_axi.aw.ready @[quasar.scala 274:21]
module quasar_wrapper :
input clock : Clock

2
quasar_wrapper.v
View File

@ -85258,7 +85258,7 @@ module quasar(
assign pic_ctrl_inst_io_free_clk = rvclkhdr_io_l1clk; // @[quasar.scala 211:29]
assign pic_ctrl_inst_io_active_clk = rvclkhdr_1_io_l1clk; // @[quasar.scala 212:31]
assign pic_ctrl_inst_io_clk_override = dec_io_dec_tlu_pic_clk_override; // @[quasar.scala 213:33]
assign pic_ctrl_inst_io_extintsrc_req = {{1'd0}, io_extintsrc_req}; // @[quasar.scala 214:34]
assign pic_ctrl_inst_io_extintsrc_req = {io_extintsrc_req,1'h0}; // @[quasar.scala 214:34]
assign pic_ctrl_inst_io_lsu_pic_picm_wren = lsu_io_lsu_pic_picm_wren; // @[quasar.scala 215:28]
assign pic_ctrl_inst_io_lsu_pic_picm_rden = lsu_io_lsu_pic_picm_rden; // @[quasar.scala 215:28]
assign pic_ctrl_inst_io_lsu_pic_picm_mken = lsu_io_lsu_pic_picm_mken; // @[quasar.scala 215:28]

5
src/main/scala/quasar.scala
View File

@ -211,7 +211,7 @@ class quasar extends Module with RequireAsyncReset with lib {
pic_ctrl_inst.io.free_clk := free_clk
pic_ctrl_inst.io.active_clk := active_clk
pic_ctrl_inst.io.clk_override := dec.io.dec_tlu_pic_clk_override
pic_ctrl_inst.io.extintsrc_req := io.extintsrc_req
pic_ctrl_inst.io.extintsrc_req := Cat(io.extintsrc_req,0.U)
pic_ctrl_inst.io.lsu_pic <> lsu.io.lsu_pic
pic_ctrl_inst.io.dec_pic <> dec.io.dec_pic
// Trace Packet
@ -285,3 +285,6 @@ class quasar extends Module with RequireAsyncReset with lib {
}
}
//object QUASAR extends App {
// println((new chisel3.stage.ChiselStage).emitVerilog(new quasar()))
//}

BIN
target/scala-2.12/classes/quasar.class
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