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DMA Inserted

This commit is contained in:
​Laraib Khan 2020-12-16 16:48:55 +05:00
parent 168d355e26
commit 09739661c2
10 changed files with 9560 additions and 9341 deletions
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2
firrtl_black_box_resource_files.f
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@ -1 +1,3 @@
/home/laraibkhan/Desktop/SweRV-Chislified/gated_latch.v /home/laraibkhan/Desktop/SweRV-Chislified/gated_latch.v
/home/laraibkhan/Desktop/SweRV-Chislified/dmi_wrapper.sv
/home/laraibkhan/Desktop/SweRV-Chislified/mem.sv

8
quasar_wrapper.anno.json
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@ -968,6 +968,14 @@
"class":"firrtl.transforms.DontTouchAnnotation", "class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|exu>i0_rs2_d" "target":"~quasar_wrapper|exu>i0_rs2_d"
}, },
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|dbg>rst_temp"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|dbg>dbg_dm_rst_l"
},
{ {
"class":"firrtl.transforms.DontTouchAnnotation", "class":"firrtl.transforms.DontTouchAnnotation",
"target":"~quasar_wrapper|dec_trigger>io_dec_i0_trigger_match_d" "target":"~quasar_wrapper|dec_trigger>io_dec_i0_trigger_match_d"

13085
quasar_wrapper.fir
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File diff suppressed because it is too large Load Diff

5698
quasar_wrapper.v
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File diff suppressed because it is too large Load Diff

104
src/main/scala/dbg/dbg.scala
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@ -96,41 +96,46 @@ class dbg extends Module with lib with RequireAsyncReset {
val sb_free_clken = io.dmi_reg_en | sb_state_en | (sb_state =/= sb_state_t.sbidle) | io.clk_override; val sb_free_clken = io.dmi_reg_en | sb_state_en | (sb_state =/= sb_state_t.sbidle) | io.clk_override;
val dbg_free_clk = rvclkhdr(clock, dbg_free_clken, io.scan_mode) // dbg_free_cgc val dbg_free_clk = rvclkhdr(clock, dbg_free_clken, io.scan_mode) // dbg_free_cgc
val sb_free_clk = rvclkhdr(clock, sb_free_clken, io.scan_mode) // sb_free_cgc val sb_free_clk = rvclkhdr(clock, sb_free_clken, io.scan_mode) // sb_free_cgc
val dbg_dm_rst_l = io.dbg_rst_l.asBool() & (dmcontrol_reg(0) | io.scan_mode)
val dbg_dm_rst_l = (io.dbg_rst_l.asBool() & (dmcontrol_reg(0) | io.scan_mode)).asAsyncReset()
dontTouch(dbg_dm_rst_l)
val rst_temp = (dbg_dm_rst_l.asBool() & reset.asBool()).asAsyncReset()
dontTouch(rst_temp)
io.dbg_core_rst_l := (!dmcontrol_reg(1)).asBool() io.dbg_core_rst_l := (!dmcontrol_reg(1)).asBool()
val sbcs_wren = (io.dmi_reg_addr === "h38".U) & io.dmi_reg_en & io.dmi_reg_wr_en & (sb_state === sb_state_t.sbidle) val sbcs_wren = (io.dmi_reg_addr === "h38".U) & io.dmi_reg_en & io.dmi_reg_wr_en & (sb_state === sb_state_t.sbidle)
val sbcs_sbbusyerror_wren = (sbcs_wren & io.dmi_reg_wdata(22)) | ((sb_state =/= sb_state_t.sbidle) & io.dmi_reg_en & val sbcs_sbbusyerror_wren = (sbcs_wren & io.dmi_reg_wdata(22)) | ((sb_state =/= sb_state_t.sbidle) & io.dmi_reg_en &
((io.dmi_reg_addr === "h39".U) | (io.dmi_reg_addr === "h3c".U) | (io.dmi_reg_addr === "h3d".U))) ((io.dmi_reg_addr === "h39".U) | (io.dmi_reg_addr === "h3c".U) | (io.dmi_reg_addr === "h3d".U)))
val sbcs_sbbusyerror_din = (~(sbcs_wren & io.dmi_reg_wdata(22))).asUInt() val sbcs_sbbusyerror_din = (~(sbcs_wren & io.dmi_reg_wdata(22))).asUInt()
val temp_sbcs_22 = withClockAndReset(sb_free_clk, !dbg_dm_rst_l) { val temp_sbcs_22 = withClockAndReset(sb_free_clk, dbg_dm_rst_l) {
RegEnable(sbcs_sbbusyerror_din, 0.U, sbcs_sbbusyerror_wren) RegEnable(sbcs_sbbusyerror_din, 0.U, sbcs_sbbusyerror_wren)
} // sbcs_sbbusyerror_reg } // sbcs_sbbusyerror_reg
val temp_sbcs_21 = withClockAndReset(sb_free_clk, !dbg_dm_rst_l) { val temp_sbcs_21 = withClockAndReset(sb_free_clk, dbg_dm_rst_l) {
RegEnable(sbcs_sbbusy_din, 0.U, sbcs_sbbusy_wren) RegEnable(sbcs_sbbusy_din, 0.U, sbcs_sbbusy_wren)
} // sbcs_sbbusy_reg } // sbcs_sbbusy_reg
val temp_sbcs_20 = withClockAndReset(sb_free_clk, !dbg_dm_rst_l) { val temp_sbcs_20 = withClockAndReset(sb_free_clk, dbg_dm_rst_l) {
RegEnable(io.dmi_reg_wdata(20), 0.U, sbcs_wren) RegEnable(io.dmi_reg_wdata(20), 0.U, sbcs_wren)
} // sbcs_sbreadonaddr_reg } // sbcs_sbreadonaddr_reg
val temp_sbcs_19_15 = withClockAndReset(sb_free_clk, !dbg_dm_rst_l) { val temp_sbcs_19_15 = withClockAndReset(sb_free_clk, dbg_dm_rst_l) {
RegEnable(io.dmi_reg_wdata(19, 15), 0.U, sbcs_wren) RegEnable(io.dmi_reg_wdata(19, 15), 0.U, sbcs_wren)
} // sbcs_misc_reg } // sbcs_misc_reg
val temp_sbcs_14_12 = withClockAndReset(sb_free_clk, !dbg_dm_rst_l) { val temp_sbcs_14_12 = withClockAndReset(sb_free_clk, dbg_dm_rst_l) {
RegEnable(sbcs_sberror_din(2, 0), 0.U, sbcs_sberror_wren) RegEnable(sbcs_sberror_din(2, 0), 0.U, sbcs_sberror_wren)
} // sbcs_error_reg } // sbcs_error_reg
sbcs_reg := Cat(1.U(3.W), 0.U(6.W), temp_sbcs_22, temp_sbcs_21, temp_sbcs_20, temp_sbcs_19_15, temp_sbcs_14_12, "h20".U(7.W), "b01111".U(5.W)) sbcs_reg := Cat(1.U(3.W), 0.U(6.W), temp_sbcs_22, temp_sbcs_21, temp_sbcs_20, temp_sbcs_19_15, temp_sbcs_14_12, "h20".U(7.W), "b01111".U(5.W))
val sbcs_unaligned = (sbcs_reg(19, 17) === "b001".U) & sbaddress0_reg(0) | val sbcs_unaligned = (sbcs_reg(19, 17) === "b001".U(3.W)) & sbaddress0_reg(0) |
(sbcs_reg(19, 17) === "b010".U) & sbaddress0_reg(1, 0).orR | (sbcs_reg(19, 17) === "b010".U(3.W)) & sbaddress0_reg(1, 0).orR |
(sbcs_reg(19, 17) === "b011".U) & sbaddress0_reg(2, 0).orR (sbcs_reg(19, 17) === "b011".U(3.W)) & sbaddress0_reg(2, 0).orR
val sbcs_illegal_size = sbcs_reg(19) val sbcs_illegal_size = sbcs_reg(19)
val sbaddress0_incr = Fill(4, (sbcs_reg(19, 17) === "h0".U)) & "b0001".U | Fill(4, (sbcs_reg(19, 17) === "h1".U)) & "b0010".U | val sbaddress0_incr = Fill(4, (sbcs_reg(19, 17) === "h0".U)) & "b0001".U(4.W) | Fill(4, (sbcs_reg(19, 17) === "h1".U)) & "b0010".U(4.W) |
Fill(4, (sbcs_reg(19, 17) === "h2".U)) & "b0100".U | Fill(4, (sbcs_reg(19, 17) === "h3".U)) & "b1000".U Fill(4, (sbcs_reg(19, 17) === "h2".U)) & "b0100".U(4.W) | Fill(4, (sbcs_reg(19, 17) === "h3".U)) & "b1000".U(4.W)
val sbdata0_reg_wren0 = io.dmi_reg_en & io.dmi_reg_wr_en & (io.dmi_reg_addr === "h3c".U) val sbdata0_reg_wren0 = io.dmi_reg_en & io.dmi_reg_wr_en & (io.dmi_reg_addr === "h3c".U)
val sbdata0_reg_wren1 = (sb_state === sb_state_t.rsp_rd) & sb_state_en & !sbcs_sberror_wren val sbdata0_reg_wren1 = (sb_state === sb_state_t.rsp_rd) & sb_state_en & !sbcs_sberror_wren
@ -144,11 +149,11 @@ class dbg extends Module with lib with RequireAsyncReset {
val sbdata1_din = Fill(32, sbdata1_reg_wren0) & io.dmi_reg_wdata | val sbdata1_din = Fill(32, sbdata1_reg_wren0) & io.dmi_reg_wdata |
Fill(32, sbdata1_reg_wren1) & sb_bus_rdata(63, 32) Fill(32, sbdata1_reg_wren1) & sb_bus_rdata(63, 32)
val sbdata0_reg = withReset(!dbg_dm_rst_l) { val sbdata0_reg = withReset(dbg_dm_rst_l) {
rvdffe(sbdata0_din, sbdata0_reg_wren, clock, io.scan_mode) rvdffe(sbdata0_din, sbdata0_reg_wren, clock, io.scan_mode)
} // dbg_sbdata0_reg } // dbg_sbdata0_reg
val sbdata1_reg = withReset(!dbg_dm_rst_l) { val sbdata1_reg = withReset(dbg_dm_rst_l) {
rvdffe(sbdata1_din, sbdata1_reg_wren, clock, io.scan_mode) rvdffe(sbdata1_din, sbdata1_reg_wren, clock, io.scan_mode)
} // dbg_sbdata1_reg } // dbg_sbdata1_reg
@ -156,7 +161,7 @@ class dbg extends Module with lib with RequireAsyncReset {
val sbaddress0_reg_wren = sbaddress0_reg_wren0 | sbaddress0_reg_wren1 val sbaddress0_reg_wren = sbaddress0_reg_wren0 | sbaddress0_reg_wren1
val sbaddress0_reg_din = Fill(32, sbaddress0_reg_wren0) & io.dmi_reg_wdata | val sbaddress0_reg_din = Fill(32, sbaddress0_reg_wren0) & io.dmi_reg_wdata |
Fill(32, sbaddress0_reg_wren1) & (sbaddress0_reg + Cat(0.U(28.W), sbaddress0_incr)) Fill(32, sbaddress0_reg_wren1) & (sbaddress0_reg + Cat(0.U(28.W), sbaddress0_incr))
sbaddress0_reg := withReset(!dbg_dm_rst_l) { sbaddress0_reg := withReset(dbg_dm_rst_l) {
rvdffe(sbaddress0_reg_din, sbaddress0_reg_wren, clock, io.scan_mode) rvdffe(sbaddress0_reg_din, sbaddress0_reg_wren, clock, io.scan_mode)
} // dbg_sbaddress0_reg } // dbg_sbaddress0_reg
@ -164,20 +169,20 @@ class dbg extends Module with lib with RequireAsyncReset {
val sbreadondata_access = io.dmi_reg_en & !io.dmi_reg_wr_en & (io.dmi_reg_addr === "h3c".U) & sbcs_reg(15) val sbreadondata_access = io.dmi_reg_en & !io.dmi_reg_wr_en & (io.dmi_reg_addr === "h3c".U) & sbcs_reg(15)
val sbdata0wr_access = io.dmi_reg_en & io.dmi_reg_wr_en & (io.dmi_reg_addr === "h3c".U) val sbdata0wr_access = io.dmi_reg_en & io.dmi_reg_wr_en & (io.dmi_reg_addr === "h3c".U)
val dmcontrol_wren = (io.dmi_reg_addr === "h10".U) & io.dmi_reg_en & io.dmi_reg_wr_en val dmcontrol_wren = (io.dmi_reg_addr === "h10".U) & io.dmi_reg_en & io.dmi_reg_wr_en
val dm_temp = withClockAndReset(dbg_free_clk, !dbg_dm_rst_l) { val dm_temp = withClockAndReset(dbg_free_clk, dbg_dm_rst_l) {
RegEnable( RegEnable(
Cat(io.dmi_reg_wdata(31, 30), io.dmi_reg_wdata(28), io.dmi_reg_wdata(1)), Cat(io.dmi_reg_wdata(31, 30), io.dmi_reg_wdata(28), io.dmi_reg_wdata(1)),
0.U, dmcontrol_wren) 0.U, dmcontrol_wren)
} // dmcontrolff } // dmcontrolff
val dm_temp_0 = withClockAndReset(dbg_free_clk, io.dbg_rst_l) { val dm_temp_0 = withClockAndReset(dbg_free_clk, io.dbg_rst_l.asAsyncReset()) {
RegEnable(io.dmi_reg_wdata(0), 0.U, dmcontrol_wren) RegEnable(io.dmi_reg_wdata(0), 0.U, dmcontrol_wren)
} // dmcontrol_dmactive_ff } // dmcontrol_dmactive_ff
val temp = Cat(dm_temp(3, 2), 0.U, dm_temp(1), 0.U(26.W), dm_temp(0), dm_temp_0) val temp = Cat(dm_temp(3, 2), 0.U, dm_temp(1), 0.U(26.W), dm_temp(0), dm_temp_0)
dmcontrol_reg := temp dmcontrol_reg := temp
val dmcontrol_wren_Q = withClockAndReset(dbg_free_clk, !dbg_dm_rst_l) { val dmcontrol_wren_Q = withClockAndReset(dbg_free_clk, dbg_dm_rst_l) {
RegNext(dmcontrol_wren, 0.U) RegNext(dmcontrol_wren, 0.U)
} // dmcontrol_wrenff } // dmcontrol_wrenff
@ -190,16 +195,16 @@ class dbg extends Module with lib with RequireAsyncReset {
val temp_rst = reset.asBool() val temp_rst = reset.asBool()
dmstatus_unavail := (dmcontrol_reg(1) | !(temp_rst)).asBool() dmstatus_unavail := (dmcontrol_reg(1) | !(temp_rst)).asBool()
dmstatus_running := ~(dmstatus_unavail | dmstatus_halted) dmstatus_running := ~(dmstatus_unavail | dmstatus_halted)
dmstatus_resumeack := withClockAndReset(dbg_free_clk, !dbg_dm_rst_l) { dmstatus_resumeack := withClockAndReset(dbg_free_clk, dbg_dm_rst_l) {
RegEnable(dmstatus_resumeack_din, 0.U, dmstatus_resumeack_wren) RegEnable(dmstatus_resumeack_din, 0.U, dmstatus_resumeack_wren)
} // dmstatus_resumeack_reg } // dmstatus_resumeack_reg
dmstatus_halted := withClockAndReset(dbg_free_clk, !dbg_dm_rst_l) { dmstatus_halted := withClockAndReset(dbg_free_clk, dbg_dm_rst_l) {
RegNext(io.dec_tlu_dbg_halted & !io.dec_tlu_mpc_halted_only, 0.U) RegNext(io.dec_tlu_dbg_halted & !io.dec_tlu_mpc_halted_only, 0.U)
} // dmstatus_halted_reg } // dmstatus_halted_reg
dmstatus_havereset := withClockAndReset(dbg_free_clk, !dbg_dm_rst_l) { dmstatus_havereset := withClockAndReset(dbg_free_clk, dbg_dm_rst_l) {
RegEnable(~dmstatus_havereset_rst, 0.U, dmstatus_havereset_wren) RegNext(Mux(dmstatus_havereset_wren, true.B, dmstatus_havereset) & !dmstatus_havereset_rst, false.B)
} // dmstatus_havereset_reg } // dmstatus_havereset_reg
val haltsum0_reg = Cat(0.U(31.W), dmstatus_halted) val haltsum0_reg = Cat(0.U(31.W), dmstatus_halted)
@ -210,23 +215,23 @@ class dbg extends Module with lib with RequireAsyncReset {
val abstractcs_error_sel2 = io.core_dbg_cmd_done & io.core_dbg_cmd_fail val abstractcs_error_sel2 = io.core_dbg_cmd_done & io.core_dbg_cmd_fail
val abstractcs_error_sel3 = io.dmi_reg_en & io.dmi_reg_wr_en & (io.dmi_reg_addr === "h17".U) & !dmstatus_reg(9); val abstractcs_error_sel3 = io.dmi_reg_en & io.dmi_reg_wr_en & (io.dmi_reg_addr === "h17".U) & !dmstatus_reg(9);
val abstractcs_error_sel4 = (io.dmi_reg_addr === "h17".U) & io.dmi_reg_en & io.dmi_reg_wr_en & val abstractcs_error_sel4 = (io.dmi_reg_addr === "h17".U) & io.dmi_reg_en & io.dmi_reg_wr_en &
((io.dmi_reg_wdata(22, 20) =/= "b010".U) | ((io.dmi_reg_wdata(31, 24) === "h2".U) && data1_reg(1, 0).orR)) ((io.dmi_reg_wdata(22, 20) =/= "b010".U(3.W)) | ((io.dmi_reg_wdata(31, 24) === "h2".U) && data1_reg(1, 0).orR))
val abstractcs_error_sel5 = (io.dmi_reg_addr === "h16".U) & io.dmi_reg_en & io.dmi_reg_wr_en val abstractcs_error_sel5 = (io.dmi_reg_addr === "h16".U) & io.dmi_reg_en & io.dmi_reg_wr_en
val abstractcs_error_selor = abstractcs_error_sel0 | abstractcs_error_sel1 | abstractcs_error_sel2 | abstractcs_error_sel3 | abstractcs_error_sel4 | abstractcs_error_sel5 val abstractcs_error_selor = abstractcs_error_sel0 | abstractcs_error_sel1 | abstractcs_error_sel2 | abstractcs_error_sel3 | abstractcs_error_sel4 | abstractcs_error_sel5
val abstractcs_error_din = (Fill(3, abstractcs_error_sel0) & "b001".U) | val abstractcs_error_din = (Fill(3, abstractcs_error_sel0) & "b001".U(3.W)) |
(Fill(3, abstractcs_error_sel1) & "b010".U) | (Fill(3, abstractcs_error_sel1) & "b010".U(3.W)) |
(Fill(3, abstractcs_error_sel2) & "b011".U) | (Fill(3, abstractcs_error_sel2) & "b011".U(3.W)) |
(Fill(3, abstractcs_error_sel3) & "b100".U) | (Fill(3, abstractcs_error_sel3) & "b100".U(3.W)) |
(Fill(3, abstractcs_error_sel4) & "b111".U) | (Fill(3, abstractcs_error_sel4) & "b111".U(3.W)) |
(Fill(3, abstractcs_error_sel5) & (~io.dmi_reg_wdata(10, 8)).asUInt() & abstractcs_reg(10, 8)) | (Fill(3, abstractcs_error_sel5) & (~io.dmi_reg_wdata(10, 8)).asUInt() & abstractcs_reg(10, 8)) |
(Fill(3, (~abstractcs_error_selor).asUInt()) & abstractcs_reg(10, 8)) (Fill(3, (~abstractcs_error_selor).asUInt()) & abstractcs_reg(10, 8))
val abs_temp_12 = withClockAndReset(dbg_free_clk, !dbg_dm_rst_l) { val abs_temp_12 = withClockAndReset(dbg_free_clk, dbg_dm_rst_l) {
RegEnable(abstractcs_busy_din, 0.U, abstractcs_busy_wren) RegEnable(abstractcs_busy_din, 0.U, abstractcs_busy_wren)
} // dmabstractcs_busy_reg } // dmabstractcs_busy_reg
val abs_temp_10_8 = withClockAndReset(dbg_free_clk, !dbg_dm_rst_l) { val abs_temp_10_8 = withClockAndReset(dbg_free_clk, dbg_dm_rst_l) {
RegNext(abstractcs_error_din(2, 0), 0.U) RegNext(abstractcs_error_din(2, 0), 0.U)
} // dmabstractcs_error_reg } // dmabstractcs_error_reg
@ -234,8 +239,8 @@ class dbg extends Module with lib with RequireAsyncReset {
val command_wren = (io.dmi_reg_addr === "h17".U) & io.dmi_reg_en & io.dmi_reg_wr_en & (dbg_state === state_t.halted) val command_wren = (io.dmi_reg_addr === "h17".U) & io.dmi_reg_en & io.dmi_reg_wr_en & (dbg_state === state_t.halted)
val command_din = Cat(io.dmi_reg_wdata(31, 24), 0.U(1.W), io.dmi_reg_wdata(22, 20), 0.U(3.W), io.dmi_reg_wdata(16, 0)) val command_din = Cat(io.dmi_reg_wdata(31, 24), 0.U(1.W), io.dmi_reg_wdata(22, 20), 0.U(3.W), io.dmi_reg_wdata(16, 0))
val command_reg = withReset(!dbg_dm_rst_l) { val command_reg = withReset(dbg_dm_rst_l) {
RegEnable(command_din, 0.U, command_wren) rvdffe(command_din, command_wren,clock,io.scan_mode)
} // dmcommand_reg } // dmcommand_reg
val data0_reg_wren0 = io.dmi_reg_en & io.dmi_reg_wr_en & (io.dmi_reg_addr === "h4".U) & (dbg_state === state_t.halted) val data0_reg_wren0 = io.dmi_reg_en & io.dmi_reg_wr_en & (io.dmi_reg_addr === "h4".U) & (dbg_state === state_t.halted)
@ -243,13 +248,13 @@ class dbg extends Module with lib with RequireAsyncReset {
val data0_reg_wren = data0_reg_wren0 | data0_reg_wren1 val data0_reg_wren = data0_reg_wren0 | data0_reg_wren1
val data0_din = Fill(32, data0_reg_wren0) & io.dmi_reg_wdata | Fill(32, data0_reg_wren1) & io.core_dbg_rddata val data0_din = Fill(32, data0_reg_wren0) & io.dmi_reg_wdata | Fill(32, data0_reg_wren1) & io.core_dbg_rddata
val data0_reg = withReset(!dbg_dm_rst_l) { val data0_reg = withReset(dbg_dm_rst_l) {
RegEnable(data0_din, 0.U, data0_reg_wren) rvdffe(data0_din,data0_reg_wren,clock,io.scan_mode)
} // dbg_data0_reg } // dbg_data0_reg
val data1_reg_wren = (io.dmi_reg_en & io.dmi_reg_wr_en & (io.dmi_reg_addr === "h5".U) & (dbg_state === state_t.halted)) val data1_reg_wren = (io.dmi_reg_en & io.dmi_reg_wr_en & (io.dmi_reg_addr === "h5".U) & (dbg_state === state_t.halted))
val data1_din = Fill(32, data1_reg_wren) & io.dmi_reg_wdata val data1_din = Fill(32, data1_reg_wren) & io.dmi_reg_wdata
data1_reg := withReset(!dbg_dm_rst_l) { data1_reg := withReset(dbg_dm_rst_l) {
rvdffe(data1_din, data1_reg_wren, clock, io.scan_mode) rvdffe(data1_din, data1_reg_wren, clock, io.scan_mode)
} // dbg_data1_reg } // dbg_data1_reg
@ -273,7 +278,7 @@ class dbg extends Module with lib with RequireAsyncReset {
} }
is(state_t.halted) { is(state_t.halted) {
dbg_nxtstate := Mux(dmstatus_reg(9) & !dmcontrol_reg(1), dbg_nxtstate := Mux(dmstatus_reg(9) & !dmcontrol_reg(1),
Mux(dmcontrol_reg(30) & !dmcontrol_reg(3), state_t.resuming, state_t.cmd_start), Mux(dmcontrol_reg(30) & !dmcontrol_reg(31), state_t.resuming, state_t.cmd_start),
Mux(dmcontrol_reg(31), state_t.halting, state_t.idle)) Mux(dmcontrol_reg(31), state_t.halting, state_t.idle))
dbg_state_en := dmstatus_reg(9) & dmcontrol_reg(30) & !dmcontrol_reg(31) & dmcontrol_wren_Q | command_wren | dbg_state_en := dmstatus_reg(9) & dmcontrol_reg(30) & !dmcontrol_reg(31) & dmcontrol_wren_Q | command_wren |
dmcontrol_reg(1) | !(dmstatus_reg(9) | io.dec_tlu_mpc_halted_only) dmcontrol_reg(1) | !(dmstatus_reg(9) | io.dec_tlu_mpc_halted_only)
@ -312,20 +317,20 @@ class dbg extends Module with lib with RequireAsyncReset {
Fill(32, io.dmi_reg_addr === "h39".U) & sbaddress0_reg | Fill(32, io.dmi_reg_addr === "h3c".U) & sbdata0_reg | Fill(32, io.dmi_reg_addr === "h39".U) & sbaddress0_reg | Fill(32, io.dmi_reg_addr === "h3c".U) & sbdata0_reg |
Fill(32, io.dmi_reg_addr === "h3d".U) & sbdata1_reg Fill(32, io.dmi_reg_addr === "h3d".U) & sbdata1_reg
dbg_state := withClockAndReset(dbg_free_clk, !dbg_dm_rst_l & temp_rst) { dbg_state := withClockAndReset(dbg_free_clk, rst_temp) {
RegEnable(dbg_nxtstate, 0.U, dbg_state_en) RegEnable(dbg_nxtstate, 0.U, dbg_state_en)
} // dbg_state_reg } // dbg_state_reg
io.dmi_reg_rdata := withClockAndReset(dbg_free_clk, !dbg_dm_rst_l) { io.dmi_reg_rdata := withClockAndReset(dbg_free_clk, dbg_dm_rst_l) {
RegEnable(dmi_reg_rdata_din, 0.U, io.dmi_reg_en) RegEnable(dmi_reg_rdata_din, 0.U, io.dmi_reg_en)
} // dmi_rddata_reg } // dmi_rddata_reg
io.dbg_dec.dbg_ib.dbg_cmd_addr := Mux((command_reg(31, 24) === "h2".U), Cat(data1_reg(31, 2), "b00".U), Cat(0.U(20.W), command_reg(11, 0))) io.dbg_dec.dbg_ib.dbg_cmd_addr := Mux((command_reg(31, 24) === "h2".U), Cat(data1_reg(31, 2), "b00".U(2.W)), Cat(0.U(20.W), command_reg(11, 0)))
io.dbg_dec.dbg_dctl.dbg_cmd_wrdata := data0_reg(31, 0) io.dbg_dec.dbg_dctl.dbg_cmd_wrdata := data0_reg(31, 0)
io.dbg_dec.dbg_ib.dbg_cmd_valid := ((dbg_state === state_t.cmd_start) & !(abstractcs_reg(10, 8).orR) & io.dbg_dma_io.dma_dbg_ready).asBool() io.dbg_dec.dbg_ib.dbg_cmd_valid := ((dbg_state === state_t.cmd_start) & !(abstractcs_reg(10, 8).orR) & io.dbg_dma_io.dma_dbg_ready).asBool()
io.dbg_dec.dbg_ib.dbg_cmd_write := command_reg(16).asBool() io.dbg_dec.dbg_ib.dbg_cmd_write := command_reg(16).asBool()
io.dbg_dec.dbg_ib.dbg_cmd_type := Mux((command_reg(31, 24) === "h2".U), "b10".U, Cat("b0".U, (command_reg(15, 12) === "b0".U))) io.dbg_dec.dbg_ib.dbg_cmd_type := Mux((command_reg(31, 24) === "h2".U), "b10".U(2.W), Cat("b0".U, (command_reg(15, 12) === "b0".U)))
io.dbg_cmd_size := command_reg(21, 20) io.dbg_cmd_size := command_reg(21, 20)
io.dbg_dma_io.dbg_dma_bubble := ((dbg_state === state_t.cmd_start) & !(abstractcs_reg(10, 8).orR) | (dbg_state === state_t.cmd_wait)).asBool() io.dbg_dma_io.dbg_dma_bubble := ((dbg_state === state_t.cmd_start) & !(abstractcs_reg(10, 8).orR) | (dbg_state === state_t.cmd_wait)).asBool()
@ -344,19 +349,19 @@ class dbg extends Module with lib with RequireAsyncReset {
sbcs_sbbusy_wren := sb_state_en sbcs_sbbusy_wren := sb_state_en
sbcs_sbbusy_din := true.B sbcs_sbbusy_din := true.B
sbcs_sberror_wren := sbcs_wren & io.dmi_reg_wdata(14, 12).orR sbcs_sberror_wren := sbcs_wren & io.dmi_reg_wdata(14, 12).orR
sbcs_sberror_din := !io.dmi_reg_wdata(14, 12) & sbcs_reg(14, 12) sbcs_sberror_din := ~io.dmi_reg_wdata(14, 12) & sbcs_reg(14, 12)
} }
is(sb_state_t.wait_rd) { is(sb_state_t.wait_rd) {
sb_nxtstate := Mux(sbcs_unaligned | sbcs_illegal_size, sb_state_t.done, sb_state_t.cmd_rd) sb_nxtstate := Mux(sbcs_unaligned | sbcs_illegal_size, sb_state_t.done, sb_state_t.cmd_rd)
sb_state_en := io.dbg_bus_clk_en | sbcs_unaligned | sbcs_illegal_size sb_state_en := io.dbg_bus_clk_en | sbcs_unaligned | sbcs_illegal_size
sbcs_sberror_wren := sbcs_unaligned | sbcs_illegal_size sbcs_sberror_wren := sbcs_unaligned | sbcs_illegal_size
sbcs_sberror_din := Mux(sbcs_unaligned, "b011".U, "b100".U) sbcs_sberror_din := Mux(sbcs_unaligned, "b011".U(3.W), "b100".U(3.W))
} }
is(sb_state_t.wait_wr) { is(sb_state_t.wait_wr) {
sb_nxtstate := Mux(sbcs_unaligned | sbcs_illegal_size, sb_state_t.done, sb_state_t.cmd_wr) sb_nxtstate := Mux(sbcs_unaligned | sbcs_illegal_size, sb_state_t.done, sb_state_t.cmd_wr)
sb_state_en := io.dbg_bus_clk_en | sbcs_unaligned | sbcs_illegal_size sb_state_en := io.dbg_bus_clk_en | sbcs_unaligned | sbcs_illegal_size
sbcs_sberror_wren := sbcs_unaligned | sbcs_illegal_size; sbcs_sberror_wren := sbcs_unaligned | sbcs_illegal_size;
sbcs_sberror_din := Mux(sbcs_unaligned, "b011".U, "b100".U) sbcs_sberror_din := Mux(sbcs_unaligned, "b011".U(3.W), "b100".U)
} }
is(sb_state_t.cmd_rd) { is(sb_state_t.cmd_rd) {
sb_nxtstate := sb_state_t.rsp_rd sb_nxtstate := sb_state_t.rsp_rd
@ -378,13 +383,13 @@ class dbg extends Module with lib with RequireAsyncReset {
sb_nxtstate := sb_state_t.done sb_nxtstate := sb_state_t.done
sb_state_en := sb_bus_rsp_read & io.dbg_bus_clk_en sb_state_en := sb_bus_rsp_read & io.dbg_bus_clk_en
sbcs_sberror_wren := sb_state_en & sb_bus_rsp_error sbcs_sberror_wren := sb_state_en & sb_bus_rsp_error
sbcs_sberror_din := "b010".U sbcs_sberror_din := "b010".U(3.W)
} }
is(sb_state_t.rsp_wr) { is(sb_state_t.rsp_wr) {
sb_nxtstate := sb_state_t.done; sb_nxtstate := sb_state_t.done;
sb_state_en := sb_bus_rsp_write & io.dbg_bus_clk_en sb_state_en := sb_bus_rsp_write & io.dbg_bus_clk_en
sbcs_sberror_wren := sb_state_en & sb_bus_rsp_error sbcs_sberror_wren := sb_state_en & sb_bus_rsp_error
sbcs_sberror_din := "b010".U sbcs_sberror_din := "b010".U(3.W)
} }
is(sb_state_t.done) { is(sb_state_t.done) {
sb_nxtstate := sb_state_t.sbidle; sb_nxtstate := sb_state_t.sbidle;
@ -394,7 +399,7 @@ class dbg extends Module with lib with RequireAsyncReset {
sbaddress0_reg_wren1 := sbcs_reg(16) sbaddress0_reg_wren1 := sbcs_reg(16)
}} }}
sb_state := withClockAndReset(sb_free_clk, !dbg_dm_rst_l) { sb_state := withClockAndReset(sb_free_clk, dbg_dm_rst_l) {
RegEnable(sb_nxtstate, 0.U, sb_state_en) RegEnable(sb_nxtstate, 0.U, sb_state_en)
} // sb_state_reg } // sb_state_reg
@ -412,7 +417,7 @@ class dbg extends Module with lib with RequireAsyncReset {
io.sb_axi.aw.bits.cache := "b1111".U io.sb_axi.aw.bits.cache := "b1111".U
io.sb_axi.aw.bits.region := sbaddress0_reg(31, 28) io.sb_axi.aw.bits.region := sbaddress0_reg(31, 28)
io.sb_axi.aw.bits.len := 0.U io.sb_axi.aw.bits.len := 0.U
io.sb_axi.aw.bits.burst := "b01".U io.sb_axi.aw.bits.burst := "b01".U(2.W)
io.sb_axi.aw.bits.qos := 0.U io.sb_axi.aw.bits.qos := 0.U
io.sb_axi.aw.bits.lock := false.B io.sb_axi.aw.bits.lock := false.B
io.sb_axi.w.valid := ((sb_state === sb_state_t.cmd_wr) | (sb_state === sb_state_t.cmd_wr_data)).asBool() io.sb_axi.w.valid := ((sb_state === sb_state_t.cmd_wr) | (sb_state === sb_state_t.cmd_wr_data)).asBool()
@ -421,7 +426,7 @@ class dbg extends Module with lib with RequireAsyncReset {
io.sb_axi.w.bits.strb := Fill(8, (sbcs_reg(19, 17) === "h0".U)) & ("h1".U(8.W) << sbaddress0_reg(2, 0)) | io.sb_axi.w.bits.strb := Fill(8, (sbcs_reg(19, 17) === "h0".U)) & ("h1".U(8.W) << sbaddress0_reg(2, 0)) |
Fill(8, (sbcs_reg(19, 17) === "h1".U)) & ("h3".U(8.W) << Cat(sbaddress0_reg(2, 1), "b0".U)) | Fill(8, (sbcs_reg(19, 17) === "h1".U)) & ("h3".U(8.W) << Cat(sbaddress0_reg(2, 1), "b0".U)) |
Fill(8, (sbcs_reg(19, 17) === "h2".U)) & ("hf".U(8.W) << Cat(sbaddress0_reg(2), "b00".U)) | Fill(8, (sbcs_reg(19, 17) === "h2".U)) & ("hf".U(8.W) << Cat(sbaddress0_reg(2), "b00".U(2.W))) |
Fill(8, (sbcs_reg(19, 17) === "h3".U)) & "hff".U Fill(8, (sbcs_reg(19, 17) === "h3".U)) & "hff".U
io.sb_axi.w.bits.last := true.B io.sb_axi.w.bits.last := true.B
@ -433,7 +438,7 @@ class dbg extends Module with lib with RequireAsyncReset {
io.sb_axi.ar.bits.cache := 0.U io.sb_axi.ar.bits.cache := 0.U
io.sb_axi.ar.bits.region := sbaddress0_reg(31, 28) io.sb_axi.ar.bits.region := sbaddress0_reg(31, 28)
io.sb_axi.ar.bits.len := 0.U io.sb_axi.ar.bits.len := 0.U
io.sb_axi.ar.bits.burst := "b01".U io.sb_axi.ar.bits.burst := "b01".U(2.W)
io.sb_axi.ar.bits.qos := 0.U io.sb_axi.ar.bits.qos := 0.U
io.sb_axi.ar.bits.lock := false.B io.sb_axi.ar.bits.lock := false.B
io.sb_axi.b.ready := true.B io.sb_axi.b.ready := true.B
@ -450,6 +455,7 @@ class dbg extends Module with lib with RequireAsyncReset {
io.dbg_dma.dbg_ib.dbg_cmd_write := io.dbg_dec.dbg_ib.dbg_cmd_write io.dbg_dma.dbg_ib.dbg_cmd_write := io.dbg_dec.dbg_ib.dbg_cmd_write
io.dbg_dma.dbg_ib.dbg_cmd_type := io.dbg_dec.dbg_ib.dbg_cmd_type io.dbg_dma.dbg_ib.dbg_cmd_type := io.dbg_dec.dbg_ib.dbg_cmd_type
} }
object dbg_top extends App {
object dbg_main extends App {
println((new chisel3.stage.ChiselStage).emitVerilog(new dbg())) println((new chisel3.stage.ChiselStage).emitVerilog(new dbg()))
} }

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target/scala-2.12/classes/dbg/dbg_top$.class → target/scala-2.12/classes/dbg/dbg_main$.class
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