inp-id to 1

firrtl_black_box_resource_files.f

@@ -1 +1,3 @@
-/home/waleedbinehsan/Downloads/Quasar/gated_latch.v
+/home/waleedbinehsan/Downloads/Quasar/gated_latch.v
+/home/waleedbinehsan/Downloads/Quasar/dmi_wrapper.sv
+/home/waleedbinehsan/Downloads/Quasar/mem.sv

quasar.anno.json

@@ -1237,6 +1237,10 @@
     "class":"firrtl.transforms.DontTouchAnnotation",
     "target":"~quasar|dec_trigger>io_dec_i0_trigger_match_d"
   },
+  {
+    "class":"firrtl.transforms.DontTouchAnnotation",
+    "target":"~quasar|csr_tlu>_T_755"
+  },
   {
     "class":"firrtl.options.TargetDirAnnotation",
     "directory":"."

quasar_wrapper.anno.json

@@ -980,6 +980,10 @@
     "class":"firrtl.transforms.DontTouchAnnotation",
     "target":"~quasar_wrapper|dec_trigger>io_dec_i0_trigger_match_d"
   },
+  {
+    "class":"firrtl.transforms.DontTouchAnnotation",
+    "target":"~quasar_wrapper|csr_tlu>_T_755"
+  },
   {
     "class":"firrtl.transforms.BlackBoxResourceAnno",
     "target":"quasar_wrapper.dmi_wrapper",

src/main/scala/dec/dec_tlu_ctl.scala

@@ -2125,7 +2125,8 @@ miccme_ce_req := (("hffffffff".U(32.W) << miccmect(31,27)) & Cat(0.U(5.W), miccm
  val dicad1_raw = WireInit(UInt(7.W),0.U)
  val wr_dicad1_r = io.allow_dbg_halt_csr_write & io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === DICAD1)
 
- val dicad1_ns = Mux(wr_dicad1_r.asBool, io.dec_csr_wrdata_r(6,0), io.ifu_ic_debug_rd_data(70,64))
+ val dicad1_ns = Mux(wr_dicad1_r.asBool, io.dec_csr_wrdata_r, io.ifu_ic_debug_rd_data(70,64))
+	dontTouch(dicad1_ns)
 
  dicad1_raw := withClock(io.active_clk){RegEnable(dicad1_ns,0.U,(wr_dicad1_r | io.ifu_ic_debug_rd_data_valid).asBool)}
  dicad1 := Cat(0.U(25.W), dicad1_raw)
@@ -2497,7 +2498,7 @@ for(i <- 0 until 4) {io.trigger_pkt_any(i).tdata2 := mtdata2_t(i)}
  				        io.csr_pkt.csr_misa.asBool            -> 0x40001104.U(32.W),
                 io.csr_pkt.csr_mvendorid.asBool       -> 0x00000045.U(32.W),
                 io.csr_pkt.csr_marchid.asBool         -> 0x00000010.U(32.W),
-                io.csr_pkt.csr_mimpid.asBool          -> 0x1.U(32.W),
+                io.csr_pkt.csr_mimpid.asBool          -> 0x2.U(32.W),
                 io.csr_pkt.csr_mhartid.asBool         -> Cat(io.core_id,0.U(4.W)),
                 io.csr_pkt.csr_mstatus.asBool         -> Cat(0.U(19.W), 3.U(2.W), 0.U(3.W), io.mstatus(1), 0.U(3.W), io.mstatus(0), 0.U(3.W)),
                 io.csr_pkt.csr_mtvec.asBool           -> Cat(io.mtvec(30,1), 0.U(1.W), io.mtvec(0)),

src/main/scala/quasar.scala

@@ -100,8 +100,8 @@ class quasar extends Module with RequireAsyncReset with lib {
   ifu.io.ic <> io.ic
   ifu.io.iccm <> io.iccm
   ifu.io.exu_ifu.exu_bp <> exu.io.exu_bp
-  //ifu.io.exu_ifu.exu_bp.exu_i0_br_fghr_r := exu.io.exu_bp.exu_i0_br_fghr_r
-  //ifu.io.exu_ifu.exu_bp.exu_i0_br_index_r := exu.io.dec_exu.tlu_exu.exu_i0_br_index_r
+  ifu.io.exu_ifu.exu_bp.exu_i0_br_fghr_r := exu.io.exu_bp.exu_i0_br_fghr_r
+  ifu.io.exu_ifu.exu_bp.exu_i0_br_index_r := exu.io.dec_exu.tlu_exu.exu_i0_br_index_r
   ifu.io.dec_tlu_flush_lower_wb := dec.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r
   ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt <> dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt