Update el2_ifu_aln_ctl.scala
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@ -377,7 +377,7 @@ class el2_ifu_aln_ctl extends Module with el2_lib {
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f2pc := RegEnable(io.ifu_fetch_pc, 0.U, f2_wr_en.asBool)
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f2pc := RegEnable(f1pc_in, 0.U, f1_shift_wr_en.asBool)
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f2pc := RegEnable(f0pc_in, 0.U, f0_shift_wr_en.asBool)
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}
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}/*
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object ifu_aln extends App {
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println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu_aln_ctl()))
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}
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}*/
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