All 5 dividers added with LEC

src/main/scala/exu/exu_div_ctl.scala

@@ -275,7 +275,6 @@ class exu_div_existing_1bit_cheapshortq extends Module with RequireAsyncReset wi
     smallnum_ff      := rvdffe(smallnum, div_clken,clock,io.scan_mode)
     shortq_enable_ff := rvdffe(shortq_enable, div_clken,clock,io.scan_mode)
     shortq_shift_xx  := rvdffe(shortq_shift, div_clken,clock,io.scan_mode)
-
     q_ff             := rvdffe(q_in, qff_enable,clock,io.scan_mode)
     a_ff             := rvdffe(a_in, aff_enable,clock,io.scan_mode)
     m_ff             := rvdffe(Cat(io.signed_in & io.divisor_in(31), io.divisor_in(31,0)), io.valid_in,clock,io.scan_mode)
@@ -834,15 +833,10 @@ class exu_div_new_4bit_fullshortq extends Module with RequireAsyncReset with lib
 
   quotient_new := Cat(
     (Mux1H((8 to 14).map(i=> (quotient_raw(15,i)=== Cat(Fill(15-i,0.U),1.U)).asBool -> 1.U)) | (quotient_raw(15)===1.U)),
-
-    ( quotient_raw(15,4) === "b000000000001".U(12.W))| ( quotient_raw(15,5) === "b00000000001".U(11.W)) | ( quotient_raw(15,6) === "b0000000001".U(10.W)) |
-      ( quotient_raw(15,7) === "b000000001".U(9.W)) | ( quotient_raw(15,12)=== "b0001".U(4.W)) | ( quotient_raw(15,13)=== "b001".U(3.W)) |
-      ( quotient_raw(15,14)=== "b01".U(2.W)) | ( quotient_raw(15)   === "b1".U),
-
-    ( quotient_raw(15,2) === "b00000000000001".U(14.W))| ( quotient_raw(15,3) === "b0000000000001".U(13.W)) | ( quotient_raw(15,6) === "b0000000001".U(10.W)) |
-        ( quotient_raw(15,7) === "b000000001".U(9.W)) | ( quotient_raw(15,10)=== "b000001".U(6.W)) | ( quotient_raw(15,11)=== "b00001".U(5.W)) |
-        ( quotient_raw(15,14)=== "b01".U(2.W)) | ( quotient_raw(15)   === "b1".U),
-
+     Mux1H (Seq(( quotient_raw(15,4)   === "b000000000001".U(12.W)) -> 1.U, ( quotient_raw(15,5) === "b00000000001".U(11.W)) -> 1.U, ( quotient_raw(15,6) === "b0000000001".U(10.W)) -> 1.U, ( quotient_raw(15,7) === "b000000001".U(9.W)) -> 1.U,
+      ( quotient_raw(15,12)=== "b0001".U(4.W)) -> 1.U, ( quotient_raw(15,13)=== "b001".U(3.W)) -> 1.U, ( quotient_raw(15,14)=== "b01".U(2.W)) -> 1.U, ( quotient_raw(15)   === "b1".U) -> 1.U)),
+     Mux1H(Seq(( quotient_raw(15,2) === "b00000000000001".U(14.W)) -> 1.U, ( quotient_raw(15,3) === "b0000000000001".U(13.W)) -> 1.U, ( quotient_raw(15,6) === "b0000000001".U(10.W)) -> 1.U, ( quotient_raw(15,7) === "b000000001".U(9.W)) -> 1.U,
+        ( quotient_raw(15,10)=== "b000001".U(6.W)) -> 1.U, ( quotient_raw(15,11)=== "b00001".U(5.W)) -> 1.U, ( quotient_raw(15,14)=== "b01".U(2.W)) -> 1.U, ( quotient_raw(15)   === "b1".U) -> 1.U)),
     (Mux1H((1 to 13 by 2).map(i=> (quotient_raw(15,i)=== Cat(Fill(15-i,0.U),1.U)).asBool -> 1.U)) | (quotient_raw(15)===1.U) ))
   val twos_comp_in = Mux1H(Seq (
     twos_comp_q_sel                       -> q_ff,