ICCM Done
This commit is contained in:
waleed-lm
parent
d6f6e7fd38
commit
1d9661d2c5
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@ -1996,7 +1996,7 @@ circuit el2_ifu_aln_ctl :
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module el2_ifu_aln_ctl :
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input clock : Clock
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input reset : UInt<1>
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output io : {flip scan_mode : UInt<1>, flip active_clk : Clock, flip ifu_async_error_start : UInt<1>, flip iccm_rd_ecc_double_err : UInt<1>, flip ic_access_fault_f : UInt<1>, flip ic_access_fault_type_f : UInt<2>, flip ifu_bp_fghr_f : UInt<8>, flip ifu_bp_btb_target_f : UInt<32>, flip ifu_bp_poffset_f : UInt<12>, flip ifu_bp_hist0_f : UInt<2>, flip ifu_bp_hist1_f : UInt<2>, flip ifu_bp_pc4_f : UInt<2>, flip ifu_bp_way_f : UInt<2>, flip ifu_bp_valid_f : UInt<2>, flip ifu_bp_ret_f : UInt<2>, flip exu_flush_final : UInt<1>, flip dec_i0_decode_d : UInt<1>, flip ifu_fetch_data_f : UInt<32>, flip ifu_fetch_val : UInt<2>, flip ifu_fetch_pc : UInt<32>, ifu_i0_valid : UInt<1>, ifu_i0_icaf : UInt<1>, ifu_i0_icaf_type : UInt<2>, ifu_i0_icaf_f1 : UInt<1>, ifu_i0_dbecc : UInt<1>, ifu_i0_instr : UInt<32>, ifu_i0_pc : UInt<32>, ifu_i0_pc4 : UInt<1>, ifu_fb_consume1 : UInt<1>, ifu_fb_consume2 : UInt<1>, ifu_i0_bp_index : UInt<7>, ifu_i0_bp_fghr : UInt<8>, ifu_i0_bp_btag : UInt<5>, ifu_pmu_instr_aligned : UInt<1>, ifu_i0_cinst : UInt<16>, i0_brp : {valid : UInt<1>, toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<32>, way : UInt<1>, ret : UInt<1>}}
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output io : {flip scan_mode : UInt<1>, flip active_clk : Clock, flip ifu_async_error_start : UInt<1>, flip iccm_rd_ecc_double_err : UInt<1>, flip ic_access_fault_f : UInt<1>, flip ic_access_fault_type_f : UInt<2>, flip ifu_bp_fghr_f : UInt<8>, flip ifu_bp_btb_target_f : UInt<32>, flip ifu_bp_poffset_f : UInt<12>, flip ifu_bp_hist0_f : UInt<2>, flip ifu_bp_hist1_f : UInt<2>, flip ifu_bp_pc4_f : UInt<2>, flip ifu_bp_way_f : UInt<2>, flip ifu_bp_valid_f : UInt<2>, flip ifu_bp_ret_f : UInt<2>, flip exu_flush_final : UInt<1>, flip dec_i0_decode_d : UInt<1>, flip ifu_fetch_data_f : UInt<32>, flip ifu_fetch_val : UInt<2>, flip ifu_fetch_pc : UInt<32>, ifu_i0_valid : UInt<1>, ifu_i0_icaf : UInt<1>, ifu_i0_icaf_type : UInt<2>, ifu_i0_icaf_f1 : UInt<1>, ifu_i0_dbecc : UInt<1>, ifu_i0_instr : UInt<32>, ifu_i0_pc : UInt<32>, ifu_i0_pc4 : UInt<1>, ifu_fb_consume1 : UInt<1>, ifu_fb_consume2 : UInt<1>, ifu_i0_bp_index : UInt<7>, ifu_i0_bp_fghr : UInt<8>, ifu_i0_bp_btag : UInt<5>, ifu_pmu_instr_aligned : UInt<1>, ifu_i0_cinst : UInt<16>, i0_brp : {valid : UInt<1>, toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}
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wire error_stall_in : UInt<1>
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error_stall_in <= UInt<1>("h00")
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@ -2905,34 +2905,34 @@ circuit el2_ifu_aln_ctl :
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wire _T_671 : UInt<1> @[Mux.scala 27:72]
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_T_671 <= _T_670 @[Mux.scala 27:72]
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io.ifu_i0_dbecc <= _T_671 @[el2_ifu_aln_ctl.scala 330:19]
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node _T_672 = bits(f0pc, 8, 1) @[el2_lib.scala 186:12]
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node _T_673 = bits(f0pc, 16, 9) @[el2_lib.scala 186:50]
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node _T_674 = xor(_T_672, _T_673) @[el2_lib.scala 186:46]
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node _T_675 = bits(f0pc, 24, 17) @[el2_lib.scala 186:88]
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node firstpc_hash = xor(_T_674, _T_675) @[el2_lib.scala 186:84]
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node _T_676 = bits(secondpc, 8, 1) @[el2_lib.scala 186:12]
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node _T_677 = bits(secondpc, 16, 9) @[el2_lib.scala 186:50]
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node _T_678 = xor(_T_676, _T_677) @[el2_lib.scala 186:46]
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node _T_679 = bits(secondpc, 24, 17) @[el2_lib.scala 186:88]
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node secondpc_hash = xor(_T_678, _T_679) @[el2_lib.scala 186:84]
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node _T_680 = bits(f0pc, 13, 9) @[el2_lib.scala 177:32]
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node _T_681 = bits(f0pc, 18, 14) @[el2_lib.scala 177:32]
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node _T_682 = bits(f0pc, 23, 19) @[el2_lib.scala 177:32]
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wire _T_683 : UInt<5>[3] @[el2_lib.scala 177:24]
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_T_683[0] <= _T_680 @[el2_lib.scala 177:24]
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_T_683[1] <= _T_681 @[el2_lib.scala 177:24]
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_T_683[2] <= _T_682 @[el2_lib.scala 177:24]
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node _T_684 = xor(_T_683[0], _T_683[1]) @[el2_lib.scala 177:111]
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node firstbrtag_hash = xor(_T_684, _T_683[2]) @[el2_lib.scala 177:111]
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node _T_685 = bits(secondpc, 13, 9) @[el2_lib.scala 177:32]
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node _T_686 = bits(secondpc, 18, 14) @[el2_lib.scala 177:32]
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node _T_687 = bits(secondpc, 23, 19) @[el2_lib.scala 177:32]
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wire _T_688 : UInt<5>[3] @[el2_lib.scala 177:24]
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_T_688[0] <= _T_685 @[el2_lib.scala 177:24]
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_T_688[1] <= _T_686 @[el2_lib.scala 177:24]
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_T_688[2] <= _T_687 @[el2_lib.scala 177:24]
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node _T_689 = xor(_T_688[0], _T_688[1]) @[el2_lib.scala 177:111]
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node secondbrtag_hash = xor(_T_689, _T_688[2]) @[el2_lib.scala 177:111]
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node _T_672 = bits(f0pc, 8, 1) @[el2_lib.scala 191:12]
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node _T_673 = bits(f0pc, 16, 9) @[el2_lib.scala 191:50]
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node _T_674 = xor(_T_672, _T_673) @[el2_lib.scala 191:46]
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node _T_675 = bits(f0pc, 24, 17) @[el2_lib.scala 191:88]
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node firstpc_hash = xor(_T_674, _T_675) @[el2_lib.scala 191:84]
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node _T_676 = bits(secondpc, 8, 1) @[el2_lib.scala 191:12]
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node _T_677 = bits(secondpc, 16, 9) @[el2_lib.scala 191:50]
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node _T_678 = xor(_T_676, _T_677) @[el2_lib.scala 191:46]
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node _T_679 = bits(secondpc, 24, 17) @[el2_lib.scala 191:88]
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node secondpc_hash = xor(_T_678, _T_679) @[el2_lib.scala 191:84]
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node _T_680 = bits(f0pc, 13, 9) @[el2_lib.scala 182:32]
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node _T_681 = bits(f0pc, 18, 14) @[el2_lib.scala 182:32]
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node _T_682 = bits(f0pc, 23, 19) @[el2_lib.scala 182:32]
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wire _T_683 : UInt<5>[3] @[el2_lib.scala 182:24]
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_T_683[0] <= _T_680 @[el2_lib.scala 182:24]
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_T_683[1] <= _T_681 @[el2_lib.scala 182:24]
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_T_683[2] <= _T_682 @[el2_lib.scala 182:24]
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node _T_684 = xor(_T_683[0], _T_683[1]) @[el2_lib.scala 182:111]
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node firstbrtag_hash = xor(_T_684, _T_683[2]) @[el2_lib.scala 182:111]
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node _T_685 = bits(secondpc, 13, 9) @[el2_lib.scala 182:32]
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node _T_686 = bits(secondpc, 18, 14) @[el2_lib.scala 182:32]
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node _T_687 = bits(secondpc, 23, 19) @[el2_lib.scala 182:32]
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wire _T_688 : UInt<5>[3] @[el2_lib.scala 182:24]
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_T_688[0] <= _T_685 @[el2_lib.scala 182:24]
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_T_688[1] <= _T_686 @[el2_lib.scala 182:24]
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_T_688[2] <= _T_687 @[el2_lib.scala 182:24]
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node _T_689 = xor(_T_688[0], _T_688[1]) @[el2_lib.scala 182:111]
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node secondbrtag_hash = xor(_T_689, _T_688[2]) @[el2_lib.scala 182:111]
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node _T_690 = bits(alignbrend, 0, 0) @[el2_ifu_aln_ctl.scala 340:42]
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node _T_691 = and(first2B, _T_690) @[el2_ifu_aln_ctl.scala 340:30]
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node _T_692 = bits(alignbrend, 1, 1) @[el2_ifu_aln_ctl.scala 340:70]
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@ -551,7 +551,7 @@ module el2_ifu_aln_ctl(
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output io_i0_brp_br_error,
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output io_i0_brp_br_start_error,
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output io_i0_brp_bank,
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output [31:0] io_i0_brp_prett,
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output [30:0] io_i0_brp_prett,
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output io_i0_brp_way,
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output io_i0_brp_ret
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);
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@ -725,7 +725,6 @@ module el2_ifu_aln_ctl(
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wire [54:0] misc_data_in = {io_iccm_rd_ecc_double_err,io_ic_access_fault_f,io_ic_access_fault_type_f,io_ifu_bp_btb_target_f[31:1],io_ifu_bp_poffset_f,io_ifu_bp_fghr_f}; // @[Cat.scala 29:58]
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wire f1dbecc = misc1eff[52]; // @[el2_ifu_aln_ctl.scala 194:25]
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wire f0dbecc = misc0eff[54]; // @[el2_ifu_aln_ctl.scala 201:25]
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wire [30:0] f0prett = misc0eff[50:20]; // @[el2_ifu_aln_ctl.scala 204:25]
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wire [5:0] _T_299 = {io_ifu_bp_hist1_f[0],io_ifu_bp_hist0_f[0],io_ifu_bp_pc4_f[0],io_ifu_bp_way_f[0],io_ifu_bp_valid_f[0],io_ifu_bp_ret_f[0]}; // @[Cat.scala 29:58]
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wire [11:0] brdata_in = {io_ifu_bp_hist1_f[1],io_ifu_bp_hist0_f[1],io_ifu_bp_pc4_f[1],io_ifu_bp_way_f[1],io_ifu_bp_valid_f[1],io_ifu_bp_ret_f[1],_T_299}; // @[Cat.scala 29:58]
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reg [11:0] brdata1; // @[Reg.scala 27:20]
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@ -846,7 +845,7 @@ module el2_ifu_aln_ctl(
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assign io_i0_brp_br_error = io_i0_brp_valid & i0_brp_pc4; // @[el2_ifu_aln_ctl.scala 358:22]
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assign io_i0_brp_br_start_error = 1'h0; // @[el2_ifu_aln_ctl.scala 352:29]
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assign io_i0_brp_bank = 1'h0; // @[el2_ifu_aln_ctl.scala 354:29]
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assign io_i0_brp_prett = {{1'd0}, f0prett}; // @[el2_ifu_aln_ctl.scala 350:19]
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assign io_i0_brp_prett = misc0eff[50:20]; // @[el2_ifu_aln_ctl.scala 350:19]
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assign io_i0_brp_way = alignway[0]; // @[el2_ifu_aln_ctl.scala 344:17]
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assign io_i0_brp_ret = alignret[0]; // @[el2_ifu_aln_ctl.scala 342:17]
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assign decompressed_io_din = aligndata[15:0]; // @[el2_ifu_aln_ctl.scala 101:23]
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@ -1,8 +1,69 @@
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[
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_hit_f",
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"sources":[
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"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final",
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"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_access_fault_f",
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"sources":[
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"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_error_start",
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"sources":[
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"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_eccerr",
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"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit",
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"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_dma_active",
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"sources":[
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"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_flush_err_wb"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ifu_async_error_start",
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"sources":[
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"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rd_ecc_single_err",
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"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_error_start",
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"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_eccerr",
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"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_rd_hit",
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"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_exu_flush_final"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_access_fault_type_f",
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"sources":[
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"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_iccm_rd_ecc_double_err"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_ic_debug_wr_data",
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"sources":[
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"~el2_ifu_mem_ctl|el2_ifu_mem_ctl>io_dec_tlu_ic_diag_pkt_icache_wrdata"
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]
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},
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{
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"class":"firrtl.EmitCircuitAnnotation",
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"emitter":"firrtl.VerilogEmitter"
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},
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{
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"class":"firrtl.transforms.BlackBoxResourceAnno",
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"target":"el2_ifu_mem_ctl.TEC_RV_ICG",
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"resourceId":"/vsrc/TEC_RV_ICG.v"
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},
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{
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"class":"firrtl.options.TargetDirAnnotation",
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"directory":"."
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2155
el2_ifu_mem_ctl.fir
2155
el2_ifu_mem_ctl.fir
File diff suppressed because it is too large
Load Diff
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@ -1,3 +1,22 @@
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module rvclkhdr(
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input io_clk,
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input io_en,
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input io_scan_mode
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);
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wire clkhdr_Q; // @[el2_lib.scala 403:26]
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wire clkhdr_CK; // @[el2_lib.scala 403:26]
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wire clkhdr_EN; // @[el2_lib.scala 403:26]
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wire clkhdr_SE; // @[el2_lib.scala 403:26]
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TEC_RV_ICG clkhdr ( // @[el2_lib.scala 403:26]
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.Q(clkhdr_Q),
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.CK(clkhdr_CK),
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.EN(clkhdr_EN),
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.SE(clkhdr_SE)
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);
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assign clkhdr_CK = io_clk; // @[el2_lib.scala 405:18]
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assign clkhdr_EN = io_en; // @[el2_lib.scala 406:18]
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assign clkhdr_SE = io_scan_mode; // @[el2_lib.scala 407:18]
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endmodule
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module el2_ifu_mem_ctl(
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input clock,
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input reset,
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@ -119,81 +138,379 @@ module el2_ifu_mem_ctl(
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input io_dec_tlu_core_ecc_disable,
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output io_ifu_ic_debug_rd_data_valid,
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output io_iccm_buf_correct_ecc,
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output io_iccm_correction_state
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output io_iccm_correction_state,
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input io_scan_mode
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);
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assign io_ifu_miss_state_idle = 1'h0; // @[el2_ifu_mem_ctl.scala 129:25]
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assign io_ifu_ic_mb_empty = 1'h0; // @[el2_ifu_mem_ctl.scala 130:21]
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assign io_ic_dma_active = 1'h0; // @[el2_ifu_mem_ctl.scala 131:19]
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assign io_ic_write_stall = 1'h0; // @[el2_ifu_mem_ctl.scala 132:20]
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assign io_ifu_pmu_ic_miss = 1'h0; // @[el2_ifu_mem_ctl.scala 133:21]
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assign io_ifu_pmu_ic_hit = 1'h0; // @[el2_ifu_mem_ctl.scala 134:20]
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assign io_ifu_pmu_bus_error = 1'h0; // @[el2_ifu_mem_ctl.scala 135:23]
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assign io_ifu_pmu_bus_busy = 1'h0; // @[el2_ifu_mem_ctl.scala 136:22]
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assign io_ifu_pmu_bus_trxn = 1'h0; // @[el2_ifu_mem_ctl.scala 137:22]
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assign io_ifu_axi_awvalid = 1'h0; // @[el2_ifu_mem_ctl.scala 138:21]
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assign io_ifu_axi_awid = 3'h0; // @[el2_ifu_mem_ctl.scala 139:18]
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assign io_ifu_axi_awaddr = 32'h0; // @[el2_ifu_mem_ctl.scala 140:20]
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assign io_ifu_axi_awregion = 4'h0; // @[el2_ifu_mem_ctl.scala 199:22]
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assign io_ifu_axi_awlen = 8'h0; // @[el2_ifu_mem_ctl.scala 141:19]
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assign io_ifu_axi_awsize = 3'h0; // @[el2_ifu_mem_ctl.scala 142:20]
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assign io_ifu_axi_awburst = 2'h0; // @[el2_ifu_mem_ctl.scala 143:21]
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assign io_ifu_axi_awlock = 1'h0; // @[el2_ifu_mem_ctl.scala 144:20]
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assign io_ifu_axi_awcache = 4'h0; // @[el2_ifu_mem_ctl.scala 145:21]
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assign io_ifu_axi_awprot = 3'h0; // @[el2_ifu_mem_ctl.scala 146:20]
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assign io_ifu_axi_awqos = 4'h0; // @[el2_ifu_mem_ctl.scala 147:19]
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assign io_ifu_axi_wvalid = 1'h0; // @[el2_ifu_mem_ctl.scala 148:20]
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assign io_ifu_axi_wdata = 64'h0; // @[el2_ifu_mem_ctl.scala 149:19]
|
||||
assign io_ifu_axi_wstrb = 8'h0; // @[el2_ifu_mem_ctl.scala 150:19]
|
||||
assign io_ifu_axi_wlast = 1'h0; // @[el2_ifu_mem_ctl.scala 151:19]
|
||||
assign io_ifu_axi_bready = 1'h0; // @[el2_ifu_mem_ctl.scala 152:20]
|
||||
assign io_ifu_axi_arvalid = 1'h0; // @[el2_ifu_mem_ctl.scala 153:21]
|
||||
assign io_ifu_axi_arid = 3'h0; // @[el2_ifu_mem_ctl.scala 155:18]
|
||||
assign io_ifu_axi_araddr = 32'h0; // @[el2_ifu_mem_ctl.scala 156:20]
|
||||
assign io_ifu_axi_arregion = 4'h0; // @[el2_ifu_mem_ctl.scala 157:22]
|
||||
assign io_ifu_axi_arlen = 8'h0; // @[el2_ifu_mem_ctl.scala 158:19]
|
||||
assign io_ifu_axi_arsize = 3'h0; // @[el2_ifu_mem_ctl.scala 159:20]
|
||||
assign io_ifu_axi_arburst = 2'h0; // @[el2_ifu_mem_ctl.scala 160:21]
|
||||
assign io_ifu_axi_arlock = 1'h0; // @[el2_ifu_mem_ctl.scala 161:20]
|
||||
assign io_ifu_axi_arcache = 4'h0; // @[el2_ifu_mem_ctl.scala 162:21]
|
||||
assign io_ifu_axi_arprot = 3'h0; // @[el2_ifu_mem_ctl.scala 163:20]
|
||||
assign io_ifu_axi_arqos = 4'h0; // @[el2_ifu_mem_ctl.scala 164:19]
|
||||
assign io_ifu_axi_rready = 1'h0; // @[el2_ifu_mem_ctl.scala 165:20]
|
||||
assign io_iccm_dma_ecc_error = 1'h0; // @[el2_ifu_mem_ctl.scala 166:24]
|
||||
assign io_iccm_dma_rvalid = 1'h0; // @[el2_ifu_mem_ctl.scala 167:21]
|
||||
assign io_iccm_dma_rdata = 64'h0; // @[el2_ifu_mem_ctl.scala 168:20]
|
||||
assign io_iccm_dma_rtag = 3'h0; // @[el2_ifu_mem_ctl.scala 169:19]
|
||||
assign io_iccm_ready = 1'h0; // @[el2_ifu_mem_ctl.scala 170:16]
|
||||
assign io_ic_rw_addr = 31'h0; // @[el2_ifu_mem_ctl.scala 171:16]
|
||||
assign io_ic_wr_en = 2'h0; // @[el2_ifu_mem_ctl.scala 172:14]
|
||||
assign io_ic_rd_en = 1'h0; // @[el2_ifu_mem_ctl.scala 173:14]
|
||||
assign io_ic_wr_data_0 = 71'h0; // @[el2_ifu_mem_ctl.scala 174:16]
|
||||
assign io_ic_wr_data_1 = 71'h0; // @[el2_ifu_mem_ctl.scala 174:16]
|
||||
assign io_ic_debug_wr_data = 71'h0; // @[el2_ifu_mem_ctl.scala 175:22]
|
||||
assign io_ifu_ic_debug_rd_data = 71'h0; // @[el2_ifu_mem_ctl.scala 176:26]
|
||||
assign io_ic_debug_addr = 10'h0; // @[el2_ifu_mem_ctl.scala 154:19]
|
||||
assign io_ic_debug_rd_en = 1'h0; // @[el2_ifu_mem_ctl.scala 126:20]
|
||||
assign io_ic_debug_wr_en = 1'h0; // @[el2_ifu_mem_ctl.scala 127:20]
|
||||
assign io_ic_debug_tag_array = 1'h0; // @[el2_ifu_mem_ctl.scala 128:24]
|
||||
assign io_ic_debug_way = 2'h0; // @[el2_ifu_mem_ctl.scala 198:18]
|
||||
assign io_ic_tag_valid = 2'h0; // @[el2_ifu_mem_ctl.scala 177:18]
|
||||
assign io_iccm_rw_addr = 15'h0; // @[el2_ifu_mem_ctl.scala 178:18]
|
||||
assign io_iccm_wren = 1'h0; // @[el2_ifu_mem_ctl.scala 179:15]
|
||||
assign io_iccm_rden = 1'h0; // @[el2_ifu_mem_ctl.scala 180:15]
|
||||
assign io_iccm_wr_data = 78'h0; // @[el2_ifu_mem_ctl.scala 181:18]
|
||||
assign io_iccm_wr_size = 3'h0; // @[el2_ifu_mem_ctl.scala 182:18]
|
||||
assign io_ic_hit_f = 1'h0; // @[el2_ifu_mem_ctl.scala 183:14]
|
||||
assign io_ic_access_fault_f = 1'h0; // @[el2_ifu_mem_ctl.scala 184:23]
|
||||
assign io_ic_access_fault_type_f = 2'h0; // @[el2_ifu_mem_ctl.scala 185:28]
|
||||
assign io_iccm_rd_ecc_single_err = 1'h0; // @[el2_ifu_mem_ctl.scala 186:28]
|
||||
assign io_iccm_rd_ecc_double_err = 1'h0; // @[el2_ifu_mem_ctl.scala 187:28]
|
||||
assign io_ic_error_start = 1'h0; // @[el2_ifu_mem_ctl.scala 188:20]
|
||||
assign io_ifu_async_error_start = 1'h0; // @[el2_ifu_mem_ctl.scala 189:27]
|
||||
assign io_iccm_dma_sb_error = 1'h0; // @[el2_ifu_mem_ctl.scala 190:23]
|
||||
assign io_ic_fetch_val_f = 2'h0; // @[el2_ifu_mem_ctl.scala 191:20]
|
||||
assign io_ic_data_f = 32'h0; // @[el2_ifu_mem_ctl.scala 192:15]
|
||||
assign io_ic_premux_data = 64'h0; // @[el2_ifu_mem_ctl.scala 193:20]
|
||||
assign io_ic_sel_premux_data = 1'h0; // @[el2_ifu_mem_ctl.scala 194:24]
|
||||
assign io_ifu_ic_debug_rd_data_valid = 1'h0; // @[el2_ifu_mem_ctl.scala 195:32]
|
||||
assign io_iccm_buf_correct_ecc = 1'h0; // @[el2_ifu_mem_ctl.scala 196:26]
|
||||
assign io_iccm_correction_state = 1'h0; // @[el2_ifu_mem_ctl.scala 197:27]
|
||||
`ifdef RANDOMIZE_REG_INIT
|
||||
reg [31:0] _RAND_0;
|
||||
reg [31:0] _RAND_1;
|
||||
reg [31:0] _RAND_2;
|
||||
reg [31:0] _RAND_3;
|
||||
reg [31:0] _RAND_4;
|
||||
reg [31:0] _RAND_5;
|
||||
reg [31:0] _RAND_6;
|
||||
reg [31:0] _RAND_7;
|
||||
reg [95:0] _RAND_8;
|
||||
`endif // RANDOMIZE_REG_INIT
|
||||
wire rvclkhdr_io_clk; // @[el2_lib.scala 412:22]
|
||||
wire rvclkhdr_io_en; // @[el2_lib.scala 412:22]
|
||||
wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 412:22]
|
||||
wire rvclkhdr_1_io_clk; // @[el2_lib.scala 412:22]
|
||||
wire rvclkhdr_1_io_en; // @[el2_lib.scala 412:22]
|
||||
wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 412:22]
|
||||
reg flush_final_f; // @[el2_ifu_mem_ctl.scala 234:30]
|
||||
reg ifc_fetch_req_f_raw; // @[el2_ifu_mem_ctl.scala 367:36]
|
||||
wire _T_308 = ~io_exu_flush_final; // @[el2_ifu_mem_ctl.scala 368:44]
|
||||
wire ifc_fetch_req_f = ifc_fetch_req_f_raw & _T_308; // @[el2_ifu_mem_ctl.scala 368:42]
|
||||
wire _T = io_ifc_fetch_req_bf_raw | ifc_fetch_req_f; // @[el2_ifu_mem_ctl.scala 235:53]
|
||||
reg [2:0] miss_state; // @[Reg.scala 27:20]
|
||||
wire miss_pending = miss_state != 3'h0; // @[el2_ifu_mem_ctl.scala 300:30]
|
||||
wire _T_1 = _T | miss_pending; // @[el2_ifu_mem_ctl.scala 235:71]
|
||||
wire _T_26 = 3'h0 == miss_state; // @[Conditional.scala 37:30]
|
||||
wire _T_219 = |io_ic_rd_hit; // @[el2_ifu_mem_ctl.scala 330:37]
|
||||
wire _T_220 = ~_T_219; // @[el2_ifu_mem_ctl.scala 330:23]
|
||||
reg ifc_iccm_access_f; // @[el2_ifu_mem_ctl.scala 369:31]
|
||||
wire _T_199 = ~ifc_iccm_access_f; // @[el2_ifu_mem_ctl.scala 321:48]
|
||||
wire fetch_req_icache_f = ifc_fetch_req_f & _T_199; // @[el2_ifu_mem_ctl.scala 321:46]
|
||||
wire _T_222 = _T_220 & fetch_req_icache_f; // @[el2_ifu_mem_ctl.scala 330:59]
|
||||
wire _T_223 = ~miss_pending; // @[el2_ifu_mem_ctl.scala 330:82]
|
||||
wire ic_act_miss_f = _T_222 & _T_223; // @[el2_ifu_mem_ctl.scala 330:80]
|
||||
wire _T_28 = ic_act_miss_f & _T_308; // @[el2_ifu_mem_ctl.scala 249:43]
|
||||
wire [2:0] _T_30 = _T_28 ? 3'h1 : 3'h2; // @[el2_ifu_mem_ctl.scala 249:27]
|
||||
wire _T_33 = 3'h1 == miss_state; // @[Conditional.scala 37:30]
|
||||
reg uncacheable_miss_ff; // @[el2_ifu_mem_ctl.scala 357:33]
|
||||
wire _T_52 = ~uncacheable_miss_ff; // @[el2_ifu_mem_ctl.scala 255:51]
|
||||
wire ifu_bp_hit_taken_q_f = io_ifu_bp_hit_taken_f & io_ic_hit_f; // @[el2_ifu_mem_ctl.scala 245:52]
|
||||
wire _T_74 = io_exu_flush_final | ifu_bp_hit_taken_q_f; // @[el2_ifu_mem_ctl.scala 258:44]
|
||||
wire [2:0] _T_79 = _T_74 ? 3'h2 : 3'h0; // @[el2_ifu_mem_ctl.scala 258:22]
|
||||
wire [2:0] _T_85 = io_dec_tlu_force_halt ? 3'h0 : _T_79; // @[el2_ifu_mem_ctl.scala 252:27]
|
||||
wire _T_94 = 3'h4 == miss_state; // @[Conditional.scala 37:30]
|
||||
wire _T_98 = 3'h6 == miss_state; // @[Conditional.scala 37:30]
|
||||
wire _T_104 = ~io_dec_tlu_force_halt; // @[el2_ifu_mem_ctl.scala 266:124]
|
||||
wire _T_105 = _T_74 & _T_104; // @[el2_ifu_mem_ctl.scala 266:122]
|
||||
wire [2:0] _T_107 = _T_105 ? 3'h2 : 3'h0; // @[el2_ifu_mem_ctl.scala 266:27]
|
||||
wire _T_113 = 3'h3 == miss_state; // @[Conditional.scala 37:30]
|
||||
wire _T_118 = io_exu_flush_final & _T_104; // @[el2_ifu_mem_ctl.scala 270:82]
|
||||
wire [2:0] _T_120 = _T_118 ? 3'h2 : 3'h0; // @[el2_ifu_mem_ctl.scala 270:27]
|
||||
wire _T_124 = 3'h2 == miss_state; // @[Conditional.scala 37:30]
|
||||
wire _T_228 = io_ic_rd_hit == 2'h0; // @[el2_ifu_mem_ctl.scala 331:28]
|
||||
wire _T_230 = _T_228 & fetch_req_icache_f; // @[el2_ifu_mem_ctl.scala 331:60]
|
||||
wire _T_231 = miss_state == 3'h2; // @[el2_ifu_mem_ctl.scala 331:94]
|
||||
wire _T_232 = _T_230 & _T_231; // @[el2_ifu_mem_ctl.scala 331:81]
|
||||
reg [30:0] imb_ff; // @[el2_ifu_mem_ctl.scala 358:20]
|
||||
reg [30:0] ifu_fetch_addr_int_f; // @[el2_ifu_mem_ctl.scala 355:34]
|
||||
wire _T_235 = imb_ff[30:5] != ifu_fetch_addr_int_f[30:5]; // @[el2_ifu_mem_ctl.scala 332:39]
|
||||
wire _T_236 = _T_232 & _T_235; // @[el2_ifu_mem_ctl.scala 331:111]
|
||||
wire ic_miss_under_miss_f = _T_236 & _T_52; // @[el2_ifu_mem_ctl.scala 332:91]
|
||||
wire _T_129 = ic_miss_under_miss_f & _T_104; // @[el2_ifu_mem_ctl.scala 274:84]
|
||||
wire _T_248 = _T_222 & _T_231; // @[el2_ifu_mem_ctl.scala 333:85]
|
||||
wire _T_251 = imb_ff[30:5] == ifu_fetch_addr_int_f[30:5]; // @[el2_ifu_mem_ctl.scala 334:39]
|
||||
wire _T_252 = _T_251 | uncacheable_miss_ff; // @[el2_ifu_mem_ctl.scala 334:91]
|
||||
wire ic_ignore_2nd_miss_f = _T_248 & _T_252; // @[el2_ifu_mem_ctl.scala 333:117]
|
||||
wire _T_135 = ic_ignore_2nd_miss_f & _T_104; // @[el2_ifu_mem_ctl.scala 275:69]
|
||||
wire [2:0] _T_137 = _T_135 ? 3'h7 : 3'h0; // @[el2_ifu_mem_ctl.scala 275:12]
|
||||
wire [2:0] _T_138 = _T_129 ? 3'h5 : _T_137; // @[el2_ifu_mem_ctl.scala 274:27]
|
||||
wire _T_143 = 3'h5 == miss_state; // @[Conditional.scala 37:30]
|
||||
wire [2:0] _T_147 = io_exu_flush_final ? 3'h2 : 3'h1; // @[el2_ifu_mem_ctl.scala 279:62]
|
||||
wire [2:0] _T_148 = io_dec_tlu_force_halt ? 3'h0 : _T_147; // @[el2_ifu_mem_ctl.scala 279:27]
|
||||
wire _T_152 = 3'h7 == miss_state; // @[Conditional.scala 37:30]
|
||||
wire [2:0] _T_156 = io_exu_flush_final ? 3'h2 : 3'h0; // @[el2_ifu_mem_ctl.scala 284:62]
|
||||
wire [2:0] _T_157 = io_dec_tlu_force_halt ? 3'h0 : _T_156; // @[el2_ifu_mem_ctl.scala 284:27]
|
||||
wire [2:0] _GEN_0 = _T_152 ? _T_157 : 3'h0; // @[Conditional.scala 39:67]
|
||||
wire [2:0] _GEN_2 = _T_143 ? _T_148 : _GEN_0; // @[Conditional.scala 39:67]
|
||||
wire [2:0] _GEN_4 = _T_124 ? _T_138 : _GEN_2; // @[Conditional.scala 39:67]
|
||||
wire [2:0] _GEN_6 = _T_113 ? _T_120 : _GEN_4; // @[Conditional.scala 39:67]
|
||||
wire [2:0] _GEN_8 = _T_98 ? _T_107 : _GEN_6; // @[Conditional.scala 39:67]
|
||||
wire [2:0] _GEN_10 = _T_94 ? 3'h0 : _GEN_8; // @[Conditional.scala 39:67]
|
||||
wire [2:0] _GEN_12 = _T_33 ? _T_85 : _GEN_10; // @[Conditional.scala 39:67]
|
||||
wire [2:0] miss_nxtstate = _T_26 ? _T_30 : _GEN_12; // @[Conditional.scala 40:58]
|
||||
wire _T_32 = ic_act_miss_f & _T_104; // @[el2_ifu_mem_ctl.scala 250:38]
|
||||
wire _T_86 = io_dec_tlu_force_halt | io_exu_flush_final; // @[el2_ifu_mem_ctl.scala 259:46]
|
||||
wire _T_88 = _T_86 | ifu_bp_hit_taken_q_f; // @[el2_ifu_mem_ctl.scala 259:82]
|
||||
wire _T_95 = io_exu_flush_final | flush_final_f; // @[el2_ifu_mem_ctl.scala 263:43]
|
||||
wire _T_97 = _T_95 | io_dec_tlu_force_halt; // @[el2_ifu_mem_ctl.scala 263:74]
|
||||
wire _T_112 = _T_74 | io_dec_tlu_force_halt; // @[el2_ifu_mem_ctl.scala 267:118]
|
||||
wire _T_123 = io_exu_flush_final | io_dec_tlu_force_halt; // @[el2_ifu_mem_ctl.scala 271:76]
|
||||
wire _T_141 = ic_miss_under_miss_f | ic_ignore_2nd_miss_f; // @[el2_ifu_mem_ctl.scala 276:78]
|
||||
wire _T_142 = _T_141 | io_dec_tlu_force_halt; // @[el2_ifu_mem_ctl.scala 276:101]
|
||||
wire _GEN_1 = _T_152 & _T_123; // @[Conditional.scala 39:67]
|
||||
wire _GEN_3 = _T_143 ? _T_123 : _GEN_1; // @[Conditional.scala 39:67]
|
||||
wire _GEN_5 = _T_124 ? _T_142 : _GEN_3; // @[Conditional.scala 39:67]
|
||||
wire _GEN_7 = _T_113 ? _T_123 : _GEN_5; // @[Conditional.scala 39:67]
|
||||
wire _GEN_9 = _T_98 ? _T_112 : _GEN_7; // @[Conditional.scala 39:67]
|
||||
wire _GEN_11 = _T_94 ? _T_97 : _GEN_9; // @[Conditional.scala 39:67]
|
||||
wire _GEN_13 = _T_33 ? _T_88 : _GEN_11; // @[Conditional.scala 39:67]
|
||||
wire miss_state_en = _T_26 ? _T_32 : _GEN_13; // @[Conditional.scala 40:58]
|
||||
wire _T_165 = miss_state == 3'h4; // @[el2_ifu_mem_ctl.scala 301:73]
|
||||
wire _T_172 = _T_165 & io_exu_flush_final; // @[el2_ifu_mem_ctl.scala 302:106]
|
||||
wire _T_173 = ~_T_172; // @[el2_ifu_mem_ctl.scala 302:72]
|
||||
wire _T_174 = miss_pending & _T_173; // @[el2_ifu_mem_ctl.scala 302:70]
|
||||
wire _T_179 = _T_174 | ic_act_miss_f; // @[el2_ifu_mem_ctl.scala 303:77]
|
||||
wire _T_180 = miss_nxtstate == 3'h4; // @[el2_ifu_mem_ctl.scala 304:36]
|
||||
wire _T_181 = miss_pending & _T_180; // @[el2_ifu_mem_ctl.scala 304:19]
|
||||
wire sel_hold_imb = _T_179 | _T_181; // @[el2_ifu_mem_ctl.scala 303:93]
|
||||
wire fetch_req_iccm_f = ifc_fetch_req_f & ifc_iccm_access_f; // @[el2_ifu_mem_ctl.scala 322:46]
|
||||
wire _T_204 = _T_223 | _T_231; // @[el2_ifu_mem_ctl.scala 323:59]
|
||||
wire _T_205 = miss_state == 3'h6; // @[el2_ifu_mem_ctl.scala 323:105]
|
||||
wire _T_206 = _T_204 | _T_205; // @[el2_ifu_mem_ctl.scala 323:91]
|
||||
wire ic_iccm_hit_f = fetch_req_iccm_f & _T_206; // @[el2_ifu_mem_ctl.scala 323:41]
|
||||
wire _T_211 = _T_219 & fetch_req_icache_f; // @[el2_ifu_mem_ctl.scala 329:39]
|
||||
wire ic_act_hit_f = _T_211 & _T_204; // @[el2_ifu_mem_ctl.scala 329:78]
|
||||
wire _T_304 = _T_165 & flush_final_f; // @[el2_ifu_mem_ctl.scala 366:87]
|
||||
wire _T_305 = ~_T_304; // @[el2_ifu_mem_ctl.scala 366:55]
|
||||
wire ifc_fetch_req_qual_bf = io_ifc_fetch_req_bf & _T_305; // @[el2_ifu_mem_ctl.scala 366:53]
|
||||
reg ifc_region_acc_fault_f; // @[el2_ifu_mem_ctl.scala 372:39]
|
||||
wire _T_1179 = |io_ic_eccerr; // @[el2_ifu_mem_ctl.scala 391:56]
|
||||
reg [70:0] _T_1192; // @[el2_ifu_mem_ctl.scala 397:37]
|
||||
wire [1:0] _T_1256 = ifc_region_acc_fault_f ? 2'h2 : 2'h0; // @[el2_ifu_mem_ctl.scala 429:8]
|
||||
rvclkhdr rvclkhdr ( // @[el2_lib.scala 412:22]
|
||||
.io_clk(rvclkhdr_io_clk),
|
||||
.io_en(rvclkhdr_io_en),
|
||||
.io_scan_mode(rvclkhdr_io_scan_mode)
|
||||
);
|
||||
rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 412:22]
|
||||
.io_clk(rvclkhdr_1_io_clk),
|
||||
.io_en(rvclkhdr_1_io_en),
|
||||
.io_scan_mode(rvclkhdr_1_io_scan_mode)
|
||||
);
|
||||
assign io_ifu_miss_state_idle = 1'h0; // @[el2_ifu_mem_ctl.scala 131:25]
|
||||
assign io_ifu_ic_mb_empty = 1'h0; // @[el2_ifu_mem_ctl.scala 132:21]
|
||||
assign io_ic_dma_active = io_dec_tlu_flush_err_wb; // @[el2_ifu_mem_ctl.scala 133:19 el2_ifu_mem_ctl.scala 241:20]
|
||||
assign io_ic_write_stall = 1'h0; // @[el2_ifu_mem_ctl.scala 134:20]
|
||||
assign io_ifu_pmu_ic_miss = 1'h0; // @[el2_ifu_mem_ctl.scala 135:21]
|
||||
assign io_ifu_pmu_ic_hit = 1'h0; // @[el2_ifu_mem_ctl.scala 136:20]
|
||||
assign io_ifu_pmu_bus_error = 1'h0; // @[el2_ifu_mem_ctl.scala 137:23]
|
||||
assign io_ifu_pmu_bus_busy = 1'h0; // @[el2_ifu_mem_ctl.scala 138:22]
|
||||
assign io_ifu_pmu_bus_trxn = 1'h0; // @[el2_ifu_mem_ctl.scala 139:22]
|
||||
assign io_ifu_axi_awvalid = 1'h0; // @[el2_ifu_mem_ctl.scala 140:21]
|
||||
assign io_ifu_axi_awid = 3'h0; // @[el2_ifu_mem_ctl.scala 141:18]
|
||||
assign io_ifu_axi_awaddr = 32'h0; // @[el2_ifu_mem_ctl.scala 142:20]
|
||||
assign io_ifu_axi_awregion = 4'h0; // @[el2_ifu_mem_ctl.scala 201:22]
|
||||
assign io_ifu_axi_awlen = 8'h0; // @[el2_ifu_mem_ctl.scala 143:19]
|
||||
assign io_ifu_axi_awsize = 3'h0; // @[el2_ifu_mem_ctl.scala 144:20]
|
||||
assign io_ifu_axi_awburst = 2'h0; // @[el2_ifu_mem_ctl.scala 145:21]
|
||||
assign io_ifu_axi_awlock = 1'h0; // @[el2_ifu_mem_ctl.scala 146:20]
|
||||
assign io_ifu_axi_awcache = 4'h0; // @[el2_ifu_mem_ctl.scala 147:21]
|
||||
assign io_ifu_axi_awprot = 3'h0; // @[el2_ifu_mem_ctl.scala 148:20]
|
||||
assign io_ifu_axi_awqos = 4'h0; // @[el2_ifu_mem_ctl.scala 149:19]
|
||||
assign io_ifu_axi_wvalid = 1'h0; // @[el2_ifu_mem_ctl.scala 150:20]
|
||||
assign io_ifu_axi_wdata = 64'h0; // @[el2_ifu_mem_ctl.scala 151:19]
|
||||
assign io_ifu_axi_wstrb = 8'h0; // @[el2_ifu_mem_ctl.scala 152:19]
|
||||
assign io_ifu_axi_wlast = 1'h0; // @[el2_ifu_mem_ctl.scala 153:19]
|
||||
assign io_ifu_axi_bready = 1'h0; // @[el2_ifu_mem_ctl.scala 154:20]
|
||||
assign io_ifu_axi_arvalid = 1'h0; // @[el2_ifu_mem_ctl.scala 155:21]
|
||||
assign io_ifu_axi_arid = 3'h0; // @[el2_ifu_mem_ctl.scala 157:18]
|
||||
assign io_ifu_axi_araddr = 32'h0; // @[el2_ifu_mem_ctl.scala 158:20]
|
||||
assign io_ifu_axi_arregion = 4'h0; // @[el2_ifu_mem_ctl.scala 159:22]
|
||||
assign io_ifu_axi_arlen = 8'h0; // @[el2_ifu_mem_ctl.scala 160:19]
|
||||
assign io_ifu_axi_arsize = 3'h0; // @[el2_ifu_mem_ctl.scala 161:20]
|
||||
assign io_ifu_axi_arburst = 2'h0; // @[el2_ifu_mem_ctl.scala 162:21]
|
||||
assign io_ifu_axi_arlock = 1'h0; // @[el2_ifu_mem_ctl.scala 163:20]
|
||||
assign io_ifu_axi_arcache = 4'h0; // @[el2_ifu_mem_ctl.scala 164:21]
|
||||
assign io_ifu_axi_arprot = 3'h0; // @[el2_ifu_mem_ctl.scala 165:20]
|
||||
assign io_ifu_axi_arqos = 4'h0; // @[el2_ifu_mem_ctl.scala 166:19]
|
||||
assign io_ifu_axi_rready = 1'h0; // @[el2_ifu_mem_ctl.scala 167:20]
|
||||
assign io_iccm_dma_ecc_error = 1'h0; // @[el2_ifu_mem_ctl.scala 168:24]
|
||||
assign io_iccm_dma_rvalid = 1'h0; // @[el2_ifu_mem_ctl.scala 169:21]
|
||||
assign io_iccm_dma_rdata = 64'h0; // @[el2_ifu_mem_ctl.scala 170:20]
|
||||
assign io_iccm_dma_rtag = 3'h0; // @[el2_ifu_mem_ctl.scala 171:19]
|
||||
assign io_iccm_ready = 1'h0; // @[el2_ifu_mem_ctl.scala 172:16]
|
||||
assign io_ic_rw_addr = 31'h0; // @[el2_ifu_mem_ctl.scala 173:16]
|
||||
assign io_ic_wr_en = 2'h0; // @[el2_ifu_mem_ctl.scala 174:14]
|
||||
assign io_ic_rd_en = 1'h0; // @[el2_ifu_mem_ctl.scala 175:14]
|
||||
assign io_ic_wr_data_0 = 71'h0; // @[el2_ifu_mem_ctl.scala 176:16 el2_ifu_mem_ctl.scala 388:17]
|
||||
assign io_ic_wr_data_1 = 71'h0; // @[el2_ifu_mem_ctl.scala 176:16 el2_ifu_mem_ctl.scala 388:17]
|
||||
assign io_ic_debug_wr_data = io_dec_tlu_ic_diag_pkt_icache_wrdata; // @[el2_ifu_mem_ctl.scala 177:22 el2_ifu_mem_ctl.scala 389:23]
|
||||
assign io_ifu_ic_debug_rd_data = _T_1192; // @[el2_ifu_mem_ctl.scala 178:26 el2_ifu_mem_ctl.scala 397:27]
|
||||
assign io_ic_debug_addr = 10'h0; // @[el2_ifu_mem_ctl.scala 156:19]
|
||||
assign io_ic_debug_rd_en = 1'h0; // @[el2_ifu_mem_ctl.scala 128:20]
|
||||
assign io_ic_debug_wr_en = 1'h0; // @[el2_ifu_mem_ctl.scala 129:20]
|
||||
assign io_ic_debug_tag_array = 1'h0; // @[el2_ifu_mem_ctl.scala 130:24]
|
||||
assign io_ic_debug_way = 2'h0; // @[el2_ifu_mem_ctl.scala 200:18]
|
||||
assign io_ic_tag_valid = 2'h0; // @[el2_ifu_mem_ctl.scala 179:18]
|
||||
assign io_iccm_rw_addr = 15'h0; // @[el2_ifu_mem_ctl.scala 180:18]
|
||||
assign io_iccm_wren = 1'h0; // @[el2_ifu_mem_ctl.scala 181:15]
|
||||
assign io_iccm_rden = 1'h0; // @[el2_ifu_mem_ctl.scala 182:15]
|
||||
assign io_iccm_wr_data = 78'h0; // @[el2_ifu_mem_ctl.scala 183:18]
|
||||
assign io_iccm_wr_size = 3'h0; // @[el2_ifu_mem_ctl.scala 184:18]
|
||||
assign io_ic_hit_f = ic_act_hit_f | ic_iccm_hit_f; // @[el2_ifu_mem_ctl.scala 185:14 el2_ifu_mem_ctl.scala 336:15]
|
||||
assign io_ic_access_fault_f = 1'h0; // @[el2_ifu_mem_ctl.scala 186:23 el2_ifu_mem_ctl.scala 427:24]
|
||||
assign io_ic_access_fault_type_f = io_iccm_rd_ecc_double_err ? 2'h1 : _T_1256; // @[el2_ifu_mem_ctl.scala 187:28 el2_ifu_mem_ctl.scala 428:29]
|
||||
assign io_iccm_rd_ecc_single_err = 1'h0; // @[el2_ifu_mem_ctl.scala 188:28]
|
||||
assign io_iccm_rd_ecc_double_err = 1'h0; // @[el2_ifu_mem_ctl.scala 189:28]
|
||||
assign io_ic_error_start = _T_1179 & ic_act_hit_f; // @[el2_ifu_mem_ctl.scala 190:20 el2_ifu_mem_ctl.scala 391:21]
|
||||
assign io_ifu_async_error_start = io_iccm_rd_ecc_single_err | io_ic_error_start; // @[el2_ifu_mem_ctl.scala 191:27 el2_ifu_mem_ctl.scala 240:28]
|
||||
assign io_iccm_dma_sb_error = 1'h0; // @[el2_ifu_mem_ctl.scala 192:23 el2_ifu_mem_ctl.scala 239:24]
|
||||
assign io_ic_fetch_val_f = 2'h0; // @[el2_ifu_mem_ctl.scala 193:20]
|
||||
assign io_ic_data_f = 32'h0; // @[el2_ifu_mem_ctl.scala 194:15]
|
||||
assign io_ic_premux_data = 64'h0; // @[el2_ifu_mem_ctl.scala 195:20]
|
||||
assign io_ic_sel_premux_data = 1'h0; // @[el2_ifu_mem_ctl.scala 196:24]
|
||||
assign io_ifu_ic_debug_rd_data_valid = 1'h0; // @[el2_ifu_mem_ctl.scala 197:32]
|
||||
assign io_iccm_buf_correct_ecc = 1'h0; // @[el2_ifu_mem_ctl.scala 198:26]
|
||||
assign io_iccm_correction_state = 1'h0; // @[el2_ifu_mem_ctl.scala 199:27]
|
||||
assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 413:17]
|
||||
assign rvclkhdr_io_en = io_ic_debug_rd_en | io_ic_debug_wr_en; // @[el2_lib.scala 414:16]
|
||||
assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 415:23]
|
||||
assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 413:17]
|
||||
assign rvclkhdr_1_io_en = _T_1 | io_exu_flush_final; // @[el2_lib.scala 414:16]
|
||||
assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 415:23]
|
||||
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
||||
`define RANDOMIZE
|
||||
`endif
|
||||
`ifdef RANDOMIZE_INVALID_ASSIGN
|
||||
`define RANDOMIZE
|
||||
`endif
|
||||
`ifdef RANDOMIZE_REG_INIT
|
||||
`define RANDOMIZE
|
||||
`endif
|
||||
`ifdef RANDOMIZE_MEM_INIT
|
||||
`define RANDOMIZE
|
||||
`endif
|
||||
`ifndef RANDOM
|
||||
`define RANDOM $random
|
||||
`endif
|
||||
`ifdef RANDOMIZE_MEM_INIT
|
||||
integer initvar;
|
||||
`endif
|
||||
`ifndef SYNTHESIS
|
||||
`ifdef FIRRTL_BEFORE_INITIAL
|
||||
`FIRRTL_BEFORE_INITIAL
|
||||
`endif
|
||||
initial begin
|
||||
`ifdef RANDOMIZE
|
||||
`ifdef INIT_RANDOM
|
||||
`INIT_RANDOM
|
||||
`endif
|
||||
`ifndef VERILATOR
|
||||
`ifdef RANDOMIZE_DELAY
|
||||
#`RANDOMIZE_DELAY begin end
|
||||
`else
|
||||
#0.002 begin end
|
||||
`endif
|
||||
`endif
|
||||
`ifdef RANDOMIZE_REG_INIT
|
||||
_RAND_0 = {1{`RANDOM}};
|
||||
flush_final_f = _RAND_0[0:0];
|
||||
_RAND_1 = {1{`RANDOM}};
|
||||
ifc_fetch_req_f_raw = _RAND_1[0:0];
|
||||
_RAND_2 = {1{`RANDOM}};
|
||||
miss_state = _RAND_2[2:0];
|
||||
_RAND_3 = {1{`RANDOM}};
|
||||
ifc_iccm_access_f = _RAND_3[0:0];
|
||||
_RAND_4 = {1{`RANDOM}};
|
||||
uncacheable_miss_ff = _RAND_4[0:0];
|
||||
_RAND_5 = {1{`RANDOM}};
|
||||
imb_ff = _RAND_5[30:0];
|
||||
_RAND_6 = {1{`RANDOM}};
|
||||
ifu_fetch_addr_int_f = _RAND_6[30:0];
|
||||
_RAND_7 = {1{`RANDOM}};
|
||||
ifc_region_acc_fault_f = _RAND_7[0:0];
|
||||
_RAND_8 = {3{`RANDOM}};
|
||||
_T_1192 = _RAND_8[70:0];
|
||||
`endif // RANDOMIZE_REG_INIT
|
||||
`endif // RANDOMIZE
|
||||
end // initial
|
||||
`ifdef FIRRTL_AFTER_INITIAL
|
||||
`FIRRTL_AFTER_INITIAL
|
||||
`endif
|
||||
`endif // SYNTHESIS
|
||||
always @(posedge clock) begin
|
||||
if (reset) begin
|
||||
flush_final_f <= 1'h0;
|
||||
end else begin
|
||||
flush_final_f <= io_exu_flush_final;
|
||||
end
|
||||
if (reset) begin
|
||||
ifc_fetch_req_f_raw <= 1'h0;
|
||||
end else begin
|
||||
ifc_fetch_req_f_raw <= ifc_fetch_req_qual_bf;
|
||||
end
|
||||
if (reset) begin
|
||||
miss_state <= 3'h0;
|
||||
end else if (miss_state_en) begin
|
||||
if (_T_26) begin
|
||||
if (_T_28) begin
|
||||
miss_state <= 3'h1;
|
||||
end else begin
|
||||
miss_state <= 3'h2;
|
||||
end
|
||||
end else if (_T_33) begin
|
||||
if (io_dec_tlu_force_halt) begin
|
||||
miss_state <= 3'h0;
|
||||
end else if (_T_74) begin
|
||||
miss_state <= 3'h2;
|
||||
end else begin
|
||||
miss_state <= 3'h0;
|
||||
end
|
||||
end else if (_T_94) begin
|
||||
miss_state <= 3'h0;
|
||||
end else if (_T_98) begin
|
||||
if (_T_105) begin
|
||||
miss_state <= 3'h2;
|
||||
end else begin
|
||||
miss_state <= 3'h0;
|
||||
end
|
||||
end else if (_T_113) begin
|
||||
if (_T_118) begin
|
||||
miss_state <= 3'h2;
|
||||
end else begin
|
||||
miss_state <= 3'h0;
|
||||
end
|
||||
end else if (_T_124) begin
|
||||
if (_T_129) begin
|
||||
miss_state <= 3'h5;
|
||||
end else if (_T_135) begin
|
||||
miss_state <= 3'h7;
|
||||
end else begin
|
||||
miss_state <= 3'h0;
|
||||
end
|
||||
end else if (_T_143) begin
|
||||
if (io_dec_tlu_force_halt) begin
|
||||
miss_state <= 3'h0;
|
||||
end else if (io_exu_flush_final) begin
|
||||
miss_state <= 3'h2;
|
||||
end else begin
|
||||
miss_state <= 3'h1;
|
||||
end
|
||||
end else if (_T_152) begin
|
||||
if (io_dec_tlu_force_halt) begin
|
||||
miss_state <= 3'h0;
|
||||
end else if (io_exu_flush_final) begin
|
||||
miss_state <= 3'h2;
|
||||
end else begin
|
||||
miss_state <= 3'h0;
|
||||
end
|
||||
end else begin
|
||||
miss_state <= 3'h0;
|
||||
end
|
||||
end
|
||||
if (reset) begin
|
||||
ifc_iccm_access_f <= 1'h0;
|
||||
end else begin
|
||||
ifc_iccm_access_f <= io_ifc_iccm_access_bf;
|
||||
end
|
||||
if (reset) begin
|
||||
uncacheable_miss_ff <= 1'h0;
|
||||
end else if (!(sel_hold_imb)) begin
|
||||
uncacheable_miss_ff <= io_ifc_fetch_uncacheable_bf;
|
||||
end
|
||||
if (!(sel_hold_imb)) begin
|
||||
imb_ff <= io_ifc_fetch_addr_bf;
|
||||
end
|
||||
if (reset) begin
|
||||
ifu_fetch_addr_int_f <= 31'h0;
|
||||
end else begin
|
||||
ifu_fetch_addr_int_f <= io_ifc_fetch_addr_bf;
|
||||
end
|
||||
if (reset) begin
|
||||
ifc_region_acc_fault_f <= 1'h0;
|
||||
end else begin
|
||||
ifc_region_acc_fault_f <= io_ifc_region_acc_fault_bf;
|
||||
end
|
||||
if (reset) begin
|
||||
_T_1192 <= 71'h0;
|
||||
end else begin
|
||||
_T_1192 <= io_ic_debug_rd_data;
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -25,7 +25,7 @@ class el2_ifu_aln_ctl extends Module with el2_lib {
|
|||
val dec_i0_decode_d = Input(Bool())
|
||||
val ifu_fetch_data_f = Input(UInt(32.W))
|
||||
val ifu_fetch_val = Input(UInt(2.W))
|
||||
val ifu_fetch_pc = Input(UInt(32.W))
|
||||
val ifu_fetch_pc = Input(UInt(31.W))
|
||||
val ifu_i0_valid = Output(Bool())
|
||||
val ifu_i0_icaf = Output(Bool())
|
||||
val ifu_i0_icaf_type = Output(UInt(2.W))
|
||||
|
|
@ -84,12 +84,37 @@ class el2_ifu_aln_ctl extends Module with el2_lib {
|
|||
val brdata0 = WireInit(UInt(12.W), init = 0.U)
|
||||
val brdata2 = WireInit(UInt(12.W), init = 0.U)
|
||||
|
||||
val f1pc_in = WireInit(UInt(31.W), 0.U)
|
||||
val f0pc_in = WireInit(UInt(31.W), 0.U)
|
||||
val error_stall = WireInit(Bool(), 0.U)
|
||||
|
||||
|
||||
val error_stall = withClock(io.active_clk) {RegNext(error_stall_in, init = 0.U)}
|
||||
val f0val = withClock(io.active_clk) {RegNext(f0val_in, init = 0.U)}
|
||||
error_stall_in := (error_stall | io.ifu_async_error_start) & !io.exu_flush_final
|
||||
|
||||
error_stall := withClock(io.active_clk) {RegNext(error_stall_in, init = 0.U)}
|
||||
val wrptr = withClock(io.active_clk) {RegNext(wrptr_in, init = 0.U)}
|
||||
val rdptr = withClock(io.active_clk) {RegNext(wrptr_in, init = 0.U)}
|
||||
|
||||
val f2val = withClock(io.active_clk) {RegNext(f2val_in, init = 0.U)}
|
||||
val f1val = withClock(io.active_clk) {RegNext(f1val_in, init = 0.U)}
|
||||
val f0val = withClock(io.active_clk) {RegNext(f0val_in, init = 0.U)}
|
||||
|
||||
val q2off = withClock(io.active_clk) {RegNext(q2off_in, init = 0.U)}
|
||||
val q1off = withClock(io.active_clk) {RegNext(q1off_in, init = 0.U)}
|
||||
val q0off = withClock(io.active_clk) {RegNext(q0off_in, init = 0.U)}
|
||||
|
||||
val f2pc = RegEnable(io.ifu_fetch_pc, 0.U, f2_wr_en.asBool)
|
||||
val f1pc = RegEnable(f1pc_in, 0.U, f1_shift_wr_en.asBool)
|
||||
val f0pc = RegEnable(f0pc_in, 0.U, f0_shift_wr_en.asBool)
|
||||
|
||||
brdata2 := RegEnable(brdata_in, 0.U, qwen(2))
|
||||
brdata1 := RegEnable(brdata_in, 0.U, qwen(1))
|
||||
brdata0 := RegEnable(brdata_in, 0.U, qwen(0))
|
||||
|
||||
misc2 := RegEnable(misc_data_in, 0.U, qwen(2))
|
||||
misc1 := RegEnable(misc_data_in, 0.U, qwen(1))
|
||||
misc0 := RegEnable(misc_data_in, 0.U, qwen(0))
|
||||
|
||||
|
||||
val i0_shift = io.dec_i0_decode_d & ~error_stall
|
||||
|
||||
io.ifu_pmu_instr_aligned := i0_shift
|
||||
|
|
@ -120,16 +145,10 @@ class el2_ifu_aln_ctl extends Module with el2_lib {
|
|||
val f0_shift_2B = Mux1H(Seq(shift_2B.asBool -> f0val(0), shift_4B.asBool -> (!f0val(0) & f0val(0))))
|
||||
val f1_shift_2B = f0val(0) & !f0val(1) & shift_4B
|
||||
|
||||
val wrptr = withClock(io.active_clk) {RegNext(wrptr_in, init = 0.U)}
|
||||
val rdptr = withClock(io.active_clk) {RegNext(wrptr_in, init = 0.U)}
|
||||
|
||||
val f2val = withClock(io.active_clk) {RegNext(f2val_in, init = 0.U)}
|
||||
val f1val = withClock(io.active_clk) {RegNext(f1val_in, init = 0.U)}
|
||||
|
||||
|
||||
val q2off = withClock(io.active_clk) {RegNext(q2off_in, init = 0.U)}
|
||||
val q1off = withClock(io.active_clk) {RegNext(q1off_in, init = 0.U)}
|
||||
val q0off = withClock(io.active_clk) {RegNext(q0off_in, init = 0.U)}
|
||||
|
||||
|
||||
|
||||
val fetch_to_f0 = !sf0_valid & !sf1_valid & !f2_valid & ifvalid
|
||||
val fetch_to_f1 = (!sf0_valid & !sf1_valid & f2_valid & ifvalid) |
|
||||
|
|
@ -259,18 +278,18 @@ class el2_ifu_aln_ctl extends Module with el2_lib {
|
|||
shift_f2_f0 := !sf0_valid & !sf1_valid & f2_valid
|
||||
shift_f2_f1 := !sf0_valid & sf1_valid & f2_valid
|
||||
|
||||
val f0pc = WireInit(UInt(31.W), 0.U)
|
||||
val f2pc = WireInit(UInt(31.W), 0.U)
|
||||
//val f0pc = WireInit(UInt(31.W), 0.U)
|
||||
// val f2pc = WireInit(UInt(31.W), 0.U)
|
||||
|
||||
val f0pc_plus1 = f0pc + 1.U
|
||||
|
||||
val sf1pc = (Fill(31, f1_shift_2B) & f0pc_plus1) | (Fill(31, !f1_shift_2B) & f0pc)
|
||||
|
||||
val f1pc_in = Mux1H(Seq(fetch_to_f1.asBool->io.ifu_fetch_pc,
|
||||
f1pc_in := Mux1H(Seq(fetch_to_f1.asBool->io.ifu_fetch_pc,
|
||||
shift_f2_f1.asBool->f2pc,
|
||||
(!fetch_to_f1 & !shift_f2_f1).asBool -> sf1pc))
|
||||
|
||||
val f0pc_in = Mux1H(Seq(fetch_to_f0.asBool->io.ifu_fetch_pc,
|
||||
f0pc_in := Mux1H(Seq(fetch_to_f0.asBool->io.ifu_fetch_pc,
|
||||
shift_f2_f0.asBool->f2pc,
|
||||
shift_f1_f0.asBool->sf1pc,
|
||||
(!fetch_to_f0 & !shift_f2_f0 & !shift_f1_f0).asBool->f0pc_plus1))
|
||||
|
|
@ -313,7 +332,7 @@ class el2_ifu_aln_ctl extends Module with el2_lib {
|
|||
|
||||
val alignfromf1 = !f0val(1) & f0val(0)
|
||||
|
||||
val f1pc = WireInit(UInt(31.W), init = 0.U)
|
||||
//val f1pc = WireInit(UInt(31.W), init = 0.U)
|
||||
|
||||
val secondpc = Mux1H(Seq(f0val(1).asBool()->f0pc_plus1 , (!f0val(1) & f0val(0)).asBool->f1pc))
|
||||
|
||||
|
|
@ -364,21 +383,13 @@ class el2_ifu_aln_ctl extends Module with el2_lib {
|
|||
|
||||
io.ifu_i0_bp_btag := Mux((first2B | alignbrend(0)).asBool, firstbrtag_hash, secondbrtag_hash)
|
||||
|
||||
brdata2 := RegEnable(brdata_in, 0.U, qwen(2))
|
||||
brdata1 := RegEnable(brdata_in, 0.U, qwen(1))
|
||||
brdata0 := RegEnable(brdata_in, 0.U, qwen(0))
|
||||
|
||||
misc2 := RegEnable(misc_data_in, 0.U, qwen(2))
|
||||
misc1 := RegEnable(misc_data_in, 0.U, qwen(1))
|
||||
misc0 := RegEnable(misc_data_in, 0.U, qwen(0))
|
||||
|
||||
q2 := RegEnable(io.ifu_fetch_data_f, 0.U, qwen(2))
|
||||
q1 := RegEnable(io.ifu_fetch_data_f, 0.U, qwen(1))
|
||||
q0 := RegEnable(io.ifu_fetch_data_f, 0.U, qwen(0))
|
||||
|
||||
f2pc := RegEnable(io.ifu_fetch_pc, 0.U, f2_wr_en.asBool)
|
||||
f2pc := RegEnable(f1pc_in, 0.U, f1_shift_wr_en.asBool)
|
||||
f2pc := RegEnable(f0pc_in, 0.U, f0_shift_wr_en.asBool)
|
||||
|
||||
}
|
||||
object ifu_aln extends App {
|
||||
println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu_aln_ctl()))
|
||||
|
|
|
|||
|
|
@ -215,12 +215,23 @@ class el2_ifu_mem_ctl extends Module with el2_lib {
|
|||
val err_stop_fetch = WireInit(Bool(), 0.U)
|
||||
val miss_state = WireInit(UInt(3.W), 0.U)
|
||||
val miss_nxtstate = WireInit(UInt(3.W), 0.U)
|
||||
val miss_state_en = WireInit(Bool(), 0.U)
|
||||
val ifu_bus_rsp_valid = WireInit(Bool(), 0.U)
|
||||
val bus_ifu_bus_clk_en = WireInit(Bool(), 0.U)
|
||||
val ifu_bus_rsp_ready = WireInit(Bool(), 0.U)
|
||||
val uncacheable_miss_ff = WireInit(Bool(), 0.U)
|
||||
val ic_act_miss_f = WireInit(Bool(), 0.U)
|
||||
val ic_byp_hit_f = WireInit(Bool(), 0.U)
|
||||
val bus_new_data_beat_count = WireInit(UInt(ICACHE_BEAT_BITS.W), 0.U)
|
||||
val bus_ifu_wr_en_ff = WireInit(Bool(), 0.U)
|
||||
val last_beat = WireInit(Bool(), 0.U)
|
||||
val last_data_recieved_ff = WireInit(Bool(), 0.U)
|
||||
//val flush_final_f = WireInit(Bool(), 0.U)
|
||||
val stream_eol_f = WireInit(Bool(), 0.U)
|
||||
val ic_miss_under_miss_f = WireInit(Bool(), 0.U)
|
||||
val ic_ignore_2nd_miss_f = WireInit(Bool(), 0.U)
|
||||
|
||||
val flush_final_f = RegNext(io.exu_flush_final, 0.U)
|
||||
val fetch_bf_f_c1_clken = io.ifc_fetch_req_bf_raw | ifc_fetch_req_f | miss_pending | io.exu_flush_final | scnd_miss_req
|
||||
val debug_c1_clken = io.ic_debug_rd_en | io.ic_debug_wr_en
|
||||
val debug_c1_clk = rvclkhdr(clock, debug_c1_clken, io.scan_mode)
|
||||
|
|
@ -233,7 +244,194 @@ class el2_ifu_mem_ctl extends Module with el2_lib {
|
|||
|
||||
val ifu_bp_hit_taken_q_f = io.ifu_bp_hit_taken_f & io.ic_hit_f
|
||||
|
||||
switch(miss_state){
|
||||
is (idle_C){
|
||||
miss_nxtstate := Mux((ic_act_miss_f & !io.exu_flush_final).asBool, crit_byp_ok_C, hit_u_miss_C)
|
||||
miss_state_en := ic_act_miss_f & !io.dec_tlu_force_halt}
|
||||
is (crit_byp_ok_C){
|
||||
miss_nxtstate := Mux((io.dec_tlu_force_halt | ic_byp_hit_f & (last_data_recieved_ff | (bus_ifu_wr_en_ff & last_beat)) & uncacheable_miss_ff).asBool, idle_C,
|
||||
Mux((ic_byp_hit_f & !last_data_recieved_ff & uncacheable_miss_ff).asBool, miss_wait_C,
|
||||
Mux((!ic_byp_hit_f & !io.exu_flush_final & (bus_ifu_wr_en_ff & last_beat) & uncacheable_miss_ff).asBool, crit_byp_ok_C,
|
||||
Mux(((bus_ifu_wr_en_ff & last_beat) & !uncacheable_miss_ff).asBool, idle_C,
|
||||
Mux(((ic_byp_hit_f | bus_ifu_wr_en_ff) & !io.exu_flush_final & !(bus_ifu_wr_en_ff & last_beat) & !ifu_bp_hit_taken_q_f & !uncacheable_miss_ff).asBool, stream_C,
|
||||
Mux((!ic_byp_hit_f & !io.exu_flush_final & (bus_ifu_wr_en_ff & last_beat) & !uncacheable_miss_ff).asBool, idle_C,
|
||||
Mux(((io.exu_flush_final | ifu_bp_hit_taken_q_f) & !(bus_ifu_wr_en_ff & last_beat)).asBool, hit_u_miss_C, idle_C)))))))
|
||||
miss_state_en := io.dec_tlu_force_halt | io.exu_flush_final | ic_byp_hit_f | ifu_bp_hit_taken_q_f | (bus_ifu_wr_en_ff & last_beat) | (bus_ifu_wr_en_ff & !uncacheable_miss_ff)
|
||||
}
|
||||
is (crit_wrd_rdy_C){
|
||||
miss_nxtstate := idle_C
|
||||
miss_state_en := io.exu_flush_final | flush_final_f | ic_byp_hit_f | io.dec_tlu_force_halt
|
||||
}
|
||||
is (stream_C){
|
||||
miss_nxtstate := Mux(((io.exu_flush_final | ifu_bp_hit_taken_q_f | stream_eol_f)&(!(bus_ifu_wr_en_ff & last_beat)) & !io.dec_tlu_force_halt).asBool, hit_u_miss_C, idle_C)
|
||||
miss_state_en := io.exu_flush_final | ifu_bp_hit_taken_q_f | stream_eol_f | (bus_ifu_wr_en_ff & last_beat) | io.dec_tlu_force_halt
|
||||
}
|
||||
is (miss_wait_C){
|
||||
miss_nxtstate := Mux((io.exu_flush_final & !(bus_ifu_wr_en_ff & last_beat) & !io.dec_tlu_force_halt).asBool, hit_u_miss_C, idle_C)
|
||||
miss_state_en := io.exu_flush_final | (bus_ifu_wr_en_ff & last_beat) | io.dec_tlu_force_halt
|
||||
}
|
||||
is (hit_u_miss_C){
|
||||
miss_nxtstate := Mux((ic_miss_under_miss_f & !(bus_ifu_wr_en_ff & last_beat) & !io.dec_tlu_force_halt).asBool, scnd_miss_C,
|
||||
Mux((ic_ignore_2nd_miss_f & !(bus_ifu_wr_en_ff & last_beat) & !io.dec_tlu_force_halt).asBool, stall_scnd_miss_C, idle_C))
|
||||
miss_state_en := (bus_ifu_wr_en_ff & last_beat) | ic_miss_under_miss_f | ic_ignore_2nd_miss_f | io.dec_tlu_force_halt
|
||||
}
|
||||
is (scnd_miss_C){
|
||||
miss_nxtstate := Mux(io.dec_tlu_force_halt, idle_C, Mux(io.exu_flush_final,
|
||||
Mux((bus_ifu_wr_en_ff & last_beat).asBool, idle_C, hit_u_miss_C), crit_byp_ok_C))
|
||||
miss_state_en := (bus_ifu_wr_en_ff & last_beat) | io.exu_flush_final | io.dec_tlu_force_halt
|
||||
}
|
||||
is (stall_scnd_miss_C){
|
||||
miss_nxtstate := Mux(io.dec_tlu_force_halt, idle_C, Mux(io.exu_flush_final,
|
||||
Mux((bus_ifu_wr_en_ff & last_beat).asBool, idle_C, hit_u_miss_C), idle_C))
|
||||
miss_state_en := (bus_ifu_wr_en_ff & last_beat) | io.exu_flush_final | io.dec_tlu_force_halt
|
||||
}
|
||||
}
|
||||
miss_state := RegEnable(miss_nxtstate, 0.U, miss_state_en.asBool)
|
||||
val crit_byp_hit_f = WireInit(Bool(), 0.U)
|
||||
val way_status_mb_scnd_ff = WireInit(UInt(ICACHE_STATUS_BITS.W), 0.U)
|
||||
val way_status = WireInit(UInt(ICACHE_STATUS_BITS.W), 0.U)
|
||||
val tagv_mb_scnd_ff = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U)
|
||||
val ic_tag_valid = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U)
|
||||
val uncacheable_miss_scnd_ff = WireInit(Bool(), 0.U)
|
||||
val imb_scnd_ff = WireInit(UInt(31.W), 0.U)
|
||||
val reset_all_tags = WireInit(Bool(), 0.U)
|
||||
val bus_rd_addr_count = WireInit(UInt(ICACHE_BEAT_BITS.W), 0.U)
|
||||
val ifu_bus_rid_ff = WireInit(UInt(ICACHE_BEAT_BITS.W), 0.U)
|
||||
miss_pending := miss_state =/= idle_C
|
||||
val crit_wd_byp_ok_ff = (miss_state === crit_byp_ok_C) | ((miss_state === crit_wrd_rdy_C) & !flush_final_f)
|
||||
val sel_hold_imb = (miss_pending & !(bus_ifu_wr_en_ff & last_beat) & !((miss_state === crit_wrd_rdy_C) & io.exu_flush_final) &
|
||||
!((miss_state === crit_wrd_rdy_C) & crit_byp_hit_f) ) | ic_act_miss_f |
|
||||
(miss_pending & (miss_nxtstate === crit_wrd_rdy_C))
|
||||
|
||||
val sel_hold_imb_scnd = ((miss_state === scnd_miss_C) | ic_miss_under_miss_f) & !flush_final_f
|
||||
val way_status_mb_scnd_in = Mux(miss_state === scnd_miss_C, way_status_mb_scnd_ff, way_status)
|
||||
|
||||
val tagv_mb_scnd_in = Mux(miss_state === scnd_miss_C, tagv_mb_scnd_ff, Fill(ICACHE_NUM_WAYS, !reset_all_tags) & ic_tag_valid)
|
||||
val uncacheable_miss_scnd_in = Mux(sel_hold_imb_scnd.asBool, uncacheable_miss_scnd_ff, io.ifc_fetch_uncacheable_bf)
|
||||
uncacheable_miss_scnd_ff := RegNext(uncacheable_miss_scnd_in, 0.U)
|
||||
val imb_scnd_in = Mux(sel_hold_imb_scnd.asBool, imb_scnd_ff, io.ifc_fetch_addr_bf)
|
||||
imb_scnd_ff := RegNext(imb_scnd_in, 0.U)
|
||||
way_status_mb_scnd_ff := RegNext(way_status_mb_scnd_in, 0.U)
|
||||
tagv_mb_scnd_ff := RegNext(tagv_mb_scnd_in, 0.U)
|
||||
|
||||
val ic_req_addr_bits_hi_3 = bus_rd_addr_count
|
||||
val ic_wr_addr_bits_hi_3 = ifu_bus_rid_ff & Fill(ICACHE_BEAT_BITS, bus_ifu_wr_en_ff)
|
||||
val ifc_iccm_access_f = WireInit(Bool(), 0.U)
|
||||
val ifc_region_acc_fault_final_f = WireInit(Bool(), 0.U)
|
||||
val fetch_req_icache_f = ifc_fetch_req_f & !ifc_iccm_access_f & !ifc_region_acc_fault_final_f
|
||||
val fetch_req_iccm_f = ifc_fetch_req_f & ifc_iccm_access_f
|
||||
val ic_iccm_hit_f = fetch_req_iccm_f & (!miss_pending | (miss_state === hit_u_miss_C) | (miss_state === stream_C))
|
||||
val stream_hit_f = WireInit(Bool(), 0.U)
|
||||
ic_byp_hit_f := (crit_byp_hit_f | stream_hit_f) & fetch_req_icache_f & miss_pending
|
||||
val sel_mb_addr_ff = WireInit(Bool(), 0.U)
|
||||
val imb_ff = WireInit(UInt(31.W), 0.U)
|
||||
val ifu_fetch_addr_int_f = WireInit(UInt(31.W), 0.U)
|
||||
val ic_act_hit_f = io.ic_rd_hit.orR & fetch_req_icache_f & !reset_all_tags & (!miss_pending | (miss_state===hit_u_miss_C)) & !sel_mb_addr_ff
|
||||
ic_act_miss_f := (((!io.ic_rd_hit.orR | reset_all_tags) & fetch_req_icache_f & !miss_pending) | scnd_miss_req) & !ifc_region_acc_fault_final_f
|
||||
ic_miss_under_miss_f := (!io.ic_rd_hit | reset_all_tags) & fetch_req_icache_f & (miss_state===hit_u_miss_C) &
|
||||
(imb_ff(30,ICACHE_TAG_INDEX_LO-1) =/= ifu_fetch_addr_int_f(30,ICACHE_TAG_INDEX_LO-1)) & !uncacheable_miss_ff & !sel_mb_addr_ff & !ifc_region_acc_fault_final_f
|
||||
ic_ignore_2nd_miss_f := (!io.ic_rd_hit.orR | reset_all_tags) & fetch_req_icache_f & (miss_state === hit_u_miss_C) &
|
||||
((imb_ff(30,ICACHE_TAG_INDEX_LO-1)===ifu_fetch_addr_int_f(30,ICACHE_TAG_INDEX_LO-1)) | uncacheable_miss_ff)
|
||||
// Output
|
||||
io.ic_hit_f := ic_act_hit_f | ic_byp_hit_f | ic_iccm_hit_f | (ifc_region_acc_fault_final_f & ifc_fetch_req_f)
|
||||
val uncacheable_miss_in = Mux(scnd_miss_req.asBool, uncacheable_miss_scnd_ff, Mux(sel_hold_imb.asBool, uncacheable_miss_ff, io.ifc_fetch_uncacheable_bf))
|
||||
val imb_in = Mux(scnd_miss_req.asBool, imb_scnd_ff, Mux(sel_hold_imb.asBool, imb_ff, io.ifc_fetch_addr_bf))
|
||||
val ifu_wr_cumulative_err_data = WireInit(Bool(), 0.U)
|
||||
val scnd_miss_index_match = (imb_ff(ICACHE_INDEX_HI,ICACHE_TAG_INDEX_LO)===imb_scnd_ff(ICACHE_INDEX_HI,ICACHE_TAG_INDEX_LO))& scnd_miss_req & !ifu_wr_cumulative_err_data
|
||||
val way_status_mb_ff = WireInit(UInt(ICACHE_STATUS_BITS.W), 0.U)
|
||||
val way_status_rep_new = WireInit(UInt(ICACHE_STATUS_BITS.W), 0.U)
|
||||
val way_status_mb_in = Mux((scnd_miss_req & !scnd_miss_index_match).asBool, way_status_mb_scnd_ff,
|
||||
Mux((scnd_miss_req & scnd_miss_index_match).asBool, way_status_rep_new,
|
||||
Mux(miss_pending.asBool, way_status_mb_ff, way_status)))
|
||||
val replace_way_mb_any = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U)
|
||||
val tagv_mb_ff = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U)
|
||||
val tagv_mb_in = Mux(scnd_miss_req.asBool, tagv_mb_scnd_ff | (Fill(ICACHE_NUM_WAYS, scnd_miss_index_match) & replace_way_mb_any),
|
||||
Mux(miss_pending.asBool, tagv_mb_ff, ic_tag_valid & Fill(ICACHE_NUM_WAYS, !reset_all_tags)))
|
||||
val scnd_miss_req_q = WireInit(Bool(), 0.U)
|
||||
val reset_ic_ff = WireInit(Bool(), 0.U)
|
||||
val reset_ic_in = miss_pending & !scnd_miss_req_q & (reset_all_tags | reset_ic_ff)
|
||||
reset_ic_ff := RegNext(reset_ic_in)
|
||||
val fetch_uncacheable_ff = RegNext(io.ifc_fetch_uncacheable_bf, 0.U)
|
||||
ifu_fetch_addr_int_f := RegNext(io.ifc_fetch_addr_bf, 0.U)
|
||||
val vaddr_f = ifu_fetch_addr_int_f
|
||||
uncacheable_miss_ff := RegNext(uncacheable_miss_in, 0.U)
|
||||
imb_ff := RegNext(imb_in)
|
||||
val miss_addr = WireInit(UInt((31-ICACHE_BEAT_ADDR_HI).W), 0.U)
|
||||
val miss_addr_in = Mux(!miss_pending, imb_ff(30, ICACHE_BEAT_ADDR_HI),
|
||||
Mux(scnd_miss_req_q.asBool, imb_scnd_ff(30, ICACHE_BEAT_ADDR_HI), miss_addr))
|
||||
miss_addr := RegNext(miss_addr_in, 0.U)
|
||||
way_status_mb_ff := RegNext(way_status_mb_in, 0.U)
|
||||
tagv_mb_ff := RegNext(tagv_mb_in, 0.U)
|
||||
val stream_miss_f = WireInit(Bool(), 0.U)
|
||||
val ifc_fetch_req_qual_bf = io.ifc_fetch_req_bf & !((miss_state===crit_wrd_rdy_C) & flush_final_f) & !stream_miss_f
|
||||
val ifc_fetch_req_f_raw = RegNext(ifc_fetch_req_qual_bf, 0.U)
|
||||
ifc_fetch_req_f := ifc_fetch_req_f_raw & !io.exu_flush_final
|
||||
ifc_iccm_access_f := RegNext(io.ifc_iccm_access_bf, 0.U)
|
||||
val ifc_region_acc_fault_final_bf = WireInit(Bool(), 0.U)
|
||||
ifc_region_acc_fault_final_f := RegNext(ifc_region_acc_fault_final_bf, 0.U)
|
||||
val ifc_region_acc_fault_f = RegNext(io.ifc_region_acc_fault_bf, 0.U)
|
||||
val ifu_ic_req_addr_f = Cat(miss_addr, ic_req_addr_bits_hi_3)
|
||||
val ifu_ic_mb_empty = (((miss_state===hit_u_miss_C) | (miss_state===stream_C)) & !(bus_ifu_wr_en_ff & last_beat)) | !miss_pending
|
||||
val ifu_miss_state_idle = miss_state === idle_C
|
||||
val write_ic_16_bytes = WireInit(Bool(), 0.U)
|
||||
val reset_tag_valid_for_miss = WireInit(Bool(), 0.U)
|
||||
val sel_mb_addr = (miss_pending & write_ic_16_bytes & !uncacheable_miss_ff) | reset_tag_valid_for_miss
|
||||
val ifu_ic_rw_int_addr = Mux1H(Seq(sel_mb_addr.asBool->Cat(imb_ff(30,ICACHE_BEAT_ADDR_HI) , ic_wr_addr_bits_hi_3 , imb_ff(1,0)),
|
||||
!sel_mb_addr.asBool->ifu_fetch_addr_int_f))
|
||||
val ic_rw_addr = ifu_ic_rw_int_addr
|
||||
sel_mb_addr_ff := withClock(io.free_clk){RegNext(sel_mb_addr, 0.U)}
|
||||
val ifu_bus_rdata_ff = WireInit(UInt(64.W), 0.U)
|
||||
val ic_miss_buff_half = WireInit(UInt(64.W), 0.U)
|
||||
val ic_wr_ecc = rvecc_encode_64(ifu_bus_rdata_ff)
|
||||
val ic_miss_buff_ecc = rvecc_encode_64(ic_miss_buff_half)
|
||||
val ic_wr_16bytes_data = WireInit(UInt((ICACHE_BANKS_WAY * (if(ICACHE_ECC) 71 else 68)).W), 0.U)
|
||||
io.ic_wr_data := (0 until ICACHE_BANKS_WAY).map(i=>ic_wr_16bytes_data((i*(if(ICACHE_ECC) 71 else 68))+(if(ICACHE_ECC) 70 else 67),(if(ICACHE_ECC) 71 else 68)*i))
|
||||
io.ic_debug_wr_data := io.dec_tlu_ic_diag_pkt.icache_wrdata
|
||||
val ic_rd_parity_final_err = WireInit(Bool(), 0.U)
|
||||
io.ic_error_start := ((if(ICACHE_ECC)io.ic_eccerr.orR()else io.ic_parerr.orR()) & ic_act_hit_f) | ic_rd_parity_final_err
|
||||
val ic_debug_tag_val_rd_out = WireInit(Bool(), 0.U)
|
||||
val ic_debug_ict_array_sel_ff = WireInit(Bool(), 0.U)
|
||||
val ifu_ic_debug_rd_data_in = Mux(ic_debug_ict_array_sel_ff.asBool, if(ICACHE_ECC) Cat(0.U(2.W),io.ictag_debug_rd_data(25,21),0.U(32.W),io.ictag_debug_rd_data(20,0), 0.U(7-ICACHE_STATUS_BITS), way_status, 0.U(3.W),ic_debug_tag_val_rd_out)
|
||||
else Cat(0.U(6.W),io.ictag_debug_rd_data(21),0.U(32.W),io.ictag_debug_rd_data(20,0),0.U(7-ICACHE_STATUS_BITS),way_status ,0.U(3.W) ,ic_debug_tag_val_rd_out) ,
|
||||
io.ic_debug_rd_data)
|
||||
io.ifu_ic_debug_rd_data := RegNext(ifu_ic_debug_rd_data_in, 0.U)
|
||||
val ic_wr_parity = (0 until 4).map(i=>rveven_paritygen(ifu_bus_rdata_ff((16*i)+15,16*i))).reverse.reduce(Cat(_,_))
|
||||
val ic_miss_buff_parity = (0 until 4).map(i=>rveven_paritygen(ic_miss_buff_half((16*i)+15,16*i))).reverse.reduce(Cat(_,_))
|
||||
|
||||
ic_wr_16bytes_data := Mux(ifu_bus_rid_ff(0).asBool,Cat(if(ICACHE_ECC)ic_wr_ecc else ic_wr_parity, ifu_bus_rdata_ff(63,0) , if(ICACHE_ECC)ic_miss_buff_ecc else ic_miss_buff_parity, ic_miss_buff_half(63,0)),
|
||||
Cat(if(ICACHE_ECC)ic_miss_buff_ecc else ic_miss_buff_parity, ic_miss_buff_half, if(ICACHE_ECC)ic_wr_ecc else ic_wr_parity, ifu_bus_rdata_ff))
|
||||
val bus_ifu_wr_data_error_ff = WireInit(Bool(), 0.U)
|
||||
val ifu_wr_data_comb_err_ff = WireInit(Bool(), 0.U)
|
||||
val reset_beat_cnt = WireInit(Bool(), 0.U)
|
||||
val ifu_wr_data_comb_err = bus_ifu_wr_data_error_ff
|
||||
val ifu_wr_cumulative_err = (ifu_wr_data_comb_err | ifu_wr_data_comb_err_ff) & !reset_beat_cnt
|
||||
ifu_wr_cumulative_err_data := ifu_wr_data_comb_err | ifu_wr_data_comb_err_ff
|
||||
ifu_wr_data_comb_err_ff := withClock(io.free_clk) {RegNext(ifu_wr_cumulative_err, 0.U)}
|
||||
val ic_crit_wd_rdy = WireInit(Bool(), 0.U)
|
||||
val ifu_byp_data_err_new = WireInit(Bool(), 0.U)
|
||||
val sel_byp_data = (ic_crit_wd_rdy | (miss_state===stream_C) | (miss_state===crit_byp_ok_C)) & !ifu_byp_data_err_new
|
||||
val sel_ic_data = !(ic_crit_wd_rdy | (miss_state===stream_C) | (miss_state===crit_byp_ok_C)) & !fetch_req_iccm_f
|
||||
val sel_iccm_data = fetch_req_iccm_f
|
||||
|
||||
val ic_byp_data_only_new = WireInit(UInt(80.W), 0.U)
|
||||
val ic_final_data = Mux1H(Seq((sel_byp_data | (if(ICCM_ICACHE) (sel_iccm_data | sel_ic_data) else if(ICACHE_ONLY) sel_ic_data else 0.U)).asBool->
|
||||
(if(ICCM_ICACHE) io.ic_rd_data else ic_byp_data_only_new(63,0))))
|
||||
val ic_premux_data = if(ICCM_ICACHE) (Fill(64,sel_iccm_data) & io.iccm_rd_data) | (Fill(64, sel_byp_data) & ic_byp_data_only_new)
|
||||
else if(ICACHE_ONLY) Fill(64, sel_byp_data) & ic_byp_data_only_new else 0.U
|
||||
val ic_sel_premux_data = if(ICCM_ICACHE) sel_iccm_data | sel_byp_data else if(ICACHE_ONLY) sel_byp_data else 0.U
|
||||
|
||||
val ifc_bus_acc_fault_f = ic_byp_hit_f & ifu_byp_data_err_new
|
||||
val ic_data_f = ic_final_data
|
||||
val fetch_req_f_qual = io.ic_hit_f & !io.exu_flush_final
|
||||
val ifc_region_acc_fault_memory_f = WireInit(Bool(), 0.U)
|
||||
io.ic_access_fault_f := (ifc_region_acc_fault_final_f | ifc_bus_acc_fault_f) & !io.exu_flush_final
|
||||
io.ic_access_fault_type_f := Mux(io.iccm_rd_ecc_double_err.asBool, 1.U,
|
||||
Mux(ifc_region_acc_fault_f.asBool, 2.U,
|
||||
Mux(ifc_region_acc_fault_memory_f.asBool(), 3.U, 0.U)))
|
||||
val ifu_bp_inst_mask_f = WireInit(Bool(), 0.U)
|
||||
io.ic_fetch_val_f := Cat(fetch_req_f_qual & ifu_bp_inst_mask_f & !(vaddr_f===Fill(ICACHE_BEAT_ADDR_HI,1.U)) & (err_stop_state=/=err_fetch2_C), fetch_req_f_qual)
|
||||
val two_byte_instr = ic_data_f(1,0) =/= 3.U
|
||||
//// Creating full buffer
|
||||
}
|
||||
object ifu_mem extends App {
|
||||
println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu_mem_ctl()))
|
||||
|
|
|
|||
|
|
@ -101,7 +101,7 @@ trait param {
|
|||
val ICCM_ICACHE = true //.U(1.W)
|
||||
val ICCM_INDEX_BITS = 0xC //.U(4.W)
|
||||
val ICCM_NUM_BANKS = 0x04 //.U(5.W)
|
||||
val ICCM_ONLY = 0x0 //.U(1.W)
|
||||
val ICCM_ONLY = false //.U(1.W)
|
||||
val ICCM_REGION = 0xE //.U(4.W)
|
||||
val ICCM_SADR = 0xEE000000L //.U(32.W)
|
||||
val ICCM_SIZE = 0x040 //.U(10.W)
|
||||
|
|
@ -141,7 +141,7 @@ trait param {
|
|||
val LSU_NUM_NBLOAD_WIDTH = 0x2 //.U(3.W)
|
||||
val LSU_SB_BITS = 0x10 //.U(5.W)
|
||||
val LSU_STBUF_DEPTH = 0x4 //.U(4.W)
|
||||
val NO_ICCM_NO_ICACHE = 0x0 //.U(1.W)
|
||||
val NO_ICCM_NO_ICACHE = false //.U(1.W)
|
||||
val PIC_2CYCLE = 0x0 //.U(1.W)
|
||||
val PIC_BASE_ADDR = 0xF00C0000 //.U(32.W)
|
||||
val PIC_BITS = 0x0F //.U(5.W)
|
||||
|
|
@ -160,6 +160,11 @@ trait param {
|
|||
trait el2_lib extends param{
|
||||
def repl(b:Int, a:UInt) = VecInit.tabulate(b)(i => a).reduce(Cat(_,_))
|
||||
|
||||
// IMC
|
||||
// def IMC =
|
||||
// (ICCM_ICACHE, ICCM_ONLY, ICACHE_ONLY, NO_ICCM_NO_ICACHE) match {
|
||||
// case ()
|
||||
// }
|
||||
|
||||
// Configuration Methods
|
||||
def MEM_CAL : (Int, Int, Int, Int)=
|
||||
|
|
@ -325,7 +330,7 @@ trait el2_lib extends param{
|
|||
var j = 0;var k = 0;var m = 0; var n =0;
|
||||
var x = 0;var y = 0;var z = 0
|
||||
|
||||
for(i <- 63 to 0)
|
||||
for(i <- 0 to 63)
|
||||
{
|
||||
if(mask0(i)==1) {w0(j) := din(i); j = j +1 }
|
||||
if(mask1(i)==1) {w1(k) := din(i); k = k +1 }
|
||||
|
|
|
|||
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@ -1 +0,0 @@
|
|||
val a = 5
|
||||
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Reference in New Issue