Bus-buffer testing start

el2_lsu_bus_buffer.anno.json

@@ -94,9 +94,9 @@
     "class":"firrtl.transforms.CombinationalPath",
     "sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_WrPtr1_m",
     "sources":[
-      "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ldst_dual_r",
       "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_busreq_r",
-      "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_busreq_m"
+      "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_busreq_m",
+      "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ldst_dual_r"
     ]
   },
   {

src/main/scala/lsu/el2_lsu_bus_buffer.scala

@@ -114,6 +114,7 @@ class  el2_lsu_bus_buffer extends Module with RequireAsyncReset with el2_lib {
     val WrPtr1_r = Output(UInt())
     val WrPtr1_m = Output(UInt())
     val wdata_in = Output(UInt())
+    val buf_state = Output(UInt())
   })
   def indexing(in : UInt, index : UInt) = Mux1H((0 until math.pow(2, index.getWidth).asInstanceOf[Int]).map(i=>(index===i.U)->in(i)))
   def indexing(in : Vec[UInt], index : UInt) = Mux1H((0 until math.pow(2, index.getWidth).asInstanceOf[Int]).map(i=>(index===i.U)->in(i)))
@@ -417,12 +418,19 @@ class  el2_lsu_bus_buffer extends Module with RequireAsyncReset with el2_lib {
   val obuf_data = rvdffe(obuf_data_in, obuf_wr_en, io.lsu_busm_clk, io.scan_mode)
   obuf_wr_timer := withClock(io.lsu_busm_clk){RegNext(obuf_wr_timer_in, 0.U)}
   val WrPtr0_m = WireInit(UInt(DEPTH_LOG2.W), 0.U)
+
   val found_array1 = (0 until DEPTH).map(i=>((buf_state(i)===idle_C) & !((ibuf_valid & (ibuf_tag===i.U)) |
-    (io.lsu_busreq_r & (WrPtr0_r===i.U)) | (io.ldst_dual_r & (WrPtr1_r === i.U))))->i.U)
+    (io.lsu_busreq_r & (WrPtr0_r === i.U)) |
+    (io.ldst_dual_r & (WrPtr1_r === i.U)))) -> i.U)
+
   WrPtr0_m := MuxCase(0.U, found_array1)
-  val found_array2 = (0 until DEPTH).map(i=>((buf_state(i)===idle_C) & !((ibuf_valid & (ibuf_tag===i.U)) |
+  io.buf_state := buf_state.reduce(Cat(_,_))
-    (io.lsu_busreq_m & (WrPtr0_m===i.U)) | (io.lsu_busreq_r & (WrPtr0_r === i.U)) | (io.ldst_dual_r & (WrPtr1_r===i.U))))->i.U)
+
-  val WrPtr1_m = MuxCase(0.U, found_array2)
+  val WrPtr1_m = MuxCase(0.U, (0 until DEPTH).map(i=>((buf_state(i)===idle_C) & !((ibuf_valid & (ibuf_tag===i.U)) |
+    (io.lsu_busreq_m & (WrPtr0_m===i.U)) |
+    (io.lsu_busreq_r & (((WrPtr0_r === i.U)) |
+      (io.ldst_dual_r & (WrPtr1_r===i.U))))))           ->  i.U))
+
   io.WrPtr1_m := WrPtr1_m
   val buf_age = Wire(Vec(DEPTH, UInt(DEPTH.W)))
   buf_age := buf_age.map(i=> 0.U)