Bus-buffer testing start
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@ -94,9 +94,9 @@
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"class":"firrtl.transforms.CombinationalPath",
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_WrPtr1_m",
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"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_WrPtr1_m",
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"sources":[
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"sources":[
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"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ldst_dual_r",
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"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_busreq_r",
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"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_busreq_r",
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"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_busreq_m"
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"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_busreq_m",
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"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ldst_dual_r"
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]
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]
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},
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},
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{
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{
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10350
el2_lsu_bus_buffer.fir
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el2_lsu_bus_buffer.fir
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4621
el2_lsu_bus_buffer.v
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el2_lsu_bus_buffer.v
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@ -114,6 +114,7 @@ class el2_lsu_bus_buffer extends Module with RequireAsyncReset with el2_lib {
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val WrPtr1_r = Output(UInt())
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val WrPtr1_r = Output(UInt())
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val WrPtr1_m = Output(UInt())
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val WrPtr1_m = Output(UInt())
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val wdata_in = Output(UInt())
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val wdata_in = Output(UInt())
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val buf_state = Output(UInt())
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})
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})
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def indexing(in : UInt, index : UInt) = Mux1H((0 until math.pow(2, index.getWidth).asInstanceOf[Int]).map(i=>(index===i.U)->in(i)))
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def indexing(in : UInt, index : UInt) = Mux1H((0 until math.pow(2, index.getWidth).asInstanceOf[Int]).map(i=>(index===i.U)->in(i)))
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def indexing(in : Vec[UInt], index : UInt) = Mux1H((0 until math.pow(2, index.getWidth).asInstanceOf[Int]).map(i=>(index===i.U)->in(i)))
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def indexing(in : Vec[UInt], index : UInt) = Mux1H((0 until math.pow(2, index.getWidth).asInstanceOf[Int]).map(i=>(index===i.U)->in(i)))
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@ -417,12 +418,19 @@ class el2_lsu_bus_buffer extends Module with RequireAsyncReset with el2_lib {
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val obuf_data = rvdffe(obuf_data_in, obuf_wr_en, io.lsu_busm_clk, io.scan_mode)
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val obuf_data = rvdffe(obuf_data_in, obuf_wr_en, io.lsu_busm_clk, io.scan_mode)
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obuf_wr_timer := withClock(io.lsu_busm_clk){RegNext(obuf_wr_timer_in, 0.U)}
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obuf_wr_timer := withClock(io.lsu_busm_clk){RegNext(obuf_wr_timer_in, 0.U)}
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val WrPtr0_m = WireInit(UInt(DEPTH_LOG2.W), 0.U)
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val WrPtr0_m = WireInit(UInt(DEPTH_LOG2.W), 0.U)
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val found_array1 = (0 until DEPTH).map(i=>((buf_state(i)===idle_C) & !((ibuf_valid & (ibuf_tag===i.U)) |
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val found_array1 = (0 until DEPTH).map(i=>((buf_state(i)===idle_C) & !((ibuf_valid & (ibuf_tag===i.U)) |
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(io.lsu_busreq_r & (WrPtr0_r===i.U)) | (io.ldst_dual_r & (WrPtr1_r === i.U))))->i.U)
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(io.lsu_busreq_r & (WrPtr0_r === i.U)) |
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(io.ldst_dual_r & (WrPtr1_r === i.U)))) -> i.U)
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WrPtr0_m := MuxCase(0.U, found_array1)
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WrPtr0_m := MuxCase(0.U, found_array1)
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val found_array2 = (0 until DEPTH).map(i=>((buf_state(i)===idle_C) & !((ibuf_valid & (ibuf_tag===i.U)) |
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io.buf_state := buf_state.reduce(Cat(_,_))
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(io.lsu_busreq_m & (WrPtr0_m===i.U)) | (io.lsu_busreq_r & (WrPtr0_r === i.U)) | (io.ldst_dual_r & (WrPtr1_r===i.U))))->i.U)
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val WrPtr1_m = MuxCase(0.U, found_array2)
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val WrPtr1_m = MuxCase(0.U, (0 until DEPTH).map(i=>((buf_state(i)===idle_C) & !((ibuf_valid & (ibuf_tag===i.U)) |
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(io.lsu_busreq_m & (WrPtr0_m===i.U)) |
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(io.lsu_busreq_r & (((WrPtr0_r === i.U)) |
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(io.ldst_dual_r & (WrPtr1_r===i.U)))))) -> i.U))
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io.WrPtr1_m := WrPtr1_m
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io.WrPtr1_m := WrPtr1_m
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val buf_age = Wire(Vec(DEPTH, UInt(DEPTH.W)))
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val buf_age = Wire(Vec(DEPTH, UInt(DEPTH.W)))
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buf_age := buf_age.map(i=> 0.U)
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buf_age := buf_age.map(i=> 0.U)
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