EXU integrated
This commit is contained in:
waleed-lm
parent
a3c6794072
commit
1f7988a179
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@ -0,0 +1,494 @@
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[
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_lsu|el2_lsu>io_dccm_dma_rdata",
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"sources":[
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"~el2_lsu|el2_lsu>io_picm_rd_data",
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"~el2_lsu|el2_lsu>io_dec_tlu_core_ecc_disable",
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"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
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"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
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"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_lsu|el2_lsu>io_lsu_single_ecc_error_incr",
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"sources":[
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"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r",
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"~el2_lsu|el2_lsu>io_dec_tlu_core_ecc_disable",
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"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
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"~el2_lsu|el2_lsu>io_dccm_rd_data_lo"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_lsu|el2_lsu>io_picm_rdaddr",
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"sources":[
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"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
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"~el2_lsu|el2_lsu>io_dma_mem_addr",
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"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
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"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
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"~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d",
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"~el2_lsu|el2_lsu>io_picm_rd_data",
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"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
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"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
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"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
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"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_lsu|el2_lsu>io_lsu_trigger_match_m",
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"sources":[
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"~el2_lsu|el2_lsu>io_trigger_pkt_any_0_store",
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"~el2_lsu|el2_lsu>io_trigger_pkt_any_1_store",
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"~el2_lsu|el2_lsu>io_trigger_pkt_any_0_load",
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"~el2_lsu|el2_lsu>io_trigger_pkt_any_0_select",
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"~el2_lsu|el2_lsu>io_trigger_pkt_any_3_store",
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"~el2_lsu|el2_lsu>io_trigger_pkt_any_2_store",
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"~el2_lsu|el2_lsu>io_trigger_pkt_any_1_load",
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"~el2_lsu|el2_lsu>io_trigger_pkt_any_1_select",
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"~el2_lsu|el2_lsu>io_trigger_pkt_any_3_load",
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"~el2_lsu|el2_lsu>io_trigger_pkt_any_3_select",
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"~el2_lsu|el2_lsu>io_trigger_pkt_any_2_load",
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"~el2_lsu|el2_lsu>io_trigger_pkt_any_2_select",
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"~el2_lsu|el2_lsu>io_trigger_pkt_any_0_tdata2",
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"~el2_lsu|el2_lsu>io_trigger_pkt_any_0_match_",
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"~el2_lsu|el2_lsu>io_trigger_pkt_any_1_tdata2",
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"~el2_lsu|el2_lsu>io_trigger_pkt_any_1_match_",
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"~el2_lsu|el2_lsu>io_trigger_pkt_any_3_tdata2",
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"~el2_lsu|el2_lsu>io_trigger_pkt_any_3_match_",
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"~el2_lsu|el2_lsu>io_trigger_pkt_any_2_tdata2",
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"~el2_lsu|el2_lsu>io_trigger_pkt_any_2_match_",
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"~el2_lsu|el2_lsu>io_picm_rd_data",
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"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
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"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
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"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
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"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_lsu|el2_lsu>io_dccm_wren",
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"sources":[
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"~el2_lsu|el2_lsu>io_dma_dccm_req",
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"~el2_lsu|el2_lsu>io_dma_mem_write",
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"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
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"~el2_lsu|el2_lsu>io_dma_mem_addr",
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"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
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"~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d",
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"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
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"~el2_lsu|el2_lsu>io_lsu_p_dword",
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"~el2_lsu|el2_lsu>io_lsu_p_half",
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"~el2_lsu|el2_lsu>io_lsu_p_word",
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"~el2_lsu|el2_lsu>io_dma_mem_sz",
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"~el2_lsu|el2_lsu>io_lsu_p_valid",
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"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
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"~el2_lsu|el2_lsu>io_lsu_p_fast_int",
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"~el2_lsu|el2_lsu>io_lsu_p_load",
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"~el2_lsu|el2_lsu>io_lsu_p_store",
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"~el2_lsu|el2_lsu>io_picm_rd_data",
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"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
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"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
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"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_lsu|el2_lsu>io_lsu_load_stall_any",
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"sources":[
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"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
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"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
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"~el2_lsu|el2_lsu>io_dma_mem_addr",
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"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
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"~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d",
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"~el2_lsu|el2_lsu>io_lsu_p_dword",
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"~el2_lsu|el2_lsu>io_lsu_p_half",
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"~el2_lsu|el2_lsu>io_lsu_p_word",
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"~el2_lsu|el2_lsu>io_dma_mem_sz",
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"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
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"~el2_lsu|el2_lsu>io_picm_rd_data",
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"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
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"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
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"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_lsu|el2_lsu>io_dccm_wr_data_hi",
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"sources":[
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"~el2_lsu|el2_lsu>io_dma_dccm_req",
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"~el2_lsu|el2_lsu>io_dma_mem_write",
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"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
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"~el2_lsu|el2_lsu>io_dma_mem_addr",
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"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
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"~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d",
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"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
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"~el2_lsu|el2_lsu>io_lsu_p_dword",
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"~el2_lsu|el2_lsu>io_lsu_p_half",
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"~el2_lsu|el2_lsu>io_lsu_p_word",
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"~el2_lsu|el2_lsu>io_dma_mem_sz",
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"~el2_lsu|el2_lsu>io_dma_mem_wdata",
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"~el2_lsu|el2_lsu>io_picm_rd_data",
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"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
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"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
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"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
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"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_lsu|el2_lsu>io_dccm_rden",
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"sources":[
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"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
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"~el2_lsu|el2_lsu>io_dma_mem_addr",
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"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
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"~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d",
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"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
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"~el2_lsu|el2_lsu>io_lsu_p_dword",
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"~el2_lsu|el2_lsu>io_lsu_p_half",
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"~el2_lsu|el2_lsu>io_lsu_p_word",
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"~el2_lsu|el2_lsu>io_dma_mem_sz",
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"~el2_lsu|el2_lsu>io_dma_dccm_req",
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"~el2_lsu|el2_lsu>io_lsu_p_valid",
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"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
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"~el2_lsu|el2_lsu>io_lsu_p_fast_int",
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"~el2_lsu|el2_lsu>io_lsu_p_load",
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"~el2_lsu|el2_lsu>io_dma_mem_write",
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"~el2_lsu|el2_lsu>io_lsu_p_store",
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"~el2_lsu|el2_lsu>io_picm_rd_data",
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"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
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"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
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"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_lsu|el2_lsu>io_picm_rden",
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"sources":[
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"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
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"~el2_lsu|el2_lsu>io_dma_mem_addr",
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"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
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"~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d",
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"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
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"~el2_lsu|el2_lsu>io_lsu_p_dword",
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"~el2_lsu|el2_lsu>io_lsu_p_half",
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"~el2_lsu|el2_lsu>io_lsu_p_word",
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"~el2_lsu|el2_lsu>io_dma_mem_sz",
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"~el2_lsu|el2_lsu>io_dma_dccm_req",
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"~el2_lsu|el2_lsu>io_lsu_p_valid",
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"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
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"~el2_lsu|el2_lsu>io_lsu_p_fast_int",
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"~el2_lsu|el2_lsu>io_lsu_p_load",
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"~el2_lsu|el2_lsu>io_dma_mem_write",
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"~el2_lsu|el2_lsu>io_picm_rd_data",
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"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
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"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
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"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_lsu|el2_lsu>io_picm_wren",
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"sources":[
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"~el2_lsu|el2_lsu>io_dma_dccm_req",
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"~el2_lsu|el2_lsu>io_dma_mem_write",
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"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r",
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"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
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"~el2_lsu|el2_lsu>io_dma_mem_addr",
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"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
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"~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d",
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"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
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"~el2_lsu|el2_lsu>io_lsu_p_dword",
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"~el2_lsu|el2_lsu>io_lsu_p_half",
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"~el2_lsu|el2_lsu>io_lsu_p_word",
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"~el2_lsu|el2_lsu>io_dma_mem_sz",
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"~el2_lsu|el2_lsu>io_picm_rd_data",
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"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
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"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
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"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_lsu|el2_lsu>io_dccm_rd_addr_hi",
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"sources":[
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"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
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"~el2_lsu|el2_lsu>io_dma_mem_addr",
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"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
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"~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d",
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"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
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"~el2_lsu|el2_lsu>io_lsu_p_dword",
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"~el2_lsu|el2_lsu>io_lsu_p_half",
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"~el2_lsu|el2_lsu>io_lsu_p_word",
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"~el2_lsu|el2_lsu>io_dma_mem_sz",
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"~el2_lsu|el2_lsu>io_picm_rd_data",
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"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
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"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
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"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
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"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_lsu|el2_lsu>io_dccm_ready",
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"sources":[
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"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_lsu|el2_lsu>io_picm_wraddr",
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"sources":[
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"~el2_lsu|el2_lsu>io_dma_mem_addr",
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"~el2_lsu|el2_lsu>io_dma_dccm_req",
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"~el2_lsu|el2_lsu>io_dma_mem_write",
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||||||
|
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
|
||||||
|
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
|
||||||
|
"~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d",
|
||||||
|
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
|
||||||
|
"~el2_lsu|el2_lsu>io_lsu_p_dword",
|
||||||
|
"~el2_lsu|el2_lsu>io_lsu_p_half",
|
||||||
|
"~el2_lsu|el2_lsu>io_lsu_p_word",
|
||||||
|
"~el2_lsu|el2_lsu>io_dma_mem_sz",
|
||||||
|
"~el2_lsu|el2_lsu>io_picm_rd_data",
|
||||||
|
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
|
||||||
|
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
|
||||||
|
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
|
||||||
|
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
|
||||||
|
]
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"class":"firrtl.transforms.CombinationalPath",
|
||||||
|
"sink":"~el2_lsu|el2_lsu>io_lsu_store_stall_any",
|
||||||
|
"sources":[
|
||||||
|
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
|
||||||
|
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
|
||||||
|
"~el2_lsu|el2_lsu>io_dma_mem_addr",
|
||||||
|
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
|
||||||
|
"~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d",
|
||||||
|
"~el2_lsu|el2_lsu>io_lsu_p_dword",
|
||||||
|
"~el2_lsu|el2_lsu>io_lsu_p_half",
|
||||||
|
"~el2_lsu|el2_lsu>io_lsu_p_word",
|
||||||
|
"~el2_lsu|el2_lsu>io_dma_mem_sz",
|
||||||
|
"~el2_lsu|el2_lsu>io_picm_rd_data",
|
||||||
|
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
|
||||||
|
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
|
||||||
|
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
|
||||||
|
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
|
||||||
|
]
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"class":"firrtl.transforms.CombinationalPath",
|
||||||
|
"sink":"~el2_lsu|el2_lsu>io_lsu_pmu_bus_trxn",
|
||||||
|
"sources":[
|
||||||
|
"~el2_lsu|el2_lsu>io_lsu_axi_arready",
|
||||||
|
"~el2_lsu|el2_lsu>io_lsu_axi_awready",
|
||||||
|
"~el2_lsu|el2_lsu>io_lsu_axi_wready"
|
||||||
|
]
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"class":"firrtl.transforms.CombinationalPath",
|
||||||
|
"sink":"~el2_lsu|el2_lsu>io_dccm_dma_ecc_error",
|
||||||
|
"sources":[
|
||||||
|
"~el2_lsu|el2_lsu>io_dec_tlu_core_ecc_disable",
|
||||||
|
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
|
||||||
|
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo"
|
||||||
|
]
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"class":"firrtl.transforms.CombinationalPath",
|
||||||
|
"sink":"~el2_lsu|el2_lsu>io_lsu_fastint_stall_any",
|
||||||
|
"sources":[
|
||||||
|
"~el2_lsu|el2_lsu>io_dec_tlu_core_ecc_disable",
|
||||||
|
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
|
||||||
|
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo"
|
||||||
|
]
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"class":"firrtl.transforms.CombinationalPath",
|
||||||
|
"sink":"~el2_lsu|el2_lsu>io_lsu_pmu_bus_busy",
|
||||||
|
"sources":[
|
||||||
|
"~el2_lsu|el2_lsu>io_lsu_axi_arready",
|
||||||
|
"~el2_lsu|el2_lsu>io_lsu_axi_awready",
|
||||||
|
"~el2_lsu|el2_lsu>io_lsu_axi_wready"
|
||||||
|
]
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"class":"firrtl.transforms.CombinationalPath",
|
||||||
|
"sink":"~el2_lsu|el2_lsu>io_dccm_rd_addr_lo",
|
||||||
|
"sources":[
|
||||||
|
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
|
||||||
|
"~el2_lsu|el2_lsu>io_dma_mem_addr",
|
||||||
|
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
|
||||||
|
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
|
||||||
|
"~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d",
|
||||||
|
"~el2_lsu|el2_lsu>io_picm_rd_data",
|
||||||
|
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
|
||||||
|
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
|
||||||
|
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
|
||||||
|
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
|
||||||
|
]
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"class":"firrtl.transforms.CombinationalPath",
|
||||||
|
"sink":"~el2_lsu|el2_lsu>io_picm_wr_data",
|
||||||
|
"sources":[
|
||||||
|
"~el2_lsu|el2_lsu>io_dma_mem_wdata",
|
||||||
|
"~el2_lsu|el2_lsu>io_dma_dccm_req",
|
||||||
|
"~el2_lsu|el2_lsu>io_dma_mem_write",
|
||||||
|
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
|
||||||
|
"~el2_lsu|el2_lsu>io_dma_mem_addr",
|
||||||
|
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
|
||||||
|
"~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d",
|
||||||
|
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
|
||||||
|
"~el2_lsu|el2_lsu>io_lsu_p_dword",
|
||||||
|
"~el2_lsu|el2_lsu>io_lsu_p_half",
|
||||||
|
"~el2_lsu|el2_lsu>io_lsu_p_word",
|
||||||
|
"~el2_lsu|el2_lsu>io_dma_mem_sz",
|
||||||
|
"~el2_lsu|el2_lsu>io_lsu_p_valid",
|
||||||
|
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
|
||||||
|
"~el2_lsu|el2_lsu>io_lsu_p_fast_int",
|
||||||
|
"~el2_lsu|el2_lsu>io_lsu_p_load",
|
||||||
|
"~el2_lsu|el2_lsu>io_lsu_p_store",
|
||||||
|
"~el2_lsu|el2_lsu>io_picm_rd_data",
|
||||||
|
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
|
||||||
|
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
|
||||||
|
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
|
||||||
|
]
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"class":"firrtl.transforms.CombinationalPath",
|
||||||
|
"sink":"~el2_lsu|el2_lsu>io_dccm_wr_addr_lo",
|
||||||
|
"sources":[
|
||||||
|
"~el2_lsu|el2_lsu>io_dma_dccm_req",
|
||||||
|
"~el2_lsu|el2_lsu>io_dma_mem_write",
|
||||||
|
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
|
||||||
|
"~el2_lsu|el2_lsu>io_dma_mem_addr",
|
||||||
|
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
|
||||||
|
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
|
||||||
|
"~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d",
|
||||||
|
"~el2_lsu|el2_lsu>io_lsu_p_dword",
|
||||||
|
"~el2_lsu|el2_lsu>io_lsu_p_half",
|
||||||
|
"~el2_lsu|el2_lsu>io_lsu_p_word",
|
||||||
|
"~el2_lsu|el2_lsu>io_dma_mem_sz",
|
||||||
|
"~el2_lsu|el2_lsu>io_picm_rd_data",
|
||||||
|
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
|
||||||
|
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
|
||||||
|
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
|
||||||
|
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
|
||||||
|
]
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"class":"firrtl.transforms.CombinationalPath",
|
||||||
|
"sink":"~el2_lsu|el2_lsu>io_picm_mken",
|
||||||
|
"sources":[
|
||||||
|
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
|
||||||
|
"~el2_lsu|el2_lsu>io_dma_mem_addr",
|
||||||
|
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
|
||||||
|
"~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d",
|
||||||
|
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
|
||||||
|
"~el2_lsu|el2_lsu>io_lsu_p_dword",
|
||||||
|
"~el2_lsu|el2_lsu>io_lsu_p_half",
|
||||||
|
"~el2_lsu|el2_lsu>io_lsu_p_word",
|
||||||
|
"~el2_lsu|el2_lsu>io_dma_mem_sz",
|
||||||
|
"~el2_lsu|el2_lsu>io_dma_dccm_req",
|
||||||
|
"~el2_lsu|el2_lsu>io_lsu_p_valid",
|
||||||
|
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
|
||||||
|
"~el2_lsu|el2_lsu>io_lsu_p_fast_int",
|
||||||
|
"~el2_lsu|el2_lsu>io_lsu_p_store",
|
||||||
|
"~el2_lsu|el2_lsu>io_dma_mem_write",
|
||||||
|
"~el2_lsu|el2_lsu>io_picm_rd_data",
|
||||||
|
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
|
||||||
|
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
|
||||||
|
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
|
||||||
|
]
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"class":"firrtl.transforms.CombinationalPath",
|
||||||
|
"sink":"~el2_lsu|el2_lsu>io_lsu_nonblock_load_valid_m",
|
||||||
|
"sources":[
|
||||||
|
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r"
|
||||||
|
]
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"class":"firrtl.transforms.CombinationalPath",
|
||||||
|
"sink":"~el2_lsu|el2_lsu>io_dccm_wr_data_lo",
|
||||||
|
"sources":[
|
||||||
|
"~el2_lsu|el2_lsu>io_dma_dccm_req",
|
||||||
|
"~el2_lsu|el2_lsu>io_dma_mem_write",
|
||||||
|
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
|
||||||
|
"~el2_lsu|el2_lsu>io_dma_mem_addr",
|
||||||
|
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
|
||||||
|
"~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d",
|
||||||
|
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
|
||||||
|
"~el2_lsu|el2_lsu>io_lsu_p_dword",
|
||||||
|
"~el2_lsu|el2_lsu>io_lsu_p_half",
|
||||||
|
"~el2_lsu|el2_lsu>io_lsu_p_word",
|
||||||
|
"~el2_lsu|el2_lsu>io_dma_mem_sz",
|
||||||
|
"~el2_lsu|el2_lsu>io_dma_mem_wdata",
|
||||||
|
"~el2_lsu|el2_lsu>io_picm_rd_data",
|
||||||
|
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
|
||||||
|
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
|
||||||
|
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
|
||||||
|
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
|
||||||
|
]
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"class":"firrtl.transforms.CombinationalPath",
|
||||||
|
"sink":"~el2_lsu|el2_lsu>io_lsu_pmu_bus_misaligned",
|
||||||
|
"sources":[
|
||||||
|
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
|
||||||
|
]
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"class":"firrtl.transforms.CombinationalPath",
|
||||||
|
"sink":"~el2_lsu|el2_lsu>io_lsu_nonblock_load_inv_r",
|
||||||
|
"sources":[
|
||||||
|
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
|
||||||
|
]
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"class":"firrtl.transforms.CombinationalPath",
|
||||||
|
"sink":"~el2_lsu|el2_lsu>io_dccm_wr_addr_hi",
|
||||||
|
"sources":[
|
||||||
|
"~el2_lsu|el2_lsu>io_dma_dccm_req",
|
||||||
|
"~el2_lsu|el2_lsu>io_dma_mem_write",
|
||||||
|
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
|
||||||
|
"~el2_lsu|el2_lsu>io_dma_mem_addr",
|
||||||
|
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
|
||||||
|
"~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d",
|
||||||
|
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
|
||||||
|
"~el2_lsu|el2_lsu>io_lsu_p_dword",
|
||||||
|
"~el2_lsu|el2_lsu>io_lsu_p_half",
|
||||||
|
"~el2_lsu|el2_lsu>io_lsu_p_word",
|
||||||
|
"~el2_lsu|el2_lsu>io_dma_mem_sz",
|
||||||
|
"~el2_lsu|el2_lsu>io_picm_rd_data",
|
||||||
|
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
|
||||||
|
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
|
||||||
|
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
|
||||||
|
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
|
||||||
|
]
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"class":"firrtl.EmitCircuitAnnotation",
|
||||||
|
"emitter":"firrtl.VerilogEmitter"
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"class":"firrtl.transforms.BlackBoxResourceAnno",
|
||||||
|
"target":"el2_lsu.TEC_RV_ICG",
|
||||||
|
"resourceId":"/vsrc/TEC_RV_ICG.v"
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"class":"firrtl.options.TargetDirAnnotation",
|
||||||
|
"directory":"."
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"class":"firrtl.options.OutputAnnotationFileAnnotation",
|
||||||
|
"file":"el2_lsu"
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
|
||||||
|
"targetDir":"."
|
||||||
|
}
|
||||||
|
]
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,102 @@
|
||||||
|
[
|
||||||
|
{
|
||||||
|
"class":"firrtl.transforms.CombinationalPath",
|
||||||
|
"sink":"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pmu_bus_misaligned",
|
||||||
|
"sources":[
|
||||||
|
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_commit_r"
|
||||||
|
]
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"class":"firrtl.transforms.CombinationalPath",
|
||||||
|
"sink":"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_bus_read_data_m",
|
||||||
|
"sources":[
|
||||||
|
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_addr_m",
|
||||||
|
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_busreq_m",
|
||||||
|
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_end_addr_m",
|
||||||
|
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_r_store",
|
||||||
|
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_r_valid",
|
||||||
|
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_store_data_r",
|
||||||
|
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_addr_r",
|
||||||
|
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_r_by",
|
||||||
|
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_r_word",
|
||||||
|
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_r_half",
|
||||||
|
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_end_addr_r"
|
||||||
|
]
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"class":"firrtl.transforms.CombinationalPath",
|
||||||
|
"sink":"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_nonblock_load_inv_r",
|
||||||
|
"sources":[
|
||||||
|
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_commit_r"
|
||||||
|
]
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"class":"firrtl.transforms.CombinationalPath",
|
||||||
|
"sink":"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pmu_bus_trxn",
|
||||||
|
"sources":[
|
||||||
|
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_axi_arready",
|
||||||
|
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_axi_awready",
|
||||||
|
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_axi_wready"
|
||||||
|
]
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"class":"firrtl.transforms.CombinationalPath",
|
||||||
|
"sink":"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pmu_bus_busy",
|
||||||
|
"sources":[
|
||||||
|
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_axi_arready",
|
||||||
|
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_axi_awready",
|
||||||
|
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_axi_wready"
|
||||||
|
]
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"class":"firrtl.transforms.CombinationalPath",
|
||||||
|
"sink":"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_nonblock_load_valid_m",
|
||||||
|
"sources":[
|
||||||
|
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_m_load",
|
||||||
|
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_flush_m_up",
|
||||||
|
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_busreq_m",
|
||||||
|
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_m_valid",
|
||||||
|
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_is_sideeffects_m",
|
||||||
|
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_addr_m",
|
||||||
|
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_end_addr_m",
|
||||||
|
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_r_store",
|
||||||
|
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_r_by",
|
||||||
|
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_r_valid",
|
||||||
|
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_r_word",
|
||||||
|
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_r_half",
|
||||||
|
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_addr_r",
|
||||||
|
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_end_addr_r"
|
||||||
|
]
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"class":"firrtl.transforms.CombinationalPath",
|
||||||
|
"sink":"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_bus_buffer_full_any",
|
||||||
|
"sources":[
|
||||||
|
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_dec_lsu_valid_raw_d",
|
||||||
|
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_busreq_m",
|
||||||
|
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_addr_d",
|
||||||
|
"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_end_addr_d"
|
||||||
|
]
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"class":"firrtl.EmitCircuitAnnotation",
|
||||||
|
"emitter":"firrtl.VerilogEmitter"
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"class":"firrtl.transforms.BlackBoxResourceAnno",
|
||||||
|
"target":"el2_lsu_bus_intf.TEC_RV_ICG",
|
||||||
|
"resourceId":"/vsrc/TEC_RV_ICG.v"
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"class":"firrtl.options.TargetDirAnnotation",
|
||||||
|
"directory":"."
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"class":"firrtl.options.OutputAnnotationFileAnnotation",
|
||||||
|
"file":"el2_lsu_bus_intf"
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
|
||||||
|
"targetDir":"."
|
||||||
|
}
|
||||||
|
]
|
||||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -130,7 +130,6 @@ class el2_ifu_ifc_ctl extends Module with el2_lib with RequireAsyncReset {
|
||||||
rvrangecheck(ICCM_SADR, ICCM_SIZE, Cat(io.ifc_fetch_addr_bf,0.U))
|
rvrangecheck(ICCM_SADR, ICCM_SIZE, Cat(io.ifc_fetch_addr_bf,0.U))
|
||||||
else (0.U, 0.U)
|
else (0.U, 0.U)
|
||||||
io.ifc_iccm_access_bf := iccm_acc_in_range_bf
|
io.ifc_iccm_access_bf := iccm_acc_in_range_bf
|
||||||
|
|
||||||
io.ifc_dma_access_ok := ( (!io.ifc_iccm_access_bf |
|
io.ifc_dma_access_ok := ( (!io.ifc_iccm_access_bf |
|
||||||
(fb_full_f & !(io.ifu_fb_consume2 | io.ifu_fb_consume1)) |
|
(fb_full_f & !(io.ifu_fb_consume2 | io.ifu_fb_consume1)) |
|
||||||
(wfm & !io.ifc_fetch_req_bf) | idle ) & !io.exu_flush_final) | dma_iccm_stall_any_f
|
(wfm & !io.ifc_fetch_req_bf) | idle ) & !io.exu_flush_final) | dma_iccm_stall_any_f
|
||||||
|
|
@ -141,7 +140,7 @@ class el2_ifu_ifc_ctl extends Module with el2_lib with RequireAsyncReset {
|
||||||
io.ifc_fetch_req_f := withClock(io.active_clk){RegNext(io.ifc_fetch_req_bf, init=0.U)}
|
io.ifc_fetch_req_f := withClock(io.active_clk){RegNext(io.ifc_fetch_req_bf, init=0.U)}
|
||||||
|
|
||||||
io.ifc_fetch_addr_f := rvdffe(io.ifc_fetch_addr_bf, io.exu_flush_final|io.ifc_fetch_req_f, clock, io.scan_mode)
|
io.ifc_fetch_addr_f := rvdffe(io.ifc_fetch_addr_bf, io.exu_flush_final|io.ifc_fetch_req_f, clock, io.scan_mode)
|
||||||
|
//rvdffe(io.ifc_fetch_addr_bf,(io.exu_flush_final|io.ifc_fetch_req_f).asBool,clock,io.scan_mode)
|
||||||
}
|
}
|
||||||
|
|
||||||
object ifu_ifc extends App {
|
object ifu_ifc extends App {
|
||||||
|
|
|
||||||
|
|
@ -59,7 +59,7 @@ trait param {
|
||||||
val DCCM_INDEX_BITS = 0xC //.U(4.W)
|
val DCCM_INDEX_BITS = 0xC //.U(4.W)
|
||||||
val DCCM_NUM_BANKS = 0x04 //.U(5.W)
|
val DCCM_NUM_BANKS = 0x04 //.U(5.W)
|
||||||
val DCCM_REGION = 15 //.U(4.W)
|
val DCCM_REGION = 15 //.U(4.W)
|
||||||
val DCCM_SADR = 0xF0040000
|
val DCCM_SADR = 0xF0040000L
|
||||||
val DCCM_SIZE = 0x040
|
val DCCM_SIZE = 0x040
|
||||||
val DCCM_WIDTH_BITS = 2 //.U(2.W)
|
val DCCM_WIDTH_BITS = 2 //.U(2.W)
|
||||||
val DMA_BUF_DEPTH = 5 //.U(3.W)
|
val DMA_BUF_DEPTH = 5 //.U(3.W)
|
||||||
|
|
@ -226,6 +226,13 @@ trait el2_lib extends param{
|
||||||
(in_region, in_range)
|
(in_region, in_range)
|
||||||
}
|
}
|
||||||
|
|
||||||
|
def rvlsadder(rs1:UInt,offset:UInt) = {
|
||||||
|
val w1 = Cat(0.U(1.W),rs1(11,0)) + Cat(0.U(1.W),offset(11,0)) //w1[12] =cout offset[11]=sign
|
||||||
|
val dout_upper = ((Fill(20, ~(offset(11) ^ w1(12)))) & rs1(31,12)) |
|
||||||
|
((Fill(20, ~offset(11) & w1(12))) & (rs1(31,12)+1.U)) |
|
||||||
|
((Fill(20, offset(11) & ~w1(12))) & (rs1(31,12)-1.U))
|
||||||
|
Cat(dout_upper,w1(11,0))
|
||||||
|
}
|
||||||
///////////////////////////////////////////////////////////////////
|
///////////////////////////////////////////////////////////////////
|
||||||
def rvmaskandmatch(mask:UInt, data:UInt, masken:Bool):UInt={
|
def rvmaskandmatch(mask:UInt, data:UInt, masken:Bool):UInt={
|
||||||
val matchvec = Wire(Vec(data.getWidth,UInt(1.W)))
|
val matchvec = Wire(Vec(data.getWidth,UInt(1.W)))
|
||||||
|
|
@ -479,6 +486,20 @@ trait el2_lib extends param{
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
def rvrangecheck_ch(addr:UInt,CCM_SADR:UInt, CCM_SIZE:Int=128) = {
|
||||||
|
val REGION_BITS = 4
|
||||||
|
val MASK_BITS = 10 + log2Ceil(CCM_SIZE)
|
||||||
|
val start_addr = CCM_SADR
|
||||||
|
val region = start_addr(31,(32-REGION_BITS))
|
||||||
|
val in_region = (addr(31,(32-REGION_BITS)) === region(REGION_BITS-1,0)).asUInt
|
||||||
|
val in_range = Wire(UInt(1.W))
|
||||||
|
if(CCM_SIZE == 48)
|
||||||
|
in_range := (addr(31,MASK_BITS) === start_addr(31,MASK_BITS)).asUInt & ~(addr(MASK_BITS-1,MASK_BITS-2).andR.asUInt)
|
||||||
|
else
|
||||||
|
in_range := (addr(31,MASK_BITS) === start_addr(31,MASK_BITS)).asUInt
|
||||||
|
(in_range,in_region)
|
||||||
|
}
|
||||||
|
|
||||||
////rvdffe ///////////////////////////////////////////////////////////////////////
|
////rvdffe ///////////////////////////////////////////////////////////////////////
|
||||||
object rvdffe {
|
object rvdffe {
|
||||||
def apply(din: UInt, en: Bool, clk: Clock, scan_mode: Bool): UInt = {
|
def apply(din: UInt, en: Bool, clk: Clock, scan_mode: Bool): UInt = {
|
||||||
|
|
|
||||||
|
|
@ -0,0 +1,498 @@
|
||||||
|
package lsu
|
||||||
|
import lib._
|
||||||
|
import chisel3._
|
||||||
|
import chisel3.util._
|
||||||
|
import include._
|
||||||
|
|
||||||
|
|
||||||
|
class el2_lsu extends Module with RequireAsyncReset with param with el2_lib {
|
||||||
|
val io = IO (new Bundle {
|
||||||
|
val clk_override = Input(Bool())
|
||||||
|
val dec_tlu_flush_lower_r = Input(Bool())
|
||||||
|
val dec_tlu_i0_kill_writeb_r = Input(Bool())
|
||||||
|
val dec_tlu_force_halt = Input(Bool())
|
||||||
|
// chicken signals
|
||||||
|
val dec_tlu_external_ldfwd_disable = Input(Bool())
|
||||||
|
val dec_tlu_wb_coalescing_disable = Input(Bool())
|
||||||
|
val dec_tlu_sideeffect_posted_disable = Input(Bool())
|
||||||
|
val dec_tlu_core_ecc_disable = Input(Bool())
|
||||||
|
|
||||||
|
val exu_lsu_rs1_d = Input(UInt(32.W))
|
||||||
|
val exu_lsu_rs2_d = Input(UInt(32.W))
|
||||||
|
val dec_lsu_offset_d = Input(UInt(12.W))
|
||||||
|
val lsu_p = Input(new el2_lsu_pkt_t)
|
||||||
|
val trigger_pkt_any = Input(Vec(4, new el2_trigger_pkt_t))
|
||||||
|
|
||||||
|
val dec_lsu_valid_raw_d = Input(Bool())
|
||||||
|
val dec_tlu_mrac_ff = Input(UInt(32.W))
|
||||||
|
|
||||||
|
//Outputs
|
||||||
|
// val lsu_result_m = Output(UInt(32.W))
|
||||||
|
// val lsu_result_corr_r = Output(UInt(32.W))
|
||||||
|
val lsu_load_stall_any = Output(Bool())
|
||||||
|
val lsu_store_stall_any = Output(Bool())
|
||||||
|
val lsu_fastint_stall_any = Output(Bool())
|
||||||
|
val lsu_idle_any = Output(Bool())
|
||||||
|
val lsu_fir_addr = Output(UInt(32.W))
|
||||||
|
val lsu_fir_error = Output(UInt(2.W))
|
||||||
|
val lsu_single_ecc_error_incr = Output(Bool())
|
||||||
|
val lsu_error_pkt_r = Output(new el2_lsu_error_pkt_t)
|
||||||
|
val lsu_imprecise_error_load_any = Output(Bool())
|
||||||
|
val lsu_imprecise_error_store_any = Output(Bool())
|
||||||
|
val lsu_imprecise_error_addr_any = Output(UInt(32.W))
|
||||||
|
|
||||||
|
// Non-blocking loads
|
||||||
|
val lsu_nonblock_load_valid_m = Output(Bool())
|
||||||
|
val lsu_nonblock_load_tag_m = Output(UInt(LSU_NUM_NBLOAD_WIDTH.W))
|
||||||
|
val lsu_nonblock_load_inv_r = Output(Bool())
|
||||||
|
val lsu_nonblock_load_inv_tag_r = Output(UInt(LSU_NUM_NBLOAD_WIDTH.W))
|
||||||
|
val lsu_nonblock_load_data_valid = Output(Bool())
|
||||||
|
val lsu_nonblock_load_data_error = Output(Bool())
|
||||||
|
val lsu_nonblock_load_data_tag = Output(UInt(LSU_NUM_NBLOAD_WIDTH.W))
|
||||||
|
val lsu_nonblock_load_data = Output(UInt(32.W))
|
||||||
|
|
||||||
|
val lsu_pmu_load_external_m = Output(Bool())
|
||||||
|
val lsu_pmu_store_external_m = Output(Bool())
|
||||||
|
val lsu_pmu_misaligned_m = Output(Bool())
|
||||||
|
val lsu_pmu_bus_trxn = Output(Bool())
|
||||||
|
val lsu_pmu_bus_misaligned = Output(Bool())
|
||||||
|
val lsu_pmu_bus_error = Output(Bool())
|
||||||
|
val lsu_pmu_bus_busy = Output(Bool())
|
||||||
|
|
||||||
|
val lsu_trigger_match_m = Output(UInt(4.W))
|
||||||
|
// DCCM ports
|
||||||
|
val dccm_wren = Output(Bool())
|
||||||
|
val dccm_rden = Output(Bool())
|
||||||
|
val dccm_wr_addr_lo = Output(UInt(DCCM_BITS.W))
|
||||||
|
val dccm_wr_addr_hi = Output(UInt(DCCM_BITS.W))
|
||||||
|
val dccm_rd_addr_lo = Output(UInt(DCCM_BITS.W))
|
||||||
|
val dccm_rd_addr_hi = Output(UInt(DCCM_BITS.W))
|
||||||
|
val dccm_wr_data_lo = Output(UInt(DCCM_FDATA_WIDTH.W))
|
||||||
|
val dccm_wr_data_hi = Output(UInt(DCCM_FDATA_WIDTH.W))
|
||||||
|
val dccm_rd_data_lo = Input(UInt(DCCM_FDATA_WIDTH.W))
|
||||||
|
val dccm_rd_data_hi = Input(UInt(DCCM_FDATA_WIDTH.W))
|
||||||
|
// PIC ports
|
||||||
|
val picm_wren = Output(Bool())
|
||||||
|
val picm_rden = Output(Bool())
|
||||||
|
val picm_mken = Output(Bool())
|
||||||
|
val picm_rdaddr = Output(UInt(32.W))
|
||||||
|
val picm_wraddr = Output(UInt(32.W))
|
||||||
|
val picm_wr_data = Output(UInt(32.W))
|
||||||
|
val picm_rd_data = Input(UInt(32.W))
|
||||||
|
|
||||||
|
// AXI Write Channels
|
||||||
|
|
||||||
|
val lsu_axi_awvalid = Output(Bool())
|
||||||
|
val lsu_axi_awlock = Output(Bool())
|
||||||
|
val lsu_axi_awready = Input(Bool())
|
||||||
|
val lsu_axi_awid = Output(UInt(LSU_BUS_TAG.W))
|
||||||
|
val lsu_axi_awaddr = Output(UInt(32.W))
|
||||||
|
val lsu_axi_awregion = Output(UInt(4.W))
|
||||||
|
val lsu_axi_awlen = Output(UInt(8.W))
|
||||||
|
val lsu_axi_awsize = Output(UInt(3.W))
|
||||||
|
val lsu_axi_awburst = Output(UInt(2.W))
|
||||||
|
val lsu_axi_awcache = Output(UInt(4.W))
|
||||||
|
val lsu_axi_awprot = Output(UInt(3.W))
|
||||||
|
val lsu_axi_awqos = Output(UInt(4.W))
|
||||||
|
val lsu_axi_wvalid = Output(Bool())
|
||||||
|
val lsu_axi_wready = Input(Bool())
|
||||||
|
val lsu_axi_wdata = Output(UInt(64.W))
|
||||||
|
val lsu_axi_wstrb = Output(UInt(8.W))
|
||||||
|
val lsu_axi_wlast = Output(Bool())
|
||||||
|
val lsu_axi_bvalid = Input(Bool())
|
||||||
|
val lsu_axi_bready = Output(Bool())
|
||||||
|
val lsu_axi_bresp = Input(UInt(2.W))
|
||||||
|
val lsu_axi_bid = Input(UInt(LSU_BUS_TAG.W))
|
||||||
|
|
||||||
|
// AXI Read Channels
|
||||||
|
|
||||||
|
val lsu_axi_arvalid = Output(Bool())
|
||||||
|
val lsu_axi_arlock = Output(Bool())
|
||||||
|
val lsu_axi_arready = Input(Bool())
|
||||||
|
val lsu_axi_arid = Output(UInt(LSU_BUS_TAG.W))
|
||||||
|
val lsu_axi_araddr = Output(UInt(32.W))
|
||||||
|
val lsu_axi_arregion = Output(UInt(4.W))
|
||||||
|
val lsu_axi_arlen = Output(UInt(8.W))
|
||||||
|
val lsu_axi_arsize = Output(UInt(3.W))
|
||||||
|
val lsu_axi_arburst = Output(UInt(2.W))
|
||||||
|
val lsu_axi_arcache = Output(UInt(4.W))
|
||||||
|
val lsu_axi_arprot = Output(UInt(3.W))
|
||||||
|
val lsu_axi_arqos = Output(UInt(4.W))
|
||||||
|
val lsu_axi_rvalid = Input(Bool())
|
||||||
|
val lsu_axi_rready = Output(Bool())
|
||||||
|
val lsu_axi_rdata = Input(UInt(64.W))
|
||||||
|
val lsu_axi_rlast = Input(Bool())
|
||||||
|
val lsu_axi_rresp = Input(UInt(2.W))
|
||||||
|
val lsu_axi_rid = Input(UInt(LSU_BUS_TAG.W))
|
||||||
|
|
||||||
|
val lsu_bus_clk_en = Input(Bool())
|
||||||
|
// DMA slave
|
||||||
|
|
||||||
|
val dma_dccm_req = Input(Bool())
|
||||||
|
val dma_mem_write = Input(Bool())
|
||||||
|
val dccm_dma_rvalid = Output(Bool())
|
||||||
|
val dccm_dma_ecc_error = Output(Bool())
|
||||||
|
val dma_mem_tag = Input(UInt(3.W))
|
||||||
|
val dma_mem_addr = Input(UInt(32.W))
|
||||||
|
val dma_mem_sz = Input(UInt(3.W))
|
||||||
|
val dma_mem_wdata = Input(UInt(64.W))
|
||||||
|
val dccm_dma_rtag = Output(UInt(3.W))
|
||||||
|
val dccm_dma_rdata = Output(UInt(64.W))
|
||||||
|
val dccm_ready = Output(Bool())
|
||||||
|
|
||||||
|
val scan_mode = Input(Bool())
|
||||||
|
val free_clk = Input(Clock())
|
||||||
|
|
||||||
|
})
|
||||||
|
val dma_dccm_wdata = WireInit(0.U(64.W))
|
||||||
|
val dma_dccm_wdata_lo = WireInit(0.U(32.W))
|
||||||
|
val dma_dccm_wdata_hi = WireInit(0.U(32.W))
|
||||||
|
val dma_mem_tag_m = WireInit(0.U(32.W))
|
||||||
|
val lsu_raw_fwd_lo_r = WireInit(0.U(1.W))
|
||||||
|
val lsu_raw_fwd_hi_r = WireInit(0.U(1.W))
|
||||||
|
|
||||||
|
val lsu_lsc_ctl = Module(new el2_lsu_lsc_ctl )
|
||||||
|
val dccm_ctl = Module(new el2_lsu_dccm_ctl )
|
||||||
|
val stbuf = Module(new el2_lsu_stbuf )
|
||||||
|
val ecc = Module(new el2_lsu_ecc )
|
||||||
|
val trigger = Module(new el2_lsu_trigger )
|
||||||
|
val clkdomain = Module(new el2_lsu_clkdomain )
|
||||||
|
val bus_intf = Module(new el2_lsu_bus_intf )
|
||||||
|
|
||||||
|
val lsu_raw_fwd_lo_m = stbuf.io.stbuf_fwdbyteen_lo_m.orR
|
||||||
|
val lsu_raw_fwd_hi_m = stbuf.io.stbuf_fwdbyteen_hi_m.orR
|
||||||
|
|
||||||
|
// block stores in decode - for either bus or stbuf reasons
|
||||||
|
io.lsu_store_stall_any := stbuf.io.lsu_stbuf_full_any | bus_intf.io.lsu_bus_buffer_full_any | dccm_ctl.io.ld_single_ecc_error_r_ff
|
||||||
|
io.lsu_load_stall_any := bus_intf.io.lsu_bus_buffer_full_any | dccm_ctl.io.ld_single_ecc_error_r_ff
|
||||||
|
io.lsu_fastint_stall_any := dccm_ctl.io.ld_single_ecc_error_r // Stall the fastint in decode-1 stage
|
||||||
|
|
||||||
|
// Ready to accept dma trxns
|
||||||
|
// There can't be any inpipe forwarding from non-dma packet to dma packet since they can be flushed so we can't have st in r when dma is in m
|
||||||
|
val dma_mem_tag_d = io.dma_mem_tag
|
||||||
|
val ldst_nodma_mtor = lsu_lsc_ctl.io.lsu_pkt_m.valid & !lsu_lsc_ctl.io.lsu_pkt_m.dma & (lsu_lsc_ctl.io.addr_in_dccm_m | lsu_lsc_ctl.io.addr_in_pic_m) & lsu_lsc_ctl.io.lsu_pkt_m.store
|
||||||
|
io.dccm_ready := !(io.dec_lsu_valid_raw_d | ldst_nodma_mtor | dccm_ctl.io.ld_single_ecc_error_r_ff)
|
||||||
|
val dma_dccm_wen = io.dma_dccm_req & io.dma_mem_write & lsu_lsc_ctl.io.addr_in_dccm_d
|
||||||
|
val dma_pic_wen = io.dma_dccm_req & io.dma_mem_write & lsu_lsc_ctl.io.addr_in_pic_d
|
||||||
|
dma_dccm_wdata := io.dma_mem_wdata >> Cat(io.dma_mem_addr(2,0), 0.U(3.W)) // Shift the dma data to lower bits to make it consistent to lsu stores
|
||||||
|
dma_dccm_wdata_hi := dma_dccm_wdata(63,32)
|
||||||
|
dma_dccm_wdata_lo := dma_dccm_wdata(31,0)
|
||||||
|
|
||||||
|
val flush_m_up = io.dec_tlu_flush_lower_r
|
||||||
|
val flush_r = io.dec_tlu_i0_kill_writeb_r
|
||||||
|
|
||||||
|
// lsu halt idle. This is used for entering the halt mode. Also, DMA accesses are allowed during fence.
|
||||||
|
// Indicates non-idle if there is a instruction valid in d-r or read/write buffers are non-empty since they can come with error
|
||||||
|
// Store buffer now have only non-dma dccm stores
|
||||||
|
// stbuf_empty not needed since it has only dccm stores
|
||||||
|
io.lsu_idle_any := !((lsu_lsc_ctl.io.lsu_pkt_m.valid & !lsu_lsc_ctl.io.lsu_pkt_m.dma) | (lsu_lsc_ctl.io.lsu_pkt_r.valid & !lsu_lsc_ctl.io.lsu_pkt_r.dma)) & bus_intf.io.lsu_bus_buffer_empty_any & bus_intf.io.lsu_bus_idle_any
|
||||||
|
// Instantiate the store buffer
|
||||||
|
val store_stbuf_reqvld_r = lsu_lsc_ctl.io.lsu_pkt_r.valid & lsu_lsc_ctl.io.lsu_pkt_r.store & lsu_lsc_ctl.io.addr_in_dccm_r & !flush_r & !lsu_lsc_ctl.io.lsu_pkt_r.dma
|
||||||
|
// Disable Forwarding for now
|
||||||
|
val lsu_cmpen_m = lsu_lsc_ctl.io.lsu_pkt_m.valid & (lsu_lsc_ctl.io.lsu_pkt_m.load | lsu_lsc_ctl.io.lsu_pkt_m.store) & (lsu_lsc_ctl.io.addr_in_dccm_m | lsu_lsc_ctl.io.addr_in_pic_m)
|
||||||
|
// Bus signals
|
||||||
|
val lsu_busreq_m = lsu_lsc_ctl.io.lsu_pkt_m.valid & ((lsu_lsc_ctl.io.lsu_pkt_m.load | lsu_lsc_ctl.io.lsu_pkt_m.store) & lsu_lsc_ctl.io.addr_external_m) & !flush_m_up & !lsu_lsc_ctl.io.lsu_exc_m & !lsu_lsc_ctl.io.lsu_pkt_m.fast_int
|
||||||
|
// PMU signals
|
||||||
|
io.lsu_pmu_misaligned_m := lsu_lsc_ctl.io.lsu_pkt_m.valid & ((lsu_lsc_ctl.io.lsu_pkt_m.half & lsu_lsc_ctl.io.lsu_addr_m(0)) | (lsu_lsc_ctl.io.lsu_pkt_m.word & lsu_lsc_ctl.io.lsu_addr_m(1,0).orR))
|
||||||
|
io.lsu_pmu_load_external_m := lsu_lsc_ctl.io.lsu_pkt_m.valid & lsu_lsc_ctl.io.lsu_pkt_m.load & lsu_lsc_ctl.io.addr_external_m
|
||||||
|
io.lsu_pmu_store_external_m := lsu_lsc_ctl.io.lsu_pkt_m.valid & lsu_lsc_ctl.io.lsu_pkt_m.store & lsu_lsc_ctl.io.addr_external_m
|
||||||
|
|
||||||
|
//LSU_LSC_Control
|
||||||
|
//Inputs
|
||||||
|
lsu_lsc_ctl.io.lsu_c1_m_clk := clkdomain.io.lsu_c1_m_clk
|
||||||
|
lsu_lsc_ctl.io.lsu_c1_r_clk := clkdomain.io.lsu_c1_r_clk
|
||||||
|
lsu_lsc_ctl.io.lsu_c2_m_clk := clkdomain.io.lsu_c2_m_clk
|
||||||
|
lsu_lsc_ctl.io.lsu_c2_r_clk := clkdomain.io.lsu_c2_r_clk
|
||||||
|
lsu_lsc_ctl.io.lsu_store_c1_m_clk := clkdomain.io.lsu_store_c1_m_clk
|
||||||
|
lsu_lsc_ctl.io.lsu_ld_data_r := dccm_ctl.io.lsu_ld_data_r
|
||||||
|
lsu_lsc_ctl.io.lsu_ld_data_corr_r := dccm_ctl.io.lsu_ld_data_corr_r
|
||||||
|
lsu_lsc_ctl.io.lsu_single_ecc_error_r := ecc.io.lsu_single_ecc_error_r
|
||||||
|
lsu_lsc_ctl.io.lsu_double_ecc_error_r := ecc.io.lsu_double_ecc_error_r
|
||||||
|
lsu_lsc_ctl.io.lsu_ld_data_m := dccm_ctl.io.lsu_ld_data_m
|
||||||
|
lsu_lsc_ctl.io.lsu_single_ecc_error_m := ecc.io.lsu_single_ecc_error_m
|
||||||
|
lsu_lsc_ctl.io.lsu_double_ecc_error_m := ecc.io.lsu_double_ecc_error_m
|
||||||
|
lsu_lsc_ctl.io.flush_m_up := flush_m_up
|
||||||
|
lsu_lsc_ctl.io.flush_r := flush_r
|
||||||
|
lsu_lsc_ctl.io.exu_lsu_rs1_d := io.exu_lsu_rs1_d
|
||||||
|
lsu_lsc_ctl.io.exu_lsu_rs2_d := io.exu_lsu_rs2_d
|
||||||
|
lsu_lsc_ctl.io.lsu_p := io.lsu_p
|
||||||
|
lsu_lsc_ctl.io.dec_lsu_valid_raw_d := io.dec_lsu_valid_raw_d
|
||||||
|
lsu_lsc_ctl.io.dec_lsu_offset_d := io.dec_lsu_offset_d
|
||||||
|
lsu_lsc_ctl.io.picm_mask_data_m := dccm_ctl.io.picm_mask_data_m
|
||||||
|
lsu_lsc_ctl.io.bus_read_data_m := bus_intf.io.bus_read_data_m
|
||||||
|
lsu_lsc_ctl.io.dma_dccm_req := io.dma_dccm_req
|
||||||
|
lsu_lsc_ctl.io.dma_mem_addr := io.dma_mem_addr
|
||||||
|
lsu_lsc_ctl.io.dma_mem_sz := io.dma_mem_sz
|
||||||
|
lsu_lsc_ctl.io.dma_mem_write := io.dma_mem_write
|
||||||
|
lsu_lsc_ctl.io.dma_mem_wdata := io.dma_mem_wdata
|
||||||
|
lsu_lsc_ctl.io.dec_tlu_mrac_ff := io.dec_tlu_mrac_ff
|
||||||
|
lsu_lsc_ctl.io.scan_mode := io.scan_mode
|
||||||
|
//Outputs
|
||||||
|
|
||||||
|
io.lsu_single_ecc_error_incr := lsu_lsc_ctl.io.lsu_single_ecc_error_incr
|
||||||
|
io.lsu_error_pkt_r := lsu_lsc_ctl.io.lsu_error_pkt_r
|
||||||
|
io.lsu_fir_addr := lsu_lsc_ctl.io.lsu_fir_addr
|
||||||
|
io.lsu_fir_error := lsu_lsc_ctl.io.lsu_fir_error
|
||||||
|
// DCCM Control
|
||||||
|
//Inputs
|
||||||
|
dccm_ctl.io.lsu_c2_m_clk := clkdomain.io.lsu_c2_m_clk
|
||||||
|
dccm_ctl.io.lsu_c2_r_clk := clkdomain.io.lsu_c2_m_clk
|
||||||
|
dccm_ctl.io.lsu_free_c2_clk := clkdomain.io.lsu_c2_r_clk
|
||||||
|
dccm_ctl.io.lsu_c1_r_clk := clkdomain.io.lsu_free_c2_clk
|
||||||
|
dccm_ctl.io.lsu_store_c1_r_clk := clkdomain.io.lsu_c1_r_clk
|
||||||
|
//dccm_ctl.io.clk := clock
|
||||||
|
dccm_ctl.io.lsu_pkt_d := lsu_lsc_ctl.io.lsu_pkt_d
|
||||||
|
dccm_ctl.io.lsu_pkt_m := lsu_lsc_ctl.io.lsu_pkt_m
|
||||||
|
dccm_ctl.io.lsu_pkt_r := lsu_lsc_ctl.io.lsu_pkt_r
|
||||||
|
dccm_ctl.io.addr_in_dccm_d := lsu_lsc_ctl.io.addr_in_dccm_d
|
||||||
|
dccm_ctl.io.addr_in_dccm_m := lsu_lsc_ctl.io.addr_in_dccm_m
|
||||||
|
dccm_ctl.io.addr_in_dccm_r := lsu_lsc_ctl.io.addr_in_dccm_r
|
||||||
|
dccm_ctl.io.addr_in_pic_d := lsu_lsc_ctl.io.addr_in_pic_d
|
||||||
|
dccm_ctl.io.addr_in_pic_m := lsu_lsc_ctl.io.addr_in_pic_m
|
||||||
|
dccm_ctl.io.addr_in_pic_r := lsu_lsc_ctl.io.addr_in_pic_r
|
||||||
|
dccm_ctl.io.lsu_raw_fwd_lo_r := lsu_raw_fwd_lo_r
|
||||||
|
dccm_ctl.io.lsu_raw_fwd_hi_r := lsu_raw_fwd_hi_r
|
||||||
|
dccm_ctl.io.lsu_commit_r := lsu_lsc_ctl.io.lsu_commit_r
|
||||||
|
dccm_ctl.io.lsu_addr_d := lsu_lsc_ctl.io.lsu_addr_d
|
||||||
|
dccm_ctl.io.lsu_addr_m := lsu_lsc_ctl.io.lsu_addr_m
|
||||||
|
dccm_ctl.io.lsu_addr_r := lsu_lsc_ctl.io.lsu_addr_r
|
||||||
|
dccm_ctl.io.end_addr_d := lsu_lsc_ctl.io.end_addr_d
|
||||||
|
dccm_ctl.io.end_addr_m := lsu_lsc_ctl.io.end_addr_m
|
||||||
|
dccm_ctl.io.end_addr_r := lsu_lsc_ctl.io.end_addr_r
|
||||||
|
dccm_ctl.io.stbuf_reqvld_any := stbuf.io.stbuf_reqvld_any
|
||||||
|
dccm_ctl.io.stbuf_addr_any := stbuf.io.stbuf_addr_any
|
||||||
|
dccm_ctl.io.stbuf_data_any := stbuf.io.stbuf_data_any
|
||||||
|
dccm_ctl.io.stbuf_ecc_any := ecc.io.stbuf_ecc_any
|
||||||
|
dccm_ctl.io.stbuf_fwddata_hi_m := stbuf.io.stbuf_fwddata_hi_m
|
||||||
|
dccm_ctl.io.stbuf_fwddata_lo_m := stbuf.io.stbuf_fwddata_lo_m
|
||||||
|
dccm_ctl.io.stbuf_fwdbyteen_lo_m := stbuf.io.stbuf_fwdbyteen_lo_m
|
||||||
|
dccm_ctl.io.stbuf_fwdbyteen_hi_m := stbuf.io.stbuf_fwdbyteen_hi_m
|
||||||
|
dccm_ctl.io.lsu_double_ecc_error_r := ecc.io.lsu_double_ecc_error_r
|
||||||
|
dccm_ctl.io.single_ecc_error_hi_r := ecc.io.single_ecc_error_hi_r
|
||||||
|
dccm_ctl.io.single_ecc_error_lo_r := ecc.io.single_ecc_error_lo_r
|
||||||
|
dccm_ctl.io.sec_data_hi_r := ecc.io.sec_data_hi_r
|
||||||
|
dccm_ctl.io.sec_data_lo_r := ecc.io.sec_data_lo_r
|
||||||
|
dccm_ctl.io.sec_data_hi_r_ff := ecc.io.sec_data_hi_r_ff
|
||||||
|
dccm_ctl.io.sec_data_lo_r_ff := ecc.io.sec_data_lo_r_ff
|
||||||
|
dccm_ctl.io.sec_data_ecc_hi_r_ff := ecc.io.sec_data_ecc_hi_r_ff
|
||||||
|
dccm_ctl.io.sec_data_ecc_lo_r_ff := ecc.io.sec_data_ecc_lo_r_ff
|
||||||
|
dccm_ctl.io.lsu_double_ecc_error_m := ecc.io.lsu_double_ecc_error_m
|
||||||
|
dccm_ctl.io.sec_data_hi_m := ecc.io.sec_data_hi_m
|
||||||
|
dccm_ctl.io.sec_data_lo_m := ecc.io.sec_data_lo_m
|
||||||
|
dccm_ctl.io.store_data_m := lsu_lsc_ctl.io.store_data_m
|
||||||
|
dccm_ctl.io.dma_dccm_wen := dma_dccm_wen
|
||||||
|
dccm_ctl.io.dma_pic_wen := dma_pic_wen
|
||||||
|
dccm_ctl.io.dma_mem_tag_m := dma_mem_tag_m
|
||||||
|
dccm_ctl.io.dma_mem_addr := io.dma_mem_addr
|
||||||
|
dccm_ctl.io.dma_mem_wdata := io.dma_mem_wdata
|
||||||
|
dccm_ctl.io.dma_dccm_wdata_lo := dma_dccm_wdata_lo
|
||||||
|
dccm_ctl.io.dma_dccm_wdata_hi := dma_dccm_wdata_hi
|
||||||
|
dccm_ctl.io.dma_dccm_wdata_ecc_hi := ecc.io.dma_dccm_wdata_ecc_hi
|
||||||
|
dccm_ctl.io.dma_dccm_wdata_ecc_lo := ecc.io.dma_dccm_wdata_ecc_lo
|
||||||
|
dccm_ctl.io.dccm_rd_data_lo := io.dccm_rd_data_lo
|
||||||
|
dccm_ctl.io.dccm_rd_data_hi := io.dccm_rd_data_hi
|
||||||
|
dccm_ctl.io.picm_rd_data := io.picm_rd_data
|
||||||
|
dccm_ctl.io.scan_mode := io.scan_mode
|
||||||
|
//Outputs
|
||||||
|
io.dccm_dma_rvalid := dccm_ctl.io.dccm_dma_rvalid
|
||||||
|
io.dccm_dma_ecc_error := dccm_ctl.io.dccm_dma_ecc_error
|
||||||
|
io.dccm_dma_rtag := dccm_ctl.io.dccm_dma_rtag
|
||||||
|
io.dccm_dma_rdata := dccm_ctl.io.dccm_dma_rdata
|
||||||
|
io.dccm_wren := dccm_ctl.io.dccm_wren
|
||||||
|
io.dccm_rden := dccm_ctl.io.dccm_rden
|
||||||
|
io.dccm_wr_addr_lo := dccm_ctl.io.dccm_wr_addr_lo
|
||||||
|
io.dccm_wr_data_lo := dccm_ctl.io.dccm_wr_data_lo
|
||||||
|
io.dccm_rd_addr_lo := dccm_ctl.io.dccm_rd_addr_lo
|
||||||
|
io.dccm_wr_addr_hi := dccm_ctl.io.dccm_wr_addr_hi
|
||||||
|
io.dccm_wr_data_hi := dccm_ctl.io.dccm_wr_data_hi
|
||||||
|
io.dccm_rd_addr_hi := dccm_ctl.io.dccm_rd_addr_hi
|
||||||
|
io.picm_wren := dccm_ctl.io.picm_wren
|
||||||
|
io.picm_rden := dccm_ctl.io.picm_rden
|
||||||
|
io.picm_mken := dccm_ctl.io.picm_mken
|
||||||
|
io.picm_rdaddr := dccm_ctl.io.picm_rdaddr
|
||||||
|
io.picm_wraddr := dccm_ctl.io.picm_wraddr
|
||||||
|
io.picm_wr_data := dccm_ctl.io.picm_wr_data
|
||||||
|
//Store Buffer
|
||||||
|
//Inputs
|
||||||
|
stbuf.io.lsu_c1_m_clk := clkdomain.io.lsu_c1_m_clk
|
||||||
|
stbuf.io.lsu_c1_r_clk := clkdomain.io.lsu_c1_m_clk
|
||||||
|
stbuf.io.lsu_stbuf_c1_clk := clkdomain.io.lsu_stbuf_c1_clk
|
||||||
|
stbuf.io.lsu_free_c2_clk := clkdomain.io.lsu_free_c2_clk
|
||||||
|
stbuf.io.lsu_pkt_m := lsu_lsc_ctl.io.lsu_pkt_m
|
||||||
|
stbuf.io.lsu_pkt_r := lsu_lsc_ctl.io.lsu_pkt_r
|
||||||
|
stbuf.io.store_stbuf_reqvld_r := store_stbuf_reqvld_r
|
||||||
|
stbuf.io.lsu_commit_r := lsu_lsc_ctl.io.lsu_commit_r
|
||||||
|
stbuf.io.dec_lsu_valid_raw_d := io.dec_lsu_valid_raw_d
|
||||||
|
stbuf.io.store_data_hi_r := dccm_ctl.io.store_data_hi_r
|
||||||
|
stbuf.io.store_data_lo_r := dccm_ctl.io.store_data_lo_r
|
||||||
|
stbuf.io.store_datafn_hi_r := dccm_ctl.io.store_datafn_hi_r
|
||||||
|
stbuf.io.store_datafn_lo_r := dccm_ctl.io.store_datafn_lo_r
|
||||||
|
stbuf.io.lsu_stbuf_commit_any := dccm_ctl.io.lsu_stbuf_commit_any
|
||||||
|
stbuf.io.lsu_addr_d := lsu_lsc_ctl.io.lsu_addr_d
|
||||||
|
stbuf.io.lsu_addr_m := lsu_lsc_ctl.io.lsu_addr_m
|
||||||
|
stbuf.io.lsu_addr_r := lsu_lsc_ctl.io.lsu_addr_r
|
||||||
|
stbuf.io.end_addr_d := lsu_lsc_ctl.io.end_addr_d
|
||||||
|
stbuf.io.end_addr_m := lsu_lsc_ctl.io.end_addr_m
|
||||||
|
stbuf.io.end_addr_r := lsu_lsc_ctl.io.end_addr_r
|
||||||
|
stbuf.io.addr_in_dccm_m := lsu_lsc_ctl.io.addr_in_dccm_m
|
||||||
|
stbuf.io.addr_in_dccm_r := lsu_lsc_ctl.io.addr_in_dccm_r
|
||||||
|
stbuf.io.lsu_cmpen_m := lsu_cmpen_m
|
||||||
|
stbuf.io.scan_mode := io.scan_mode
|
||||||
|
|
||||||
|
// ECC
|
||||||
|
//Inputs
|
||||||
|
ecc.io.lsu_c2_r_clk := clkdomain.io.lsu_c2_r_clk
|
||||||
|
ecc.io.lsu_pkt_m := lsu_lsc_ctl.io.lsu_pkt_m
|
||||||
|
ecc.io.lsu_pkt_r := lsu_lsc_ctl.io.lsu_pkt_r
|
||||||
|
ecc.io.stbuf_data_any := stbuf.io.stbuf_data_any
|
||||||
|
ecc.io.dec_tlu_core_ecc_disable := io.dec_tlu_core_ecc_disable
|
||||||
|
ecc.io.lsu_dccm_rden_r := dccm_ctl.io.lsu_dccm_rden_r
|
||||||
|
ecc.io.addr_in_dccm_r := lsu_lsc_ctl.io.addr_in_dccm_r
|
||||||
|
ecc.io.lsu_addr_r := lsu_lsc_ctl.io.lsu_addr_r
|
||||||
|
ecc.io.end_addr_r := lsu_lsc_ctl.io.end_addr_r
|
||||||
|
ecc.io.lsu_addr_m := lsu_lsc_ctl.io.lsu_addr_m
|
||||||
|
ecc.io.end_addr_m := lsu_lsc_ctl.io.end_addr_m
|
||||||
|
ecc.io.dccm_rdata_hi_r := dccm_ctl.io.dccm_rdata_hi_r
|
||||||
|
ecc.io.dccm_rdata_lo_r := dccm_ctl.io.dccm_rdata_lo_r
|
||||||
|
ecc.io.dccm_rdata_hi_m := dccm_ctl.io.dccm_rdata_hi_m
|
||||||
|
ecc.io.dccm_rdata_lo_m := dccm_ctl.io.dccm_rdata_lo_m
|
||||||
|
ecc.io.dccm_data_ecc_hi_r := dccm_ctl.io.dccm_data_ecc_hi_r
|
||||||
|
ecc.io.dccm_data_ecc_lo_r := dccm_ctl.io.dccm_data_ecc_lo_r
|
||||||
|
ecc.io.dccm_data_ecc_hi_m := dccm_ctl.io.dccm_data_ecc_hi_m
|
||||||
|
ecc.io.dccm_data_ecc_lo_m := dccm_ctl.io.dccm_data_ecc_lo_m
|
||||||
|
ecc.io.ld_single_ecc_error_r := dccm_ctl.io.ld_single_ecc_error_r
|
||||||
|
ecc.io.ld_single_ecc_error_r_ff := dccm_ctl.io.ld_single_ecc_error_r_ff
|
||||||
|
ecc.io.lsu_dccm_rden_m := dccm_ctl.io.lsu_dccm_rden_m
|
||||||
|
ecc.io.addr_in_dccm_m := lsu_lsc_ctl.io.addr_in_dccm_m
|
||||||
|
ecc.io.dma_dccm_wen := dma_dccm_wen
|
||||||
|
ecc.io.dma_dccm_wdata_lo := dma_dccm_wdata_lo
|
||||||
|
ecc.io.dma_dccm_wdata_hi := dma_dccm_wdata_hi
|
||||||
|
ecc.io.scan_mode := io.scan_mode
|
||||||
|
|
||||||
|
//Trigger
|
||||||
|
//Inputs
|
||||||
|
trigger.io.trigger_pkt_any := io.trigger_pkt_any
|
||||||
|
trigger.io.lsu_pkt_m := lsu_lsc_ctl.io.lsu_pkt_m
|
||||||
|
trigger.io.lsu_addr_m := lsu_lsc_ctl.io.lsu_addr_m
|
||||||
|
trigger.io.store_data_m := lsu_lsc_ctl.io.store_data_m
|
||||||
|
//Outputs
|
||||||
|
io.lsu_trigger_match_m :=trigger.io.lsu_trigger_match_m
|
||||||
|
|
||||||
|
//Clock Domain
|
||||||
|
//Inputs
|
||||||
|
clkdomain.io.free_clk := io.free_clk
|
||||||
|
clkdomain.io.clk_override := io.clk_override
|
||||||
|
clkdomain.io.addr_in_dccm_m := lsu_lsc_ctl.io.addr_in_dccm_m
|
||||||
|
clkdomain.io.dma_dccm_req := io.dma_dccm_req
|
||||||
|
clkdomain.io.ldst_stbuf_reqvld_r := stbuf.io.ldst_stbuf_reqvld_r
|
||||||
|
clkdomain.io.stbuf_reqvld_any := stbuf.io.stbuf_reqvld_any
|
||||||
|
clkdomain.io.stbuf_reqvld_flushed_any := stbuf.io.stbuf_reqvld_flushed_any
|
||||||
|
clkdomain.io.lsu_busreq_r := bus_intf.io.lsu_busreq_r
|
||||||
|
clkdomain.io.lsu_bus_buffer_pend_any := bus_intf.io.lsu_bus_buffer_pend_any
|
||||||
|
clkdomain.io.lsu_bus_buffer_empty_any := bus_intf.io.lsu_bus_buffer_empty_any
|
||||||
|
clkdomain.io.lsu_stbuf_empty_any := stbuf.io.lsu_stbuf_empty_any
|
||||||
|
clkdomain.io.lsu_bus_clk_en := io.lsu_bus_clk_en
|
||||||
|
clkdomain.io.lsu_p := io.lsu_p
|
||||||
|
clkdomain.io.lsu_pkt_d := lsu_lsc_ctl.io.lsu_pkt_d
|
||||||
|
clkdomain.io.lsu_pkt_m := lsu_lsc_ctl.io.lsu_pkt_m
|
||||||
|
clkdomain.io.lsu_pkt_r := lsu_lsc_ctl.io.lsu_pkt_r
|
||||||
|
clkdomain.io.scan_mode := io.scan_mode
|
||||||
|
|
||||||
|
//Bus Interface
|
||||||
|
//Inputs
|
||||||
|
bus_intf.io.scan_mode := io.scan_mode
|
||||||
|
bus_intf.io.dec_tlu_external_ldfwd_disable := io.dec_tlu_external_ldfwd_disable
|
||||||
|
bus_intf.io.dec_tlu_wb_coalescing_disable := io.dec_tlu_wb_coalescing_disable
|
||||||
|
bus_intf.io.dec_tlu_sideeffect_posted_disable := io.dec_tlu_sideeffect_posted_disable
|
||||||
|
bus_intf.io.lsu_c1_m_clk := clkdomain.io.lsu_c1_m_clk
|
||||||
|
bus_intf.io.lsu_c1_r_clk := clkdomain.io.lsu_c1_r_clk
|
||||||
|
bus_intf.io.lsu_c2_r_clk := clkdomain.io.lsu_c2_r_clk
|
||||||
|
bus_intf.io.lsu_bus_ibuf_c1_clk := clkdomain.io.lsu_bus_ibuf_c1_clk
|
||||||
|
bus_intf.io.lsu_bus_obuf_c1_clk := clkdomain.io.lsu_bus_obuf_c1_clk
|
||||||
|
bus_intf.io.lsu_bus_buf_c1_clk := clkdomain.io.lsu_bus_buf_c1_clk
|
||||||
|
bus_intf.io.lsu_free_c2_clk := clkdomain.io.lsu_free_c2_clk
|
||||||
|
bus_intf.io.free_clk := io.free_clk
|
||||||
|
bus_intf.io.lsu_busm_clk := clkdomain.io.lsu_busm_clk
|
||||||
|
bus_intf.io.dec_lsu_valid_raw_d := io.dec_lsu_valid_raw_d
|
||||||
|
bus_intf.io.lsu_busreq_m := lsu_busreq_m
|
||||||
|
bus_intf.io.lsu_addr_d := lsu_lsc_ctl.io.lsu_addr_d
|
||||||
|
bus_intf.io.lsu_addr_m := lsu_lsc_ctl.io.lsu_addr_m
|
||||||
|
bus_intf.io.lsu_addr_r := lsu_lsc_ctl.io.lsu_addr_r
|
||||||
|
bus_intf.io.end_addr_d := lsu_lsc_ctl.io.end_addr_d
|
||||||
|
bus_intf.io.end_addr_m := lsu_lsc_ctl.io.end_addr_m
|
||||||
|
bus_intf.io.end_addr_r := lsu_lsc_ctl.io.end_addr_r
|
||||||
|
bus_intf.io.store_data_r := dccm_ctl.io.store_data_r
|
||||||
|
bus_intf.io.lsu_pkt_m <> lsu_lsc_ctl.io.lsu_pkt_m
|
||||||
|
bus_intf.io.lsu_pkt_r <> lsu_lsc_ctl.io.lsu_pkt_r
|
||||||
|
bus_intf.io.dec_tlu_force_halt := io.dec_tlu_force_halt
|
||||||
|
bus_intf.io.lsu_commit_r := lsu_lsc_ctl.io.lsu_commit_r
|
||||||
|
bus_intf.io.is_sideeffects_m := lsu_lsc_ctl.io.is_sideeffects_m
|
||||||
|
bus_intf.io.flush_m_up := flush_m_up
|
||||||
|
bus_intf.io.flush_r := flush_r
|
||||||
|
//Outputs
|
||||||
|
|
||||||
|
io.lsu_imprecise_error_load_any := bus_intf.io.lsu_imprecise_error_load_any
|
||||||
|
io.lsu_imprecise_error_store_any := bus_intf.io.lsu_imprecise_error_store_any
|
||||||
|
io.lsu_imprecise_error_addr_any := bus_intf.io.lsu_imprecise_error_addr_any
|
||||||
|
io.lsu_nonblock_load_valid_m := bus_intf.io.lsu_nonblock_load_valid_m
|
||||||
|
io.lsu_nonblock_load_tag_m := bus_intf.io.lsu_nonblock_load_tag_m
|
||||||
|
io.lsu_nonblock_load_inv_r := bus_intf.io.lsu_nonblock_load_inv_r
|
||||||
|
io.lsu_nonblock_load_inv_tag_r := bus_intf.io.lsu_nonblock_load_inv_tag_r
|
||||||
|
io.lsu_nonblock_load_data_valid := bus_intf.io.lsu_nonblock_load_data_valid
|
||||||
|
io.lsu_nonblock_load_data_error := bus_intf.io.lsu_nonblock_load_data_error
|
||||||
|
io.lsu_nonblock_load_data_tag := bus_intf.io.lsu_nonblock_load_data_tag
|
||||||
|
io.lsu_nonblock_load_data := bus_intf.io.lsu_nonblock_load_data
|
||||||
|
io.lsu_pmu_bus_trxn := bus_intf.io.lsu_pmu_bus_trxn
|
||||||
|
io.lsu_pmu_bus_misaligned := bus_intf.io.lsu_pmu_bus_misaligned
|
||||||
|
io.lsu_pmu_bus_error := bus_intf.io.lsu_pmu_bus_error
|
||||||
|
io.lsu_pmu_bus_busy := bus_intf.io.lsu_pmu_bus_busy
|
||||||
|
io.lsu_axi_awvalid := bus_intf.io.lsu_axi_awvalid
|
||||||
|
bus_intf.io.lsu_axi_awready := io.lsu_axi_awready
|
||||||
|
io.lsu_axi_awid := bus_intf.io.lsu_axi_awid
|
||||||
|
io.lsu_axi_awaddr := bus_intf.io.lsu_axi_awaddr
|
||||||
|
io.lsu_axi_awregion := bus_intf.io.lsu_axi_awregion
|
||||||
|
io.lsu_axi_awlen := bus_intf.io.lsu_axi_awlen
|
||||||
|
io.lsu_axi_awsize := bus_intf.io.lsu_axi_awsize
|
||||||
|
io.lsu_axi_awburst := bus_intf.io.lsu_axi_awburst
|
||||||
|
io.lsu_axi_awlock := bus_intf.io.lsu_axi_awlock
|
||||||
|
io.lsu_axi_awcache := bus_intf.io.lsu_axi_awcache
|
||||||
|
io.lsu_axi_awprot := bus_intf.io.lsu_axi_awprot
|
||||||
|
io.lsu_axi_awqos := bus_intf.io.lsu_axi_awqos
|
||||||
|
io.lsu_axi_wvalid := bus_intf.io.lsu_axi_wvalid
|
||||||
|
bus_intf.io.lsu_axi_wready := io.lsu_axi_wready
|
||||||
|
io.lsu_axi_wdata := bus_intf.io.lsu_axi_wdata
|
||||||
|
io.lsu_axi_wstrb := bus_intf.io.lsu_axi_wstrb
|
||||||
|
io.lsu_axi_wlast := bus_intf.io.lsu_axi_wlast
|
||||||
|
bus_intf.io.lsu_axi_bvalid := io.lsu_axi_bvalid
|
||||||
|
io.lsu_axi_bready := bus_intf.io.lsu_axi_bready
|
||||||
|
bus_intf.io.lsu_axi_bresp := io.lsu_axi_bresp
|
||||||
|
bus_intf.io.lsu_axi_bid := io.lsu_axi_bid
|
||||||
|
io.lsu_axi_arvalid := bus_intf.io.lsu_axi_arvalid
|
||||||
|
bus_intf.io.lsu_axi_arready := io.lsu_axi_arready
|
||||||
|
io.lsu_axi_arid := bus_intf.io.lsu_axi_arid
|
||||||
|
io.lsu_axi_araddr := bus_intf.io.lsu_axi_araddr
|
||||||
|
io.lsu_axi_arregion := bus_intf.io.lsu_axi_arregion
|
||||||
|
io.lsu_axi_arlen := bus_intf.io.lsu_axi_arlen
|
||||||
|
io.lsu_axi_arsize := bus_intf.io.lsu_axi_arsize
|
||||||
|
io.lsu_axi_arburst := bus_intf.io.lsu_axi_arburst
|
||||||
|
io.lsu_axi_arlock := bus_intf.io.lsu_axi_arlock
|
||||||
|
io.lsu_axi_arcache := bus_intf.io.lsu_axi_arcache
|
||||||
|
io.lsu_axi_arprot := bus_intf.io.lsu_axi_arprot
|
||||||
|
io.lsu_axi_arqos := bus_intf.io.lsu_axi_arqos
|
||||||
|
bus_intf.io.lsu_axi_rvalid := io.lsu_axi_rvalid
|
||||||
|
io.lsu_axi_rready := bus_intf.io.lsu_axi_rready
|
||||||
|
bus_intf.io.lsu_axi_rid := io.lsu_axi_rid
|
||||||
|
bus_intf.io.lsu_axi_rdata := io.lsu_axi_rdata
|
||||||
|
bus_intf.io.lsu_axi_rresp := io.lsu_axi_rresp
|
||||||
|
bus_intf.io.lsu_axi_rlast := io.lsu_axi_rlast
|
||||||
|
bus_intf.io.lsu_bus_clk_en := io.lsu_bus_clk_en
|
||||||
|
|
||||||
|
withClock(clkdomain.io.lsu_c1_m_clk){dma_mem_tag_m := RegNext(dma_mem_tag_d,0.U)}
|
||||||
|
withClock(clkdomain.io.lsu_c2_r_clk){lsu_raw_fwd_hi_r := RegNext(lsu_raw_fwd_hi_m,0.U)}
|
||||||
|
withClock(clkdomain.io.lsu_c2_r_clk){lsu_raw_fwd_lo_r := RegNext(lsu_raw_fwd_lo_m,0.U)}
|
||||||
|
|
||||||
|
}
|
||||||
|
object main_lsu_top extends App{
|
||||||
|
println("Generate Verilog")
|
||||||
|
println((new chisel3.stage.ChiselStage).emitVerilog(new el2_lsu))
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,126 @@
|
||||||
|
package lsu
|
||||||
|
|
||||||
|
import include._
|
||||||
|
import lib._
|
||||||
|
import chisel3._
|
||||||
|
import chisel3.util._
|
||||||
|
import chisel3.experimental.chiselName
|
||||||
|
|
||||||
|
@chiselName
|
||||||
|
class el2_lsu_addrcheck extends Module with RequireAsyncReset with el2_lib
|
||||||
|
{val io = IO(new Bundle{
|
||||||
|
val lsu_c2_m_clk = Input(Clock())
|
||||||
|
|
||||||
|
val start_addr_d = Input(UInt(32.W))
|
||||||
|
val end_addr_d = Input(UInt(32.W))
|
||||||
|
val lsu_pkt_d = Input(new el2_lsu_pkt_t)
|
||||||
|
val dec_tlu_mrac_ff = Input(UInt(32.W))
|
||||||
|
val rs1_region_d = Input(UInt(4.W))
|
||||||
|
val rs1_d = Input(UInt(32.W))
|
||||||
|
|
||||||
|
|
||||||
|
val is_sideeffects_m = Output(UInt(1.W))
|
||||||
|
val addr_in_dccm_d = Output(UInt(1.W))
|
||||||
|
val addr_in_pic_d = Output(UInt(1.W))
|
||||||
|
val addr_external_d = Output(UInt(1.W))
|
||||||
|
val access_fault_d = Output(UInt(1.W))
|
||||||
|
val misaligned_fault_d = Output(UInt(1.W))
|
||||||
|
val exc_mscause_d = Output(UInt(4.W))
|
||||||
|
val fir_dccm_access_error_d = Output(UInt(1.W))
|
||||||
|
val fir_nondccm_access_error_d = Output(UInt(1.W))
|
||||||
|
val scan_mode = Input(UInt(1.W))})
|
||||||
|
|
||||||
|
//DCCM check
|
||||||
|
// Start address check
|
||||||
|
// Gen_dccm_enable
|
||||||
|
val (start_addr_in_dccm_d,start_addr_in_dccm_region_d) = if(DCCM_ENABLE) rvrangecheck_ch(io.start_addr_d,DCCM_SADR.U,DCCM_SIZE) else (0.U,0.U)
|
||||||
|
// End address check
|
||||||
|
val (end_addr_in_dccm_d ,end_addr_in_dccm_region_d) = if(DCCM_ENABLE) rvrangecheck_ch(io.end_addr_d,DCCM_SADR.U,DCCM_SIZE) else (0.U,0.U)
|
||||||
|
|
||||||
|
val addr_in_iccm = WireInit(0.U(1.W))
|
||||||
|
if(ICCM_ENABLE ){ //check_iccm
|
||||||
|
addr_in_iccm := (io.start_addr_d(31,28) === ICCM_REGION.U)
|
||||||
|
}
|
||||||
|
else{
|
||||||
|
addr_in_iccm := 1.U
|
||||||
|
}
|
||||||
|
|
||||||
|
//PIC memory check
|
||||||
|
//start address check
|
||||||
|
val (start_addr_in_pic_d,start_addr_in_pic_region_d) = rvrangecheck_ch(io.start_addr_d(31,0),PIC_BASE_ADDR.U,PIC_SIZE)
|
||||||
|
//End address check
|
||||||
|
val (end_addr_in_pic_d,end_addr_in_pic_region_d) = rvrangecheck_ch(io.end_addr_d(31,0),PIC_BASE_ADDR.U,PIC_SIZE)
|
||||||
|
|
||||||
|
val start_addr_dccm_or_pic = start_addr_in_dccm_region_d | start_addr_in_pic_region_d
|
||||||
|
val base_reg_dccm_or_pic = (io.rs1_region_d(3,0) === DCCM_REGION.U) | (io.rs1_region_d(3,0) === PIC_REGION.U) //base region
|
||||||
|
io.addr_in_dccm_d := (start_addr_in_dccm_d & end_addr_in_dccm_d)
|
||||||
|
io.addr_in_pic_d := (start_addr_in_pic_d & end_addr_in_pic_d)
|
||||||
|
|
||||||
|
io.addr_external_d := ~(start_addr_in_dccm_region_d | start_addr_in_pic_region_d); //if start address does not belong to dccm/pic
|
||||||
|
val csr_idx = Cat(io.start_addr_d(31,28),1.U)
|
||||||
|
val is_sideeffects_d = io.dec_tlu_mrac_ff(csr_idx) & !(start_addr_in_dccm_region_d | start_addr_in_pic_region_d | addr_in_iccm) & io.lsu_pkt_d.valid & (io.lsu_pkt_d.store | io.lsu_pkt_d.load) //every region has the 2 LSB indicating ( 1: sideeffects/no_side effects, and 0: cacheable ). Ignored in internal regions
|
||||||
|
val is_aligned_d = (io.lsu_pkt_d.word & (io.start_addr_d(1,0) === 0.U)) | (io.lsu_pkt_d.half & (io.start_addr_d(0) === 0.U)) | io.lsu_pkt_d.by
|
||||||
|
|
||||||
|
|
||||||
|
val non_dccm_access_ok = (!(Cat(DATA_ACCESS_ENABLE0.B ,DATA_ACCESS_ENABLE1.B,DATA_ACCESS_ENABLE2.B,DATA_ACCESS_ENABLE3.B,
|
||||||
|
DATA_ACCESS_ENABLE4.B,DATA_ACCESS_ENABLE5.B,DATA_ACCESS_ENABLE6.B,DATA_ACCESS_ENABLE7.B)).orR) |
|
||||||
|
(((DATA_ACCESS_ENABLE0.B & ((io.start_addr_d(31,0) | DATA_ACCESS_MASK0.U)) === (DATA_ACCESS_ADDR0.U | DATA_ACCESS_MASK0.U)) | //0111
|
||||||
|
(DATA_ACCESS_ENABLE1.B & ((io.start_addr_d(31,0) | DATA_ACCESS_MASK1.U)) === (DATA_ACCESS_ADDR1.U | DATA_ACCESS_MASK1.U)) | //1111
|
||||||
|
(DATA_ACCESS_ENABLE2.B & ((io.start_addr_d(31,0) | DATA_ACCESS_MASK2.U)) === (DATA_ACCESS_ADDR2.U | DATA_ACCESS_MASK2.U)) | //1011
|
||||||
|
(DATA_ACCESS_ENABLE3.B & ((io.start_addr_d(31,0) | DATA_ACCESS_MASK3.U)) === (DATA_ACCESS_ADDR3.U | DATA_ACCESS_MASK3.U)) | //1000
|
||||||
|
(DATA_ACCESS_ENABLE4.B & ((io.start_addr_d(31,0) | DATA_ACCESS_MASK4.U)) === (DATA_ACCESS_ADDR4.U | DATA_ACCESS_MASK4.U)) |
|
||||||
|
(DATA_ACCESS_ENABLE5.B & ((io.start_addr_d(31,0) | DATA_ACCESS_MASK5.U)) === (DATA_ACCESS_ADDR5.U | DATA_ACCESS_MASK5.U)) |
|
||||||
|
(DATA_ACCESS_ENABLE6.B & ((io.start_addr_d(31,0) | DATA_ACCESS_MASK6.U)) === (DATA_ACCESS_ADDR6.U | DATA_ACCESS_MASK6.U)) |
|
||||||
|
(DATA_ACCESS_ENABLE7.B & ((io.start_addr_d(31,0) | DATA_ACCESS_MASK7.U)) === (DATA_ACCESS_ADDR7.U | DATA_ACCESS_MASK7.U)))
|
||||||
|
&
|
||||||
|
((DATA_ACCESS_ENABLE0.B & ((io.end_addr_d(31,0) | DATA_ACCESS_MASK0.U)) === (DATA_ACCESS_ADDR0.U | DATA_ACCESS_MASK0.U)) |
|
||||||
|
(DATA_ACCESS_ENABLE1.B & ((io.end_addr_d(31,0) | DATA_ACCESS_MASK1.U)) === (DATA_ACCESS_ADDR1.U | DATA_ACCESS_MASK1.U)) |
|
||||||
|
(DATA_ACCESS_ENABLE2.B & ((io.end_addr_d(31,0) | DATA_ACCESS_MASK2.U)) === (DATA_ACCESS_ADDR2.U | DATA_ACCESS_MASK2.U)) |
|
||||||
|
(DATA_ACCESS_ENABLE3.B & ((io.end_addr_d(31,0) | DATA_ACCESS_MASK3.U)) === (DATA_ACCESS_ADDR3.U | DATA_ACCESS_MASK3.U)) |
|
||||||
|
(DATA_ACCESS_ENABLE4.B & ((io.end_addr_d(31,0) | DATA_ACCESS_MASK4.U)) === (DATA_ACCESS_ADDR4.U | DATA_ACCESS_MASK4.U)) |
|
||||||
|
(DATA_ACCESS_ENABLE5.B & ((io.end_addr_d(31,0) | DATA_ACCESS_MASK5.U)) === (DATA_ACCESS_ADDR5.U | DATA_ACCESS_MASK5.U)) |
|
||||||
|
(DATA_ACCESS_ENABLE6.B & ((io.end_addr_d(31,0) | DATA_ACCESS_MASK6.U)) === (DATA_ACCESS_ADDR6.U | DATA_ACCESS_MASK6.U)) |
|
||||||
|
(DATA_ACCESS_ENABLE7.B & ((io.end_addr_d(31,0) | DATA_ACCESS_MASK7.U)) === (DATA_ACCESS_ADDR7.U | DATA_ACCESS_MASK7.U))))
|
||||||
|
|
||||||
|
val regpred_access_fault_d = (start_addr_dccm_or_pic ^ base_reg_dccm_or_pic)
|
||||||
|
val picm_access_fault_d = (io.addr_in_pic_d & ((io.start_addr_d(1,0) =/= 0.U(2.W)) | !io.lsu_pkt_d.word))
|
||||||
|
|
||||||
|
val unmapped_access_fault_d = WireInit(1.U(1.W))
|
||||||
|
val mpu_access_fault_d = WireInit(1.U(1.W))
|
||||||
|
if(DCCM_REGION == PIC_REGION){
|
||||||
|
unmapped_access_fault_d := ((start_addr_in_dccm_region_d & !(start_addr_in_dccm_d | start_addr_in_pic_d)) |
|
||||||
|
// 0. Addr in dccm/pic region but not in dccm/pic offset
|
||||||
|
(end_addr_in_dccm_region_d & !(end_addr_in_dccm_d | end_addr_in_pic_d)) |
|
||||||
|
// 0. Addr in dccm/pic region but not in dccm/pic offset
|
||||||
|
(start_addr_in_dccm_d & end_addr_in_pic_d) |
|
||||||
|
// 0. DCCM -> PIC cross when DCCM/PIC in same region
|
||||||
|
(start_addr_in_pic_d & end_addr_in_dccm_d))
|
||||||
|
// 0. DCCM -> PIC cross when DCCM/PIC in same region
|
||||||
|
mpu_access_fault_d := (!start_addr_in_dccm_region_d & !non_dccm_access_ok)
|
||||||
|
// 3. Address is not in a populated non-dccm region
|
||||||
|
}
|
||||||
|
|
||||||
|
else{
|
||||||
|
unmapped_access_fault_d := ((start_addr_in_dccm_region_d & !start_addr_in_dccm_d) | (end_addr_in_dccm_region_d & !end_addr_in_dccm_d) |
|
||||||
|
(start_addr_in_pic_region_d & !start_addr_in_pic_d) | (end_addr_in_pic_region_d & !end_addr_in_pic_d))
|
||||||
|
mpu_access_fault_d := (!start_addr_in_pic_region_d & !start_addr_in_dccm_region_d & !non_dccm_access_ok);
|
||||||
|
// 3. Address is not in a populated non-dccm region
|
||||||
|
}
|
||||||
|
|
||||||
|
//check width of access_fault_mscause_d
|
||||||
|
io.access_fault_d := (unmapped_access_fault_d | mpu_access_fault_d | picm_access_fault_d | regpred_access_fault_d) & io.lsu_pkt_d.valid & !io.lsu_pkt_d.dma
|
||||||
|
val access_fault_mscause_d = Mux(unmapped_access_fault_d.asBool,2.U(4.W), Mux(mpu_access_fault_d.asBool,3.U(4.W), Mux(regpred_access_fault_d.asBool,5.U(4.W), Mux(picm_access_fault_d.asBool,6.U(4.W),0.U(4.W)))))
|
||||||
|
val regcross_misaligned_fault_d = (io.start_addr_d(31,28) =/= io.end_addr_d(31,28))
|
||||||
|
val sideeffect_misaligned_fault_d = (is_sideeffects_d & !is_aligned_d)
|
||||||
|
io.misaligned_fault_d := (regcross_misaligned_fault_d | (sideeffect_misaligned_fault_d & io.addr_external_d)) & io.lsu_pkt_d.valid & !io.lsu_pkt_d.dma
|
||||||
|
val misaligned_fault_mscause_d = Mux(regcross_misaligned_fault_d,2.U(4.W),Mux(sideeffect_misaligned_fault_d.asBool,1.U(4.W),0.U(4.W)))
|
||||||
|
io.exc_mscause_d := Mux(io.misaligned_fault_d.asBool, misaligned_fault_mscause_d(3,0), access_fault_mscause_d(3,0))
|
||||||
|
io.fir_dccm_access_error_d := ((start_addr_in_dccm_region_d & !start_addr_in_dccm_d)|(end_addr_in_dccm_region_d & !end_addr_in_dccm_d)) & io.lsu_pkt_d.valid & io.lsu_pkt_d.fast_int
|
||||||
|
io.fir_nondccm_access_error_d := !(start_addr_in_dccm_region_d & end_addr_in_dccm_region_d) & io.lsu_pkt_d.valid & io.lsu_pkt_d.fast_int
|
||||||
|
|
||||||
|
withClock(io.lsu_c2_m_clk){io.is_sideeffects_m := RegNext(is_sideeffects_d,0.U)} //TBD for clock and reset
|
||||||
|
}
|
||||||
|
object address_checker extends App{
|
||||||
|
println("Generate Verilog")
|
||||||
|
println((new chisel3.stage.ChiselStage).emitVerilog(new el2_lsu_addrcheck()))
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,299 @@
|
||||||
|
|
||||||
|
package lsu
|
||||||
|
import chisel3._
|
||||||
|
import chisel3.util._
|
||||||
|
import lib._
|
||||||
|
import include._
|
||||||
|
import snapshot._
|
||||||
|
class el2_lsu_bus_intf extends Module with RequireAsyncReset with el2_lib {
|
||||||
|
val io = IO (new Bundle {
|
||||||
|
// val clk = Input(Clock()) //implicit
|
||||||
|
// val rst_l = Input(1.W) //implicit
|
||||||
|
val scan_mode = Input(Bool())
|
||||||
|
val dec_tlu_external_ldfwd_disable = Input(Bool()) // disable load to load forwarding for externals
|
||||||
|
val dec_tlu_wb_coalescing_disable = Input(Bool()) // disable write buffer coalescing
|
||||||
|
val dec_tlu_sideeffect_posted_disable = Input(Bool()) // disable the posted sideeffect load store to the bus
|
||||||
|
val lsu_c1_m_clk = Input(Clock())
|
||||||
|
val lsu_c1_r_clk = Input(Clock())
|
||||||
|
val lsu_c2_r_clk = Input(Clock())
|
||||||
|
val lsu_bus_ibuf_c1_clk = Input(Clock())
|
||||||
|
val lsu_bus_obuf_c1_clk = Input(Clock())
|
||||||
|
val lsu_bus_buf_c1_clk = Input(Clock())
|
||||||
|
val lsu_free_c2_clk = Input(Clock())
|
||||||
|
val free_clk = Input(Clock())
|
||||||
|
val lsu_busm_clk = Input(Clock())
|
||||||
|
val dec_lsu_valid_raw_d = Input(Bool())
|
||||||
|
val lsu_busreq_m = Input(Bool())
|
||||||
|
val lsu_pkt_m = Input(new el2_lsu_pkt_t)
|
||||||
|
val lsu_pkt_r = Input(new el2_lsu_pkt_t)
|
||||||
|
val lsu_addr_d = Input(UInt(32.W))
|
||||||
|
val lsu_addr_m = Input(UInt(32.W))
|
||||||
|
val lsu_addr_r = Input(UInt(32.W))
|
||||||
|
val end_addr_d = Input(UInt(32.W))
|
||||||
|
val end_addr_m = Input(UInt(32.W))
|
||||||
|
val end_addr_r = Input(UInt(32.W))
|
||||||
|
val store_data_r = Input(UInt(32.W))
|
||||||
|
val dec_tlu_force_halt = Input(Bool())
|
||||||
|
val lsu_commit_r = Input(Bool())
|
||||||
|
val is_sideeffects_m = Input(Bool())
|
||||||
|
val flush_m_up = Input(Bool())
|
||||||
|
val flush_r = Input(Bool())
|
||||||
|
val lsu_axi_awready = Input(Bool())
|
||||||
|
val lsu_axi_wready = Input(Bool())
|
||||||
|
val lsu_axi_bvalid = Input(Bool())
|
||||||
|
val lsu_axi_bresp = Input(UInt(2.W))
|
||||||
|
val lsu_axi_bid = Input(UInt(LSU_BUS_TAG.W))
|
||||||
|
val lsu_axi_arready = Input(Bool())
|
||||||
|
val lsu_axi_rvalid = Input(Bool())
|
||||||
|
val lsu_axi_rid = Input(UInt(LSU_BUS_TAG.W))
|
||||||
|
val lsu_axi_rdata = Input(UInt(64.W))
|
||||||
|
val lsu_axi_rresp = Input(UInt(2.W))
|
||||||
|
val lsu_axi_rlast = Input(Bool())
|
||||||
|
val lsu_bus_clk_en = Input(Bool())
|
||||||
|
val lsu_busreq_r = Output(Bool())
|
||||||
|
val lsu_bus_buffer_pend_any = Output(Bool())
|
||||||
|
val lsu_bus_buffer_full_any = Output(Bool())
|
||||||
|
val lsu_bus_buffer_empty_any = Output(Bool())
|
||||||
|
val lsu_bus_idle_any = Output(Bool())
|
||||||
|
val bus_read_data_m = Output(UInt(32.W))
|
||||||
|
val lsu_imprecise_error_load_any = Output(Bool())
|
||||||
|
val lsu_imprecise_error_store_any = Output(Bool())
|
||||||
|
val lsu_imprecise_error_addr_any = Output(UInt(32.W))
|
||||||
|
val lsu_nonblock_load_valid_m = Output(Bool())
|
||||||
|
val lsu_nonblock_load_tag_m = Output(UInt(LSU_NUM_NBLOAD_WIDTH.W))
|
||||||
|
val lsu_nonblock_load_inv_r = Output(Bool())
|
||||||
|
val lsu_nonblock_load_inv_tag_r = Output(UInt(LSU_NUM_NBLOAD_WIDTH.W))
|
||||||
|
val lsu_nonblock_load_data_valid = Output(Bool())
|
||||||
|
val lsu_nonblock_load_data_error = Output(Bool())
|
||||||
|
val lsu_nonblock_load_data_tag = Output(UInt(LSU_NUM_NBLOAD_WIDTH.W))
|
||||||
|
val lsu_nonblock_load_data = Output(UInt(32.W))
|
||||||
|
val lsu_pmu_bus_trxn = Output(Bool())
|
||||||
|
val lsu_pmu_bus_misaligned = Output(Bool())
|
||||||
|
val lsu_pmu_bus_error = Output(Bool())
|
||||||
|
val lsu_pmu_bus_busy = Output(Bool())
|
||||||
|
val lsu_axi_awvalid = Output(Bool())
|
||||||
|
val lsu_axi_awid = Output(UInt(LSU_BUS_TAG.W))
|
||||||
|
val lsu_axi_awaddr = Output(UInt(32.W))
|
||||||
|
val lsu_axi_awregion = Output(UInt(4.W))
|
||||||
|
val lsu_axi_awlen = Output(UInt(8.W))
|
||||||
|
val lsu_axi_awsize = Output(UInt(3.W))
|
||||||
|
val lsu_axi_awburst = Output(UInt(2.W))
|
||||||
|
val lsu_axi_awlock = Output(Bool())
|
||||||
|
val lsu_axi_awcache = Output(UInt(4.W))
|
||||||
|
val lsu_axi_awprot = Output(UInt(3.W))
|
||||||
|
val lsu_axi_awqos = Output(UInt(4.W))
|
||||||
|
val lsu_axi_wvalid = Output(Bool())
|
||||||
|
val lsu_axi_wdata = Output(UInt(64.W))
|
||||||
|
val lsu_axi_wstrb = Output(UInt(8.W))
|
||||||
|
val lsu_axi_wlast = Output(Bool())
|
||||||
|
val lsu_axi_bready = Output(Bool())
|
||||||
|
val lsu_axi_arvalid = Output(Bool())
|
||||||
|
val lsu_axi_arid = Output(UInt(LSU_BUS_TAG.W))
|
||||||
|
val lsu_axi_araddr = Output(UInt(32.W))
|
||||||
|
val lsu_axi_arregion = Output(UInt(4.W))
|
||||||
|
val lsu_axi_arlen = Output(UInt(8.W))
|
||||||
|
val lsu_axi_arsize = Output(UInt(3.W))
|
||||||
|
val lsu_axi_arburst = Output(UInt(2.W))
|
||||||
|
val lsu_axi_arlock = Output(Bool())
|
||||||
|
val lsu_axi_arcache = Output(UInt(4.W))
|
||||||
|
val lsu_axi_arprot = Output(UInt(3.W))
|
||||||
|
val lsu_axi_arqos = Output(UInt(4.W))
|
||||||
|
val lsu_axi_rready = Output(Bool())
|
||||||
|
})
|
||||||
|
|
||||||
|
val lsu_bus_clk_en_q = WireInit(Bool(), init = false.B)
|
||||||
|
val ldst_dual_d = WireInit(Bool(), init = false.B)
|
||||||
|
val ldst_dual_m = WireInit(Bool(), init = false.B)
|
||||||
|
val ldst_dual_r = WireInit(Bool(), init = false.B)
|
||||||
|
val ldst_byteen_m = WireInit(UInt(4.W), init = 0.U)
|
||||||
|
val ldst_byteen_r = WireInit(UInt(4.W), init = 0.U)
|
||||||
|
val ldst_byteen_ext_m = WireInit(UInt(8.W), init = 0.U)
|
||||||
|
val ldst_byteen_ext_r = WireInit(UInt(8.W), init = 0.U)
|
||||||
|
val ldst_byteen_hi_m = WireInit(UInt(4.W), init = 0.U)
|
||||||
|
val ldst_byteen_hi_r = WireInit(UInt(4.W), init = 0.U)
|
||||||
|
val ldst_byteen_lo_m = WireInit(UInt(4.W), init = 0.U)
|
||||||
|
val ldst_byteen_lo_r = WireInit(UInt(4.W), init = 0.U)
|
||||||
|
val is_sideeffects_r = WireInit(Bool(), init = false.B)
|
||||||
|
val store_data_ext_r = WireInit(UInt(64.W), init = 0.U)
|
||||||
|
val store_data_hi_r = WireInit(UInt(32.W), init = 0.U)
|
||||||
|
val store_data_lo_r = WireInit(UInt(32.W), init = 0.U)
|
||||||
|
val addr_match_dw_lo_r_m = WireInit(Bool(), init = false.B)
|
||||||
|
val addr_match_word_lo_r_m = WireInit(Bool(), init = false.B)
|
||||||
|
val no_word_merge_r = WireInit(Bool(), init = false.B)
|
||||||
|
val no_dword_merge_r = WireInit(Bool(), init = false.B)
|
||||||
|
val ld_addr_rhit_lo_lo = WireInit(Bool(), init = false.B)
|
||||||
|
val ld_addr_rhit_hi_lo = WireInit(Bool(), init = false.B)
|
||||||
|
val ld_addr_rhit_lo_hi = WireInit(Bool(), init = false.B)
|
||||||
|
val ld_addr_rhit_hi_hi = WireInit(Bool(), init = false.B)
|
||||||
|
val ld_byte_rhit_lo_lo = WireInit(UInt(4.W), init = 0.U)
|
||||||
|
val ld_byte_rhit_hi_lo = WireInit(UInt(4.W), init = 0.U)
|
||||||
|
val ld_byte_rhit_lo_hi = WireInit(UInt(4.W), init = 0.U)
|
||||||
|
val ld_byte_rhit_hi_hi = WireInit(UInt(4.W), init = 0.U)
|
||||||
|
val ld_byte_hit_lo = WireInit(UInt(4.W), init = 0.U)
|
||||||
|
val ld_byte_rhit_lo = WireInit(UInt(4.W), init = 0.U)
|
||||||
|
val ld_byte_hit_hi = WireInit(UInt(4.W), init = 0.U)
|
||||||
|
val ld_byte_rhit_hi = WireInit(UInt(4.W), init = 0.U)
|
||||||
|
val ld_fwddata_rpipe_lo = WireInit(UInt(32.W), init = 0.U)
|
||||||
|
val ld_fwddata_rpipe_hi = WireInit(UInt(32.W), init = 0.U)
|
||||||
|
val ld_byte_hit_buf_lo = WireInit(UInt(4.W), init = 0.U)
|
||||||
|
val ld_byte_hit_buf_hi = WireInit(UInt(4.W), init = 0.U)
|
||||||
|
val ld_fwddata_buf_lo = WireInit(UInt(32.W), init = 0.U)
|
||||||
|
val ld_fwddata_buf_hi = WireInit(UInt(32.W), init = 0.U)
|
||||||
|
val ld_fwddata_lo = WireInit(UInt(64.W), init = 0.U)
|
||||||
|
val ld_fwddata_hi = WireInit(UInt(64.W), init = 0.U)
|
||||||
|
val ld_fwddata_m = WireInit(UInt(64.W), init = 0.U)
|
||||||
|
val ld_full_hit_hi_m = WireInit(Bool(), init = true.B)
|
||||||
|
val ld_full_hit_lo_m = WireInit(Bool(), init = true.B)
|
||||||
|
val ld_full_hit_m = WireInit(Bool(), init = false.B)
|
||||||
|
val bus_buffer = Module(new el2_lsu_bus_buffer)
|
||||||
|
bus_buffer.io.scan_mode := io.scan_mode
|
||||||
|
bus_buffer.io.dec_tlu_external_ldfwd_disable := io.dec_tlu_external_ldfwd_disable
|
||||||
|
bus_buffer.io.dec_tlu_wb_coalescing_disable := io.dec_tlu_wb_coalescing_disable
|
||||||
|
bus_buffer.io.dec_tlu_sideeffect_posted_disable := io.dec_tlu_sideeffect_posted_disable
|
||||||
|
bus_buffer.io.dec_tlu_force_halt := io.dec_tlu_force_halt
|
||||||
|
bus_buffer.io.lsu_c2_r_clk := io.lsu_c2_r_clk
|
||||||
|
bus_buffer.io.lsu_bus_ibuf_c1_clk := io.lsu_bus_ibuf_c1_clk
|
||||||
|
bus_buffer.io.lsu_bus_obuf_c1_clk := io.lsu_bus_obuf_c1_clk
|
||||||
|
bus_buffer.io.lsu_bus_buf_c1_clk := io.lsu_bus_buf_c1_clk
|
||||||
|
bus_buffer.io.lsu_free_c2_clk := io.lsu_free_c2_clk
|
||||||
|
bus_buffer.io.lsu_busm_clk := io.lsu_busm_clk
|
||||||
|
bus_buffer.io.dec_lsu_valid_raw_d := io.dec_lsu_valid_raw_d
|
||||||
|
bus_buffer.io.lsu_pkt_m := io.lsu_pkt_m
|
||||||
|
bus_buffer.io.lsu_pkt_r := io.lsu_pkt_r
|
||||||
|
bus_buffer.io.lsu_addr_m := io.lsu_addr_m
|
||||||
|
bus_buffer.io.end_addr_m := io.end_addr_m
|
||||||
|
bus_buffer.io.lsu_addr_r := io.lsu_addr_r
|
||||||
|
bus_buffer.io.end_addr_r := io.end_addr_r
|
||||||
|
bus_buffer.io.store_data_r := io.store_data_r
|
||||||
|
bus_buffer.io.no_word_merge_r := no_word_merge_r
|
||||||
|
bus_buffer.io.no_dword_merge_r := no_dword_merge_r
|
||||||
|
bus_buffer.io.lsu_busreq_m := io.lsu_busreq_m
|
||||||
|
bus_buffer.io.ld_full_hit_m := ld_full_hit_m
|
||||||
|
bus_buffer.io.flush_m_up := io.flush_m_up
|
||||||
|
bus_buffer.io.flush_r := io.flush_r
|
||||||
|
bus_buffer.io.lsu_commit_r := io.lsu_commit_r
|
||||||
|
bus_buffer.io.is_sideeffects_r := is_sideeffects_r
|
||||||
|
bus_buffer.io.ldst_dual_d := ldst_dual_d
|
||||||
|
bus_buffer.io.ldst_dual_m := ldst_dual_m
|
||||||
|
bus_buffer.io.ldst_dual_r := ldst_dual_r
|
||||||
|
bus_buffer.io.ldst_byteen_ext_m := ldst_byteen_ext_m
|
||||||
|
bus_buffer.io.lsu_axi_awready := io.lsu_axi_awready
|
||||||
|
bus_buffer.io.lsu_axi_wready := io.lsu_axi_wready
|
||||||
|
bus_buffer.io.lsu_axi_bvalid := io.lsu_axi_bvalid
|
||||||
|
bus_buffer.io.lsu_axi_bresp := io.lsu_axi_bresp
|
||||||
|
bus_buffer.io.lsu_axi_bid := io.lsu_axi_bid
|
||||||
|
bus_buffer.io.lsu_axi_arready := io.lsu_axi_arready
|
||||||
|
bus_buffer.io.lsu_axi_rvalid := io.lsu_axi_rvalid
|
||||||
|
bus_buffer.io.lsu_axi_rid := io.lsu_axi_rid
|
||||||
|
bus_buffer.io.lsu_axi_rdata := io.lsu_axi_rdata
|
||||||
|
bus_buffer.io.lsu_axi_rresp := io.lsu_axi_rresp
|
||||||
|
bus_buffer.io.lsu_bus_clk_en := io.lsu_bus_clk_en
|
||||||
|
bus_buffer.io.lsu_bus_clk_en_q := lsu_bus_clk_en_q
|
||||||
|
|
||||||
|
io.lsu_busreq_r := bus_buffer.io.lsu_busreq_r
|
||||||
|
io.lsu_bus_buffer_pend_any := bus_buffer.io.lsu_bus_buffer_pend_any
|
||||||
|
io.lsu_bus_buffer_full_any := bus_buffer.io.lsu_bus_buffer_full_any
|
||||||
|
io.lsu_bus_buffer_empty_any := bus_buffer.io.lsu_bus_buffer_empty_any
|
||||||
|
io.lsu_bus_idle_any := bus_buffer.io.lsu_bus_idle_any
|
||||||
|
ld_byte_hit_buf_lo := bus_buffer.io.ld_byte_hit_buf_lo
|
||||||
|
ld_byte_hit_buf_hi := bus_buffer.io.ld_byte_hit_buf_hi
|
||||||
|
ld_fwddata_buf_lo := bus_buffer.io.ld_fwddata_buf_lo
|
||||||
|
ld_fwddata_buf_hi := bus_buffer.io.ld_fwddata_buf_hi
|
||||||
|
io.lsu_imprecise_error_load_any := bus_buffer.io.lsu_imprecise_error_load_any
|
||||||
|
io.lsu_imprecise_error_store_any := bus_buffer.io.lsu_imprecise_error_store_any
|
||||||
|
io.lsu_imprecise_error_addr_any := bus_buffer.io.lsu_imprecise_error_addr_any
|
||||||
|
io.lsu_nonblock_load_valid_m := bus_buffer.io.lsu_nonblock_load_valid_m
|
||||||
|
io.lsu_nonblock_load_tag_m := bus_buffer.io.lsu_nonblock_load_tag_m
|
||||||
|
io.lsu_nonblock_load_inv_r := bus_buffer.io.lsu_nonblock_load_inv_r
|
||||||
|
io.lsu_nonblock_load_inv_tag_r := bus_buffer.io.lsu_nonblock_load_inv_tag_r
|
||||||
|
io.lsu_nonblock_load_data_valid := bus_buffer.io.lsu_nonblock_load_data_valid
|
||||||
|
io.lsu_nonblock_load_data_error := bus_buffer.io.lsu_nonblock_load_data_error
|
||||||
|
io.lsu_nonblock_load_data_tag := bus_buffer.io.lsu_nonblock_load_data_tag
|
||||||
|
io.lsu_nonblock_load_data := bus_buffer.io.lsu_nonblock_load_data
|
||||||
|
io.lsu_pmu_bus_trxn := bus_buffer.io.lsu_pmu_bus_trxn
|
||||||
|
io.lsu_pmu_bus_misaligned := bus_buffer.io.lsu_pmu_bus_misaligned
|
||||||
|
io.lsu_pmu_bus_error := bus_buffer.io.lsu_pmu_bus_error
|
||||||
|
io.lsu_pmu_bus_busy := bus_buffer.io.lsu_pmu_bus_busy
|
||||||
|
io.lsu_axi_awvalid := bus_buffer.io.lsu_axi_awvalid
|
||||||
|
io.lsu_axi_awid := bus_buffer.io.lsu_axi_awid
|
||||||
|
io.lsu_axi_awaddr := bus_buffer.io.lsu_axi_awaddr
|
||||||
|
io.lsu_axi_awregion := bus_buffer.io.lsu_axi_awregion
|
||||||
|
io.lsu_axi_awlen := bus_buffer.io.lsu_axi_awlen
|
||||||
|
io.lsu_axi_awsize := bus_buffer.io.lsu_axi_awsize
|
||||||
|
io.lsu_axi_awburst := bus_buffer.io.lsu_axi_awburst
|
||||||
|
io.lsu_axi_awlock := bus_buffer.io.lsu_axi_awlock
|
||||||
|
io.lsu_axi_awcache := bus_buffer.io.lsu_axi_awcache
|
||||||
|
io.lsu_axi_awprot := bus_buffer.io.lsu_axi_awprot
|
||||||
|
io.lsu_axi_awqos := bus_buffer.io.lsu_axi_awqos
|
||||||
|
io.lsu_axi_wvalid := bus_buffer.io.lsu_axi_wvalid
|
||||||
|
io.lsu_axi_wdata := bus_buffer.io.lsu_axi_wdata
|
||||||
|
io.lsu_axi_wstrb := bus_buffer.io.lsu_axi_wstrb
|
||||||
|
io.lsu_axi_wlast := bus_buffer.io.lsu_axi_wlast
|
||||||
|
io.lsu_axi_bready := bus_buffer.io.lsu_axi_bready
|
||||||
|
io.lsu_axi_arvalid := bus_buffer.io.lsu_axi_arvalid
|
||||||
|
io.lsu_axi_arid := bus_buffer.io.lsu_axi_arid
|
||||||
|
io.lsu_axi_araddr := bus_buffer.io.lsu_axi_araddr
|
||||||
|
io.lsu_axi_arregion := bus_buffer.io.lsu_axi_arregion
|
||||||
|
io.lsu_axi_arlen := bus_buffer.io.lsu_axi_arlen
|
||||||
|
io.lsu_axi_arsize := bus_buffer.io.lsu_axi_arsize
|
||||||
|
io.lsu_axi_arburst := bus_buffer.io.lsu_axi_arburst
|
||||||
|
io.lsu_axi_arlock := bus_buffer.io.lsu_axi_arlock
|
||||||
|
io.lsu_axi_arcache := bus_buffer.io.lsu_axi_arcache
|
||||||
|
io.lsu_axi_arprot := bus_buffer.io.lsu_axi_arprot
|
||||||
|
io.lsu_axi_arqos := bus_buffer.io.lsu_axi_arqos
|
||||||
|
io.lsu_axi_rready := bus_buffer.io.lsu_axi_rready
|
||||||
|
|
||||||
|
ldst_byteen_m := Mux1H(Seq(io.lsu_pkt_r.word.asBool -> 15.U(4.W), io.lsu_pkt_r.half.asBool -> 3.U(4.W), io.lsu_pkt_r.by.asBool -> 1.U(4.W)))
|
||||||
|
ldst_dual_d := io.lsu_addr_d(2) =/= io.end_addr_d(2)
|
||||||
|
addr_match_dw_lo_r_m := (io.lsu_addr_r(31,3) === io.lsu_addr_m(31,3))
|
||||||
|
addr_match_word_lo_r_m := addr_match_dw_lo_r_m & !(io.lsu_addr_r(2)^io.lsu_addr_m(2))
|
||||||
|
no_word_merge_r := io.lsu_busreq_r & !ldst_dual_r & io.lsu_busreq_m & (io.lsu_pkt_m.load | !addr_match_word_lo_r_m)
|
||||||
|
no_dword_merge_r := io.lsu_busreq_r & !ldst_dual_r & io.lsu_busreq_m & (io.lsu_pkt_m.load | !addr_match_dw_lo_r_m)
|
||||||
|
ldst_byteen_ext_m := Cat(0.U(4.W),ldst_byteen_m(3,0)) << io.lsu_addr_m(1,0)
|
||||||
|
ldst_byteen_ext_r := Cat(0.U(4.W),ldst_byteen_r(3,0)) << io.lsu_addr_r(1,0)
|
||||||
|
store_data_ext_r := Cat(0.U(32.W),io.store_data_r(31,0)) << Cat(io.lsu_addr_r(1,0),0.U(3.W))
|
||||||
|
ldst_byteen_hi_m := ldst_byteen_ext_m(7,4)
|
||||||
|
ldst_byteen_lo_m := ldst_byteen_ext_m(3,0)
|
||||||
|
ldst_byteen_hi_r := ldst_byteen_ext_r(7,4)
|
||||||
|
ldst_byteen_lo_r := ldst_byteen_ext_r(3,0)
|
||||||
|
store_data_hi_r := store_data_ext_r(63,32)
|
||||||
|
store_data_lo_r := store_data_ext_r(31,0)
|
||||||
|
ld_addr_rhit_lo_lo := (io.lsu_addr_m(31,2) === io.lsu_addr_r(31,2)) & io.lsu_pkt_r.valid & io.lsu_pkt_r.store & io.lsu_busreq_m
|
||||||
|
ld_addr_rhit_lo_hi := (io.end_addr_m(31,2) === io.lsu_addr_r(31,2)) & io.lsu_pkt_r.valid & io.lsu_pkt_r.store & io.lsu_busreq_m
|
||||||
|
ld_addr_rhit_hi_lo := (io.lsu_addr_m(31,2) === io.end_addr_r(31,2)) & io.lsu_pkt_r.valid & io.lsu_pkt_r.store & io.lsu_busreq_m
|
||||||
|
ld_addr_rhit_hi_hi := (io.end_addr_m(31,2) === io.end_addr_r(31,2)) & io.lsu_pkt_r.valid & io.lsu_pkt_r.store & io.lsu_busreq_m
|
||||||
|
ld_byte_rhit_lo_lo := (0 until 4).map(i =>(ld_addr_rhit_lo_lo & ldst_byteen_lo_r(i) & ldst_byteen_lo_m(i)).asUInt).reverse.reduce(Cat(_,_))
|
||||||
|
ld_byte_rhit_lo_hi := (0 until 4).map(i =>(ld_addr_rhit_lo_hi & ldst_byteen_lo_r(i) & ldst_byteen_hi_m(i)).asUInt).reverse.reduce(Cat(_,_))
|
||||||
|
ld_byte_rhit_hi_lo := (0 until 4).map(i =>(ld_addr_rhit_hi_lo & ldst_byteen_hi_r(i) & ldst_byteen_lo_m(i)).asUInt).reverse.reduce(Cat(_,_))
|
||||||
|
ld_byte_rhit_hi_hi := (0 until 4).map(i =>(ld_addr_rhit_hi_hi & ldst_byteen_hi_r(i) & ldst_byteen_hi_m(i)).asUInt).reverse.reduce(Cat(_,_))
|
||||||
|
ld_byte_hit_lo := (0 until 4).map(i =>(ld_byte_rhit_lo_lo(i) | ld_byte_rhit_hi_lo(i) | ld_byte_hit_buf_lo(i)).asUInt).reverse.reduce(Cat(_,_))
|
||||||
|
ld_byte_hit_hi := (0 until 4).map(i =>(ld_byte_rhit_lo_hi(i) | ld_byte_rhit_hi_hi(i) | ld_byte_hit_buf_hi(i)).asUInt).reverse.reduce(Cat(_,_))
|
||||||
|
ld_byte_rhit_lo := (0 until 4).map(i =>(ld_byte_rhit_lo_lo(i) | ld_byte_rhit_hi_lo(i) ).asUInt).reverse.reduce(Cat(_,_))
|
||||||
|
ld_byte_rhit_hi := (0 until 4).map(i =>(ld_byte_rhit_lo_hi(i) | ld_byte_rhit_hi_hi(i) ).asUInt).reverse.reduce(Cat(_,_))
|
||||||
|
ld_fwddata_rpipe_lo := (0 until 4).map(i =>(Mux1H(Seq(ld_byte_rhit_lo_lo(i) -> store_data_lo_r((8*i)+7,(8*i)), ld_byte_rhit_hi_lo(i) -> store_data_hi_r((8*i)+7,(8*i))))).asUInt).reverse.reduce(Cat(_,_))
|
||||||
|
ld_fwddata_rpipe_hi := (0 until 4).map(i =>(Mux1H(Seq(ld_byte_rhit_lo_hi(i) -> store_data_lo_r((8*i)+7,(8*i)), ld_byte_rhit_hi_hi(i) -> store_data_hi_r((8*i)+7,(8*i))))).asUInt).reverse.reduce(Cat(_,_))
|
||||||
|
ld_fwddata_lo := (0 until 4).map(i =>(Mux(ld_byte_rhit_lo(i), ld_fwddata_rpipe_lo((8*i)+7,(8*i)), ld_fwddata_buf_lo((8*i)+7,(8*i)))).asUInt).reverse.reduce(Cat(_,_))
|
||||||
|
ld_fwddata_hi := (0 until 4).map(i =>(Mux(ld_byte_rhit_hi(i), ld_fwddata_rpipe_hi((8*i)+7,(8*i)), ld_fwddata_buf_hi((8*i)+7,(8*i)))).asUInt).reverse.reduce(Cat(_,_))
|
||||||
|
ld_full_hit_lo_m := (0 until 4).map(i =>((ld_byte_hit_lo(i) | !ldst_byteen_lo_m(i))).asUInt).reduce(_&_)
|
||||||
|
ld_full_hit_hi_m := (0 until 4).map(i =>((ld_byte_hit_hi(i) | !ldst_byteen_hi_m(i))).asUInt).reduce(_&_)
|
||||||
|
ld_full_hit_m := ld_full_hit_lo_m & ld_full_hit_hi_m & io.lsu_busreq_m & io.lsu_pkt_m.load & !io.is_sideeffects_m
|
||||||
|
ld_fwddata_m := Cat(ld_fwddata_hi(31,0), ld_fwddata_lo(31,0)) >> (8.U*io.lsu_addr_m(1,0))
|
||||||
|
io.bus_read_data_m := ld_fwddata_m(31,0)
|
||||||
|
|
||||||
|
withClock(io.free_clk) {
|
||||||
|
lsu_bus_clk_en_q := RegNext(io.lsu_bus_clk_en, init = 0.U)
|
||||||
|
}
|
||||||
|
withClock(io.lsu_c1_m_clk) {
|
||||||
|
ldst_dual_m := RegNext(io.lsu_bus_clk_en, init = 0.U)
|
||||||
|
}
|
||||||
|
withClock(io.lsu_c1_r_clk) {
|
||||||
|
ldst_dual_r := RegNext(io.lsu_bus_clk_en, init = 0.U)
|
||||||
|
is_sideeffects_r := RegNext(io.lsu_bus_clk_en, init = 0.U)
|
||||||
|
ldst_byteen_r := RegNext(io.lsu_bus_clk_en, init = 0.U(4.W))
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
object BusIntfMain extends App{
|
||||||
|
println("Generate Verilog")
|
||||||
|
println((new chisel3.stage.ChiselStage).emitVerilog(new el2_lsu_bus_intf()))
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,103 @@
|
||||||
|
package lsu
|
||||||
|
import chisel3._
|
||||||
|
import chisel3.experimental.chiselName
|
||||||
|
import chisel3.util._
|
||||||
|
import lib._
|
||||||
|
import include._
|
||||||
|
import snapshot._
|
||||||
|
|
||||||
|
@chiselName
|
||||||
|
class el2_lsu_clkdomain extends Module with RequireAsyncReset with el2_lib{
|
||||||
|
val io = IO (new Bundle {
|
||||||
|
|
||||||
|
val free_clk = Input(Clock()) // clock
|
||||||
|
// Inputs
|
||||||
|
val clk_override = Input(Bool()) // chciken bit to turn off clock gating
|
||||||
|
val addr_in_dccm_m = Input(Bool()) // address in dccm
|
||||||
|
val dma_dccm_req = Input(Bool()) // dma is active
|
||||||
|
val ldst_stbuf_reqvld_r = Input(Bool()) // allocating in to the store queue
|
||||||
|
|
||||||
|
val stbuf_reqvld_any = Input(Bool()) // stbuf is draining
|
||||||
|
val stbuf_reqvld_flushed_any = Input(Bool()) // instruction going to stbuf is flushed
|
||||||
|
val lsu_busreq_r = Input(Bool()) // busreq in r
|
||||||
|
val lsu_bus_buffer_pend_any = Input(Bool()) // bus buffer has a pending bus entry
|
||||||
|
val lsu_bus_buffer_empty_any = Input(Bool()) // external bus buffer is empty
|
||||||
|
val lsu_stbuf_empty_any = Input(Bool()) // stbuf is empty
|
||||||
|
|
||||||
|
val lsu_bus_clk_en = Input(Bool()) // bus clock enable
|
||||||
|
|
||||||
|
val lsu_p = Input(new el2_lsu_pkt_t) // lsu packet in decode
|
||||||
|
val lsu_pkt_d = Input(new el2_lsu_pkt_t) // lsu packet in d
|
||||||
|
val lsu_pkt_m = Input(new el2_lsu_pkt_t) // lsu packet in m
|
||||||
|
val lsu_pkt_r = Input(new el2_lsu_pkt_t) // lsu packet in r
|
||||||
|
|
||||||
|
// Outputs
|
||||||
|
val lsu_c1_m_clk = Output(Clock()) // m pipe single pulse clock
|
||||||
|
val lsu_c1_r_clk = Output(Clock()) // r pipe single pulse clock
|
||||||
|
|
||||||
|
val lsu_c2_m_clk = Output(Clock()) // m pipe double pulse clock
|
||||||
|
val lsu_c2_r_clk = Output(Clock()) // r pipe double pulse clock
|
||||||
|
|
||||||
|
val lsu_store_c1_m_clk = Output(Clock()) // store in m
|
||||||
|
val lsu_store_c1_r_clk = Output(Clock()) // store in r
|
||||||
|
|
||||||
|
val lsu_stbuf_c1_clk = Output(Clock())
|
||||||
|
val lsu_bus_obuf_c1_clk = Output(Clock()) // ibuf clock
|
||||||
|
val lsu_bus_ibuf_c1_clk = Output(Clock()) // ibuf clock
|
||||||
|
val lsu_bus_buf_c1_clk = Output(Clock()) // ibuf clock
|
||||||
|
val lsu_busm_clk = Output(Clock()) // bus clock
|
||||||
|
|
||||||
|
val lsu_free_c2_clk = Output(Clock())
|
||||||
|
|
||||||
|
val scan_mode = Input(Bool())
|
||||||
|
})
|
||||||
|
|
||||||
|
//-------------------------------------------------------------------------------------------
|
||||||
|
// Clock Enable Logic
|
||||||
|
//-------------------------------------------------------------------------------------------
|
||||||
|
val lsu_c1_d_clken_q = Wire(Bool())
|
||||||
|
val lsu_c1_m_clken_q = Wire(Bool())
|
||||||
|
val lsu_c1_r_clken_q = Wire(Bool())
|
||||||
|
val lsu_free_c1_clken_q = Wire(Bool())
|
||||||
|
|
||||||
|
val lsu_c1_d_clken = io.lsu_p.valid | io.dma_dccm_req | io.clk_override
|
||||||
|
val lsu_c1_m_clken = io.lsu_pkt_d.valid | lsu_c1_d_clken_q | io.clk_override
|
||||||
|
val lsu_c1_r_clken = io.lsu_pkt_m.valid | lsu_c1_m_clken_q | io.clk_override
|
||||||
|
|
||||||
|
val lsu_c2_m_clken = lsu_c1_m_clken | lsu_c1_m_clken_q | io.clk_override
|
||||||
|
val lsu_c2_r_clken = lsu_c1_r_clken | lsu_c1_r_clken_q | io.clk_override
|
||||||
|
|
||||||
|
val lsu_store_c1_m_clken = ((lsu_c1_m_clken & io.lsu_pkt_d.store) | io.clk_override)
|
||||||
|
val lsu_store_c1_r_clken = ((lsu_c1_r_clken & io.lsu_pkt_m.store) | io.clk_override)
|
||||||
|
val lsu_stbuf_c1_clken = io.ldst_stbuf_reqvld_r | io.stbuf_reqvld_any | io.stbuf_reqvld_flushed_any | io.clk_override
|
||||||
|
val lsu_bus_ibuf_c1_clken = io.lsu_busreq_r | io.clk_override
|
||||||
|
val lsu_bus_obuf_c1_clken = (io.lsu_bus_buffer_pend_any | io.lsu_busreq_r | io.clk_override) & io.lsu_bus_clk_en
|
||||||
|
val lsu_bus_buf_c1_clken = (!io.lsu_bus_buffer_empty_any | io.lsu_busreq_r | io.clk_override).asBool
|
||||||
|
|
||||||
|
val lsu_free_c1_clken = (io.lsu_p.valid | io.lsu_pkt_d.valid | io.lsu_pkt_m.valid | io.lsu_pkt_r.valid) | ~io.lsu_bus_buffer_empty_any | ~io.lsu_stbuf_empty_any | io.clk_override
|
||||||
|
val lsu_free_c2_clken = lsu_free_c1_clken | lsu_free_c1_clken_q | io.clk_override
|
||||||
|
|
||||||
|
|
||||||
|
lsu_free_c1_clken_q := withClock(io.free_clk) {RegNext(lsu_free_c1_clken,0.U)}
|
||||||
|
lsu_c1_d_clken_q := withClock(io.lsu_free_c2_clk) {RegNext(lsu_c1_d_clken, 0.U)}
|
||||||
|
lsu_c1_m_clken_q := withClock(io.lsu_free_c2_clk) {RegNext(lsu_c1_m_clken, 0.U)}
|
||||||
|
lsu_c1_r_clken_q := withClock(io.lsu_free_c2_clk) {RegNext(lsu_c1_r_clken, 0.U)}
|
||||||
|
|
||||||
|
io.lsu_c1_m_clk := rvclkhdr(clock,lsu_c1_m_clken.asBool,io.scan_mode)
|
||||||
|
io.lsu_c1_r_clk := rvclkhdr(clock,lsu_c1_r_clken.asBool,io.scan_mode)
|
||||||
|
io.lsu_c2_m_clk := rvclkhdr(clock,lsu_c2_m_clken.asBool,io.scan_mode)
|
||||||
|
io.lsu_c2_r_clk := rvclkhdr(clock,lsu_c2_r_clken.asBool,io.scan_mode)
|
||||||
|
io.lsu_store_c1_m_clk := rvclkhdr(clock,lsu_store_c1_m_clken.asBool,io.scan_mode)
|
||||||
|
io.lsu_store_c1_r_clk := rvclkhdr(clock,lsu_store_c1_r_clken.asBool,io.scan_mode)
|
||||||
|
io.lsu_stbuf_c1_clk := rvclkhdr(clock,lsu_stbuf_c1_clken.asBool,io.scan_mode)
|
||||||
|
io.lsu_bus_ibuf_c1_clk := rvclkhdr(clock,lsu_bus_ibuf_c1_clken.asBool,io.scan_mode)
|
||||||
|
io.lsu_bus_obuf_c1_clk := rvclkhdr(clock,lsu_bus_obuf_c1_clken.asBool,io.scan_mode)
|
||||||
|
io.lsu_bus_buf_c1_clk := rvclkhdr(clock,lsu_bus_buf_c1_clken.asBool,io.scan_mode)
|
||||||
|
io.lsu_busm_clk := rvclkhdr(clock,io.lsu_bus_clk_en.asBool,io.scan_mode)
|
||||||
|
io.lsu_free_c2_clk := rvclkhdr(clock,lsu_free_c2_clken.asBool,io.scan_mode)
|
||||||
|
|
||||||
|
}
|
||||||
|
object cgcmain extends App{
|
||||||
|
println("Generate Verilog")
|
||||||
|
println((new chisel3.stage.ChiselStage).emitVerilog(new el2_lsu_clkdomain()))
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,316 @@
|
||||||
|
package lsu
|
||||||
|
import include._
|
||||||
|
import lib._
|
||||||
|
import chisel3._
|
||||||
|
import chisel3.util._
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
import chisel3.experimental.chiselName
|
||||||
|
@chiselName
|
||||||
|
class el2_lsu_dccm_ctl extends Module with RequireAsyncReset with el2_lib
|
||||||
|
{
|
||||||
|
val io = IO(new Bundle{
|
||||||
|
//val rst_l = IO(Input(1.W)) //implicit
|
||||||
|
val lsu_c2_m_clk = Input(Clock())
|
||||||
|
val lsu_c2_r_clk = Input(Clock())
|
||||||
|
val lsu_free_c2_clk = Input(Clock()) //tbd
|
||||||
|
val lsu_c1_r_clk = Input(Clock())
|
||||||
|
val lsu_store_c1_r_clk = Input(Clock())
|
||||||
|
// val clk = Input(Clock()) //tbd
|
||||||
|
|
||||||
|
val lsu_pkt_d = Input(new el2_lsu_pkt_t())
|
||||||
|
val lsu_pkt_m = Input(new el2_lsu_pkt_t())
|
||||||
|
val lsu_pkt_r = Input(new el2_lsu_pkt_t())
|
||||||
|
|
||||||
|
val addr_in_dccm_d = Input(UInt(1.W))
|
||||||
|
val addr_in_dccm_m = Input(UInt(1.W))
|
||||||
|
val addr_in_dccm_r = Input(UInt(1.W))
|
||||||
|
val addr_in_pic_d = Input(UInt(1.W))
|
||||||
|
val addr_in_pic_m = Input(UInt(1.W))
|
||||||
|
val addr_in_pic_r = Input(UInt(1.W))
|
||||||
|
|
||||||
|
val lsu_raw_fwd_lo_r = Input(UInt(1.W))
|
||||||
|
val lsu_raw_fwd_hi_r = Input(UInt(1.W))
|
||||||
|
val lsu_commit_r = Input(UInt(1.W))
|
||||||
|
|
||||||
|
// lsu address down the pipe
|
||||||
|
val lsu_addr_d = Input(UInt(32.W))//verify bits
|
||||||
|
val lsu_addr_m = Input(UInt(DCCM_BITS.W))
|
||||||
|
val lsu_addr_r = Input(UInt(32.W))
|
||||||
|
|
||||||
|
// lsu address down the pipe - needed to check unaligned
|
||||||
|
val end_addr_d = Input(UInt(DCCM_BITS.W))
|
||||||
|
val end_addr_m = Input(UInt(DCCM_BITS.W))
|
||||||
|
val end_addr_r = Input(UInt(DCCM_BITS.W))
|
||||||
|
|
||||||
|
val stbuf_reqvld_any = Input(UInt(1.W))
|
||||||
|
val stbuf_addr_any = Input(UInt(LSU_SB_BITS.W))
|
||||||
|
val stbuf_data_any = Input(UInt(DCCM_DATA_WIDTH.W))
|
||||||
|
val stbuf_ecc_any = Input(UInt(DCCM_ECC_WIDTH.W))
|
||||||
|
val stbuf_fwddata_hi_m = Input(UInt(DCCM_DATA_WIDTH.W))
|
||||||
|
val stbuf_fwddata_lo_m = Input(UInt(DCCM_DATA_WIDTH.W))
|
||||||
|
val stbuf_fwdbyteen_lo_m = Input(UInt(DCCM_BYTE_WIDTH.W))
|
||||||
|
val stbuf_fwdbyteen_hi_m = Input(UInt(DCCM_BYTE_WIDTH.W))
|
||||||
|
val dccm_rdata_hi_r = Output(UInt(DCCM_DATA_WIDTH.W))
|
||||||
|
val dccm_rdata_lo_r = Output(UInt(DCCM_DATA_WIDTH.W))
|
||||||
|
val dccm_data_ecc_hi_r = Output(UInt(DCCM_ECC_WIDTH.W))
|
||||||
|
val dccm_data_ecc_lo_r = Output(UInt(DCCM_ECC_WIDTH.W))
|
||||||
|
val lsu_ld_data_r = Output(UInt(DCCM_DATA_WIDTH.W))
|
||||||
|
val lsu_ld_data_corr_r = Output(UInt(DCCM_DATA_WIDTH.W))
|
||||||
|
val lsu_double_ecc_error_r = Input(UInt(1.W))
|
||||||
|
val single_ecc_error_hi_r = Input(UInt(1.W))
|
||||||
|
val single_ecc_error_lo_r = Input(UInt(1.W))
|
||||||
|
val sec_data_hi_r = Input(UInt(DCCM_DATA_WIDTH.W))
|
||||||
|
val sec_data_lo_r = Input(UInt(DCCM_DATA_WIDTH.W))
|
||||||
|
val sec_data_hi_r_ff = Input(UInt(DCCM_DATA_WIDTH.W))
|
||||||
|
val sec_data_lo_r_ff = Input(UInt(DCCM_DATA_WIDTH.W))
|
||||||
|
val sec_data_ecc_hi_r_ff = Input(UInt(DCCM_ECC_WIDTH.W))
|
||||||
|
val sec_data_ecc_lo_r_ff = Input(UInt(DCCM_ECC_WIDTH.W))
|
||||||
|
val dccm_rdata_hi_m = Output(UInt(DCCM_DATA_WIDTH.W))
|
||||||
|
val dccm_rdata_lo_m = Output(UInt(DCCM_DATA_WIDTH.W))
|
||||||
|
val dccm_data_ecc_hi_m = Output(UInt(DCCM_ECC_WIDTH.W))
|
||||||
|
val dccm_data_ecc_lo_m = Output(UInt(DCCM_ECC_WIDTH.W))
|
||||||
|
val lsu_ld_data_m = Output(UInt(DCCM_DATA_WIDTH.W))
|
||||||
|
val lsu_double_ecc_error_m = Input(UInt(1.W))
|
||||||
|
val sec_data_hi_m = Input(UInt(DCCM_DATA_WIDTH.W))
|
||||||
|
val sec_data_lo_m = Input(UInt(DCCM_DATA_WIDTH.W))
|
||||||
|
val store_data_m = Input(UInt(32.W))
|
||||||
|
val dma_dccm_wen = Input(UInt(1.W))
|
||||||
|
val dma_pic_wen = Input(UInt(1.W))
|
||||||
|
val dma_mem_tag_m = Input(UInt(3.W))
|
||||||
|
val dma_mem_addr = Input(UInt(32.W))
|
||||||
|
val dma_mem_wdata = Input(UInt(64.W))
|
||||||
|
val dma_dccm_wdata_lo = Input(UInt(32.W))
|
||||||
|
val dma_dccm_wdata_hi = Input(UInt(32.W))
|
||||||
|
val dma_dccm_wdata_ecc_hi = Input(UInt(DCCM_ECC_WIDTH.W))
|
||||||
|
val dma_dccm_wdata_ecc_lo = Input(UInt(DCCM_ECC_WIDTH.W))
|
||||||
|
val store_data_hi_r = Output(UInt(DCCM_DATA_WIDTH.W))
|
||||||
|
val store_data_lo_r = Output(UInt(DCCM_DATA_WIDTH.W))
|
||||||
|
val store_datafn_hi_r = Output(UInt(DCCM_DATA_WIDTH.W))
|
||||||
|
val store_datafn_lo_r = Output(UInt(DCCM_DATA_WIDTH.W))
|
||||||
|
val store_data_r = Output(UInt(32.W))
|
||||||
|
val ld_single_ecc_error_r = Output(UInt(1.W))
|
||||||
|
val ld_single_ecc_error_r_ff = Output(UInt(1.W))
|
||||||
|
val picm_mask_data_m = Output(UInt(32.W))
|
||||||
|
val lsu_stbuf_commit_any = Output(UInt(1.W))
|
||||||
|
val lsu_dccm_rden_m = Output(UInt(1.W))
|
||||||
|
val lsu_dccm_rden_r = Output(UInt(1.W))
|
||||||
|
val dccm_dma_rvalid = Output(UInt(1.W))
|
||||||
|
val dccm_dma_ecc_error = Output(UInt(1.W))
|
||||||
|
val dccm_dma_rtag = Output(UInt(3.W))
|
||||||
|
val dccm_dma_rdata = Output(UInt(64.W))
|
||||||
|
val dccm_wren = Output(UInt(1.W))
|
||||||
|
val dccm_rden = Output(UInt(1.W))
|
||||||
|
val dccm_wr_addr_lo = Output(UInt(DCCM_BITS.W))
|
||||||
|
val dccm_wr_data_lo = Output(UInt(DCCM_FDATA_WIDTH.W))
|
||||||
|
val dccm_rd_addr_lo = Output(UInt(DCCM_BITS.W))
|
||||||
|
val dccm_rd_data_lo = Input(UInt(DCCM_FDATA_WIDTH.W))
|
||||||
|
val dccm_wr_addr_hi = Output(UInt(DCCM_BITS.W))
|
||||||
|
val dccm_wr_data_hi = Output(UInt(DCCM_FDATA_WIDTH.W))
|
||||||
|
val dccm_rd_addr_hi = Output(UInt(DCCM_BITS.W))
|
||||||
|
val dccm_rd_data_hi = Input(UInt(DCCM_FDATA_WIDTH.W))
|
||||||
|
val picm_wren = Output(UInt(1.W))
|
||||||
|
val picm_rden = Output(UInt(1.W))
|
||||||
|
val picm_mken = Output(UInt(1.W))
|
||||||
|
val picm_rdaddr = Output(UInt(32.W))
|
||||||
|
val picm_wraddr = Output(UInt(32.W))
|
||||||
|
val picm_wr_data = Output(UInt(32.W))
|
||||||
|
val picm_rd_data = Input(UInt(32.W))
|
||||||
|
val scan_mode = Input(UInt(1.W))
|
||||||
|
})
|
||||||
|
val picm_rd_data_m = Cat(io.picm_rd_data,io.picm_rd_data) //used in both if and else
|
||||||
|
val dccm_rdata_corr_r = Cat(io.sec_data_hi_r,io.sec_data_lo_r)
|
||||||
|
val dccm_rdata_corr_m = Cat(io.sec_data_hi_m,io.sec_data_lo_m)
|
||||||
|
val dccm_rdata_r = Cat(io.dccm_rdata_hi_r,io.dccm_rdata_lo_r)
|
||||||
|
val dccm_rdata_m = Cat(io.dccm_rdata_hi_m,io.dccm_rdata_lo_m)
|
||||||
|
val lsu_rdata_r = WireInit(UInt(64.W),0.U)
|
||||||
|
val lsu_rdata_m = WireInit(UInt(64.W),0.U)
|
||||||
|
val lsu_rdata_corr_r = WireInit(UInt(64.W),0.U)
|
||||||
|
val lsu_rdata_corr_m = WireInit(UInt(64.W),0.U)
|
||||||
|
val stbuf_fwddata_r = WireInit(UInt(64.W),0.U)
|
||||||
|
val stbuf_fwdbyteen_r = WireInit(UInt(64.W),0.U)
|
||||||
|
val picm_rd_data_r_32 = WireInit(UInt(32.W),0.U)
|
||||||
|
val picm_rd_data_r = WireInit(UInt(64.W),0.U)
|
||||||
|
val lsu_ld_data_corr_m = WireInit(UInt(64.W),0.U)
|
||||||
|
|
||||||
|
|
||||||
|
//Forwarding stbuf
|
||||||
|
if (LOAD_TO_USE_PLUS1 == 1){
|
||||||
|
io.dccm_dma_rvalid := io.lsu_pkt_r.valid & io.lsu_pkt_r.load & io.lsu_pkt_r.dma
|
||||||
|
io.dccm_dma_ecc_error := io.lsu_double_ecc_error_r //from ecc
|
||||||
|
io.dccm_dma_rdata := lsu_rdata_corr_r
|
||||||
|
//Registers
|
||||||
|
io.dccm_rdata_hi_r := rvdffe(io.dccm_rdata_hi_m,io.lsu_dccm_rden_m.asBool,clock,io.scan_mode.asBool)
|
||||||
|
io.dccm_rdata_lo_r := rvdffe(io.dccm_rdata_lo_m,io.lsu_dccm_rden_m.asBool,clock,io.scan_mode.asBool)
|
||||||
|
io.dccm_data_ecc_hi_r := rvdffe(io.dccm_data_ecc_hi_m,io.lsu_dccm_rden_m.asBool,clock,io.scan_mode.asBool)
|
||||||
|
io.dccm_data_ecc_lo_r := rvdffe(io.dccm_data_ecc_lo_m,io.lsu_dccm_rden_m.asBool,clock,io.scan_mode.asBool)
|
||||||
|
stbuf_fwdbyteen_r := withClock(io.lsu_c2_r_clk){RegNext(Cat(io.stbuf_fwdbyteen_hi_m,io.stbuf_fwdbyteen_lo_m),0.U)}
|
||||||
|
stbuf_fwddata_r := withClock(io.lsu_c2_r_clk){RegNext(Cat(io.stbuf_fwddata_hi_m ,io.stbuf_fwddata_lo_m ),0.U)}
|
||||||
|
picm_rd_data_r_32 := withClock(io.lsu_c2_r_clk){RegNext(picm_rd_data_m(31,0),0.U)}
|
||||||
|
picm_rd_data_r := Cat(picm_rd_data_r_32,picm_rd_data_r_32)
|
||||||
|
io.dccm_dma_rtag := withClock(io.lsu_c1_r_clk){RegNext(io.dma_mem_tag_m,0.U)}
|
||||||
|
|
||||||
|
lsu_rdata_corr_r := Reverse(Cat(VecInit.tabulate(8)(i=> Reverse(Mux(stbuf_fwdbyteen_r(i).asBool,stbuf_fwddata_r((8*i)+7,8*i),Mux(io.addr_in_pic_r.asBool,picm_rd_data_r((8*i)+7,8*i),dccm_rdata_corr_r((8*i)+7,8*i)))))))
|
||||||
|
lsu_rdata_r := Reverse(Cat(VecInit.tabulate(8)(i=> Reverse(Mux(stbuf_fwdbyteen_r(i).asBool,stbuf_fwddata_r((8*i)+7,8*i),Mux(io.addr_in_pic_r.asBool,picm_rd_data_r((8*i)+7,8*i),dccm_rdata_r((8*i)+7,8*i)))))))
|
||||||
|
io.lsu_ld_data_r := lsu_rdata_r>> 8.U*io.lsu_addr_r(1,0)
|
||||||
|
io.lsu_ld_data_corr_r := lsu_rdata_corr_r >> 8.U*io.lsu_addr_r(1,0)
|
||||||
|
}
|
||||||
|
|
||||||
|
else{
|
||||||
|
io.dccm_dma_rvalid := io.lsu_pkt_m.valid & io.lsu_pkt_m.load & io.lsu_pkt_m.dma
|
||||||
|
io.dccm_dma_ecc_error := io.lsu_double_ecc_error_m //from ecc
|
||||||
|
io.dccm_dma_rdata := lsu_rdata_corr_m
|
||||||
|
io.dccm_dma_rtag := io.dma_mem_tag_m
|
||||||
|
io.dccm_rdata_lo_r := 0.U
|
||||||
|
io.dccm_rdata_hi_r := 0.U
|
||||||
|
io.dccm_data_ecc_hi_r := 0.U
|
||||||
|
io.dccm_data_ecc_lo_r := 0.U
|
||||||
|
io.lsu_ld_data_r := 0.U
|
||||||
|
//Registers
|
||||||
|
io.lsu_ld_data_corr_r := withClock(io.lsu_c2_r_clk){RegNext(lsu_ld_data_corr_m,0.U)}
|
||||||
|
lsu_rdata_corr_m := Reverse(Cat(VecInit.tabulate(8)(i=> Reverse(Mux(((Cat(io.stbuf_fwdbyteen_hi_m,io.stbuf_fwdbyteen_lo_m))(i)).asBool,(Cat(io.stbuf_fwddata_hi_m,io.stbuf_fwddata_lo_m))((8*i)+7,8*i),Mux(io.addr_in_pic_m.asBool,picm_rd_data_m((8*i)+7,8*i),dccm_rdata_corr_m((8*i)+7,8*i)))))))
|
||||||
|
lsu_rdata_m := Reverse(Cat(VecInit.tabulate(8)(i=> Reverse(Mux(((Cat(io.stbuf_fwdbyteen_hi_m,io.stbuf_fwdbyteen_lo_m))(i)).asBool,(Cat(io.stbuf_fwddata_hi_m,io.stbuf_fwddata_lo_m))((8*i)+7,8*i),Mux(io.addr_in_pic_m.asBool,picm_rd_data_m((8*i)+7,8*i),dccm_rdata_m((8*i)+7,8*i)))))))
|
||||||
|
io.lsu_ld_data_m := lsu_rdata_m >> 8.U*io.lsu_addr_m(1,0)
|
||||||
|
lsu_ld_data_corr_m := lsu_rdata_corr_m >> 8.U*io.lsu_addr_m(1,0)
|
||||||
|
}
|
||||||
|
|
||||||
|
//Ecc error kill
|
||||||
|
val kill_ecc_corr_lo_r = (((io.lsu_addr_d(DCCM_BITS-1,2) === io.lsu_addr_r(DCCM_BITS-1,2)).asUInt | (io.end_addr_d(DCCM_BITS-1,2) === io.lsu_addr_r(DCCM_BITS-1,2)).asUInt) & io.lsu_pkt_d.valid & io.lsu_pkt_d.store & io.lsu_pkt_d.dma & io.addr_in_dccm_d) |
|
||||||
|
(((io.lsu_addr_m(DCCM_BITS-1,2) === io.lsu_addr_r(DCCM_BITS-1,2)).asUInt | (io.end_addr_m(DCCM_BITS-1,2) === io.lsu_addr_r(DCCM_BITS-1,2)).asUInt) & io.lsu_pkt_m.valid & io.lsu_pkt_m.store & io.lsu_pkt_m.dma & io.addr_in_dccm_m)
|
||||||
|
|
||||||
|
val kill_ecc_corr_hi_r = (((io.lsu_addr_d(DCCM_BITS-1,2) === io.end_addr_r(DCCM_BITS-1,2)).asUInt | (io.end_addr_d(DCCM_BITS-1,2) === io.end_addr_r(DCCM_BITS-1,2)).asUInt) & io.lsu_pkt_d.valid & io.lsu_pkt_d.store & io.lsu_pkt_d.dma & io.addr_in_dccm_d) |
|
||||||
|
(((io.lsu_addr_m(DCCM_BITS-1,2) === io.end_addr_r(DCCM_BITS-1,2)).asUInt | (io.end_addr_m(DCCM_BITS-1,2) === io.end_addr_r(DCCM_BITS-1,2)).asUInt) & io.lsu_pkt_m.valid & io.lsu_pkt_m.store & io.lsu_pkt_m.dma & io.addr_in_dccm_m)
|
||||||
|
|
||||||
|
val ld_single_ecc_error_lo_r = io.lsu_pkt_r.load & io.single_ecc_error_lo_r & !io.lsu_raw_fwd_lo_r
|
||||||
|
val ld_single_ecc_error_hi_r = io.lsu_pkt_r.load & io.single_ecc_error_hi_r & !io.lsu_raw_fwd_hi_r
|
||||||
|
io.ld_single_ecc_error_r := (ld_single_ecc_error_lo_r | ld_single_ecc_error_hi_r) & !io.lsu_double_ecc_error_r
|
||||||
|
val ld_single_ecc_error_lo_r_ns = ld_single_ecc_error_lo_r & (io.lsu_commit_r | io.lsu_pkt_r.dma) & !kill_ecc_corr_lo_r
|
||||||
|
val ld_single_ecc_error_hi_r_ns = ld_single_ecc_error_hi_r & (io.lsu_commit_r | io.lsu_pkt_r.dma) & !kill_ecc_corr_hi_r
|
||||||
|
|
||||||
|
val lsu_double_ecc_error_r_ff = withClock(io.lsu_free_c2_clk){RegNext(io.lsu_double_ecc_error_r,0.U)}
|
||||||
|
val ld_single_ecc_error_hi_r_ff = withClock(io.lsu_free_c2_clk){RegNext(ld_single_ecc_error_hi_r_ns,0.U)}
|
||||||
|
val ld_single_ecc_error_lo_r_ff = withClock(io.lsu_free_c2_clk){RegNext(ld_single_ecc_error_lo_r_ns,0.U)}
|
||||||
|
|
||||||
|
val ld_sec_addr_hi_r_ff = rvdffe(io.end_addr_r(DCCM_BITS-1,0),io.ld_single_ecc_error_r.asBool,clock,io.scan_mode.asBool)
|
||||||
|
val ld_sec_addr_lo_r_ff = rvdffe(io.lsu_addr_r(DCCM_BITS-1,0),io.ld_single_ecc_error_r.asBool,clock,io.scan_mode.asBool)
|
||||||
|
val lsu_dccm_rden_d = io.lsu_pkt_d.valid & (io.lsu_pkt_d.load | (io.lsu_pkt_d.store & (!(io.lsu_pkt_d.word | io.lsu_pkt_d.dword) | (io.lsu_addr_d(1,0) =/= 0.U(2.W))))) & io.addr_in_dccm_d
|
||||||
|
val lsu_dccm_wren_d = io.dma_dccm_wen
|
||||||
|
|
||||||
|
io.ld_single_ecc_error_r_ff := (ld_single_ecc_error_lo_r_ff | ld_single_ecc_error_hi_r_ff) & !lsu_double_ecc_error_r_ff
|
||||||
|
io.lsu_stbuf_commit_any := io.stbuf_reqvld_any & (!(lsu_dccm_rden_d | lsu_dccm_wren_d | io.ld_single_ecc_error_r_ff) |
|
||||||
|
(lsu_dccm_rden_d & !((io.stbuf_addr_any(DCCM_WIDTH_BITS+DCCM_BANK_BITS-1,DCCM_WIDTH_BITS) === io.lsu_addr_d(DCCM_WIDTH_BITS+DCCM_BANK_BITS-1,DCCM_WIDTH_BITS)).asUInt |
|
||||||
|
(io.stbuf_addr_any(DCCM_WIDTH_BITS+DCCM_BANK_BITS-1,DCCM_WIDTH_BITS) === io.end_addr_d(DCCM_WIDTH_BITS+DCCM_BANK_BITS-1,DCCM_WIDTH_BITS)).asUInt)))
|
||||||
|
|
||||||
|
|
||||||
|
//DCCM inputs
|
||||||
|
io.dccm_wren := lsu_dccm_wren_d | io.lsu_stbuf_commit_any | io.ld_single_ecc_error_r_ff
|
||||||
|
io.dccm_rden := lsu_dccm_rden_d & io.addr_in_dccm_d
|
||||||
|
|
||||||
|
io.dccm_wr_addr_lo := Mux(io.ld_single_ecc_error_r_ff.asBool,
|
||||||
|
Mux(ld_single_ecc_error_lo_r_ff===1.U,ld_sec_addr_lo_r_ff(DCCM_BITS-1,0),ld_sec_addr_hi_r_ff(DCCM_BITS-1,0)),
|
||||||
|
Mux(lsu_dccm_wren_d.asBool,io.lsu_addr_d(DCCM_BITS-1,0),io.stbuf_addr_any(DCCM_BITS-1,0)))
|
||||||
|
|
||||||
|
io.dccm_wr_addr_hi := Mux(io.ld_single_ecc_error_r_ff.asBool,
|
||||||
|
Mux(ld_single_ecc_error_hi_r_ff===1.U, ld_sec_addr_hi_r_ff(DCCM_BITS-1,0), ld_sec_addr_lo_r_ff(DCCM_BITS-1,0)),
|
||||||
|
Mux(lsu_dccm_wren_d.asBool, io.end_addr_d(DCCM_BITS-1,0),io.stbuf_addr_any(DCCM_BITS-1,0)))
|
||||||
|
|
||||||
|
io.dccm_rd_addr_lo := io.lsu_addr_d(DCCM_BITS-1,0)
|
||||||
|
io.dccm_rd_addr_hi := io.end_addr_d(DCCM_BITS-1,0)
|
||||||
|
|
||||||
|
io.dccm_wr_data_lo := Mux(io.ld_single_ecc_error_r_ff.asBool,
|
||||||
|
Mux(ld_single_ecc_error_lo_r_ff===0.U,Cat(io.sec_data_ecc_lo_r_ff(DCCM_ECC_WIDTH-1,0),io.sec_data_lo_r_ff(DCCM_DATA_WIDTH-1,0)) ,
|
||||||
|
Cat(io.sec_data_ecc_hi_r_ff(DCCM_ECC_WIDTH-1,0),io.sec_data_hi_r_ff(DCCM_DATA_WIDTH-1,0))) ,
|
||||||
|
Mux(io.dma_dccm_wen.asBool,Cat(io.dma_dccm_wdata_ecc_lo(DCCM_ECC_WIDTH-1,0),io.dma_dccm_wdata_lo(DCCM_DATA_WIDTH-1,0)),
|
||||||
|
Cat(io.stbuf_ecc_any(DCCM_ECC_WIDTH-1,0),io.stbuf_data_any(DCCM_DATA_WIDTH-1,0))))
|
||||||
|
|
||||||
|
io.dccm_wr_data_hi := Mux(io.ld_single_ecc_error_r_ff.asBool,
|
||||||
|
Mux(ld_single_ecc_error_hi_r_ff===0.U, Cat(io.sec_data_ecc_hi_r_ff(DCCM_ECC_WIDTH-1,0),io.sec_data_hi_r_ff(DCCM_DATA_WIDTH-1,0)),
|
||||||
|
Cat(io.sec_data_ecc_lo_r_ff(DCCM_ECC_WIDTH-1,0),io.sec_data_lo_r_ff(DCCM_DATA_WIDTH-1,0))),
|
||||||
|
Mux(io.dma_dccm_wen.asBool, Cat(io.dma_dccm_wdata_ecc_hi(DCCM_ECC_WIDTH-1,0),io.dma_dccm_wdata_hi(DCCM_DATA_WIDTH-1,0)),
|
||||||
|
Cat(io.stbuf_ecc_any(DCCM_ECC_WIDTH-1,0),io.stbuf_data_any(DCCM_DATA_WIDTH-1,0))))
|
||||||
|
////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||||
|
// DCCM outputs
|
||||||
|
val store_byteen_m = (Fill(4,io.lsu_pkt_m.store)) & ((Fill(4,io.lsu_pkt_m.by) & 1.U(4.W)) |
|
||||||
|
(Fill(4,io.lsu_pkt_m.half) & 3.U(4.W)) |
|
||||||
|
(Fill(4,io.lsu_pkt_m.word) & 15.U(4.W)))
|
||||||
|
|
||||||
|
val store_byteen_r = (Fill(4,io.lsu_pkt_r.store)) & ((Fill(4,io.lsu_pkt_r.by) & 1.U(4.W)) |
|
||||||
|
(Fill(4,io.lsu_pkt_r.half) & 3.U(4.W)) |
|
||||||
|
(Fill(4,io.lsu_pkt_r.word) & 15.U(4.W)))
|
||||||
|
val store_byteen_ext_m = WireInit(UInt(8.W),0.U)
|
||||||
|
store_byteen_ext_m := store_byteen_m(3,0) << io.lsu_addr_m(1,0) // The packet in m
|
||||||
|
val store_byteen_ext_r = WireInit(UInt(8.W),0.U)
|
||||||
|
store_byteen_ext_r := store_byteen_r(3,0) << io.lsu_addr_r(1,0)
|
||||||
|
|
||||||
|
//LM: If store buffer addr matches with the address in the m-stage then there will be bypassed
|
||||||
|
val dccm_wr_bypass_d_m_lo = (io.stbuf_addr_any(DCCM_BITS-1,2) === io.lsu_addr_m(DCCM_BITS-1,2)) & io.addr_in_dccm_m
|
||||||
|
val dccm_wr_bypass_d_m_hi = (io.stbuf_addr_any(DCCM_BITS-1,2) === io.end_addr_m(DCCM_BITS-1,2)) & io.addr_in_dccm_m
|
||||||
|
|
||||||
|
val dccm_wr_bypass_d_r_lo = (io.stbuf_addr_any(DCCM_BITS-1,2) === io.lsu_addr_r(DCCM_BITS-1,2)) & io.addr_in_dccm_r
|
||||||
|
val dccm_wr_bypass_d_r_hi = (io.stbuf_addr_any(DCCM_BITS-1,2) === io.end_addr_r(DCCM_BITS-1,2)) & io.addr_in_dccm_r
|
||||||
|
|
||||||
|
val dccm_wr_bypass_d_m_hi_Q = WireInit(0.U(1.W))
|
||||||
|
val dccm_wr_bypass_d_m_lo_Q = WireInit(0.U(1.W))
|
||||||
|
val dccm_wren_Q = WireInit(0.U(1.W))
|
||||||
|
val dccm_wr_data_Q = WireInit(0.U(32.W))
|
||||||
|
val store_data_pre_r = WireInit(0.U(64.W))
|
||||||
|
val store_data_pre_hi_r = WireInit(0.U(32.W))
|
||||||
|
val store_data_pre_lo_r = WireInit(0.U(32.W))
|
||||||
|
val store_data_pre_m = WireInit(0.U(64.W))
|
||||||
|
val store_data_hi_m = WireInit(0.U(32.W))
|
||||||
|
val store_data_lo_m = WireInit(0.U(32.W))
|
||||||
|
|
||||||
|
if(LOAD_TO_USE_PLUS1 == 1){
|
||||||
|
store_data_pre_r := Cat(Fill(32,0.U),io.store_data_r(31,0)) << 8.U*io.lsu_addr_r(1,0)
|
||||||
|
store_data_pre_hi_r := store_data_pre_r(63,32)
|
||||||
|
store_data_pre_lo_r := store_data_pre_r(31, 0)
|
||||||
|
io.store_data_lo_r := Reverse(Cat(VecInit.tabulate(4)(i=> Reverse(Mux(store_byteen_ext_r(i).asBool, store_data_pre_lo_r((8*i)+7,8*i), Mux((dccm_wren_Q & dccm_wr_bypass_d_m_lo_Q).asBool, dccm_wr_data_Q((8*i)+7,8*i),io.sec_data_lo_r((8*i)+7,8*i)))))))
|
||||||
|
io.store_data_hi_r := Reverse(Cat(VecInit.tabulate(4)(i=> Reverse(Mux(store_byteen_ext_r(i+4).asBool,store_data_pre_hi_r((8*i)+7,8*i), Mux((dccm_wren_Q & dccm_wr_bypass_d_m_hi_Q).asBool, dccm_wr_data_Q((8*i)+7,8*i),io.sec_data_hi_r((8*i)+7,8*i)))))))
|
||||||
|
io.store_datafn_lo_r := Reverse(Cat(VecInit.tabulate(4)(i=> Reverse(Mux(store_byteen_ext_r(i).asBool, store_data_pre_lo_r((8*i)+7,8*i), Mux((io.lsu_stbuf_commit_any & dccm_wr_bypass_d_r_lo).asBool,io.stbuf_data_any((8*i)+7,(8*i)),Mux((dccm_wren_Q & dccm_wr_bypass_d_m_lo_Q).asBool, dccm_wr_data_Q((8*i)+7,8*i),io.sec_data_lo_r((8*i)+7,8*i))))))))
|
||||||
|
io.store_datafn_hi_r := Reverse(Cat(VecInit.tabulate(4)(i=> Reverse(Mux(store_byteen_ext_r(i+4).asBool,store_data_pre_hi_r((8*i)+7,8*i), Mux((io.lsu_stbuf_commit_any & dccm_wr_bypass_d_r_lo).asBool,io.stbuf_data_any((8*i)+7,(8*i)),Mux((dccm_wren_Q & dccm_wr_bypass_d_m_hi_Q).asBool, dccm_wr_data_Q((8*i)+7,8*i),io.sec_data_hi_r((8*i)+7,8*i))))))))
|
||||||
|
dccm_wren_Q := withClock(io.lsu_free_c2_clk){RegNext(io.lsu_stbuf_commit_any,0.U)}
|
||||||
|
dccm_wr_data_Q := rvdffe(io.stbuf_data_any,io.lsu_stbuf_commit_any.asBool,clock,io.scan_mode.asBool)
|
||||||
|
dccm_wr_bypass_d_m_lo_Q := withClock(io.lsu_free_c2_clk){RegNext(dccm_wr_bypass_d_m_lo,0.U)}
|
||||||
|
dccm_wr_bypass_d_m_hi_Q := withClock(io.lsu_free_c2_clk){RegNext(dccm_wr_bypass_d_m_hi,0.U)}
|
||||||
|
io.store_data_r := withClock(io.lsu_store_c1_r_clk){RegNext(io.store_data_m,0.U)}
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
store_data_pre_m := Cat(Fill(32,0.U),io.store_data_m(31,0)) << 8.U*io.lsu_addr_m(1,0)
|
||||||
|
store_data_hi_m := store_data_pre_m(63,32)
|
||||||
|
store_data_lo_m := store_data_pre_m(31, 0)
|
||||||
|
io.store_data_lo_r := withClock(io.lsu_store_c1_r_clk){RegNext(Reverse(Cat(VecInit.tabulate(4)(i=> Reverse(Mux(store_byteen_ext_m(i).asBool, store_data_lo_m((8*i)+7,8*i), Mux((io.lsu_stbuf_commit_any & dccm_wr_bypass_d_m_lo).asBool, io.stbuf_data_any((8*i)+7,8*i),io.sec_data_lo_m((8*i)+7,8*i))))))),0.U)}
|
||||||
|
io.store_data_hi_r := withClock(io.lsu_store_c1_r_clk){RegNext(Reverse(Cat(VecInit.tabulate(4)(i=> Reverse(Mux(store_byteen_ext_m(i+4).asBool,store_data_hi_m((8*i)+7,8*i), Mux((io.lsu_stbuf_commit_any & dccm_wr_bypass_d_m_hi).asBool, io.stbuf_data_any((8*i)+7,8*i),io.sec_data_hi_m((8*i)+7,8*i))))))),0.U)}
|
||||||
|
io.store_datafn_lo_r := Reverse(Cat(VecInit.tabulate(4)(i=> Reverse(Mux((io.lsu_stbuf_commit_any & dccm_wr_bypass_d_r_lo & !store_byteen_ext_r(i)).asBool,io.stbuf_data_any((8*i)+7,8*i),io.store_data_lo_r((8*i)+7,8*i))))))
|
||||||
|
io.store_datafn_hi_r := Reverse(Cat(VecInit.tabulate(4)(i=> Reverse(Mux((io.lsu_stbuf_commit_any & dccm_wr_bypass_d_r_lo & !store_byteen_ext_r(i)).asBool,io.stbuf_data_any((8*i)+7,8*i),io.store_data_hi_r((8*i)+7,8*i))))))
|
||||||
|
io.store_data_r := (Cat(io.store_data_hi_r(31,0),io.store_data_lo_r(31,0)) >> 8.U*io.lsu_addr_r(1,0)) & Reverse(Cat(VecInit.tabulate(4)(i=> Fill(8,store_byteen_r(i)))))
|
||||||
|
}
|
||||||
|
io.dccm_rdata_lo_m := io.dccm_rd_data_lo(DCCM_DATA_WIDTH-1,0) //4 lines
|
||||||
|
io.dccm_rdata_hi_m := io.dccm_rd_data_hi(DCCM_DATA_WIDTH-1,0)
|
||||||
|
io.dccm_data_ecc_lo_m := io.dccm_rd_data_lo(DCCM_FDATA_WIDTH-1,DCCM_DATA_WIDTH)
|
||||||
|
io.dccm_data_ecc_hi_m := io.dccm_rd_data_hi(DCCM_FDATA_WIDTH-1,DCCM_DATA_WIDTH)
|
||||||
|
|
||||||
|
io.picm_wren := (io.lsu_pkt_r.valid & io.lsu_pkt_r.store & io.addr_in_pic_r & io.lsu_commit_r) | io.dma_pic_wen
|
||||||
|
io.picm_rden := io.lsu_pkt_d.valid & io.lsu_pkt_d.load & io.addr_in_pic_d
|
||||||
|
io.picm_mken := io.lsu_pkt_d.valid & io.lsu_pkt_d.store & io.addr_in_pic_d
|
||||||
|
io.picm_rdaddr := PIC_BASE_ADDR.U | Cat(Fill(32-PIC_BITS,0.U),io.lsu_addr_d(PIC_BITS-1,0))
|
||||||
|
io.picm_wraddr := PIC_BASE_ADDR.U | Cat(Fill(32-PIC_BITS,0.U),Mux(io.dma_pic_wen.asBool,io.dma_mem_addr(PIC_BITS-1,0),io.lsu_addr_r(PIC_BITS-1,0)))
|
||||||
|
io.picm_mask_data_m := picm_rd_data_m(31,0)
|
||||||
|
io.picm_wr_data := Mux(io.dma_pic_wen.asBool,io.dma_mem_wdata(31,0),io.store_datafn_lo_r(31,0))
|
||||||
|
|
||||||
|
if(DCCM_ENABLE){
|
||||||
|
io.lsu_dccm_rden_m := withClock(io.lsu_c2_m_clk){RegNext(lsu_dccm_rden_d,0.U)}
|
||||||
|
io.lsu_dccm_rden_r := withClock(io.lsu_c2_r_clk){RegNext(io.lsu_dccm_rden_m,0.U)}
|
||||||
|
}
|
||||||
|
else{
|
||||||
|
io.lsu_dccm_rden_m := 0.U
|
||||||
|
io.lsu_dccm_rden_r := 0.U}
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
object dccm_ctl extends App{
|
||||||
|
println("Generate Verilog")
|
||||||
|
println((new chisel3.stage.ChiselStage).emitVerilog(new el2_lsu_dccm_ctl()))
|
||||||
|
}
|
||||||
|
|
||||||
|
|
@ -0,0 +1,164 @@
|
||||||
|
package lsu
|
||||||
|
import chisel3._
|
||||||
|
import chisel3.util._
|
||||||
|
import chisel3.experimental.chiselName
|
||||||
|
import include._
|
||||||
|
import lib._
|
||||||
|
|
||||||
|
@chiselName
|
||||||
|
class el2_lsu_ecc extends Module with el2_lib with RequireAsyncReset {
|
||||||
|
val io = IO(new Bundle{
|
||||||
|
|
||||||
|
val lsu_c2_r_clk = Input(Clock())
|
||||||
|
val lsu_pkt_m = Input(new el2_lsu_pkt_t)
|
||||||
|
val lsu_pkt_r = Input(new el2_lsu_pkt_t)
|
||||||
|
val stbuf_data_any = Input(UInt(DCCM_DATA_WIDTH.W))
|
||||||
|
val dec_tlu_core_ecc_disable = Input(Bool())
|
||||||
|
val lsu_dccm_rden_r = Input(Bool())
|
||||||
|
val addr_in_dccm_r = Input(Bool())
|
||||||
|
|
||||||
|
val lsu_addr_r = Input(UInt(DCCM_BITS.W))
|
||||||
|
val end_addr_r = Input(UInt(DCCM_BITS.W))
|
||||||
|
val lsu_addr_m = Input(UInt(DCCM_BITS.W))
|
||||||
|
val end_addr_m = Input(UInt(DCCM_BITS.W))
|
||||||
|
|
||||||
|
val dccm_rdata_hi_r = Input(UInt(DCCM_DATA_WIDTH.W))
|
||||||
|
val dccm_rdata_lo_r = Input(UInt(DCCM_DATA_WIDTH.W))
|
||||||
|
val dccm_rdata_hi_m = Input(UInt(DCCM_DATA_WIDTH.W))
|
||||||
|
val dccm_rdata_lo_m = Input(UInt(DCCM_DATA_WIDTH.W))
|
||||||
|
|
||||||
|
val dccm_data_ecc_hi_r = Input(UInt(DCCM_ECC_WIDTH.W))
|
||||||
|
val dccm_data_ecc_lo_r = Input(UInt(DCCM_ECC_WIDTH.W))
|
||||||
|
val dccm_data_ecc_hi_m = Input(UInt(DCCM_ECC_WIDTH.W))
|
||||||
|
val dccm_data_ecc_lo_m = Input(UInt(DCCM_ECC_WIDTH.W))
|
||||||
|
|
||||||
|
val ld_single_ecc_error_r = Input(Bool())
|
||||||
|
val ld_single_ecc_error_r_ff = Input(Bool())
|
||||||
|
val lsu_dccm_rden_m = Input(Bool())
|
||||||
|
val addr_in_dccm_m = Input(Bool())
|
||||||
|
|
||||||
|
val dma_dccm_wen = Input(Bool())
|
||||||
|
val dma_dccm_wdata_lo = Input(UInt(32.W))
|
||||||
|
val dma_dccm_wdata_hi = Input(UInt(32.W))
|
||||||
|
|
||||||
|
val scan_mode = Input(Bool())
|
||||||
|
|
||||||
|
//Outputs
|
||||||
|
val sec_data_hi_r = Output(UInt(DCCM_DATA_WIDTH.W))
|
||||||
|
val sec_data_lo_r = Output(UInt(DCCM_DATA_WIDTH.W))
|
||||||
|
val sec_data_hi_m = Output(UInt(DCCM_DATA_WIDTH.W))
|
||||||
|
val sec_data_lo_m = Output(UInt(DCCM_DATA_WIDTH.W))
|
||||||
|
val sec_data_hi_r_ff = Output(UInt(DCCM_DATA_WIDTH.W))
|
||||||
|
val sec_data_lo_r_ff = Output(UInt(DCCM_DATA_WIDTH.W))
|
||||||
|
|
||||||
|
val dma_dccm_wdata_ecc_hi = Output(UInt(DCCM_ECC_WIDTH.W))
|
||||||
|
val dma_dccm_wdata_ecc_lo = Output(UInt(DCCM_ECC_WIDTH.W))
|
||||||
|
val stbuf_ecc_any = Output(UInt(DCCM_ECC_WIDTH.W))
|
||||||
|
val sec_data_ecc_hi_r_ff = Output(UInt(DCCM_ECC_WIDTH.W))
|
||||||
|
val sec_data_ecc_lo_r_ff = Output(UInt(DCCM_ECC_WIDTH.W))
|
||||||
|
|
||||||
|
val single_ecc_error_hi_r = Output(Bool())
|
||||||
|
val single_ecc_error_lo_r = Output(Bool())
|
||||||
|
val lsu_single_ecc_error_r = Output(Bool())
|
||||||
|
val lsu_double_ecc_error_r = Output(Bool())
|
||||||
|
val lsu_single_ecc_error_m = Output(Bool())
|
||||||
|
val lsu_double_ecc_error_m = Output(Bool())
|
||||||
|
})
|
||||||
|
val is_ldst_r = WireInit(Bool(),init = 0.U)
|
||||||
|
val is_ldst_hi_any = WireInit(Bool(),init = 0.U)
|
||||||
|
val is_ldst_lo_any = WireInit(Bool(),init = 0.U)
|
||||||
|
val dccm_wdata_hi_any = WireInit(0.U(DCCM_DATA_WIDTH.W))
|
||||||
|
val dccm_wdata_lo_any = WireInit(0.U(DCCM_DATA_WIDTH.W))
|
||||||
|
val dccm_rdata_hi_any = WireInit(0.U(DCCM_DATA_WIDTH.W))
|
||||||
|
val dccm_rdata_lo_any = WireInit(0.U(DCCM_DATA_WIDTH.W))
|
||||||
|
// val dccm_wdata_ecc_hi_any = WireInit(0.U(DCCM_ECC_WIDTH.W))
|
||||||
|
//val dccm_wdata_ecc_lo_any = WireInit(0.U(DCCM_ECC_WIDTH.W))
|
||||||
|
val dccm_data_ecc_hi_any = WireInit(0.U(DCCM_ECC_WIDTH.W))
|
||||||
|
val dccm_data_ecc_lo_any = WireInit(0.U(DCCM_ECC_WIDTH.W))
|
||||||
|
val double_ecc_error_hi_m = WireInit(Bool(),init = 0.U)
|
||||||
|
val double_ecc_error_lo_m = WireInit(Bool(),init = 0.U)
|
||||||
|
val double_ecc_error_hi_r = WireInit(Bool(),init = 0.U)
|
||||||
|
val double_ecc_error_lo_r = WireInit(Bool(),init = 0.U)
|
||||||
|
val ldst_dual_m = WireInit(Bool(),init = 0.U)
|
||||||
|
val ldst_dual_r = WireInit(Bool(),init = 0.U)
|
||||||
|
val is_ldst_m = WireInit(Bool(),init = 0.U)
|
||||||
|
val is_ldst_hi_m = WireInit(Bool(),init = 0.U)
|
||||||
|
val is_ldst_lo_m = WireInit(Bool(),init = 0.U)
|
||||||
|
val is_ldst_hi_r = WireInit(Bool(),init = 0.U)
|
||||||
|
val is_ldst_lo_r = WireInit(Bool(),init = 0.U)
|
||||||
|
|
||||||
|
io.sec_data_hi_m :=0.U
|
||||||
|
io.sec_data_lo_m :=0.U
|
||||||
|
io.lsu_single_ecc_error_m :=0.U
|
||||||
|
io.lsu_double_ecc_error_m :=0.U
|
||||||
|
|
||||||
|
//////////////////////////////CODE STARTS HERE///////////////////////
|
||||||
|
val (ecc_out_hi_nc, sec_data_hi_any, single_ecc_error_hi_any, double_ecc_error_hi_any) = if(DCCM_ENABLE)
|
||||||
|
rvecc_decode(is_ldst_hi_any, dccm_rdata_hi_any, dccm_data_ecc_hi_any, 0.U) else (0.U, 0.U, 0.U, 0.U)
|
||||||
|
val ( ecc_out_lo_nc, sec_data_lo_any, single_ecc_error_lo_any, double_ecc_error_lo_any) = if(DCCM_ENABLE)
|
||||||
|
rvecc_decode(is_ldst_lo_any, dccm_rdata_lo_any, dccm_data_ecc_lo_any, 0.U) else (0.U, 0.U, 0.U, 0.U)
|
||||||
|
val dccm_wdata_ecc_lo_any = if(DCCM_ENABLE) rvecc_encode(dccm_wdata_lo_any) else (0.U)
|
||||||
|
val dccm_wdata_ecc_hi_any = if(DCCM_ENABLE) rvecc_encode(dccm_wdata_hi_any) else (0.U)
|
||||||
|
|
||||||
|
when (LOAD_TO_USE_PLUS1.B) {
|
||||||
|
ldst_dual_r := io.lsu_addr_r(2) =/= io.end_addr_r(2)
|
||||||
|
is_ldst_r := io.lsu_pkt_r.valid & (io.lsu_pkt_r.load | io.lsu_pkt_r.store) & io.addr_in_dccm_r & io.lsu_dccm_rden_r
|
||||||
|
is_ldst_lo_r := is_ldst_r & !io.dec_tlu_core_ecc_disable
|
||||||
|
is_ldst_hi_r := is_ldst_r & (ldst_dual_r | io.lsu_pkt_r.dma) & !io.dec_tlu_core_ecc_disable
|
||||||
|
is_ldst_hi_any := is_ldst_hi_r
|
||||||
|
dccm_rdata_hi_any := io.dccm_rdata_hi_r
|
||||||
|
dccm_data_ecc_hi_any := io.dccm_data_ecc_hi_r
|
||||||
|
is_ldst_lo_any := is_ldst_lo_r
|
||||||
|
dccm_rdata_lo_any := io.dccm_rdata_lo_r
|
||||||
|
dccm_data_ecc_lo_any := io.dccm_data_ecc_lo_r
|
||||||
|
io.sec_data_hi_r := sec_data_hi_any;
|
||||||
|
io.single_ecc_error_hi_r := single_ecc_error_hi_any
|
||||||
|
double_ecc_error_hi_r := double_ecc_error_hi_any
|
||||||
|
io.sec_data_lo_r := sec_data_lo_any
|
||||||
|
io.single_ecc_error_lo_r := single_ecc_error_lo_any
|
||||||
|
double_ecc_error_lo_r := double_ecc_error_lo_any
|
||||||
|
io.lsu_single_ecc_error_r := io.single_ecc_error_hi_r | io.single_ecc_error_lo_r;
|
||||||
|
io.lsu_double_ecc_error_r := double_ecc_error_hi_r | double_ecc_error_lo_r
|
||||||
|
}
|
||||||
|
.otherwise {
|
||||||
|
ldst_dual_m := io.lsu_addr_m(2) =/= io.end_addr_m(2)
|
||||||
|
is_ldst_m := io.lsu_pkt_m.valid & (io.lsu_pkt_m.load | io.lsu_pkt_m.store) & io.addr_in_dccm_m & io.lsu_dccm_rden_m
|
||||||
|
is_ldst_lo_m := is_ldst_m & !io.dec_tlu_core_ecc_disable
|
||||||
|
is_ldst_hi_m := is_ldst_m & (ldst_dual_m | io.lsu_pkt_m.dma) & !io.dec_tlu_core_ecc_disable
|
||||||
|
is_ldst_hi_any := is_ldst_hi_m
|
||||||
|
dccm_rdata_hi_any := io.dccm_rdata_hi_m
|
||||||
|
dccm_data_ecc_hi_any := io.dccm_data_ecc_hi_m
|
||||||
|
is_ldst_lo_any := is_ldst_lo_m
|
||||||
|
dccm_rdata_lo_any := io.dccm_rdata_lo_m
|
||||||
|
dccm_data_ecc_lo_any := io.dccm_data_ecc_lo_m
|
||||||
|
io.sec_data_hi_m := sec_data_hi_any
|
||||||
|
double_ecc_error_hi_m := double_ecc_error_hi_any
|
||||||
|
io.sec_data_lo_m := sec_data_lo_any
|
||||||
|
double_ecc_error_lo_m := double_ecc_error_lo_any
|
||||||
|
io.lsu_single_ecc_error_m := single_ecc_error_hi_any | single_ecc_error_lo_any;
|
||||||
|
io.lsu_double_ecc_error_m := double_ecc_error_hi_m | double_ecc_error_lo_m
|
||||||
|
|
||||||
|
withClock(io.lsu_c2_r_clk) {io.lsu_single_ecc_error_r := RegNext(io.lsu_single_ecc_error_m,0.U)}
|
||||||
|
withClock(io.lsu_c2_r_clk) {io.lsu_double_ecc_error_r := RegNext(io.lsu_double_ecc_error_m,0.U)}
|
||||||
|
withClock(io.lsu_c2_r_clk) {io.single_ecc_error_lo_r := RegNext(single_ecc_error_lo_any,0.U)}
|
||||||
|
withClock(io.lsu_c2_r_clk) {io.single_ecc_error_hi_r := RegNext(single_ecc_error_hi_any,0.U)}
|
||||||
|
withClock(io.lsu_c2_r_clk) {io.sec_data_hi_r := RegNext(io.sec_data_hi_m,0.U)}
|
||||||
|
withClock(io.lsu_c2_r_clk) {io.sec_data_lo_r := RegNext(io.sec_data_lo_m,0.U)}
|
||||||
|
}
|
||||||
|
// Logic for ECC generation during write
|
||||||
|
dccm_wdata_lo_any := Mux(io.ld_single_ecc_error_r_ff.asBool, io.sec_data_lo_r_ff,Mux(io.dma_dccm_wen.asBool, io.dma_dccm_wdata_lo, io.stbuf_data_any))
|
||||||
|
dccm_wdata_hi_any := Mux(io.ld_single_ecc_error_r_ff.asBool, io.sec_data_hi_r_ff,Mux(io.dma_dccm_wen.asBool, io.dma_dccm_wdata_hi, io.stbuf_data_any))
|
||||||
|
io.sec_data_ecc_hi_r_ff := dccm_wdata_ecc_hi_any
|
||||||
|
io.sec_data_ecc_lo_r_ff := dccm_wdata_ecc_lo_any
|
||||||
|
io.stbuf_ecc_any := dccm_wdata_ecc_lo_any
|
||||||
|
io.dma_dccm_wdata_ecc_hi := dccm_wdata_ecc_hi_any
|
||||||
|
io.dma_dccm_wdata_ecc_lo := dccm_wdata_ecc_lo_any
|
||||||
|
|
||||||
|
io.sec_data_hi_r_ff := rvdffe(io.sec_data_hi_r, io.ld_single_ecc_error_r,clock,io.scan_mode)
|
||||||
|
io.sec_data_lo_r_ff := rvdffe(io.sec_data_lo_r, io.ld_single_ecc_error_r,clock,io.scan_mode)
|
||||||
|
|
||||||
|
}
|
||||||
|
object eccmain extends App{
|
||||||
|
println("Generate Verilog")
|
||||||
|
println((new chisel3.stage.ChiselStage).emitVerilog(new el2_lsu_ecc()))
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,281 @@
|
||||||
|
package lsu
|
||||||
|
import include._
|
||||||
|
import lib._
|
||||||
|
import chisel3._
|
||||||
|
import chisel3.util._
|
||||||
|
|
||||||
|
|
||||||
|
import chisel3.experimental.chiselName
|
||||||
|
@chiselName
|
||||||
|
class el2_lsu_lsc_ctl extends Module with RequireAsyncReset with el2_lib
|
||||||
|
{
|
||||||
|
val io = IO(new Bundle{
|
||||||
|
//val rst_l = IO(Input(1.W)) //implicit
|
||||||
|
val lsu_c1_m_clk = Input(Clock())
|
||||||
|
val lsu_c1_r_clk = Input(Clock())
|
||||||
|
val lsu_c2_m_clk = Input(Clock())
|
||||||
|
val lsu_c2_r_clk = Input(Clock())
|
||||||
|
val lsu_store_c1_m_clk = Input(Clock())
|
||||||
|
|
||||||
|
val lsu_ld_data_r = Input(UInt(32.W)) //DCCM data
|
||||||
|
val lsu_ld_data_corr_r = Input(UInt(32.W)) // ECC corrected data
|
||||||
|
val lsu_single_ecc_error_r = Input(UInt(1.W))
|
||||||
|
val lsu_double_ecc_error_r = Input(UInt(1.W))
|
||||||
|
|
||||||
|
val lsu_ld_data_m = Input(UInt(32.W))
|
||||||
|
val lsu_single_ecc_error_m = Input(UInt(1.W))
|
||||||
|
val lsu_double_ecc_error_m = Input(UInt(1.W))
|
||||||
|
|
||||||
|
val flush_m_up = Input(UInt(1.W))
|
||||||
|
val flush_r = Input(UInt(1.W))
|
||||||
|
|
||||||
|
val exu_lsu_rs1_d = Input(UInt(32.W)) // address
|
||||||
|
val exu_lsu_rs2_d = Input(UInt(32.W)) // store data
|
||||||
|
|
||||||
|
val lsu_p = Input(new el2_lsu_pkt_t()) // lsu control packet //coming from decode
|
||||||
|
val dec_lsu_valid_raw_d = Input(UInt(1.W)) // Raw valid for address computation
|
||||||
|
val dec_lsu_offset_d = Input(UInt(12.W))
|
||||||
|
|
||||||
|
val picm_mask_data_m = Input(UInt(32.W))
|
||||||
|
val bus_read_data_m = Input(UInt(32.W)) //coming from bus interface
|
||||||
|
|
||||||
|
val lsu_result_m = Output(UInt(32.W))
|
||||||
|
val lsu_result_corr_r = Output(UInt(32.W)) // This is the ECC corrected data going to RF
|
||||||
|
|
||||||
|
// lsu address down the pipe
|
||||||
|
val lsu_addr_d = Output(UInt(32.W))
|
||||||
|
val lsu_addr_m = Output(UInt(32.W))
|
||||||
|
val lsu_addr_r = Output(UInt(32.W))
|
||||||
|
|
||||||
|
// lsu address down the pipe - needed to check unaligned
|
||||||
|
val end_addr_d = Output(UInt(32.W))
|
||||||
|
val end_addr_m = Output(UInt(32.W))
|
||||||
|
val end_addr_r = Output(UInt(32.W))
|
||||||
|
|
||||||
|
// store data down the pipe
|
||||||
|
val store_data_m = Output(UInt(32.W))
|
||||||
|
|
||||||
|
val dec_tlu_mrac_ff = Input(UInt(32.W)) // CSR read
|
||||||
|
|
||||||
|
val lsu_exc_m = Output(UInt(1.W))
|
||||||
|
val is_sideeffects_m = Output(UInt(1.W))
|
||||||
|
val lsu_commit_r = Output(UInt(1.W))
|
||||||
|
val lsu_single_ecc_error_incr = Output(UInt(1.W))
|
||||||
|
val lsu_error_pkt_r = Output(new el2_lsu_error_pkt_t())
|
||||||
|
|
||||||
|
val lsu_fir_addr = Output(UInt(31.W)) //(31:1) in sv // fast interrupt address TBD
|
||||||
|
val lsu_fir_error = Output(UInt(2.W)) // Error during fast interrupt lookup TBD
|
||||||
|
|
||||||
|
// address in dccm/pic/external per pipe stage
|
||||||
|
val addr_in_dccm_d = Output(UInt(1.W))
|
||||||
|
val addr_in_dccm_m = Output(UInt(1.W))
|
||||||
|
val addr_in_dccm_r = Output(UInt(1.W))
|
||||||
|
|
||||||
|
val addr_in_pic_d = Output(UInt(1.W))
|
||||||
|
val addr_in_pic_m = Output(UInt(1.W))
|
||||||
|
val addr_in_pic_r = Output(UInt(1.W))
|
||||||
|
|
||||||
|
val addr_external_m = Output(UInt(1.W))
|
||||||
|
|
||||||
|
// DMA slave
|
||||||
|
val dma_dccm_req = Input(UInt(1.W))
|
||||||
|
val dma_mem_addr = Input(UInt(32.W))
|
||||||
|
val dma_mem_sz = Input(UInt(3.W))
|
||||||
|
val dma_mem_write = Input(UInt(1.W))
|
||||||
|
val dma_mem_wdata = Input(UInt(64.W))
|
||||||
|
|
||||||
|
// Store buffer related signals
|
||||||
|
val lsu_pkt_d = Output(new el2_lsu_pkt_t())
|
||||||
|
val lsu_pkt_m = Output(new el2_lsu_pkt_t())
|
||||||
|
val lsu_pkt_r = Output(new el2_lsu_pkt_t())
|
||||||
|
|
||||||
|
val scan_mode = Input(UInt(1.W))
|
||||||
|
})
|
||||||
|
|
||||||
|
|
||||||
|
val dma_pkt_d = Wire(new el2_lsu_pkt_t())
|
||||||
|
val lsu_pkt_m_in = Wire(new el2_lsu_pkt_t())
|
||||||
|
val lsu_pkt_r_in = Wire(new el2_lsu_pkt_t())
|
||||||
|
val lsu_error_pkt_m = Wire(new el2_lsu_error_pkt_t())
|
||||||
|
|
||||||
|
val lsu_rs1_d = Mux(io.dec_lsu_valid_raw_d.asBool,io.exu_lsu_rs1_d,io.dma_mem_addr)
|
||||||
|
val lsu_offset_d = io.dec_lsu_offset_d(11,0) & Fill(12,io.dec_lsu_valid_raw_d)
|
||||||
|
val rs1_d_raw = lsu_rs1_d
|
||||||
|
val offset_d = lsu_offset_d
|
||||||
|
val rs1_d = Mux(io.lsu_pkt_d.load_ldst_bypass_d.asBool,io.lsu_result_m,rs1_d_raw)
|
||||||
|
|
||||||
|
// generate the ls address
|
||||||
|
val full_addr_d = rvlsadder(rs1_d,offset_d)
|
||||||
|
|
||||||
|
val addr_offset_d = ((Fill(3,io.lsu_pkt_d.half)) & 1.U(3.W)) |
|
||||||
|
((Fill(3,io.lsu_pkt_d.word)) & 3.U(3.W)) |
|
||||||
|
((Fill(3,io.lsu_pkt_d.dword)) & 7.U(3.W))
|
||||||
|
|
||||||
|
val end_addr_offset_d = Cat(offset_d(11),offset_d(11,0)) + Cat(Fill(9,0.U),addr_offset_d(2,0))
|
||||||
|
val full_end_addr_d = rs1_d(31,0) + Cat(Fill(19,end_addr_offset_d(12)),end_addr_offset_d(12,0))
|
||||||
|
io.end_addr_d := full_end_addr_d
|
||||||
|
|
||||||
|
//optimize with bulk operator
|
||||||
|
val addrcheck = Module(new el2_lsu_addrcheck())
|
||||||
|
|
||||||
|
addrcheck.io.lsu_c2_m_clk := io.lsu_c2_m_clk
|
||||||
|
//val rst_l = IO(Input(1.W)) //implicit
|
||||||
|
addrcheck.io.start_addr_d := full_addr_d
|
||||||
|
addrcheck.io.end_addr_d := full_end_addr_d
|
||||||
|
addrcheck.io.lsu_pkt_d := io.lsu_pkt_d
|
||||||
|
addrcheck.io.dec_tlu_mrac_ff := io.dec_tlu_mrac_ff
|
||||||
|
addrcheck.io.rs1_region_d := rs1_d(31,28)
|
||||||
|
addrcheck.io.rs1_d := rs1_d
|
||||||
|
io.is_sideeffects_m := addrcheck.io.is_sideeffects_m
|
||||||
|
io.addr_in_dccm_d := addrcheck.io.addr_in_dccm_d
|
||||||
|
io.addr_in_pic_d := addrcheck.io.addr_in_pic_d
|
||||||
|
val addr_external_d = addrcheck.io.addr_external_d
|
||||||
|
val access_fault_d = addrcheck.io.access_fault_d
|
||||||
|
val misaligned_fault_d = addrcheck.io.misaligned_fault_d
|
||||||
|
val exc_mscause_d = addrcheck.io.exc_mscause_d
|
||||||
|
val fir_dccm_access_error_d = addrcheck.io.fir_dccm_access_error_d
|
||||||
|
val fir_nondccm_access_error_d = addrcheck.io.fir_nondccm_access_error_d
|
||||||
|
addrcheck.io.scan_mode := io.scan_mode
|
||||||
|
|
||||||
|
|
||||||
|
val exc_mscause_r = WireInit(0.U(4.W))
|
||||||
|
val fir_dccm_access_error_r = WireInit(0.U(1.W))
|
||||||
|
val fir_nondccm_access_error_r = WireInit(0.U(1.W))
|
||||||
|
val access_fault_r = WireInit(0.U(1.W))
|
||||||
|
val misaligned_fault_r = WireInit(0.U(1.W))
|
||||||
|
val lsu_fir_error_m = WireInit(0.U(2.W))
|
||||||
|
val fir_dccm_access_error_m = WireInit(0.U(1.W))
|
||||||
|
val fir_nondccm_access_error_m = WireInit(0.U(1.W))
|
||||||
|
|
||||||
|
val access_fault_m = withClock(io.lsu_c1_m_clk){RegNext(access_fault_d,0.U)}
|
||||||
|
val misaligned_fault_m = withClock(io.lsu_c1_m_clk){RegNext(misaligned_fault_d,0.U)}
|
||||||
|
val exc_mscause_m = withClock(io.lsu_c1_m_clk){RegNext(exc_mscause_d,0.U)}
|
||||||
|
fir_dccm_access_error_m := withClock(io.lsu_c1_m_clk){RegNext(fir_dccm_access_error_d,0.U)}
|
||||||
|
fir_nondccm_access_error_m := withClock(io.lsu_c1_m_clk){RegNext(fir_nondccm_access_error_d,0.U)}
|
||||||
|
|
||||||
|
io.lsu_exc_m := access_fault_m | misaligned_fault_m
|
||||||
|
io.lsu_single_ecc_error_incr := (io.lsu_single_ecc_error_r & !io.lsu_double_ecc_error_r) & (io.lsu_commit_r | io.lsu_pkt_r.dma) & io.lsu_pkt_r.valid
|
||||||
|
|
||||||
|
if (LOAD_TO_USE_PLUS1 == 1){
|
||||||
|
// Generate exception packet
|
||||||
|
io.lsu_error_pkt_r.exc_valid := (access_fault_r | misaligned_fault_r | io.lsu_double_ecc_error_r) & io.lsu_pkt_r.valid & !io.lsu_pkt_r.dma & !io.lsu_pkt_r.fast_int //TBD(lsu_pkt_r.fast_int)
|
||||||
|
io.lsu_error_pkt_r.single_ecc_error := io.lsu_single_ecc_error_r & !io.lsu_error_pkt_r.exc_valid & !io.lsu_pkt_r.dma
|
||||||
|
io.lsu_error_pkt_r.inst_type := io.lsu_pkt_r.store
|
||||||
|
io.lsu_error_pkt_r.exc_type := ~misaligned_fault_r
|
||||||
|
io.lsu_error_pkt_r.mscause := Mux((io.lsu_double_ecc_error_r & !misaligned_fault_r & !access_fault_r).asBool,1.U(4.W), exc_mscause_r(3,0))
|
||||||
|
io.lsu_error_pkt_r.addr := io.lsu_addr_r(31,0)//lsu_addr_d->lsu_full_addr
|
||||||
|
io.lsu_fir_error := Mux(fir_nondccm_access_error_r.asBool,3.U(2.W), Mux(fir_dccm_access_error_r.asBool,2.U(2.W), Mux((io.lsu_pkt_r.fast_int & io.lsu_double_ecc_error_r).asBool,1.U(2.W),0.U(2.W))))
|
||||||
|
|
||||||
|
access_fault_r := withClock(io.lsu_c1_r_clk){RegNext(access_fault_m,0.U)}
|
||||||
|
exc_mscause_r := withClock(io.lsu_c1_r_clk){RegNext(exc_mscause_m,0.U)}
|
||||||
|
fir_dccm_access_error_r := withClock(io.lsu_c1_r_clk){RegNext(fir_dccm_access_error_m,0.U)}
|
||||||
|
fir_nondccm_access_error_r := withClock(io.lsu_c1_r_clk){RegNext(fir_nondccm_access_error_m,0.U)}
|
||||||
|
misaligned_fault_r := withClock(io.lsu_c1_r_clk){RegNext(misaligned_fault_m,0.U)}
|
||||||
|
}
|
||||||
|
|
||||||
|
else //L2U_Plus1_0
|
||||||
|
{
|
||||||
|
// Generate exception packet
|
||||||
|
lsu_error_pkt_m.exc_valid := (access_fault_m | misaligned_fault_m | io.lsu_double_ecc_error_m) & io.lsu_pkt_m.valid & !io.lsu_pkt_m.dma & !io.lsu_pkt_m.fast_int & !io.flush_m_up //TBD(lsu_pkt_r.fast_int)
|
||||||
|
lsu_error_pkt_m.single_ecc_error := io.lsu_single_ecc_error_m & !lsu_error_pkt_m.exc_valid & !io.lsu_pkt_m.dma
|
||||||
|
lsu_error_pkt_m.inst_type := io.lsu_pkt_m.store
|
||||||
|
lsu_error_pkt_m.exc_type := ~misaligned_fault_m
|
||||||
|
lsu_error_pkt_m.mscause := Mux(((io.lsu_double_ecc_error_m & !misaligned_fault_m & !access_fault_m)===1.U),1.U(4.W), exc_mscause_m(3,0))
|
||||||
|
lsu_error_pkt_m.addr := io.lsu_addr_m(31,0)//lsu_addr_d->lsu_full_addr
|
||||||
|
lsu_fir_error_m := Mux(fir_nondccm_access_error_m.asBool,3.U(2.W), Mux(fir_dccm_access_error_m.asBool,2.U(2.W), Mux((io.lsu_pkt_m.fast_int & io.lsu_double_ecc_error_m).asBool,1.U(2.W),0.U(2.W))))
|
||||||
|
io.lsu_error_pkt_r := withClock(io.lsu_c2_r_clk){RegNext(lsu_error_pkt_m,0.U.asTypeOf(lsu_error_pkt_m.cloneType))}
|
||||||
|
io.lsu_fir_error := withClock(io.lsu_c2_r_clk){RegNext(lsu_fir_error_m,0.U)}
|
||||||
|
}
|
||||||
|
dma_pkt_d.unsign := 0.U
|
||||||
|
dma_pkt_d.fast_int := 0.U
|
||||||
|
dma_pkt_d.valid := io.dma_dccm_req
|
||||||
|
dma_pkt_d.dma := 1.U
|
||||||
|
dma_pkt_d.store := io.dma_mem_write
|
||||||
|
dma_pkt_d.load := ~io.dma_mem_write
|
||||||
|
dma_pkt_d.by := (io.dma_mem_sz(2,0) === 0.U(3.W))
|
||||||
|
dma_pkt_d.half := (io.dma_mem_sz(2,0) === 1.U(3.W))
|
||||||
|
dma_pkt_d.word := (io.dma_mem_sz(2,0) === 2.U(3.W))
|
||||||
|
dma_pkt_d.dword := (io.dma_mem_sz(2,0) === 3.U(3.W))
|
||||||
|
dma_pkt_d.store_data_bypass_d := 0.U
|
||||||
|
dma_pkt_d.load_ldst_bypass_d := 0.U
|
||||||
|
dma_pkt_d.store_data_bypass_m := 0.U
|
||||||
|
|
||||||
|
val lsu_ld_datafn_r = WireInit(0.U(32.W))
|
||||||
|
val lsu_ld_datafn_corr_r = WireInit(0.U(32.W))
|
||||||
|
val lsu_ld_datafn_m = WireInit(0.U(32.W))
|
||||||
|
|
||||||
|
io.lsu_pkt_d := Mux(io.dec_lsu_valid_raw_d.asBool,io.lsu_p,dma_pkt_d)
|
||||||
|
lsu_pkt_m_in := io.lsu_pkt_d
|
||||||
|
lsu_pkt_r_in := io.lsu_pkt_m
|
||||||
|
|
||||||
|
io.lsu_pkt_d.valid := (io.lsu_p.valid & !(io.flush_m_up & !io.lsu_p.fast_int)) | io.dma_dccm_req
|
||||||
|
lsu_pkt_m_in.valid := io.lsu_pkt_d.valid & !(io.flush_m_up & !io.lsu_pkt_d.dma)
|
||||||
|
lsu_pkt_r_in.valid := io.lsu_pkt_m.valid & !(io.flush_m_up & !io.lsu_pkt_m.dma)
|
||||||
|
|
||||||
|
io.lsu_pkt_m := withClock(io.lsu_c1_m_clk){RegNext(lsu_pkt_m_in,0.U.asTypeOf(lsu_pkt_m_in.cloneType))}
|
||||||
|
io.lsu_pkt_r := withClock(io.lsu_c1_r_clk){RegNext(lsu_pkt_r_in,0.U.asTypeOf(lsu_pkt_r_in.cloneType))}
|
||||||
|
io.lsu_pkt_m.valid := withClock(io.lsu_c2_m_clk){RegNext(lsu_pkt_m_in.valid,0.U)}
|
||||||
|
io.lsu_pkt_r.valid := withClock(io.lsu_c2_r_clk){RegNext(lsu_pkt_r_in.valid,0.U)}
|
||||||
|
|
||||||
|
val dma_mem_wdata_shifted = io.dma_mem_wdata(63,0) >> Cat(io.dma_mem_addr(2,0), 0.U(3.W)) // Shift the dma data to lower bits to make it consistent to lsu stores
|
||||||
|
val store_data_d = Mux(io.dma_dccm_req.asBool,dma_mem_wdata_shifted(31,0),io.exu_lsu_rs2_d(31,0)) // Write to PIC still happens in r stage
|
||||||
|
val store_data_m_in = Mux(io.lsu_pkt_d.store_data_bypass_d.asBool,io.lsu_result_m(31,0),store_data_d(31,0))
|
||||||
|
|
||||||
|
val store_data_pre_m = withClock(io.lsu_store_c1_m_clk){RegNext(store_data_m_in,0.U)}
|
||||||
|
io.lsu_addr_m := withClock(io.lsu_c1_m_clk){RegNext(io.lsu_addr_d,0.U)}
|
||||||
|
io.lsu_addr_r := withClock(io.lsu_c1_r_clk){RegNext(io.lsu_addr_m,0.U)}
|
||||||
|
io.end_addr_m := withClock(io.lsu_c1_m_clk){RegNext(io.end_addr_d,0.U)}
|
||||||
|
io.end_addr_r := withClock(io.lsu_c1_r_clk){RegNext(io.end_addr_m,0.U)}
|
||||||
|
io.addr_in_dccm_m := withClock(io.lsu_c1_m_clk){RegNext(io.addr_in_dccm_d,0.U)}
|
||||||
|
io.addr_in_dccm_r := withClock(io.lsu_c1_r_clk){RegNext(io.addr_in_dccm_m,0.U)}
|
||||||
|
io.addr_in_pic_m := withClock(io.lsu_c1_m_clk){RegNext(io.addr_in_pic_d,0.U)}
|
||||||
|
io.addr_in_pic_r := withClock(io.lsu_c1_r_clk){RegNext(io.addr_in_pic_m,0.U)}
|
||||||
|
io.addr_external_m := withClock(io.lsu_c1_m_clk){RegNext(addr_external_d,0.U)}
|
||||||
|
val addr_external_r = withClock(io.lsu_c1_r_clk){RegNext(io.addr_external_m,0.U)}
|
||||||
|
val bus_read_data_r = withClock(io.lsu_c1_r_clk){RegNext(io.bus_read_data_m,0.U)}
|
||||||
|
// Fast interrupt address
|
||||||
|
io.lsu_fir_addr := io.lsu_ld_data_corr_r(31,1) //original (31,1) TBD
|
||||||
|
// absence load/store all 0's
|
||||||
|
io.lsu_addr_d := full_addr_d
|
||||||
|
// Interrupt as a flush source allows the WB to occur
|
||||||
|
io.lsu_commit_r := io.lsu_pkt_r.valid & (io.lsu_pkt_r.store | io.lsu_pkt_r.load) & !io.flush_r & !io.lsu_pkt_r.dma
|
||||||
|
io.store_data_m := (io.picm_mask_data_m(31,0) | Fill(32,!io.addr_in_pic_m)) & Mux(io.lsu_pkt_m.store_data_bypass_m.asBool,io.lsu_result_m,store_data_pre_m)
|
||||||
|
|
||||||
|
if (LOAD_TO_USE_PLUS1 == 1){
|
||||||
|
//bus_read_data_r coming from bus interface, lsu_ld_data_r -> coming from dccm_ctl
|
||||||
|
lsu_ld_datafn_r := Mux(addr_external_r.asBool, bus_read_data_r,io.lsu_ld_data_r)
|
||||||
|
lsu_ld_datafn_corr_r := Mux(addr_external_r.asBool, bus_read_data_r,io.lsu_ld_data_corr_r)
|
||||||
|
// this is really R stage but don't want to make all the changes to support M,R buses
|
||||||
|
io.lsu_result_m := ((Fill(32,io.lsu_pkt_r.unsign & io.lsu_pkt_r.by)) & Cat(0.U(24.W),lsu_ld_datafn_r(7,0))) |
|
||||||
|
((Fill(32,io.lsu_pkt_r.unsign & io.lsu_pkt_r.half)) & Cat(0.U(16.W),lsu_ld_datafn_r(15,0))) |
|
||||||
|
((Fill(32,!io.lsu_pkt_r.unsign & io.lsu_pkt_r.by)) & Cat((Fill(24, lsu_ld_datafn_r(7))) ,lsu_ld_datafn_r(7,0))) |
|
||||||
|
((Fill(32,!io.lsu_pkt_r.unsign & io.lsu_pkt_r.half)) & Cat((Fill(16,lsu_ld_datafn_r(15))) ,lsu_ld_datafn_r(15,0))) |
|
||||||
|
((Fill(32,io.lsu_pkt_r.word)) & lsu_ld_datafn_r(31,0))
|
||||||
|
// this signal is used for gpr update
|
||||||
|
io.lsu_result_corr_r := ((Fill(32,io.lsu_pkt_r.unsign & io.lsu_pkt_r.by)) & Cat(0.U(24.W),lsu_ld_datafn_corr_r(7,0))) |
|
||||||
|
((Fill(32,io.lsu_pkt_r.unsign & io.lsu_pkt_r.half)) & Cat(0.U(16.W),lsu_ld_datafn_corr_r(15,0))) |
|
||||||
|
((Fill(32,!io.lsu_pkt_r.unsign & io.lsu_pkt_r.by)) & Cat((Fill(24, lsu_ld_datafn_corr_r(7))) ,lsu_ld_datafn_corr_r(7,0))) |
|
||||||
|
((Fill(32,!io.lsu_pkt_r.unsign & io.lsu_pkt_r.half)) & Cat((Fill(16,lsu_ld_datafn_corr_r(15))) ,lsu_ld_datafn_corr_r(15,0))) |
|
||||||
|
((Fill(32,io.lsu_pkt_r.word)) & lsu_ld_datafn_corr_r(31,0))
|
||||||
|
}
|
||||||
|
|
||||||
|
else {
|
||||||
|
lsu_ld_datafn_m := Mux(io.addr_external_m.asBool, io.bus_read_data_m,io.lsu_ld_data_m)
|
||||||
|
lsu_ld_datafn_corr_r := Mux(addr_external_r===1.U, bus_read_data_r,io.lsu_ld_data_corr_r)
|
||||||
|
io.lsu_result_m := ((Fill(32,io.lsu_pkt_m.unsign & io.lsu_pkt_m.by)) & Cat(0.U(24.W),lsu_ld_datafn_m(7,0))) |
|
||||||
|
((Fill(32,io.lsu_pkt_m.unsign & io.lsu_pkt_m.half)) & Cat(0.U(16.W),lsu_ld_datafn_m(15,0))) |
|
||||||
|
((Fill(32,!io.lsu_pkt_m.unsign & io.lsu_pkt_m.by)) & Cat((Fill(24, lsu_ld_datafn_m(7))) ,lsu_ld_datafn_m(7,0))) |
|
||||||
|
((Fill(32,!io.lsu_pkt_m.unsign & io.lsu_pkt_m.half)) & Cat((Fill(16,lsu_ld_datafn_m(15))) ,lsu_ld_datafn_m(15,0))) |
|
||||||
|
((Fill(32,io.lsu_pkt_m.word)) & lsu_ld_datafn_m(31,0))
|
||||||
|
io.lsu_result_corr_r := ((Fill(32,io.lsu_pkt_r.unsign & io.lsu_pkt_r.by)) & Cat(0.U(24.W),lsu_ld_datafn_corr_r(7,0))) |
|
||||||
|
((Fill(32,io.lsu_pkt_r.unsign & io.lsu_pkt_r.half)) & Cat(0.U(16.W),lsu_ld_datafn_corr_r(15,0))) |
|
||||||
|
((Fill(32,!io.lsu_pkt_r.unsign & io.lsu_pkt_r.by)) & Cat((Fill(24, lsu_ld_datafn_corr_r(7))) ,lsu_ld_datafn_corr_r(7,0))) |
|
||||||
|
((Fill(32,!io.lsu_pkt_r.unsign & io.lsu_pkt_r.half)) & Cat((Fill(16,lsu_ld_datafn_corr_r(15))) ,lsu_ld_datafn_corr_r(15,0))) |
|
||||||
|
((Fill(32,io.lsu_pkt_r.word)) & lsu_ld_datafn_corr_r(31,0))
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
object lsu_lsc_ctl extends App{
|
||||||
|
println("Generate Verilog")
|
||||||
|
println((new chisel3.stage.ChiselStage).emitVerilog(new el2_lsu_lsc_ctl()))
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,280 @@
|
||||||
|
package lsu
|
||||||
|
import lib._
|
||||||
|
import chisel3._
|
||||||
|
import chisel3.experimental.chiselName
|
||||||
|
import chisel3.util._
|
||||||
|
import include._
|
||||||
|
|
||||||
|
@chiselName
|
||||||
|
class el2_lsu_stbuf extends Module with el2_lib with RequireAsyncReset {
|
||||||
|
val io = IO (new Bundle {
|
||||||
|
val lsu_c1_m_clk = Input(Clock())
|
||||||
|
val lsu_c1_r_clk = Input(Clock())
|
||||||
|
val lsu_stbuf_c1_clk = Input(Clock())
|
||||||
|
val lsu_free_c2_clk = Input(Clock())
|
||||||
|
val lsu_pkt_m = Input(new el2_lsu_pkt_t)
|
||||||
|
val lsu_pkt_r = Input(new el2_lsu_pkt_t)
|
||||||
|
val store_stbuf_reqvld_r = Input(Bool())
|
||||||
|
val lsu_commit_r = Input(Bool())
|
||||||
|
val dec_lsu_valid_raw_d = Input(Bool())
|
||||||
|
val store_data_hi_r = Input(UInt(DCCM_DATA_WIDTH.W))
|
||||||
|
val store_data_lo_r = Input(UInt(DCCM_DATA_WIDTH.W))
|
||||||
|
val store_datafn_hi_r = Input(UInt(DCCM_DATA_WIDTH.W))
|
||||||
|
val store_datafn_lo_r = Input(UInt(DCCM_DATA_WIDTH.W))
|
||||||
|
val lsu_stbuf_commit_any = Input(Bool())
|
||||||
|
val lsu_addr_d = Input(UInt(LSU_SB_BITS.W))
|
||||||
|
val lsu_addr_m = Input(UInt(32.W))
|
||||||
|
val lsu_addr_r = Input(UInt(32.W))
|
||||||
|
val end_addr_d = Input(UInt(LSU_SB_BITS.W))
|
||||||
|
val end_addr_m = Input(UInt(32.W))
|
||||||
|
val end_addr_r = Input(UInt(32.W))
|
||||||
|
|
||||||
|
val addr_in_dccm_m = Input(Bool())
|
||||||
|
val addr_in_dccm_r = Input(Bool())
|
||||||
|
val lsu_cmpen_m = Input(Bool())
|
||||||
|
val scan_mode = Input(Bool())
|
||||||
|
|
||||||
|
//Outputs
|
||||||
|
val stbuf_reqvld_any = Output(Bool())
|
||||||
|
val stbuf_reqvld_flushed_any = Output(Bool())
|
||||||
|
val stbuf_addr_any = Output(UInt(LSU_SB_BITS.W))
|
||||||
|
val stbuf_data_any = Output(UInt(DCCM_DATA_WIDTH.W))
|
||||||
|
val lsu_stbuf_full_any = Output(Bool())
|
||||||
|
val lsu_stbuf_empty_any = Output(Bool())
|
||||||
|
val ldst_stbuf_reqvld_r = Output(Bool())
|
||||||
|
val stbuf_fwddata_hi_m = Output(UInt(DCCM_DATA_WIDTH.W))
|
||||||
|
val stbuf_fwddata_lo_m = Output(UInt(DCCM_DATA_WIDTH.W))
|
||||||
|
val stbuf_fwdbyteen_hi_m = Output(UInt(DCCM_BYTE_WIDTH.W))
|
||||||
|
val stbuf_fwdbyteen_lo_m = Output(UInt(DCCM_BYTE_WIDTH.W))
|
||||||
|
// val testout = Output(Vec(LSU_STBUF_DEPTH, UInt(8.W)))
|
||||||
|
})
|
||||||
|
|
||||||
|
io.stbuf_reqvld_any := 0.U
|
||||||
|
io.stbuf_reqvld_flushed_any := 0.U
|
||||||
|
io.stbuf_addr_any := 0.U
|
||||||
|
io.stbuf_data_any := 0.U
|
||||||
|
io.lsu_stbuf_full_any := 0.U
|
||||||
|
io.lsu_stbuf_empty_any := 0.U
|
||||||
|
io.ldst_stbuf_reqvld_r := 0.U
|
||||||
|
io.stbuf_fwddata_hi_m := 0.U
|
||||||
|
io.stbuf_fwddata_lo_m := 0.U
|
||||||
|
io.stbuf_fwdbyteen_hi_m := 0.U
|
||||||
|
io.stbuf_fwdbyteen_lo_m := 0.U
|
||||||
|
|
||||||
|
|
||||||
|
val stbuf_vld = WireInit(UInt(LSU_STBUF_DEPTH.W), init = 0.U)
|
||||||
|
val stbuf_wr_en = WireInit(UInt(LSU_STBUF_DEPTH.W), init = 0.U)
|
||||||
|
val stbuf_dma_kill_en = WireInit(UInt(LSU_STBUF_DEPTH.W), init = 0.U)
|
||||||
|
val stbuf_dma_kill = WireInit(UInt(LSU_STBUF_DEPTH.W), init = 0.U)
|
||||||
|
val stbuf_reset = WireInit(UInt(LSU_STBUF_DEPTH.W), init = 0.U)
|
||||||
|
val store_byteen_ext_r = WireInit(UInt(8.W), init= 0.U)
|
||||||
|
val stbuf_addr = Wire(Vec(LSU_STBUF_DEPTH,UInt(LSU_SB_BITS.W)))
|
||||||
|
stbuf_addr := (0 until LSU_STBUF_DEPTH).map(i => 0.U)
|
||||||
|
val stbuf_byteen = Wire(Vec(LSU_STBUF_DEPTH,UInt(DCCM_BYTE_WIDTH.W)))
|
||||||
|
stbuf_byteen := (0 until LSU_STBUF_DEPTH).map(i => 0.U)
|
||||||
|
val stbuf_data = Wire(Vec(LSU_STBUF_DEPTH,UInt(DCCM_DATA_WIDTH.W)))
|
||||||
|
stbuf_data := (0 until LSU_STBUF_DEPTH).map(i => 0.U)
|
||||||
|
val stbuf_addrin = Wire(Vec(LSU_STBUF_DEPTH,UInt(LSU_SB_BITS.W)))
|
||||||
|
stbuf_addrin := (0 until LSU_STBUF_DEPTH).map(i => 0.U)
|
||||||
|
val stbuf_datain = Wire(Vec(LSU_STBUF_DEPTH,UInt(DCCM_DATA_WIDTH.W)))
|
||||||
|
stbuf_datain := (0 until LSU_STBUF_DEPTH).map(i => 0.U)
|
||||||
|
val stbuf_byteenin = Wire(Vec(LSU_STBUF_DEPTH,UInt(DCCM_BYTE_WIDTH.W)))
|
||||||
|
stbuf_byteenin := (0 until LSU_STBUF_DEPTH).map(i => 0.U)
|
||||||
|
val WrPtr = WireInit(UInt(log2Ceil(LSU_STBUF_DEPTH).W),init = 0.U)
|
||||||
|
val RdPtr = WireInit(UInt(log2Ceil(LSU_STBUF_DEPTH).W),init = 0.U)
|
||||||
|
val ldst_dual_m = WireInit(Bool(),init = 0.U)
|
||||||
|
val ldst_dual_r = WireInit(Bool(),init = 0.U)
|
||||||
|
val cmpaddr_hi_m = WireInit(0.U(16.W))
|
||||||
|
val stbuf_specvld_m = WireInit(0.U(2.W))
|
||||||
|
val stbuf_specvld_r = WireInit(0.U(2.W))
|
||||||
|
val cmpaddr_lo_m = WireInit(0.U(16.W))
|
||||||
|
val stbuf_fwdata_hi_pre_m = WireInit(UInt(DCCM_DATA_WIDTH.W),init = 0.U)
|
||||||
|
val stbuf_fwdata_lo_pre_m = WireInit(UInt(DCCM_DATA_WIDTH.W),init = 0.U)
|
||||||
|
val ld_byte_rhit_lo_lo = WireInit(UInt(DCCM_BYTE_WIDTH.W),init = 0.U)
|
||||||
|
val ld_byte_rhit_hi_lo = WireInit(UInt(DCCM_BYTE_WIDTH.W),init = 0.U)
|
||||||
|
val ld_byte_rhit_lo_hi = WireInit(UInt(DCCM_BYTE_WIDTH.W),init = 0.U)
|
||||||
|
val ld_byte_rhit_hi_hi = WireInit(UInt(DCCM_BYTE_WIDTH.W),init = 0.U)
|
||||||
|
val ld_byte_hit_lo = WireInit(UInt(DCCM_BYTE_WIDTH.W),init = 0.U)
|
||||||
|
val ld_byte_rhit_lo = WireInit(UInt(DCCM_BYTE_WIDTH.W),init = 0.U)
|
||||||
|
val ld_byte_hit_hi = WireInit(UInt(DCCM_BYTE_WIDTH.W),init = 0.U)
|
||||||
|
val ld_byte_rhit_hi = WireInit(UInt(DCCM_BYTE_WIDTH.W),init = 0.U)
|
||||||
|
val ldst_byteen_ext_r = WireInit(UInt(8.W),init = 0.U)
|
||||||
|
val ld_fwddata_rpipe_lo = WireInit(UInt(32.W),init = 0.U)
|
||||||
|
val ld_fwddata_rpipe_hi = WireInit(UInt(32.W),init = 0.U)
|
||||||
|
|
||||||
|
//
|
||||||
|
val datain1 = Wire(Vec(LSU_STBUF_DEPTH,UInt(8.W)))
|
||||||
|
val datain2 = Wire(Vec(LSU_STBUF_DEPTH,UInt(8.W)))
|
||||||
|
val datain3 = Wire(Vec(LSU_STBUF_DEPTH,UInt(8.W)))
|
||||||
|
val datain4 = Wire(Vec(LSU_STBUF_DEPTH,UInt(8.W)))
|
||||||
|
|
||||||
|
//////////////////////////////////////Code Start here///////////////////////////////
|
||||||
|
val ldst_byteen_r = Mux1H(Seq(
|
||||||
|
io.lsu_pkt_r.by.asBool -> "b00000001".U,
|
||||||
|
io.lsu_pkt_r.half.asBool ->"b00000011".U,
|
||||||
|
io.lsu_pkt_r.word.asBool -> "b00001111".U,
|
||||||
|
io.lsu_pkt_r.dword.asBool -> "b11111111".U
|
||||||
|
))
|
||||||
|
val ldst_dual_d = io.lsu_addr_d (2) =/= io.end_addr_d(2)
|
||||||
|
val dual_stbuf_write_r = ldst_dual_r & io.store_stbuf_reqvld_r
|
||||||
|
|
||||||
|
store_byteen_ext_r := ldst_byteen_r << io.lsu_addr_r(1,0)
|
||||||
|
val store_byteen_hi_r = store_byteen_ext_r (7,4) & Fill(4, io.lsu_pkt_r.store)
|
||||||
|
val store_byteen_lo_r = store_byteen_ext_r (3,0) & Fill(4, io.lsu_pkt_r.store)
|
||||||
|
|
||||||
|
val RdPtrPlus1 = RdPtr + "b01".U
|
||||||
|
val WrPtrPlus1 = WrPtr + "b01".U
|
||||||
|
val WrPtrPlus2 = WrPtr + "b10".U
|
||||||
|
|
||||||
|
io.ldst_stbuf_reqvld_r := io.lsu_commit_r & io.store_stbuf_reqvld_r
|
||||||
|
|
||||||
|
val store_matchvec_lo_r = (0 until LSU_STBUF_DEPTH).map(i=> (stbuf_addr(i)(LSU_SB_BITS-1,log2Ceil(DCCM_BYTE_WIDTH)) === io.lsu_addr_r(LSU_SB_BITS-1,log2Ceil(DCCM_BYTE_WIDTH)) & stbuf_vld(i) & !stbuf_dma_kill(i) & !stbuf_reset(i)).asUInt).reverse.reduce(Cat(_,_))
|
||||||
|
val store_matchvec_hi_r = (0 until LSU_STBUF_DEPTH).map(i=> (stbuf_addr(i)(LSU_SB_BITS-1,log2Ceil(DCCM_BYTE_WIDTH)) === io.end_addr_r(LSU_SB_BITS-1,log2Ceil(DCCM_BYTE_WIDTH)) & stbuf_vld(i) & !stbuf_dma_kill(i) & dual_stbuf_write_r & !stbuf_reset(i)).asUInt).reverse.reduce(Cat(_,_))
|
||||||
|
|
||||||
|
val store_coalesce_lo_r = store_matchvec_lo_r.orR
|
||||||
|
val store_coalesce_hi_r = store_matchvec_hi_r.orR
|
||||||
|
|
||||||
|
stbuf_wr_en := (0 until LSU_STBUF_DEPTH).map(i=> (io.ldst_stbuf_reqvld_r & (
|
||||||
|
((i.asUInt === WrPtr) & !store_coalesce_lo_r) |
|
||||||
|
((i.asUInt === WrPtr) & dual_stbuf_write_r & !store_coalesce_hi_r) |
|
||||||
|
((i.asUInt === WrPtrPlus1) & dual_stbuf_write_r & !(store_coalesce_lo_r | store_coalesce_hi_r)) |
|
||||||
|
store_matchvec_lo_r(i) | store_matchvec_hi_r(i))).asUInt).reverse.reduce(Cat(_,_))
|
||||||
|
stbuf_reset := (0 until LSU_STBUF_DEPTH).map(i=> ((io.lsu_stbuf_commit_any | io.stbuf_reqvld_flushed_any) & (i.asUInt === RdPtr).asBool).asUInt).reverse.reduce(Cat(_,_))
|
||||||
|
val sel_lo = (0 until LSU_STBUF_DEPTH).map(i=> (((!ldst_dual_r | io.store_stbuf_reqvld_r) & (i.asUInt === WrPtr).asBool & !store_coalesce_lo_r) | store_matchvec_lo_r(i)).asUInt).reverse.reduce(Cat(_,_))
|
||||||
|
|
||||||
|
stbuf_addrin := (0 until LSU_STBUF_DEPTH).map(i=> Mux(sel_lo(i), io.lsu_addr_r(LSU_SB_BITS-1,0), io.end_addr_r(LSU_SB_BITS-1,0)))
|
||||||
|
stbuf_byteenin := (0 until LSU_STBUF_DEPTH).map(i=> Mux(sel_lo(i), stbuf_byteen(i) | store_byteen_lo_r, stbuf_byteen(i) | store_byteen_hi_r).asUInt)
|
||||||
|
|
||||||
|
datain1 := (0 until LSU_STBUF_DEPTH).map(i=> Mux(sel_lo(i), Mux(!stbuf_byteen(i)(0) | store_byteen_lo_r(0), io.store_datafn_lo_r(7, 0), stbuf_data(i)(7, 0)),
|
||||||
|
Mux(!stbuf_byteen(i)(0) | store_byteen_hi_r(0), io.store_datafn_hi_r(7, 0), stbuf_data(i)(7, 0))).asUInt)
|
||||||
|
|
||||||
|
datain2 := (0 until LSU_STBUF_DEPTH).map(i=> Mux(sel_lo(i), Mux(!stbuf_byteen(i)(1) | store_byteen_lo_r(1), io.store_datafn_lo_r(15, 8), stbuf_data(i)(15, 8)),
|
||||||
|
Mux(!stbuf_byteen(i)(1) | store_byteen_hi_r(1), io.store_datafn_hi_r(15, 8), stbuf_data(i)(15, 8))).asUInt)
|
||||||
|
|
||||||
|
datain3 := (0 until LSU_STBUF_DEPTH).map(i=> Mux(sel_lo(i), Mux(!stbuf_byteen(i)(2) | store_byteen_lo_r(2), io.store_datafn_lo_r(23, 16), stbuf_data(i)(23, 16)),
|
||||||
|
Mux(!stbuf_byteen(i)(2) | store_byteen_hi_r(2), io.store_datafn_hi_r(23, 16), stbuf_data(i)(23, 16))).asUInt)
|
||||||
|
|
||||||
|
datain4 := (0 until LSU_STBUF_DEPTH).map(i=> Mux(sel_lo(i), Mux(!stbuf_byteen(i)(3) | store_byteen_lo_r(3), io.store_datafn_lo_r(31, 24), stbuf_data(i)(31, 24)),
|
||||||
|
Mux(!stbuf_byteen(i)(3) | store_byteen_hi_r(3), io.store_datafn_hi_r(31, 24), stbuf_data(i)(31, 24))).asUInt)
|
||||||
|
|
||||||
|
stbuf_datain := (0 until LSU_STBUF_DEPTH).map(i=>Cat(datain4(i), datain3(i), datain2(i), datain1(i)))
|
||||||
|
// io.testout := datain3
|
||||||
|
|
||||||
|
// for (i<- 0 until LSU_STBUF_DEPTH) {
|
||||||
|
stbuf_vld := (0 until LSU_STBUF_DEPTH).map(i=> withClock(io.lsu_free_c2_clk){ RegNext(Mux(stbuf_wr_en(i).asBool(),1.U ,stbuf_vld(i)) & !stbuf_reset(i), 0.U)}).reverse.reduce(Cat(_,_))
|
||||||
|
// stbuf_addr := (0 until LSU_STBUF_DEPTH).map(i=> RegEnable(stbuf_addrin(i), 0.U, stbuf_wr_en(i).asBool())).reverse.reduce(Cat(_,_))
|
||||||
|
stbuf_dma_kill := (0 until LSU_STBUF_DEPTH).map(i=> withClock(io.lsu_free_c2_clk){RegNext(Mux(stbuf_dma_kill_en(i).asBool,1.U ,stbuf_dma_kill(i)) & !stbuf_reset(i), 0.U)}).reverse.reduce(Cat(_,_))
|
||||||
|
stbuf_byteen := (0 until LSU_STBUF_DEPTH).map(i=> withClock(io.lsu_stbuf_c1_clk){ RegNext(Mux(stbuf_wr_en(i).asBool(),stbuf_byteenin(i) , stbuf_byteen(i)) & Fill(stbuf_byteenin(i).getWidth , !stbuf_reset(i)), 0.U)})
|
||||||
|
//stbuf_data := (0 until LSU_STBUF_DEPTH).map(i=> RegEnable(stbuf_datain(i), 0.U, stbuf_wr_en(i).asBool())).reverse.reduce(Cat(_,_))
|
||||||
|
for (i<- 0 until LSU_STBUF_DEPTH) {
|
||||||
|
// withClock(io.lsu_free_c2_clk){ stbuf_dma_kill(i) := RegEnable(1.U & !stbuf_reset(i), 0.U, stbuf_dma_kill_en(i).asBool)}
|
||||||
|
|
||||||
|
stbuf_addr(i) := rvdffe(stbuf_addrin(i),stbuf_wr_en(i).asBool(),clock,io.scan_mode)
|
||||||
|
// withClock(io.lsu_stbuf_c1_clk){ stbuf_byteen(i) := RegNext( stbuf_byteenin(i) & Fill(stbuf_byteenin(i).getWidth, !stbuf_reset(i)), 0.U, stbuf_wr_en(i).asBool())}
|
||||||
|
stbuf_data(i) := rvdffe(stbuf_datain(i),stbuf_wr_en(i).asBool(),clock,io.scan_mode)
|
||||||
|
}
|
||||||
|
withClock(io.lsu_c1_m_clk){ldst_dual_m := RegNext(ldst_dual_d,0.U)}
|
||||||
|
withClock(io.lsu_c1_r_clk){ldst_dual_r := RegNext(ldst_dual_m,0.U)}
|
||||||
|
|
||||||
|
// Store Buffer drain logic
|
||||||
|
io.stbuf_reqvld_flushed_any := stbuf_vld(RdPtr) & stbuf_dma_kill(RdPtr)
|
||||||
|
io.stbuf_reqvld_any := stbuf_vld(RdPtr) & !stbuf_dma_kill(RdPtr) & !(stbuf_dma_kill_en.orR)
|
||||||
|
io.stbuf_addr_any := stbuf_addr(RdPtr)
|
||||||
|
io.stbuf_data_any := stbuf_data(RdPtr)
|
||||||
|
|
||||||
|
val WrPtrEn = ((io.ldst_stbuf_reqvld_r & !dual_stbuf_write_r & !(store_coalesce_hi_r | store_coalesce_lo_r)) |
|
||||||
|
(io.ldst_stbuf_reqvld_r & dual_stbuf_write_r & !(store_coalesce_hi_r & store_coalesce_lo_r))).asBool
|
||||||
|
val NxtWrPtr = Mux((io.ldst_stbuf_reqvld_r & dual_stbuf_write_r & !(store_coalesce_hi_r | store_coalesce_lo_r)).asBool, WrPtrPlus2, WrPtrPlus1)
|
||||||
|
val RdPtrEn = io.lsu_stbuf_commit_any | io.stbuf_reqvld_flushed_any
|
||||||
|
val NxtRdPtr = RdPtrPlus1
|
||||||
|
|
||||||
|
withClock(io.lsu_stbuf_c1_clk){ WrPtr := RegEnable(NxtWrPtr, 0.U, WrPtrEn)}
|
||||||
|
withClock(io.lsu_stbuf_c1_clk){ RdPtr := RegEnable(NxtRdPtr, 0.U, RdPtrEn)}
|
||||||
|
|
||||||
|
val stbuf_numvld_any = VecInit.tabulate(LSU_STBUF_DEPTH)(i=>Cat(0.U(3.W), stbuf_vld(i))).reduce (_+_)
|
||||||
|
val isdccmst_m = io.lsu_pkt_m.valid & io.lsu_pkt_m.store & io.addr_in_dccm_m & !io.lsu_pkt_m.dma
|
||||||
|
val isdccmst_r = io.lsu_pkt_r.valid & io.lsu_pkt_r.store & io.addr_in_dccm_r & !io.lsu_pkt_r.dma
|
||||||
|
|
||||||
|
stbuf_specvld_m := Cat(0.U(1.W),isdccmst_m) << (isdccmst_m & ldst_dual_m)
|
||||||
|
stbuf_specvld_r := Cat(0.U(1.W),isdccmst_r) << (isdccmst_r & ldst_dual_r)
|
||||||
|
val stbuf_specvld_any = stbuf_numvld_any + Cat(0.U(2.W), stbuf_specvld_m) + Cat(0.U(2.W), stbuf_specvld_r)
|
||||||
|
|
||||||
|
io.lsu_stbuf_full_any := Mux((!ldst_dual_d & io.dec_lsu_valid_raw_d).asBool,(stbuf_specvld_any >= LSU_STBUF_DEPTH.U),(stbuf_specvld_any >= (LSU_STBUF_DEPTH-1).U))
|
||||||
|
io.lsu_stbuf_empty_any := stbuf_numvld_any === 0.U
|
||||||
|
|
||||||
|
val cmpen_hi_m = io.lsu_cmpen_m & ldst_dual_m
|
||||||
|
cmpaddr_hi_m := io.end_addr_m(LSU_SB_BITS-1,log2Ceil(DCCM_BYTE_WIDTH))
|
||||||
|
|
||||||
|
val cmpen_lo_m = io.lsu_cmpen_m
|
||||||
|
cmpaddr_lo_m := io.lsu_addr_m(LSU_SB_BITS-1,log2Ceil(DCCM_BYTE_WIDTH))
|
||||||
|
|
||||||
|
|
||||||
|
val stbuf_match_hi = (0 until LSU_STBUF_DEPTH).map(i=> ((stbuf_addr(i)(LSU_SB_BITS-1,log2Ceil(DCCM_BYTE_WIDTH)) === cmpaddr_hi_m(13,0)) & stbuf_vld(i) & !stbuf_dma_kill(i) & io.addr_in_dccm_m).asUInt).reverse.reduce(Cat(_,_))
|
||||||
|
val stbuf_match_lo = (0 until LSU_STBUF_DEPTH).map(i=> ((stbuf_addr(i)(LSU_SB_BITS-1,log2Ceil(DCCM_BYTE_WIDTH)) === cmpaddr_lo_m(13,0)) & stbuf_vld(i) & !stbuf_dma_kill(i) & io.addr_in_dccm_m).asUInt).reverse.reduce(Cat(_,_))
|
||||||
|
stbuf_dma_kill_en := (0 until LSU_STBUF_DEPTH).map(i=> ((stbuf_match_hi(i) | stbuf_match_lo(i)) & io.lsu_pkt_m.valid & io.lsu_pkt_m.dma & io.lsu_pkt_m.store).asUInt).reverse.reduce(Cat(_,_))
|
||||||
|
|
||||||
|
|
||||||
|
val stbuf_fwdbyteenvec_hi = (0 until LSU_STBUF_DEPTH).map(i=>(0 until DCCM_BYTE_WIDTH).map(j=> stbuf_match_hi(i) & stbuf_byteen(i)(j) & stbuf_vld(i).asUInt()))
|
||||||
|
val stbuf_fwdbyteenvec_lo = (0 until LSU_STBUF_DEPTH).map(i=>(0 until DCCM_BYTE_WIDTH).map(j=> stbuf_match_lo(i) & stbuf_byteen(i)(j) & stbuf_vld(i).asUInt()))
|
||||||
|
val stbuf_fwdbyteen_hi_pre_m = (0 until LSU_STBUF_DEPTH).map(j=>(0 until DCCM_BYTE_WIDTH).map(i=> stbuf_fwdbyteenvec_hi(i)(j).asUInt()).reduce(_|_))
|
||||||
|
val stbuf_fwdbyteen_lo_pre_m = (0 until LSU_STBUF_DEPTH).map(j=>(0 until DCCM_BYTE_WIDTH).map(i=> stbuf_fwdbyteenvec_lo(i)(j).asUInt()).reduce(_|_))
|
||||||
|
|
||||||
|
val stbuf_fwddata_hi_pre_m = VecInit.tabulate(LSU_STBUF_DEPTH)(i=> Fill(32,stbuf_match_hi(i)) & stbuf_data(i)).reverse.reduce(_|_)
|
||||||
|
val stbuf_fwddata_lo_pre_m = VecInit.tabulate(LSU_STBUF_DEPTH)(i=> Fill(32,stbuf_match_lo(i)) & stbuf_data(i)).reverse.reduce(_|_)
|
||||||
|
|
||||||
|
|
||||||
|
ldst_byteen_ext_r := ldst_byteen_r << io.lsu_addr_r(1,0)
|
||||||
|
val ldst_byteen_hi_r = ldst_byteen_ext_r(7,4)
|
||||||
|
val ldst_byteen_lo_r = ldst_byteen_ext_r(3,0)
|
||||||
|
|
||||||
|
val ld_addr_rhit_lo_lo = (io.lsu_addr_m(31,2) === io.lsu_addr_r(31,2)) & io.lsu_pkt_r.valid & io.lsu_pkt_r.store & !io.lsu_pkt_r.dma
|
||||||
|
val ld_addr_rhit_lo_hi = (io.end_addr_m(31,2) === io.lsu_addr_r(31,2)) & io.lsu_pkt_r.valid & io.lsu_pkt_r.store & !io.lsu_pkt_r.dma
|
||||||
|
val ld_addr_rhit_hi_lo = (io.lsu_addr_m(31,2) === io.end_addr_r(31,2)) & io.lsu_pkt_r.valid & io.lsu_pkt_r.store & !io.lsu_pkt_r.dma & dual_stbuf_write_r
|
||||||
|
val ld_addr_rhit_hi_hi = (io.end_addr_m(31,2) === io.end_addr_r(31,2)) & io.lsu_pkt_r.valid & io.lsu_pkt_r.store & !io.lsu_pkt_r.dma & dual_stbuf_write_r
|
||||||
|
|
||||||
|
ld_byte_rhit_lo_lo := (0 until DCCM_BYTE_WIDTH).map(i=> (ld_addr_rhit_lo_lo & ldst_byteen_lo_r(i)).asUInt).reverse.reduce(Cat(_,_))
|
||||||
|
ld_byte_rhit_lo_hi := (0 until DCCM_BYTE_WIDTH).map(i=> (ld_addr_rhit_lo_hi & ldst_byteen_lo_r(i)).asUInt).reverse.reduce(Cat(_,_))
|
||||||
|
ld_byte_rhit_hi_lo := (0 until DCCM_BYTE_WIDTH).map(i=> (ld_addr_rhit_hi_lo & ldst_byteen_hi_r(i)).asUInt).reverse.reduce(Cat(_,_))
|
||||||
|
ld_byte_rhit_hi_hi := (0 until DCCM_BYTE_WIDTH).map(i=> (ld_addr_rhit_hi_hi & ldst_byteen_hi_r(i)).asUInt).reverse.reduce(Cat(_,_))
|
||||||
|
|
||||||
|
ld_byte_rhit_lo := (0 until DCCM_BYTE_WIDTH).map(i=> (ld_byte_rhit_lo_lo(i) | ld_byte_rhit_hi_lo(i)).asUInt).reverse.reduce(Cat(_,_))
|
||||||
|
ld_byte_rhit_hi := (0 until DCCM_BYTE_WIDTH).map(i=> (ld_byte_rhit_lo_hi(i) | ld_byte_rhit_hi_hi(i)).asUInt).reverse.reduce(Cat(_,_))
|
||||||
|
|
||||||
|
val fwdpipe1_lo = (Fill(8, ld_byte_rhit_lo_lo(0)) & io.store_data_lo_r(7,0)) | (Fill(8, ld_byte_rhit_hi_lo(0)) & io.store_data_hi_r(7,0))
|
||||||
|
val fwdpipe2_lo = (Fill(8, ld_byte_rhit_lo_lo(1)) & io.store_data_lo_r(15,8)) | (Fill(8, ld_byte_rhit_hi_lo(1)) & io.store_data_hi_r(15,8))
|
||||||
|
val fwdpipe3_lo = (Fill(8, ld_byte_rhit_lo_lo(2)) & io.store_data_lo_r(23,16)) | (Fill(8, ld_byte_rhit_hi_lo(2)) & io.store_data_hi_r(23,16))
|
||||||
|
val fwdpipe4_lo = (Fill(8, ld_byte_rhit_lo_lo(3)) & io.store_data_lo_r(31,24)) | (Fill(8, ld_byte_rhit_hi_lo(3)) & io.store_data_hi_r(31,24))
|
||||||
|
ld_fwddata_rpipe_lo := Cat(fwdpipe4_lo,fwdpipe3_lo,fwdpipe2_lo,fwdpipe1_lo)
|
||||||
|
|
||||||
|
val fwdpipe1_hi = (Fill(8, ld_byte_rhit_lo_hi(0)) & io.store_data_lo_r(7,0)) | (Fill(8, ld_byte_rhit_hi_hi(0)) & io.store_data_hi_r(7,0))
|
||||||
|
val fwdpipe2_hi = (Fill(8, ld_byte_rhit_lo_hi(1)) & io.store_data_lo_r(15,8)) | (Fill(8, ld_byte_rhit_hi_hi(1)) & io.store_data_hi_r(15,8))
|
||||||
|
val fwdpipe3_hi = (Fill(8, ld_byte_rhit_lo_hi(2)) & io.store_data_lo_r(23,16)) | (Fill(8, ld_byte_rhit_hi_hi(2)) & io.store_data_hi_r(23,16))
|
||||||
|
val fwdpipe4_hi = (Fill(8, ld_byte_rhit_lo_hi(3)) & io.store_data_lo_r(31,24)) | (Fill(8, ld_byte_rhit_hi_hi(3)) & io.store_data_hi_r(31,24))
|
||||||
|
ld_fwddata_rpipe_hi := Cat(fwdpipe4_hi,fwdpipe3_hi,fwdpipe2_hi,fwdpipe1_hi)
|
||||||
|
|
||||||
|
ld_byte_hit_lo := (0 until DCCM_BYTE_WIDTH).map(i=> (ld_byte_rhit_lo_lo(i) | ld_byte_rhit_hi_lo(i)).asUInt).reverse.reduce(Cat(_,_))
|
||||||
|
ld_byte_hit_hi := (0 until DCCM_BYTE_WIDTH).map(i=> (ld_byte_rhit_lo_hi(i) | ld_byte_rhit_hi_hi(i)).asUInt).reverse.reduce(Cat(_,_))
|
||||||
|
|
||||||
|
io.stbuf_fwdbyteen_hi_m := (0 until DCCM_BYTE_WIDTH).map(i=> (ld_byte_hit_hi(i) | stbuf_fwdbyteen_hi_pre_m(i)).asUInt).reverse.reduce(Cat(_,_))
|
||||||
|
io.stbuf_fwdbyteen_lo_m := (0 until DCCM_BYTE_WIDTH).map(i=> (ld_byte_hit_lo(i) | stbuf_fwdbyteen_lo_pre_m(i)).asUInt).reverse.reduce(Cat(_,_))
|
||||||
|
|
||||||
|
// Pipe vs Store Queue priority
|
||||||
|
val stbuf_fwdpipe1_lo = Mux(ld_byte_rhit_lo(0),ld_fwddata_rpipe_lo(7,0),stbuf_fwddata_lo_pre_m(7,0))
|
||||||
|
val stbuf_fwdpipe2_lo = Mux(ld_byte_rhit_lo(1),ld_fwddata_rpipe_lo(15,8),stbuf_fwddata_lo_pre_m(15,8))
|
||||||
|
val stbuf_fwdpipe3_lo = Mux(ld_byte_rhit_lo(2),ld_fwddata_rpipe_lo(23,16),stbuf_fwddata_lo_pre_m(23,16))
|
||||||
|
val stbuf_fwdpipe4_lo = Mux(ld_byte_rhit_lo(3),ld_fwddata_rpipe_lo(31,24),stbuf_fwddata_lo_pre_m(31,24))
|
||||||
|
io.stbuf_fwddata_lo_m := Cat(stbuf_fwdpipe4_lo,stbuf_fwdpipe3_lo,stbuf_fwdpipe2_lo,stbuf_fwdpipe1_lo)
|
||||||
|
// Pipe vs Store Queue priority
|
||||||
|
val stbuf_fwdpipe1_hi = Mux(ld_byte_rhit_hi(0),ld_fwddata_rpipe_hi(7,0),stbuf_fwddata_hi_pre_m(7,0))
|
||||||
|
val stbuf_fwdpipe2_hi = Mux(ld_byte_rhit_hi(1),ld_fwddata_rpipe_hi(15,8),stbuf_fwddata_hi_pre_m(15,8))
|
||||||
|
val stbuf_fwdpipe3_hi = Mux(ld_byte_rhit_hi(2),ld_fwddata_rpipe_hi(23,16),stbuf_fwddata_hi_pre_m(23,16))
|
||||||
|
val stbuf_fwdpipe4_hi = Mux(ld_byte_rhit_hi(3),ld_fwddata_rpipe_hi(31,24),stbuf_fwddata_hi_pre_m(31,24))
|
||||||
|
io.stbuf_fwddata_hi_m := Cat(stbuf_fwdpipe4_hi,stbuf_fwdpipe3_hi,stbuf_fwdpipe2_hi,stbuf_fwdpipe1_hi)
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
}
|
||||||
|
object stbmain extends App{
|
||||||
|
println("Generate Verilog")
|
||||||
|
println((new chisel3.stage.ChiselStage).emitVerilog(new el2_lsu_stbuf()))
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,27 @@
|
||||||
|
package lsu
|
||||||
|
import chisel3._
|
||||||
|
import lib._
|
||||||
|
import chisel3.util._
|
||||||
|
import include._
|
||||||
|
class el2_lsu_trigger extends Module with RequireAsyncReset with el2_lib {
|
||||||
|
val io = IO(new Bundle{
|
||||||
|
val trigger_pkt_any = Input(Vec (4,(new el2_trigger_pkt_t)))
|
||||||
|
val lsu_pkt_m = Input(new el2_lsu_pkt_t)
|
||||||
|
val lsu_addr_m = Input(UInt(32.W))
|
||||||
|
val store_data_m = Input(UInt(32.W))
|
||||||
|
val lsu_trigger_match_m = Output(UInt(4.W))
|
||||||
|
|
||||||
|
})
|
||||||
|
|
||||||
|
val store_data_trigger_m= Cat((Fill(16,io.lsu_pkt_m.word) & io.store_data_m(31,16)),(Fill(8,(io.lsu_pkt_m.half | io.lsu_pkt_m.word)) & io.store_data_m(15,8)), io.store_data_m(7,0))
|
||||||
|
val lsu_match_data = (0 until 4).map(i=>Mux1H(Seq(!io.trigger_pkt_any(i).select.asBool->io.lsu_addr_m, (io.trigger_pkt_any(i).select & io.trigger_pkt_any(i).store).asBool->store_data_trigger_m)))
|
||||||
|
io.lsu_trigger_match_m := (0 until 4).map(i =>io.lsu_pkt_m.valid & !io.lsu_pkt_m.dma & ((io.trigger_pkt_any(i).store & io.lsu_pkt_m.store)|
|
||||||
|
(io.trigger_pkt_any(i).load & io.lsu_pkt_m.load & !io.trigger_pkt_any(i).select) )&
|
||||||
|
rvmaskandmatch(io.trigger_pkt_any(i).tdata2, lsu_match_data(i), io.trigger_pkt_any(i).match_.asBool())).reverse.reduce(Cat(_,_))
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
object main_trigger extends App{
|
||||||
|
println("Generate Verilog")
|
||||||
|
println((new chisel3.stage.ChiselStage).emitVerilog(new el2_lsu_trigger()))
|
||||||
|
}
|
||||||
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Reference in New Issue