dec update
This commit is contained in:
Laraib Khan
parent
220b0575c1
commit
23069873a9
2084
el2_dec.anno.json
2084
el2_dec.anno.json
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131
el2_dec.fir
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el2_dec.fir
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279
el2_dec.v
279
el2_dec.v
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@ -4,13 +4,13 @@ module el2_dec_ib_ctl(
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input [1:0] io_dbg_cmd_type,
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input [31:0] io_dbg_cmd_addr,
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input io_i0_brp_valid,
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input [11:0] io_i0_brp_toffset,
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input [1:0] io_i0_brp_hist,
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input io_i0_brp_br_error,
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input io_i0_brp_br_start_error,
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input [30:0] io_i0_brp_prett,
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input io_i0_brp_way,
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input io_i0_brp_ret,
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input [11:0] io_i0_brp_bits_toffset,
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input [1:0] io_i0_brp_bits_hist,
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input io_i0_brp_bits_br_error,
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input io_i0_brp_bits_br_start_error,
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input [30:0] io_i0_brp_bits_prett,
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input io_i0_brp_bits_way,
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input io_i0_brp_bits_ret,
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input [7:0] io_ifu_i0_bp_index,
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input [7:0] io_ifu_i0_bp_fghr,
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input [4:0] io_ifu_i0_bp_btag,
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@ -28,13 +28,13 @@ module el2_dec_ib_ctl(
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output [30:0] io_dec_i0_pc_d,
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output io_dec_i0_pc4_d,
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output io_dec_i0_brp_valid,
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output [11:0] io_dec_i0_brp_toffset,
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output [1:0] io_dec_i0_brp_hist,
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output io_dec_i0_brp_br_error,
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output io_dec_i0_brp_br_start_error,
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output [30:0] io_dec_i0_brp_prett,
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output io_dec_i0_brp_way,
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output io_dec_i0_brp_ret,
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output [11:0] io_dec_i0_brp_bits_toffset,
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output [1:0] io_dec_i0_brp_bits_hist,
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output io_dec_i0_brp_bits_br_error,
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output io_dec_i0_brp_bits_br_start_error,
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output [30:0] io_dec_i0_brp_bits_prett,
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output io_dec_i0_brp_bits_way,
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output io_dec_i0_brp_bits_ret,
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output [7:0] io_dec_i0_bp_index,
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output [7:0] io_dec_i0_bp_fghr,
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output [4:0] io_dec_i0_bp_btag,
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@ -78,13 +78,13 @@ module el2_dec_ib_ctl(
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assign io_dec_i0_pc_d = io_ifu_i0_pc; // @[el2_dec_ib_ctl.scala 11:31]
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assign io_dec_i0_pc4_d = io_ifu_i0_pc4; // @[el2_dec_ib_ctl.scala 12:31]
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assign io_dec_i0_brp_valid = io_i0_brp_valid; // @[el2_dec_ib_ctl.scala 14:31]
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assign io_dec_i0_brp_toffset = io_i0_brp_toffset; // @[el2_dec_ib_ctl.scala 14:31]
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assign io_dec_i0_brp_hist = io_i0_brp_hist; // @[el2_dec_ib_ctl.scala 14:31]
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assign io_dec_i0_brp_br_error = io_i0_brp_br_error; // @[el2_dec_ib_ctl.scala 14:31]
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assign io_dec_i0_brp_br_start_error = io_i0_brp_br_start_error; // @[el2_dec_ib_ctl.scala 14:31]
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assign io_dec_i0_brp_prett = io_i0_brp_prett; // @[el2_dec_ib_ctl.scala 14:31]
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assign io_dec_i0_brp_way = io_i0_brp_way; // @[el2_dec_ib_ctl.scala 14:31]
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assign io_dec_i0_brp_ret = io_i0_brp_ret; // @[el2_dec_ib_ctl.scala 14:31]
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assign io_dec_i0_brp_bits_toffset = io_i0_brp_bits_toffset; // @[el2_dec_ib_ctl.scala 14:31]
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assign io_dec_i0_brp_bits_hist = io_i0_brp_bits_hist; // @[el2_dec_ib_ctl.scala 14:31]
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assign io_dec_i0_brp_bits_br_error = io_i0_brp_bits_br_error; // @[el2_dec_ib_ctl.scala 14:31]
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assign io_dec_i0_brp_bits_br_start_error = io_i0_brp_bits_br_start_error; // @[el2_dec_ib_ctl.scala 14:31]
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assign io_dec_i0_brp_bits_prett = io_i0_brp_bits_prett; // @[el2_dec_ib_ctl.scala 14:31]
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assign io_dec_i0_brp_bits_way = io_i0_brp_bits_way; // @[el2_dec_ib_ctl.scala 14:31]
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assign io_dec_i0_brp_bits_ret = io_i0_brp_bits_ret; // @[el2_dec_ib_ctl.scala 14:31]
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assign io_dec_i0_bp_index = io_ifu_i0_bp_index; // @[el2_dec_ib_ctl.scala 15:31]
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assign io_dec_i0_bp_fghr = io_ifu_i0_bp_fghr; // @[el2_dec_ib_ctl.scala 16:31]
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assign io_dec_i0_bp_btag = io_ifu_i0_bp_btag; // @[el2_dec_ib_ctl.scala 17:31]
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@ -855,13 +855,13 @@ module el2_dec_decode_ctl(
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input [1:0] io_dec_i0_icaf_type_d,
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input io_dec_i0_dbecc_d,
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input io_dec_i0_brp_valid,
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input [11:0] io_dec_i0_brp_toffset,
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input [1:0] io_dec_i0_brp_hist,
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input io_dec_i0_brp_br_error,
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input io_dec_i0_brp_br_start_error,
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input [30:0] io_dec_i0_brp_prett,
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input io_dec_i0_brp_way,
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input io_dec_i0_brp_ret,
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input [11:0] io_dec_i0_brp_bits_toffset,
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input [1:0] io_dec_i0_brp_bits_hist,
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input io_dec_i0_brp_bits_br_error,
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input io_dec_i0_brp_bits_br_start_error,
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input [30:0] io_dec_i0_brp_bits_prett,
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input io_dec_i0_brp_bits_way,
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input io_dec_i0_brp_bits_ret,
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input [7:0] io_dec_i0_bp_index,
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input [7:0] io_dec_i0_bp_fghr,
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input [4:0] io_dec_i0_bp_btag,
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@ -1285,21 +1285,21 @@ module el2_dec_decode_ctl(
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wire _T_22 = _T_21 | i0_pret_raw; // @[el2_dec_decode_ctl.scala 237:103]
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wire _T_23 = ~_T_22; // @[el2_dec_decode_ctl.scala 237:56]
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wire i0_notbr_error = i0_brp_valid & _T_23; // @[el2_dec_decode_ctl.scala 237:54]
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wire _T_31 = io_dec_i0_brp_br_error | i0_notbr_error; // @[el2_dec_decode_ctl.scala 242:57]
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wire _T_25 = i0_brp_valid & io_dec_i0_brp_hist[1]; // @[el2_dec_decode_ctl.scala 240:47]
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wire _T_31 = io_dec_i0_brp_bits_br_error | i0_notbr_error; // @[el2_dec_decode_ctl.scala 242:62]
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wire _T_25 = i0_brp_valid & io_dec_i0_brp_bits_hist[1]; // @[el2_dec_decode_ctl.scala 240:47]
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wire _T_314 = i0_pcall_raw | i0_pja_raw; // @[el2_dec_decode_ctl.scala 415:41]
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wire [11:0] _T_323 = {io_dec_i0_instr_d[31],io_dec_i0_instr_d[7],io_dec_i0_instr_d[30:25],io_dec_i0_instr_d[11:8]}; // @[Cat.scala 29:58]
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wire [11:0] i0_br_offset = _T_314 ? i0_pcall_imm[11:0] : _T_323; // @[el2_dec_decode_ctl.scala 415:26]
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wire _T_26 = io_dec_i0_brp_toffset != i0_br_offset; // @[el2_dec_decode_ctl.scala 240:96]
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wire _T_27 = _T_25 & _T_26; // @[el2_dec_decode_ctl.scala 240:71]
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wire _T_28 = ~i0_pret_raw; // @[el2_dec_decode_ctl.scala 240:116]
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wire i0_br_toffset_error = _T_27 & _T_28; // @[el2_dec_decode_ctl.scala 240:114]
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wire _T_32 = _T_31 | i0_br_toffset_error; // @[el2_dec_decode_ctl.scala 242:74]
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wire _T_29 = i0_brp_valid & io_dec_i0_brp_ret; // @[el2_dec_decode_ctl.scala 241:47]
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wire i0_ret_error = _T_29 & _T_28; // @[el2_dec_decode_ctl.scala 241:67]
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wire i0_br_error = _T_32 | i0_ret_error; // @[el2_dec_decode_ctl.scala 242:96]
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wire _T_39 = i0_br_error | io_dec_i0_brp_br_start_error; // @[el2_dec_decode_ctl.scala 247:47]
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wire i0_br_error_all = _T_39 & _T_18; // @[el2_dec_decode_ctl.scala 247:79]
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wire _T_26 = io_dec_i0_brp_bits_toffset != i0_br_offset; // @[el2_dec_decode_ctl.scala 240:106]
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wire _T_27 = _T_25 & _T_26; // @[el2_dec_decode_ctl.scala 240:76]
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wire _T_28 = ~i0_pret_raw; // @[el2_dec_decode_ctl.scala 240:126]
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wire i0_br_toffset_error = _T_27 & _T_28; // @[el2_dec_decode_ctl.scala 240:124]
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wire _T_32 = _T_31 | i0_br_toffset_error; // @[el2_dec_decode_ctl.scala 242:79]
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wire _T_29 = i0_brp_valid & io_dec_i0_brp_bits_ret; // @[el2_dec_decode_ctl.scala 241:47]
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wire i0_ret_error = _T_29 & _T_28; // @[el2_dec_decode_ctl.scala 241:72]
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wire i0_br_error = _T_32 | i0_ret_error; // @[el2_dec_decode_ctl.scala 242:101]
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wire _T_39 = i0_br_error | io_dec_i0_brp_bits_br_start_error; // @[el2_dec_decode_ctl.scala 247:47]
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wire i0_br_error_all = _T_39 & _T_18; // @[el2_dec_decode_ctl.scala 247:84]
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wire i0_icaf_d = io_dec_i0_icaf_d | io_dec_i0_dbecc_d; // @[el2_dec_decode_ctl.scala 256:36]
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wire _T_41 = i0_br_error_all | i0_icaf_d; // @[el2_dec_decode_ctl.scala 260:25]
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wire i0_dp_raw_postsync = i0_dec_io_out_postsync; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12]
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@ -1344,7 +1344,7 @@ module el2_dec_decode_ctl(
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wire _T_16 = illegal_lockout_in ^ illegal_lockout; // @[el2_dec_decode_ctl.scala 219:32]
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wire i0_legal_decode_d = io_dec_i0_decode_d & i0_legal; // @[el2_dec_decode_ctl.scala 644:46]
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wire _T_33 = i0_br_error & i0_legal_decode_d; // @[el2_dec_decode_ctl.scala 243:72]
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wire _T_36 = io_dec_i0_brp_br_start_error & i0_legal_decode_d; // @[el2_dec_decode_ctl.scala 244:89]
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wire _T_36 = io_dec_i0_brp_bits_br_start_error & i0_legal_decode_d; // @[el2_dec_decode_ctl.scala 244:94]
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wire i0_dp_raw_pm_alu = i0_dec_io_out_pm_alu; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12]
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wire i0_dp_pm_alu = _T_41 ? 1'h0 : i0_dp_raw_pm_alu; // @[el2_dec_decode_ctl.scala 260:50]
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wire i0_dp_raw_fence_i = i0_dec_io_out_fence_i; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 394:12]
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@ -1421,7 +1421,7 @@ module el2_dec_decode_ctl(
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wire _T_45 = _T_44 | i0_pja; // @[el2_dec_decode_ctl.scala 274:49]
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wire i0_pret = i0_dp_jal & i0_pret_case; // @[el2_dec_decode_ctl.scala 419:32]
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wire i0_predict_br = _T_45 | i0_pret; // @[el2_dec_decode_ctl.scala 274:58]
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wire _T_47 = io_dec_i0_brp_hist[1] & i0_brp_valid; // @[el2_dec_decode_ctl.scala 276:50]
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wire _T_47 = io_dec_i0_brp_bits_hist[1] & i0_brp_valid; // @[el2_dec_decode_ctl.scala 276:55]
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wire _T_48 = ~_T_47; // @[el2_dec_decode_ctl.scala 276:26]
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wire i0_ap_pc2 = ~io_dec_i0_pc4_d; // @[el2_dec_decode_ctl.scala 278:20]
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wire cam_data_reset = io_lsu_nonblock_load_data_valid | io_lsu_nonblock_load_data_error; // @[el2_dec_decode_ctl.scala 311:63]
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@ -2208,15 +2208,15 @@ module el2_dec_decode_ctl(
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assign io_pred_correct_npc_x = temp_pred_correct_npc_x[31:1]; // @[el2_dec_decode_ctl.scala 764:25]
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assign io_dec_i0_predict_p_d_valid = i0_brp_valid & i0_legal_decode_d; // @[el2_dec_decode_ctl.scala 236:38]
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assign io_dec_i0_predict_p_d_bits_pc4 = io_dec_i0_pc4_d; // @[el2_dec_decode_ctl.scala 234:43]
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assign io_dec_i0_predict_p_d_bits_hist = io_dec_i0_brp_hist; // @[el2_dec_decode_ctl.scala 235:43]
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assign io_dec_i0_predict_p_d_bits_hist = io_dec_i0_brp_bits_hist; // @[el2_dec_decode_ctl.scala 235:43]
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assign io_dec_i0_predict_p_d_bits_toffset = _T_314 ? i0_pcall_imm[11:0] : _T_323; // @[el2_dec_decode_ctl.scala 248:49]
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assign io_dec_i0_predict_p_d_bits_br_error = _T_33 & _T_18; // @[el2_dec_decode_ctl.scala 243:56]
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assign io_dec_i0_predict_p_d_bits_br_start_error = _T_36 & _T_18; // @[el2_dec_decode_ctl.scala 244:56]
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assign io_dec_i0_predict_p_d_bits_prett = io_dec_i0_brp_prett; // @[el2_dec_decode_ctl.scala 233:43]
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assign io_dec_i0_predict_p_d_bits_prett = io_dec_i0_brp_bits_prett; // @[el2_dec_decode_ctl.scala 233:43]
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assign io_dec_i0_predict_p_d_bits_pcall = i0_dp_jal & i0_pcall_case; // @[el2_dec_decode_ctl.scala 230:43]
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assign io_dec_i0_predict_p_d_bits_pret = i0_dp_jal & i0_pret_case; // @[el2_dec_decode_ctl.scala 232:43]
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assign io_dec_i0_predict_p_d_bits_pja = i0_dp_jal & i0_pja_case; // @[el2_dec_decode_ctl.scala 231:43]
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assign io_dec_i0_predict_p_d_bits_way = io_dec_i0_brp_way; // @[el2_dec_decode_ctl.scala 250:56]
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assign io_dec_i0_predict_p_d_bits_way = io_dec_i0_brp_bits_way; // @[el2_dec_decode_ctl.scala 250:56]
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assign io_i0_predict_fghr_d = io_dec_i0_bp_fghr; // @[el2_dec_decode_ctl.scala 249:32]
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assign io_i0_predict_index_d = io_dec_i0_bp_index; // @[el2_dec_decode_ctl.scala 245:32]
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assign io_i0_predict_btag_d = io_dec_i0_bp_btag; // @[el2_dec_decode_ctl.scala 246:32]
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@ -9251,11 +9251,11 @@ module el2_dec_tlu_ctl(
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output [31:0] io_dec_csr_rddata_d,
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output io_dec_csr_legal_d,
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output io_dec_tlu_br0_r_pkt_valid,
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output [1:0] io_dec_tlu_br0_r_pkt_hist,
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output io_dec_tlu_br0_r_pkt_br_error,
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output io_dec_tlu_br0_r_pkt_br_start_error,
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output io_dec_tlu_br0_r_pkt_way,
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output io_dec_tlu_br0_r_pkt_middle,
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output [1:0] io_dec_tlu_br0_r_pkt_bits_hist,
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output io_dec_tlu_br0_r_pkt_bits_br_error,
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output io_dec_tlu_br0_r_pkt_bits_br_start_error,
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output io_dec_tlu_br0_r_pkt_bits_way,
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output io_dec_tlu_br0_r_pkt_bits_middle,
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output io_dec_tlu_i0_kill_writeb_wb,
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output io_dec_tlu_flush_lower_wb,
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output io_dec_tlu_i0_commit_cmt,
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@ -10896,11 +10896,11 @@ module el2_dec_tlu_ctl(
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assign io_dec_csr_rddata_d = csr_io_dec_csr_rddata_d; // @[el2_dec_tlu_ctl.scala 977:40]
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assign io_dec_csr_legal_d = _T_887 & _T_894; // @[el2_dec_tlu_ctl.scala 1101:22]
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assign io_dec_tlu_br0_r_pkt_valid = _T_459 & _T_462; // @[el2_dec_tlu_ctl.scala 733:49]
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assign io_dec_tlu_br0_r_pkt_hist = io_exu_i0_br_hist_r; // @[el2_dec_tlu_ctl.scala 730:49]
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assign io_dec_tlu_br0_r_pkt_br_error = _T_453 & _T_429; // @[el2_dec_tlu_ctl.scala 731:49]
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assign io_dec_tlu_br0_r_pkt_br_start_error = _T_455 & _T_429; // @[el2_dec_tlu_ctl.scala 732:41]
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assign io_dec_tlu_br0_r_pkt_way = io_exu_i0_br_way_r; // @[el2_dec_tlu_ctl.scala 734:49]
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assign io_dec_tlu_br0_r_pkt_middle = io_exu_i0_br_middle_r; // @[el2_dec_tlu_ctl.scala 735:49]
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assign io_dec_tlu_br0_r_pkt_bits_hist = io_exu_i0_br_hist_r; // @[el2_dec_tlu_ctl.scala 730:57]
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assign io_dec_tlu_br0_r_pkt_bits_br_error = _T_453 & _T_429; // @[el2_dec_tlu_ctl.scala 731:49]
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assign io_dec_tlu_br0_r_pkt_bits_br_start_error = _T_455 & _T_429; // @[el2_dec_tlu_ctl.scala 732:49]
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assign io_dec_tlu_br0_r_pkt_bits_way = io_exu_i0_br_way_r; // @[el2_dec_tlu_ctl.scala 734:57]
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assign io_dec_tlu_br0_r_pkt_bits_middle = io_exu_i0_br_middle_r; // @[el2_dec_tlu_ctl.scala 735:57]
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assign io_dec_tlu_i0_kill_writeb_wb = _T_32; // @[el2_dec_tlu_ctl.scala 409:33]
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assign io_dec_tlu_flush_lower_wb = tlu_flush_lower_r_d1; // @[el2_dec_tlu_ctl.scala 881:33]
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assign io_dec_tlu_i0_commit_cmt = _T_422 & _T_465; // @[el2_dec_tlu_ctl.scala 708:28]
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@ -12777,14 +12777,15 @@ module el2_dec(
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input io_ifu_i0_dbecc,
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input io_lsu_idle_any,
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input io_i0_brp_valid,
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input [11:0] io_i0_brp_toffset,
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input [1:0] io_i0_brp_hist,
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input io_i0_brp_br_error,
|
||||
input io_i0_brp_br_start_error,
|
||||
input io_i0_brp_bank,
|
||||
input [30:0] io_i0_brp_prett,
|
||||
input io_i0_brp_way,
|
||||
input io_i0_brp_ret,
|
||||
input io_i0_brp_bits_valid,
|
||||
input [11:0] io_i0_brp_bits_toffset,
|
||||
input [1:0] io_i0_brp_bits_hist,
|
||||
input io_i0_brp_bits_br_error,
|
||||
input io_i0_brp_bits_br_start_error,
|
||||
input io_i0_brp_bits_bank,
|
||||
input [30:0] io_i0_brp_bits_prett,
|
||||
input io_i0_brp_bits_way,
|
||||
input io_i0_brp_bits_ret,
|
||||
input [7:0] io_ifu_i0_bp_index,
|
||||
input [7:0] io_ifu_i0_bp_fghr,
|
||||
input [4:0] io_ifu_i0_bp_btag,
|
||||
|
|
@ -12957,11 +12958,11 @@ module el2_dec(
|
|||
output io_dec_tlu_fence_i_r,
|
||||
output [30:0] io_pred_correct_npc_x,
|
||||
output io_dec_tlu_br0_r_pkt_valid,
|
||||
output [1:0] io_dec_tlu_br0_r_pkt_hist,
|
||||
output io_dec_tlu_br0_r_pkt_br_error,
|
||||
output io_dec_tlu_br0_r_pkt_br_start_error,
|
||||
output io_dec_tlu_br0_r_pkt_way,
|
||||
output io_dec_tlu_br0_r_pkt_middle,
|
||||
output [1:0] io_dec_tlu_br0_r_pkt_bits_hist,
|
||||
output io_dec_tlu_br0_r_pkt_bits_br_error,
|
||||
output io_dec_tlu_br0_r_pkt_bits_br_start_error,
|
||||
output io_dec_tlu_br0_r_pkt_bits_way,
|
||||
output io_dec_tlu_br0_r_pkt_bits_middle,
|
||||
output io_dec_tlu_perfcnt0,
|
||||
output io_dec_tlu_perfcnt1,
|
||||
output io_dec_tlu_perfcnt2,
|
||||
|
|
@ -13016,13 +13017,13 @@ module el2_dec(
|
|||
wire [1:0] instbuff_io_dbg_cmd_type; // @[el2_dec.scala 285:24]
|
||||
wire [31:0] instbuff_io_dbg_cmd_addr; // @[el2_dec.scala 285:24]
|
||||
wire instbuff_io_i0_brp_valid; // @[el2_dec.scala 285:24]
|
||||
wire [11:0] instbuff_io_i0_brp_toffset; // @[el2_dec.scala 285:24]
|
||||
wire [1:0] instbuff_io_i0_brp_hist; // @[el2_dec.scala 285:24]
|
||||
wire instbuff_io_i0_brp_br_error; // @[el2_dec.scala 285:24]
|
||||
wire instbuff_io_i0_brp_br_start_error; // @[el2_dec.scala 285:24]
|
||||
wire [30:0] instbuff_io_i0_brp_prett; // @[el2_dec.scala 285:24]
|
||||
wire instbuff_io_i0_brp_way; // @[el2_dec.scala 285:24]
|
||||
wire instbuff_io_i0_brp_ret; // @[el2_dec.scala 285:24]
|
||||
wire [11:0] instbuff_io_i0_brp_bits_toffset; // @[el2_dec.scala 285:24]
|
||||
wire [1:0] instbuff_io_i0_brp_bits_hist; // @[el2_dec.scala 285:24]
|
||||
wire instbuff_io_i0_brp_bits_br_error; // @[el2_dec.scala 285:24]
|
||||
wire instbuff_io_i0_brp_bits_br_start_error; // @[el2_dec.scala 285:24]
|
||||
wire [30:0] instbuff_io_i0_brp_bits_prett; // @[el2_dec.scala 285:24]
|
||||
wire instbuff_io_i0_brp_bits_way; // @[el2_dec.scala 285:24]
|
||||
wire instbuff_io_i0_brp_bits_ret; // @[el2_dec.scala 285:24]
|
||||
wire [7:0] instbuff_io_ifu_i0_bp_index; // @[el2_dec.scala 285:24]
|
||||
wire [7:0] instbuff_io_ifu_i0_bp_fghr; // @[el2_dec.scala 285:24]
|
||||
wire [4:0] instbuff_io_ifu_i0_bp_btag; // @[el2_dec.scala 285:24]
|
||||
|
|
@ -13040,13 +13041,13 @@ module el2_dec(
|
|||
wire [30:0] instbuff_io_dec_i0_pc_d; // @[el2_dec.scala 285:24]
|
||||
wire instbuff_io_dec_i0_pc4_d; // @[el2_dec.scala 285:24]
|
||||
wire instbuff_io_dec_i0_brp_valid; // @[el2_dec.scala 285:24]
|
||||
wire [11:0] instbuff_io_dec_i0_brp_toffset; // @[el2_dec.scala 285:24]
|
||||
wire [1:0] instbuff_io_dec_i0_brp_hist; // @[el2_dec.scala 285:24]
|
||||
wire instbuff_io_dec_i0_brp_br_error; // @[el2_dec.scala 285:24]
|
||||
wire instbuff_io_dec_i0_brp_br_start_error; // @[el2_dec.scala 285:24]
|
||||
wire [30:0] instbuff_io_dec_i0_brp_prett; // @[el2_dec.scala 285:24]
|
||||
wire instbuff_io_dec_i0_brp_way; // @[el2_dec.scala 285:24]
|
||||
wire instbuff_io_dec_i0_brp_ret; // @[el2_dec.scala 285:24]
|
||||
wire [11:0] instbuff_io_dec_i0_brp_bits_toffset; // @[el2_dec.scala 285:24]
|
||||
wire [1:0] instbuff_io_dec_i0_brp_bits_hist; // @[el2_dec.scala 285:24]
|
||||
wire instbuff_io_dec_i0_brp_bits_br_error; // @[el2_dec.scala 285:24]
|
||||
wire instbuff_io_dec_i0_brp_bits_br_start_error; // @[el2_dec.scala 285:24]
|
||||
wire [30:0] instbuff_io_dec_i0_brp_bits_prett; // @[el2_dec.scala 285:24]
|
||||
wire instbuff_io_dec_i0_brp_bits_way; // @[el2_dec.scala 285:24]
|
||||
wire instbuff_io_dec_i0_brp_bits_ret; // @[el2_dec.scala 285:24]
|
||||
wire [7:0] instbuff_io_dec_i0_bp_index; // @[el2_dec.scala 285:24]
|
||||
wire [7:0] instbuff_io_dec_i0_bp_fghr; // @[el2_dec.scala 285:24]
|
||||
wire [4:0] instbuff_io_dec_i0_bp_btag; // @[el2_dec.scala 285:24]
|
||||
|
|
@ -13085,13 +13086,13 @@ module el2_dec(
|
|||
wire [1:0] decode_io_dec_i0_icaf_type_d; // @[el2_dec.scala 286:22]
|
||||
wire decode_io_dec_i0_dbecc_d; // @[el2_dec.scala 286:22]
|
||||
wire decode_io_dec_i0_brp_valid; // @[el2_dec.scala 286:22]
|
||||
wire [11:0] decode_io_dec_i0_brp_toffset; // @[el2_dec.scala 286:22]
|
||||
wire [1:0] decode_io_dec_i0_brp_hist; // @[el2_dec.scala 286:22]
|
||||
wire decode_io_dec_i0_brp_br_error; // @[el2_dec.scala 286:22]
|
||||
wire decode_io_dec_i0_brp_br_start_error; // @[el2_dec.scala 286:22]
|
||||
wire [30:0] decode_io_dec_i0_brp_prett; // @[el2_dec.scala 286:22]
|
||||
wire decode_io_dec_i0_brp_way; // @[el2_dec.scala 286:22]
|
||||
wire decode_io_dec_i0_brp_ret; // @[el2_dec.scala 286:22]
|
||||
wire [11:0] decode_io_dec_i0_brp_bits_toffset; // @[el2_dec.scala 286:22]
|
||||
wire [1:0] decode_io_dec_i0_brp_bits_hist; // @[el2_dec.scala 286:22]
|
||||
wire decode_io_dec_i0_brp_bits_br_error; // @[el2_dec.scala 286:22]
|
||||
wire decode_io_dec_i0_brp_bits_br_start_error; // @[el2_dec.scala 286:22]
|
||||
wire [30:0] decode_io_dec_i0_brp_bits_prett; // @[el2_dec.scala 286:22]
|
||||
wire decode_io_dec_i0_brp_bits_way; // @[el2_dec.scala 286:22]
|
||||
wire decode_io_dec_i0_brp_bits_ret; // @[el2_dec.scala 286:22]
|
||||
wire [7:0] decode_io_dec_i0_bp_index; // @[el2_dec.scala 286:22]
|
||||
wire [7:0] decode_io_dec_i0_bp_fghr; // @[el2_dec.scala 286:22]
|
||||
wire [4:0] decode_io_dec_i0_bp_btag; // @[el2_dec.scala 286:22]
|
||||
|
|
@ -13397,11 +13398,11 @@ module el2_dec(
|
|||
wire [31:0] tlu_io_dec_csr_rddata_d; // @[el2_dec.scala 288:19]
|
||||
wire tlu_io_dec_csr_legal_d; // @[el2_dec.scala 288:19]
|
||||
wire tlu_io_dec_tlu_br0_r_pkt_valid; // @[el2_dec.scala 288:19]
|
||||
wire [1:0] tlu_io_dec_tlu_br0_r_pkt_hist; // @[el2_dec.scala 288:19]
|
||||
wire tlu_io_dec_tlu_br0_r_pkt_br_error; // @[el2_dec.scala 288:19]
|
||||
wire tlu_io_dec_tlu_br0_r_pkt_br_start_error; // @[el2_dec.scala 288:19]
|
||||
wire tlu_io_dec_tlu_br0_r_pkt_way; // @[el2_dec.scala 288:19]
|
||||
wire tlu_io_dec_tlu_br0_r_pkt_middle; // @[el2_dec.scala 288:19]
|
||||
wire [1:0] tlu_io_dec_tlu_br0_r_pkt_bits_hist; // @[el2_dec.scala 288:19]
|
||||
wire tlu_io_dec_tlu_br0_r_pkt_bits_br_error; // @[el2_dec.scala 288:19]
|
||||
wire tlu_io_dec_tlu_br0_r_pkt_bits_br_start_error; // @[el2_dec.scala 288:19]
|
||||
wire tlu_io_dec_tlu_br0_r_pkt_bits_way; // @[el2_dec.scala 288:19]
|
||||
wire tlu_io_dec_tlu_br0_r_pkt_bits_middle; // @[el2_dec.scala 288:19]
|
||||
wire tlu_io_dec_tlu_i0_kill_writeb_wb; // @[el2_dec.scala 288:19]
|
||||
wire tlu_io_dec_tlu_flush_lower_wb; // @[el2_dec.scala 288:19]
|
||||
wire tlu_io_dec_tlu_i0_commit_cmt; // @[el2_dec.scala 288:19]
|
||||
|
|
@ -13468,13 +13469,13 @@ module el2_dec(
|
|||
.io_dbg_cmd_type(instbuff_io_dbg_cmd_type),
|
||||
.io_dbg_cmd_addr(instbuff_io_dbg_cmd_addr),
|
||||
.io_i0_brp_valid(instbuff_io_i0_brp_valid),
|
||||
.io_i0_brp_toffset(instbuff_io_i0_brp_toffset),
|
||||
.io_i0_brp_hist(instbuff_io_i0_brp_hist),
|
||||
.io_i0_brp_br_error(instbuff_io_i0_brp_br_error),
|
||||
.io_i0_brp_br_start_error(instbuff_io_i0_brp_br_start_error),
|
||||
.io_i0_brp_prett(instbuff_io_i0_brp_prett),
|
||||
.io_i0_brp_way(instbuff_io_i0_brp_way),
|
||||
.io_i0_brp_ret(instbuff_io_i0_brp_ret),
|
||||
.io_i0_brp_bits_toffset(instbuff_io_i0_brp_bits_toffset),
|
||||
.io_i0_brp_bits_hist(instbuff_io_i0_brp_bits_hist),
|
||||
.io_i0_brp_bits_br_error(instbuff_io_i0_brp_bits_br_error),
|
||||
.io_i0_brp_bits_br_start_error(instbuff_io_i0_brp_bits_br_start_error),
|
||||
.io_i0_brp_bits_prett(instbuff_io_i0_brp_bits_prett),
|
||||
.io_i0_brp_bits_way(instbuff_io_i0_brp_bits_way),
|
||||
.io_i0_brp_bits_ret(instbuff_io_i0_brp_bits_ret),
|
||||
.io_ifu_i0_bp_index(instbuff_io_ifu_i0_bp_index),
|
||||
.io_ifu_i0_bp_fghr(instbuff_io_ifu_i0_bp_fghr),
|
||||
.io_ifu_i0_bp_btag(instbuff_io_ifu_i0_bp_btag),
|
||||
|
|
@ -13492,13 +13493,13 @@ module el2_dec(
|
|||
.io_dec_i0_pc_d(instbuff_io_dec_i0_pc_d),
|
||||
.io_dec_i0_pc4_d(instbuff_io_dec_i0_pc4_d),
|
||||
.io_dec_i0_brp_valid(instbuff_io_dec_i0_brp_valid),
|
||||
.io_dec_i0_brp_toffset(instbuff_io_dec_i0_brp_toffset),
|
||||
.io_dec_i0_brp_hist(instbuff_io_dec_i0_brp_hist),
|
||||
.io_dec_i0_brp_br_error(instbuff_io_dec_i0_brp_br_error),
|
||||
.io_dec_i0_brp_br_start_error(instbuff_io_dec_i0_brp_br_start_error),
|
||||
.io_dec_i0_brp_prett(instbuff_io_dec_i0_brp_prett),
|
||||
.io_dec_i0_brp_way(instbuff_io_dec_i0_brp_way),
|
||||
.io_dec_i0_brp_ret(instbuff_io_dec_i0_brp_ret),
|
||||
.io_dec_i0_brp_bits_toffset(instbuff_io_dec_i0_brp_bits_toffset),
|
||||
.io_dec_i0_brp_bits_hist(instbuff_io_dec_i0_brp_bits_hist),
|
||||
.io_dec_i0_brp_bits_br_error(instbuff_io_dec_i0_brp_bits_br_error),
|
||||
.io_dec_i0_brp_bits_br_start_error(instbuff_io_dec_i0_brp_bits_br_start_error),
|
||||
.io_dec_i0_brp_bits_prett(instbuff_io_dec_i0_brp_bits_prett),
|
||||
.io_dec_i0_brp_bits_way(instbuff_io_dec_i0_brp_bits_way),
|
||||
.io_dec_i0_brp_bits_ret(instbuff_io_dec_i0_brp_bits_ret),
|
||||
.io_dec_i0_bp_index(instbuff_io_dec_i0_bp_index),
|
||||
.io_dec_i0_bp_fghr(instbuff_io_dec_i0_bp_fghr),
|
||||
.io_dec_i0_bp_btag(instbuff_io_dec_i0_bp_btag),
|
||||
|
|
@ -13539,13 +13540,13 @@ module el2_dec(
|
|||
.io_dec_i0_icaf_type_d(decode_io_dec_i0_icaf_type_d),
|
||||
.io_dec_i0_dbecc_d(decode_io_dec_i0_dbecc_d),
|
||||
.io_dec_i0_brp_valid(decode_io_dec_i0_brp_valid),
|
||||
.io_dec_i0_brp_toffset(decode_io_dec_i0_brp_toffset),
|
||||
.io_dec_i0_brp_hist(decode_io_dec_i0_brp_hist),
|
||||
.io_dec_i0_brp_br_error(decode_io_dec_i0_brp_br_error),
|
||||
.io_dec_i0_brp_br_start_error(decode_io_dec_i0_brp_br_start_error),
|
||||
.io_dec_i0_brp_prett(decode_io_dec_i0_brp_prett),
|
||||
.io_dec_i0_brp_way(decode_io_dec_i0_brp_way),
|
||||
.io_dec_i0_brp_ret(decode_io_dec_i0_brp_ret),
|
||||
.io_dec_i0_brp_bits_toffset(decode_io_dec_i0_brp_bits_toffset),
|
||||
.io_dec_i0_brp_bits_hist(decode_io_dec_i0_brp_bits_hist),
|
||||
.io_dec_i0_brp_bits_br_error(decode_io_dec_i0_brp_bits_br_error),
|
||||
.io_dec_i0_brp_bits_br_start_error(decode_io_dec_i0_brp_bits_br_start_error),
|
||||
.io_dec_i0_brp_bits_prett(decode_io_dec_i0_brp_bits_prett),
|
||||
.io_dec_i0_brp_bits_way(decode_io_dec_i0_brp_bits_way),
|
||||
.io_dec_i0_brp_bits_ret(decode_io_dec_i0_brp_bits_ret),
|
||||
.io_dec_i0_bp_index(decode_io_dec_i0_bp_index),
|
||||
.io_dec_i0_bp_fghr(decode_io_dec_i0_bp_fghr),
|
||||
.io_dec_i0_bp_btag(decode_io_dec_i0_bp_btag),
|
||||
|
|
@ -13855,11 +13856,11 @@ module el2_dec(
|
|||
.io_dec_csr_rddata_d(tlu_io_dec_csr_rddata_d),
|
||||
.io_dec_csr_legal_d(tlu_io_dec_csr_legal_d),
|
||||
.io_dec_tlu_br0_r_pkt_valid(tlu_io_dec_tlu_br0_r_pkt_valid),
|
||||
.io_dec_tlu_br0_r_pkt_hist(tlu_io_dec_tlu_br0_r_pkt_hist),
|
||||
.io_dec_tlu_br0_r_pkt_br_error(tlu_io_dec_tlu_br0_r_pkt_br_error),
|
||||
.io_dec_tlu_br0_r_pkt_br_start_error(tlu_io_dec_tlu_br0_r_pkt_br_start_error),
|
||||
.io_dec_tlu_br0_r_pkt_way(tlu_io_dec_tlu_br0_r_pkt_way),
|
||||
.io_dec_tlu_br0_r_pkt_middle(tlu_io_dec_tlu_br0_r_pkt_middle),
|
||||
.io_dec_tlu_br0_r_pkt_bits_hist(tlu_io_dec_tlu_br0_r_pkt_bits_hist),
|
||||
.io_dec_tlu_br0_r_pkt_bits_br_error(tlu_io_dec_tlu_br0_r_pkt_bits_br_error),
|
||||
.io_dec_tlu_br0_r_pkt_bits_br_start_error(tlu_io_dec_tlu_br0_r_pkt_bits_br_start_error),
|
||||
.io_dec_tlu_br0_r_pkt_bits_way(tlu_io_dec_tlu_br0_r_pkt_bits_way),
|
||||
.io_dec_tlu_br0_r_pkt_bits_middle(tlu_io_dec_tlu_br0_r_pkt_bits_middle),
|
||||
.io_dec_tlu_i0_kill_writeb_wb(tlu_io_dec_tlu_i0_kill_writeb_wb),
|
||||
.io_dec_tlu_flush_lower_wb(tlu_io_dec_tlu_flush_lower_wb),
|
||||
.io_dec_tlu_i0_commit_cmt(tlu_io_dec_tlu_i0_commit_cmt),
|
||||
|
|
@ -14055,11 +14056,11 @@ module el2_dec(
|
|||
assign io_dec_tlu_fence_i_r = tlu_io_dec_tlu_fence_i_r; // @[el2_dec.scala 562:34]
|
||||
assign io_pred_correct_npc_x = decode_io_pred_correct_npc_x; // @[el2_dec.scala 411:40]
|
||||
assign io_dec_tlu_br0_r_pkt_valid = tlu_io_dec_tlu_br0_r_pkt_valid; // @[el2_dec.scala 557:42]
|
||||
assign io_dec_tlu_br0_r_pkt_hist = tlu_io_dec_tlu_br0_r_pkt_hist; // @[el2_dec.scala 557:42]
|
||||
assign io_dec_tlu_br0_r_pkt_br_error = tlu_io_dec_tlu_br0_r_pkt_br_error; // @[el2_dec.scala 557:42]
|
||||
assign io_dec_tlu_br0_r_pkt_br_start_error = tlu_io_dec_tlu_br0_r_pkt_br_start_error; // @[el2_dec.scala 557:42]
|
||||
assign io_dec_tlu_br0_r_pkt_way = tlu_io_dec_tlu_br0_r_pkt_way; // @[el2_dec.scala 557:42]
|
||||
assign io_dec_tlu_br0_r_pkt_middle = tlu_io_dec_tlu_br0_r_pkt_middle; // @[el2_dec.scala 557:42]
|
||||
assign io_dec_tlu_br0_r_pkt_bits_hist = tlu_io_dec_tlu_br0_r_pkt_bits_hist; // @[el2_dec.scala 557:42]
|
||||
assign io_dec_tlu_br0_r_pkt_bits_br_error = tlu_io_dec_tlu_br0_r_pkt_bits_br_error; // @[el2_dec.scala 557:42]
|
||||
assign io_dec_tlu_br0_r_pkt_bits_br_start_error = tlu_io_dec_tlu_br0_r_pkt_bits_br_start_error; // @[el2_dec.scala 557:42]
|
||||
assign io_dec_tlu_br0_r_pkt_bits_way = tlu_io_dec_tlu_br0_r_pkt_bits_way; // @[el2_dec.scala 557:42]
|
||||
assign io_dec_tlu_br0_r_pkt_bits_middle = tlu_io_dec_tlu_br0_r_pkt_bits_middle; // @[el2_dec.scala 557:42]
|
||||
assign io_dec_tlu_perfcnt0 = tlu_io_dec_tlu_perfcnt0; // @[el2_dec.scala 565:29]
|
||||
assign io_dec_tlu_perfcnt1 = tlu_io_dec_tlu_perfcnt1; // @[el2_dec.scala 566:29]
|
||||
assign io_dec_tlu_perfcnt2 = tlu_io_dec_tlu_perfcnt2; // @[el2_dec.scala 567:29]
|
||||
|
|
@ -14111,13 +14112,13 @@ module el2_dec(
|
|||
assign instbuff_io_dbg_cmd_type = io_dbg_cmd_type; // @[el2_dec.scala 299:45]
|
||||
assign instbuff_io_dbg_cmd_addr = io_dbg_cmd_addr; // @[el2_dec.scala 300:45]
|
||||
assign instbuff_io_i0_brp_valid = io_i0_brp_valid; // @[el2_dec.scala 301:55]
|
||||
assign instbuff_io_i0_brp_toffset = io_i0_brp_toffset; // @[el2_dec.scala 301:55]
|
||||
assign instbuff_io_i0_brp_hist = io_i0_brp_hist; // @[el2_dec.scala 301:55]
|
||||
assign instbuff_io_i0_brp_br_error = io_i0_brp_br_error; // @[el2_dec.scala 301:55]
|
||||
assign instbuff_io_i0_brp_br_start_error = io_i0_brp_br_start_error; // @[el2_dec.scala 301:55]
|
||||
assign instbuff_io_i0_brp_prett = io_i0_brp_prett; // @[el2_dec.scala 301:55]
|
||||
assign instbuff_io_i0_brp_way = io_i0_brp_way; // @[el2_dec.scala 301:55]
|
||||
assign instbuff_io_i0_brp_ret = io_i0_brp_ret; // @[el2_dec.scala 301:55]
|
||||
assign instbuff_io_i0_brp_bits_toffset = io_i0_brp_bits_toffset; // @[el2_dec.scala 301:55]
|
||||
assign instbuff_io_i0_brp_bits_hist = io_i0_brp_bits_hist; // @[el2_dec.scala 301:55]
|
||||
assign instbuff_io_i0_brp_bits_br_error = io_i0_brp_bits_br_error; // @[el2_dec.scala 301:55]
|
||||
assign instbuff_io_i0_brp_bits_br_start_error = io_i0_brp_bits_br_start_error; // @[el2_dec.scala 301:55]
|
||||
assign instbuff_io_i0_brp_bits_prett = io_i0_brp_bits_prett; // @[el2_dec.scala 301:55]
|
||||
assign instbuff_io_i0_brp_bits_way = io_i0_brp_bits_way; // @[el2_dec.scala 301:55]
|
||||
assign instbuff_io_i0_brp_bits_ret = io_i0_brp_bits_ret; // @[el2_dec.scala 301:55]
|
||||
assign instbuff_io_ifu_i0_bp_index = io_ifu_i0_bp_index; // @[el2_dec.scala 302:35]
|
||||
assign instbuff_io_ifu_i0_bp_fghr = io_ifu_i0_bp_fghr; // @[el2_dec.scala 303:35]
|
||||
assign instbuff_io_ifu_i0_bp_btag = io_ifu_i0_bp_btag; // @[el2_dec.scala 304:35]
|
||||
|
|
@ -14156,13 +14157,13 @@ module el2_dec(
|
|||
assign decode_io_dec_i0_icaf_type_d = instbuff_io_dec_i0_icaf_type_d; // @[el2_dec.scala 352:48]
|
||||
assign decode_io_dec_i0_dbecc_d = instbuff_io_dec_i0_dbecc_d; // @[el2_dec.scala 353:48]
|
||||
assign decode_io_dec_i0_brp_valid = instbuff_io_dec_i0_brp_valid; // @[el2_dec.scala 354:48]
|
||||
assign decode_io_dec_i0_brp_toffset = instbuff_io_dec_i0_brp_toffset; // @[el2_dec.scala 354:48]
|
||||
assign decode_io_dec_i0_brp_hist = instbuff_io_dec_i0_brp_hist; // @[el2_dec.scala 354:48]
|
||||
assign decode_io_dec_i0_brp_br_error = instbuff_io_dec_i0_brp_br_error; // @[el2_dec.scala 354:48]
|
||||
assign decode_io_dec_i0_brp_br_start_error = instbuff_io_dec_i0_brp_br_start_error; // @[el2_dec.scala 354:48]
|
||||
assign decode_io_dec_i0_brp_prett = instbuff_io_dec_i0_brp_prett; // @[el2_dec.scala 354:48]
|
||||
assign decode_io_dec_i0_brp_way = instbuff_io_dec_i0_brp_way; // @[el2_dec.scala 354:48]
|
||||
assign decode_io_dec_i0_brp_ret = instbuff_io_dec_i0_brp_ret; // @[el2_dec.scala 354:48]
|
||||
assign decode_io_dec_i0_brp_bits_toffset = instbuff_io_dec_i0_brp_bits_toffset; // @[el2_dec.scala 354:48]
|
||||
assign decode_io_dec_i0_brp_bits_hist = instbuff_io_dec_i0_brp_bits_hist; // @[el2_dec.scala 354:48]
|
||||
assign decode_io_dec_i0_brp_bits_br_error = instbuff_io_dec_i0_brp_bits_br_error; // @[el2_dec.scala 354:48]
|
||||
assign decode_io_dec_i0_brp_bits_br_start_error = instbuff_io_dec_i0_brp_bits_br_start_error; // @[el2_dec.scala 354:48]
|
||||
assign decode_io_dec_i0_brp_bits_prett = instbuff_io_dec_i0_brp_bits_prett; // @[el2_dec.scala 354:48]
|
||||
assign decode_io_dec_i0_brp_bits_way = instbuff_io_dec_i0_brp_bits_way; // @[el2_dec.scala 354:48]
|
||||
assign decode_io_dec_i0_brp_bits_ret = instbuff_io_dec_i0_brp_bits_ret; // @[el2_dec.scala 354:48]
|
||||
assign decode_io_dec_i0_bp_index = instbuff_io_dec_i0_bp_index; // @[el2_dec.scala 355:48]
|
||||
assign decode_io_dec_i0_bp_fghr = instbuff_io_dec_i0_bp_fghr; // @[el2_dec.scala 356:48]
|
||||
assign decode_io_dec_i0_bp_btag = instbuff_io_dec_i0_bp_btag; // @[el2_dec.scala 357:48]
|
||||
|
|
|
|||
|
|
@ -1,28 +1,88 @@
|
|||
[
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu|el2_ifu>io_ifu_pmu_fetch_stall",
|
||||
"sink":"~el2_ifu|el2_ifu>io_iccm_dma_ecc_error",
|
||||
"sources":[
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_core_ecc_disable",
|
||||
"~el2_ifu|el2_ifu>io_iccm_rd_data_ecc",
|
||||
"~el2_ifu|el2_ifu>io_exu_flush_final",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_err_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_i0_commit_cmt",
|
||||
"~el2_ifu|el2_ifu>io_ic_rd_data",
|
||||
"~el2_ifu|el2_ifu>io_dec_i0_decode_d",
|
||||
"~el2_ifu|el2_ifu>io_ic_rd_hit",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_start_error",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_error",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_start_error",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_error",
|
||||
"~el2_ifu|el2_ifu>io_exu_i0_br_index_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu|el2_ifu>io_iccm_wren",
|
||||
"sink":"~el2_ifu|el2_ifu>io_ic_rd_en",
|
||||
"sources":[
|
||||
"~el2_ifu|el2_ifu>io_exu_flush_final",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_force_halt",
|
||||
"~el2_ifu|el2_ifu>io_ic_rd_hit",
|
||||
"~el2_ifu|el2_ifu>io_exu_flush_path_final",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_noredir_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_mrac_ff",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_start_error",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_error",
|
||||
"~el2_ifu|el2_ifu>io_exu_i0_br_index_r",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_err_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_i0_commit_cmt",
|
||||
"~el2_ifu|el2_ifu>io_ic_rd_data",
|
||||
"~el2_ifu|el2_ifu>io_dec_i0_decode_d"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu|el2_ifu>io_iccm_rden",
|
||||
"sources":[
|
||||
"~el2_ifu|el2_ifu>io_dma_mem_write",
|
||||
"~el2_ifu|el2_ifu>io_dma_iccm_req",
|
||||
"~el2_ifu|el2_ifu>io_dma_mem_write",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_core_ecc_disable",
|
||||
"~el2_ifu|el2_ifu>io_iccm_rd_data_ecc",
|
||||
"~el2_ifu|el2_ifu>io_exu_flush_final",
|
||||
"~el2_ifu|el2_ifu>io_ic_rd_hit",
|
||||
"~el2_ifu|el2_ifu>io_exu_flush_path_final",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_noredir_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_start_error",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_error",
|
||||
"~el2_ifu|el2_ifu>io_exu_i0_br_index_r",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_err_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_i0_commit_cmt",
|
||||
"~el2_ifu|el2_ifu>io_ic_rd_data",
|
||||
"~el2_ifu|el2_ifu>io_dec_i0_decode_d"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu|el2_ifu>io_ic_premux_data",
|
||||
"sources":[
|
||||
"~el2_ifu|el2_ifu>io_iccm_rd_data",
|
||||
"~el2_ifu|el2_ifu>io_exu_flush_final",
|
||||
"~el2_ifu|el2_ifu>io_ic_rd_hit",
|
||||
"~el2_ifu|el2_ifu>io_ifu_axi_rid",
|
||||
"~el2_ifu|el2_ifu>io_ifu_axi_rvalid",
|
||||
"~el2_ifu|el2_ifu>io_ifu_bus_clk_en",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_start_error",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_error",
|
||||
"~el2_ifu|el2_ifu>io_exu_i0_br_index_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu|el2_ifu>io_iccm_ready",
|
||||
"sources":[
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_core_ecc_disable",
|
||||
"~el2_ifu|el2_ifu>io_iccm_rd_data_ecc",
|
||||
"~el2_ifu|el2_ifu>io_exu_flush_final",
|
||||
|
|
@ -32,8 +92,8 @@
|
|||
"~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_start_error",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_error",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_start_error",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_error",
|
||||
"~el2_ifu|el2_ifu>io_exu_i0_br_index_r",
|
||||
"~el2_ifu|el2_ifu>io_dec_i0_decode_d",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_err_wb",
|
||||
|
|
@ -62,6 +122,58 @@
|
|||
"~el2_ifu|el2_ifu>io_dec_tlu_ic_diag_pkt_icache_rd_valid"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu|el2_ifu>io_iccm_dma_sb_error",
|
||||
"sources":[
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_core_ecc_disable",
|
||||
"~el2_ifu|el2_ifu>io_iccm_rd_data_ecc",
|
||||
"~el2_ifu|el2_ifu>io_exu_flush_final",
|
||||
"~el2_ifu|el2_ifu>io_ic_rd_hit",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_start_error",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_error",
|
||||
"~el2_ifu|el2_ifu>io_exu_i0_br_index_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu|el2_ifu>io_ifu_ic_error_start",
|
||||
"sources":[
|
||||
"~el2_ifu|el2_ifu>io_ic_eccerr",
|
||||
"~el2_ifu|el2_ifu>io_ic_tag_perr",
|
||||
"~el2_ifu|el2_ifu>io_ic_rd_hit",
|
||||
"~el2_ifu|el2_ifu>io_exu_flush_final",
|
||||
"~el2_ifu|el2_ifu>io_ifu_axi_rid",
|
||||
"~el2_ifu|el2_ifu>io_ifu_axi_rvalid",
|
||||
"~el2_ifu|el2_ifu>io_ifu_bus_clk_en",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_start_error",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_error",
|
||||
"~el2_ifu|el2_ifu>io_exu_i0_br_index_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu|el2_ifu>io_ic_sel_premux_data",
|
||||
"sources":[
|
||||
"~el2_ifu|el2_ifu>io_exu_flush_final",
|
||||
"~el2_ifu|el2_ifu>io_ic_rd_hit",
|
||||
"~el2_ifu|el2_ifu>io_ifu_axi_rid",
|
||||
"~el2_ifu|el2_ifu>io_ifu_axi_rvalid",
|
||||
"~el2_ifu|el2_ifu>io_ifu_bus_clk_en",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_start_error",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_error",
|
||||
"~el2_ifu|el2_ifu>io_exu_i0_br_index_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu|el2_ifu>io_iccm_wr_data",
|
||||
|
|
@ -77,8 +189,8 @@
|
|||
"~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_start_error",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_error",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_start_error",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_error",
|
||||
"~el2_ifu|el2_ifu>io_exu_i0_br_index_r",
|
||||
"~el2_ifu|el2_ifu>io_dec_i0_decode_d",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_err_wb",
|
||||
|
|
@ -101,173 +213,6 @@
|
|||
"~el2_ifu|el2_ifu>io_dec_tlu_ic_diag_pkt_icache_wr_valid"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu|el2_ifu>io_ifu_ic_error_start",
|
||||
"sources":[
|
||||
"~el2_ifu|el2_ifu>io_ic_eccerr",
|
||||
"~el2_ifu|el2_ifu>io_ic_tag_perr",
|
||||
"~el2_ifu|el2_ifu>io_ic_rd_hit",
|
||||
"~el2_ifu|el2_ifu>io_exu_flush_final",
|
||||
"~el2_ifu|el2_ifu>io_ifu_axi_rid",
|
||||
"~el2_ifu|el2_ifu>io_ifu_axi_rvalid",
|
||||
"~el2_ifu|el2_ifu>io_ifu_bus_clk_en",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_start_error",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_error",
|
||||
"~el2_ifu|el2_ifu>io_exu_i0_br_index_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu|el2_ifu>io_iccm_dma_ecc_error",
|
||||
"sources":[
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_core_ecc_disable",
|
||||
"~el2_ifu|el2_ifu>io_iccm_rd_data_ecc",
|
||||
"~el2_ifu|el2_ifu>io_exu_flush_final",
|
||||
"~el2_ifu|el2_ifu>io_ic_rd_hit",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_start_error",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_error",
|
||||
"~el2_ifu|el2_ifu>io_exu_i0_br_index_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu|el2_ifu>io_iccm_rden",
|
||||
"sources":[
|
||||
"~el2_ifu|el2_ifu>io_dma_iccm_req",
|
||||
"~el2_ifu|el2_ifu>io_dma_mem_write",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_core_ecc_disable",
|
||||
"~el2_ifu|el2_ifu>io_iccm_rd_data_ecc",
|
||||
"~el2_ifu|el2_ifu>io_exu_flush_final",
|
||||
"~el2_ifu|el2_ifu>io_ic_rd_hit",
|
||||
"~el2_ifu|el2_ifu>io_exu_flush_path_final",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_noredir_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_start_error",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_error",
|
||||
"~el2_ifu|el2_ifu>io_exu_i0_br_index_r",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_err_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_i0_commit_cmt",
|
||||
"~el2_ifu|el2_ifu>io_ic_rd_data",
|
||||
"~el2_ifu|el2_ifu>io_dec_i0_decode_d"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu|el2_ifu>io_ifu_pmu_instr_aligned",
|
||||
"sources":[
|
||||
"~el2_ifu|el2_ifu>io_dec_i0_decode_d"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu|el2_ifu>io_iccm_dma_sb_error",
|
||||
"sources":[
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_core_ecc_disable",
|
||||
"~el2_ifu|el2_ifu>io_iccm_rd_data_ecc",
|
||||
"~el2_ifu|el2_ifu>io_exu_flush_final",
|
||||
"~el2_ifu|el2_ifu>io_ic_rd_hit",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_start_error",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_error",
|
||||
"~el2_ifu|el2_ifu>io_exu_i0_br_index_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu|el2_ifu>io_ic_debug_tag_array",
|
||||
"sources":[
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_ic_diag_pkt_icache_dicawics"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu|el2_ifu>io_ic_premux_data",
|
||||
"sources":[
|
||||
"~el2_ifu|el2_ifu>io_iccm_rd_data",
|
||||
"~el2_ifu|el2_ifu>io_exu_flush_final",
|
||||
"~el2_ifu|el2_ifu>io_ic_rd_hit",
|
||||
"~el2_ifu|el2_ifu>io_ifu_axi_rid",
|
||||
"~el2_ifu|el2_ifu>io_ifu_axi_rvalid",
|
||||
"~el2_ifu|el2_ifu>io_ifu_bus_clk_en",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_start_error",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_error",
|
||||
"~el2_ifu|el2_ifu>io_exu_i0_br_index_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu|el2_ifu>io_ic_rw_addr",
|
||||
"sources":[
|
||||
"~el2_ifu|el2_ifu>io_exu_flush_path_final",
|
||||
"~el2_ifu|el2_ifu>io_exu_flush_final",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_start_error",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_error",
|
||||
"~el2_ifu|el2_ifu>io_exu_i0_br_index_r",
|
||||
"~el2_ifu|el2_ifu>io_ic_rd_hit",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu|el2_ifu>io_ifu_iccm_rd_ecc_single_err",
|
||||
"sources":[
|
||||
"~el2_ifu|el2_ifu>io_exu_flush_final",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_core_ecc_disable",
|
||||
"~el2_ifu|el2_ifu>io_iccm_rd_data_ecc",
|
||||
"~el2_ifu|el2_ifu>io_ic_rd_hit",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_start_error",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_error",
|
||||
"~el2_ifu|el2_ifu>io_exu_i0_br_index_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu|el2_ifu>io_ic_tag_valid",
|
||||
"sources":[
|
||||
"~el2_ifu|el2_ifu>io_exu_flush_final"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu|el2_ifu>io_ic_rd_en",
|
||||
"sources":[
|
||||
"~el2_ifu|el2_ifu>io_exu_flush_final",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_force_halt",
|
||||
"~el2_ifu|el2_ifu>io_ic_rd_hit",
|
||||
"~el2_ifu|el2_ifu>io_exu_flush_path_final",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_noredir_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_mrac_ff",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_start_error",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_error",
|
||||
"~el2_ifu|el2_ifu>io_exu_i0_br_index_r",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_err_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_i0_commit_cmt",
|
||||
"~el2_ifu|el2_ifu>io_ic_rd_data",
|
||||
"~el2_ifu|el2_ifu>io_dec_i0_decode_d"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu|el2_ifu>io_iccm_rw_addr",
|
||||
|
|
@ -283,8 +228,8 @@
|
|||
"~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_start_error",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_error",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_start_error",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_error",
|
||||
"~el2_ifu|el2_ifu>io_exu_i0_br_index_r",
|
||||
"~el2_ifu|el2_ifu>io_dec_i0_decode_d",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_err_wb",
|
||||
|
|
@ -294,15 +239,10 @@
|
|||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu|el2_ifu>io_ic_debug_wr_data",
|
||||
"sources":[
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_ic_diag_pkt_icache_wrdata"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu|el2_ifu>io_iccm_ready",
|
||||
"sink":"~el2_ifu|el2_ifu>io_iccm_wren",
|
||||
"sources":[
|
||||
"~el2_ifu|el2_ifu>io_dma_mem_write",
|
||||
"~el2_ifu|el2_ifu>io_dma_iccm_req",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_core_ecc_disable",
|
||||
"~el2_ifu|el2_ifu>io_iccm_rd_data_ecc",
|
||||
"~el2_ifu|el2_ifu>io_exu_flush_final",
|
||||
|
|
@ -312,8 +252,8 @@
|
|||
"~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_start_error",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_error",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_start_error",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_error",
|
||||
"~el2_ifu|el2_ifu>io_exu_i0_br_index_r",
|
||||
"~el2_ifu|el2_ifu>io_dec_i0_decode_d",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_err_wb",
|
||||
|
|
@ -323,21 +263,81 @@
|
|||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu|el2_ifu>io_ic_sel_premux_data",
|
||||
"sink":"~el2_ifu|el2_ifu>io_ifu_pmu_instr_aligned",
|
||||
"sources":[
|
||||
"~el2_ifu|el2_ifu>io_dec_i0_decode_d"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu|el2_ifu>io_ifu_iccm_rd_ecc_single_err",
|
||||
"sources":[
|
||||
"~el2_ifu|el2_ifu>io_exu_flush_final",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_core_ecc_disable",
|
||||
"~el2_ifu|el2_ifu>io_iccm_rd_data_ecc",
|
||||
"~el2_ifu|el2_ifu>io_ic_rd_hit",
|
||||
"~el2_ifu|el2_ifu>io_ifu_axi_rid",
|
||||
"~el2_ifu|el2_ifu>io_ifu_axi_rvalid",
|
||||
"~el2_ifu|el2_ifu>io_ifu_bus_clk_en",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_start_error",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_br_error",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_start_error",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_error",
|
||||
"~el2_ifu|el2_ifu>io_exu_i0_br_index_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu|el2_ifu>io_ic_debug_tag_array",
|
||||
"sources":[
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_ic_diag_pkt_icache_dicawics"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu|el2_ifu>io_ifu_pmu_fetch_stall",
|
||||
"sources":[
|
||||
"~el2_ifu|el2_ifu>io_exu_flush_final",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_err_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_i0_commit_cmt",
|
||||
"~el2_ifu|el2_ifu>io_ic_rd_data",
|
||||
"~el2_ifu|el2_ifu>io_dec_i0_decode_d",
|
||||
"~el2_ifu|el2_ifu>io_ic_rd_hit",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_start_error",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_error",
|
||||
"~el2_ifu|el2_ifu>io_exu_i0_br_index_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu|el2_ifu>io_ic_tag_valid",
|
||||
"sources":[
|
||||
"~el2_ifu|el2_ifu>io_exu_flush_final"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu|el2_ifu>io_ic_rw_addr",
|
||||
"sources":[
|
||||
"~el2_ifu|el2_ifu>io_exu_flush_path_final",
|
||||
"~el2_ifu|el2_ifu>io_exu_flush_final",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_start_error",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_error",
|
||||
"~el2_ifu|el2_ifu>io_exu_i0_br_index_r",
|
||||
"~el2_ifu|el2_ifu>io_ic_rd_hit",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu|el2_ifu>io_ic_debug_wr_data",
|
||||
"sources":[
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_ic_diag_pkt_icache_wrdata"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.EmitCircuitAnnotation",
|
||||
"emitter":"firrtl.VerilogEmitter"
|
||||
|
|
|
|||
1152
el2_ifu.fir
1152
el2_ifu.fir
File diff suppressed because it is too large
Load Diff
|
|
@ -2284,7 +2284,7 @@ circuit el2_ifu_aln_ctl :
|
|||
module el2_ifu_aln_ctl :
|
||||
input clock : Clock
|
||||
input reset : AsyncReset
|
||||
output io : {flip scan_mode : UInt<1>, flip active_clk : Clock, flip ifu_async_error_start : UInt<1>, flip iccm_rd_ecc_double_err : UInt<1>, flip ic_access_fault_f : UInt<1>, flip ic_access_fault_type_f : UInt<2>, flip ifu_bp_fghr_f : UInt<8>, flip ifu_bp_btb_target_f : UInt<31>, flip ifu_bp_poffset_f : UInt<12>, flip ifu_bp_hist0_f : UInt<2>, flip ifu_bp_hist1_f : UInt<2>, flip ifu_bp_pc4_f : UInt<2>, flip ifu_bp_way_f : UInt<2>, flip ifu_bp_valid_f : UInt<2>, flip ifu_bp_ret_f : UInt<2>, flip exu_flush_final : UInt<1>, flip dec_i0_decode_d : UInt<1>, flip ifu_fetch_data_f : UInt<32>, flip ifu_fetch_val : UInt<2>, flip ifu_fetch_pc : UInt<31>, ifu_i0_valid : UInt<1>, ifu_i0_icaf : UInt<1>, ifu_i0_icaf_type : UInt<2>, ifu_i0_icaf_f1 : UInt<1>, ifu_i0_dbecc : UInt<1>, ifu_i0_instr : UInt<32>, ifu_i0_pc : UInt<31>, ifu_i0_pc4 : UInt<1>, ifu_fb_consume1 : UInt<1>, ifu_fb_consume2 : UInt<1>, ifu_i0_bp_index : UInt<8>, ifu_i0_bp_fghr : UInt<8>, ifu_i0_bp_btag : UInt<5>, ifu_pmu_instr_aligned : UInt<1>, ifu_i0_cinst : UInt<16>, i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}}
|
||||
output io : {flip scan_mode : UInt<1>, flip active_clk : Clock, flip ifu_async_error_start : UInt<1>, flip iccm_rd_ecc_double_err : UInt<1>, flip ic_access_fault_f : UInt<1>, flip ic_access_fault_type_f : UInt<2>, flip ifu_bp_fghr_f : UInt<8>, flip ifu_bp_btb_target_f : UInt<31>, flip ifu_bp_poffset_f : UInt<12>, flip ifu_bp_hist0_f : UInt<2>, flip ifu_bp_hist1_f : UInt<2>, flip ifu_bp_pc4_f : UInt<2>, flip ifu_bp_way_f : UInt<2>, flip ifu_bp_valid_f : UInt<2>, flip ifu_bp_ret_f : UInt<2>, flip exu_flush_final : UInt<1>, flip dec_i0_decode_d : UInt<1>, flip ifu_fetch_data_f : UInt<32>, flip ifu_fetch_val : UInt<2>, flip ifu_fetch_pc : UInt<31>, ifu_i0_valid : UInt<1>, ifu_i0_icaf : UInt<1>, ifu_i0_icaf_type : UInt<2>, ifu_i0_icaf_f1 : UInt<1>, ifu_i0_dbecc : UInt<1>, ifu_i0_instr : UInt<32>, ifu_i0_pc : UInt<31>, ifu_i0_pc4 : UInt<1>, ifu_fb_consume1 : UInt<1>, ifu_fb_consume2 : UInt<1>, ifu_i0_bp_index : UInt<8>, ifu_i0_bp_fghr : UInt<8>, ifu_i0_bp_btag : UInt<5>, ifu_pmu_instr_aligned : UInt<1>, ifu_i0_cinst : UInt<16>, i0_brp : {valid : UInt<1>, bits : {valid : UInt<1>, toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}}
|
||||
|
||||
io.ifu_i0_valid <= UInt<1>("h00") @[el2_ifu_aln_ctl.scala 47:19]
|
||||
io.ifu_i0_icaf <= UInt<1>("h00") @[el2_ifu_aln_ctl.scala 48:18]
|
||||
|
|
|
|||
File diff suppressed because one or more lines are too long
1588
el2_swerv_wrapper.v
1588
el2_swerv_wrapper.v
File diff suppressed because it is too large
Load Diff
|
|
@ -96,7 +96,7 @@ class el2_dec_IO extends Bundle with el2_lib {
|
|||
|
||||
val lsu_idle_any = Input(Bool()) // lsu idle for halting
|
||||
|
||||
val i0_brp = Input(new el2_br_pkt_t) // branch packet
|
||||
val i0_brp = Flipped(Valid(new el2_br_pkt_t)) // branch packet
|
||||
val ifu_i0_bp_index = Input(UInt((BTB_ADDR_HI-BTB_ADDR_LO+1).W)) // BP index
|
||||
val ifu_i0_bp_fghr = Input(UInt(BHT_GHR_SIZE.W)) // BP FGHR
|
||||
val ifu_i0_bp_btag = Input(UInt(BTB_BTAG_SIZE.W)) // BP tag
|
||||
|
|
@ -223,7 +223,7 @@ class el2_dec_IO extends Bundle with el2_lib {
|
|||
|
||||
val pred_correct_npc_x = Output(UInt(31.W)) // npc if prediction is correct at e2 stage
|
||||
|
||||
val dec_tlu_br0_r_pkt = Output(new el2_br_tlu_pkt_t) // slot 0 branch predictor update packet
|
||||
val dec_tlu_br0_r_pkt = Valid(new el2_br_tlu_pkt_t) // slot 0 branch predictor update packet
|
||||
|
||||
val dec_tlu_perfcnt0 = Output(Bool()) // toggles when slot0 perf counter 0 has an event inc
|
||||
val dec_tlu_perfcnt1 = Output(Bool()) // toggles when slot0 perf counter 1 has an event inc
|
||||
|
|
|
|||
|
|
@ -35,7 +35,7 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
|
|||
val dec_i0_icaf_f1_d = Input(Bool()) // i0 instruction access fault at decode for f1 fetch group
|
||||
val dec_i0_icaf_type_d = Input(UInt(2.W)) // i0 instruction access fault type
|
||||
val dec_i0_dbecc_d = Input(Bool()) // icache/iccm double-bit error
|
||||
val dec_i0_brp = Input(new el2_br_pkt_t) // branch packet
|
||||
val dec_i0_brp = Flipped(Valid(new el2_br_pkt_t)) // branch packet
|
||||
val dec_i0_bp_index = Input(UInt(((BTB_ADDR_HI-BTB_ADDR_LO)+1).W)) // i0 branch index
|
||||
val dec_i0_bp_fghr = Input(UInt(BHT_GHR_SIZE.W)) // BP FGHR
|
||||
val dec_i0_bp_btag = Input(UInt(BTB_BTAG_SIZE.W)) // BP tag
|
||||
|
|
@ -230,24 +230,24 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
|
|||
io.dec_i0_predict_p_d.bits.pcall := i0_pcall // don't mark as pcall if branch error
|
||||
io.dec_i0_predict_p_d.bits.pja := i0_pja
|
||||
io.dec_i0_predict_p_d.bits.pret := i0_pret
|
||||
io.dec_i0_predict_p_d.bits.prett := io.dec_i0_brp.prett
|
||||
io.dec_i0_predict_p_d.bits.prett := io.dec_i0_brp.bits.prett
|
||||
io.dec_i0_predict_p_d.bits.pc4 := io.dec_i0_pc4_d
|
||||
io.dec_i0_predict_p_d.bits.hist := io.dec_i0_brp.hist
|
||||
io.dec_i0_predict_p_d.bits.hist := io.dec_i0_brp.bits.hist
|
||||
io.dec_i0_predict_p_d.valid := i0_brp_valid & i0_legal_decode_d
|
||||
val i0_notbr_error = i0_brp_valid & !(i0_dp_raw.condbr | i0_pcall_raw | i0_pja_raw | i0_pret_raw)
|
||||
|
||||
// no toffset error for a pret
|
||||
val i0_br_toffset_error = i0_brp_valid & io.dec_i0_brp.hist(1) & (io.dec_i0_brp.toffset =/= i0_br_offset) & !i0_pret_raw
|
||||
val i0_ret_error = i0_brp_valid & io.dec_i0_brp.ret & !i0_pret_raw;
|
||||
val i0_br_error = io.dec_i0_brp.br_error | i0_notbr_error | i0_br_toffset_error | i0_ret_error
|
||||
val i0_br_toffset_error = i0_brp_valid & io.dec_i0_brp.bits.hist(1) & (io.dec_i0_brp.bits.toffset =/= i0_br_offset) & !i0_pret_raw
|
||||
val i0_ret_error = i0_brp_valid & io.dec_i0_brp.bits.ret & !i0_pret_raw;
|
||||
val i0_br_error = io.dec_i0_brp.bits.br_error | i0_notbr_error | i0_br_toffset_error | i0_ret_error
|
||||
io.dec_i0_predict_p_d.bits.br_error := i0_br_error & i0_legal_decode_d & !leak1_mode
|
||||
io.dec_i0_predict_p_d.bits.br_start_error := io.dec_i0_brp.br_start_error & i0_legal_decode_d & !leak1_mode
|
||||
io.dec_i0_predict_p_d.bits.br_start_error := io.dec_i0_brp.bits.br_start_error & i0_legal_decode_d & !leak1_mode
|
||||
io.i0_predict_index_d := io.dec_i0_bp_index
|
||||
io.i0_predict_btag_d := io.dec_i0_bp_btag
|
||||
val i0_br_error_all = (i0_br_error | io.dec_i0_brp.br_start_error) & !leak1_mode
|
||||
val i0_br_error_all = (i0_br_error | io.dec_i0_brp.bits.br_start_error) & !leak1_mode
|
||||
io.dec_i0_predict_p_d.bits.toffset := i0_br_offset
|
||||
io.i0_predict_fghr_d := io.dec_i0_bp_fghr
|
||||
io.dec_i0_predict_p_d.bits.way := io.dec_i0_brp.way
|
||||
io.dec_i0_predict_p_d.bits.way := io.dec_i0_brp.bits.way
|
||||
// end
|
||||
|
||||
// on br error turn anything into a nop
|
||||
|
|
@ -273,8 +273,8 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
|
|||
// branches that can be predicted
|
||||
val i0_predict_br = i0_dp.condbr | i0_pcall | i0_pja | i0_pret;
|
||||
|
||||
val i0_predict_nt = !(io.dec_i0_brp.hist(1) & i0_brp_valid) & i0_predict_br
|
||||
val i0_predict_t = (io.dec_i0_brp.hist(1) & i0_brp_valid) & i0_predict_br
|
||||
val i0_predict_nt = !(io.dec_i0_brp.bits.hist(1) & i0_brp_valid) & i0_predict_br
|
||||
val i0_predict_t = (io.dec_i0_brp.bits.hist(1) & i0_brp_valid) & i0_predict_br
|
||||
val i0_ap_pc2 = !io.dec_i0_pc4_d
|
||||
val i0_ap_pc4 = io.dec_i0_pc4_d
|
||||
io.i0_ap.predict_nt := i0_predict_nt
|
||||
|
|
|
|||
|
|
@ -63,7 +63,7 @@ class el2_dec_ib_ctl_IO extends Bundle with param{
|
|||
val dbg_cmd_write =Input(UInt(1.W)) // dbg cmd is write
|
||||
val dbg_cmd_type =Input(UInt(2.W)) // dbg type
|
||||
val dbg_cmd_addr =Input(UInt(32.W)) // expand to 31:0
|
||||
val i0_brp =Input(new el2_br_pkt_t) // i0 branch packet from aligner
|
||||
val i0_brp =Flipped(Valid(new el2_br_pkt_t)) // i0 branch packet from aligner
|
||||
val ifu_i0_bp_index =Input(UInt(((BTB_ADDR_HI-BTB_ADDR_LO)+1).W)) // BP index(Changed size)
|
||||
val ifu_i0_bp_fghr =Input(UInt((BHT_GHR_SIZE).W)) // BP FGHR
|
||||
val ifu_i0_bp_btag =Input(UInt((BTB_BTAG_SIZE).W)) // BP tag
|
||||
|
|
@ -81,7 +81,7 @@ class el2_dec_ib_ctl_IO extends Bundle with param{
|
|||
val dec_i0_instr_d =Output(UInt(32.W)) // i0 inst at decode
|
||||
val dec_i0_pc_d =Output(UInt(31.W)) // i0 pc at decode
|
||||
val dec_i0_pc4_d =Output(UInt(1.W)) // i0 is 4B inst else 2B
|
||||
val dec_i0_brp =Output(new el2_br_pkt_t) // i0 branch packet at decode
|
||||
val dec_i0_brp =Valid(new el2_br_pkt_t) // i0 branch packet at decode
|
||||
val dec_i0_bp_index =Output(UInt(((BTB_ADDR_HI-BTB_ADDR_LO)+1).W)) // i0 branch index
|
||||
val dec_i0_bp_fghr =Output(UInt(BHT_GHR_SIZE.W)) // BP FGHR
|
||||
val dec_i0_bp_btag =Output(UInt(BTB_BTAG_SIZE.W)) // BP tag
|
||||
|
|
|
|||
|
|
@ -188,7 +188,7 @@ class el2_dec_tlu_ctl_IO extends Bundle with el2_lib {
|
|||
val dec_tlu_meipt = Output(UInt(4.W)) // to PIC
|
||||
val dec_csr_rddata_d = Output(UInt(32.W)) // csr read data at wb
|
||||
val dec_csr_legal_d = Output(UInt(1.W)) // csr indicates legal operation
|
||||
val dec_tlu_br0_r_pkt = Output(new el2_br_tlu_pkt_t) // branch pkt to bp
|
||||
val dec_tlu_br0_r_pkt = Valid(new el2_br_tlu_pkt_t) // branch pkt to bp
|
||||
val dec_tlu_i0_kill_writeb_wb = Output(UInt(1.W)) // I0 is flushed, don't writeback any results to arch state
|
||||
val dec_tlu_flush_lower_wb = Output(UInt(1.W)) // commit has a flush (exception, int, mispredict at e4)
|
||||
val dec_tlu_i0_commit_cmt = Output(UInt(1.W)) // committed an instruction
|
||||
|
|
@ -727,12 +727,12 @@ class el2_dec_tlu_ctl extends Module with el2_lib with RequireAsyncReset with CS
|
|||
val dec_tlu_br0_v_r = io.exu_i0_br_valid_r & io.dec_tlu_i0_valid_r & ~tlu_flush_lower_r_d1 & (~io.exu_i0_br_mp_r | ~io.exu_pmu_i0_br_ataken)
|
||||
|
||||
|
||||
io.dec_tlu_br0_r_pkt.hist := io.exu_i0_br_hist_r
|
||||
io.dec_tlu_br0_r_pkt.br_error := dec_tlu_br0_error_r
|
||||
io.dec_tlu_br0_r_pkt.br_start_error := dec_tlu_br0_start_error_r
|
||||
io.dec_tlu_br0_r_pkt.bits.hist := io.exu_i0_br_hist_r
|
||||
io.dec_tlu_br0_r_pkt.bits.br_error := dec_tlu_br0_error_r
|
||||
io.dec_tlu_br0_r_pkt.bits.br_start_error := dec_tlu_br0_start_error_r
|
||||
io.dec_tlu_br0_r_pkt.valid := dec_tlu_br0_v_r
|
||||
io.dec_tlu_br0_r_pkt.way := io.exu_i0_br_way_r
|
||||
io.dec_tlu_br0_r_pkt.middle := io.exu_i0_br_middle_r
|
||||
io.dec_tlu_br0_r_pkt.bits.way := io.exu_i0_br_way_r
|
||||
io.dec_tlu_br0_r_pkt.bits.middle := io.exu_i0_br_middle_r
|
||||
|
||||
|
||||
ebreak_r := (io.dec_tlu_packet_r.pmu_i0_itype === EBREAK) & io.dec_tlu_i0_valid_r & ~i0_trigger_hit_r & ~dcsr(DCSR_EBREAKM) & ~rfpc_i0_r
|
||||
|
|
|
|||
|
|
@ -384,7 +384,7 @@ class el2_swerv extends Module with RequireAsyncReset with el2_lib {
|
|||
ifu.io.exu_mp_fghr := exu.io.exu_mp_fghr
|
||||
ifu.io.exu_mp_index := exu.io.exu_mp_index
|
||||
ifu.io.exu_mp_btag := exu.io.exu_mp_btag
|
||||
ifu.io.dec_tlu_br0_r_pkt := dec.io.dec_tlu_br0_r_pkt
|
||||
ifu.io.dec_tlu_br0_r_pkt <> dec.io.dec_tlu_br0_r_pkt
|
||||
ifu.io.exu_i0_br_fghr_r := exu.io.exu_i0_br_fghr_r
|
||||
ifu.io.exu_i0_br_index_r := exu.io.exu_i0_br_index_r
|
||||
ifu.io.dec_tlu_flush_lower_wb := dec.io.dec_tlu_flush_lower_r
|
||||
|
|
|
|||
|
|
@ -122,7 +122,7 @@ class el2_ifu extends Module with el2_lib with RequireAsyncReset {
|
|||
val ifu_i0_pc4 = Output(Bool())
|
||||
val ifu_miss_state_idle = Output(Bool())
|
||||
// Aligner branch data
|
||||
val i0_brp = Output(new el2_br_pkt_t)
|
||||
val i0_brp = Valid(new el2_br_pkt_t)
|
||||
val ifu_i0_bp_index = Output(UInt((BTB_ADDR_HI-BTB_ADDR_LO+1).W))
|
||||
val ifu_i0_bp_fghr = Output(UInt(BHT_GHR_SIZE.W))
|
||||
val ifu_i0_bp_btag = Output(UInt(BTB_BTAG_SIZE.W))
|
||||
|
|
@ -132,7 +132,7 @@ class el2_ifu extends Module with el2_lib with RequireAsyncReset {
|
|||
val exu_mp_fghr = Input(UInt(BHT_GHR_SIZE.W))
|
||||
val exu_mp_index = Input(UInt((BTB_ADDR_HI-BTB_ADDR_LO+1).W)) // Misprediction index
|
||||
val exu_mp_btag = Input(UInt(BTB_BTAG_SIZE.W))
|
||||
val dec_tlu_br0_r_pkt = Input(new el2_br_tlu_pkt_t)
|
||||
val dec_tlu_br0_r_pkt = Flipped(Valid(new el2_br_tlu_pkt_t))
|
||||
val exu_i0_br_fghr_r = Input(UInt(BHT_GHR_SIZE.W)) // Updated GHR from the exu
|
||||
val exu_i0_br_index_r = Input(UInt((BTB_ADDR_HI-BTB_ADDR_LO+1).W))
|
||||
val dec_tlu_flush_lower_wb = Input(Bool())
|
||||
|
|
@ -328,7 +328,7 @@ class el2_ifu extends Module with el2_lib with RequireAsyncReset {
|
|||
io.ifu_i0_pc4 := aln_ctl_ch.io.ifu_i0_pc4
|
||||
io.ifu_miss_state_idle := mem_ctl_ch.io.ifu_miss_state_idle
|
||||
// Aligner branch data
|
||||
io.i0_brp <> aln_ctl_ch.io.i0_brp
|
||||
io.i0_brp := aln_ctl_ch.io.i0_brp
|
||||
io.ifu_i0_bp_index := aln_ctl_ch.io.ifu_i0_bp_index
|
||||
io.ifu_i0_bp_fghr := aln_ctl_ch.io.ifu_i0_bp_fghr
|
||||
io.ifu_i0_bp_btag := aln_ctl_ch.io.ifu_i0_bp_btag
|
||||
|
|
|
|||
|
|
@ -42,7 +42,7 @@ class el2_ifu_aln_ctl extends Module with el2_lib with RequireAsyncReset {
|
|||
val ifu_i0_bp_btag = Output(UInt(BTB_BTAG_SIZE.W))
|
||||
val ifu_pmu_instr_aligned = Output(Bool())
|
||||
val ifu_i0_cinst = Output(UInt(16.W))
|
||||
val i0_brp = Output(new el2_br_pkt_t)
|
||||
val i0_brp = Valid(new el2_br_pkt_t)
|
||||
})
|
||||
io.ifu_i0_valid := 0.U
|
||||
io.ifu_i0_icaf := 0.U
|
||||
|
|
@ -377,25 +377,25 @@ class el2_ifu_aln_ctl extends Module with el2_lib with RequireAsyncReset {
|
|||
|
||||
io.i0_brp.valid :=(first2B & alignbrend(0)) | (first4B & alignbrend(1)) | (first4B & alignval(1) & alignbrend(0))
|
||||
|
||||
io.i0_brp.ret := (first2B & alignret(0)) | (first4B & alignret(1))
|
||||
io.i0_brp.bits.ret := (first2B & alignret(0)) | (first4B & alignret(1))
|
||||
|
||||
val i0_brp_pc4 = (first2B & alignpc4(0)) | (first4B & alignpc4(1))
|
||||
|
||||
io.i0_brp.way := Mux((first2B | alignbrend(0)).asBool, alignway(0), alignway(1))
|
||||
io.i0_brp.bits.way := Mux((first2B | alignbrend(0)).asBool, alignway(0), alignway(1))
|
||||
|
||||
io.i0_brp.hist := Cat((first2B & alignhist1(0)) | (first4B & alignhist1(1)),
|
||||
io.i0_brp.bits.hist := Cat((first2B & alignhist1(0)) | (first4B & alignhist1(1)),
|
||||
(first2B & alignhist0(0)) | (first4B & alignhist0(1)))
|
||||
|
||||
val i0_ends_f1 = first4B & alignfromf1
|
||||
io.i0_brp.toffset := Mux(i0_ends_f1.asBool, f1poffset, f0poffset)
|
||||
io.i0_brp.bits.toffset := Mux(i0_ends_f1.asBool, f1poffset, f0poffset)
|
||||
|
||||
io.i0_brp.prett := Mux(i0_ends_f1.asBool, f1prett, f0prett)
|
||||
io.i0_brp.bits.prett := Mux(i0_ends_f1.asBool, f1prett, f0prett)
|
||||
|
||||
io.i0_brp.br_start_error := (first4B & alignval(1) & alignbrend(0))
|
||||
io.i0_brp.bits.br_start_error := (first4B & alignval(1) & alignbrend(0))
|
||||
|
||||
io.i0_brp.bank := Mux((first2B | alignbrend(0)).asBool, firstpc(0), secondpc(0))
|
||||
io.i0_brp.bits.bank := Mux((first2B | alignbrend(0)).asBool, firstpc(0), secondpc(0))
|
||||
|
||||
io.i0_brp.br_error := (io.i0_brp.valid & i0_brp_pc4 & first2B) | (io.i0_brp.valid & !i0_brp_pc4 & first4B)
|
||||
io.i0_brp.bits.br_error := (io.i0_brp.valid & i0_brp_pc4 & first2B) | (io.i0_brp.valid & !i0_brp_pc4 & first4B)
|
||||
|
||||
io.ifu_i0_bp_index := Mux((first2B | alignbrend(0)).asBool, firstpc_hash, secondpc_hash)
|
||||
|
||||
|
|
|
|||
|
|
@ -13,7 +13,7 @@ class el2_ifu_bp_ctl extends Module with el2_lib with RequireAsyncReset {
|
|||
val ifc_fetch_addr_f = Input(UInt(31.W))
|
||||
val ifc_fetch_req_f = Input(Bool()) // Fetch request generated by the IFC
|
||||
// Decode packet containing information if its a brnach or not
|
||||
val dec_tlu_br0_r_pkt = Input(new el2_br_tlu_pkt_t)
|
||||
val dec_tlu_br0_r_pkt = Flipped(Valid(new el2_br_tlu_pkt_t))
|
||||
val exu_i0_br_fghr_r = Input(UInt(BHT_GHR_SIZE.W)) // Updated GHR from the exu
|
||||
val exu_i0_br_index_r = Input(UInt((BTB_ADDR_HI-BTB_ADDR_LO+1).W)) // Way from where the btb got a hit
|
||||
val dec_tlu_flush_lower_wb = Input(Bool())
|
||||
|
|
@ -83,12 +83,12 @@ class el2_ifu_bp_ctl extends Module with el2_lib with RequireAsyncReset {
|
|||
|
||||
// Its a commit or update packet
|
||||
val dec_tlu_br0_v_wb = io.dec_tlu_br0_r_pkt.valid
|
||||
val dec_tlu_br0_hist_wb = io.dec_tlu_br0_r_pkt.hist
|
||||
val dec_tlu_br0_hist_wb = io.dec_tlu_br0_r_pkt.bits.hist
|
||||
val dec_tlu_br0_addr_wb = io.exu_i0_br_index_r
|
||||
val dec_tlu_br0_error_wb = io.dec_tlu_br0_r_pkt.br_error
|
||||
val dec_tlu_br0_middle_wb = io.dec_tlu_br0_r_pkt.middle
|
||||
val dec_tlu_br0_way_wb = io.dec_tlu_br0_r_pkt.way
|
||||
val dec_tlu_br0_start_error_wb = io.dec_tlu_br0_r_pkt.br_start_error
|
||||
val dec_tlu_br0_error_wb = io.dec_tlu_br0_r_pkt.bits.br_error
|
||||
val dec_tlu_br0_middle_wb = io.dec_tlu_br0_r_pkt.bits.middle
|
||||
val dec_tlu_br0_way_wb = io.dec_tlu_br0_r_pkt.bits.way
|
||||
val dec_tlu_br0_start_error_wb = io.dec_tlu_br0_r_pkt.bits.br_start_error
|
||||
val exu_i0_br_fghr_wb = io.exu_i0_br_fghr_r
|
||||
|
||||
dec_tlu_error_wb := dec_tlu_br0_start_error_wb | dec_tlu_br0_error_wb
|
||||
|
|
|
|||
|
|
@ -49,7 +49,7 @@ class el2_rets_pkt_t extends Bundle {
|
|||
}
|
||||
|
||||
class el2_br_pkt_t extends Bundle {
|
||||
val valid = UInt(1.W)
|
||||
// val valid = UInt(1.W)
|
||||
val toffset = UInt(12.W)
|
||||
val hist = UInt(2.W)
|
||||
val br_error = UInt(1.W)
|
||||
|
|
@ -62,7 +62,7 @@ class el2_br_pkt_t extends Bundle {
|
|||
|
||||
|
||||
class el2_br_tlu_pkt_t extends Bundle {
|
||||
val valid = UInt(1.W)
|
||||
// val valid = UInt(1.W)
|
||||
val hist = UInt(2.W)
|
||||
val br_error = UInt(1.W)
|
||||
val br_start_error = UInt(1.W)
|
||||
|
|
|
|||
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Reference in New Issue