Bus-buffer testing start
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waleed-lm
parent
1cdcb71e7e
commit
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2824
el2_dec_decode_ctl.v
2824
el2_dec_decode_ctl.v
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[
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_dec_gpr_ctl|el2_dec_gpr_ctl>io_rd1",
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"sources":[
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"~el2_dec_gpr_ctl|el2_dec_gpr_ctl>io_raddr1"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_dec_gpr_ctl|el2_dec_gpr_ctl>io_rd0",
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"sources":[
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"~el2_dec_gpr_ctl|el2_dec_gpr_ctl>io_raddr0"
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]
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},
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{
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"class":"firrtl.EmitCircuitAnnotation",
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"emitter":"firrtl.VerilogEmitter"
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},
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{
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||||
"class":"firrtl.transforms.BlackBoxResourceAnno",
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"target":"el2_dec_gpr_ctl.TEC_RV_ICG",
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"resourceId":"/vsrc/TEC_RV_ICG.v"
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},
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{
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"class":"firrtl.options.TargetDirAnnotation",
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"directory":"."
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},
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{
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"class":"firrtl.options.OutputAnnotationFileAnnotation",
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"file":"el2_dec_gpr_ctl"
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},
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{
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"class":"firrtl.transforms.BlackBoxTargetDirAnno",
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"targetDir":"."
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}
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]
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@ -0,0 +1,183 @@
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[
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_debug_wdata_rs1_d",
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"sources":[
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"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dbg_cmd_write",
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"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dbg_cmd_type",
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"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dbg_cmd_valid"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_i0_brp_ret",
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"sources":[
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"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_i0_brp_ret"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_i0_dbecc_d",
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"sources":[
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"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_ifu_i0_dbecc"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_i0_brp_br_error",
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"sources":[
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"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_i0_brp_br_error"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_i0_pc_d",
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"sources":[
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"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_ifu_i0_pc"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_i0_brp_toffset",
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"sources":[
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"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_i0_brp_toffset"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_i0_icaf_f1_d",
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"sources":[
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"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_ifu_i0_icaf_f1"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_i0_bp_btag",
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"sources":[
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"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_ifu_i0_bp_btag"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_i0_brp_way",
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"sources":[
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"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_i0_brp_way"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_i0_pc4_d",
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"sources":[
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"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_ifu_i0_pc4"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_i0_brp_hist",
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"sources":[
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"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_i0_brp_hist"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_ib0_valid_d",
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"sources":[
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"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_ifu_i0_valid",
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"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dbg_cmd_valid",
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"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dbg_cmd_type"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_i0_instr_d",
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"sources":[
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"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_ifu_i0_instr",
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"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dbg_cmd_valid",
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"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dbg_cmd_type",
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"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dbg_cmd_addr",
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"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dbg_cmd_write"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_i0_brp_br_start_error",
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"sources":[
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"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_i0_brp_br_start_error"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_i0_bp_fghr",
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"sources":[
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"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_ifu_i0_bp_fghr"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_i0_brp_prett",
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"sources":[
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"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_i0_brp_prett"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_i0_brp_bank",
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"sources":[
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"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_i0_brp_bank"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_i0_icaf_d",
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"sources":[
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"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_ifu_i0_icaf"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_i0_bp_index",
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"sources":[
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"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_ifu_i0_bp_index"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_i0_icaf_type_d",
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"sources":[
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"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_ifu_i0_icaf_type"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_i0_brp_valid",
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"sources":[
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"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_i0_brp_valid"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dec_debug_fence_d",
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"sources":[
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"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dbg_cmd_write",
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"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dbg_cmd_type",
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"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dbg_cmd_addr",
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"~el2_dec_ib_ctl|el2_dec_ib_ctl>io_dbg_cmd_valid"
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]
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||||
},
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||||
{
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||||
"class":"firrtl.EmitCircuitAnnotation",
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||||
"emitter":"firrtl.VerilogEmitter"
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||||
},
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||||
{
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||||
"class":"firrtl.options.TargetDirAnnotation",
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||||
"directory":"."
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},
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||||
{
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||||
"class":"firrtl.options.OutputAnnotationFileAnnotation",
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||||
"file":"el2_dec_ib_ctl"
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||||
},
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||||
{
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||||
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
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||||
"targetDir":"."
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}
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||||
]
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@ -0,0 +1,71 @@
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;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
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circuit el2_dec_ib_ctl :
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module el2_dec_ib_ctl :
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input clock : Clock
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input reset : UInt<1>
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output io : {flip dbg_cmd_valid : UInt<1>, flip dbg_cmd_write : UInt<1>, flip dbg_cmd_type : UInt<2>, flip dbg_cmd_addr : UInt<32>, flip i0_brp : {valid : UInt<1>, toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}, flip ifu_i0_bp_index : UInt<8>, flip ifu_i0_bp_fghr : UInt<8>, flip ifu_i0_bp_btag : UInt<5>, flip ifu_i0_pc4 : UInt<1>, flip ifu_i0_valid : UInt<1>, flip ifu_i0_icaf : UInt<1>, flip ifu_i0_icaf_type : UInt<2>, flip ifu_i0_icaf_f1 : UInt<1>, flip ifu_i0_dbecc : UInt<1>, flip ifu_i0_instr : UInt<32>, flip ifu_i0_pc : UInt<31>, dec_ib0_valid_d : UInt<1>, dec_i0_icaf_type_d : UInt<2>, dec_i0_instr_d : UInt<32>, dec_i0_pc_d : UInt<31>, dec_i0_pc4_d : UInt<1>, dec_i0_brp : {valid : UInt<1>, toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}, dec_i0_bp_index : UInt<8>, dec_i0_bp_fghr : UInt<8>, dec_i0_bp_btag : UInt<5>, dec_i0_icaf_d : UInt<1>, dec_i0_icaf_f1_d : UInt<1>, dec_i0_dbecc_d : UInt<1>, dec_debug_wdata_rs1_d : UInt<1>, dec_debug_fence_d : UInt<1>}
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io.dec_i0_icaf_f1_d <= io.ifu_i0_icaf_f1 @[el2_dec_ib_ctl.scala 43:31]
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io.dec_i0_dbecc_d <= io.ifu_i0_dbecc @[el2_dec_ib_ctl.scala 44:31]
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io.dec_i0_icaf_d <= io.ifu_i0_icaf @[el2_dec_ib_ctl.scala 45:31]
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io.dec_i0_pc_d <= io.ifu_i0_pc @[el2_dec_ib_ctl.scala 46:31]
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io.dec_i0_pc4_d <= io.ifu_i0_pc4 @[el2_dec_ib_ctl.scala 47:31]
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io.dec_i0_icaf_type_d <= io.ifu_i0_icaf_type @[el2_dec_ib_ctl.scala 48:31]
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io.dec_i0_brp.ret <= io.i0_brp.ret @[el2_dec_ib_ctl.scala 49:31]
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io.dec_i0_brp.way <= io.i0_brp.way @[el2_dec_ib_ctl.scala 49:31]
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io.dec_i0_brp.prett <= io.i0_brp.prett @[el2_dec_ib_ctl.scala 49:31]
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io.dec_i0_brp.bank <= io.i0_brp.bank @[el2_dec_ib_ctl.scala 49:31]
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io.dec_i0_brp.br_start_error <= io.i0_brp.br_start_error @[el2_dec_ib_ctl.scala 49:31]
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io.dec_i0_brp.br_error <= io.i0_brp.br_error @[el2_dec_ib_ctl.scala 49:31]
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io.dec_i0_brp.hist <= io.i0_brp.hist @[el2_dec_ib_ctl.scala 49:31]
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io.dec_i0_brp.toffset <= io.i0_brp.toffset @[el2_dec_ib_ctl.scala 49:31]
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io.dec_i0_brp.valid <= io.i0_brp.valid @[el2_dec_ib_ctl.scala 49:31]
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io.dec_i0_bp_index <= io.ifu_i0_bp_index @[el2_dec_ib_ctl.scala 50:31]
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io.dec_i0_bp_fghr <= io.ifu_i0_bp_fghr @[el2_dec_ib_ctl.scala 51:31]
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io.dec_i0_bp_btag <= io.ifu_i0_bp_btag @[el2_dec_ib_ctl.scala 52:31]
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node _T = neq(io.dbg_cmd_type, UInt<2>("h02")) @[el2_dec_ib_ctl.scala 66:60]
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node debug_valid = and(io.dbg_cmd_valid, _T) @[el2_dec_ib_ctl.scala 66:41]
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node _T_1 = eq(io.dbg_cmd_write, UInt<1>("h00")) @[el2_dec_ib_ctl.scala 67:38]
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node debug_read = and(debug_valid, _T_1) @[el2_dec_ib_ctl.scala 67:36]
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node debug_write = and(debug_valid, io.dbg_cmd_write) @[el2_dec_ib_ctl.scala 68:36]
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node _T_2 = eq(io.dbg_cmd_type, UInt<1>("h00")) @[el2_dec_ib_ctl.scala 70:55]
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node debug_read_gpr = and(debug_read, _T_2) @[el2_dec_ib_ctl.scala 70:37]
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node _T_3 = eq(io.dbg_cmd_type, UInt<1>("h00")) @[el2_dec_ib_ctl.scala 71:55]
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node debug_write_gpr = and(debug_write, _T_3) @[el2_dec_ib_ctl.scala 71:37]
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node _T_4 = eq(io.dbg_cmd_type, UInt<1>("h01")) @[el2_dec_ib_ctl.scala 72:55]
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node debug_read_csr = and(debug_read, _T_4) @[el2_dec_ib_ctl.scala 72:37]
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node _T_5 = eq(io.dbg_cmd_type, UInt<1>("h01")) @[el2_dec_ib_ctl.scala 73:55]
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node debug_write_csr = and(debug_write, _T_5) @[el2_dec_ib_ctl.scala 73:37]
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node dreg = bits(io.dbg_cmd_addr, 4, 0) @[el2_dec_ib_ctl.scala 75:40]
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node dcsr = bits(io.dbg_cmd_addr, 11, 0) @[el2_dec_ib_ctl.scala 76:40]
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node _T_6 = bits(debug_read_gpr, 0, 0) @[el2_dec_ib_ctl.scala 79:20]
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node _T_7 = mux(UInt<1>("h00"), UInt<12>("h0fff"), UInt<12>("h00")) @[Bitwise.scala 72:12]
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node _T_8 = cat(_T_7, dreg) @[Cat.scala 29:58]
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node _T_9 = cat(_T_8, UInt<15>("h06033")) @[Cat.scala 29:58]
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node _T_10 = bits(debug_write_gpr, 0, 0) @[el2_dec_ib_ctl.scala 80:21]
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node _T_11 = cat(UInt<20>("h06"), dreg) @[Cat.scala 29:58]
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node _T_12 = cat(_T_11, UInt<7>("h033")) @[Cat.scala 29:58]
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node _T_13 = bits(debug_read_csr, 0, 0) @[el2_dec_ib_ctl.scala 81:20]
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node _T_14 = cat(dcsr, UInt<20>("h02073")) @[Cat.scala 29:58]
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node _T_15 = bits(debug_write_csr, 0, 0) @[el2_dec_ib_ctl.scala 82:21]
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node _T_16 = cat(dcsr, UInt<20>("h01073")) @[Cat.scala 29:58]
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node _T_17 = mux(_T_6, _T_9, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_18 = mux(_T_10, _T_12, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_19 = mux(_T_13, _T_14, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_20 = mux(_T_15, _T_16, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_21 = or(_T_17, _T_18) @[Mux.scala 27:72]
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node _T_22 = or(_T_21, _T_19) @[Mux.scala 27:72]
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node _T_23 = or(_T_22, _T_20) @[Mux.scala 27:72]
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wire ib0_debug_in : UInt<32> @[Mux.scala 27:72]
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ib0_debug_in <= _T_23 @[Mux.scala 27:72]
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node _T_24 = or(debug_write_gpr, debug_write_csr) @[el2_dec_ib_ctl.scala 86:47]
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io.dec_debug_wdata_rs1_d <= _T_24 @[el2_dec_ib_ctl.scala 86:28]
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node _T_25 = eq(dcsr, UInt<11>("h07c4")) @[el2_dec_ib_ctl.scala 89:51]
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node _T_26 = and(debug_write_csr, _T_25) @[el2_dec_ib_ctl.scala 89:43]
|
||||
io.dec_debug_fence_d <= _T_26 @[el2_dec_ib_ctl.scala 89:24]
|
||||
node _T_27 = or(io.ifu_i0_valid, debug_valid) @[el2_dec_ib_ctl.scala 91:41]
|
||||
io.dec_ib0_valid_d <= _T_27 @[el2_dec_ib_ctl.scala 91:22]
|
||||
node _T_28 = bits(debug_valid, 0, 0) @[el2_dec_ib_ctl.scala 92:41]
|
||||
node _T_29 = mux(_T_28, ib0_debug_in, io.ifu_i0_instr) @[el2_dec_ib_ctl.scala 92:28]
|
||||
io.dec_i0_instr_d <= _T_29 @[el2_dec_ib_ctl.scala 92:22]
|
||||
|
||||
|
|
@ -0,0 +1,98 @@
|
|||
module el2_dec_ib_ctl(
|
||||
input clock,
|
||||
input reset,
|
||||
input io_dbg_cmd_valid,
|
||||
input io_dbg_cmd_write,
|
||||
input [1:0] io_dbg_cmd_type,
|
||||
input [31:0] io_dbg_cmd_addr,
|
||||
input io_i0_brp_valid,
|
||||
input [11:0] io_i0_brp_toffset,
|
||||
input [1:0] io_i0_brp_hist,
|
||||
input io_i0_brp_br_error,
|
||||
input io_i0_brp_br_start_error,
|
||||
input io_i0_brp_bank,
|
||||
input [30:0] io_i0_brp_prett,
|
||||
input io_i0_brp_way,
|
||||
input io_i0_brp_ret,
|
||||
input [7:0] io_ifu_i0_bp_index,
|
||||
input [7:0] io_ifu_i0_bp_fghr,
|
||||
input [4:0] io_ifu_i0_bp_btag,
|
||||
input io_ifu_i0_pc4,
|
||||
input io_ifu_i0_valid,
|
||||
input io_ifu_i0_icaf,
|
||||
input [1:0] io_ifu_i0_icaf_type,
|
||||
input io_ifu_i0_icaf_f1,
|
||||
input io_ifu_i0_dbecc,
|
||||
input [31:0] io_ifu_i0_instr,
|
||||
input [30:0] io_ifu_i0_pc,
|
||||
output io_dec_ib0_valid_d,
|
||||
output [1:0] io_dec_i0_icaf_type_d,
|
||||
output [31:0] io_dec_i0_instr_d,
|
||||
output [30:0] io_dec_i0_pc_d,
|
||||
output io_dec_i0_pc4_d,
|
||||
output io_dec_i0_brp_valid,
|
||||
output [11:0] io_dec_i0_brp_toffset,
|
||||
output [1:0] io_dec_i0_brp_hist,
|
||||
output io_dec_i0_brp_br_error,
|
||||
output io_dec_i0_brp_br_start_error,
|
||||
output io_dec_i0_brp_bank,
|
||||
output [30:0] io_dec_i0_brp_prett,
|
||||
output io_dec_i0_brp_way,
|
||||
output io_dec_i0_brp_ret,
|
||||
output [7:0] io_dec_i0_bp_index,
|
||||
output [7:0] io_dec_i0_bp_fghr,
|
||||
output [4:0] io_dec_i0_bp_btag,
|
||||
output io_dec_i0_icaf_d,
|
||||
output io_dec_i0_icaf_f1_d,
|
||||
output io_dec_i0_dbecc_d,
|
||||
output io_dec_debug_wdata_rs1_d,
|
||||
output io_dec_debug_fence_d
|
||||
);
|
||||
wire _T = io_dbg_cmd_type != 2'h2; // @[el2_dec_ib_ctl.scala 66:60]
|
||||
wire debug_valid = io_dbg_cmd_valid & _T; // @[el2_dec_ib_ctl.scala 66:41]
|
||||
wire _T_1 = ~io_dbg_cmd_write; // @[el2_dec_ib_ctl.scala 67:38]
|
||||
wire debug_read = debug_valid & _T_1; // @[el2_dec_ib_ctl.scala 67:36]
|
||||
wire debug_write = debug_valid & io_dbg_cmd_write; // @[el2_dec_ib_ctl.scala 68:36]
|
||||
wire _T_2 = io_dbg_cmd_type == 2'h0; // @[el2_dec_ib_ctl.scala 70:55]
|
||||
wire debug_read_gpr = debug_read & _T_2; // @[el2_dec_ib_ctl.scala 70:37]
|
||||
wire debug_write_gpr = debug_write & _T_2; // @[el2_dec_ib_ctl.scala 71:37]
|
||||
wire _T_4 = io_dbg_cmd_type == 2'h1; // @[el2_dec_ib_ctl.scala 72:55]
|
||||
wire debug_read_csr = debug_read & _T_4; // @[el2_dec_ib_ctl.scala 72:37]
|
||||
wire debug_write_csr = debug_write & _T_4; // @[el2_dec_ib_ctl.scala 73:37]
|
||||
wire [4:0] dreg = io_dbg_cmd_addr[4:0]; // @[el2_dec_ib_ctl.scala 75:40]
|
||||
wire [11:0] dcsr = io_dbg_cmd_addr[11:0]; // @[el2_dec_ib_ctl.scala 76:40]
|
||||
wire [31:0] _T_9 = {12'h0,dreg,15'h6033}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_12 = {20'h6,dreg,7'h33}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_14 = {dcsr,20'h2073}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_16 = {dcsr,20'h1073}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_17 = debug_read_gpr ? _T_9 : 32'h0; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_18 = debug_write_gpr ? _T_12 : 32'h0; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_19 = debug_read_csr ? _T_14 : 32'h0; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_20 = debug_write_csr ? _T_16 : 32'h0; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_21 = _T_17 | _T_18; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_22 = _T_21 | _T_19; // @[Mux.scala 27:72]
|
||||
wire [31:0] ib0_debug_in = _T_22 | _T_20; // @[Mux.scala 27:72]
|
||||
wire _T_25 = dcsr == 12'h7c4; // @[el2_dec_ib_ctl.scala 89:51]
|
||||
assign io_dec_ib0_valid_d = io_ifu_i0_valid | debug_valid; // @[el2_dec_ib_ctl.scala 91:22]
|
||||
assign io_dec_i0_icaf_type_d = io_ifu_i0_icaf_type; // @[el2_dec_ib_ctl.scala 48:31]
|
||||
assign io_dec_i0_instr_d = debug_valid ? ib0_debug_in : io_ifu_i0_instr; // @[el2_dec_ib_ctl.scala 92:22]
|
||||
assign io_dec_i0_pc_d = io_ifu_i0_pc; // @[el2_dec_ib_ctl.scala 46:31]
|
||||
assign io_dec_i0_pc4_d = io_ifu_i0_pc4; // @[el2_dec_ib_ctl.scala 47:31]
|
||||
assign io_dec_i0_brp_valid = io_i0_brp_valid; // @[el2_dec_ib_ctl.scala 49:31]
|
||||
assign io_dec_i0_brp_toffset = io_i0_brp_toffset; // @[el2_dec_ib_ctl.scala 49:31]
|
||||
assign io_dec_i0_brp_hist = io_i0_brp_hist; // @[el2_dec_ib_ctl.scala 49:31]
|
||||
assign io_dec_i0_brp_br_error = io_i0_brp_br_error; // @[el2_dec_ib_ctl.scala 49:31]
|
||||
assign io_dec_i0_brp_br_start_error = io_i0_brp_br_start_error; // @[el2_dec_ib_ctl.scala 49:31]
|
||||
assign io_dec_i0_brp_bank = io_i0_brp_bank; // @[el2_dec_ib_ctl.scala 49:31]
|
||||
assign io_dec_i0_brp_prett = io_i0_brp_prett; // @[el2_dec_ib_ctl.scala 49:31]
|
||||
assign io_dec_i0_brp_way = io_i0_brp_way; // @[el2_dec_ib_ctl.scala 49:31]
|
||||
assign io_dec_i0_brp_ret = io_i0_brp_ret; // @[el2_dec_ib_ctl.scala 49:31]
|
||||
assign io_dec_i0_bp_index = io_ifu_i0_bp_index; // @[el2_dec_ib_ctl.scala 50:31]
|
||||
assign io_dec_i0_bp_fghr = io_ifu_i0_bp_fghr; // @[el2_dec_ib_ctl.scala 51:31]
|
||||
assign io_dec_i0_bp_btag = io_ifu_i0_bp_btag; // @[el2_dec_ib_ctl.scala 52:31]
|
||||
assign io_dec_i0_icaf_d = io_ifu_i0_icaf; // @[el2_dec_ib_ctl.scala 45:31]
|
||||
assign io_dec_i0_icaf_f1_d = io_ifu_i0_icaf_f1; // @[el2_dec_ib_ctl.scala 43:31]
|
||||
assign io_dec_i0_dbecc_d = io_ifu_i0_dbecc; // @[el2_dec_ib_ctl.scala 44:31]
|
||||
assign io_dec_debug_wdata_rs1_d = debug_write_gpr | debug_write_csr; // @[el2_dec_ib_ctl.scala 86:28]
|
||||
assign io_dec_debug_fence_d = debug_write_csr & _T_25; // @[el2_dec_ib_ctl.scala 89:24]
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,508 @@
|
|||
[
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_br0_r_pkt_hist",
|
||||
"sources":[
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_hist_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_wr_pause_r",
|
||||
"sources":[
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wraddr_r",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wen_r",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_single_ecc_error",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fastint_stall_any",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_error_r",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_start_error_r",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_inst_type",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_stall_int_ff",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wrdata_r",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_pmu_i0_itype",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fir_error",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_lower_wb",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mpc_reset_run_req",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_exc_valid",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_o_cpu_halt_status",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_fence_i",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mhwakeup",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_load_any",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_store_any",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_pause_state",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_debug_mode",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_legal",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_div_active",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dbg_halt_req",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_ifu_miss_state_idle",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_idle_any"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_kill_writeb_r",
|
||||
"sources":[
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_exc_valid",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_legal",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_single_ecc_error",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_lower_wb",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_error_r",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_start_error_r",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_inst_type",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_rddata_d",
|
||||
"sources":[
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_core_id",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_rdaddr_d"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_dbg_cmd_done",
|
||||
"sources":[
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_fence_i_r",
|
||||
"sources":[
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_fence_i",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_single_ecc_error",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_error_r",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_start_error_r",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_inst_type",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_lower_wb",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_exc_valid",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_perfcnt2",
|
||||
"sources":[
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_leak_one_r",
|
||||
"sources":[
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_noredir_r",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_lower_r",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_resume_ack",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_pause_r",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mpc_reset_run_req",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fastint_stall_any",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_fence_i",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_stall_int_ff",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wrdata_r",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wraddr_r",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wen_r",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_pmu_i0_itype",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_single_ecc_error",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_error_r",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_start_error_r",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_inst_type",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_lower_wb",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fir_error",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_o_cpu_halt_status",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_exc_valid",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mhwakeup",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_div_active",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_pause_state",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dbg_halt_req",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_legal",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_ifu_miss_state_idle",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_idle_any",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_debug_mode",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_load_any",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_store_any"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_perfcnt1",
|
||||
"sources":[
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_presync_d",
|
||||
"sources":[
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_any_unq_d",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wen_unq_d",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_rdaddr_d"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_extint",
|
||||
"sources":[
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fastint_stall_any",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_stall_int_ff",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wrdata_r",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wraddr_r",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wen_r",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_pmu_i0_itype",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_single_ecc_error",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fir_error",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_error_r",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_start_error_r",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_inst_type",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mpc_reset_run_req",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_o_cpu_halt_status",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_fence_i",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mhwakeup",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_lower_wb",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_exc_valid",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_pause_state",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_debug_mode",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_legal",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_load_any",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_store_any",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_div_active",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dbg_halt_req",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_ifu_miss_state_idle",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_idle_any"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_br0_r_pkt_br_error",
|
||||
"sources":[
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_error_r",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_path_r",
|
||||
"sources":[
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_rst_vec",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mpc_reset_run_req",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_pc_r",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_nmi_vec",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fir_addr",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fir_error",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_o_cpu_halt_status",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_npc_r",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_pmu_i0_itype",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mhwakeup",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_pause_state",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_exc_valid",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_single_ecc_error",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_lower_wb",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_error_r",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_start_error_r",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_inst_type",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_fence_i",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wraddr_r",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_stall_int_ff",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wrdata_r",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wen_r",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fastint_stall_any",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_exc_type",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_legal",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_load_any",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_store_any",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_debug_mode",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_div_active",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dbg_halt_req",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_ifu_miss_state_idle",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_idle_any"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_br0_r_pkt_middle",
|
||||
"sources":[
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_middle_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_pause_r",
|
||||
"sources":[
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fastint_stall_any",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_stall_int_ff",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wrdata_r",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wraddr_r",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wen_r",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_pmu_i0_itype",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fir_error",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mpc_reset_run_req",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_single_ecc_error",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_error_r",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_start_error_r",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_inst_type",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_o_cpu_halt_status",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_fence_i",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mhwakeup",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_load_any",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_store_any",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_lower_wb",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_exc_valid",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_pause_state",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_debug_mode",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_legal",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_div_active",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dbg_halt_req",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_ifu_miss_state_idle",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_idle_any"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_br0_r_pkt_way",
|
||||
"sources":[
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_way_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_noredir_r",
|
||||
"sources":[
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_pause_r",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fastint_stall_any",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mpc_reset_run_req",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_fence_i",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_stall_int_ff",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wrdata_r",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wraddr_r",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wen_r",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_pmu_i0_itype",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_single_ecc_error",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_error_r",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_start_error_r",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_inst_type",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_lower_wb",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fir_error",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_exc_valid",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_div_active",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_o_cpu_halt_status",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dbg_halt_req",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mhwakeup",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_ifu_miss_state_idle",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_pause_state",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_idle_any",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_debug_mode",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_legal",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_load_any",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_store_any"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_perfcnt0",
|
||||
"sources":[
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_err_r",
|
||||
"sources":[
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_lower_r",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mpc_reset_run_req",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fastint_stall_any",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_stall_int_ff",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_pmu_i0_itype",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wrdata_r",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wraddr_r",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wen_r",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_single_ecc_error",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_error_r",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_start_error_r",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_inst_type",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_o_cpu_halt_status",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fir_error",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_fence_i",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mhwakeup",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_exc_valid",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_pause_state",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_lower_wb",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_legal",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_debug_mode",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_load_any",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_store_any",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_div_active",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dbg_halt_req",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_ifu_miss_state_idle",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_idle_any"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_lower_r",
|
||||
"sources":[
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mpc_reset_run_req",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fastint_stall_any",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_stall_int_ff",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_pmu_i0_itype",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wrdata_r",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wraddr_r",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wen_r",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_single_ecc_error",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_error_r",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_start_error_r",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_inst_type",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_o_cpu_halt_status",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_fir_error",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_fence_i",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_mhwakeup",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_exc_valid",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_pause_state",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_lower_wb",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_legal",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_debug_mode",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_load_any",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_imprecise_error_store_any",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_div_active",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dbg_halt_req",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_ifu_miss_state_idle",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_idle_any"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_postsync_d",
|
||||
"sources":[
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_any_unq_d",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_rdaddr_d"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_legal_d",
|
||||
"sources":[
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_any_unq_d",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_wen_unq_d",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_csr_rdaddr_d"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_commit_cmt",
|
||||
"sources":[
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_exc_valid",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_lower_wb",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_single_ecc_error",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_error_r",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_start_error_r",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_inst_type",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_br0_r_pkt_br_start_error",
|
||||
"sources":[
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_start_error_r",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_dbg_cmd_fail",
|
||||
"sources":[
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_dbg_cmd_done",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_legal",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_single_ecc_error",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_error_r",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_start_error_r",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_inst_type",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_flush_lower_wb",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_i0trigger",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_lsu_error_pkt_r_exc_valid",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_packet_r_icaf"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_perfcnt3",
|
||||
"sources":[
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_dbg_halted"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_br0_r_pkt_valid",
|
||||
"sources":[
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_valid_r",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_dec_tlu_i0_valid_r",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_i0_br_mp_r",
|
||||
"~el2_dec_tlu_ctl|el2_dec_tlu_ctl>io_exu_pmu_i0_br_ataken"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.EmitCircuitAnnotation",
|
||||
"emitter":"firrtl.VerilogEmitter"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.BlackBoxResourceAnno",
|
||||
"target":"el2_dec_tlu_ctl.TEC_RV_ICG",
|
||||
"resourceId":"/vsrc/TEC_RV_ICG.v"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.options.TargetDirAnnotation",
|
||||
"directory":"."
|
||||
},
|
||||
{
|
||||
"class":"firrtl.options.OutputAnnotationFileAnnotation",
|
||||
"file":"el2_dec_tlu_ctl"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
|
||||
"targetDir":"."
|
||||
}
|
||||
]
|
||||
File diff suppressed because one or more lines are too long
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,45 @@
|
|||
[
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_dec_trigger|el2_dec_trigger>io_dec_i0_trigger_match_d",
|
||||
"sources":[
|
||||
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_0_execute",
|
||||
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_0_m",
|
||||
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_1_execute",
|
||||
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_1_m",
|
||||
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_3_execute",
|
||||
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_3_m",
|
||||
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_2_execute",
|
||||
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_2_m",
|
||||
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_0_tdata2",
|
||||
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_0_match_",
|
||||
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_1_tdata2",
|
||||
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_1_match_",
|
||||
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_3_tdata2",
|
||||
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_3_match_",
|
||||
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_2_tdata2",
|
||||
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_2_match_",
|
||||
"~el2_dec_trigger|el2_dec_trigger>io_dec_i0_pc_d",
|
||||
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_0_select",
|
||||
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_1_select",
|
||||
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_3_select",
|
||||
"~el2_dec_trigger|el2_dec_trigger>io_trigger_pkt_any_2_select"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.EmitCircuitAnnotation",
|
||||
"emitter":"firrtl.VerilogEmitter"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.options.TargetDirAnnotation",
|
||||
"directory":"."
|
||||
},
|
||||
{
|
||||
"class":"firrtl.options.OutputAnnotationFileAnnotation",
|
||||
"file":"el2_dec_trigger"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
|
||||
"targetDir":"."
|
||||
}
|
||||
]
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,613 @@
|
|||
module el2_dec_trigger(
|
||||
input clock,
|
||||
input reset,
|
||||
input io_trigger_pkt_any_0_select,
|
||||
input io_trigger_pkt_any_0_match_,
|
||||
input io_trigger_pkt_any_0_store,
|
||||
input io_trigger_pkt_any_0_load,
|
||||
input io_trigger_pkt_any_0_execute,
|
||||
input io_trigger_pkt_any_0_m,
|
||||
input [31:0] io_trigger_pkt_any_0_tdata2,
|
||||
input io_trigger_pkt_any_1_select,
|
||||
input io_trigger_pkt_any_1_match_,
|
||||
input io_trigger_pkt_any_1_store,
|
||||
input io_trigger_pkt_any_1_load,
|
||||
input io_trigger_pkt_any_1_execute,
|
||||
input io_trigger_pkt_any_1_m,
|
||||
input [31:0] io_trigger_pkt_any_1_tdata2,
|
||||
input io_trigger_pkt_any_2_select,
|
||||
input io_trigger_pkt_any_2_match_,
|
||||
input io_trigger_pkt_any_2_store,
|
||||
input io_trigger_pkt_any_2_load,
|
||||
input io_trigger_pkt_any_2_execute,
|
||||
input io_trigger_pkt_any_2_m,
|
||||
input [31:0] io_trigger_pkt_any_2_tdata2,
|
||||
input io_trigger_pkt_any_3_select,
|
||||
input io_trigger_pkt_any_3_match_,
|
||||
input io_trigger_pkt_any_3_store,
|
||||
input io_trigger_pkt_any_3_load,
|
||||
input io_trigger_pkt_any_3_execute,
|
||||
input io_trigger_pkt_any_3_m,
|
||||
input [31:0] io_trigger_pkt_any_3_tdata2,
|
||||
input [30:0] io_dec_i0_pc_d,
|
||||
output [3:0] io_dec_i0_trigger_match_d
|
||||
);
|
||||
wire _T = ~io_trigger_pkt_any_0_select; // @[el2_dec_trigger.scala 14:63]
|
||||
wire _T_1 = _T & io_trigger_pkt_any_0_execute; // @[el2_dec_trigger.scala 14:93]
|
||||
wire [9:0] _T_11 = {_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1}; // @[Cat.scala 29:58]
|
||||
wire [18:0] _T_20 = {_T_11,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1}; // @[Cat.scala 29:58]
|
||||
wire [27:0] _T_29 = {_T_20,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1,_T_1}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_33 = {_T_29,_T_1,_T_1,_T_1,_T_1}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_35 = {io_dec_i0_pc_d,io_trigger_pkt_any_0_tdata2[0]}; // @[Cat.scala 29:58]
|
||||
wire [31:0] dec_i0_match_data_0 = _T_33 & _T_35; // @[el2_dec_trigger.scala 14:127]
|
||||
wire _T_37 = ~io_trigger_pkt_any_1_select; // @[el2_dec_trigger.scala 14:63]
|
||||
wire _T_38 = _T_37 & io_trigger_pkt_any_1_execute; // @[el2_dec_trigger.scala 14:93]
|
||||
wire [9:0] _T_48 = {_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38}; // @[Cat.scala 29:58]
|
||||
wire [18:0] _T_57 = {_T_48,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38}; // @[Cat.scala 29:58]
|
||||
wire [27:0] _T_66 = {_T_57,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38,_T_38}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_70 = {_T_66,_T_38,_T_38,_T_38,_T_38}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_72 = {io_dec_i0_pc_d,io_trigger_pkt_any_1_tdata2[0]}; // @[Cat.scala 29:58]
|
||||
wire [31:0] dec_i0_match_data_1 = _T_70 & _T_72; // @[el2_dec_trigger.scala 14:127]
|
||||
wire _T_74 = ~io_trigger_pkt_any_2_select; // @[el2_dec_trigger.scala 14:63]
|
||||
wire _T_75 = _T_74 & io_trigger_pkt_any_2_execute; // @[el2_dec_trigger.scala 14:93]
|
||||
wire [9:0] _T_85 = {_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75}; // @[Cat.scala 29:58]
|
||||
wire [18:0] _T_94 = {_T_85,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75}; // @[Cat.scala 29:58]
|
||||
wire [27:0] _T_103 = {_T_94,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75,_T_75}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_107 = {_T_103,_T_75,_T_75,_T_75,_T_75}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_109 = {io_dec_i0_pc_d,io_trigger_pkt_any_2_tdata2[0]}; // @[Cat.scala 29:58]
|
||||
wire [31:0] dec_i0_match_data_2 = _T_107 & _T_109; // @[el2_dec_trigger.scala 14:127]
|
||||
wire _T_111 = ~io_trigger_pkt_any_3_select; // @[el2_dec_trigger.scala 14:63]
|
||||
wire _T_112 = _T_111 & io_trigger_pkt_any_3_execute; // @[el2_dec_trigger.scala 14:93]
|
||||
wire [9:0] _T_122 = {_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112}; // @[Cat.scala 29:58]
|
||||
wire [18:0] _T_131 = {_T_122,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112}; // @[Cat.scala 29:58]
|
||||
wire [27:0] _T_140 = {_T_131,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112,_T_112}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_144 = {_T_140,_T_112,_T_112,_T_112,_T_112}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_146 = {io_dec_i0_pc_d,io_trigger_pkt_any_3_tdata2[0]}; // @[Cat.scala 29:58]
|
||||
wire [31:0] dec_i0_match_data_3 = _T_144 & _T_146; // @[el2_dec_trigger.scala 14:127]
|
||||
wire _T_148 = io_trigger_pkt_any_0_execute & io_trigger_pkt_any_0_m; // @[el2_dec_trigger.scala 15:83]
|
||||
wire _T_151 = &io_trigger_pkt_any_0_tdata2; // @[el2_lib.scala 232:45]
|
||||
wire _T_152 = ~_T_151; // @[el2_lib.scala 232:39]
|
||||
wire _T_153 = io_trigger_pkt_any_0_match_ & _T_152; // @[el2_lib.scala 232:37]
|
||||
wire _T_156 = io_trigger_pkt_any_0_tdata2[0] == dec_i0_match_data_0[0]; // @[el2_lib.scala 233:52]
|
||||
wire _T_157 = _T_153 | _T_156; // @[el2_lib.scala 233:41]
|
||||
wire _T_159 = &io_trigger_pkt_any_0_tdata2[0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_160 = _T_159 & _T_153; // @[el2_lib.scala 235:41]
|
||||
wire _T_163 = io_trigger_pkt_any_0_tdata2[1] == dec_i0_match_data_0[1]; // @[el2_lib.scala 235:78]
|
||||
wire _T_164 = _T_160 | _T_163; // @[el2_lib.scala 235:23]
|
||||
wire _T_166 = &io_trigger_pkt_any_0_tdata2[1:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_167 = _T_166 & _T_153; // @[el2_lib.scala 235:41]
|
||||
wire _T_170 = io_trigger_pkt_any_0_tdata2[2] == dec_i0_match_data_0[2]; // @[el2_lib.scala 235:78]
|
||||
wire _T_171 = _T_167 | _T_170; // @[el2_lib.scala 235:23]
|
||||
wire _T_173 = &io_trigger_pkt_any_0_tdata2[2:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_174 = _T_173 & _T_153; // @[el2_lib.scala 235:41]
|
||||
wire _T_177 = io_trigger_pkt_any_0_tdata2[3] == dec_i0_match_data_0[3]; // @[el2_lib.scala 235:78]
|
||||
wire _T_178 = _T_174 | _T_177; // @[el2_lib.scala 235:23]
|
||||
wire _T_180 = &io_trigger_pkt_any_0_tdata2[3:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_181 = _T_180 & _T_153; // @[el2_lib.scala 235:41]
|
||||
wire _T_184 = io_trigger_pkt_any_0_tdata2[4] == dec_i0_match_data_0[4]; // @[el2_lib.scala 235:78]
|
||||
wire _T_185 = _T_181 | _T_184; // @[el2_lib.scala 235:23]
|
||||
wire _T_187 = &io_trigger_pkt_any_0_tdata2[4:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_188 = _T_187 & _T_153; // @[el2_lib.scala 235:41]
|
||||
wire _T_191 = io_trigger_pkt_any_0_tdata2[5] == dec_i0_match_data_0[5]; // @[el2_lib.scala 235:78]
|
||||
wire _T_192 = _T_188 | _T_191; // @[el2_lib.scala 235:23]
|
||||
wire _T_194 = &io_trigger_pkt_any_0_tdata2[5:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_195 = _T_194 & _T_153; // @[el2_lib.scala 235:41]
|
||||
wire _T_198 = io_trigger_pkt_any_0_tdata2[6] == dec_i0_match_data_0[6]; // @[el2_lib.scala 235:78]
|
||||
wire _T_199 = _T_195 | _T_198; // @[el2_lib.scala 235:23]
|
||||
wire _T_201 = &io_trigger_pkt_any_0_tdata2[6:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_202 = _T_201 & _T_153; // @[el2_lib.scala 235:41]
|
||||
wire _T_205 = io_trigger_pkt_any_0_tdata2[7] == dec_i0_match_data_0[7]; // @[el2_lib.scala 235:78]
|
||||
wire _T_206 = _T_202 | _T_205; // @[el2_lib.scala 235:23]
|
||||
wire _T_208 = &io_trigger_pkt_any_0_tdata2[7:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_209 = _T_208 & _T_153; // @[el2_lib.scala 235:41]
|
||||
wire _T_212 = io_trigger_pkt_any_0_tdata2[8] == dec_i0_match_data_0[8]; // @[el2_lib.scala 235:78]
|
||||
wire _T_213 = _T_209 | _T_212; // @[el2_lib.scala 235:23]
|
||||
wire _T_215 = &io_trigger_pkt_any_0_tdata2[8:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_216 = _T_215 & _T_153; // @[el2_lib.scala 235:41]
|
||||
wire _T_219 = io_trigger_pkt_any_0_tdata2[9] == dec_i0_match_data_0[9]; // @[el2_lib.scala 235:78]
|
||||
wire _T_220 = _T_216 | _T_219; // @[el2_lib.scala 235:23]
|
||||
wire _T_222 = &io_trigger_pkt_any_0_tdata2[9:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_223 = _T_222 & _T_153; // @[el2_lib.scala 235:41]
|
||||
wire _T_226 = io_trigger_pkt_any_0_tdata2[10] == dec_i0_match_data_0[10]; // @[el2_lib.scala 235:78]
|
||||
wire _T_227 = _T_223 | _T_226; // @[el2_lib.scala 235:23]
|
||||
wire _T_229 = &io_trigger_pkt_any_0_tdata2[10:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_230 = _T_229 & _T_153; // @[el2_lib.scala 235:41]
|
||||
wire _T_233 = io_trigger_pkt_any_0_tdata2[11] == dec_i0_match_data_0[11]; // @[el2_lib.scala 235:78]
|
||||
wire _T_234 = _T_230 | _T_233; // @[el2_lib.scala 235:23]
|
||||
wire _T_236 = &io_trigger_pkt_any_0_tdata2[11:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_237 = _T_236 & _T_153; // @[el2_lib.scala 235:41]
|
||||
wire _T_240 = io_trigger_pkt_any_0_tdata2[12] == dec_i0_match_data_0[12]; // @[el2_lib.scala 235:78]
|
||||
wire _T_241 = _T_237 | _T_240; // @[el2_lib.scala 235:23]
|
||||
wire _T_243 = &io_trigger_pkt_any_0_tdata2[12:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_244 = _T_243 & _T_153; // @[el2_lib.scala 235:41]
|
||||
wire _T_247 = io_trigger_pkt_any_0_tdata2[13] == dec_i0_match_data_0[13]; // @[el2_lib.scala 235:78]
|
||||
wire _T_248 = _T_244 | _T_247; // @[el2_lib.scala 235:23]
|
||||
wire _T_250 = &io_trigger_pkt_any_0_tdata2[13:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_251 = _T_250 & _T_153; // @[el2_lib.scala 235:41]
|
||||
wire _T_254 = io_trigger_pkt_any_0_tdata2[14] == dec_i0_match_data_0[14]; // @[el2_lib.scala 235:78]
|
||||
wire _T_255 = _T_251 | _T_254; // @[el2_lib.scala 235:23]
|
||||
wire _T_257 = &io_trigger_pkt_any_0_tdata2[14:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_258 = _T_257 & _T_153; // @[el2_lib.scala 235:41]
|
||||
wire _T_261 = io_trigger_pkt_any_0_tdata2[15] == dec_i0_match_data_0[15]; // @[el2_lib.scala 235:78]
|
||||
wire _T_262 = _T_258 | _T_261; // @[el2_lib.scala 235:23]
|
||||
wire _T_264 = &io_trigger_pkt_any_0_tdata2[15:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_265 = _T_264 & _T_153; // @[el2_lib.scala 235:41]
|
||||
wire _T_268 = io_trigger_pkt_any_0_tdata2[16] == dec_i0_match_data_0[16]; // @[el2_lib.scala 235:78]
|
||||
wire _T_269 = _T_265 | _T_268; // @[el2_lib.scala 235:23]
|
||||
wire _T_271 = &io_trigger_pkt_any_0_tdata2[16:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_272 = _T_271 & _T_153; // @[el2_lib.scala 235:41]
|
||||
wire _T_275 = io_trigger_pkt_any_0_tdata2[17] == dec_i0_match_data_0[17]; // @[el2_lib.scala 235:78]
|
||||
wire _T_276 = _T_272 | _T_275; // @[el2_lib.scala 235:23]
|
||||
wire _T_278 = &io_trigger_pkt_any_0_tdata2[17:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_279 = _T_278 & _T_153; // @[el2_lib.scala 235:41]
|
||||
wire _T_282 = io_trigger_pkt_any_0_tdata2[18] == dec_i0_match_data_0[18]; // @[el2_lib.scala 235:78]
|
||||
wire _T_283 = _T_279 | _T_282; // @[el2_lib.scala 235:23]
|
||||
wire _T_285 = &io_trigger_pkt_any_0_tdata2[18:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_286 = _T_285 & _T_153; // @[el2_lib.scala 235:41]
|
||||
wire _T_289 = io_trigger_pkt_any_0_tdata2[19] == dec_i0_match_data_0[19]; // @[el2_lib.scala 235:78]
|
||||
wire _T_290 = _T_286 | _T_289; // @[el2_lib.scala 235:23]
|
||||
wire _T_292 = &io_trigger_pkt_any_0_tdata2[19:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_293 = _T_292 & _T_153; // @[el2_lib.scala 235:41]
|
||||
wire _T_296 = io_trigger_pkt_any_0_tdata2[20] == dec_i0_match_data_0[20]; // @[el2_lib.scala 235:78]
|
||||
wire _T_297 = _T_293 | _T_296; // @[el2_lib.scala 235:23]
|
||||
wire _T_299 = &io_trigger_pkt_any_0_tdata2[20:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_300 = _T_299 & _T_153; // @[el2_lib.scala 235:41]
|
||||
wire _T_303 = io_trigger_pkt_any_0_tdata2[21] == dec_i0_match_data_0[21]; // @[el2_lib.scala 235:78]
|
||||
wire _T_304 = _T_300 | _T_303; // @[el2_lib.scala 235:23]
|
||||
wire _T_306 = &io_trigger_pkt_any_0_tdata2[21:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_307 = _T_306 & _T_153; // @[el2_lib.scala 235:41]
|
||||
wire _T_310 = io_trigger_pkt_any_0_tdata2[22] == dec_i0_match_data_0[22]; // @[el2_lib.scala 235:78]
|
||||
wire _T_311 = _T_307 | _T_310; // @[el2_lib.scala 235:23]
|
||||
wire _T_313 = &io_trigger_pkt_any_0_tdata2[22:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_314 = _T_313 & _T_153; // @[el2_lib.scala 235:41]
|
||||
wire _T_317 = io_trigger_pkt_any_0_tdata2[23] == dec_i0_match_data_0[23]; // @[el2_lib.scala 235:78]
|
||||
wire _T_318 = _T_314 | _T_317; // @[el2_lib.scala 235:23]
|
||||
wire _T_320 = &io_trigger_pkt_any_0_tdata2[23:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_321 = _T_320 & _T_153; // @[el2_lib.scala 235:41]
|
||||
wire _T_324 = io_trigger_pkt_any_0_tdata2[24] == dec_i0_match_data_0[24]; // @[el2_lib.scala 235:78]
|
||||
wire _T_325 = _T_321 | _T_324; // @[el2_lib.scala 235:23]
|
||||
wire _T_327 = &io_trigger_pkt_any_0_tdata2[24:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_328 = _T_327 & _T_153; // @[el2_lib.scala 235:41]
|
||||
wire _T_331 = io_trigger_pkt_any_0_tdata2[25] == dec_i0_match_data_0[25]; // @[el2_lib.scala 235:78]
|
||||
wire _T_332 = _T_328 | _T_331; // @[el2_lib.scala 235:23]
|
||||
wire _T_334 = &io_trigger_pkt_any_0_tdata2[25:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_335 = _T_334 & _T_153; // @[el2_lib.scala 235:41]
|
||||
wire _T_338 = io_trigger_pkt_any_0_tdata2[26] == dec_i0_match_data_0[26]; // @[el2_lib.scala 235:78]
|
||||
wire _T_339 = _T_335 | _T_338; // @[el2_lib.scala 235:23]
|
||||
wire _T_341 = &io_trigger_pkt_any_0_tdata2[26:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_342 = _T_341 & _T_153; // @[el2_lib.scala 235:41]
|
||||
wire _T_345 = io_trigger_pkt_any_0_tdata2[27] == dec_i0_match_data_0[27]; // @[el2_lib.scala 235:78]
|
||||
wire _T_346 = _T_342 | _T_345; // @[el2_lib.scala 235:23]
|
||||
wire _T_348 = &io_trigger_pkt_any_0_tdata2[27:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_349 = _T_348 & _T_153; // @[el2_lib.scala 235:41]
|
||||
wire _T_352 = io_trigger_pkt_any_0_tdata2[28] == dec_i0_match_data_0[28]; // @[el2_lib.scala 235:78]
|
||||
wire _T_353 = _T_349 | _T_352; // @[el2_lib.scala 235:23]
|
||||
wire _T_355 = &io_trigger_pkt_any_0_tdata2[28:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_356 = _T_355 & _T_153; // @[el2_lib.scala 235:41]
|
||||
wire _T_359 = io_trigger_pkt_any_0_tdata2[29] == dec_i0_match_data_0[29]; // @[el2_lib.scala 235:78]
|
||||
wire _T_360 = _T_356 | _T_359; // @[el2_lib.scala 235:23]
|
||||
wire _T_362 = &io_trigger_pkt_any_0_tdata2[29:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_363 = _T_362 & _T_153; // @[el2_lib.scala 235:41]
|
||||
wire _T_366 = io_trigger_pkt_any_0_tdata2[30] == dec_i0_match_data_0[30]; // @[el2_lib.scala 235:78]
|
||||
wire _T_367 = _T_363 | _T_366; // @[el2_lib.scala 235:23]
|
||||
wire _T_369 = &io_trigger_pkt_any_0_tdata2[30:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_370 = _T_369 & _T_153; // @[el2_lib.scala 235:41]
|
||||
wire _T_373 = io_trigger_pkt_any_0_tdata2[31] == dec_i0_match_data_0[31]; // @[el2_lib.scala 235:78]
|
||||
wire _T_374 = _T_370 | _T_373; // @[el2_lib.scala 235:23]
|
||||
wire [7:0] _T_381 = {_T_206,_T_199,_T_192,_T_185,_T_178,_T_171,_T_164,_T_157}; // @[el2_lib.scala 236:14]
|
||||
wire [15:0] _T_389 = {_T_262,_T_255,_T_248,_T_241,_T_234,_T_227,_T_220,_T_213,_T_381}; // @[el2_lib.scala 236:14]
|
||||
wire [7:0] _T_396 = {_T_318,_T_311,_T_304,_T_297,_T_290,_T_283,_T_276,_T_269}; // @[el2_lib.scala 236:14]
|
||||
wire [31:0] _T_405 = {_T_374,_T_367,_T_360,_T_353,_T_346,_T_339,_T_332,_T_325,_T_396,_T_389}; // @[el2_lib.scala 236:14]
|
||||
wire [31:0] _GEN_0 = {{31'd0}, _T_148}; // @[el2_dec_trigger.scala 15:109]
|
||||
wire [31:0] _T_406 = _GEN_0 & _T_405; // @[el2_dec_trigger.scala 15:109]
|
||||
wire _T_407 = io_trigger_pkt_any_1_execute & io_trigger_pkt_any_1_m; // @[el2_dec_trigger.scala 15:83]
|
||||
wire _T_410 = &io_trigger_pkt_any_1_tdata2; // @[el2_lib.scala 232:45]
|
||||
wire _T_411 = ~_T_410; // @[el2_lib.scala 232:39]
|
||||
wire _T_412 = io_trigger_pkt_any_1_match_ & _T_411; // @[el2_lib.scala 232:37]
|
||||
wire _T_415 = io_trigger_pkt_any_1_tdata2[0] == dec_i0_match_data_1[0]; // @[el2_lib.scala 233:52]
|
||||
wire _T_416 = _T_412 | _T_415; // @[el2_lib.scala 233:41]
|
||||
wire _T_418 = &io_trigger_pkt_any_1_tdata2[0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_419 = _T_418 & _T_412; // @[el2_lib.scala 235:41]
|
||||
wire _T_422 = io_trigger_pkt_any_1_tdata2[1] == dec_i0_match_data_1[1]; // @[el2_lib.scala 235:78]
|
||||
wire _T_423 = _T_419 | _T_422; // @[el2_lib.scala 235:23]
|
||||
wire _T_425 = &io_trigger_pkt_any_1_tdata2[1:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_426 = _T_425 & _T_412; // @[el2_lib.scala 235:41]
|
||||
wire _T_429 = io_trigger_pkt_any_1_tdata2[2] == dec_i0_match_data_1[2]; // @[el2_lib.scala 235:78]
|
||||
wire _T_430 = _T_426 | _T_429; // @[el2_lib.scala 235:23]
|
||||
wire _T_432 = &io_trigger_pkt_any_1_tdata2[2:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_433 = _T_432 & _T_412; // @[el2_lib.scala 235:41]
|
||||
wire _T_436 = io_trigger_pkt_any_1_tdata2[3] == dec_i0_match_data_1[3]; // @[el2_lib.scala 235:78]
|
||||
wire _T_437 = _T_433 | _T_436; // @[el2_lib.scala 235:23]
|
||||
wire _T_439 = &io_trigger_pkt_any_1_tdata2[3:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_440 = _T_439 & _T_412; // @[el2_lib.scala 235:41]
|
||||
wire _T_443 = io_trigger_pkt_any_1_tdata2[4] == dec_i0_match_data_1[4]; // @[el2_lib.scala 235:78]
|
||||
wire _T_444 = _T_440 | _T_443; // @[el2_lib.scala 235:23]
|
||||
wire _T_446 = &io_trigger_pkt_any_1_tdata2[4:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_447 = _T_446 & _T_412; // @[el2_lib.scala 235:41]
|
||||
wire _T_450 = io_trigger_pkt_any_1_tdata2[5] == dec_i0_match_data_1[5]; // @[el2_lib.scala 235:78]
|
||||
wire _T_451 = _T_447 | _T_450; // @[el2_lib.scala 235:23]
|
||||
wire _T_453 = &io_trigger_pkt_any_1_tdata2[5:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_454 = _T_453 & _T_412; // @[el2_lib.scala 235:41]
|
||||
wire _T_457 = io_trigger_pkt_any_1_tdata2[6] == dec_i0_match_data_1[6]; // @[el2_lib.scala 235:78]
|
||||
wire _T_458 = _T_454 | _T_457; // @[el2_lib.scala 235:23]
|
||||
wire _T_460 = &io_trigger_pkt_any_1_tdata2[6:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_461 = _T_460 & _T_412; // @[el2_lib.scala 235:41]
|
||||
wire _T_464 = io_trigger_pkt_any_1_tdata2[7] == dec_i0_match_data_1[7]; // @[el2_lib.scala 235:78]
|
||||
wire _T_465 = _T_461 | _T_464; // @[el2_lib.scala 235:23]
|
||||
wire _T_467 = &io_trigger_pkt_any_1_tdata2[7:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_468 = _T_467 & _T_412; // @[el2_lib.scala 235:41]
|
||||
wire _T_471 = io_trigger_pkt_any_1_tdata2[8] == dec_i0_match_data_1[8]; // @[el2_lib.scala 235:78]
|
||||
wire _T_472 = _T_468 | _T_471; // @[el2_lib.scala 235:23]
|
||||
wire _T_474 = &io_trigger_pkt_any_1_tdata2[8:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_475 = _T_474 & _T_412; // @[el2_lib.scala 235:41]
|
||||
wire _T_478 = io_trigger_pkt_any_1_tdata2[9] == dec_i0_match_data_1[9]; // @[el2_lib.scala 235:78]
|
||||
wire _T_479 = _T_475 | _T_478; // @[el2_lib.scala 235:23]
|
||||
wire _T_481 = &io_trigger_pkt_any_1_tdata2[9:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_482 = _T_481 & _T_412; // @[el2_lib.scala 235:41]
|
||||
wire _T_485 = io_trigger_pkt_any_1_tdata2[10] == dec_i0_match_data_1[10]; // @[el2_lib.scala 235:78]
|
||||
wire _T_486 = _T_482 | _T_485; // @[el2_lib.scala 235:23]
|
||||
wire _T_488 = &io_trigger_pkt_any_1_tdata2[10:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_489 = _T_488 & _T_412; // @[el2_lib.scala 235:41]
|
||||
wire _T_492 = io_trigger_pkt_any_1_tdata2[11] == dec_i0_match_data_1[11]; // @[el2_lib.scala 235:78]
|
||||
wire _T_493 = _T_489 | _T_492; // @[el2_lib.scala 235:23]
|
||||
wire _T_495 = &io_trigger_pkt_any_1_tdata2[11:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_496 = _T_495 & _T_412; // @[el2_lib.scala 235:41]
|
||||
wire _T_499 = io_trigger_pkt_any_1_tdata2[12] == dec_i0_match_data_1[12]; // @[el2_lib.scala 235:78]
|
||||
wire _T_500 = _T_496 | _T_499; // @[el2_lib.scala 235:23]
|
||||
wire _T_502 = &io_trigger_pkt_any_1_tdata2[12:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_503 = _T_502 & _T_412; // @[el2_lib.scala 235:41]
|
||||
wire _T_506 = io_trigger_pkt_any_1_tdata2[13] == dec_i0_match_data_1[13]; // @[el2_lib.scala 235:78]
|
||||
wire _T_507 = _T_503 | _T_506; // @[el2_lib.scala 235:23]
|
||||
wire _T_509 = &io_trigger_pkt_any_1_tdata2[13:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_510 = _T_509 & _T_412; // @[el2_lib.scala 235:41]
|
||||
wire _T_513 = io_trigger_pkt_any_1_tdata2[14] == dec_i0_match_data_1[14]; // @[el2_lib.scala 235:78]
|
||||
wire _T_514 = _T_510 | _T_513; // @[el2_lib.scala 235:23]
|
||||
wire _T_516 = &io_trigger_pkt_any_1_tdata2[14:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_517 = _T_516 & _T_412; // @[el2_lib.scala 235:41]
|
||||
wire _T_520 = io_trigger_pkt_any_1_tdata2[15] == dec_i0_match_data_1[15]; // @[el2_lib.scala 235:78]
|
||||
wire _T_521 = _T_517 | _T_520; // @[el2_lib.scala 235:23]
|
||||
wire _T_523 = &io_trigger_pkt_any_1_tdata2[15:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_524 = _T_523 & _T_412; // @[el2_lib.scala 235:41]
|
||||
wire _T_527 = io_trigger_pkt_any_1_tdata2[16] == dec_i0_match_data_1[16]; // @[el2_lib.scala 235:78]
|
||||
wire _T_528 = _T_524 | _T_527; // @[el2_lib.scala 235:23]
|
||||
wire _T_530 = &io_trigger_pkt_any_1_tdata2[16:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_531 = _T_530 & _T_412; // @[el2_lib.scala 235:41]
|
||||
wire _T_534 = io_trigger_pkt_any_1_tdata2[17] == dec_i0_match_data_1[17]; // @[el2_lib.scala 235:78]
|
||||
wire _T_535 = _T_531 | _T_534; // @[el2_lib.scala 235:23]
|
||||
wire _T_537 = &io_trigger_pkt_any_1_tdata2[17:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_538 = _T_537 & _T_412; // @[el2_lib.scala 235:41]
|
||||
wire _T_541 = io_trigger_pkt_any_1_tdata2[18] == dec_i0_match_data_1[18]; // @[el2_lib.scala 235:78]
|
||||
wire _T_542 = _T_538 | _T_541; // @[el2_lib.scala 235:23]
|
||||
wire _T_544 = &io_trigger_pkt_any_1_tdata2[18:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_545 = _T_544 & _T_412; // @[el2_lib.scala 235:41]
|
||||
wire _T_548 = io_trigger_pkt_any_1_tdata2[19] == dec_i0_match_data_1[19]; // @[el2_lib.scala 235:78]
|
||||
wire _T_549 = _T_545 | _T_548; // @[el2_lib.scala 235:23]
|
||||
wire _T_551 = &io_trigger_pkt_any_1_tdata2[19:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_552 = _T_551 & _T_412; // @[el2_lib.scala 235:41]
|
||||
wire _T_555 = io_trigger_pkt_any_1_tdata2[20] == dec_i0_match_data_1[20]; // @[el2_lib.scala 235:78]
|
||||
wire _T_556 = _T_552 | _T_555; // @[el2_lib.scala 235:23]
|
||||
wire _T_558 = &io_trigger_pkt_any_1_tdata2[20:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_559 = _T_558 & _T_412; // @[el2_lib.scala 235:41]
|
||||
wire _T_562 = io_trigger_pkt_any_1_tdata2[21] == dec_i0_match_data_1[21]; // @[el2_lib.scala 235:78]
|
||||
wire _T_563 = _T_559 | _T_562; // @[el2_lib.scala 235:23]
|
||||
wire _T_565 = &io_trigger_pkt_any_1_tdata2[21:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_566 = _T_565 & _T_412; // @[el2_lib.scala 235:41]
|
||||
wire _T_569 = io_trigger_pkt_any_1_tdata2[22] == dec_i0_match_data_1[22]; // @[el2_lib.scala 235:78]
|
||||
wire _T_570 = _T_566 | _T_569; // @[el2_lib.scala 235:23]
|
||||
wire _T_572 = &io_trigger_pkt_any_1_tdata2[22:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_573 = _T_572 & _T_412; // @[el2_lib.scala 235:41]
|
||||
wire _T_576 = io_trigger_pkt_any_1_tdata2[23] == dec_i0_match_data_1[23]; // @[el2_lib.scala 235:78]
|
||||
wire _T_577 = _T_573 | _T_576; // @[el2_lib.scala 235:23]
|
||||
wire _T_579 = &io_trigger_pkt_any_1_tdata2[23:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_580 = _T_579 & _T_412; // @[el2_lib.scala 235:41]
|
||||
wire _T_583 = io_trigger_pkt_any_1_tdata2[24] == dec_i0_match_data_1[24]; // @[el2_lib.scala 235:78]
|
||||
wire _T_584 = _T_580 | _T_583; // @[el2_lib.scala 235:23]
|
||||
wire _T_586 = &io_trigger_pkt_any_1_tdata2[24:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_587 = _T_586 & _T_412; // @[el2_lib.scala 235:41]
|
||||
wire _T_590 = io_trigger_pkt_any_1_tdata2[25] == dec_i0_match_data_1[25]; // @[el2_lib.scala 235:78]
|
||||
wire _T_591 = _T_587 | _T_590; // @[el2_lib.scala 235:23]
|
||||
wire _T_593 = &io_trigger_pkt_any_1_tdata2[25:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_594 = _T_593 & _T_412; // @[el2_lib.scala 235:41]
|
||||
wire _T_597 = io_trigger_pkt_any_1_tdata2[26] == dec_i0_match_data_1[26]; // @[el2_lib.scala 235:78]
|
||||
wire _T_598 = _T_594 | _T_597; // @[el2_lib.scala 235:23]
|
||||
wire _T_600 = &io_trigger_pkt_any_1_tdata2[26:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_601 = _T_600 & _T_412; // @[el2_lib.scala 235:41]
|
||||
wire _T_604 = io_trigger_pkt_any_1_tdata2[27] == dec_i0_match_data_1[27]; // @[el2_lib.scala 235:78]
|
||||
wire _T_605 = _T_601 | _T_604; // @[el2_lib.scala 235:23]
|
||||
wire _T_607 = &io_trigger_pkt_any_1_tdata2[27:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_608 = _T_607 & _T_412; // @[el2_lib.scala 235:41]
|
||||
wire _T_611 = io_trigger_pkt_any_1_tdata2[28] == dec_i0_match_data_1[28]; // @[el2_lib.scala 235:78]
|
||||
wire _T_612 = _T_608 | _T_611; // @[el2_lib.scala 235:23]
|
||||
wire _T_614 = &io_trigger_pkt_any_1_tdata2[28:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_615 = _T_614 & _T_412; // @[el2_lib.scala 235:41]
|
||||
wire _T_618 = io_trigger_pkt_any_1_tdata2[29] == dec_i0_match_data_1[29]; // @[el2_lib.scala 235:78]
|
||||
wire _T_619 = _T_615 | _T_618; // @[el2_lib.scala 235:23]
|
||||
wire _T_621 = &io_trigger_pkt_any_1_tdata2[29:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_622 = _T_621 & _T_412; // @[el2_lib.scala 235:41]
|
||||
wire _T_625 = io_trigger_pkt_any_1_tdata2[30] == dec_i0_match_data_1[30]; // @[el2_lib.scala 235:78]
|
||||
wire _T_626 = _T_622 | _T_625; // @[el2_lib.scala 235:23]
|
||||
wire _T_628 = &io_trigger_pkt_any_1_tdata2[30:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_629 = _T_628 & _T_412; // @[el2_lib.scala 235:41]
|
||||
wire _T_632 = io_trigger_pkt_any_1_tdata2[31] == dec_i0_match_data_1[31]; // @[el2_lib.scala 235:78]
|
||||
wire _T_633 = _T_629 | _T_632; // @[el2_lib.scala 235:23]
|
||||
wire [7:0] _T_640 = {_T_465,_T_458,_T_451,_T_444,_T_437,_T_430,_T_423,_T_416}; // @[el2_lib.scala 236:14]
|
||||
wire [15:0] _T_648 = {_T_521,_T_514,_T_507,_T_500,_T_493,_T_486,_T_479,_T_472,_T_640}; // @[el2_lib.scala 236:14]
|
||||
wire [7:0] _T_655 = {_T_577,_T_570,_T_563,_T_556,_T_549,_T_542,_T_535,_T_528}; // @[el2_lib.scala 236:14]
|
||||
wire [31:0] _T_664 = {_T_633,_T_626,_T_619,_T_612,_T_605,_T_598,_T_591,_T_584,_T_655,_T_648}; // @[el2_lib.scala 236:14]
|
||||
wire [31:0] _GEN_1 = {{31'd0}, _T_407}; // @[el2_dec_trigger.scala 15:109]
|
||||
wire [31:0] _T_665 = _GEN_1 & _T_664; // @[el2_dec_trigger.scala 15:109]
|
||||
wire _T_666 = io_trigger_pkt_any_2_execute & io_trigger_pkt_any_2_m; // @[el2_dec_trigger.scala 15:83]
|
||||
wire _T_669 = &io_trigger_pkt_any_2_tdata2; // @[el2_lib.scala 232:45]
|
||||
wire _T_670 = ~_T_669; // @[el2_lib.scala 232:39]
|
||||
wire _T_671 = io_trigger_pkt_any_2_match_ & _T_670; // @[el2_lib.scala 232:37]
|
||||
wire _T_674 = io_trigger_pkt_any_2_tdata2[0] == dec_i0_match_data_2[0]; // @[el2_lib.scala 233:52]
|
||||
wire _T_675 = _T_671 | _T_674; // @[el2_lib.scala 233:41]
|
||||
wire _T_677 = &io_trigger_pkt_any_2_tdata2[0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_678 = _T_677 & _T_671; // @[el2_lib.scala 235:41]
|
||||
wire _T_681 = io_trigger_pkt_any_2_tdata2[1] == dec_i0_match_data_2[1]; // @[el2_lib.scala 235:78]
|
||||
wire _T_682 = _T_678 | _T_681; // @[el2_lib.scala 235:23]
|
||||
wire _T_684 = &io_trigger_pkt_any_2_tdata2[1:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_685 = _T_684 & _T_671; // @[el2_lib.scala 235:41]
|
||||
wire _T_688 = io_trigger_pkt_any_2_tdata2[2] == dec_i0_match_data_2[2]; // @[el2_lib.scala 235:78]
|
||||
wire _T_689 = _T_685 | _T_688; // @[el2_lib.scala 235:23]
|
||||
wire _T_691 = &io_trigger_pkt_any_2_tdata2[2:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_692 = _T_691 & _T_671; // @[el2_lib.scala 235:41]
|
||||
wire _T_695 = io_trigger_pkt_any_2_tdata2[3] == dec_i0_match_data_2[3]; // @[el2_lib.scala 235:78]
|
||||
wire _T_696 = _T_692 | _T_695; // @[el2_lib.scala 235:23]
|
||||
wire _T_698 = &io_trigger_pkt_any_2_tdata2[3:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_699 = _T_698 & _T_671; // @[el2_lib.scala 235:41]
|
||||
wire _T_702 = io_trigger_pkt_any_2_tdata2[4] == dec_i0_match_data_2[4]; // @[el2_lib.scala 235:78]
|
||||
wire _T_703 = _T_699 | _T_702; // @[el2_lib.scala 235:23]
|
||||
wire _T_705 = &io_trigger_pkt_any_2_tdata2[4:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_706 = _T_705 & _T_671; // @[el2_lib.scala 235:41]
|
||||
wire _T_709 = io_trigger_pkt_any_2_tdata2[5] == dec_i0_match_data_2[5]; // @[el2_lib.scala 235:78]
|
||||
wire _T_710 = _T_706 | _T_709; // @[el2_lib.scala 235:23]
|
||||
wire _T_712 = &io_trigger_pkt_any_2_tdata2[5:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_713 = _T_712 & _T_671; // @[el2_lib.scala 235:41]
|
||||
wire _T_716 = io_trigger_pkt_any_2_tdata2[6] == dec_i0_match_data_2[6]; // @[el2_lib.scala 235:78]
|
||||
wire _T_717 = _T_713 | _T_716; // @[el2_lib.scala 235:23]
|
||||
wire _T_719 = &io_trigger_pkt_any_2_tdata2[6:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_720 = _T_719 & _T_671; // @[el2_lib.scala 235:41]
|
||||
wire _T_723 = io_trigger_pkt_any_2_tdata2[7] == dec_i0_match_data_2[7]; // @[el2_lib.scala 235:78]
|
||||
wire _T_724 = _T_720 | _T_723; // @[el2_lib.scala 235:23]
|
||||
wire _T_726 = &io_trigger_pkt_any_2_tdata2[7:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_727 = _T_726 & _T_671; // @[el2_lib.scala 235:41]
|
||||
wire _T_730 = io_trigger_pkt_any_2_tdata2[8] == dec_i0_match_data_2[8]; // @[el2_lib.scala 235:78]
|
||||
wire _T_731 = _T_727 | _T_730; // @[el2_lib.scala 235:23]
|
||||
wire _T_733 = &io_trigger_pkt_any_2_tdata2[8:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_734 = _T_733 & _T_671; // @[el2_lib.scala 235:41]
|
||||
wire _T_737 = io_trigger_pkt_any_2_tdata2[9] == dec_i0_match_data_2[9]; // @[el2_lib.scala 235:78]
|
||||
wire _T_738 = _T_734 | _T_737; // @[el2_lib.scala 235:23]
|
||||
wire _T_740 = &io_trigger_pkt_any_2_tdata2[9:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_741 = _T_740 & _T_671; // @[el2_lib.scala 235:41]
|
||||
wire _T_744 = io_trigger_pkt_any_2_tdata2[10] == dec_i0_match_data_2[10]; // @[el2_lib.scala 235:78]
|
||||
wire _T_745 = _T_741 | _T_744; // @[el2_lib.scala 235:23]
|
||||
wire _T_747 = &io_trigger_pkt_any_2_tdata2[10:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_748 = _T_747 & _T_671; // @[el2_lib.scala 235:41]
|
||||
wire _T_751 = io_trigger_pkt_any_2_tdata2[11] == dec_i0_match_data_2[11]; // @[el2_lib.scala 235:78]
|
||||
wire _T_752 = _T_748 | _T_751; // @[el2_lib.scala 235:23]
|
||||
wire _T_754 = &io_trigger_pkt_any_2_tdata2[11:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_755 = _T_754 & _T_671; // @[el2_lib.scala 235:41]
|
||||
wire _T_758 = io_trigger_pkt_any_2_tdata2[12] == dec_i0_match_data_2[12]; // @[el2_lib.scala 235:78]
|
||||
wire _T_759 = _T_755 | _T_758; // @[el2_lib.scala 235:23]
|
||||
wire _T_761 = &io_trigger_pkt_any_2_tdata2[12:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_762 = _T_761 & _T_671; // @[el2_lib.scala 235:41]
|
||||
wire _T_765 = io_trigger_pkt_any_2_tdata2[13] == dec_i0_match_data_2[13]; // @[el2_lib.scala 235:78]
|
||||
wire _T_766 = _T_762 | _T_765; // @[el2_lib.scala 235:23]
|
||||
wire _T_768 = &io_trigger_pkt_any_2_tdata2[13:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_769 = _T_768 & _T_671; // @[el2_lib.scala 235:41]
|
||||
wire _T_772 = io_trigger_pkt_any_2_tdata2[14] == dec_i0_match_data_2[14]; // @[el2_lib.scala 235:78]
|
||||
wire _T_773 = _T_769 | _T_772; // @[el2_lib.scala 235:23]
|
||||
wire _T_775 = &io_trigger_pkt_any_2_tdata2[14:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_776 = _T_775 & _T_671; // @[el2_lib.scala 235:41]
|
||||
wire _T_779 = io_trigger_pkt_any_2_tdata2[15] == dec_i0_match_data_2[15]; // @[el2_lib.scala 235:78]
|
||||
wire _T_780 = _T_776 | _T_779; // @[el2_lib.scala 235:23]
|
||||
wire _T_782 = &io_trigger_pkt_any_2_tdata2[15:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_783 = _T_782 & _T_671; // @[el2_lib.scala 235:41]
|
||||
wire _T_786 = io_trigger_pkt_any_2_tdata2[16] == dec_i0_match_data_2[16]; // @[el2_lib.scala 235:78]
|
||||
wire _T_787 = _T_783 | _T_786; // @[el2_lib.scala 235:23]
|
||||
wire _T_789 = &io_trigger_pkt_any_2_tdata2[16:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_790 = _T_789 & _T_671; // @[el2_lib.scala 235:41]
|
||||
wire _T_793 = io_trigger_pkt_any_2_tdata2[17] == dec_i0_match_data_2[17]; // @[el2_lib.scala 235:78]
|
||||
wire _T_794 = _T_790 | _T_793; // @[el2_lib.scala 235:23]
|
||||
wire _T_796 = &io_trigger_pkt_any_2_tdata2[17:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_797 = _T_796 & _T_671; // @[el2_lib.scala 235:41]
|
||||
wire _T_800 = io_trigger_pkt_any_2_tdata2[18] == dec_i0_match_data_2[18]; // @[el2_lib.scala 235:78]
|
||||
wire _T_801 = _T_797 | _T_800; // @[el2_lib.scala 235:23]
|
||||
wire _T_803 = &io_trigger_pkt_any_2_tdata2[18:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_804 = _T_803 & _T_671; // @[el2_lib.scala 235:41]
|
||||
wire _T_807 = io_trigger_pkt_any_2_tdata2[19] == dec_i0_match_data_2[19]; // @[el2_lib.scala 235:78]
|
||||
wire _T_808 = _T_804 | _T_807; // @[el2_lib.scala 235:23]
|
||||
wire _T_810 = &io_trigger_pkt_any_2_tdata2[19:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_811 = _T_810 & _T_671; // @[el2_lib.scala 235:41]
|
||||
wire _T_814 = io_trigger_pkt_any_2_tdata2[20] == dec_i0_match_data_2[20]; // @[el2_lib.scala 235:78]
|
||||
wire _T_815 = _T_811 | _T_814; // @[el2_lib.scala 235:23]
|
||||
wire _T_817 = &io_trigger_pkt_any_2_tdata2[20:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_818 = _T_817 & _T_671; // @[el2_lib.scala 235:41]
|
||||
wire _T_821 = io_trigger_pkt_any_2_tdata2[21] == dec_i0_match_data_2[21]; // @[el2_lib.scala 235:78]
|
||||
wire _T_822 = _T_818 | _T_821; // @[el2_lib.scala 235:23]
|
||||
wire _T_824 = &io_trigger_pkt_any_2_tdata2[21:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_825 = _T_824 & _T_671; // @[el2_lib.scala 235:41]
|
||||
wire _T_828 = io_trigger_pkt_any_2_tdata2[22] == dec_i0_match_data_2[22]; // @[el2_lib.scala 235:78]
|
||||
wire _T_829 = _T_825 | _T_828; // @[el2_lib.scala 235:23]
|
||||
wire _T_831 = &io_trigger_pkt_any_2_tdata2[22:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_832 = _T_831 & _T_671; // @[el2_lib.scala 235:41]
|
||||
wire _T_835 = io_trigger_pkt_any_2_tdata2[23] == dec_i0_match_data_2[23]; // @[el2_lib.scala 235:78]
|
||||
wire _T_836 = _T_832 | _T_835; // @[el2_lib.scala 235:23]
|
||||
wire _T_838 = &io_trigger_pkt_any_2_tdata2[23:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_839 = _T_838 & _T_671; // @[el2_lib.scala 235:41]
|
||||
wire _T_842 = io_trigger_pkt_any_2_tdata2[24] == dec_i0_match_data_2[24]; // @[el2_lib.scala 235:78]
|
||||
wire _T_843 = _T_839 | _T_842; // @[el2_lib.scala 235:23]
|
||||
wire _T_845 = &io_trigger_pkt_any_2_tdata2[24:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_846 = _T_845 & _T_671; // @[el2_lib.scala 235:41]
|
||||
wire _T_849 = io_trigger_pkt_any_2_tdata2[25] == dec_i0_match_data_2[25]; // @[el2_lib.scala 235:78]
|
||||
wire _T_850 = _T_846 | _T_849; // @[el2_lib.scala 235:23]
|
||||
wire _T_852 = &io_trigger_pkt_any_2_tdata2[25:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_853 = _T_852 & _T_671; // @[el2_lib.scala 235:41]
|
||||
wire _T_856 = io_trigger_pkt_any_2_tdata2[26] == dec_i0_match_data_2[26]; // @[el2_lib.scala 235:78]
|
||||
wire _T_857 = _T_853 | _T_856; // @[el2_lib.scala 235:23]
|
||||
wire _T_859 = &io_trigger_pkt_any_2_tdata2[26:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_860 = _T_859 & _T_671; // @[el2_lib.scala 235:41]
|
||||
wire _T_863 = io_trigger_pkt_any_2_tdata2[27] == dec_i0_match_data_2[27]; // @[el2_lib.scala 235:78]
|
||||
wire _T_864 = _T_860 | _T_863; // @[el2_lib.scala 235:23]
|
||||
wire _T_866 = &io_trigger_pkt_any_2_tdata2[27:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_867 = _T_866 & _T_671; // @[el2_lib.scala 235:41]
|
||||
wire _T_870 = io_trigger_pkt_any_2_tdata2[28] == dec_i0_match_data_2[28]; // @[el2_lib.scala 235:78]
|
||||
wire _T_871 = _T_867 | _T_870; // @[el2_lib.scala 235:23]
|
||||
wire _T_873 = &io_trigger_pkt_any_2_tdata2[28:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_874 = _T_873 & _T_671; // @[el2_lib.scala 235:41]
|
||||
wire _T_877 = io_trigger_pkt_any_2_tdata2[29] == dec_i0_match_data_2[29]; // @[el2_lib.scala 235:78]
|
||||
wire _T_878 = _T_874 | _T_877; // @[el2_lib.scala 235:23]
|
||||
wire _T_880 = &io_trigger_pkt_any_2_tdata2[29:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_881 = _T_880 & _T_671; // @[el2_lib.scala 235:41]
|
||||
wire _T_884 = io_trigger_pkt_any_2_tdata2[30] == dec_i0_match_data_2[30]; // @[el2_lib.scala 235:78]
|
||||
wire _T_885 = _T_881 | _T_884; // @[el2_lib.scala 235:23]
|
||||
wire _T_887 = &io_trigger_pkt_any_2_tdata2[30:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_888 = _T_887 & _T_671; // @[el2_lib.scala 235:41]
|
||||
wire _T_891 = io_trigger_pkt_any_2_tdata2[31] == dec_i0_match_data_2[31]; // @[el2_lib.scala 235:78]
|
||||
wire _T_892 = _T_888 | _T_891; // @[el2_lib.scala 235:23]
|
||||
wire [7:0] _T_899 = {_T_724,_T_717,_T_710,_T_703,_T_696,_T_689,_T_682,_T_675}; // @[el2_lib.scala 236:14]
|
||||
wire [15:0] _T_907 = {_T_780,_T_773,_T_766,_T_759,_T_752,_T_745,_T_738,_T_731,_T_899}; // @[el2_lib.scala 236:14]
|
||||
wire [7:0] _T_914 = {_T_836,_T_829,_T_822,_T_815,_T_808,_T_801,_T_794,_T_787}; // @[el2_lib.scala 236:14]
|
||||
wire [31:0] _T_923 = {_T_892,_T_885,_T_878,_T_871,_T_864,_T_857,_T_850,_T_843,_T_914,_T_907}; // @[el2_lib.scala 236:14]
|
||||
wire [31:0] _GEN_2 = {{31'd0}, _T_666}; // @[el2_dec_trigger.scala 15:109]
|
||||
wire [31:0] _T_924 = _GEN_2 & _T_923; // @[el2_dec_trigger.scala 15:109]
|
||||
wire _T_925 = io_trigger_pkt_any_3_execute & io_trigger_pkt_any_3_m; // @[el2_dec_trigger.scala 15:83]
|
||||
wire _T_928 = &io_trigger_pkt_any_3_tdata2; // @[el2_lib.scala 232:45]
|
||||
wire _T_929 = ~_T_928; // @[el2_lib.scala 232:39]
|
||||
wire _T_930 = io_trigger_pkt_any_3_match_ & _T_929; // @[el2_lib.scala 232:37]
|
||||
wire _T_933 = io_trigger_pkt_any_3_tdata2[0] == dec_i0_match_data_3[0]; // @[el2_lib.scala 233:52]
|
||||
wire _T_934 = _T_930 | _T_933; // @[el2_lib.scala 233:41]
|
||||
wire _T_936 = &io_trigger_pkt_any_3_tdata2[0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_937 = _T_936 & _T_930; // @[el2_lib.scala 235:41]
|
||||
wire _T_940 = io_trigger_pkt_any_3_tdata2[1] == dec_i0_match_data_3[1]; // @[el2_lib.scala 235:78]
|
||||
wire _T_941 = _T_937 | _T_940; // @[el2_lib.scala 235:23]
|
||||
wire _T_943 = &io_trigger_pkt_any_3_tdata2[1:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_944 = _T_943 & _T_930; // @[el2_lib.scala 235:41]
|
||||
wire _T_947 = io_trigger_pkt_any_3_tdata2[2] == dec_i0_match_data_3[2]; // @[el2_lib.scala 235:78]
|
||||
wire _T_948 = _T_944 | _T_947; // @[el2_lib.scala 235:23]
|
||||
wire _T_950 = &io_trigger_pkt_any_3_tdata2[2:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_951 = _T_950 & _T_930; // @[el2_lib.scala 235:41]
|
||||
wire _T_954 = io_trigger_pkt_any_3_tdata2[3] == dec_i0_match_data_3[3]; // @[el2_lib.scala 235:78]
|
||||
wire _T_955 = _T_951 | _T_954; // @[el2_lib.scala 235:23]
|
||||
wire _T_957 = &io_trigger_pkt_any_3_tdata2[3:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_958 = _T_957 & _T_930; // @[el2_lib.scala 235:41]
|
||||
wire _T_961 = io_trigger_pkt_any_3_tdata2[4] == dec_i0_match_data_3[4]; // @[el2_lib.scala 235:78]
|
||||
wire _T_962 = _T_958 | _T_961; // @[el2_lib.scala 235:23]
|
||||
wire _T_964 = &io_trigger_pkt_any_3_tdata2[4:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_965 = _T_964 & _T_930; // @[el2_lib.scala 235:41]
|
||||
wire _T_968 = io_trigger_pkt_any_3_tdata2[5] == dec_i0_match_data_3[5]; // @[el2_lib.scala 235:78]
|
||||
wire _T_969 = _T_965 | _T_968; // @[el2_lib.scala 235:23]
|
||||
wire _T_971 = &io_trigger_pkt_any_3_tdata2[5:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_972 = _T_971 & _T_930; // @[el2_lib.scala 235:41]
|
||||
wire _T_975 = io_trigger_pkt_any_3_tdata2[6] == dec_i0_match_data_3[6]; // @[el2_lib.scala 235:78]
|
||||
wire _T_976 = _T_972 | _T_975; // @[el2_lib.scala 235:23]
|
||||
wire _T_978 = &io_trigger_pkt_any_3_tdata2[6:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_979 = _T_978 & _T_930; // @[el2_lib.scala 235:41]
|
||||
wire _T_982 = io_trigger_pkt_any_3_tdata2[7] == dec_i0_match_data_3[7]; // @[el2_lib.scala 235:78]
|
||||
wire _T_983 = _T_979 | _T_982; // @[el2_lib.scala 235:23]
|
||||
wire _T_985 = &io_trigger_pkt_any_3_tdata2[7:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_986 = _T_985 & _T_930; // @[el2_lib.scala 235:41]
|
||||
wire _T_989 = io_trigger_pkt_any_3_tdata2[8] == dec_i0_match_data_3[8]; // @[el2_lib.scala 235:78]
|
||||
wire _T_990 = _T_986 | _T_989; // @[el2_lib.scala 235:23]
|
||||
wire _T_992 = &io_trigger_pkt_any_3_tdata2[8:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_993 = _T_992 & _T_930; // @[el2_lib.scala 235:41]
|
||||
wire _T_996 = io_trigger_pkt_any_3_tdata2[9] == dec_i0_match_data_3[9]; // @[el2_lib.scala 235:78]
|
||||
wire _T_997 = _T_993 | _T_996; // @[el2_lib.scala 235:23]
|
||||
wire _T_999 = &io_trigger_pkt_any_3_tdata2[9:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_1000 = _T_999 & _T_930; // @[el2_lib.scala 235:41]
|
||||
wire _T_1003 = io_trigger_pkt_any_3_tdata2[10] == dec_i0_match_data_3[10]; // @[el2_lib.scala 235:78]
|
||||
wire _T_1004 = _T_1000 | _T_1003; // @[el2_lib.scala 235:23]
|
||||
wire _T_1006 = &io_trigger_pkt_any_3_tdata2[10:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_1007 = _T_1006 & _T_930; // @[el2_lib.scala 235:41]
|
||||
wire _T_1010 = io_trigger_pkt_any_3_tdata2[11] == dec_i0_match_data_3[11]; // @[el2_lib.scala 235:78]
|
||||
wire _T_1011 = _T_1007 | _T_1010; // @[el2_lib.scala 235:23]
|
||||
wire _T_1013 = &io_trigger_pkt_any_3_tdata2[11:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_1014 = _T_1013 & _T_930; // @[el2_lib.scala 235:41]
|
||||
wire _T_1017 = io_trigger_pkt_any_3_tdata2[12] == dec_i0_match_data_3[12]; // @[el2_lib.scala 235:78]
|
||||
wire _T_1018 = _T_1014 | _T_1017; // @[el2_lib.scala 235:23]
|
||||
wire _T_1020 = &io_trigger_pkt_any_3_tdata2[12:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_1021 = _T_1020 & _T_930; // @[el2_lib.scala 235:41]
|
||||
wire _T_1024 = io_trigger_pkt_any_3_tdata2[13] == dec_i0_match_data_3[13]; // @[el2_lib.scala 235:78]
|
||||
wire _T_1025 = _T_1021 | _T_1024; // @[el2_lib.scala 235:23]
|
||||
wire _T_1027 = &io_trigger_pkt_any_3_tdata2[13:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_1028 = _T_1027 & _T_930; // @[el2_lib.scala 235:41]
|
||||
wire _T_1031 = io_trigger_pkt_any_3_tdata2[14] == dec_i0_match_data_3[14]; // @[el2_lib.scala 235:78]
|
||||
wire _T_1032 = _T_1028 | _T_1031; // @[el2_lib.scala 235:23]
|
||||
wire _T_1034 = &io_trigger_pkt_any_3_tdata2[14:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_1035 = _T_1034 & _T_930; // @[el2_lib.scala 235:41]
|
||||
wire _T_1038 = io_trigger_pkt_any_3_tdata2[15] == dec_i0_match_data_3[15]; // @[el2_lib.scala 235:78]
|
||||
wire _T_1039 = _T_1035 | _T_1038; // @[el2_lib.scala 235:23]
|
||||
wire _T_1041 = &io_trigger_pkt_any_3_tdata2[15:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_1042 = _T_1041 & _T_930; // @[el2_lib.scala 235:41]
|
||||
wire _T_1045 = io_trigger_pkt_any_3_tdata2[16] == dec_i0_match_data_3[16]; // @[el2_lib.scala 235:78]
|
||||
wire _T_1046 = _T_1042 | _T_1045; // @[el2_lib.scala 235:23]
|
||||
wire _T_1048 = &io_trigger_pkt_any_3_tdata2[16:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_1049 = _T_1048 & _T_930; // @[el2_lib.scala 235:41]
|
||||
wire _T_1052 = io_trigger_pkt_any_3_tdata2[17] == dec_i0_match_data_3[17]; // @[el2_lib.scala 235:78]
|
||||
wire _T_1053 = _T_1049 | _T_1052; // @[el2_lib.scala 235:23]
|
||||
wire _T_1055 = &io_trigger_pkt_any_3_tdata2[17:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_1056 = _T_1055 & _T_930; // @[el2_lib.scala 235:41]
|
||||
wire _T_1059 = io_trigger_pkt_any_3_tdata2[18] == dec_i0_match_data_3[18]; // @[el2_lib.scala 235:78]
|
||||
wire _T_1060 = _T_1056 | _T_1059; // @[el2_lib.scala 235:23]
|
||||
wire _T_1062 = &io_trigger_pkt_any_3_tdata2[18:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_1063 = _T_1062 & _T_930; // @[el2_lib.scala 235:41]
|
||||
wire _T_1066 = io_trigger_pkt_any_3_tdata2[19] == dec_i0_match_data_3[19]; // @[el2_lib.scala 235:78]
|
||||
wire _T_1067 = _T_1063 | _T_1066; // @[el2_lib.scala 235:23]
|
||||
wire _T_1069 = &io_trigger_pkt_any_3_tdata2[19:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_1070 = _T_1069 & _T_930; // @[el2_lib.scala 235:41]
|
||||
wire _T_1073 = io_trigger_pkt_any_3_tdata2[20] == dec_i0_match_data_3[20]; // @[el2_lib.scala 235:78]
|
||||
wire _T_1074 = _T_1070 | _T_1073; // @[el2_lib.scala 235:23]
|
||||
wire _T_1076 = &io_trigger_pkt_any_3_tdata2[20:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_1077 = _T_1076 & _T_930; // @[el2_lib.scala 235:41]
|
||||
wire _T_1080 = io_trigger_pkt_any_3_tdata2[21] == dec_i0_match_data_3[21]; // @[el2_lib.scala 235:78]
|
||||
wire _T_1081 = _T_1077 | _T_1080; // @[el2_lib.scala 235:23]
|
||||
wire _T_1083 = &io_trigger_pkt_any_3_tdata2[21:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_1084 = _T_1083 & _T_930; // @[el2_lib.scala 235:41]
|
||||
wire _T_1087 = io_trigger_pkt_any_3_tdata2[22] == dec_i0_match_data_3[22]; // @[el2_lib.scala 235:78]
|
||||
wire _T_1088 = _T_1084 | _T_1087; // @[el2_lib.scala 235:23]
|
||||
wire _T_1090 = &io_trigger_pkt_any_3_tdata2[22:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_1091 = _T_1090 & _T_930; // @[el2_lib.scala 235:41]
|
||||
wire _T_1094 = io_trigger_pkt_any_3_tdata2[23] == dec_i0_match_data_3[23]; // @[el2_lib.scala 235:78]
|
||||
wire _T_1095 = _T_1091 | _T_1094; // @[el2_lib.scala 235:23]
|
||||
wire _T_1097 = &io_trigger_pkt_any_3_tdata2[23:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_1098 = _T_1097 & _T_930; // @[el2_lib.scala 235:41]
|
||||
wire _T_1101 = io_trigger_pkt_any_3_tdata2[24] == dec_i0_match_data_3[24]; // @[el2_lib.scala 235:78]
|
||||
wire _T_1102 = _T_1098 | _T_1101; // @[el2_lib.scala 235:23]
|
||||
wire _T_1104 = &io_trigger_pkt_any_3_tdata2[24:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_1105 = _T_1104 & _T_930; // @[el2_lib.scala 235:41]
|
||||
wire _T_1108 = io_trigger_pkt_any_3_tdata2[25] == dec_i0_match_data_3[25]; // @[el2_lib.scala 235:78]
|
||||
wire _T_1109 = _T_1105 | _T_1108; // @[el2_lib.scala 235:23]
|
||||
wire _T_1111 = &io_trigger_pkt_any_3_tdata2[25:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_1112 = _T_1111 & _T_930; // @[el2_lib.scala 235:41]
|
||||
wire _T_1115 = io_trigger_pkt_any_3_tdata2[26] == dec_i0_match_data_3[26]; // @[el2_lib.scala 235:78]
|
||||
wire _T_1116 = _T_1112 | _T_1115; // @[el2_lib.scala 235:23]
|
||||
wire _T_1118 = &io_trigger_pkt_any_3_tdata2[26:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_1119 = _T_1118 & _T_930; // @[el2_lib.scala 235:41]
|
||||
wire _T_1122 = io_trigger_pkt_any_3_tdata2[27] == dec_i0_match_data_3[27]; // @[el2_lib.scala 235:78]
|
||||
wire _T_1123 = _T_1119 | _T_1122; // @[el2_lib.scala 235:23]
|
||||
wire _T_1125 = &io_trigger_pkt_any_3_tdata2[27:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_1126 = _T_1125 & _T_930; // @[el2_lib.scala 235:41]
|
||||
wire _T_1129 = io_trigger_pkt_any_3_tdata2[28] == dec_i0_match_data_3[28]; // @[el2_lib.scala 235:78]
|
||||
wire _T_1130 = _T_1126 | _T_1129; // @[el2_lib.scala 235:23]
|
||||
wire _T_1132 = &io_trigger_pkt_any_3_tdata2[28:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_1133 = _T_1132 & _T_930; // @[el2_lib.scala 235:41]
|
||||
wire _T_1136 = io_trigger_pkt_any_3_tdata2[29] == dec_i0_match_data_3[29]; // @[el2_lib.scala 235:78]
|
||||
wire _T_1137 = _T_1133 | _T_1136; // @[el2_lib.scala 235:23]
|
||||
wire _T_1139 = &io_trigger_pkt_any_3_tdata2[29:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_1140 = _T_1139 & _T_930; // @[el2_lib.scala 235:41]
|
||||
wire _T_1143 = io_trigger_pkt_any_3_tdata2[30] == dec_i0_match_data_3[30]; // @[el2_lib.scala 235:78]
|
||||
wire _T_1144 = _T_1140 | _T_1143; // @[el2_lib.scala 235:23]
|
||||
wire _T_1146 = &io_trigger_pkt_any_3_tdata2[30:0]; // @[el2_lib.scala 235:36]
|
||||
wire _T_1147 = _T_1146 & _T_930; // @[el2_lib.scala 235:41]
|
||||
wire _T_1150 = io_trigger_pkt_any_3_tdata2[31] == dec_i0_match_data_3[31]; // @[el2_lib.scala 235:78]
|
||||
wire _T_1151 = _T_1147 | _T_1150; // @[el2_lib.scala 235:23]
|
||||
wire [7:0] _T_1158 = {_T_983,_T_976,_T_969,_T_962,_T_955,_T_948,_T_941,_T_934}; // @[el2_lib.scala 236:14]
|
||||
wire [15:0] _T_1166 = {_T_1039,_T_1032,_T_1025,_T_1018,_T_1011,_T_1004,_T_997,_T_990,_T_1158}; // @[el2_lib.scala 236:14]
|
||||
wire [7:0] _T_1173 = {_T_1095,_T_1088,_T_1081,_T_1074,_T_1067,_T_1060,_T_1053,_T_1046}; // @[el2_lib.scala 236:14]
|
||||
wire [31:0] _T_1182 = {_T_1151,_T_1144,_T_1137,_T_1130,_T_1123,_T_1116,_T_1109,_T_1102,_T_1173,_T_1166}; // @[el2_lib.scala 236:14]
|
||||
wire [31:0] _GEN_3 = {{31'd0}, _T_925}; // @[el2_dec_trigger.scala 15:109]
|
||||
wire [31:0] _T_1183 = _GEN_3 & _T_1182; // @[el2_dec_trigger.scala 15:109]
|
||||
wire [127:0] _T_1186 = {_T_1183,_T_924,_T_665,_T_406}; // @[Cat.scala 29:58]
|
||||
assign io_dec_i0_trigger_match_d = _T_1186[3:0]; // @[el2_dec_trigger.scala 15:29]
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,713 @@
|
|||
package dec
|
||||
import chisel3._
|
||||
import include._
|
||||
import lib._
|
||||
|
||||
class el2_dec_IO extends Bundle with el2_lib {
|
||||
//val clk = Input(Clock())
|
||||
val free_clk = Input(Clock())
|
||||
val active_clk = Input(Clock())
|
||||
|
||||
val lsu_fastint_stall_any = Input(Bool()) // needed by lsu for 2nd pass of dma with ecc correction, stall next cycle
|
||||
|
||||
val dec_extint_stall = Output(Bool())
|
||||
|
||||
val dec_i0_decode_d = Output(Bool())
|
||||
val dec_pause_state_cg = Output(Bool()) // to top for active state clock gating
|
||||
|
||||
// val rst_l = Input(Bool()) // reset, active low
|
||||
val rst_vec = Input(UInt(32.W)) // [31:1] reset vector, from core pins
|
||||
|
||||
val nmi_int = Input(Bool()) // NMI pin
|
||||
val nmi_vec = Input(UInt(32.W)) // [31:1] NMI vector, from pins
|
||||
|
||||
val i_cpu_halt_req = Input(Bool()) // Asynchronous Halt request to CPU
|
||||
val i_cpu_run_req = Input(Bool()) // Asynchronous Restart request to CPU
|
||||
|
||||
val o_cpu_halt_status = Output(Bool()) // Halt status of core (pmu/fw)
|
||||
val o_cpu_halt_ack = Output(Bool()) // Halt request ack
|
||||
val o_cpu_run_ack = Output(Bool()) // Run request ack
|
||||
val o_debug_mode_status = Output(Bool()) // Core to the PMU that core is in debug mode. When core is in debug mode, the PMU should refrain from sendng a halt or run request
|
||||
|
||||
val core_id = Input(UInt(32.W)) // [31:4] CORE ID
|
||||
|
||||
// external MPC halt/run interface
|
||||
val mpc_debug_halt_req = Input(Bool()) // Async halt request
|
||||
val mpc_debug_run_req = Input(Bool()) // Async run request
|
||||
val mpc_reset_run_req = Input(Bool()) // Run/halt after reset
|
||||
val mpc_debug_halt_ack = Output(Bool()) // Halt ack
|
||||
val mpc_debug_run_ack = Output(Bool()) // Run ack
|
||||
val debug_brkpt_status = Output(Bool()) // debug breakpoint
|
||||
|
||||
val exu_pmu_i0_br_misp = Input(Bool()) // slot 0 branch misp
|
||||
val exu_pmu_i0_br_ataken = Input(Bool()) // slot 0 branch actual taken
|
||||
val exu_pmu_i0_pc4 = Input(Bool()) // slot 0 4 byte branch
|
||||
|
||||
|
||||
val lsu_nonblock_load_valid_m = Input(Bool()) // valid nonblock load at m
|
||||
val lsu_nonblock_load_tag_m = Input(UInt(LSU_NUM_NBLOAD_WIDTH.W)) // -> corresponding tag
|
||||
val lsu_nonblock_load_inv_r = Input(Bool()) // invalidate request for nonblock load r
|
||||
val lsu_nonblock_load_inv_tag_r = Input(UInt(LSU_NUM_NBLOAD_WIDTH.W)) // -> corresponding tag
|
||||
val lsu_nonblock_load_data_valid = Input(Bool()) // valid nonblock load data back
|
||||
val lsu_nonblock_load_data_error = Input(Bool()) // nonblock load bus error
|
||||
val lsu_nonblock_load_data_tag = Input(UInt(LSU_NUM_NBLOAD_WIDTH.W)) // -> corresponding tag
|
||||
val lsu_nonblock_load_data = Input(UInt(32.W)) // nonblock load data
|
||||
|
||||
val lsu_pmu_bus_trxn = Input(Bool()) // D side bus transaction
|
||||
val lsu_pmu_bus_misaligned = Input(Bool()) // D side bus misaligned
|
||||
val lsu_pmu_bus_error = Input(Bool()) // D side bus error
|
||||
val lsu_pmu_bus_busy = Input(Bool()) // D side bus busy
|
||||
val lsu_pmu_misaligned_m = Input(Bool()) // D side load or store misaligned
|
||||
val lsu_pmu_load_external_m = Input(Bool()) // D side bus load
|
||||
val lsu_pmu_store_external_m = Input(Bool()) // D side bus store
|
||||
val dma_pmu_dccm_read = Input(Bool()) // DMA DCCM read
|
||||
val dma_pmu_dccm_write = Input(Bool()) // DMA DCCM write
|
||||
val dma_pmu_any_read = Input(Bool()) // DMA read
|
||||
val dma_pmu_any_write = Input(Bool()) // DMA write
|
||||
|
||||
val lsu_fir_addr = Input(UInt(32.W)) //[31:1] Fast int address
|
||||
val lsu_fir_error = Input(UInt(2.W)) //[1:0] Fast int lookup error
|
||||
|
||||
val ifu_pmu_instr_aligned = Input(Bool()) // aligned instructions
|
||||
val ifu_pmu_fetch_stall = Input(Bool()) // fetch unit stalled
|
||||
val ifu_pmu_ic_miss = Input(Bool()) // icache miss
|
||||
val ifu_pmu_ic_hit = Input(Bool()) // icache hit
|
||||
val ifu_pmu_bus_error = Input(Bool()) // Instruction side bus error
|
||||
val ifu_pmu_bus_busy = Input(Bool()) // Instruction side bus busy
|
||||
val ifu_pmu_bus_trxn = Input(Bool()) // Instruction side bus transaction
|
||||
|
||||
val ifu_ic_error_start = Input(Bool()) // IC single bit error
|
||||
val ifu_iccm_rd_ecc_single_err = Input(Bool()) // ICCM single bit error
|
||||
|
||||
val lsu_trigger_match_m = Input(UInt(4.W))
|
||||
val dbg_cmd_valid = Input(Bool()) // debugger abstract command valid
|
||||
val dbg_cmd_write = Input(Bool()) // command is a write
|
||||
val dbg_cmd_type = Input(UInt(2.W)) // command type
|
||||
val dbg_cmd_addr = Input(UInt(32.W)) // command address
|
||||
val dbg_cmd_wrdata = Input(UInt(2.W)) // command write data, for fence/fence_i
|
||||
|
||||
|
||||
val ifu_i0_icaf = Input(Bool()) // icache access fault
|
||||
val ifu_i0_icaf_type = Input(UInt(2.W))
|
||||
|
||||
val ifu_i0_icaf_f1 = Input(Bool()) // i0 has access fault on second fetch group
|
||||
val ifu_i0_dbecc = Input(Bool()) // icache/iccm double-bit error
|
||||
|
||||
val lsu_idle_any = Input(Bool()) // lsu idle for halting
|
||||
|
||||
val i0_brp = Input(new el2_br_pkt_t) // branch packet
|
||||
val ifu_i0_bp_index = Input(UInt(BTB_ADDR_HI.W)) // BP index
|
||||
val ifu_i0_bp_fghr = Input(UInt(BHT_GHR_SIZE.W)) // BP FGHR
|
||||
val ifu_i0_bp_btag = Input(UInt(BTB_BTAG_SIZE.W)) // BP tag
|
||||
|
||||
val lsu_error_pkt_r = Input(new el2_lsu_error_pkt_t) // LSU exception/error packet
|
||||
val lsu_single_ecc_error_incr = Input(Bool())// LSU inc SB error counter
|
||||
|
||||
val lsu_imprecise_error_load_any = Input(Bool()) // LSU imprecise load bus error
|
||||
val lsu_imprecise_error_store_any = Input(Bool()) // LSU imprecise store bus error
|
||||
val lsu_imprecise_error_addr_any = Input(UInt(32.W)) // LSU imprecise bus error address
|
||||
|
||||
val exu_div_result = Input(UInt(32.W)) // final div result
|
||||
val exu_div_wren = Input(UInt(1.W)) // Divide write enable to GPR
|
||||
val exu_csr_rs1_x = Input(UInt(32.W)) // rs1 for csr instruction
|
||||
val lsu_result_m = Input(UInt(32.W)) // load result
|
||||
val lsu_result_corr_r = Input(UInt(32.W)) // load result - corrected load data
|
||||
|
||||
val lsu_load_stall_any = Input(Bool()) // This is for blocking loads
|
||||
val lsu_store_stall_any = Input(Bool()) // This is for blocking stores
|
||||
val dma_dccm_stall_any = Input(Bool()) // stall any load/store at decode, pmu event
|
||||
val dma_iccm_stall_any = Input(Bool()) // iccm stalled, pmu event
|
||||
|
||||
val iccm_dma_sb_error = Input(Bool()) // ICCM DMA single bit error
|
||||
|
||||
val exu_flush_final = Input(Bool()) // slot0 flush
|
||||
|
||||
val exu_npc_r = Input(UInt(32.W)) // next PC
|
||||
|
||||
val exu_i0_result_x = Input(UInt(32.W)) // alu result x
|
||||
|
||||
|
||||
val ifu_i0_valid = Input(Bool()) // fetch valids to instruction buffer
|
||||
val ifu_i0_instr = Input(UInt(32.W)) // fetch inst's to instruction buffer
|
||||
val ifu_i0_pc = Input(UInt(32.W)) // pc's for instruction buffer
|
||||
val ifu_i0_pc4 = Input(Bool()) // indication of 4B or 2B for corresponding inst
|
||||
val exu_i0_pc_x = Input(UInt(32.W)) // pc's for e1 from the alu's
|
||||
|
||||
val mexintpend = Input(Bool()) // External interrupt pending
|
||||
val timer_int = Input(Bool()) // Timer interrupt pending (from pin)
|
||||
val soft_int = Input(Bool()) // Software interrupt pending (from pin)
|
||||
|
||||
val pic_claimid = Input(UInt(8.W)) // PIC claimid
|
||||
val pic_pl = Input(UInt(4.W)) // PIC priv level
|
||||
val mhwakeup = Input(Bool()) // High priority wakeup
|
||||
|
||||
val dec_tlu_meicurpl = Output(UInt(4.W)) // to PIC, Current priv level
|
||||
val dec_tlu_meipt = Output(UInt(4.W)) // to PIC
|
||||
|
||||
val ifu_ic_debug_rd_data = Input(UInt(70.W)) // diagnostic icache read data
|
||||
val ifu_ic_debug_rd_data_valid = Input(Bool()) // diagnostic icache read data valid
|
||||
val dec_tlu_ic_diag_pkt = Output(new el2_cache_debug_pkt_t) // packet of DICAWICS, DICAD0/1, DICAGO info for icache diagnostics
|
||||
|
||||
|
||||
// Debug start
|
||||
val dbg_halt_req = Input(Bool()) // DM requests a halt
|
||||
val dbg_resume_req = Input(Bool()) // DM requests a resume
|
||||
val ifu_miss_state_idle = Input(Bool()) // I-side miss buffer empty
|
||||
|
||||
val dec_tlu_dbg_halted = Output(Bool()) // Core is halted and ready for debug command
|
||||
val dec_tlu_debug_mode = Output(Bool()) // Core is in debug mode
|
||||
val dec_tlu_resume_ack = Output(Bool()) // Resume acknowledge
|
||||
val dec_tlu_flush_noredir_r = Output(Bool()) // Tell fetch to idle on this flush
|
||||
val dec_tlu_mpc_halted_only = Output(Bool()) // Core is halted only due to MPC
|
||||
val dec_tlu_flush_leak_one_r = Output(Bool()) // single step
|
||||
val dec_tlu_flush_err_r = Output(Bool()) // iside perr/ecc rfpc
|
||||
val dec_tlu_meihap = Output(UInt(32.W)) // Fast ext int base
|
||||
|
||||
val dec_debug_wdata_rs1_d = Output(Bool()) // insert debug write data into rs1 at decode
|
||||
|
||||
val dec_dbg_rddata = Output(UInt(32.W)) // debug command read data
|
||||
|
||||
val dec_dbg_cmd_done = Output(Bool()) // abstract command is done
|
||||
val dec_dbg_cmd_fail = Output(Bool()) // abstract command failed (illegal reg address)
|
||||
|
||||
val trigger_pkt_any = Output(Vec(4,new el2_trigger_pkt_t)) // info needed by debug trigger blocks
|
||||
|
||||
val dec_tlu_force_halt = Output(UInt(1.W)) // halt has been forced
|
||||
// Debug end
|
||||
// branch info from pipe0 for errors or counter updates
|
||||
val exu_i0_br_hist_r = Input(UInt(2.W)) // history
|
||||
val exu_i0_br_error_r = Input(Bool()) // error
|
||||
val exu_i0_br_start_error_r = Input(Bool()) // start error
|
||||
val exu_i0_br_valid_r = Input(Bool()) // valid
|
||||
val exu_i0_br_mp_r = Input(Bool()) // mispredict
|
||||
val exu_i0_br_middle_r = Input(Bool()) // middle of bank
|
||||
|
||||
val exu_i0_br_way_r = Input(Bool()) // way hit or repl
|
||||
|
||||
val dec_i0_rs1_en_d = Output(Bool()) // Qualify GPR RS1 data
|
||||
val dec_i0_rs2_en_d = Output(Bool()) // Qualify GPR RS2 data
|
||||
val gpr_i0_rs1_d = Output(UInt(32.W)) // gpr rs1 data
|
||||
val gpr_i0_rs2_d = Output(UInt(32.W)) // gpr rs2 data
|
||||
|
||||
val dec_i0_immed_d = Output(UInt(32.W)) // immediate data
|
||||
val dec_i0_br_immed_d = Output(UInt(13.W)) // br immediate data
|
||||
|
||||
val i0_ap = Output(new el2_alu_pkt_t)// alu packet
|
||||
|
||||
val dec_i0_alu_decode_d = Output(Bool()) // schedule on D-stage alu
|
||||
|
||||
val dec_i0_select_pc_d = Output(Bool()) // select pc onto rs1 for jal's
|
||||
|
||||
val dec_i0_pc_d = Output(UInt(32.W)) // pc's at decode
|
||||
val dec_i0_rs1_bypass_en_d = Output(UInt(2.W)) // rs1 bypass enable
|
||||
val dec_i0_rs2_bypass_en_d = Output(UInt(2.W)) // rs2 bypass enable
|
||||
|
||||
val dec_i0_rs1_bypass_data_d = Output(UInt(32.W)) // rs1 bypass data
|
||||
val dec_i0_rs2_bypass_data_d = Output(UInt(32.W)) // rs2 bypass data
|
||||
|
||||
val lsu_p = Output(new el2_lsu_pkt_t) // lsu packet
|
||||
val mul_p = Output(new el2_mul_pkt_t) // mul packet
|
||||
val div_p = Output(new el2_div_pkt_t) // div packet
|
||||
val dec_div_cancel = Output(Bool()) // cancel divide operation
|
||||
|
||||
val dec_lsu_offset_d = Output(UInt(12.W)) // 12b offset for load/store addresses
|
||||
|
||||
val dec_csr_ren_d = Output(Bool()) // csr read enable
|
||||
|
||||
|
||||
val dec_tlu_flush_lower_r = Output(Bool()) // tlu flush due to late mp, exception, rfpc, or int
|
||||
val dec_tlu_flush_path_r = Output(UInt(32.W)) // tlu flush target
|
||||
val dec_tlu_i0_kill_writeb_r = Output(Bool()) // I0 is flushed, don't writeback any results to arch state
|
||||
val dec_tlu_fence_i_r = Output(Bool()) // flush is a fence_i rfnpc, flush icache
|
||||
|
||||
val pred_correct_npc_x = Output(UInt(32.W)) // npc if prediction is correct at e2 stage
|
||||
|
||||
val dec_tlu_br0_r_pkt = Output(new el2_br_tlu_pkt_t) // slot 0 branch predictor update packet
|
||||
|
||||
val dec_tlu_perfcnt0 = Output(Bool()) // toggles when slot0 perf counter 0 has an event inc
|
||||
val dec_tlu_perfcnt1 = Output(Bool()) // toggles when slot0 perf counter 1 has an event inc
|
||||
val dec_tlu_perfcnt2 = Output(Bool()) // toggles when slot0 perf counter 2 has an event inc
|
||||
val dec_tlu_perfcnt3 = Output(Bool()) // toggles when slot0 perf counter 3 has an event inc
|
||||
|
||||
val dec_i0_predict_p_d = Output(new el2_predict_pkt_t) // prediction packet to alus
|
||||
val i0_predict_fghr_d = Output(UInt(BHT_GHR_SIZE.W)) // DEC predict fghr
|
||||
val i0_predict_index_d = Output(UInt(BHT_ADDR_HI.W)) // DEC predict index
|
||||
val i0_predict_btag_d = Output(UInt(BTB_BTAG_SIZE.W)) // DEC predict branch tag
|
||||
|
||||
val dec_lsu_valid_raw_d = Output(Bool())
|
||||
|
||||
val dec_tlu_mrac_ff = Output(UInt(32.W)) // CSR for memory region control
|
||||
|
||||
val dec_data_en = Output(UInt(2.W)) // clock-gate control logic
|
||||
val dec_ctl_en = Output(UInt(2.W))
|
||||
|
||||
val ifu_i0_cinst = Input(UInt(16.W)) // 16b compressed instruction
|
||||
|
||||
// val rv_trace_pkt = Output(new el2_trace_pkt_t) // trace packet
|
||||
|
||||
// feature disable from mfdc
|
||||
val dec_tlu_external_ldfwd_disable = Output(Bool()) // disable external load forwarding
|
||||
val dec_tlu_sideeffect_posted_disable = Output(Bool()) // disable posted stores to side-effect address
|
||||
val dec_tlu_core_ecc_disable = Output(Bool()) // disable core ECC
|
||||
val dec_tlu_bpred_disable = Output(Bool()) // disable branch prediction
|
||||
val dec_tlu_wb_coalescing_disable = Output(Bool()) // disable writebuffer coalescing
|
||||
val dec_tlu_dma_qos_prty = Output(UInt(3.W)) // DMA QoS priority coming from MFDC [18:16]
|
||||
|
||||
// clock gating overrides from mcgc
|
||||
val dec_tlu_misc_clk_override = Output(Bool()) // override misc clock domain gating
|
||||
val dec_tlu_ifu_clk_override = Output(Bool()) // override fetch clock domain gating
|
||||
val dec_tlu_lsu_clk_override = Output(Bool()) // override load/store clock domain gating
|
||||
val dec_tlu_bus_clk_override = Output(Bool()) // override bus clock domain gating
|
||||
val dec_tlu_pic_clk_override = Output(Bool()) // override PIC clock domain gating
|
||||
val dec_tlu_dccm_clk_override = Output(Bool()) // override DCCM clock domain gating
|
||||
val dec_tlu_icm_clk_override = Output(Bool()) // override ICCM clock domain gating
|
||||
|
||||
val dec_tlu_i0_commit_cmt = Output(Bool()) // committed i0 instruction
|
||||
val scan_mode = Input(Bool())
|
||||
|
||||
}
|
||||
|
||||
class el2_dec extends Module with param with RequireAsyncReset{
|
||||
val io = IO(new el2_dec_IO)
|
||||
io.dec_i0_pc_d := 0.U
|
||||
|
||||
|
||||
|
||||
// val dec_ib0_valid_d = WireInit(Bool(),0.B)
|
||||
//
|
||||
// val dec_pmu_instr_decoded = WireInit(Bool(),0.B)
|
||||
// val dec_pmu_decode_stall = WireInit(Bool(),0.B)
|
||||
// val dec_pmu_presync_stall = WireInit(Bool(),0.B)
|
||||
// val dec_pmu_postsync_stall = WireInit(Bool(),0.B)
|
||||
//
|
||||
// val dec_tlu_wr_pause_r = WireInit(UInt(1.W),0.U) // CSR write to pause reg is at R.
|
||||
//
|
||||
// val dec_i0_rs1_d = WireInit(UInt(5.W),0.U)
|
||||
// val dec_i0_rs2_d = WireInit(UInt(5.W),0.U)
|
||||
//
|
||||
// val dec_i0_instr_d = WireInit(UInt(32.W),0.U)
|
||||
//
|
||||
// val dec_tlu_pipelining_disable = WireInit(UInt(1.W),0.U)
|
||||
// val dec_i0_waddr_r = WireInit(UInt(5.W),0.U)
|
||||
// val dec_i0_wen_r = WireInit(UInt(5.W),0.U)
|
||||
// val dec_i0_wdata_r = WireInit(UInt(32.W),0.U)
|
||||
// val dec_csr_wen_r = WireInit(UInt(1.W),0.U) // csr write enable at wb
|
||||
// val dec_csr_wraddr_r = WireInit(UInt(12.W),0.U) // write address for csryes
|
||||
// val dec_csr_wrdata_r = WireInit(UInt(32.W),0.U) // csr write data at wb
|
||||
//
|
||||
// val dec_csr_rdaddr_d = WireInit(UInt(12.W),0.U) // read address for csr
|
||||
// val dec_csr_rddata_d = WireInit(UInt(32.W),0.U) // csr read data at wb
|
||||
// val dec_csr_legal_d = WireInit(Bool(),0.B) // csr indicates legal operation
|
||||
//
|
||||
// val dec_csr_wen_unq_d = WireInit(Bool(),0.B) // valid csr with write - for csr legal
|
||||
// val dec_csr_any_unq_d = WireInit(Bool(),0.B) // valid csr - for csr legal
|
||||
// val dec_csr_stall_int_ff = WireInit(Bool(),0.B) // csr is mie/mstatus
|
||||
//
|
||||
// val dec_tlu_packet_r = Wire(new el2_trap_pkt_t)
|
||||
//
|
||||
// val dec_i0_pc4_d = WireInit(UInt(1.W),0.U)
|
||||
// val dec_tlu_presync_d = WireInit(UInt(1.W),0.U)
|
||||
// val dec_tlu_postsync_d = WireInit(UInt(1.W),0.U)
|
||||
// val dec_tlu_debug_stall = WireInit(UInt(1.W),0.U)
|
||||
// val dec_illegal_inst = WireInit(UInt(32.W),0.U)
|
||||
// val dec_i0_icaf_d = WireInit(UInt(1.W),0.U)
|
||||
// val dec_i0_dbecc_d = WireInit(UInt(1.W),0.U)
|
||||
// val dec_i0_icaf_f1_d = WireInit(UInt(1.W),0.U)
|
||||
// val dec_i0_trigger_match_d = WireInit(UInt(4.W),0.U)
|
||||
// val dec_debug_fence_d = WireInit(UInt(1.W),0.U)
|
||||
// val dec_nonblock_load_wen = WireInit(UInt(1.W),0.U)
|
||||
// val dec_nonblock_load_waddr = WireInit(UInt(5.W),0.U)
|
||||
// val dec_tlu_flush_pause_r = WireInit(UInt(1.W),0.U)
|
||||
// val dec_i0_brp = Wire(new el2_br_pkt_t)
|
||||
// val dec_i0_bp_index = WireInit(UInt(BTB_ADDR_HI.W),0.U)
|
||||
// val dec_i0_bp_fghr = WireInit(UInt(BHT_GHR_SIZE.W),0.U)
|
||||
// val dec_i0_bp_btag = WireInit(UInt(BTB_BTAG_SIZE.W),0.U)
|
||||
//
|
||||
// val dec_tlu_i0_pc_r = WireInit(UInt(32.W),0.U)
|
||||
// val dec_tlu_i0_kill_writeb_wb = WireInit(Bool(),0.B)
|
||||
// val dec_tlu_flush_lower_wb = WireInit(Bool(),0.B)
|
||||
// val dec_tlu_i0_valid_r = WireInit(Bool(),0.B)
|
||||
//
|
||||
// val dec_pause_state = WireInit(Bool(),0.B)
|
||||
//
|
||||
// val dec_i0_icaf_type_d = WireInit(UInt(2.W),0.U) // i0 instruction access fault type
|
||||
//
|
||||
// val dec_tlu_flush_extint = WireInit(Bool(),0.B)// Fast ext int started
|
||||
//
|
||||
val dec_i0_inst_wb1 = WireInit(UInt(32.W),0.U)
|
||||
val dec_i0_pc_wb1 = WireInit(UInt(32.W),0.U)
|
||||
val dec_tlu_i0_valid_wb1 = WireInit(UInt(1.W),0.U)
|
||||
val dec_tlu_int_valid_wb1 = WireInit(UInt(1.W),0.U)
|
||||
|
||||
val dec_tlu_exc_cause_wb1 = WireInit(UInt(5.W),0.U)
|
||||
val dec_tlu_mtval_wb1 = WireInit(UInt(32.W),0.U)
|
||||
val dec_tlu_i0_exc_valid_wb1 = WireInit(Bool(),0.B)
|
||||
//
|
||||
// val div_waddr_wb = WireInit(UInt(5.W),0.U)
|
||||
//
|
||||
// val dec_div_active = WireInit(Bool(),0.B)
|
||||
|
||||
|
||||
//--------------------------------------------------------------------------//
|
||||
val instbuff = Module(new el2_dec_ib_ctl)
|
||||
val decode = Module(new el2_dec_decode_ctl)
|
||||
val gpr = Module(new el2_dec_gpr_ctl)
|
||||
val tlu = Module(new el2_dec_tlu_ctl)
|
||||
val dec_trigger = Module(new el2_dec_trigger)
|
||||
|
||||
//instbuff.io <> io // error "Connection between left (el2_dec_ib_ctl_IO(IO io in el2_dec_ib_ctl)) and source (el2_dec_IO("
|
||||
//--------------------------------------------------------------------------//
|
||||
|
||||
//connections for el2_dec_Ib
|
||||
//inputs
|
||||
instbuff.io.dbg_cmd_valid := io.dbg_cmd_valid
|
||||
instbuff.io.dbg_cmd_write := io.dbg_cmd_write
|
||||
instbuff.io.dbg_cmd_type := io.dbg_cmd_type
|
||||
instbuff.io.dbg_cmd_addr := io.dbg_cmd_addr
|
||||
instbuff.io.i0_brp := io.i0_brp
|
||||
instbuff.io.ifu_i0_bp_index := io.ifu_i0_bp_index
|
||||
instbuff.io.ifu_i0_bp_fghr := io.ifu_i0_bp_fghr
|
||||
instbuff.io.ifu_i0_bp_btag := io.ifu_i0_bp_btag
|
||||
instbuff.io.ifu_i0_pc4 := io.ifu_i0_pc4
|
||||
instbuff.io.ifu_i0_valid := io.ifu_i0_valid
|
||||
instbuff.io.ifu_i0_icaf := io.ifu_i0_icaf
|
||||
instbuff.io.ifu_i0_icaf_type := io.ifu_i0_icaf_type
|
||||
instbuff.io.ifu_i0_icaf_f1 := io.ifu_i0_icaf_f1
|
||||
instbuff.io.ifu_i0_dbecc := io.ifu_i0_dbecc
|
||||
instbuff.io.ifu_i0_instr := io.ifu_i0_instr
|
||||
instbuff.io.ifu_i0_pc := io.ifu_i0_pc
|
||||
//outputs
|
||||
decode.io.dec_ib0_valid_d := instbuff.io.dec_ib0_valid_d
|
||||
decode.io.dec_i0_icaf_type_d :=instbuff.io.dec_i0_icaf_type_d
|
||||
decode.io.dec_i0_instr_d :=instbuff.io.dec_i0_instr_d
|
||||
decode.io.dec_i0_pc_d :=instbuff.io.dec_i0_pc_d
|
||||
decode.io.dec_i0_pc4_d :=instbuff.io.dec_i0_pc4_d
|
||||
decode.io.dec_i0_brp :=instbuff.io.dec_i0_brp
|
||||
decode.io.dec_i0_bp_index :=instbuff.io.dec_i0_bp_index
|
||||
decode.io.dec_i0_bp_fghr :=instbuff.io.dec_i0_bp_fghr
|
||||
decode.io.dec_i0_bp_btag :=instbuff.io.dec_i0_bp_btag
|
||||
decode.io.dec_i0_icaf_d :=instbuff.io.dec_i0_icaf_d
|
||||
decode.io.dec_i0_icaf_f1_d :=instbuff.io.dec_i0_icaf_f1_d
|
||||
decode.io.dec_i0_dbecc_d :=instbuff.io.dec_i0_dbecc_d
|
||||
io.dec_debug_wdata_rs1_d := instbuff.io.dec_debug_wdata_rs1_d
|
||||
decode.io.dec_debug_fence_d :=instbuff.io.dec_debug_fence_d
|
||||
//--------------------------------------------------------------------------//
|
||||
|
||||
//connections for dec_trigger
|
||||
//dec_trigger.io <> io
|
||||
//inputs
|
||||
dec_trigger.io.dec_i0_pc_d := instbuff.io.dec_i0_pc_d
|
||||
dec_trigger.io.trigger_pkt_any := tlu.io.trigger_pkt_any
|
||||
//output
|
||||
val dec_i0_trigger_match_d = dec_trigger.io.dec_i0_trigger_match_d
|
||||
dontTouch(dec_i0_trigger_match_d)
|
||||
//--------------------------------------------------------------------------//
|
||||
|
||||
//connections for el2_dec_decode
|
||||
// decode.io <> io
|
||||
//inputs
|
||||
decode.io.dec_tlu_flush_extint := tlu.io.dec_tlu_flush_extint
|
||||
decode.io.dec_tlu_force_halt := tlu.io.dec_tlu_force_halt
|
||||
decode.io.ifu_i0_cinst := io.ifu_i0_cinst
|
||||
decode.io.lsu_nonblock_load_valid_m := io.lsu_nonblock_load_valid_m
|
||||
decode.io.lsu_nonblock_load_tag_m := io.lsu_nonblock_load_tag_m
|
||||
decode.io.lsu_nonblock_load_inv_r := io.lsu_nonblock_load_inv_r
|
||||
decode.io.lsu_nonblock_load_inv_tag_r := io.lsu_nonblock_load_inv_tag_r
|
||||
decode.io.lsu_nonblock_load_data_valid := io.lsu_nonblock_load_data_valid
|
||||
decode.io.lsu_nonblock_load_data_error := io.lsu_nonblock_load_data_error
|
||||
decode.io.lsu_nonblock_load_data_tag := io.lsu_nonblock_load_data_tag
|
||||
decode.io.lsu_nonblock_load_data := io.lsu_nonblock_load_data
|
||||
decode.io.dec_i0_trigger_match_d := dec_i0_trigger_match_d
|
||||
decode.io.dec_tlu_wr_pause_r := tlu.io.dec_tlu_wr_pause_r
|
||||
decode.io.dec_tlu_pipelining_disable := tlu.io.dec_tlu_pipelining_disable
|
||||
decode.io.lsu_trigger_match_m := io.lsu_trigger_match_m
|
||||
decode.io.lsu_pmu_misaligned_m := io.lsu_pmu_bus_misaligned
|
||||
decode.io.dec_tlu_debug_stall := tlu.io.dec_tlu_debug_stall
|
||||
decode.io.dec_tlu_flush_leak_one_r := tlu.io.dec_tlu_flush_leak_one_r
|
||||
decode.io.dec_debug_fence_d := instbuff.io.dec_debug_fence_d
|
||||
decode.io.dbg_cmd_wrdata := io.dbg_cmd_wrdata
|
||||
decode.io.dec_i0_icaf_d := instbuff.io.dec_i0_icaf_d
|
||||
decode.io.dec_i0_icaf_f1_d := instbuff.io.dec_i0_icaf_f1_d
|
||||
decode.io.dec_i0_icaf_type_d := instbuff.io.dec_i0_icaf_type_d
|
||||
decode.io.dec_i0_dbecc_d := instbuff.io.dec_i0_dbecc_d
|
||||
decode.io.dec_i0_brp := instbuff.io.dec_i0_brp
|
||||
decode.io.dec_i0_bp_index := instbuff.io.dec_i0_bp_index
|
||||
decode.io.dec_i0_bp_fghr := instbuff.io.dec_i0_bp_fghr
|
||||
decode.io.dec_i0_bp_btag := instbuff.io.dec_i0_bp_btag
|
||||
decode.io.dec_i0_pc_d := instbuff.io.dec_i0_pc_d
|
||||
decode.io.lsu_idle_any := io.lsu_idle_any
|
||||
decode.io.lsu_load_stall_any := io.lsu_load_stall_any
|
||||
decode.io.lsu_store_stall_any := io.lsu_store_stall_any
|
||||
decode.io.dma_dccm_stall_any := io.dma_dccm_stall_any
|
||||
decode.io.exu_div_wren := io.exu_div_wren
|
||||
decode.io.dec_tlu_i0_kill_writeb_wb := tlu.io.dec_tlu_i0_kill_writeb_wb
|
||||
decode.io.dec_tlu_flush_lower_wb := tlu.io.dec_tlu_flush_lower_wb
|
||||
decode.io.dec_tlu_i0_kill_writeb_r := tlu.io.dec_tlu_i0_kill_writeb_r
|
||||
decode.io.dec_tlu_flush_lower_r := tlu.io.dec_tlu_flush_lower_r
|
||||
decode.io.dec_tlu_flush_pause_r := tlu.io.dec_tlu_flush_pause_r
|
||||
decode.io.dec_tlu_presync_d := tlu.io.dec_tlu_presync_d
|
||||
decode.io.dec_tlu_postsync_d := tlu.io.dec_tlu_postsync_d
|
||||
decode.io.dec_i0_pc4_d := instbuff.io.dec_i0_pc_d
|
||||
decode.io.dec_csr_rddata_d := tlu.io.dec_csr_rddata_d
|
||||
decode.io.dec_csr_legal_d := tlu.io.dec_csr_legal_d
|
||||
decode.io.exu_csr_rs1_x := io.exu_csr_rs1_x
|
||||
decode.io.lsu_result_m := io.lsu_result_m
|
||||
decode.io.lsu_result_corr_r := io.lsu_result_corr_r
|
||||
decode.io.exu_flush_final := io.exu_flush_final
|
||||
decode.io.exu_i0_pc_x := io.exu_i0_pc_x
|
||||
decode.io.dec_i0_instr_d := instbuff.io.dec_i0_instr_d
|
||||
decode.io.dec_ib0_valid_d := instbuff.io.dec_ib0_valid_d
|
||||
decode.io.exu_i0_result_x := io.exu_i0_result_x
|
||||
//decode.io.clk := io.clk
|
||||
decode.io.free_clk := io.free_clk
|
||||
decode.io.active_clk := io.active_clk
|
||||
decode.io.clk_override := tlu.io.dec_tlu_dec_clk_override
|
||||
// decode.io.rst_l := io.rst_l
|
||||
decode.io.scan_mode := io.scan_mode
|
||||
//outputs
|
||||
io.dec_extint_stall := decode.io.dec_extint_stall
|
||||
dec_i0_inst_wb1 := decode.io.dec_i0_inst_wb1 //for tracer
|
||||
dec_i0_pc_wb1 := decode.io.dec_i0_pc_wb1 //for tracer
|
||||
io.dec_i0_rs1_en_d := decode.io.dec_i0_rs1_en_d
|
||||
io.dec_i0_rs2_en_d := decode.io.dec_i0_rs2_en_d
|
||||
gpr.io.raddr0 := decode.io.dec_i0_rs1_d
|
||||
gpr.io.raddr1 := decode.io.dec_i0_rs2_d
|
||||
io.dec_i0_immed_d := decode.io.dec_i0_immed_d
|
||||
io.dec_i0_br_immed_d := decode.io.dec_i0_br_immed_d
|
||||
io.i0_ap := decode.io.i0_ap
|
||||
io.dec_i0_decode_d := decode.io.dec_i0_decode_d
|
||||
io.dec_i0_alu_decode_d := decode.io.dec_i0_alu_decode_d
|
||||
io.dec_i0_rs1_bypass_data_d := decode.io.dec_i0_rs1_bypass_data_d
|
||||
io.dec_i0_rs2_bypass_data_d := decode.io.dec_i0_rs2_bypass_data_d
|
||||
gpr.io.waddr0 := decode.io.dec_i0_waddr_r
|
||||
gpr.io.wen0 := decode.io.dec_i0_wen_r
|
||||
gpr.io.wd0 := decode.io.dec_i0_wdata_r
|
||||
io.dec_i0_select_pc_d := decode.io.dec_i0_select_pc_d
|
||||
io.dec_i0_rs1_bypass_en_d := decode.io.dec_i0_rs1_bypass_en_d
|
||||
io.dec_i0_rs2_bypass_en_d := decode.io.dec_i0_rs2_bypass_en_d
|
||||
io.lsu_p := decode.io.lsu_p
|
||||
io.mul_p := decode.io.mul_p
|
||||
io.div_p := decode.io.div_p
|
||||
gpr.io.waddr2 := decode.io.div_waddr_wb
|
||||
io.dec_div_cancel := decode.io.dec_div_cancel
|
||||
io.dec_lsu_valid_raw_d := decode.io.dec_lsu_valid_raw_d
|
||||
io.dec_lsu_offset_d := decode.io.dec_lsu_offset_d
|
||||
io.dec_csr_ren_d := decode.io.dec_csr_ren_d
|
||||
tlu.io.dec_csr_wen_unq_d := decode.io.dec_csr_wen_unq_d
|
||||
tlu.io.dec_csr_any_unq_d := decode.io.dec_csr_any_unq_d
|
||||
tlu.io.dec_csr_rdaddr_d := decode.io.dec_csr_rdaddr_d
|
||||
tlu.io.dec_csr_wen_r := decode.io.dec_csr_wen_r
|
||||
tlu.io.dec_csr_wraddr_r := decode.io.dec_csr_wraddr_r
|
||||
tlu.io.dec_csr_wrdata_r := decode.io.dec_csr_wrdata_r
|
||||
tlu.io.dec_csr_stall_int_ff := decode.io.dec_csr_stall_int_ff
|
||||
tlu.io.dec_tlu_i0_valid_r := decode.io.dec_tlu_i0_valid_r
|
||||
tlu.io.dec_tlu_packet_r := decode.io.dec_tlu_packet_r
|
||||
tlu.io.dec_tlu_i0_pc_r := decode.io.dec_tlu_i0_pc_r
|
||||
tlu.io.dec_illegal_inst := decode.io.dec_illegal_inst
|
||||
io.pred_correct_npc_x := decode.io.pred_correct_npc_x
|
||||
io.dec_i0_predict_p_d := decode.io.dec_i0_predict_p_d
|
||||
io.i0_predict_fghr_d := decode.io.i0_predict_fghr_d
|
||||
io.i0_predict_index_d := decode.io.i0_predict_index_d
|
||||
io.i0_predict_btag_d := decode.io.i0_predict_btag_d
|
||||
io.dec_data_en := decode.io.dec_data_en
|
||||
io.dec_ctl_en := decode.io.dec_ctl_en
|
||||
tlu.io.dec_pmu_postsync_stall := decode.io.dec_pmu_instr_decoded
|
||||
tlu.io.dec_pmu_postsync_stall := decode.io.dec_pmu_decode_stall
|
||||
tlu.io.dec_pmu_postsync_stall := decode.io.dec_pmu_presync_stall
|
||||
tlu.io.dec_pmu_postsync_stall := decode.io.dec_pmu_postsync_stall
|
||||
tlu.io.dec_pmu_postsync_stall := decode.io.dec_nonblock_load_wen
|
||||
tlu.io.dec_pmu_postsync_stall := decode.io.dec_nonblock_load_waddr
|
||||
tlu.io.dec_pmu_postsync_stall := decode.io.dec_pause_state
|
||||
io.dec_pause_state_cg := decode.io.dec_pause_state_cg
|
||||
tlu.io.dec_div_active := decode.io.dec_div_active
|
||||
//--------------------------------------------------------------------------//
|
||||
|
||||
|
||||
//connections for gprfile
|
||||
// gpr.io <> io
|
||||
//inputs
|
||||
gpr.io.raddr0 := decode.io.dec_i0_rs1_d
|
||||
gpr.io.raddr1 := decode.io.dec_i0_rs2_d
|
||||
gpr.io.wen0 := decode.io.dec_i0_wen_r
|
||||
gpr.io.waddr0 := decode.io.dec_i0_waddr_r
|
||||
gpr.io.wd0 := decode.io.dec_i0_wdata_r
|
||||
gpr.io.wen1 := decode.io.dec_nonblock_load_wen
|
||||
gpr.io.waddr1 := decode.io.dec_nonblock_load_waddr
|
||||
gpr.io.wd1 := io.lsu_nonblock_load_data
|
||||
gpr.io.wen2 := io.exu_div_wren
|
||||
gpr.io.waddr2 := decode.io.div_waddr_wb
|
||||
gpr.io.wd2 := io.exu_div_result
|
||||
//gpr.io.clk := io.clk
|
||||
//gpr.io.rst_l := io.rst_l
|
||||
gpr.io.scan_mode := io.scan_mode
|
||||
// outputs
|
||||
io.gpr_i0_rs1_d := gpr.io.rd0
|
||||
io.gpr_i0_rs2_d := gpr.io.rd1
|
||||
//--------------------------------------------------------------------------//
|
||||
|
||||
|
||||
|
||||
//connection for dec_tlu
|
||||
// tlu.io <> io
|
||||
//inputs
|
||||
//tlu.io.clk := io.clk
|
||||
tlu.io.active_clk := io.active_clk
|
||||
tlu.io.free_clk := io.free_clk
|
||||
// tlu.io.rst_l := io.rst_l
|
||||
tlu.io.scan_mode := io.scan_mode
|
||||
tlu.io.rst_vec := io.rst_vec
|
||||
tlu.io.nmi_int := io.nmi_int
|
||||
tlu.io.nmi_vec := io.nmi_vec
|
||||
tlu.io.i_cpu_halt_req := io.i_cpu_halt_req
|
||||
tlu.io.i_cpu_run_req := io.i_cpu_run_req
|
||||
tlu.io.lsu_fastint_stall_any := io.lsu_fastint_stall_any
|
||||
tlu.io.ifu_pmu_instr_aligned := io.ifu_pmu_instr_aligned
|
||||
tlu.io.ifu_pmu_fetch_stall := io.ifu_pmu_fetch_stall
|
||||
tlu.io.ifu_pmu_ic_miss := io.ifu_pmu_ic_miss
|
||||
tlu.io.ifu_pmu_ic_hit := io.ifu_pmu_ic_hit
|
||||
tlu.io.ifu_pmu_bus_error := io.ifu_pmu_bus_error
|
||||
tlu.io.ifu_pmu_bus_busy := io.ifu_pmu_bus_busy
|
||||
tlu.io.ifu_pmu_bus_trxn := io.ifu_pmu_bus_trxn
|
||||
tlu.io.dec_pmu_instr_decoded := decode.io.dec_pmu_instr_decoded
|
||||
tlu.io.dec_pmu_decode_stall := decode.io.dec_pmu_decode_stall
|
||||
tlu.io.dec_pmu_presync_stall := decode.io.dec_pmu_presync_stall
|
||||
tlu.io.dec_pmu_postsync_stall := decode.io.dec_pmu_postsync_stall
|
||||
tlu.io.lsu_store_stall_any := io.lsu_store_stall_any
|
||||
tlu.io.dma_dccm_stall_any := io.dma_dccm_stall_any
|
||||
tlu.io.dma_iccm_stall_any := io.dma_iccm_stall_any
|
||||
tlu.io.exu_pmu_i0_br_misp := io.exu_pmu_i0_br_misp
|
||||
tlu.io.exu_pmu_i0_br_ataken := io.exu_pmu_i0_br_ataken
|
||||
tlu.io.exu_pmu_i0_pc4 := io.exu_pmu_i0_pc4
|
||||
tlu.io.lsu_pmu_bus_trxn := io.lsu_pmu_bus_trxn
|
||||
tlu.io.lsu_pmu_bus_misaligned := io.lsu_pmu_bus_misaligned
|
||||
tlu.io.lsu_pmu_bus_error := io.lsu_pmu_bus_error
|
||||
tlu.io.lsu_pmu_bus_busy := io.lsu_pmu_bus_busy
|
||||
tlu.io.lsu_pmu_load_external_m := io.lsu_pmu_load_external_m
|
||||
tlu.io.lsu_pmu_store_external_m := io.lsu_pmu_store_external_m
|
||||
tlu.io.dma_pmu_dccm_read := io.dma_pmu_dccm_read
|
||||
tlu.io.dma_pmu_dccm_write := io.dma_pmu_dccm_write
|
||||
tlu.io.dma_pmu_any_read := io.dma_pmu_any_read
|
||||
tlu.io.dma_pmu_any_write := io.dma_pmu_any_write
|
||||
tlu.io.lsu_fir_addr := io.lsu_fir_addr
|
||||
tlu.io.lsu_fir_error := io.lsu_fir_error
|
||||
tlu.io.iccm_dma_sb_error := io.iccm_dma_sb_error
|
||||
tlu.io.lsu_error_pkt_r := io.lsu_error_pkt_r
|
||||
tlu.io.lsu_single_ecc_error_incr := io.lsu_single_ecc_error_incr
|
||||
tlu.io.dec_pause_state := decode.io.dec_pause_state
|
||||
tlu.io.lsu_imprecise_error_store_any := io.lsu_imprecise_error_store_any
|
||||
tlu.io.lsu_imprecise_error_load_any := io.lsu_imprecise_error_load_any
|
||||
tlu.io.lsu_imprecise_error_addr_any := io.lsu_imprecise_error_addr_any
|
||||
tlu.io.dec_csr_wen_unq_d := decode.io.dec_csr_wen_unq_d
|
||||
tlu.io.dec_csr_any_unq_d := decode.io.dec_csr_any_unq_d
|
||||
tlu.io.dec_csr_rdaddr_d := decode.io.dec_csr_rdaddr_d
|
||||
tlu.io.dec_csr_wen_r := decode.io.dec_csr_wen_r
|
||||
tlu.io.dec_csr_wraddr_r := decode.io.dec_csr_wraddr_r
|
||||
tlu.io.dec_csr_wrdata_r := decode.io.dec_csr_wrdata_r
|
||||
tlu.io.dec_csr_stall_int_ff := decode.io.dec_csr_stall_int_ff
|
||||
tlu.io.dec_tlu_i0_valid_r := decode.io.dec_tlu_i0_valid_r
|
||||
tlu.io.exu_npc_r := io.exu_npc_r
|
||||
tlu.io.dec_tlu_i0_pc_r := decode.io.dec_tlu_i0_pc_r
|
||||
tlu.io.dec_tlu_packet_r := decode.io.dec_tlu_packet_r
|
||||
tlu.io.dec_illegal_inst := decode.io.dec_illegal_inst
|
||||
tlu.io.dec_i0_decode_d := decode.io.dec_i0_decode_d
|
||||
tlu.io.exu_i0_br_hist_r := io.exu_i0_br_hist_r
|
||||
tlu.io.exu_i0_br_error_r := io.exu_i0_br_error_r
|
||||
tlu.io.exu_i0_br_start_error_r := io.exu_i0_br_start_error_r
|
||||
tlu.io.exu_i0_br_valid_r := io.exu_i0_br_valid_r
|
||||
tlu.io.exu_i0_br_mp_r := io.exu_i0_br_mp_r
|
||||
tlu.io.exu_i0_br_middle_r := io.exu_i0_br_middle_r
|
||||
tlu.io.exu_i0_br_way_r := io.exu_i0_br_way_r
|
||||
tlu.io.dbg_halt_req := io.dbg_halt_req
|
||||
tlu.io.dbg_resume_req := io.dbg_resume_req
|
||||
tlu.io.ifu_miss_state_idle := io.ifu_miss_state_idle
|
||||
tlu.io.lsu_idle_any := io.lsu_idle_any
|
||||
tlu.io.dec_div_active := decode.io.dec_div_active
|
||||
tlu.io.ifu_ic_error_start := io.ifu_ic_error_start
|
||||
tlu.io.ifu_iccm_rd_ecc_single_err := io.ifu_iccm_rd_ecc_single_err
|
||||
tlu.io.ifu_ic_debug_rd_data := io.ifu_ic_debug_rd_data
|
||||
tlu.io.ifu_ic_debug_rd_data_valid := io.ifu_ic_debug_rd_data_valid
|
||||
tlu.io.pic_claimid := io.pic_claimid
|
||||
tlu.io.pic_pl := io.pic_pl
|
||||
tlu.io.mhwakeup := io.mhwakeup
|
||||
tlu.io.mexintpend := io.mexintpend
|
||||
tlu.io.timer_int := io.timer_int
|
||||
tlu.io.soft_int := io.soft_int
|
||||
tlu.io.core_id := io.core_id
|
||||
tlu.io.mpc_debug_halt_req := io.mpc_debug_halt_req
|
||||
tlu.io.mpc_debug_run_req := io.mpc_debug_run_req
|
||||
tlu.io.mpc_reset_run_req := io.mpc_reset_run_req
|
||||
//outputs
|
||||
io.dec_dbg_cmd_done := tlu.io.dec_dbg_cmd_done
|
||||
io.dec_dbg_cmd_fail := tlu.io.dec_dbg_cmd_fail
|
||||
io.dec_tlu_dbg_halted := tlu.io.dec_tlu_dbg_halted
|
||||
io.dec_tlu_debug_mode := tlu.io.dec_tlu_debug_mode
|
||||
io.dec_tlu_resume_ack := tlu.io.dec_tlu_resume_ack
|
||||
decode.io.dec_tlu_debug_stall := tlu.io.dec_tlu_debug_stall
|
||||
io.dec_tlu_flush_noredir_r := tlu.io.dec_tlu_flush_noredir_r
|
||||
io.dec_tlu_mpc_halted_only := tlu.io.dec_tlu_mpc_halted_only
|
||||
io.dec_tlu_flush_leak_one_r := tlu.io.dec_tlu_flush_leak_one_r
|
||||
io.dec_tlu_flush_err_r := tlu.io.dec_tlu_flush_err_r
|
||||
decode.io.dec_tlu_flush_extint := tlu.io.dec_tlu_flush_extint
|
||||
io.dec_tlu_meihap := tlu.io.dec_tlu_meihap
|
||||
io.trigger_pkt_any := tlu.io.trigger_pkt_any
|
||||
io.dec_tlu_ic_diag_pkt := tlu.io.dec_tlu_ic_diag_pkt
|
||||
io.o_cpu_halt_status := tlu.io.o_cpu_halt_status
|
||||
io.o_cpu_halt_ack := tlu.io.o_cpu_halt_ack
|
||||
io.o_cpu_run_ack := tlu.io.o_cpu_run_ack
|
||||
io.o_debug_mode_status := tlu.io.o_debug_mode_status
|
||||
io.mpc_debug_halt_ack := tlu.io.mpc_debug_halt_ack
|
||||
io.mpc_debug_run_ack := tlu.io.mpc_debug_run_ack
|
||||
io.debug_brkpt_status := tlu.io.debug_brkpt_status
|
||||
io.dec_tlu_meicurpl := tlu.io.dec_tlu_meicurpl
|
||||
io.dec_tlu_meipt := tlu.io.dec_tlu_meipt
|
||||
decode.io.dec_csr_rddata_d := tlu.io.dec_csr_rddata_d
|
||||
decode.io.dec_csr_legal_d := tlu.io.dec_csr_legal_d
|
||||
io.dec_tlu_br0_r_pkt := tlu.io.dec_tlu_br0_r_pkt
|
||||
decode.io.dec_tlu_i0_kill_writeb_wb := tlu.io.dec_tlu_i0_kill_writeb_wb
|
||||
decode.io.dec_tlu_flush_lower_wb := tlu.io.dec_tlu_flush_lower_wb
|
||||
io.dec_tlu_i0_commit_cmt := tlu.io.dec_tlu_i0_commit_cmt
|
||||
io.dec_tlu_i0_kill_writeb_r := tlu.io.dec_tlu_i0_kill_writeb_r
|
||||
io.dec_tlu_flush_lower_r := tlu.io.dec_tlu_flush_lower_r
|
||||
io.dec_tlu_flush_path_r := tlu.io.dec_tlu_flush_path_r
|
||||
io.dec_tlu_fence_i_r := tlu.io.dec_tlu_fence_i_r
|
||||
decode.io.dec_tlu_wr_pause_r := tlu.io.dec_tlu_wr_pause_r
|
||||
decode.io.dec_tlu_flush_pause_r := tlu.io.dec_tlu_flush_pause_r
|
||||
decode.io.dec_tlu_presync_d := tlu.io.dec_tlu_presync_d
|
||||
decode.io.dec_tlu_postsync_d := tlu.io.dec_tlu_postsync_d
|
||||
io.dec_tlu_mrac_ff := tlu.io.dec_tlu_mrac_ff
|
||||
io.dec_tlu_force_halt := tlu.io.dec_tlu_force_halt
|
||||
io.dec_tlu_perfcnt0 := tlu.io.dec_tlu_perfcnt0
|
||||
io.dec_tlu_perfcnt1 := tlu.io.dec_tlu_perfcnt1
|
||||
io.dec_tlu_perfcnt2 := tlu.io.dec_tlu_perfcnt2
|
||||
io.dec_tlu_perfcnt3 := tlu.io.dec_tlu_perfcnt3
|
||||
dec_tlu_i0_exc_valid_wb1 := tlu.io.dec_tlu_i0_exc_valid_wb1
|
||||
dec_tlu_i0_valid_wb1 := tlu.io.dec_tlu_i0_valid_wb1
|
||||
dec_tlu_int_valid_wb1 := tlu.io.dec_tlu_int_valid_wb1
|
||||
dec_tlu_exc_cause_wb1 := tlu.io.dec_tlu_exc_cause_wb1
|
||||
dec_tlu_mtval_wb1 := tlu.io.dec_tlu_mtval_wb1
|
||||
io.dec_tlu_external_ldfwd_disable := tlu.io.dec_tlu_external_ldfwd_disable
|
||||
io.dec_tlu_sideeffect_posted_disable := tlu.io.dec_tlu_sideeffect_posted_disable
|
||||
io.dec_tlu_core_ecc_disable := tlu.io.dec_tlu_core_ecc_disable
|
||||
io.dec_tlu_bpred_disable := tlu.io.dec_tlu_bpred_disable
|
||||
io.dec_tlu_wb_coalescing_disable := tlu.io.dec_tlu_wb_coalescing_disable
|
||||
// := tlu.io.dec_tlu_pipelining_disable
|
||||
io.dec_tlu_dma_qos_prty := tlu.io.dec_tlu_dma_qos_prty
|
||||
io.dec_tlu_misc_clk_override := tlu.io.dec_tlu_misc_clk_override
|
||||
//decode.io.clk_override := tlu.io.dec_tlu_dec_clk_override
|
||||
io.dec_tlu_ifu_clk_override := tlu.io.dec_tlu_ifu_clk_override
|
||||
io.dec_tlu_lsu_clk_override := tlu.io.dec_tlu_lsu_clk_override
|
||||
io.dec_tlu_bus_clk_override := tlu.io.dec_tlu_bus_clk_override
|
||||
io.dec_tlu_pic_clk_override := tlu.io.dec_tlu_pic_clk_override
|
||||
io.dec_tlu_dccm_clk_override := tlu.io.dec_tlu_dccm_clk_override
|
||||
io.dec_tlu_icm_clk_override := tlu.io.dec_tlu_icm_clk_override
|
||||
|
||||
//--------------------------------------------------------------------------//
|
||||
|
||||
|
||||
|
||||
// debug command read data
|
||||
io.dec_dbg_rddata := decode.io.dec_i0_wdata_r
|
||||
}
|
||||
object dec_main extends App {
|
||||
println((new chisel3.stage.ChiselStage).emitVerilog( new el2_dec()))
|
||||
}
|
||||
|
|
@ -0,0 +1,827 @@
|
|||
package dec
|
||||
import chisel3._
|
||||
import scala.collection._
|
||||
import chisel3.util._
|
||||
import include._
|
||||
import lib._
|
||||
|
||||
class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
|
||||
val io = IO(new Bundle{
|
||||
|
||||
val dec_tlu_flush_extint = Input(Bool())
|
||||
val dec_tlu_force_halt = Input(Bool()) // invalidate nonblock load cam on a force halt event
|
||||
val dec_extint_stall = Output(Bool())
|
||||
val ifu_i0_cinst = Input(UInt(16.W)) // 16b compressed instruction
|
||||
val dec_i0_inst_wb1 = Output(UInt(32.W)) // 32b instruction at wb+1 for trace encoder
|
||||
val dec_i0_pc_wb1 = Output(UInt(31.W)) // 31b pc at wb+1 for trace encoder
|
||||
val lsu_nonblock_load_valid_m = Input(Bool()) // valid nonblock load at m
|
||||
val lsu_nonblock_load_tag_m = Input(UInt(LSU_NUM_NBLOAD_WIDTH.W)) // -> corresponding tag
|
||||
val lsu_nonblock_load_inv_r = Input(Bool()) // invalidate request for nonblock load r
|
||||
val lsu_nonblock_load_inv_tag_r = Input(UInt(LSU_NUM_NBLOAD_WIDTH.W)) // -> corresponding tag
|
||||
val lsu_nonblock_load_data_valid = Input(Bool()) // valid nonblock load data back
|
||||
val lsu_nonblock_load_data_error = Input(Bool()) // nonblock load bus error
|
||||
val lsu_nonblock_load_data_tag = Input(UInt(LSU_NUM_NBLOAD_WIDTH.W)) // -> corresponding tag
|
||||
val lsu_nonblock_load_data = Input(UInt(32.W)) // nonblock load data
|
||||
val dec_i0_trigger_match_d = Input(UInt(4.W)) // i0 decode trigger matches
|
||||
val dec_tlu_wr_pause_r = Input(Bool()) // pause instruction at r
|
||||
val dec_tlu_pipelining_disable = Input(Bool()) // pipeline disable - presync, i0 decode only
|
||||
val lsu_trigger_match_m = Input(UInt(4.W)) // lsu trigger matches
|
||||
val lsu_pmu_misaligned_m = Input(Bool()) // perf mon: load/store misalign
|
||||
val dec_tlu_debug_stall = Input(Bool()) // debug stall decode
|
||||
val dec_tlu_flush_leak_one_r = Input(Bool()) // leak1 instruction
|
||||
val dec_debug_fence_d = Input(Bool()) // debug fence instruction
|
||||
val dbg_cmd_wrdata = Input(UInt(2.W)) // disambiguate fence, fence_i
|
||||
val dec_i0_icaf_d = Input(Bool()) // icache access fault
|
||||
val dec_i0_icaf_f1_d = Input(Bool()) // i0 instruction access fault at decode for f1 fetch group
|
||||
val dec_i0_icaf_type_d = Input(UInt(2.W)) // i0 instruction access fault type
|
||||
val dec_i0_dbecc_d = Input(Bool()) // icache/iccm double-bit error
|
||||
val dec_i0_brp = Input(new el2_br_pkt_t) // branch packet
|
||||
val dec_i0_bp_index = Input(UInt(((BTB_ADDR_HI-BTB_ADDR_LO)+1).W)) // i0 branch index
|
||||
val dec_i0_bp_fghr = Input(UInt(BHT_GHR_SIZE.W)) // BP FGHR
|
||||
val dec_i0_bp_btag = Input(UInt(BTB_BTAG_SIZE.W)) // BP tag
|
||||
val dec_i0_pc_d = Input(UInt(31.W)) // pc
|
||||
val lsu_idle_any = Input(Bool()) // lsu idle: if fence instr & !!!!!!!!!!!!!!!!!!!!!!!!!lsu_idle then stall decode
|
||||
val lsu_load_stall_any = Input(Bool()) // stall any load at decode
|
||||
val lsu_store_stall_any = Input(Bool()) // stall any store at decode6
|
||||
val dma_dccm_stall_any = Input(Bool()) // stall any load/store at decode
|
||||
val exu_div_wren = Input(Bool()) // nonblocking divide write enable to GPR.
|
||||
val dec_tlu_i0_kill_writeb_wb = Input(Bool()) // I0 is flushed, don't writeback any results to arch state
|
||||
val dec_tlu_flush_lower_wb = Input(Bool()) // trap lower flush
|
||||
val dec_tlu_i0_kill_writeb_r = Input(Bool()) // I0 is flushed, don't writeback any results to arch state
|
||||
val dec_tlu_flush_lower_r = Input(Bool()) // trap lower flush
|
||||
val dec_tlu_flush_pause_r = Input(Bool()) // don't clear pause state on initial lower flush
|
||||
val dec_tlu_presync_d = Input(Bool()) // CSR read needs to be presync'd
|
||||
val dec_tlu_postsync_d = Input(Bool()) // CSR ops that need to be postsync'd
|
||||
val dec_i0_pc4_d = Input(Bool()) // inst is 4B inst else 2B
|
||||
val dec_csr_rddata_d = Input(UInt(32.W)) // csr read data at wb
|
||||
val dec_csr_legal_d = Input(Bool()) // csr indicates legal operation
|
||||
val exu_csr_rs1_x = Input(UInt(32.W)) // rs1 for csr instr
|
||||
val lsu_result_m = Input(UInt(32.W)) // load result
|
||||
val lsu_result_corr_r = Input(UInt(32.W)) // load result - corrected data for writing gpr's, not for bypassing
|
||||
val exu_flush_final = Input(Bool()) // lower flush or i0 flush at X or D
|
||||
val exu_i0_pc_x = Input(UInt(31.W)) // pcs at e1
|
||||
val dec_i0_instr_d = Input(UInt(32.W)) // inst at decode
|
||||
val dec_ib0_valid_d = Input(Bool()) // inst valid at decode
|
||||
val exu_i0_result_x = Input(UInt(32.W)) // from primary alu's
|
||||
val free_clk = Input(Clock())
|
||||
val active_clk = Input(Clock()) // clk except for halt / pause
|
||||
val clk_override = Input(Bool()) // test stuff
|
||||
|
||||
val dec_i0_rs1_en_d = Output(Bool()) // rs1 enable at decode
|
||||
val dec_i0_rs2_en_d = Output(Bool())
|
||||
val dec_i0_rs1_d = Output(UInt(5.W)) // rs1 logical source
|
||||
val dec_i0_rs2_d = Output(UInt(5.W))
|
||||
val dec_i0_immed_d = Output(UInt(32.W)) // 32b immediate data decode
|
||||
val dec_i0_br_immed_d = Output(UInt(12.W)) // 12b branch immediate
|
||||
val i0_ap = Output(new el2_alu_pkt_t) // alu packets
|
||||
val dec_i0_decode_d = Output(Bool()) // i0 decode
|
||||
val dec_i0_alu_decode_d = Output(Bool()) // decode to D-stage alu
|
||||
val dec_i0_rs1_bypass_data_d = Output(UInt(32.W)) // i0 rs1 bypass data
|
||||
val dec_i0_rs2_bypass_data_d = Output(UInt(32.W)) // i0 rs2 bypass data
|
||||
val dec_i0_waddr_r = Output(UInt(5.W)) // i0 logical source to write to gpr's
|
||||
val dec_i0_wen_r = Output(Bool()) // i0 write enable
|
||||
val dec_i0_wdata_r = Output(UInt(32.W)) // i0 write data
|
||||
val dec_i0_select_pc_d = Output(Bool()) // i0 select pc for rs1 - branches
|
||||
val dec_i0_rs1_bypass_en_d = Output(UInt(2.W)) // i0 rs1 bypass enable
|
||||
val dec_i0_rs2_bypass_en_d = Output(UInt(2.W)) // i0 rs2 bypass enable
|
||||
val lsu_p = Output(new el2_lsu_pkt_t) // load/store packet
|
||||
val mul_p = Output(new el2_mul_pkt_t) // multiply packet
|
||||
val div_p = Output(new el2_div_pkt_t) // divide packet
|
||||
val div_waddr_wb = Output(UInt(5.W)) // DIV write address to GPR
|
||||
val dec_div_cancel = Output(Bool()) // cancel the divide operation
|
||||
val dec_lsu_valid_raw_d = Output(Bool())
|
||||
val dec_lsu_offset_d = Output(UInt(12.W))
|
||||
val dec_csr_ren_d = Output(Bool()) // valid csr decode
|
||||
val dec_csr_wen_unq_d = Output(Bool()) // valid csr with write - for csr legal
|
||||
val dec_csr_any_unq_d = Output(Bool()) // valid csr - for csr legal
|
||||
val dec_csr_rdaddr_d = Output(UInt(12.W)) // read address for csr
|
||||
val dec_csr_wen_r = Output(Bool()) // csr write enable at r
|
||||
val dec_csr_wraddr_r = Output(UInt(12.W)) // write address for csr
|
||||
val dec_csr_wrdata_r = Output(UInt(32.W)) // csr write data at r
|
||||
val dec_csr_stall_int_ff = Output(Bool()) // csr is mie/mstatus
|
||||
val dec_tlu_i0_valid_r = Output(Bool()) // i0 valid inst at c
|
||||
val dec_tlu_packet_r = Output(new el2_trap_pkt_t) // trap packet
|
||||
val dec_tlu_i0_pc_r = Output(UInt(31.W)) // i0 trap pc
|
||||
val dec_illegal_inst = Output(UInt(32.W)) // illegal inst
|
||||
val pred_correct_npc_x = Output(UInt(31.W)) // npc e2 if the prediction is correct
|
||||
val dec_i0_predict_p_d = Output(new el2_predict_pkt_t) // i0 predict packet decode
|
||||
val i0_predict_fghr_d = Output(UInt(BHT_GHR_SIZE.W)) // i0 predict fghr
|
||||
val i0_predict_index_d = Output(UInt(((BHT_ADDR_HI-BHT_ADDR_LO)+1).W)) // i0 predict index
|
||||
val i0_predict_btag_d = Output(UInt(BTB_BTAG_SIZE.W)) // i0_predict branch tag
|
||||
val dec_data_en = Output(UInt(2.W)) // clock-gating logic
|
||||
val dec_ctl_en = Output(UInt(2.W))
|
||||
val dec_pmu_instr_decoded = Output(Bool()) // number of instructions decode this cycle encoded
|
||||
val dec_pmu_decode_stall = Output(Bool()) // decode is stalled
|
||||
val dec_pmu_presync_stall = Output(Bool()) // decode has presync stall
|
||||
val dec_pmu_postsync_stall = Output(Bool()) // decode has postsync stall
|
||||
val dec_nonblock_load_wen = Output(Bool()) // write enable for nonblock load
|
||||
val dec_nonblock_load_waddr = Output(UInt(5.W)) // logical write addr for nonblock load
|
||||
val dec_pause_state = Output(Bool()) // core in pause state
|
||||
val dec_pause_state_cg = Output(Bool()) // pause state for clock-gating
|
||||
val dec_div_active = Output(Bool()) // non-block divide is active
|
||||
val scan_mode = Input(Bool())
|
||||
})
|
||||
/////////////////////////////////////////////////////////////////////////////////////////
|
||||
// //packets zero initialization
|
||||
io.mul_p := 0.U.asTypeOf(io.mul_p)
|
||||
// Vals defined
|
||||
val leak1_i1_stall_in = WireInit(UInt(1.W), 0.U)
|
||||
val leak1_i0_stall_in = WireInit(UInt(1.W), 0.U)
|
||||
val i0r = Wire(new el2_reg_pkt_t)
|
||||
val d_t = Wire(new el2_trap_pkt_t)
|
||||
val x_t = Wire(new el2_trap_pkt_t)
|
||||
val x_t_in = Wire(new el2_trap_pkt_t)
|
||||
val r_t = Wire(new el2_trap_pkt_t)
|
||||
val r_t_in = Wire(new el2_trap_pkt_t)
|
||||
val d_d = Wire(new el2_dest_pkt_t)
|
||||
val x_d = Wire(new el2_dest_pkt_t)
|
||||
val r_d = Wire(new el2_dest_pkt_t)
|
||||
val r_d_in = Wire(new el2_dest_pkt_t)
|
||||
val wbd = Wire(new el2_dest_pkt_t)
|
||||
val i0_d_c = Wire(new el2_class_pkt_t)
|
||||
val i0_rs1_class_d = Wire(new el2_class_pkt_t)
|
||||
val i0_rs2_class_d = Wire(new el2_class_pkt_t)
|
||||
val i0_rs1_depth_d = WireInit(UInt(2.W),0.U)
|
||||
val i0_rs2_depth_d = WireInit(UInt(2.W),0.U)
|
||||
val cam_wen=WireInit(UInt(LSU_NUM_NBLOAD.W), 0.U)
|
||||
val cam = Wire(Vec(LSU_NUM_NBLOAD,new el2_load_cam_pkt_t))
|
||||
val cam_write=WireInit(UInt(1.W), 0.U)
|
||||
val cam_inv_reset_val=Wire(Vec(LSU_NUM_NBLOAD,UInt(1.W)))
|
||||
val cam_data_reset_val=Wire(Vec(LSU_NUM_NBLOAD,UInt(1.W)))
|
||||
val nonblock_load_write=Wire(Vec(LSU_NUM_NBLOAD,UInt(1.W)))
|
||||
val cam_raw =Wire(Vec(LSU_NUM_NBLOAD,new el2_load_cam_pkt_t))
|
||||
val cam_in =Wire(Vec(LSU_NUM_NBLOAD,new el2_load_cam_pkt_t))
|
||||
//val i0_temp = Wire(new el2_inst_pkt_t)
|
||||
val i0_dp= Wire(new el2_dec_pkt_t)
|
||||
val i0_dp_raw= Wire(new el2_dec_pkt_t)
|
||||
val i0_rs1bypass = WireInit(UInt(3.W), 0.U)
|
||||
val i0_rs2bypass = WireInit(UInt(3.W), 0.U)
|
||||
val illegal_lockout = WireInit(UInt(1.W), 0.U)
|
||||
val postsync_stall = WireInit(UInt(1.W), 0.U)
|
||||
val ps_stall_in = WireInit(UInt(1.W), 0.U)
|
||||
val i0_pipe_en = WireInit(UInt(4.W), 0.U)
|
||||
val i0_load_block_d = WireInit(UInt(1.W), 0.U)
|
||||
val load_ldst_bypass_d = WireInit(UInt(1.W), 0.U)
|
||||
val store_data_bypass_d = WireInit(UInt(1.W), 0.U)
|
||||
val store_data_bypass_m = WireInit(UInt(1.W), 0.U)
|
||||
val tlu_wr_pause_r1 = WireInit(UInt(1.W), 0.U)
|
||||
val tlu_wr_pause_r2 = WireInit(UInt(1.W), 0.U)
|
||||
val leak1_i1_stall = WireInit(UInt(1.W), 0.U)
|
||||
val leak1_i0_stall = WireInit(UInt(1.W), 0.U)
|
||||
val pause_state = WireInit(Bool(), 0.B)
|
||||
val flush_final_r = WireInit(UInt(1.W), 0.U)
|
||||
val illegal_lockout_in = WireInit(UInt(1.W), 0.U)
|
||||
val lsu_idle = WireInit(Bool(), 0.B)
|
||||
val pause_state_in = WireInit(Bool(), 0.B)
|
||||
val leak1_mode = WireInit(UInt(1.W), 0.U)
|
||||
val i0_pcall = WireInit(UInt(1.W), 0.U)
|
||||
val i0_pja = WireInit(UInt(1.W), 0.U)
|
||||
val i0_pret = WireInit(UInt(1.W), 0.U)
|
||||
val i0_legal_decode_d = WireInit(UInt(1.W), 0.U)
|
||||
val i0_pcall_raw = WireInit(UInt(1.W), 0.U)
|
||||
val i0_pja_raw = WireInit(UInt(1.W), 0.U)
|
||||
val i0_pret_raw = WireInit(UInt(1.W), 0.U)
|
||||
val i0_br_offset = WireInit(UInt(12.W), 0.U)
|
||||
val i0_csr_write_only_d = WireInit(UInt(1.W), 0.U)
|
||||
val i0_jal = WireInit(UInt(1.W), 0.U)
|
||||
val i0_wen_r = WireInit(UInt(1.W), 0.U)
|
||||
val i0_x_ctl_en = WireInit(UInt(1.W), 0.U)
|
||||
val i0_r_ctl_en = WireInit(UInt(1.W), 0.U)
|
||||
val i0_wb_ctl_en = WireInit(UInt(1.W), 0.U)
|
||||
val i0_x_data_en = WireInit(UInt(1.W), 0.U)
|
||||
val i0_r_data_en = WireInit(UInt(1.W), 0.U)
|
||||
val i0_wb_data_en = WireInit(UInt(1.W), 0.U)
|
||||
val i0_wb1_data_en = WireInit(UInt(1.W), 0.U)
|
||||
val i0_nonblock_load_stall = WireInit(UInt(1.W), 0.U)
|
||||
val csr_ren_qual_d = WireInit(Bool(), 0.B)
|
||||
val lsu_decode_d = WireInit(UInt(1.W), 0.U)
|
||||
val mul_decode_d = WireInit(UInt(1.W), 0.U)
|
||||
val div_decode_d = WireInit(UInt(1.W), 0.U)
|
||||
val write_csr_data = WireInit(UInt(32.W),0.U)
|
||||
val i0_result_corr_r = WireInit(UInt(32.W),0.U)
|
||||
val presync_stall = WireInit(UInt(1.W), 0.U)
|
||||
val i0_nonblock_div_stall = WireInit(UInt(1.W), 0.U)
|
||||
val debug_fence = WireInit(Bool(), 0.B)
|
||||
val i0_immed_d = WireInit(UInt(32.W), 0.U)
|
||||
val i0_result_x = WireInit(UInt(32.W), 0.U)
|
||||
val i0_result_r = WireInit(UInt(32.W), 0.U)
|
||||
//////////////////////////////////////////////////////////////////////
|
||||
// Start - Data gating {{
|
||||
|
||||
val data_gate_en = (io.dec_tlu_wr_pause_r ^ tlu_wr_pause_r1 ) | // replaces free_clk
|
||||
(tlu_wr_pause_r1 ^ tlu_wr_pause_r2 ) | // replaces free_clk
|
||||
(io.dec_tlu_flush_extint ^ io.dec_extint_stall) |
|
||||
(leak1_i1_stall_in ^ leak1_i1_stall ) | // replaces free_clk
|
||||
(leak1_i0_stall_in ^ leak1_i0_stall ) | // replaces free_clk
|
||||
(pause_state_in ^ pause_state ) | // replaces free_clk
|
||||
(ps_stall_in ^ postsync_stall ) | // replaces free_clk
|
||||
(io.exu_flush_final ^ flush_final_r ) | // replaces free_clk
|
||||
(illegal_lockout_in ^ illegal_lockout ) // replaces active_clk
|
||||
|
||||
val data_gated_cgc= Module(new rvclkhdr)
|
||||
data_gated_cgc.io.en := data_gate_en
|
||||
data_gated_cgc.io.scan_mode :=io.scan_mode
|
||||
data_gated_cgc.io.clk :=clock
|
||||
val data_gate_clk =data_gated_cgc.io.l1clk
|
||||
|
||||
// End - Data gating }}
|
||||
|
||||
val i0_brp_valid = io.dec_i0_brp.valid & !leak1_mode
|
||||
io.dec_i0_predict_p_d.misp :=0.U
|
||||
io.dec_i0_predict_p_d.ataken :=0.U
|
||||
io.dec_i0_predict_p_d.boffset :=0.U
|
||||
io.dec_i0_predict_p_d.pcall := i0_pcall // don't mark as pcall if branch error
|
||||
io.dec_i0_predict_p_d.pja := i0_pja
|
||||
io.dec_i0_predict_p_d.pret := i0_pret
|
||||
io.dec_i0_predict_p_d.prett := io.dec_i0_brp.prett
|
||||
io.dec_i0_predict_p_d.pc4 := io.dec_i0_pc4_d
|
||||
io.dec_i0_predict_p_d.hist := io.dec_i0_brp.hist
|
||||
io.dec_i0_predict_p_d.valid := i0_brp_valid & i0_legal_decode_d
|
||||
val i0_notbr_error = i0_brp_valid & !(i0_dp_raw.condbr | i0_pcall_raw | i0_pja_raw | i0_pret_raw)
|
||||
|
||||
// no toffset error for a pret
|
||||
val i0_br_toffset_error = i0_brp_valid & io.dec_i0_brp.hist(1) & (io.dec_i0_brp.toffset =/= i0_br_offset) & !i0_pret_raw
|
||||
val i0_ret_error = i0_brp_valid & io.dec_i0_brp.ret & !i0_pret_raw;
|
||||
val i0_br_error = io.dec_i0_brp.br_error | i0_notbr_error | i0_br_toffset_error | i0_ret_error
|
||||
io.dec_i0_predict_p_d.br_error := i0_br_error & i0_legal_decode_d & !leak1_mode
|
||||
io.dec_i0_predict_p_d.br_start_error := io.dec_i0_brp.br_start_error & i0_legal_decode_d & !leak1_mode
|
||||
io.i0_predict_index_d := io.dec_i0_bp_index
|
||||
io.i0_predict_btag_d := io.dec_i0_bp_btag
|
||||
val i0_br_error_all = (i0_br_error | io.dec_i0_brp.br_start_error) & !leak1_mode
|
||||
io.dec_i0_predict_p_d.toffset := i0_br_offset
|
||||
io.i0_predict_fghr_d := io.dec_i0_bp_fghr
|
||||
io.dec_i0_predict_p_d.way := io.dec_i0_brp.way
|
||||
// end
|
||||
|
||||
// on br error turn anything into a nop
|
||||
// on i0 instruction fetch access fault turn anything into a nop
|
||||
// nop => alu rs1 imm12 rd lor
|
||||
val i0_icaf_d = io.dec_i0_icaf_d | io.dec_i0_dbecc_d
|
||||
|
||||
val i0_instr_error = i0_icaf_d;
|
||||
i0_dp := i0_dp_raw
|
||||
when((i0_br_error_all | i0_instr_error).asBool){
|
||||
i0_dp := 0.U.asTypeOf(i0_dp)
|
||||
i0_dp.alu := 1.B
|
||||
i0_dp.rs1 := 1.B
|
||||
i0_dp.rs2 := 1.B
|
||||
i0_dp.lor := 1.B
|
||||
i0_dp.legal := 1.B
|
||||
i0_dp.postsync := 1.B
|
||||
}
|
||||
|
||||
val i0 = io.dec_i0_instr_d
|
||||
io.dec_i0_select_pc_d := i0_dp.pc;
|
||||
|
||||
// branches that can be predicted
|
||||
val i0_predict_br = i0_dp.condbr | i0_pcall | i0_pja | i0_pret;
|
||||
|
||||
val i0_predict_nt = !(io.dec_i0_brp.hist(1) & i0_brp_valid) & i0_predict_br
|
||||
val i0_predict_t = (io.dec_i0_brp.hist(1) & i0_brp_valid) & i0_predict_br
|
||||
val i0_ap_pc2 = !io.dec_i0_pc4_d
|
||||
val i0_ap_pc4 = io.dec_i0_pc4_d
|
||||
io.i0_ap.predict_nt := i0_predict_nt
|
||||
io.i0_ap.predict_t := i0_predict_t
|
||||
|
||||
io.i0_ap.add := i0_dp.add
|
||||
io.i0_ap.sub := i0_dp.sub
|
||||
io.i0_ap.land := i0_dp.land
|
||||
io.i0_ap.lor := i0_dp.lor
|
||||
io.i0_ap.lxor := i0_dp.lxor
|
||||
io.i0_ap.sll := i0_dp.sll
|
||||
io.i0_ap.srl := i0_dp.srl
|
||||
io.i0_ap.sra := i0_dp.sra
|
||||
io.i0_ap.slt := i0_dp.slt
|
||||
io.i0_ap.unsign := i0_dp.unsign
|
||||
io.i0_ap.beq := i0_dp.beq
|
||||
io.i0_ap.bne := i0_dp.bne
|
||||
io.i0_ap.blt := i0_dp.blt
|
||||
io.i0_ap.bge := i0_dp.bge
|
||||
io.i0_ap.csr_write := i0_csr_write_only_d
|
||||
io.i0_ap.csr_imm := i0_dp.csr_imm
|
||||
io.i0_ap.jal := i0_jal
|
||||
|
||||
// non block load cam logic
|
||||
// val found=Wire(UInt(1.W))
|
||||
cam_wen := Mux1H((0 until LSU_NUM_NBLOAD).map(i=>(0 to i).map(j=> if(i==j) !cam(j).valid else cam(j).valid).reduce(_.asBool&_.asBool).asBool -> (cam_write << i)))
|
||||
|
||||
cam_write := io.lsu_nonblock_load_valid_m
|
||||
val cam_write_tag = io.lsu_nonblock_load_tag_m(LSU_NUM_NBLOAD_WIDTH-1,0)
|
||||
|
||||
val cam_inv_reset = io.lsu_nonblock_load_inv_r
|
||||
val cam_inv_reset_tag = io.lsu_nonblock_load_inv_tag_r(LSU_NUM_NBLOAD_WIDTH-1,0)
|
||||
|
||||
val cam_data_reset = io.lsu_nonblock_load_data_valid | io.lsu_nonblock_load_data_error
|
||||
val cam_data_reset_tag = io.lsu_nonblock_load_data_tag(LSU_NUM_NBLOAD_WIDTH-1,0)
|
||||
|
||||
val nonblock_load_rd = Mux(x_d.i0load.asBool, x_d.i0rd, 0.U(5.W)) // rd data
|
||||
val load_data_tag = io.lsu_nonblock_load_data_tag
|
||||
// case of multiple loads to same dest ie. x1 ... you have to invalidate the older one
|
||||
// don't writeback a nonblock load
|
||||
val nonblock_load_valid_m_delay=withClock(io.active_clk){RegEnable(io.lsu_nonblock_load_valid_m,0.U, i0_r_ctl_en.asBool)}
|
||||
val i0_load_kill_wen_r = nonblock_load_valid_m_delay & r_d.i0load
|
||||
for(i <- 0 until LSU_NUM_NBLOAD){
|
||||
cam_inv_reset_val(i) := cam_inv_reset & (cam_inv_reset_tag === cam(i).tag) & cam(i).valid
|
||||
cam_data_reset_val(i) := cam_data_reset & (cam_data_reset_tag === cam(i).tag) & cam_raw(i).valid
|
||||
cam_in(i):=0.U.asTypeOf(cam(0))
|
||||
cam(i):=cam_raw(i)
|
||||
|
||||
when(cam_data_reset_val(i).asBool){
|
||||
cam(i).valid := 0.U(1.W)
|
||||
}
|
||||
when(cam_wen(i).asBool){
|
||||
cam_in(i).valid := 1.U(1.W)
|
||||
cam_in(i).wb := 0.U(1.W)
|
||||
cam_in(i).tag := cam_write_tag
|
||||
cam_in(i).rd := nonblock_load_rd
|
||||
}.elsewhen(cam_inv_reset_val(i).asBool || (i0_wen_r.asBool && (r_d_in.i0rd === cam(i).rd) && cam(i).wb.asBool)){
|
||||
cam_in(i).valid := 0.U
|
||||
}.otherwise{
|
||||
cam_in(i) := cam(i)
|
||||
}
|
||||
when(nonblock_load_valid_m_delay===1.U && (io.lsu_nonblock_load_inv_tag_r === cam(i).tag) && cam(i).valid===1.U){
|
||||
cam_in(i).wb := 1.U
|
||||
}
|
||||
// force debug halt forces cam valids to 0; highest priority
|
||||
when(io.dec_tlu_force_halt){
|
||||
cam_in(i).valid := 0.U
|
||||
}
|
||||
|
||||
cam_raw(i):=withClock(io.free_clk){RegNext(cam_in(i),0.U.asTypeOf(cam(0)))}
|
||||
nonblock_load_write(i) := (load_data_tag === cam_raw(i).tag) & cam_raw(i).valid
|
||||
}
|
||||
|
||||
io.dec_nonblock_load_waddr:=0.U(5.W)
|
||||
// cancel if any younger inst (including another nonblock) committing this cycle
|
||||
val nonblock_load_cancel = ((r_d_in.i0rd === io.dec_nonblock_load_waddr) & i0_wen_r)
|
||||
io.dec_nonblock_load_wen := (io.lsu_nonblock_load_data_valid && nonblock_load_write.reduce(_|_).asBool && !nonblock_load_cancel)
|
||||
val i0_nonblock_boundary_stall = ((nonblock_load_rd===i0r.rs1) & io.lsu_nonblock_load_valid_m & io.dec_i0_rs1_en_d)|((nonblock_load_rd===i0r.rs2) & io.lsu_nonblock_load_valid_m & io.dec_i0_rs2_en_d)
|
||||
|
||||
i0_nonblock_load_stall := i0_nonblock_boundary_stall
|
||||
|
||||
val cal_temp= for(i <-0 until LSU_NUM_NBLOAD) yield ((Fill(5,nonblock_load_write(i)) & cam(i).rd), io.dec_i0_rs1_en_d & cam(i).valid & (cam(i).rd === i0r.rs1), io.dec_i0_rs2_en_d & cam(i).valid & (cam(i).rd === i0r.rs2))
|
||||
val (waddr, ld_stall_1, ld_stall_2) = (cal_temp.map(_._1).reduce(_|_) , cal_temp.map(_._2).reduce(_|_), cal_temp.map(_._3).reduce(_|_) )
|
||||
io.dec_nonblock_load_waddr:=waddr
|
||||
i0_nonblock_load_stall:=ld_stall_1 | ld_stall_2 | i0_nonblock_boundary_stall
|
||||
//i0_nonblock_load_stall:=ld_stall_2
|
||||
|
||||
// end non block load cam logic
|
||||
|
||||
// pmu start
|
||||
|
||||
val csr_read = csr_ren_qual_d
|
||||
val csr_write = io.dec_csr_wen_unq_d
|
||||
val i0_br_unpred = i0_dp.jal & !i0_predict_br
|
||||
|
||||
// the classes must be mutually exclusive with one another
|
||||
import el2_inst_pkt_t._
|
||||
d_t.pmu_i0_itype :=Fill(4,i0_legal_decode_d) & MuxCase(NULL ,Array(
|
||||
i0_dp.jal -> JAL,
|
||||
i0_dp.condbr -> CONDBR,
|
||||
i0_dp.mret -> MRET,
|
||||
i0_dp.fence_i -> FENCEI,
|
||||
i0_dp.fence -> FENCE,
|
||||
i0_dp.ecall -> ECALL,
|
||||
i0_dp.ebreak -> EBREAK,
|
||||
( csr_read & csr_write).asBool -> CSRRW,
|
||||
(!csr_read & csr_write).asBool -> CSRWRITE,
|
||||
( csr_read & !csr_write).asBool -> CSRREAD,
|
||||
i0_dp.pm_alu -> ALU,
|
||||
i0_dp.store -> STORE,
|
||||
i0_dp.load -> LOAD,
|
||||
i0_dp.mul -> MUL))
|
||||
// end pmu
|
||||
|
||||
val i0_dec =Module(new el2_dec_dec_ctl)
|
||||
i0_dec.io.ins:= i0
|
||||
i0_dp_raw:=i0_dec.io.out
|
||||
|
||||
lsu_idle:=withClock(io.active_clk){RegNext(io.lsu_idle_any,0.U)}
|
||||
|
||||
// can't make this clock active_clock
|
||||
leak1_i1_stall_in := (io.dec_tlu_flush_leak_one_r | (leak1_i1_stall & !io.dec_tlu_flush_lower_r))
|
||||
leak1_i1_stall := withClock(data_gate_clk){RegNext(leak1_i1_stall_in,0.U)}
|
||||
leak1_mode := leak1_i1_stall
|
||||
leak1_i0_stall_in := ((io.dec_i0_decode_d & leak1_i1_stall) | (leak1_i0_stall & !io.dec_tlu_flush_lower_r))
|
||||
leak1_i0_stall := withClock(data_gate_clk){RegNext(leak1_i0_stall_in,0.U)}
|
||||
|
||||
// 12b jal's can be predicted - these are calls
|
||||
|
||||
val i0_pcall_imm = Cat(i0(31),i0(19,12),i0(20),i0(30,21),0.U(1.W))
|
||||
val i0_pcall_12b_offset = Mux(i0_pcall_imm(12).asBool, i0_pcall_imm(20,13) === 0xff.U , i0_pcall_imm(20,13) === 0.U(8.W))
|
||||
val i0_pcall_case = i0_pcall_12b_offset & i0_dp_raw.imm20 & (i0r.rd === 1.U(5.W) | i0r.rd === 5.U(5.W))
|
||||
val i0_pja_case = i0_pcall_12b_offset & i0_dp_raw.imm20 & !(i0r.rd === 1.U(5.W) | i0r.rd === 5.U(5.W))
|
||||
i0_pcall_raw := i0_dp_raw.jal & i0_pcall_case // this includes ja
|
||||
i0_pcall := i0_dp.jal & i0_pcall_case
|
||||
i0_pja_raw := i0_dp_raw.jal & i0_pja_case
|
||||
i0_pja := i0_dp.jal & i0_pja_case
|
||||
i0_br_offset := Mux((i0_pcall_raw | i0_pja_raw).asBool, i0_pcall_imm(12,1) , Cat(i0(31),i0(7),i0(30,25),i0(11,8)))
|
||||
// jalr with rd==0, rs1==1 or rs1==5 is a ret
|
||||
val i0_pret_case = (i0_dp_raw.jal & i0_dp_raw.imm12 & (i0r.rd === 0.U(5.W)) & (i0r.rs1===1.U(5.W) | i0r.rs1 === 5.U(5.W)))
|
||||
i0_pret_raw := i0_dp_raw.jal & i0_pret_case
|
||||
i0_pret := i0_dp.jal & i0_pret_case
|
||||
i0_jal := i0_dp.jal & !i0_pcall_case & !i0_pja_case & !i0_pret_case
|
||||
///////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
io.div_p.valid := div_decode_d
|
||||
io.div_p.unsign := i0_dp.unsign
|
||||
io.div_p.rem := i0_dp.rem
|
||||
|
||||
io.mul_p.valid := mul_decode_d
|
||||
io.mul_p.rs1_sign := i0_dp.rs1_sign
|
||||
io.mul_p.rs2_sign := i0_dp.rs2_sign
|
||||
io.mul_p.low := i0_dp.low
|
||||
|
||||
io.dec_extint_stall := withClock(data_gate_clk){RegNext(io.dec_tlu_flush_extint,0.U)}
|
||||
|
||||
io.lsu_p := 0.U.asTypeOf(io.lsu_p)
|
||||
when (io.dec_extint_stall){
|
||||
io.lsu_p.load := 1.U(1.W)
|
||||
io.lsu_p.word := 1.U(1.W)
|
||||
io.lsu_p.fast_int := 1.U(1.W)
|
||||
io.lsu_p.valid := 1.U(1.W)
|
||||
}.otherwise {
|
||||
io.lsu_p.valid := lsu_decode_d
|
||||
io.lsu_p.load := i0_dp.load
|
||||
io.lsu_p.store := i0_dp.store
|
||||
io.lsu_p.by := i0_dp.by
|
||||
io.lsu_p.half := i0_dp.half
|
||||
io.lsu_p.word := i0_dp.word
|
||||
io.lsu_p.load_ldst_bypass_d := load_ldst_bypass_d
|
||||
io.lsu_p.store_data_bypass_d := store_data_bypass_d
|
||||
io.lsu_p.store_data_bypass_m := store_data_bypass_m
|
||||
io.lsu_p.unsign := i0_dp.unsign
|
||||
}
|
||||
|
||||
//////////////////////////////////////
|
||||
io.dec_csr_ren_d := i0_dp.csr_read //H: assigning csr read enable signal decoded from decode_ctl going as input to EXU
|
||||
csr_ren_qual_d := i0_dp.csr_read & i0_legal_decode_d.asBool //csr_ren_qual_d assigned as csr_read above
|
||||
|
||||
val i0_csr_write = i0_dp.csr_write & !io.dec_debug_fence_d
|
||||
val csr_clr_d = i0_dp.csr_clr & i0_legal_decode_d.asBool
|
||||
val csr_set_d = i0_dp.csr_set & i0_legal_decode_d.asBool
|
||||
val csr_write_d = i0_csr_write & i0_legal_decode_d.asBool
|
||||
|
||||
i0_csr_write_only_d := i0_csr_write & !i0_dp.csr_read
|
||||
io.dec_csr_wen_unq_d := (i0_dp.csr_clr | i0_dp.csr_set | i0_csr_write) // for csr legal, can't write read-only csr
|
||||
//dec_csr_wen_unq_d assigned as csr_write above
|
||||
|
||||
io.dec_csr_rdaddr_d := i0(31,20)
|
||||
io.dec_csr_wraddr_r := r_d.csrwaddr //r_d is a el2_dest_pkt
|
||||
|
||||
// make sure csr doesn't write same cycle as dec_tlu_flush_lower_wb
|
||||
// also use valid so it's flushable
|
||||
io.dec_csr_wen_r := r_d.csrwen & r_d.i0valid & !io.dec_tlu_i0_kill_writeb_r;
|
||||
|
||||
// If we are writing MIE or MSTATUS, hold off the external interrupt for a cycle on the write.
|
||||
io.dec_csr_stall_int_ff := ((r_d.csrwaddr === "h300".U) | (r_d.csrwaddr === "h304".U)) & r_d.csrwen & r_d.i0valid & !io.dec_tlu_i0_kill_writeb_wb;
|
||||
|
||||
val csr_read_x = withClock(io.active_clk){RegNext(csr_ren_qual_d,init=0.B)}
|
||||
val csr_clr_x = withClock(io.active_clk){RegNext(csr_clr_d, init=0.B)}
|
||||
val csr_set_x = withClock(io.active_clk){RegNext(csr_set_d, init=0.B)}
|
||||
val csr_write_x = withClock(io.active_clk){RegNext(csr_write_d, init=0.B)}
|
||||
val csr_imm_x = withClock(io.active_clk){RegNext(i0_dp.csr_imm, init=0.U)}
|
||||
|
||||
// perform the update operation if any
|
||||
val csrimm_x = rvdffe(i0(19,15),i0_x_data_en.asBool,clock,io.scan_mode)
|
||||
val csr_rddata_x = rvdffe(io.dec_csr_rddata_d,i0_x_data_en.asBool,clock,io.scan_mode)
|
||||
|
||||
val csr_mask_x = Mux1H(Seq(
|
||||
csr_imm_x.asBool -> Cat(repl(27,0.U),csrimm_x(4,0)),
|
||||
!csr_imm_x.asBool -> io.exu_csr_rs1_x))
|
||||
|
||||
val write_csr_data_x = Mux1H(Seq(
|
||||
csr_clr_x -> (csr_rddata_x & (~csr_mask_x).asUInt),
|
||||
csr_set_x -> (csr_rddata_x | csr_mask_x),
|
||||
csr_write_x -> ( csr_mask_x)))
|
||||
// pause instruction
|
||||
val clear_pause = (io.dec_tlu_flush_lower_r & !io.dec_tlu_flush_pause_r) | (pause_state & (write_csr_data === 0.U(31.W))) // if 0 or 1 then exit pause state - 1 cycle pause
|
||||
pause_state_in := (io.dec_tlu_wr_pause_r | pause_state) & !clear_pause
|
||||
pause_state := withClock(data_gate_clk){RegNext(pause_state_in, 0.U)}
|
||||
io.dec_pause_state := pause_state
|
||||
tlu_wr_pause_r1 := RegNext(io.dec_tlu_wr_pause_r, 0.U)
|
||||
tlu_wr_pause_r2 := RegNext(tlu_wr_pause_r1, 0.U)
|
||||
//pause for clock gating
|
||||
io.dec_pause_state_cg := (pause_state & (!tlu_wr_pause_r1 && !tlu_wr_pause_r2))
|
||||
// end pause
|
||||
|
||||
val write_csr_data_in = Mux(pause_state,(write_csr_data - 1.U(32.W)),
|
||||
Mux(io.dec_tlu_wr_pause_r,io.dec_csr_wrdata_r,write_csr_data_x))
|
||||
val csr_data_wen = ((csr_clr_x | csr_set_x | csr_write_x) & csr_read_x) | io.dec_tlu_wr_pause_r | pause_state
|
||||
write_csr_data := rvdffe(write_csr_data_in,csr_data_wen,clock,io.scan_mode)
|
||||
|
||||
// will hold until write-back at which time the CSR will be updated while GPR is possibly written with prior CSR
|
||||
val pause_stall = pause_state
|
||||
|
||||
// for csr write only data is produced by the alu
|
||||
io.dec_csr_wrdata_r := Mux(r_d.csrwonly.asBool,i0_result_corr_r,write_csr_data)
|
||||
|
||||
val prior_csr_write = x_d.csrwonly | r_d.csrwonly | wbd.csrwonly;
|
||||
|
||||
val debug_fence_i = io.dec_debug_fence_d & io.dbg_cmd_wrdata(0)
|
||||
val debug_fence_raw = io.dec_debug_fence_d & io.dbg_cmd_wrdata(1)
|
||||
debug_fence := debug_fence_raw | debug_fence_i
|
||||
|
||||
// some CSR reads need to be presync'd
|
||||
val i0_presync = i0_dp.presync | io.dec_tlu_presync_d | debug_fence_i | debug_fence_raw | io.dec_tlu_pipelining_disable // both fence's presync
|
||||
|
||||
// some CSR writes need to be postsync'd
|
||||
val i0_postsync = i0_dp.postsync | io.dec_tlu_postsync_d | debug_fence_i | (i0_csr_write_only_d & (i0(31,20) === "h7c2".U))
|
||||
|
||||
val any_csr_d = i0_dp.csr_read | i0_csr_write
|
||||
io.dec_csr_any_unq_d := any_csr_d
|
||||
val i0_legal = i0_dp.legal & (!any_csr_d | io.dec_csr_legal_d)
|
||||
val i0_inst_d = Mux(io.dec_i0_pc4_d,i0,Cat(repl(16,0.U), io.ifu_i0_cinst))
|
||||
// illegal inst handling
|
||||
|
||||
val shift_illegal = io.dec_i0_decode_d & !i0_legal//lm: valid but not legal
|
||||
val illegal_inst_en = shift_illegal & !illegal_lockout
|
||||
io.dec_illegal_inst := rvdffe(i0_inst_d,illegal_inst_en,clock,io.scan_mode)
|
||||
illegal_lockout_in := (shift_illegal | illegal_lockout) & !flush_final_r
|
||||
illegal_lockout := withClock(data_gate_clk){RegNext(illegal_lockout_in, 0.U)}
|
||||
val i0_div_prior_div_stall = i0_dp.div & io.dec_div_active
|
||||
//stalls signals
|
||||
val i0_block_raw_d = (i0_dp.csr_read & prior_csr_write) | io.dec_extint_stall | pause_stall |
|
||||
leak1_i0_stall | io.dec_tlu_debug_stall | postsync_stall | presync_stall |
|
||||
((i0_dp.fence | debug_fence) & !lsu_idle) | i0_nonblock_load_stall |
|
||||
i0_load_block_d | i0_nonblock_div_stall | i0_div_prior_div_stall
|
||||
|
||||
val i0_store_stall_d = i0_dp.store & (io.lsu_store_stall_any | io.dma_dccm_stall_any)
|
||||
val i0_load_stall_d = i0_dp.load & (io.lsu_load_stall_any | io.dma_dccm_stall_any)
|
||||
val i0_block_d = i0_block_raw_d | i0_store_stall_d | i0_load_stall_d
|
||||
val i0_exublock_d = i0_block_raw_d
|
||||
|
||||
//decode valid
|
||||
io.dec_i0_decode_d := io.dec_ib0_valid_d & !i0_block_d & !io.dec_tlu_flush_lower_r & !flush_final_r
|
||||
val i0_exudecode_d = io.dec_ib0_valid_d & !i0_exublock_d & !io.dec_tlu_flush_lower_r & !flush_final_r
|
||||
val i0_exulegal_decode_d = i0_exudecode_d & i0_legal
|
||||
|
||||
// performance monitor signals
|
||||
io.dec_pmu_instr_decoded := io.dec_i0_decode_d
|
||||
io.dec_pmu_decode_stall := io.dec_ib0_valid_d & !io.dec_i0_decode_d
|
||||
io.dec_pmu_postsync_stall := postsync_stall.asBool
|
||||
io.dec_pmu_presync_stall := presync_stall.asBool
|
||||
|
||||
val prior_inflight_x = x_d.i0valid
|
||||
val prior_inflight_wb = r_d.i0valid
|
||||
val prior_inflight = prior_inflight_x | prior_inflight_wb
|
||||
val prior_inflight_eff = Mux(i0_dp.div,prior_inflight_x,prior_inflight)
|
||||
|
||||
presync_stall := (i0_presync & prior_inflight_eff)
|
||||
postsync_stall := withClock(data_gate_clk){RegNext(ps_stall_in, 0.U)}
|
||||
// illegals will postsync
|
||||
ps_stall_in := (io.dec_i0_decode_d & (i0_postsync | !i0_legal) ) | ( postsync_stall & prior_inflight_x)
|
||||
|
||||
io.dec_i0_alu_decode_d := i0_exulegal_decode_d & i0_dp.alu
|
||||
|
||||
lsu_decode_d := i0_legal_decode_d & i0_dp.lsu
|
||||
mul_decode_d := i0_exulegal_decode_d & i0_dp.mul
|
||||
div_decode_d := i0_exulegal_decode_d & i0_dp.div
|
||||
|
||||
io.dec_tlu_i0_valid_r := r_d.i0valid & !io.dec_tlu_flush_lower_wb
|
||||
|
||||
//traps for TLU (tlu stuff)
|
||||
d_t.legal := i0_legal_decode_d
|
||||
d_t.icaf := i0_icaf_d & i0_legal_decode_d // dbecc is icaf exception
|
||||
d_t.icaf_f1 := io.dec_i0_icaf_f1_d & i0_legal_decode_d // this includes icaf and dbecc
|
||||
d_t.icaf_type := io.dec_i0_icaf_type_d
|
||||
|
||||
d_t.fence_i := (i0_dp.fence_i | debug_fence_i) & i0_legal_decode_d
|
||||
|
||||
// put pmu info into the trap packet
|
||||
d_t.pmu_i0_br_unpred := i0_br_unpred
|
||||
d_t.pmu_divide := 0.U(1.W)
|
||||
d_t.pmu_lsu_misaligned := 0.U(1.W)
|
||||
|
||||
d_t.i0trigger := io.dec_i0_trigger_match_d & repl(4,io.dec_i0_decode_d)
|
||||
|
||||
|
||||
x_t := rvdffe(d_t,i0_x_ctl_en.asBool,clock,io.scan_mode)
|
||||
|
||||
x_t_in := x_t
|
||||
x_t_in.i0trigger := x_t.i0trigger & ~(repl(4,io.dec_tlu_flush_lower_wb))
|
||||
|
||||
r_t := rvdffe(x_t_in,i0_x_ctl_en.asBool,clock,io.scan_mode)
|
||||
val lsu_trigger_match_r = RegNext(io.lsu_trigger_match_m, 0.U)
|
||||
val lsu_pmu_misaligned_r = RegNext(io.lsu_pmu_misaligned_m, 0.U)
|
||||
|
||||
r_t_in := r_t
|
||||
|
||||
r_t_in.i0trigger := (repl(4,(r_d.i0load | r_d.i0store)) & lsu_trigger_match_r) | r_t.i0trigger
|
||||
r_t_in.pmu_lsu_misaligned := lsu_pmu_misaligned_r // only valid if a load/store is valid in DC3 stage
|
||||
|
||||
when (io.dec_tlu_flush_lower_wb.asBool) {r_t_in := 0.U.asTypeOf(r_t_in) }
|
||||
|
||||
io.dec_tlu_packet_r := r_t_in
|
||||
io.dec_tlu_packet_r.pmu_divide := r_d.i0div & r_d.i0valid
|
||||
// end tlu stuff
|
||||
|
||||
flush_final_r := withClock(data_gate_clk){RegNext(io.exu_flush_final, 0.U)}
|
||||
|
||||
io.dec_i0_decode_d := io.dec_ib0_valid_d & !i0_block_d & !io.dec_tlu_flush_lower_r & !flush_final_r
|
||||
|
||||
i0r.rs1 := i0(19,15) //H: assigning reg packets the instructions bits
|
||||
i0r.rs2 := i0(24,20)
|
||||
i0r.rd := i0(11,7)
|
||||
|
||||
io.dec_i0_rs1_en_d := i0_dp.rs1 & (i0r.rs1 =/= 0.U(5.W)) // if rs1_en=0 then read will be all 0's
|
||||
io.dec_i0_rs2_en_d := i0_dp.rs2 & (i0r.rs2 =/= 0.U(5.W))
|
||||
val i0_rd_en_d = i0_dp.rd & (i0r.rd =/= 0.U(5.W))
|
||||
io.dec_i0_rs1_d := i0r.rs1//H:assiging packets to output signals leading to gprfile
|
||||
io.dec_i0_rs2_d := i0r.rs2
|
||||
|
||||
val i0_jalimm20 = i0_dp.jal & i0_dp.imm20 // H:jal (used at line 915)
|
||||
val i0_uiimm20 = !i0_dp.jal & i0_dp.imm20
|
||||
|
||||
io.dec_i0_immed_d := Mux1H(Seq(
|
||||
i0_dp.csr_read -> io.dec_csr_rddata_d,
|
||||
!i0_dp.csr_read -> i0_immed_d))
|
||||
|
||||
i0_immed_d := Mux1H(Seq(
|
||||
i0_dp.imm12 -> Cat(repl(20,i0(31)),i0(31,20)), // jalr
|
||||
i0_dp.shimm5 -> Cat(repl(27,0.U),i0(24,20)),
|
||||
i0_jalimm20 -> Cat(repl(12,i0(31)),i0(19,12),i0(20),i0(30,21),0.U),
|
||||
i0_uiimm20 -> Cat(i0(31,12),repl(12,0.U)),
|
||||
(i0_csr_write_only_d & i0_dp.csr_imm).asBool -> Cat(repl(27,0.U),i0(19,15)))) // for csr's that only write
|
||||
|
||||
i0_legal_decode_d := io.dec_i0_decode_d & i0_legal
|
||||
|
||||
i0_d_c.mul := i0_dp.mul & i0_legal_decode_d
|
||||
i0_d_c.load := i0_dp.load & i0_legal_decode_d
|
||||
i0_d_c.alu := i0_dp.alu & i0_legal_decode_d
|
||||
|
||||
val i0_x_c = withClock(io.active_clk){RegEnable(i0_d_c, i0_x_ctl_en.asBool)}
|
||||
val i0_r_c = withClock(io.active_clk){RegEnable(i0_x_c, i0_r_ctl_en.asBool)}
|
||||
i0_pipe_en := Cat(io.dec_i0_decode_d,withClock(io.active_clk){RegNext(i0_pipe_en(3,1), init=0.U)})
|
||||
|
||||
i0_x_ctl_en := (i0_pipe_en(3,2).orR | io.clk_override)
|
||||
i0_r_ctl_en := (i0_pipe_en(2,1).orR | io.clk_override)
|
||||
i0_wb_ctl_en := (i0_pipe_en(1,0).orR | io.clk_override)
|
||||
i0_x_data_en := ( i0_pipe_en(3) | io.clk_override)
|
||||
i0_r_data_en := ( i0_pipe_en(2) | io.clk_override)
|
||||
i0_wb_data_en := ( i0_pipe_en(1) | io.clk_override)
|
||||
i0_wb1_data_en := ( i0_pipe_en(0) | io.clk_override)
|
||||
|
||||
io.dec_data_en := Cat(i0_x_data_en, i0_r_data_en)
|
||||
io.dec_ctl_en := Cat(i0_x_ctl_en, i0_r_ctl_en)
|
||||
|
||||
d_d.i0rd := i0r.rd
|
||||
d_d.i0v := i0_rd_en_d & i0_legal_decode_d
|
||||
d_d.i0valid := io.dec_i0_decode_d // has flush_final_r
|
||||
|
||||
d_d.i0load := i0_dp.load & i0_legal_decode_d
|
||||
d_d.i0store := i0_dp.store & i0_legal_decode_d
|
||||
d_d.i0div := i0_dp.div & i0_legal_decode_d
|
||||
|
||||
d_d.csrwen := io.dec_csr_wen_unq_d & i0_legal_decode_d
|
||||
d_d.csrwonly := i0_csr_write_only_d & io.dec_i0_decode_d
|
||||
d_d.csrwaddr := i0(31,20)
|
||||
|
||||
x_d := rvdffe(d_d, i0_x_ctl_en.asBool,clock,io.scan_mode)
|
||||
val x_d_in = Wire(new el2_dest_pkt_t)
|
||||
x_d_in := x_d
|
||||
x_d_in.i0v := x_d.i0v & !io.dec_tlu_flush_lower_wb & !io.dec_tlu_flush_lower_r
|
||||
x_d_in.i0valid := x_d.i0valid & !io.dec_tlu_flush_lower_wb & !io.dec_tlu_flush_lower_r
|
||||
|
||||
r_d := rvdffe(x_d_in,i0_r_ctl_en.asBool,clock,io.scan_mode)
|
||||
r_d_in := r_d
|
||||
r_d_in.i0rd := r_d.i0rd
|
||||
|
||||
r_d_in.i0v := (r_d.i0v & !io.dec_tlu_flush_lower_wb)
|
||||
r_d_in.i0valid := (r_d.i0valid & !io.dec_tlu_flush_lower_wb)
|
||||
r_d_in.i0load := r_d.i0load & !io.dec_tlu_flush_lower_wb
|
||||
r_d_in.i0store := r_d.i0store & !io.dec_tlu_flush_lower_wb
|
||||
|
||||
wbd := rvdffe(r_d_in,i0_wb_ctl_en.asBool,clock,io.scan_mode)
|
||||
|
||||
io.dec_i0_waddr_r := r_d_in.i0rd
|
||||
i0_wen_r := r_d_in.i0v & !io.dec_tlu_i0_kill_writeb_r
|
||||
io.dec_i0_wen_r := i0_wen_r & !r_d_in.i0div & !i0_load_kill_wen_r // don't write a nonblock load 1st time down the pipe
|
||||
io.dec_i0_wdata_r := i0_result_corr_r
|
||||
|
||||
val i0_result_r_raw = rvdffe(i0_result_x,i0_r_data_en.asBool,clock,io.scan_mode)
|
||||
if ( LOAD_TO_USE_PLUS1 == 1 ) {
|
||||
i0_result_x := io.exu_i0_result_x
|
||||
i0_result_r := Mux((r_d.i0v & r_d.i0load).asBool,io.lsu_result_m, i0_result_r_raw)
|
||||
}
|
||||
else {
|
||||
i0_result_x := Mux((x_d.i0v & x_d.i0load).asBool,io.lsu_result_m,io.exu_i0_result_x)
|
||||
i0_result_r := i0_result_r_raw
|
||||
}
|
||||
|
||||
// correct lsu load data - don't use for bypass, do pass down the pipe
|
||||
i0_result_corr_r := Mux((r_d.i0v & r_d.i0load).asBool,io.lsu_result_corr_r,i0_result_r_raw)
|
||||
io.dec_i0_br_immed_d := Mux((io.i0_ap.predict_nt & !i0_dp.jal).asBool,i0_br_offset,Cat(repl(10,0.U),i0_ap_pc4,i0_ap_pc2))
|
||||
val last_br_immed_d = WireInit(UInt(12.W),0.U)
|
||||
last_br_immed_d := Mux((io.i0_ap.predict_nt).asBool,Cat(repl(10,0.U),i0_ap_pc4,i0_ap_pc2),i0_br_offset)
|
||||
val last_br_immed_x = WireInit(UInt(12.W),0.U)
|
||||
last_br_immed_x := rvdffe(last_br_immed_d,i0_x_data_en.asBool,clock,io.scan_mode)
|
||||
|
||||
// divide stuff
|
||||
|
||||
val div_e1_to_r = (x_d.i0div & x_d.i0valid) | (r_d.i0div & r_d.i0valid)
|
||||
|
||||
val div_flush = (x_d.i0div & x_d.i0valid & (x_d.i0rd === 0.U(5.W))) |
|
||||
(x_d.i0div & x_d.i0valid & io.dec_tlu_flush_lower_r ) |
|
||||
(r_d.i0div & r_d.i0valid & io.dec_tlu_flush_lower_r & io.dec_tlu_i0_kill_writeb_r)
|
||||
|
||||
// cancel if any younger inst committing this cycle to same dest as nonblock divide
|
||||
|
||||
val nonblock_div_cancel = (io.dec_div_active & div_flush) |
|
||||
(io.dec_div_active & !div_e1_to_r & (r_d.i0rd === io.div_waddr_wb) & i0_wen_r)
|
||||
|
||||
io.dec_div_cancel := nonblock_div_cancel.asBool
|
||||
val i0_div_decode_d = i0_legal_decode_d & i0_dp.div
|
||||
|
||||
val div_active_in = i0_div_decode_d | (io.dec_div_active & !io.exu_div_wren & !nonblock_div_cancel)
|
||||
|
||||
io.dec_div_active := withClock(io.free_clk){RegNext(div_active_in, 0.U)}
|
||||
|
||||
// nonblocking div scheme
|
||||
i0_nonblock_div_stall := (io.dec_i0_rs1_en_d & io.dec_div_active & (io.div_waddr_wb === i0r.rs1)) |
|
||||
(io.dec_i0_rs2_en_d & io.dec_div_active & (io.div_waddr_wb === i0r.rs2))
|
||||
|
||||
io.div_waddr_wb := RegEnable(i0r.rd,0.U,i0_div_decode_d.asBool)
|
||||
///div end
|
||||
|
||||
//for tracing instruction
|
||||
val i0_wb_en = i0_wb_data_en
|
||||
val i0_wb1_en = i0_wb1_data_en
|
||||
|
||||
val div_inst = rvdffe(i0_inst_d(24,7),i0_div_decode_d.asBool,clock,io.scan_mode)
|
||||
val i0_inst_x = rvdffe(i0_inst_d,i0_x_data_en.asBool,clock,io.scan_mode)
|
||||
val i0_inst_r = rvdffe(i0_inst_x,i0_r_data_en.asBool,clock,io.scan_mode)
|
||||
val i0_inst_wb_in = i0_inst_r
|
||||
val i0_inst_wb = rvdffe(i0_inst_wb_in,i0_wb_en.asBool,clock,io.scan_mode)
|
||||
io.dec_i0_inst_wb1 := rvdffe(i0_inst_wb,i0_wb1_en.asBool,clock,io.scan_mode)
|
||||
val i0_pc_wb = rvdffe(io.dec_tlu_i0_pc_r,i0_wb_en.asBool,clock,io.scan_mode)
|
||||
|
||||
io.dec_i0_pc_wb1 := rvdffe(i0_pc_wb,i0_wb1_en.asBool,clock,io.scan_mode)
|
||||
val dec_i0_pc_r = rvdffe(io.exu_i0_pc_x,i0_r_data_en.asBool,clock,io.scan_mode)
|
||||
|
||||
io.dec_tlu_i0_pc_r := dec_i0_pc_r
|
||||
|
||||
//end tracing
|
||||
|
||||
val temp_pred_correct_npc_x = rvbradder(Cat(io.exu_i0_pc_x,0.U),Cat(last_br_immed_x,0.U))
|
||||
io.pred_correct_npc_x := temp_pred_correct_npc_x(31,1)
|
||||
|
||||
// scheduling logic for primary alu's
|
||||
|
||||
val i0_rs1_depend_i0_x = io.dec_i0_rs1_en_d & x_d.i0v & (x_d.i0rd === i0r.rs1)
|
||||
val i0_rs1_depend_i0_r = io.dec_i0_rs1_en_d & r_d.i0v & (r_d.i0rd === i0r.rs1)
|
||||
|
||||
val i0_rs2_depend_i0_x = io.dec_i0_rs2_en_d & x_d.i0v & (x_d.i0rd === i0r.rs2)
|
||||
val i0_rs2_depend_i0_r = io.dec_i0_rs2_en_d & r_d.i0v & (r_d.i0rd === i0r.rs2)
|
||||
// order the producers as follows: , i0_x, i0_r, i0_wb
|
||||
i0_rs1_class_d := Mux(i0_rs1_depend_i0_x.asBool,i0_x_c,Mux(i0_rs1_depend_i0_r.asBool, i0_r_c, 0.U.asTypeOf(i0_rs1_class_d)))
|
||||
i0_rs1_depth_d := Mux(i0_rs1_depend_i0_x.asBool,1.U(2.W),Mux(i0_rs1_depend_i0_r.asBool, 2.U(2.W), 0.U))
|
||||
i0_rs2_class_d := Mux(i0_rs2_depend_i0_x.asBool,i0_x_c,Mux(i0_rs2_depend_i0_r.asBool, i0_r_c, 0.U.asTypeOf(i0_rs2_class_d)))
|
||||
i0_rs2_depth_d := Mux(i0_rs2_depend_i0_x.asBool,1.U(2.W),Mux(i0_rs2_depend_i0_r.asBool, 2.U(2.W), 0.U))
|
||||
|
||||
// stores will bypass load data in the lsu pipe
|
||||
if (LOAD_TO_USE_PLUS1 == 1) {
|
||||
i0_load_block_d := (i0_rs1_class_d.load & i0_rs1_depth_d) | (i0_rs2_class_d.load & i0_rs2_depth_d(0) & !i0_dp.store)
|
||||
load_ldst_bypass_d := (i0_dp.load | i0_dp.store) & i0_rs1_depth_d(1) & i0_rs1_class_d.load
|
||||
store_data_bypass_d := i0_dp.store & (i0_rs2_depth_d(1) & i0_rs2_class_d.load)
|
||||
store_data_bypass_m := i0_dp.store & (i0_rs2_depth_d(0) & i0_rs2_class_d.load)
|
||||
}
|
||||
else {
|
||||
i0_load_block_d := 0.B
|
||||
load_ldst_bypass_d := (i0_dp.load | i0_dp.store) & i0_rs1_depth_d(0) & i0_rs1_class_d.load
|
||||
store_data_bypass_d := i0_dp.store & i0_rs2_depth_d(0) & i0_rs2_class_d.load
|
||||
store_data_bypass_m := 0.B
|
||||
}
|
||||
// add nonblock load rs1/rs2 bypass cases
|
||||
|
||||
val i0_rs1_nonblock_load_bypass_en_d = io.dec_i0_rs1_en_d & io.dec_nonblock_load_wen & (io.dec_nonblock_load_waddr === i0r.rs1)
|
||||
|
||||
val i0_rs2_nonblock_load_bypass_en_d = io.dec_i0_rs2_en_d & io.dec_nonblock_load_wen & (io.dec_nonblock_load_waddr === i0r.rs2)
|
||||
|
||||
// bit 2 is priority match, bit 0 lowest priority , i0_x, i0_r
|
||||
i0_rs1bypass := Cat((i0_rs1_depth_d(0) &(i0_rs1_class_d.alu | i0_rs1_class_d.mul)),(i0_rs1_depth_d(0) & (i0_rs1_class_d.load)), (i0_rs1_depth_d(1) & (i0_rs1_class_d.alu | i0_rs1_class_d.mul | i0_rs1_class_d.load)))
|
||||
|
||||
i0_rs2bypass := Cat((i0_rs2_depth_d(0) & (i0_rs2_class_d.alu | i0_rs2_class_d.mul)),(i0_rs2_depth_d(0) & (i0_rs2_class_d.load)),(i0_rs2_depth_d(1) & (i0_rs2_class_d.alu | i0_rs2_class_d.mul | i0_rs2_class_d.load)))
|
||||
|
||||
io.dec_i0_rs1_bypass_en_d := Cat(i0_rs1bypass(2),(i0_rs1bypass(1) | i0_rs1bypass(0) | (!i0_rs1bypass(2) & i0_rs1_nonblock_load_bypass_en_d)))
|
||||
io.dec_i0_rs2_bypass_en_d := Cat(i0_rs2bypass(2),(i0_rs2bypass(1) | i0_rs2bypass(0) | (!i0_rs2bypass(2) & i0_rs2_nonblock_load_bypass_en_d)))
|
||||
|
||||
io.dec_i0_rs1_bypass_data_d := Mux1H(Seq(
|
||||
i0_rs1bypass(1).asBool -> io.lsu_result_m,
|
||||
i0_rs1bypass(0).asBool -> i0_result_r,
|
||||
(!i0_rs1bypass(1) & !i0_rs1bypass(0) & i0_rs1_nonblock_load_bypass_en_d).asBool -> io.lsu_nonblock_load_data,
|
||||
))
|
||||
io.dec_i0_rs2_bypass_data_d := Mux1H(Seq(
|
||||
i0_rs2bypass(1).asBool -> io.lsu_result_m,
|
||||
i0_rs2bypass(0).asBool -> i0_result_r,
|
||||
(!i0_rs2bypass(1) & !i0_rs2bypass(0) & i0_rs2_nonblock_load_bypass_en_d).asBool -> io.lsu_nonblock_load_data,
|
||||
))
|
||||
io.dec_lsu_valid_raw_d := ((io.dec_ib0_valid_d & (i0_dp_raw.load | i0_dp_raw.store) & !io.dma_dccm_stall_any & !i0_block_raw_d) | io.dec_extint_stall)
|
||||
io.dec_lsu_offset_d := Mux1H(Seq(
|
||||
(!io.dec_extint_stall & i0_dp.lsu & i0_dp.load).asBool -> i0(31,20),
|
||||
(!io.dec_extint_stall & i0_dp.lsu & i0_dp.store).asBool -> Cat(i0(31,25),i0(11,7))))
|
||||
}
|
||||
|
||||
object dec_decode extends App{
|
||||
println((new chisel3.stage.ChiselStage).emitVerilog((new el2_dec_decode_ctl)))
|
||||
}
|
||||
|
|
@ -0,0 +1,58 @@
|
|||
package dec
|
||||
import chisel3._
|
||||
import scala.collection._
|
||||
import chisel3.util._
|
||||
import include._
|
||||
import lib._
|
||||
|
||||
class el2_dec_gpr_ctl extends Module with RequireAsyncReset with el2_lib {
|
||||
val io =IO(new el2_dec_gpr_ctl_IO)
|
||||
val w0v =Wire(Vec(32,UInt(1.W)))
|
||||
val w1v =Wire(Vec(32,UInt(1.W)))
|
||||
val w2v =Wire(Vec(32,UInt(1.W)))
|
||||
val gpr_in =Wire(Vec(32,UInt(32.W)))
|
||||
val gpr_out =Wire(Vec(32,UInt(32.W)))
|
||||
val gpr_wr_en =Wire(UInt(32.W))
|
||||
w0v(0):=0.U
|
||||
w1v(0):=0.U
|
||||
w2v(0):=0.U
|
||||
gpr_out(0):=0.U
|
||||
gpr_in(0):=0.U
|
||||
io.rd0:=0.U
|
||||
io.rd1:=0.U
|
||||
gpr_wr_en:= (w0v.reverse).reduceRight(Cat(_,_)) | (w1v.reverse).reduceRight(Cat(_,_)) | (w2v.reverse).reduceRight(Cat(_,_))
|
||||
// GPR Write logic
|
||||
for (j <-1 until 32){
|
||||
w0v(j) := io.wen0 & (io.waddr0===j.asUInt)
|
||||
w1v(j) := io.wen1 & (io.waddr1===j.asUInt)
|
||||
w2v(j) := io.wen2 & (io.waddr2===j.asUInt)
|
||||
gpr_in(j) := (Fill(32,w0v(j)) & io.wd0) | (Fill(32,w1v(j)) & io.wd1) | (Fill(32,w2v(j)) & io.wd2)
|
||||
}
|
||||
// GPR Write Enables for power savings
|
||||
for (j <-1 until 32){
|
||||
gpr_out(j):=rvdffe(gpr_in(j),gpr_wr_en(j),clock,io.scan_mode)
|
||||
}
|
||||
// GPR Read logic
|
||||
io.rd0:=Mux1H((1 until 32).map(i => (io.raddr0===i.U).asBool -> gpr_out(i)))
|
||||
io.rd1:=Mux1H((1 until 32).map(i => (io.raddr1===i.U).asBool -> gpr_out(i)))
|
||||
}
|
||||
|
||||
class el2_dec_gpr_ctl_IO extends Bundle{
|
||||
val raddr0=Input(UInt(5.W)) // logical read addresses
|
||||
val raddr1=Input(UInt(5.W))
|
||||
val wen0=Input(UInt(1.W)) // write enable
|
||||
val waddr0=Input(UInt(5.W)) // write address
|
||||
val wd0=Input(UInt(32.W)) // write data
|
||||
val wen1=Input(UInt(1.W)) // write enable
|
||||
val waddr1=Input(UInt(5.W)) // write address
|
||||
val wd1=Input(UInt(32.W)) // write data
|
||||
val wen2=Input(UInt(1.W)) // write enable
|
||||
val waddr2=Input(UInt(5.W)) // write address
|
||||
val wd2=Input(UInt(32.W)) // write data
|
||||
val rd0=Output(UInt(32.W)) // read data
|
||||
val rd1=Output(UInt(32.W))
|
||||
val scan_mode=Input(Bool())
|
||||
}
|
||||
object gpr_gen extends App{
|
||||
println((new chisel3.stage.ChiselStage).emitVerilog((new el2_dec_gpr_ctl)))
|
||||
}
|
||||
|
|
@ -0,0 +1,99 @@
|
|||
package dec
|
||||
import include._
|
||||
import chisel3._
|
||||
import chisel3.util._
|
||||
import lib._
|
||||
|
||||
class el2_dec_ib_ctl_IO extends Bundle with param{
|
||||
val dbg_cmd_valid =Input(UInt(1.W)) // valid dbg cmd
|
||||
val dbg_cmd_write =Input(UInt(1.W)) // dbg cmd is write
|
||||
val dbg_cmd_type =Input(UInt(2.W)) // dbg type
|
||||
val dbg_cmd_addr =Input(UInt(32.W)) // expand to 31:0
|
||||
val i0_brp =Input(new el2_br_pkt_t) // i0 branch packet from aligner
|
||||
val ifu_i0_bp_index =Input(UInt(((BTB_ADDR_HI-BTB_ADDR_LO)+1).W)) // BP index(Changed size)
|
||||
val ifu_i0_bp_fghr =Input(UInt((BHT_GHR_SIZE).W)) // BP FGHR
|
||||
val ifu_i0_bp_btag =Input(UInt((BTB_BTAG_SIZE).W)) // BP tag
|
||||
val ifu_i0_pc4 =Input(UInt(1.W)) // i0 is 4B inst else 2B
|
||||
val ifu_i0_valid =Input(UInt(1.W)) // i0 valid from ifu
|
||||
val ifu_i0_icaf =Input(UInt(1.W)) // i0 instruction access fault
|
||||
val ifu_i0_icaf_type =Input(UInt(2.W)) // i0 instruction access fault type
|
||||
val ifu_i0_icaf_f1 =Input(UInt(1.W)) // i0 has access fault on second fetch group
|
||||
val ifu_i0_dbecc =Input(UInt(1.W)) // i0 double-bit error
|
||||
val ifu_i0_instr =Input(UInt(32.W)) // i0 instruction from the aligner
|
||||
val ifu_i0_pc =Input(UInt(31.W)) // i0 pc from the aligner
|
||||
|
||||
val dec_ib0_valid_d =Output(UInt(1.W)) // ib0 valid
|
||||
val dec_i0_icaf_type_d =Output(UInt(2.W)) // i0 instruction access fault type
|
||||
val dec_i0_instr_d =Output(UInt(32.W)) // i0 inst at decode
|
||||
val dec_i0_pc_d =Output(UInt(31.W)) // i0 pc at decode
|
||||
val dec_i0_pc4_d =Output(UInt(1.W)) // i0 is 4B inst else 2B
|
||||
val dec_i0_brp =Output(new el2_br_pkt_t) // i0 branch packet at decode
|
||||
val dec_i0_bp_index =Output(UInt(((BTB_ADDR_HI-BTB_ADDR_LO)+1).W)) // i0 branch index
|
||||
val dec_i0_bp_fghr =Output(UInt(BHT_GHR_SIZE.W)) // BP FGHR
|
||||
val dec_i0_bp_btag =Output(UInt(BTB_BTAG_SIZE.W)) // BP tag
|
||||
val dec_i0_icaf_d =Output(UInt(1.W)) // i0 instruction access fault at decode
|
||||
val dec_i0_icaf_f1_d =Output(UInt(1.W)) // i0 instruction access fault at decode for f1 fetch group
|
||||
val dec_i0_dbecc_d =Output(UInt(1.W)) // i0 double-bit error at decode
|
||||
val dec_debug_wdata_rs1_d =Output(UInt(1.W)) // put debug write data onto rs1 source: machine is halted
|
||||
val dec_debug_fence_d =Output(UInt(1.W)) // debug fence inst
|
||||
}
|
||||
|
||||
class el2_dec_ib_ctl extends Module with param{
|
||||
val io=IO(new el2_dec_ib_ctl_IO)
|
||||
io.dec_i0_icaf_f1_d :=io.ifu_i0_icaf_f1
|
||||
io.dec_i0_dbecc_d :=io.ifu_i0_dbecc
|
||||
io.dec_i0_icaf_d :=io.ifu_i0_icaf
|
||||
io.dec_i0_pc_d :=io.ifu_i0_pc
|
||||
io.dec_i0_pc4_d :=io.ifu_i0_pc4
|
||||
io.dec_i0_icaf_type_d :=io.ifu_i0_icaf_type
|
||||
io.dec_i0_brp :=io.i0_brp
|
||||
io.dec_i0_bp_index :=io.ifu_i0_bp_index
|
||||
io.dec_i0_bp_fghr :=io.ifu_i0_bp_fghr
|
||||
io.dec_i0_bp_btag :=io.ifu_i0_bp_btag
|
||||
|
||||
// GPR accesses
|
||||
// put reg to read on rs1
|
||||
// read -> or %x0, %reg,%x0 {000000000000,reg[4:0],110000000110011}
|
||||
// put write date on rs1
|
||||
// write -> or %reg, %x0, %x0 {00000000000000000110,reg[4:0],0110011}
|
||||
// CSR accesses
|
||||
// csr is of form rd, csr, rs1
|
||||
// read -> csrrs %x0, %csr, %x0 {csr[11:0],00000010000001110011}
|
||||
// put write data on rs1
|
||||
// write -> csrrw %x0, %csr, %x0 {csr[11:0],00000001000001110011}
|
||||
|
||||
|
||||
val debug_valid =io.dbg_cmd_valid & (io.dbg_cmd_type =/= 2.U)
|
||||
val debug_read =debug_valid & !io.dbg_cmd_write
|
||||
val debug_write =debug_valid & io.dbg_cmd_write
|
||||
|
||||
val debug_read_gpr = debug_read & (io.dbg_cmd_type===0.U)
|
||||
val debug_write_gpr = debug_write & (io.dbg_cmd_type===0.U)
|
||||
val debug_read_csr = debug_read & (io.dbg_cmd_type===1.U)
|
||||
val debug_write_csr = debug_write & (io.dbg_cmd_type===1.U)
|
||||
|
||||
val dreg = io.dbg_cmd_addr(4,0)
|
||||
val dcsr = io.dbg_cmd_addr(11,0)
|
||||
|
||||
val ib0_debug_in =Mux1H(Seq(
|
||||
debug_read_gpr.asBool -> Cat(Fill(12,0.U(1.W)),dreg,"b110000000110011".U),
|
||||
debug_write_gpr.asBool -> Cat("b00000000000000000110".U(20.W),dreg,"b0110011".U(7.W)),
|
||||
debug_read_csr.asBool -> Cat(dcsr,"b00000010000001110011".U(20.W)),
|
||||
debug_write_csr.asBool -> Cat(dcsr,"b00000001000001110011".U(20.W))
|
||||
))
|
||||
|
||||
// machine is in halted state, pipe empty, write will always happen next cycle
|
||||
io.dec_debug_wdata_rs1_d := debug_write_gpr | debug_write_csr
|
||||
|
||||
// special fence csr for use only in debug mode
|
||||
io.dec_debug_fence_d := debug_write_csr & (dcsr === 0x7C4.U)
|
||||
|
||||
io.dec_ib0_valid_d := io.ifu_i0_valid | debug_valid
|
||||
io.dec_i0_instr_d := Mux(debug_valid.asBool,ib0_debug_in,io.ifu_i0_instr)
|
||||
|
||||
|
||||
}
|
||||
|
||||
object ib_gen extends App{
|
||||
println((new chisel3.stage.ChiselStage).emitVerilog((new el2_dec_ib_ctl)))
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,20 @@
|
|||
package dec
|
||||
|
||||
import chisel3.util._
|
||||
import chisel3._
|
||||
import include.el2_trigger_pkt_t
|
||||
import lib._
|
||||
|
||||
class el2_dec_trigger extends Module with el2_lib {
|
||||
val io = IO(new Bundle {
|
||||
val trigger_pkt_any = Input(Vec(4, new el2_trigger_pkt_t))
|
||||
val dec_i0_pc_d = Input(UInt(31.W))
|
||||
val dec_i0_trigger_match_d = Output(UInt(4.W))
|
||||
})
|
||||
val dec_i0_match_data = VecInit.tabulate(4)(i => repl(32, (!io.trigger_pkt_any(i).select & io.trigger_pkt_any(i).execute)) & Cat(io.dec_i0_pc_d, io.trigger_pkt_any(i).tdata2(0)))
|
||||
io.dec_i0_trigger_match_d := (0 until 4).map(j =>io.trigger_pkt_any(j).execute & io.trigger_pkt_any(j).m & rvmaskandmatch(io.trigger_pkt_any(j).tdata2, dec_i0_match_data(j), io.trigger_pkt_any(j).match_.asBool())).reverse.reduce(Cat(_,_))
|
||||
|
||||
}
|
||||
object dec_trig extends App {
|
||||
println((new chisel3.stage.ChiselStage).emitVerilog((new el2_dec_trigger())))
|
||||
}
|
||||
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Reference in New Issue