bus_rst updated

lsu_bus_buffer.fir

@@ -5855,34 +5855,34 @@ circuit lsu_bus_buffer :
     buf_data[1] <= _T_4384 @[lsu_bus_buffer.scala 522:12]
     buf_data[2] <= _T_4385 @[lsu_bus_buffer.scala 522:12]
     buf_data[3] <= _T_4386 @[lsu_bus_buffer.scala 522:12]
-    node _T_4387 = bits(buf_rst[0], 0, 0) @[lsu_bus_buffer.scala 523:93]
-    node _T_4388 = eq(_T_4387, UInt<1>("h00")) @[lsu_bus_buffer.scala 523:81]
-    node _T_4389 = bits(buf_error, 0, 0) @[lsu_bus_buffer.scala 523:140]
-    node _T_4390 = mux(buf_error_en[0], UInt<1>("h01"), _T_4389) @[lsu_bus_buffer.scala 523:105]
-    node _T_4391 = and(_T_4388, _T_4390) @[lsu_bus_buffer.scala 523:100]
-    reg _T_4392 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, io.dec_tlu_force_halt)) @[lsu_bus_buffer.scala 523:80]
-    _T_4392 <= _T_4391 @[lsu_bus_buffer.scala 523:80]
-    node _T_4393 = bits(buf_rst[1], 0, 0) @[lsu_bus_buffer.scala 523:93]
-    node _T_4394 = eq(_T_4393, UInt<1>("h00")) @[lsu_bus_buffer.scala 523:81]
-    node _T_4395 = bits(buf_error, 1, 1) @[lsu_bus_buffer.scala 523:140]
-    node _T_4396 = mux(buf_error_en[1], UInt<1>("h01"), _T_4395) @[lsu_bus_buffer.scala 523:105]
-    node _T_4397 = and(_T_4394, _T_4396) @[lsu_bus_buffer.scala 523:100]
-    reg _T_4398 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, io.dec_tlu_force_halt)) @[lsu_bus_buffer.scala 523:80]
-    _T_4398 <= _T_4397 @[lsu_bus_buffer.scala 523:80]
-    node _T_4399 = bits(buf_rst[2], 0, 0) @[lsu_bus_buffer.scala 523:93]
-    node _T_4400 = eq(_T_4399, UInt<1>("h00")) @[lsu_bus_buffer.scala 523:81]
-    node _T_4401 = bits(buf_error, 2, 2) @[lsu_bus_buffer.scala 523:140]
-    node _T_4402 = mux(buf_error_en[2], UInt<1>("h01"), _T_4401) @[lsu_bus_buffer.scala 523:105]
-    node _T_4403 = and(_T_4400, _T_4402) @[lsu_bus_buffer.scala 523:100]
-    reg _T_4404 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, io.dec_tlu_force_halt)) @[lsu_bus_buffer.scala 523:80]
-    _T_4404 <= _T_4403 @[lsu_bus_buffer.scala 523:80]
-    node _T_4405 = bits(buf_rst[3], 0, 0) @[lsu_bus_buffer.scala 523:93]
-    node _T_4406 = eq(_T_4405, UInt<1>("h00")) @[lsu_bus_buffer.scala 523:81]
-    node _T_4407 = bits(buf_error, 3, 3) @[lsu_bus_buffer.scala 523:140]
-    node _T_4408 = mux(buf_error_en[3], UInt<1>("h01"), _T_4407) @[lsu_bus_buffer.scala 523:105]
-    node _T_4409 = and(_T_4406, _T_4408) @[lsu_bus_buffer.scala 523:100]
-    reg _T_4410 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, io.dec_tlu_force_halt)) @[lsu_bus_buffer.scala 523:80]
-    _T_4410 <= _T_4409 @[lsu_bus_buffer.scala 523:80]
+    node _T_4387 = bits(buf_rst[0], 0, 0) @[lsu_bus_buffer.scala 523:91]
+    node _T_4388 = eq(buf_rst[0], UInt<1>("h00")) @[lsu_bus_buffer.scala 523:107]
+    node _T_4389 = bits(buf_error, 0, 0) @[lsu_bus_buffer.scala 523:159]
+    node _T_4390 = mux(buf_error_en[0], UInt<1>("h01"), _T_4389) @[lsu_bus_buffer.scala 523:124]
+    node _T_4391 = and(_T_4388, _T_4390) @[lsu_bus_buffer.scala 523:119]
+    reg _T_4392 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (_T_4387, io.dec_tlu_force_halt)) @[lsu_bus_buffer.scala 523:106]
+    _T_4392 <= _T_4391 @[lsu_bus_buffer.scala 523:106]
+    node _T_4393 = bits(buf_rst[1], 0, 0) @[lsu_bus_buffer.scala 523:91]
+    node _T_4394 = eq(buf_rst[1], UInt<1>("h00")) @[lsu_bus_buffer.scala 523:107]
+    node _T_4395 = bits(buf_error, 1, 1) @[lsu_bus_buffer.scala 523:159]
+    node _T_4396 = mux(buf_error_en[1], UInt<1>("h01"), _T_4395) @[lsu_bus_buffer.scala 523:124]
+    node _T_4397 = and(_T_4394, _T_4396) @[lsu_bus_buffer.scala 523:119]
+    reg _T_4398 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (_T_4393, io.dec_tlu_force_halt)) @[lsu_bus_buffer.scala 523:106]
+    _T_4398 <= _T_4397 @[lsu_bus_buffer.scala 523:106]
+    node _T_4399 = bits(buf_rst[2], 0, 0) @[lsu_bus_buffer.scala 523:91]
+    node _T_4400 = eq(buf_rst[2], UInt<1>("h00")) @[lsu_bus_buffer.scala 523:107]
+    node _T_4401 = bits(buf_error, 2, 2) @[lsu_bus_buffer.scala 523:159]
+    node _T_4402 = mux(buf_error_en[2], UInt<1>("h01"), _T_4401) @[lsu_bus_buffer.scala 523:124]
+    node _T_4403 = and(_T_4400, _T_4402) @[lsu_bus_buffer.scala 523:119]
+    reg _T_4404 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (_T_4399, io.dec_tlu_force_halt)) @[lsu_bus_buffer.scala 523:106]
+    _T_4404 <= _T_4403 @[lsu_bus_buffer.scala 523:106]
+    node _T_4405 = bits(buf_rst[3], 0, 0) @[lsu_bus_buffer.scala 523:91]
+    node _T_4406 = eq(buf_rst[3], UInt<1>("h00")) @[lsu_bus_buffer.scala 523:107]
+    node _T_4407 = bits(buf_error, 3, 3) @[lsu_bus_buffer.scala 523:159]
+    node _T_4408 = mux(buf_error_en[3], UInt<1>("h01"), _T_4407) @[lsu_bus_buffer.scala 523:124]
+    node _T_4409 = and(_T_4406, _T_4408) @[lsu_bus_buffer.scala 523:119]
+    reg _T_4410 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (_T_4405, io.dec_tlu_force_halt)) @[lsu_bus_buffer.scala 523:106]
+    _T_4410 <= _T_4409 @[lsu_bus_buffer.scala 523:106]
     node _T_4411 = cat(_T_4410, _T_4404) @[Cat.scala 29:58]
     node _T_4412 = cat(_T_4411, _T_4398) @[Cat.scala 29:58]
     node _T_4413 = cat(_T_4412, _T_4392) @[Cat.scala 29:58]

src/main/scala/lsu/lsu_bus_buffer.scala

@@ -520,7 +520,7 @@ class lsu_bus_buffer extends Module with RequireAsyncReset with lib {
   buf_addr := (0 until DEPTH).map(i=>rvdffe(buf_addr_in(i), buf_wr_en(i).asBool(), clock, io.scan_mode))
   buf_byteen := (0 until DEPTH).map(i=>withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_byteen_in(i), 0.U, buf_wr_en(i).asBool())})
   buf_data := (0 until DEPTH).map(i=>rvdffe(buf_data_in(i), buf_data_en(i), clock, io.scan_mode))
-  buf_error := (0 until DEPTH).map(i=>(withClock(io.lsu_bus_buf_c1_clk){RegNext(!buf_rst(i) & Mux(buf_error_en(i), true.B, buf_error(i)), false.B)}).asUInt()).reverse.reduce(Cat(_,_))
+  buf_error := (0 until DEPTH).map(i=>(withClockAndReset(io.lsu_bus_buf_c1_clk,buf_rst(i).asBool){RegNext(!buf_rst(i) & Mux(buf_error_en(i), true.B, buf_error(i)), io.dec_tlu_force_halt)}).asUInt()).reverse.reduce(Cat(_,_))
   val buf_numvld_any = (Mux(io.ldst_dual_m, Cat(io.lsu_busreq_m, 0.U),io.lsu_busreq_m) +& Mux(io.ldst_dual_r, Cat(io.lsu_busreq_r, 0.U),io.lsu_busreq_r) +& ibuf_valid) + buf_state.map(i=>(i=/=idle_C).asUInt).reduce(_+&_)
   buf_numvld_wrcmd_any := (0 until DEPTH).map(i=>(buf_write(i) & (buf_state(i)===cmd_C) & !buf_cmd_state_bus_en(i)).asUInt).reverse.reduce(_ +& _)
   buf_numvld_cmd_any :=  (0 until DEPTH).map(i=>((buf_state(i)===cmd_C) & !buf_cmd_state_bus_en(i)).asUInt).reverse.reduce(_ +& _)