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Clk domain ready for verification.

This commit is contained in:
Jahanzaib-Rasheed 2020-09-23 10:28:05 +05:00
parent 8fdc50f01e
commit 264b94b397
1 changed files with 1 additions and 1 deletions
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2
src/main/scala/lsu/el2_lsu_clkdomain.scala
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@ -77,7 +77,7 @@ class el2_lsu_clkdomain extends Module {
val lsu_free_c1_clken_q = withClock(free_clk)RegNext(lsu_free_c1_clken,0.U) val lsu_free_c1_clken_q = withClock(free_clk)RegNext(lsu_free_c1_clken,0.U)
val tuple3( lsu_c1_d_clken_q, lsu_c1_m_clken_q, lsu_c1_r_clken_q) = withClock(lsu_free_c2_clk) { val ( lsu_c1_d_clken_q, lsu_c1_m_clken_q, lsu_c1_r_clken_q) = withClock(lsu_free_c2_clk) {
RegNext(lsu_c1_d_clken, 0.U); RegNext(lsu_c1_m_clken, 0.U); RegNext(lsu_c1_r_clken, 0.U) RegNext(lsu_c1_d_clken, 0.U); RegNext(lsu_c1_m_clken, 0.U); RegNext(lsu_c1_r_clken, 0.U)
} }