IFC
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waleed-lm
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EL2_IC_DATA.fir
3928
EL2_IC_DATA.fir
File diff suppressed because it is too large
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494
EL2_IC_DATA.v
494
EL2_IC_DATA.v
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@ -55,188 +55,188 @@ module EL2_IC_DATA(
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reg [31:0] _RAND_21;
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reg [31:0] _RAND_22;
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`endif // RANDOMIZE_REG_INIT
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reg [70:0] data_mem_0_0 [0:511]; // @[el2_ifu_ic_mem.scala 245:29]
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wire [70:0] data_mem_0_0__T_137_data; // @[el2_ifu_ic_mem.scala 245:29]
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wire [8:0] data_mem_0_0__T_137_addr; // @[el2_ifu_ic_mem.scala 245:29]
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wire [70:0] data_mem_0_0__T_144_data; // @[el2_ifu_ic_mem.scala 245:29]
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wire [8:0] data_mem_0_0__T_144_addr; // @[el2_ifu_ic_mem.scala 245:29]
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wire [70:0] data_mem_0_0__T_151_data; // @[el2_ifu_ic_mem.scala 245:29]
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wire [8:0] data_mem_0_0__T_151_addr; // @[el2_ifu_ic_mem.scala 245:29]
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wire [70:0] data_mem_0_0__T_158_data; // @[el2_ifu_ic_mem.scala 245:29]
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wire [8:0] data_mem_0_0__T_158_addr; // @[el2_ifu_ic_mem.scala 245:29]
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wire [70:0] data_mem_0_0__T_130_data; // @[el2_ifu_ic_mem.scala 245:29]
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wire [8:0] data_mem_0_0__T_130_addr; // @[el2_ifu_ic_mem.scala 245:29]
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wire data_mem_0_0__T_130_mask; // @[el2_ifu_ic_mem.scala 245:29]
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wire data_mem_0_0__T_130_en; // @[el2_ifu_ic_mem.scala 245:29]
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wire [70:0] data_mem_0_0__T_135_data; // @[el2_ifu_ic_mem.scala 245:29]
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wire [8:0] data_mem_0_0__T_135_addr; // @[el2_ifu_ic_mem.scala 245:29]
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wire data_mem_0_0__T_135_mask; // @[el2_ifu_ic_mem.scala 245:29]
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wire data_mem_0_0__T_135_en; // @[el2_ifu_ic_mem.scala 245:29]
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wire [70:0] data_mem_0_0__T_142_data; // @[el2_ifu_ic_mem.scala 245:29]
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wire [8:0] data_mem_0_0__T_142_addr; // @[el2_ifu_ic_mem.scala 245:29]
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wire data_mem_0_0__T_142_mask; // @[el2_ifu_ic_mem.scala 245:29]
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wire data_mem_0_0__T_142_en; // @[el2_ifu_ic_mem.scala 245:29]
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wire [70:0] data_mem_0_0__T_149_data; // @[el2_ifu_ic_mem.scala 245:29]
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wire [8:0] data_mem_0_0__T_149_addr; // @[el2_ifu_ic_mem.scala 245:29]
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wire data_mem_0_0__T_149_mask; // @[el2_ifu_ic_mem.scala 245:29]
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wire data_mem_0_0__T_149_en; // @[el2_ifu_ic_mem.scala 245:29]
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wire [70:0] data_mem_0_0__T_156_data; // @[el2_ifu_ic_mem.scala 245:29]
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wire [8:0] data_mem_0_0__T_156_addr; // @[el2_ifu_ic_mem.scala 245:29]
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wire data_mem_0_0__T_156_mask; // @[el2_ifu_ic_mem.scala 245:29]
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wire data_mem_0_0__T_156_en; // @[el2_ifu_ic_mem.scala 245:29]
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reg [70:0] data_mem_0_0 [0:511]; // @[el2_ifu_ic_mem.scala 230:29]
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wire [70:0] data_mem_0_0__T_137_data; // @[el2_ifu_ic_mem.scala 230:29]
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wire [8:0] data_mem_0_0__T_137_addr; // @[el2_ifu_ic_mem.scala 230:29]
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wire [70:0] data_mem_0_0__T_144_data; // @[el2_ifu_ic_mem.scala 230:29]
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wire [8:0] data_mem_0_0__T_144_addr; // @[el2_ifu_ic_mem.scala 230:29]
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wire [70:0] data_mem_0_0__T_151_data; // @[el2_ifu_ic_mem.scala 230:29]
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wire [8:0] data_mem_0_0__T_151_addr; // @[el2_ifu_ic_mem.scala 230:29]
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wire [70:0] data_mem_0_0__T_158_data; // @[el2_ifu_ic_mem.scala 230:29]
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wire [8:0] data_mem_0_0__T_158_addr; // @[el2_ifu_ic_mem.scala 230:29]
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wire [70:0] data_mem_0_0__T_130_data; // @[el2_ifu_ic_mem.scala 230:29]
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wire [8:0] data_mem_0_0__T_130_addr; // @[el2_ifu_ic_mem.scala 230:29]
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wire data_mem_0_0__T_130_mask; // @[el2_ifu_ic_mem.scala 230:29]
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wire data_mem_0_0__T_130_en; // @[el2_ifu_ic_mem.scala 230:29]
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wire [70:0] data_mem_0_0__T_135_data; // @[el2_ifu_ic_mem.scala 230:29]
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wire [8:0] data_mem_0_0__T_135_addr; // @[el2_ifu_ic_mem.scala 230:29]
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wire data_mem_0_0__T_135_mask; // @[el2_ifu_ic_mem.scala 230:29]
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wire data_mem_0_0__T_135_en; // @[el2_ifu_ic_mem.scala 230:29]
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wire [70:0] data_mem_0_0__T_142_data; // @[el2_ifu_ic_mem.scala 230:29]
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wire [8:0] data_mem_0_0__T_142_addr; // @[el2_ifu_ic_mem.scala 230:29]
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wire data_mem_0_0__T_142_mask; // @[el2_ifu_ic_mem.scala 230:29]
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wire data_mem_0_0__T_142_en; // @[el2_ifu_ic_mem.scala 230:29]
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wire [70:0] data_mem_0_0__T_149_data; // @[el2_ifu_ic_mem.scala 230:29]
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wire [8:0] data_mem_0_0__T_149_addr; // @[el2_ifu_ic_mem.scala 230:29]
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wire data_mem_0_0__T_149_mask; // @[el2_ifu_ic_mem.scala 230:29]
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wire data_mem_0_0__T_149_en; // @[el2_ifu_ic_mem.scala 230:29]
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wire [70:0] data_mem_0_0__T_156_data; // @[el2_ifu_ic_mem.scala 230:29]
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wire [8:0] data_mem_0_0__T_156_addr; // @[el2_ifu_ic_mem.scala 230:29]
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wire data_mem_0_0__T_156_mask; // @[el2_ifu_ic_mem.scala 230:29]
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wire data_mem_0_0__T_156_en; // @[el2_ifu_ic_mem.scala 230:29]
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reg [8:0] data_mem_0_0__T_137_addr_pipe_0;
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reg [8:0] data_mem_0_0__T_144_addr_pipe_0;
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reg [8:0] data_mem_0_0__T_151_addr_pipe_0;
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reg [8:0] data_mem_0_0__T_158_addr_pipe_0;
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reg [70:0] data_mem_0_1 [0:511]; // @[el2_ifu_ic_mem.scala 245:29]
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wire [70:0] data_mem_0_1__T_137_data; // @[el2_ifu_ic_mem.scala 245:29]
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wire [8:0] data_mem_0_1__T_137_addr; // @[el2_ifu_ic_mem.scala 245:29]
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wire [70:0] data_mem_0_1__T_144_data; // @[el2_ifu_ic_mem.scala 245:29]
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wire [8:0] data_mem_0_1__T_144_addr; // @[el2_ifu_ic_mem.scala 245:29]
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wire [70:0] data_mem_0_1__T_151_data; // @[el2_ifu_ic_mem.scala 245:29]
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wire [8:0] data_mem_0_1__T_151_addr; // @[el2_ifu_ic_mem.scala 245:29]
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wire [70:0] data_mem_0_1__T_158_data; // @[el2_ifu_ic_mem.scala 245:29]
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wire [8:0] data_mem_0_1__T_158_addr; // @[el2_ifu_ic_mem.scala 245:29]
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wire [70:0] data_mem_0_1__T_130_data; // @[el2_ifu_ic_mem.scala 245:29]
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wire [8:0] data_mem_0_1__T_130_addr; // @[el2_ifu_ic_mem.scala 245:29]
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wire data_mem_0_1__T_130_mask; // @[el2_ifu_ic_mem.scala 245:29]
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wire data_mem_0_1__T_130_en; // @[el2_ifu_ic_mem.scala 245:29]
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wire [70:0] data_mem_0_1__T_135_data; // @[el2_ifu_ic_mem.scala 245:29]
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wire [8:0] data_mem_0_1__T_135_addr; // @[el2_ifu_ic_mem.scala 245:29]
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wire data_mem_0_1__T_135_mask; // @[el2_ifu_ic_mem.scala 245:29]
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wire data_mem_0_1__T_135_en; // @[el2_ifu_ic_mem.scala 245:29]
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wire [70:0] data_mem_0_1__T_142_data; // @[el2_ifu_ic_mem.scala 245:29]
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wire [8:0] data_mem_0_1__T_142_addr; // @[el2_ifu_ic_mem.scala 245:29]
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wire data_mem_0_1__T_142_mask; // @[el2_ifu_ic_mem.scala 245:29]
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wire data_mem_0_1__T_142_en; // @[el2_ifu_ic_mem.scala 245:29]
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wire [70:0] data_mem_0_1__T_149_data; // @[el2_ifu_ic_mem.scala 245:29]
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wire [8:0] data_mem_0_1__T_149_addr; // @[el2_ifu_ic_mem.scala 245:29]
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wire data_mem_0_1__T_149_mask; // @[el2_ifu_ic_mem.scala 245:29]
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wire data_mem_0_1__T_149_en; // @[el2_ifu_ic_mem.scala 245:29]
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wire [70:0] data_mem_0_1__T_156_data; // @[el2_ifu_ic_mem.scala 245:29]
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wire [8:0] data_mem_0_1__T_156_addr; // @[el2_ifu_ic_mem.scala 245:29]
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wire data_mem_0_1__T_156_mask; // @[el2_ifu_ic_mem.scala 245:29]
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wire data_mem_0_1__T_156_en; // @[el2_ifu_ic_mem.scala 245:29]
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reg [70:0] data_mem_0_1 [0:511]; // @[el2_ifu_ic_mem.scala 230:29]
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wire [70:0] data_mem_0_1__T_137_data; // @[el2_ifu_ic_mem.scala 230:29]
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wire [8:0] data_mem_0_1__T_137_addr; // @[el2_ifu_ic_mem.scala 230:29]
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wire [70:0] data_mem_0_1__T_144_data; // @[el2_ifu_ic_mem.scala 230:29]
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wire [8:0] data_mem_0_1__T_144_addr; // @[el2_ifu_ic_mem.scala 230:29]
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wire [70:0] data_mem_0_1__T_151_data; // @[el2_ifu_ic_mem.scala 230:29]
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wire [8:0] data_mem_0_1__T_151_addr; // @[el2_ifu_ic_mem.scala 230:29]
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wire [70:0] data_mem_0_1__T_158_data; // @[el2_ifu_ic_mem.scala 230:29]
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wire [8:0] data_mem_0_1__T_158_addr; // @[el2_ifu_ic_mem.scala 230:29]
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wire [70:0] data_mem_0_1__T_130_data; // @[el2_ifu_ic_mem.scala 230:29]
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wire [8:0] data_mem_0_1__T_130_addr; // @[el2_ifu_ic_mem.scala 230:29]
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wire data_mem_0_1__T_130_mask; // @[el2_ifu_ic_mem.scala 230:29]
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wire data_mem_0_1__T_130_en; // @[el2_ifu_ic_mem.scala 230:29]
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wire [70:0] data_mem_0_1__T_135_data; // @[el2_ifu_ic_mem.scala 230:29]
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wire [8:0] data_mem_0_1__T_135_addr; // @[el2_ifu_ic_mem.scala 230:29]
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wire data_mem_0_1__T_135_mask; // @[el2_ifu_ic_mem.scala 230:29]
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wire data_mem_0_1__T_135_en; // @[el2_ifu_ic_mem.scala 230:29]
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wire [70:0] data_mem_0_1__T_142_data; // @[el2_ifu_ic_mem.scala 230:29]
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wire [8:0] data_mem_0_1__T_142_addr; // @[el2_ifu_ic_mem.scala 230:29]
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wire data_mem_0_1__T_142_mask; // @[el2_ifu_ic_mem.scala 230:29]
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wire data_mem_0_1__T_142_en; // @[el2_ifu_ic_mem.scala 230:29]
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wire [70:0] data_mem_0_1__T_149_data; // @[el2_ifu_ic_mem.scala 230:29]
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wire [8:0] data_mem_0_1__T_149_addr; // @[el2_ifu_ic_mem.scala 230:29]
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wire data_mem_0_1__T_149_mask; // @[el2_ifu_ic_mem.scala 230:29]
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wire data_mem_0_1__T_149_en; // @[el2_ifu_ic_mem.scala 230:29]
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wire [70:0] data_mem_0_1__T_156_data; // @[el2_ifu_ic_mem.scala 230:29]
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wire [8:0] data_mem_0_1__T_156_addr; // @[el2_ifu_ic_mem.scala 230:29]
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wire data_mem_0_1__T_156_mask; // @[el2_ifu_ic_mem.scala 230:29]
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wire data_mem_0_1__T_156_en; // @[el2_ifu_ic_mem.scala 230:29]
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reg [8:0] data_mem_0_1__T_137_addr_pipe_0;
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reg [8:0] data_mem_0_1__T_144_addr_pipe_0;
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reg [8:0] data_mem_0_1__T_151_addr_pipe_0;
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reg [8:0] data_mem_0_1__T_158_addr_pipe_0;
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reg [70:0] data_mem_1_0 [0:511]; // @[el2_ifu_ic_mem.scala 245:29]
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wire [70:0] data_mem_1_0__T_137_data; // @[el2_ifu_ic_mem.scala 245:29]
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wire [8:0] data_mem_1_0__T_137_addr; // @[el2_ifu_ic_mem.scala 245:29]
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wire [70:0] data_mem_1_0__T_144_data; // @[el2_ifu_ic_mem.scala 245:29]
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wire [8:0] data_mem_1_0__T_144_addr; // @[el2_ifu_ic_mem.scala 245:29]
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wire [70:0] data_mem_1_0__T_151_data; // @[el2_ifu_ic_mem.scala 245:29]
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wire [8:0] data_mem_1_0__T_151_addr; // @[el2_ifu_ic_mem.scala 245:29]
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wire [70:0] data_mem_1_0__T_158_data; // @[el2_ifu_ic_mem.scala 245:29]
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wire [8:0] data_mem_1_0__T_158_addr; // @[el2_ifu_ic_mem.scala 245:29]
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wire [70:0] data_mem_1_0__T_130_data; // @[el2_ifu_ic_mem.scala 245:29]
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wire [8:0] data_mem_1_0__T_130_addr; // @[el2_ifu_ic_mem.scala 245:29]
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wire data_mem_1_0__T_130_mask; // @[el2_ifu_ic_mem.scala 245:29]
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wire data_mem_1_0__T_130_en; // @[el2_ifu_ic_mem.scala 245:29]
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wire [70:0] data_mem_1_0__T_135_data; // @[el2_ifu_ic_mem.scala 245:29]
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wire [8:0] data_mem_1_0__T_135_addr; // @[el2_ifu_ic_mem.scala 245:29]
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wire data_mem_1_0__T_135_mask; // @[el2_ifu_ic_mem.scala 245:29]
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wire data_mem_1_0__T_135_en; // @[el2_ifu_ic_mem.scala 245:29]
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wire [70:0] data_mem_1_0__T_142_data; // @[el2_ifu_ic_mem.scala 245:29]
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wire [8:0] data_mem_1_0__T_142_addr; // @[el2_ifu_ic_mem.scala 245:29]
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wire data_mem_1_0__T_142_mask; // @[el2_ifu_ic_mem.scala 245:29]
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wire data_mem_1_0__T_142_en; // @[el2_ifu_ic_mem.scala 245:29]
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wire [70:0] data_mem_1_0__T_149_data; // @[el2_ifu_ic_mem.scala 245:29]
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wire [8:0] data_mem_1_0__T_149_addr; // @[el2_ifu_ic_mem.scala 245:29]
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wire data_mem_1_0__T_149_mask; // @[el2_ifu_ic_mem.scala 245:29]
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wire data_mem_1_0__T_149_en; // @[el2_ifu_ic_mem.scala 245:29]
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wire [70:0] data_mem_1_0__T_156_data; // @[el2_ifu_ic_mem.scala 245:29]
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wire [8:0] data_mem_1_0__T_156_addr; // @[el2_ifu_ic_mem.scala 245:29]
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wire data_mem_1_0__T_156_mask; // @[el2_ifu_ic_mem.scala 245:29]
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wire data_mem_1_0__T_156_en; // @[el2_ifu_ic_mem.scala 245:29]
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reg [70:0] data_mem_1_0 [0:511]; // @[el2_ifu_ic_mem.scala 230:29]
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wire [70:0] data_mem_1_0__T_137_data; // @[el2_ifu_ic_mem.scala 230:29]
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wire [8:0] data_mem_1_0__T_137_addr; // @[el2_ifu_ic_mem.scala 230:29]
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wire [70:0] data_mem_1_0__T_144_data; // @[el2_ifu_ic_mem.scala 230:29]
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wire [8:0] data_mem_1_0__T_144_addr; // @[el2_ifu_ic_mem.scala 230:29]
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wire [70:0] data_mem_1_0__T_151_data; // @[el2_ifu_ic_mem.scala 230:29]
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wire [8:0] data_mem_1_0__T_151_addr; // @[el2_ifu_ic_mem.scala 230:29]
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wire [70:0] data_mem_1_0__T_158_data; // @[el2_ifu_ic_mem.scala 230:29]
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wire [8:0] data_mem_1_0__T_158_addr; // @[el2_ifu_ic_mem.scala 230:29]
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wire [70:0] data_mem_1_0__T_130_data; // @[el2_ifu_ic_mem.scala 230:29]
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wire [8:0] data_mem_1_0__T_130_addr; // @[el2_ifu_ic_mem.scala 230:29]
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wire data_mem_1_0__T_130_mask; // @[el2_ifu_ic_mem.scala 230:29]
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wire data_mem_1_0__T_130_en; // @[el2_ifu_ic_mem.scala 230:29]
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wire [70:0] data_mem_1_0__T_135_data; // @[el2_ifu_ic_mem.scala 230:29]
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wire [8:0] data_mem_1_0__T_135_addr; // @[el2_ifu_ic_mem.scala 230:29]
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wire data_mem_1_0__T_135_mask; // @[el2_ifu_ic_mem.scala 230:29]
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wire data_mem_1_0__T_135_en; // @[el2_ifu_ic_mem.scala 230:29]
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wire [70:0] data_mem_1_0__T_142_data; // @[el2_ifu_ic_mem.scala 230:29]
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wire [8:0] data_mem_1_0__T_142_addr; // @[el2_ifu_ic_mem.scala 230:29]
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wire data_mem_1_0__T_142_mask; // @[el2_ifu_ic_mem.scala 230:29]
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wire data_mem_1_0__T_142_en; // @[el2_ifu_ic_mem.scala 230:29]
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wire [70:0] data_mem_1_0__T_149_data; // @[el2_ifu_ic_mem.scala 230:29]
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wire [8:0] data_mem_1_0__T_149_addr; // @[el2_ifu_ic_mem.scala 230:29]
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wire data_mem_1_0__T_149_mask; // @[el2_ifu_ic_mem.scala 230:29]
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wire data_mem_1_0__T_149_en; // @[el2_ifu_ic_mem.scala 230:29]
|
||||
wire [70:0] data_mem_1_0__T_156_data; // @[el2_ifu_ic_mem.scala 230:29]
|
||||
wire [8:0] data_mem_1_0__T_156_addr; // @[el2_ifu_ic_mem.scala 230:29]
|
||||
wire data_mem_1_0__T_156_mask; // @[el2_ifu_ic_mem.scala 230:29]
|
||||
wire data_mem_1_0__T_156_en; // @[el2_ifu_ic_mem.scala 230:29]
|
||||
reg [8:0] data_mem_1_0__T_137_addr_pipe_0;
|
||||
reg [8:0] data_mem_1_0__T_144_addr_pipe_0;
|
||||
reg [8:0] data_mem_1_0__T_151_addr_pipe_0;
|
||||
reg [8:0] data_mem_1_0__T_158_addr_pipe_0;
|
||||
reg [70:0] data_mem_1_1 [0:511]; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
wire [70:0] data_mem_1_1__T_137_data; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
wire [8:0] data_mem_1_1__T_137_addr; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
wire [70:0] data_mem_1_1__T_144_data; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
wire [8:0] data_mem_1_1__T_144_addr; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
wire [70:0] data_mem_1_1__T_151_data; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
wire [8:0] data_mem_1_1__T_151_addr; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
wire [70:0] data_mem_1_1__T_158_data; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
wire [8:0] data_mem_1_1__T_158_addr; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
wire [70:0] data_mem_1_1__T_130_data; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
wire [8:0] data_mem_1_1__T_130_addr; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
wire data_mem_1_1__T_130_mask; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
wire data_mem_1_1__T_130_en; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
wire [70:0] data_mem_1_1__T_135_data; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
wire [8:0] data_mem_1_1__T_135_addr; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
wire data_mem_1_1__T_135_mask; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
wire data_mem_1_1__T_135_en; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
wire [70:0] data_mem_1_1__T_142_data; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
wire [8:0] data_mem_1_1__T_142_addr; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
wire data_mem_1_1__T_142_mask; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
wire data_mem_1_1__T_142_en; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
wire [70:0] data_mem_1_1__T_149_data; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
wire [8:0] data_mem_1_1__T_149_addr; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
wire data_mem_1_1__T_149_mask; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
wire data_mem_1_1__T_149_en; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
wire [70:0] data_mem_1_1__T_156_data; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
wire [8:0] data_mem_1_1__T_156_addr; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
wire data_mem_1_1__T_156_mask; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
wire data_mem_1_1__T_156_en; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
reg [70:0] data_mem_1_1 [0:511]; // @[el2_ifu_ic_mem.scala 230:29]
|
||||
wire [70:0] data_mem_1_1__T_137_data; // @[el2_ifu_ic_mem.scala 230:29]
|
||||
wire [8:0] data_mem_1_1__T_137_addr; // @[el2_ifu_ic_mem.scala 230:29]
|
||||
wire [70:0] data_mem_1_1__T_144_data; // @[el2_ifu_ic_mem.scala 230:29]
|
||||
wire [8:0] data_mem_1_1__T_144_addr; // @[el2_ifu_ic_mem.scala 230:29]
|
||||
wire [70:0] data_mem_1_1__T_151_data; // @[el2_ifu_ic_mem.scala 230:29]
|
||||
wire [8:0] data_mem_1_1__T_151_addr; // @[el2_ifu_ic_mem.scala 230:29]
|
||||
wire [70:0] data_mem_1_1__T_158_data; // @[el2_ifu_ic_mem.scala 230:29]
|
||||
wire [8:0] data_mem_1_1__T_158_addr; // @[el2_ifu_ic_mem.scala 230:29]
|
||||
wire [70:0] data_mem_1_1__T_130_data; // @[el2_ifu_ic_mem.scala 230:29]
|
||||
wire [8:0] data_mem_1_1__T_130_addr; // @[el2_ifu_ic_mem.scala 230:29]
|
||||
wire data_mem_1_1__T_130_mask; // @[el2_ifu_ic_mem.scala 230:29]
|
||||
wire data_mem_1_1__T_130_en; // @[el2_ifu_ic_mem.scala 230:29]
|
||||
wire [70:0] data_mem_1_1__T_135_data; // @[el2_ifu_ic_mem.scala 230:29]
|
||||
wire [8:0] data_mem_1_1__T_135_addr; // @[el2_ifu_ic_mem.scala 230:29]
|
||||
wire data_mem_1_1__T_135_mask; // @[el2_ifu_ic_mem.scala 230:29]
|
||||
wire data_mem_1_1__T_135_en; // @[el2_ifu_ic_mem.scala 230:29]
|
||||
wire [70:0] data_mem_1_1__T_142_data; // @[el2_ifu_ic_mem.scala 230:29]
|
||||
wire [8:0] data_mem_1_1__T_142_addr; // @[el2_ifu_ic_mem.scala 230:29]
|
||||
wire data_mem_1_1__T_142_mask; // @[el2_ifu_ic_mem.scala 230:29]
|
||||
wire data_mem_1_1__T_142_en; // @[el2_ifu_ic_mem.scala 230:29]
|
||||
wire [70:0] data_mem_1_1__T_149_data; // @[el2_ifu_ic_mem.scala 230:29]
|
||||
wire [8:0] data_mem_1_1__T_149_addr; // @[el2_ifu_ic_mem.scala 230:29]
|
||||
wire data_mem_1_1__T_149_mask; // @[el2_ifu_ic_mem.scala 230:29]
|
||||
wire data_mem_1_1__T_149_en; // @[el2_ifu_ic_mem.scala 230:29]
|
||||
wire [70:0] data_mem_1_1__T_156_data; // @[el2_ifu_ic_mem.scala 230:29]
|
||||
wire [8:0] data_mem_1_1__T_156_addr; // @[el2_ifu_ic_mem.scala 230:29]
|
||||
wire data_mem_1_1__T_156_mask; // @[el2_ifu_ic_mem.scala 230:29]
|
||||
wire data_mem_1_1__T_156_en; // @[el2_ifu_ic_mem.scala 230:29]
|
||||
reg [8:0] data_mem_1_1__T_137_addr_pipe_0;
|
||||
reg [8:0] data_mem_1_1__T_144_addr_pipe_0;
|
||||
reg [8:0] data_mem_1_1__T_151_addr_pipe_0;
|
||||
reg [8:0] data_mem_1_1__T_158_addr_pipe_0;
|
||||
wire _T = ~io_ic_debug_tag_array; // @[el2_ifu_ic_mem.scala 210:70]
|
||||
wire _T_1 = io_ic_debug_rd_en & _T; // @[el2_ifu_ic_mem.scala 210:68]
|
||||
wire _T = ~io_ic_debug_tag_array; // @[el2_ifu_ic_mem.scala 195:70]
|
||||
wire _T_1 = io_ic_debug_rd_en & _T; // @[el2_ifu_ic_mem.scala 195:68]
|
||||
wire [1:0] _T_3 = {_T_1,_T_1}; // @[Cat.scala 29:58]
|
||||
wire [1:0] ic_debug_rd_way_en = _T_3 & io_ic_debug_way; // @[el2_ifu_ic_mem.scala 210:94]
|
||||
wire _T_5 = io_ic_debug_wr_en & _T; // @[el2_ifu_ic_mem.scala 211:68]
|
||||
wire [1:0] ic_debug_rd_way_en = _T_3 & io_ic_debug_way; // @[el2_ifu_ic_mem.scala 195:94]
|
||||
wire _T_5 = io_ic_debug_wr_en & _T; // @[el2_ifu_ic_mem.scala 196:68]
|
||||
wire [1:0] _T_7 = {_T_5,_T_5}; // @[Cat.scala 29:58]
|
||||
wire [1:0] ic_debug_wr_way_en = _T_7 & io_ic_debug_way; // @[el2_ifu_ic_mem.scala 211:94]
|
||||
wire _T_9 = ~io_ic_debug_addr[3]; // @[el2_ifu_ic_mem.scala 213:107]
|
||||
wire [1:0] ic_debug_wr_way_en = _T_7 & io_ic_debug_way; // @[el2_ifu_ic_mem.scala 196:94]
|
||||
wire _T_9 = ~io_ic_debug_addr[3]; // @[el2_ifu_ic_mem.scala 198:107]
|
||||
wire [1:0] _T_11 = {_T_9,_T_9}; // @[Cat.scala 29:58]
|
||||
wire [1:0] _T_12 = ic_debug_wr_way_en & _T_11; // @[el2_ifu_ic_mem.scala 213:36]
|
||||
wire [1:0] _T_13 = io_ic_wr_en | _T_12; // @[el2_ifu_ic_mem.scala 213:16]
|
||||
wire [1:0] _T_12 = ic_debug_wr_way_en & _T_11; // @[el2_ifu_ic_mem.scala 198:36]
|
||||
wire [1:0] _T_13 = io_ic_wr_en | _T_12; // @[el2_ifu_ic_mem.scala 198:16]
|
||||
wire [1:0] _T_17 = {io_ic_debug_addr[3],io_ic_debug_addr[3]}; // @[Cat.scala 29:58]
|
||||
wire [1:0] _T_18 = ic_debug_wr_way_en & _T_17; // @[el2_ifu_ic_mem.scala 213:36]
|
||||
wire [1:0] _T_19 = io_ic_wr_en | _T_18; // @[el2_ifu_ic_mem.scala 213:16]
|
||||
wire _T_23 = _T_9 & io_ic_debug_wr_en; // @[el2_ifu_ic_mem.scala 215:66]
|
||||
wire [70:0] _T_25 = _T_23 ? io_ic_debug_wr_data : io_ic_wr_data_0; // @[el2_ifu_ic_mem.scala 215:8]
|
||||
wire _T_28 = io_ic_debug_addr[3] & io_ic_debug_wr_en; // @[el2_ifu_ic_mem.scala 215:66]
|
||||
wire [70:0] _T_30 = _T_28 ? io_ic_debug_wr_data : io_ic_wr_data_1; // @[el2_ifu_ic_mem.scala 215:8]
|
||||
wire _T_32 = io_ic_debug_rd_en | io_ic_debug_wr_en; // @[el2_ifu_ic_mem.scala 216:49]
|
||||
wire [1:0] _T_18 = ic_debug_wr_way_en & _T_17; // @[el2_ifu_ic_mem.scala 198:36]
|
||||
wire [1:0] _T_19 = io_ic_wr_en | _T_18; // @[el2_ifu_ic_mem.scala 198:16]
|
||||
wire _T_23 = _T_9 & io_ic_debug_wr_en; // @[el2_ifu_ic_mem.scala 200:66]
|
||||
wire [70:0] _T_25 = _T_23 ? io_ic_debug_wr_data : io_ic_wr_data_0; // @[el2_ifu_ic_mem.scala 200:8]
|
||||
wire _T_28 = io_ic_debug_addr[3] & io_ic_debug_wr_en; // @[el2_ifu_ic_mem.scala 200:66]
|
||||
wire [70:0] _T_30 = _T_28 ? io_ic_debug_wr_data : io_ic_wr_data_1; // @[el2_ifu_ic_mem.scala 200:8]
|
||||
wire _T_32 = io_ic_debug_rd_en | io_ic_debug_wr_en; // @[el2_ifu_ic_mem.scala 201:49]
|
||||
wire [11:0] _T_35 = {io_ic_debug_addr[12:3],2'h0}; // @[Cat.scala 29:58]
|
||||
wire [11:0] _T_37 = _T_32 ? _T_35 : io_ic_rw_addr[12:1]; // @[el2_ifu_ic_mem.scala 216:29]
|
||||
wire [11:0] _T_37 = _T_32 ? _T_35 : io_ic_rw_addr[12:1]; // @[el2_ifu_ic_mem.scala 201:29]
|
||||
wire [12:0] ic_rw_addr_q = {_T_37,1'h0}; // @[Cat.scala 29:58]
|
||||
wire _T_38 = io_ic_rd_en | io_ic_debug_rd_en; // @[el2_ifu_ic_mem.scala 217:44]
|
||||
wire _T_39 = |io_ic_wr_en; // @[el2_ifu_ic_mem.scala 217:82]
|
||||
wire _T_40 = ~_T_39; // @[el2_ifu_ic_mem.scala 217:68]
|
||||
wire ic_rd_en_with_debug = _T_38 & _T_40; // @[el2_ifu_ic_mem.scala 217:66]
|
||||
wire _T_43 = ~ic_rw_addr_q[3]; // @[el2_ifu_ic_mem.scala 219:15]
|
||||
wire _T_47 = ic_rw_addr_q[2:1] == 2'h3; // @[el2_ifu_ic_mem.scala 220:55]
|
||||
wire _T_48 = ic_rw_addr_q[3] & _T_47; // @[el2_ifu_ic_mem.scala 220:36]
|
||||
wire _T_58 = _T_43 & _T_47; // @[el2_ifu_ic_mem.scala 222:37]
|
||||
wire _T_38 = io_ic_rd_en | io_ic_debug_rd_en; // @[el2_ifu_ic_mem.scala 202:44]
|
||||
wire _T_39 = |io_ic_wr_en; // @[el2_ifu_ic_mem.scala 202:82]
|
||||
wire _T_40 = ~_T_39; // @[el2_ifu_ic_mem.scala 202:68]
|
||||
wire ic_rd_en_with_debug = _T_38 & _T_40; // @[el2_ifu_ic_mem.scala 202:66]
|
||||
wire _T_43 = ~ic_rw_addr_q[3]; // @[el2_ifu_ic_mem.scala 204:15]
|
||||
wire _T_47 = ic_rw_addr_q[2:1] == 2'h3; // @[el2_ifu_ic_mem.scala 205:55]
|
||||
wire _T_48 = ic_rw_addr_q[3] & _T_47; // @[el2_ifu_ic_mem.scala 205:36]
|
||||
wire _T_58 = _T_43 & _T_47; // @[el2_ifu_ic_mem.scala 207:37]
|
||||
wire _T_95 = ic_rw_addr_q[3] | _T_58; // @[Mux.scala 27:72]
|
||||
wire ic_b_rden_0 = _T_95 & ic_rd_en_with_debug; // @[el2_ifu_ic_mem.scala 222:107]
|
||||
wire ic_b_rden_0 = _T_95 & ic_rd_en_with_debug; // @[el2_ifu_ic_mem.scala 207:107]
|
||||
wire [1:0] _T_99 = {ic_b_rden_0,ic_b_rden_0}; // @[Cat.scala 29:58]
|
||||
wire [1:0] _GEN_24 = {{1'd0}, io_clk_override}; // @[el2_ifu_ic_mem.scala 225:62]
|
||||
wire [1:0] _T_100 = _T_99 | _GEN_24; // @[el2_ifu_ic_mem.scala 225:62]
|
||||
wire [1:0] _T_101 = _T_100 | _T_19; // @[el2_ifu_ic_mem.scala 225:80]
|
||||
wire [1:0] _T_105 = _T_100 | _T_13; // @[el2_ifu_ic_mem.scala 227:82]
|
||||
wire [1:0] _T_106 = _T_105 | _T_101; // @[el2_ifu_ic_mem.scala 227:101]
|
||||
wire [8:0] ic_rw_addr_q_inc = ic_rw_addr_q[12:4] + 9'h1; // @[el2_ifu_ic_mem.scala 230:77]
|
||||
wire _T_113 = _T_48 & ic_rd_en_with_debug; // @[el2_ifu_ic_mem.scala 231:82]
|
||||
wire ic_rw_addr_wrap = _T_113 & _T_40; // @[el2_ifu_ic_mem.scala 231:104]
|
||||
reg [12:0] ic_rw_addr_ff; // @[el2_ifu_ic_mem.scala 234:30]
|
||||
reg [1:0] ic_debug_rd_way_en_ff; // @[el2_ifu_ic_mem.scala 236:38]
|
||||
reg ic_debug_rd_en_ff; // @[el2_ifu_ic_mem.scala 237:34]
|
||||
wire _T_122 = ~ic_rw_addr_wrap; // @[el2_ifu_ic_mem.scala 241:31]
|
||||
wire [1:0] _GEN_24 = {{1'd0}, io_clk_override}; // @[el2_ifu_ic_mem.scala 210:62]
|
||||
wire [1:0] _T_100 = _T_99 | _GEN_24; // @[el2_ifu_ic_mem.scala 210:62]
|
||||
wire [1:0] _T_101 = _T_100 | _T_19; // @[el2_ifu_ic_mem.scala 210:80]
|
||||
wire [1:0] _T_105 = _T_100 | _T_13; // @[el2_ifu_ic_mem.scala 212:82]
|
||||
wire [1:0] _T_106 = _T_105 | _T_101; // @[el2_ifu_ic_mem.scala 212:101]
|
||||
wire [8:0] ic_rw_addr_q_inc = ic_rw_addr_q[12:4] + 9'h1; // @[el2_ifu_ic_mem.scala 215:77]
|
||||
wire _T_113 = _T_48 & ic_rd_en_with_debug; // @[el2_ifu_ic_mem.scala 216:82]
|
||||
wire ic_rw_addr_wrap = _T_113 & _T_40; // @[el2_ifu_ic_mem.scala 216:104]
|
||||
reg [12:0] ic_rw_addr_ff; // @[el2_ifu_ic_mem.scala 219:30]
|
||||
reg [1:0] ic_debug_rd_way_en_ff; // @[el2_ifu_ic_mem.scala 221:38]
|
||||
reg ic_debug_rd_en_ff; // @[el2_ifu_ic_mem.scala 222:34]
|
||||
wire _T_122 = ~ic_rw_addr_wrap; // @[el2_ifu_ic_mem.scala 226:31]
|
||||
wire [8:0] _T_126 = {ic_rw_addr_q[12:6],ic_rw_addr_q_inc[5:4]}; // @[Cat.scala 29:58]
|
||||
wire [8:0] _T_127 = _T_122 ? ic_rw_addr_q[12:4] : _T_126; // @[el2_ifu_ic_mem.scala 241:30]
|
||||
wire [12:0] ic_rw_addr_bank_q_0 = {{4'd0}, _T_127}; // @[el2_ifu_ic_mem.scala 240:31 el2_ifu_ic_mem.scala 241:24]
|
||||
wire [12:0] ic_rw_addr_bank_q_1 = {{4'd0}, ic_rw_addr_q[12:4]}; // @[el2_ifu_ic_mem.scala 240:31 el2_ifu_ic_mem.scala 242:24]
|
||||
wire _T_160 = ~ic_rw_addr_ff[3]; // @[el2_ifu_ic_mem.scala 259:71]
|
||||
wire [8:0] _T_127 = _T_122 ? ic_rw_addr_q[12:4] : _T_126; // @[el2_ifu_ic_mem.scala 226:30]
|
||||
wire [12:0] ic_rw_addr_bank_q_0 = {{4'd0}, _T_127}; // @[el2_ifu_ic_mem.scala 225:31 el2_ifu_ic_mem.scala 226:24]
|
||||
wire [12:0] ic_rw_addr_bank_q_1 = {{4'd0}, ic_rw_addr_q[12:4]}; // @[el2_ifu_ic_mem.scala 225:31 el2_ifu_ic_mem.scala 227:24]
|
||||
wire _T_160 = ~ic_rw_addr_ff[3]; // @[el2_ifu_ic_mem.scala 244:71]
|
||||
wire [9:0] _T_170 = {_T_160,_T_160,_T_160,_T_160,_T_160,_T_160,_T_160,_T_160,_T_160,_T_160}; // @[Cat.scala 29:58]
|
||||
wire [18:0] _T_179 = {_T_170,_T_160,_T_160,_T_160,_T_160,_T_160,_T_160,_T_160,_T_160,_T_160}; // @[Cat.scala 29:58]
|
||||
wire [27:0] _T_188 = {_T_179,_T_160,_T_160,_T_160,_T_160,_T_160,_T_160,_T_160,_T_160,_T_160}; // @[Cat.scala 29:58]
|
||||
|
|
@ -245,8 +245,8 @@ module EL2_IC_DATA(
|
|||
wire [54:0] _T_215 = {_T_206,_T_160,_T_160,_T_160,_T_160,_T_160,_T_160,_T_160,_T_160,_T_160}; // @[Cat.scala 29:58]
|
||||
wire [63:0] _T_224 = {_T_215,_T_160,_T_160,_T_160,_T_160,_T_160,_T_160,_T_160,_T_160,_T_160}; // @[Cat.scala 29:58]
|
||||
wire [70:0] _T_231 = {_T_224,_T_160,_T_160,_T_160,_T_160,_T_160,_T_160,_T_160}; // @[Cat.scala 29:58]
|
||||
wire [70:0] wb_dout_0_0 = data_mem_0_0__T_137_data; // @[el2_ifu_ic_mem.scala 247:21 el2_ifu_ic_mem.scala 250:19 el2_ifu_ic_mem.scala 254:19]
|
||||
wire [70:0] _T_232 = _T_231 & wb_dout_0_0; // @[el2_ifu_ic_mem.scala 259:78]
|
||||
wire [70:0] wb_dout_0_0 = data_mem_0_0__T_137_data; // @[el2_ifu_ic_mem.scala 232:21 el2_ifu_ic_mem.scala 235:19 el2_ifu_ic_mem.scala 239:19]
|
||||
wire [70:0] _T_232 = _T_231 & wb_dout_0_0; // @[el2_ifu_ic_mem.scala 244:78]
|
||||
wire [9:0] _T_244 = {ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3]}; // @[Cat.scala 29:58]
|
||||
wire [18:0] _T_253 = {_T_244,ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3]}; // @[Cat.scala 29:58]
|
||||
wire [27:0] _T_262 = {_T_253,ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3]}; // @[Cat.scala 29:58]
|
||||
|
|
@ -255,16 +255,16 @@ module EL2_IC_DATA(
|
|||
wire [54:0] _T_289 = {_T_280,ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3]}; // @[Cat.scala 29:58]
|
||||
wire [63:0] _T_298 = {_T_289,ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3]}; // @[Cat.scala 29:58]
|
||||
wire [70:0] _T_305 = {_T_298,ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3]}; // @[Cat.scala 29:58]
|
||||
wire [70:0] wb_dout_0_1 = data_mem_0_1__T_144_data; // @[el2_ifu_ic_mem.scala 247:21 el2_ifu_ic_mem.scala 250:19 el2_ifu_ic_mem.scala 254:19]
|
||||
wire [70:0] _T_306 = _T_305 & wb_dout_0_1; // @[el2_ifu_ic_mem.scala 259:78]
|
||||
wire [70:0] wb_dout_way_pre_lower_0 = _T_232 | _T_306; // @[el2_ifu_ic_mem.scala 259:102]
|
||||
wire [70:0] wb_dout_1_0 = data_mem_1_0__T_151_data; // @[el2_ifu_ic_mem.scala 247:21 el2_ifu_ic_mem.scala 250:19 el2_ifu_ic_mem.scala 254:19]
|
||||
wire [70:0] _T_380 = _T_231 & wb_dout_1_0; // @[el2_ifu_ic_mem.scala 259:78]
|
||||
wire [70:0] wb_dout_1_1 = data_mem_1_1__T_158_data; // @[el2_ifu_ic_mem.scala 247:21 el2_ifu_ic_mem.scala 250:19 el2_ifu_ic_mem.scala 254:19]
|
||||
wire [70:0] _T_454 = _T_305 & wb_dout_1_1; // @[el2_ifu_ic_mem.scala 259:78]
|
||||
wire [70:0] wb_dout_way_pre_lower_1 = _T_380 | _T_454; // @[el2_ifu_ic_mem.scala 259:102]
|
||||
wire _T_457 = 1'h0 - 1'h1; // @[el2_ifu_ic_mem.scala 263:77]
|
||||
wire _T_458 = ic_rw_addr_ff[3] == _T_457; // @[el2_ifu_ic_mem.scala 263:71]
|
||||
wire [70:0] wb_dout_0_1 = data_mem_0_1__T_144_data; // @[el2_ifu_ic_mem.scala 232:21 el2_ifu_ic_mem.scala 235:19 el2_ifu_ic_mem.scala 239:19]
|
||||
wire [70:0] _T_306 = _T_305 & wb_dout_0_1; // @[el2_ifu_ic_mem.scala 244:78]
|
||||
wire [70:0] wb_dout_way_pre_lower_0 = _T_232 | _T_306; // @[el2_ifu_ic_mem.scala 244:102]
|
||||
wire [70:0] wb_dout_1_0 = data_mem_1_0__T_151_data; // @[el2_ifu_ic_mem.scala 232:21 el2_ifu_ic_mem.scala 235:19 el2_ifu_ic_mem.scala 239:19]
|
||||
wire [70:0] _T_380 = _T_231 & wb_dout_1_0; // @[el2_ifu_ic_mem.scala 244:78]
|
||||
wire [70:0] wb_dout_1_1 = data_mem_1_1__T_158_data; // @[el2_ifu_ic_mem.scala 232:21 el2_ifu_ic_mem.scala 235:19 el2_ifu_ic_mem.scala 239:19]
|
||||
wire [70:0] _T_454 = _T_305 & wb_dout_1_1; // @[el2_ifu_ic_mem.scala 244:78]
|
||||
wire [70:0] wb_dout_way_pre_lower_1 = _T_380 | _T_454; // @[el2_ifu_ic_mem.scala 244:102]
|
||||
wire _T_457 = 1'h0 - 1'h1; // @[el2_ifu_ic_mem.scala 248:77]
|
||||
wire _T_458 = ic_rw_addr_ff[3] == _T_457; // @[el2_ifu_ic_mem.scala 248:71]
|
||||
wire [9:0] _T_468 = {_T_458,_T_458,_T_458,_T_458,_T_458,_T_458,_T_458,_T_458,_T_458,_T_458}; // @[Cat.scala 29:58]
|
||||
wire [18:0] _T_477 = {_T_468,_T_458,_T_458,_T_458,_T_458,_T_458,_T_458,_T_458,_T_458,_T_458}; // @[Cat.scala 29:58]
|
||||
wire [27:0] _T_486 = {_T_477,_T_458,_T_458,_T_458,_T_458,_T_458,_T_458,_T_458,_T_458,_T_458}; // @[Cat.scala 29:58]
|
||||
|
|
@ -273,15 +273,15 @@ module EL2_IC_DATA(
|
|||
wire [54:0] _T_513 = {_T_504,_T_458,_T_458,_T_458,_T_458,_T_458,_T_458,_T_458,_T_458,_T_458}; // @[Cat.scala 29:58]
|
||||
wire [63:0] _T_522 = {_T_513,_T_458,_T_458,_T_458,_T_458,_T_458,_T_458,_T_458,_T_458,_T_458}; // @[Cat.scala 29:58]
|
||||
wire [70:0] _T_529 = {_T_522,_T_458,_T_458,_T_458,_T_458,_T_458,_T_458,_T_458}; // @[Cat.scala 29:58]
|
||||
wire [70:0] _T_530 = _T_529 & wb_dout_0_0; // @[el2_ifu_ic_mem.scala 263:82]
|
||||
wire [70:0] _T_606 = _T_231 & wb_dout_0_1; // @[el2_ifu_ic_mem.scala 263:82]
|
||||
wire [70:0] wb_dout_way_pre_upper_0 = _T_530 | _T_606; // @[el2_ifu_ic_mem.scala 263:106]
|
||||
wire [70:0] _T_682 = _T_529 & wb_dout_1_0; // @[el2_ifu_ic_mem.scala 263:82]
|
||||
wire [70:0] _T_758 = _T_231 & wb_dout_1_1; // @[el2_ifu_ic_mem.scala 263:82]
|
||||
wire [70:0] wb_dout_way_pre_upper_1 = _T_682 | _T_758; // @[el2_ifu_ic_mem.scala 263:106]
|
||||
wire [70:0] _T_530 = _T_529 & wb_dout_0_0; // @[el2_ifu_ic_mem.scala 248:82]
|
||||
wire [70:0] _T_606 = _T_231 & wb_dout_0_1; // @[el2_ifu_ic_mem.scala 248:82]
|
||||
wire [70:0] wb_dout_way_pre_upper_0 = _T_530 | _T_606; // @[el2_ifu_ic_mem.scala 248:106]
|
||||
wire [70:0] _T_682 = _T_529 & wb_dout_1_0; // @[el2_ifu_ic_mem.scala 248:82]
|
||||
wire [70:0] _T_758 = _T_231 & wb_dout_1_1; // @[el2_ifu_ic_mem.scala 248:82]
|
||||
wire [70:0] wb_dout_way_pre_upper_1 = _T_682 | _T_758; // @[el2_ifu_ic_mem.scala 248:106]
|
||||
wire [141:0] wb_dout_way_pre_0 = {wb_dout_way_pre_upper_0,wb_dout_way_pre_lower_0}; // @[Cat.scala 29:58]
|
||||
wire [141:0] wb_dout_way_pre_1 = {wb_dout_way_pre_upper_1,wb_dout_way_pre_lower_1}; // @[Cat.scala 29:58]
|
||||
wire _T_760 = ic_rw_addr_ff[2:1] == 2'h0; // @[el2_ifu_ic_mem.scala 269:36]
|
||||
wire _T_760 = ic_rw_addr_ff[2:1] == 2'h0; // @[el2_ifu_ic_mem.scala 254:36]
|
||||
wire [9:0] _T_770 = {_T_760,_T_760,_T_760,_T_760,_T_760,_T_760,_T_760,_T_760,_T_760,_T_760}; // @[Cat.scala 29:58]
|
||||
wire [18:0] _T_779 = {_T_770,_T_760,_T_760,_T_760,_T_760,_T_760,_T_760,_T_760,_T_760,_T_760}; // @[Cat.scala 29:58]
|
||||
wire [27:0] _T_788 = {_T_779,_T_760,_T_760,_T_760,_T_760,_T_760,_T_760,_T_760,_T_760,_T_760}; // @[Cat.scala 29:58]
|
||||
|
|
@ -289,8 +289,8 @@ module EL2_IC_DATA(
|
|||
wire [45:0] _T_806 = {_T_797,_T_760,_T_760,_T_760,_T_760,_T_760,_T_760,_T_760,_T_760,_T_760}; // @[Cat.scala 29:58]
|
||||
wire [54:0] _T_815 = {_T_806,_T_760,_T_760,_T_760,_T_760,_T_760,_T_760,_T_760,_T_760,_T_760}; // @[Cat.scala 29:58]
|
||||
wire [63:0] _T_824 = {_T_815,_T_760,_T_760,_T_760,_T_760,_T_760,_T_760,_T_760,_T_760,_T_760}; // @[Cat.scala 29:58]
|
||||
wire [63:0] _T_826 = _T_824 & wb_dout_way_pre_0[63:0]; // @[el2_ifu_ic_mem.scala 269:44]
|
||||
wire _T_828 = ic_rw_addr_ff[2:1] == 2'h1; // @[el2_ifu_ic_mem.scala 270:36]
|
||||
wire [63:0] _T_826 = _T_824 & wb_dout_way_pre_0[63:0]; // @[el2_ifu_ic_mem.scala 254:44]
|
||||
wire _T_828 = ic_rw_addr_ff[2:1] == 2'h1; // @[el2_ifu_ic_mem.scala 255:36]
|
||||
wire [9:0] _T_838 = {_T_828,_T_828,_T_828,_T_828,_T_828,_T_828,_T_828,_T_828,_T_828,_T_828}; // @[Cat.scala 29:58]
|
||||
wire [18:0] _T_847 = {_T_838,_T_828,_T_828,_T_828,_T_828,_T_828,_T_828,_T_828,_T_828,_T_828}; // @[Cat.scala 29:58]
|
||||
wire [27:0] _T_856 = {_T_847,_T_828,_T_828,_T_828,_T_828,_T_828,_T_828,_T_828,_T_828,_T_828}; // @[Cat.scala 29:58]
|
||||
|
|
@ -299,9 +299,9 @@ module EL2_IC_DATA(
|
|||
wire [54:0] _T_883 = {_T_874,_T_828,_T_828,_T_828,_T_828,_T_828,_T_828,_T_828,_T_828,_T_828}; // @[Cat.scala 29:58]
|
||||
wire [63:0] _T_892 = {_T_883,_T_828,_T_828,_T_828,_T_828,_T_828,_T_828,_T_828,_T_828,_T_828}; // @[Cat.scala 29:58]
|
||||
wire [63:0] _T_895 = {wb_dout_way_pre_0[86:71],wb_dout_way_pre_0[63:16]}; // @[Cat.scala 29:58]
|
||||
wire [63:0] _T_896 = _T_892 & _T_895; // @[el2_ifu_ic_mem.scala 270:44]
|
||||
wire [63:0] _T_897 = _T_826 | _T_896; // @[el2_ifu_ic_mem.scala 269:71]
|
||||
wire _T_899 = ic_rw_addr_ff[2:1] == 2'h2; // @[el2_ifu_ic_mem.scala 271:36]
|
||||
wire [63:0] _T_896 = _T_892 & _T_895; // @[el2_ifu_ic_mem.scala 255:44]
|
||||
wire [63:0] _T_897 = _T_826 | _T_896; // @[el2_ifu_ic_mem.scala 254:71]
|
||||
wire _T_899 = ic_rw_addr_ff[2:1] == 2'h2; // @[el2_ifu_ic_mem.scala 256:36]
|
||||
wire [9:0] _T_909 = {_T_899,_T_899,_T_899,_T_899,_T_899,_T_899,_T_899,_T_899,_T_899,_T_899}; // @[Cat.scala 29:58]
|
||||
wire [18:0] _T_918 = {_T_909,_T_899,_T_899,_T_899,_T_899,_T_899,_T_899,_T_899,_T_899,_T_899}; // @[Cat.scala 29:58]
|
||||
wire [27:0] _T_927 = {_T_918,_T_899,_T_899,_T_899,_T_899,_T_899,_T_899,_T_899,_T_899,_T_899}; // @[Cat.scala 29:58]
|
||||
|
|
@ -310,9 +310,9 @@ module EL2_IC_DATA(
|
|||
wire [54:0] _T_954 = {_T_945,_T_899,_T_899,_T_899,_T_899,_T_899,_T_899,_T_899,_T_899,_T_899}; // @[Cat.scala 29:58]
|
||||
wire [63:0] _T_963 = {_T_954,_T_899,_T_899,_T_899,_T_899,_T_899,_T_899,_T_899,_T_899,_T_899}; // @[Cat.scala 29:58]
|
||||
wire [63:0] _T_966 = {wb_dout_way_pre_0[102:71],wb_dout_way_pre_0[63:32]}; // @[Cat.scala 29:58]
|
||||
wire [63:0] _T_967 = _T_963 & _T_966; // @[el2_ifu_ic_mem.scala 271:44]
|
||||
wire [63:0] _T_968 = _T_897 | _T_967; // @[el2_ifu_ic_mem.scala 270:122]
|
||||
wire _T_970 = ic_rw_addr_ff[2:1] == 2'h3; // @[el2_ifu_ic_mem.scala 272:36]
|
||||
wire [63:0] _T_967 = _T_963 & _T_966; // @[el2_ifu_ic_mem.scala 256:44]
|
||||
wire [63:0] _T_968 = _T_897 | _T_967; // @[el2_ifu_ic_mem.scala 255:122]
|
||||
wire _T_970 = ic_rw_addr_ff[2:1] == 2'h3; // @[el2_ifu_ic_mem.scala 257:36]
|
||||
wire [9:0] _T_980 = {_T_970,_T_970,_T_970,_T_970,_T_970,_T_970,_T_970,_T_970,_T_970,_T_970}; // @[Cat.scala 29:58]
|
||||
wire [18:0] _T_989 = {_T_980,_T_970,_T_970,_T_970,_T_970,_T_970,_T_970,_T_970,_T_970,_T_970}; // @[Cat.scala 29:58]
|
||||
wire [27:0] _T_998 = {_T_989,_T_970,_T_970,_T_970,_T_970,_T_970,_T_970,_T_970,_T_970,_T_970}; // @[Cat.scala 29:58]
|
||||
|
|
@ -321,23 +321,23 @@ module EL2_IC_DATA(
|
|||
wire [54:0] _T_1025 = {_T_1016,_T_970,_T_970,_T_970,_T_970,_T_970,_T_970,_T_970,_T_970,_T_970}; // @[Cat.scala 29:58]
|
||||
wire [63:0] _T_1034 = {_T_1025,_T_970,_T_970,_T_970,_T_970,_T_970,_T_970,_T_970,_T_970,_T_970}; // @[Cat.scala 29:58]
|
||||
wire [63:0] _T_1037 = {wb_dout_way_pre_0[118:71],wb_dout_way_pre_0[63:48]}; // @[Cat.scala 29:58]
|
||||
wire [63:0] _T_1038 = _T_1034 & _T_1037; // @[el2_ifu_ic_mem.scala 272:44]
|
||||
wire [63:0] wb_dout_way_0 = _T_968 | _T_1038; // @[el2_ifu_ic_mem.scala 271:122]
|
||||
wire [63:0] _T_1106 = _T_824 & wb_dout_way_pre_1[63:0]; // @[el2_ifu_ic_mem.scala 269:44]
|
||||
wire [63:0] _T_1038 = _T_1034 & _T_1037; // @[el2_ifu_ic_mem.scala 257:44]
|
||||
wire [63:0] wb_dout_way_0 = _T_968 | _T_1038; // @[el2_ifu_ic_mem.scala 256:122]
|
||||
wire [63:0] _T_1106 = _T_824 & wb_dout_way_pre_1[63:0]; // @[el2_ifu_ic_mem.scala 254:44]
|
||||
wire [63:0] _T_1175 = {wb_dout_way_pre_1[86:71],wb_dout_way_pre_1[63:16]}; // @[Cat.scala 29:58]
|
||||
wire [63:0] _T_1176 = _T_892 & _T_1175; // @[el2_ifu_ic_mem.scala 270:44]
|
||||
wire [63:0] _T_1177 = _T_1106 | _T_1176; // @[el2_ifu_ic_mem.scala 269:71]
|
||||
wire [63:0] _T_1176 = _T_892 & _T_1175; // @[el2_ifu_ic_mem.scala 255:44]
|
||||
wire [63:0] _T_1177 = _T_1106 | _T_1176; // @[el2_ifu_ic_mem.scala 254:71]
|
||||
wire [63:0] _T_1246 = {wb_dout_way_pre_1[102:71],wb_dout_way_pre_1[63:32]}; // @[Cat.scala 29:58]
|
||||
wire [63:0] _T_1247 = _T_963 & _T_1246; // @[el2_ifu_ic_mem.scala 271:44]
|
||||
wire [63:0] _T_1248 = _T_1177 | _T_1247; // @[el2_ifu_ic_mem.scala 270:122]
|
||||
wire [63:0] _T_1247 = _T_963 & _T_1246; // @[el2_ifu_ic_mem.scala 256:44]
|
||||
wire [63:0] _T_1248 = _T_1177 | _T_1247; // @[el2_ifu_ic_mem.scala 255:122]
|
||||
wire [63:0] _T_1317 = {wb_dout_way_pre_1[118:71],wb_dout_way_pre_1[63:48]}; // @[Cat.scala 29:58]
|
||||
wire [63:0] _T_1318 = _T_1034 & _T_1317; // @[el2_ifu_ic_mem.scala 272:44]
|
||||
wire [63:0] wb_dout_way_1 = _T_1248 | _T_1318; // @[el2_ifu_ic_mem.scala 271:122]
|
||||
wire [1:0] ic_rd_hit_q = ic_debug_rd_en_ff ? ic_debug_rd_way_en_ff : io_ic_rd_hit; // @[el2_ifu_ic_mem.scala 275:24]
|
||||
wire [63:0] wb_dout_way_with_premux_0 = io_ic_sel_premux_data ? io_ic_premux_data : wb_dout_way_0; // @[el2_ifu_ic_mem.scala 276:52]
|
||||
wire [63:0] wb_dout_way_with_premux_1 = io_ic_sel_premux_data ? io_ic_premux_data : wb_dout_way_1; // @[el2_ifu_ic_mem.scala 276:52]
|
||||
wire _T_1321 = ic_rd_hit_q[0] | io_ic_sel_premux_data; // @[el2_ifu_ic_mem.scala 282:79]
|
||||
wire _T_1323 = ic_rd_hit_q[1] | io_ic_sel_premux_data; // @[el2_ifu_ic_mem.scala 282:79]
|
||||
wire [63:0] _T_1318 = _T_1034 & _T_1317; // @[el2_ifu_ic_mem.scala 257:44]
|
||||
wire [63:0] wb_dout_way_1 = _T_1248 | _T_1318; // @[el2_ifu_ic_mem.scala 256:122]
|
||||
wire [1:0] ic_rd_hit_q = ic_debug_rd_en_ff ? ic_debug_rd_way_en_ff : io_ic_rd_hit; // @[el2_ifu_ic_mem.scala 260:24]
|
||||
wire [63:0] wb_dout_way_with_premux_0 = io_ic_sel_premux_data ? io_ic_premux_data : wb_dout_way_0; // @[el2_ifu_ic_mem.scala 261:52]
|
||||
wire [63:0] wb_dout_way_with_premux_1 = io_ic_sel_premux_data ? io_ic_premux_data : wb_dout_way_1; // @[el2_ifu_ic_mem.scala 261:52]
|
||||
wire _T_1321 = ic_rd_hit_q[0] | io_ic_sel_premux_data; // @[el2_ifu_ic_mem.scala 267:79]
|
||||
wire _T_1323 = ic_rd_hit_q[1] | io_ic_sel_premux_data; // @[el2_ifu_ic_mem.scala 267:79]
|
||||
wire [9:0] _T_1333 = {_T_1321,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321}; // @[Cat.scala 29:58]
|
||||
wire [18:0] _T_1342 = {_T_1333,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321}; // @[Cat.scala 29:58]
|
||||
wire [27:0] _T_1351 = {_T_1342,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321}; // @[Cat.scala 29:58]
|
||||
|
|
@ -345,7 +345,7 @@ module EL2_IC_DATA(
|
|||
wire [45:0] _T_1369 = {_T_1360,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321}; // @[Cat.scala 29:58]
|
||||
wire [54:0] _T_1378 = {_T_1369,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321}; // @[Cat.scala 29:58]
|
||||
wire [63:0] _T_1387 = {_T_1378,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321}; // @[Cat.scala 29:58]
|
||||
wire [63:0] _T_1388 = _T_1387 & wb_dout_way_with_premux_0; // @[el2_lib.scala 189:94]
|
||||
wire [63:0] _T_1388 = _T_1387 & wb_dout_way_with_premux_0; // @[el2_lib.scala 190:94]
|
||||
wire [9:0] _T_1398 = {_T_1323,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323}; // @[Cat.scala 29:58]
|
||||
wire [18:0] _T_1407 = {_T_1398,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323}; // @[Cat.scala 29:58]
|
||||
wire [27:0] _T_1416 = {_T_1407,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323}; // @[Cat.scala 29:58]
|
||||
|
|
@ -353,7 +353,7 @@ module EL2_IC_DATA(
|
|||
wire [45:0] _T_1434 = {_T_1425,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323}; // @[Cat.scala 29:58]
|
||||
wire [54:0] _T_1443 = {_T_1434,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323}; // @[Cat.scala 29:58]
|
||||
wire [63:0] _T_1452 = {_T_1443,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323}; // @[Cat.scala 29:58]
|
||||
wire [63:0] _T_1453 = _T_1452 & wb_dout_way_with_premux_1; // @[el2_lib.scala 189:94]
|
||||
wire [63:0] _T_1453 = _T_1452 & wb_dout_way_with_premux_1; // @[el2_lib.scala 190:94]
|
||||
wire [9:0] _T_1468 = {ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0]}; // @[Cat.scala 29:58]
|
||||
wire [18:0] _T_1477 = {_T_1468,ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0]}; // @[Cat.scala 29:58]
|
||||
wire [27:0] _T_1486 = {_T_1477,ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0]}; // @[Cat.scala 29:58]
|
||||
|
|
@ -362,7 +362,7 @@ module EL2_IC_DATA(
|
|||
wire [54:0] _T_1513 = {_T_1504,ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0]}; // @[Cat.scala 29:58]
|
||||
wire [63:0] _T_1522 = {_T_1513,ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0]}; // @[Cat.scala 29:58]
|
||||
wire [70:0] _T_1529 = {_T_1522,ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0]}; // @[Cat.scala 29:58]
|
||||
wire [70:0] _T_1530 = _T_1529 & wb_dout_way_pre_0[70:0]; // @[el2_lib.scala 189:94]
|
||||
wire [70:0] _T_1530 = _T_1529 & wb_dout_way_pre_0[70:0]; // @[el2_lib.scala 190:94]
|
||||
wire [9:0] _T_1540 = {ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1]}; // @[Cat.scala 29:58]
|
||||
wire [18:0] _T_1549 = {_T_1540,ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1]}; // @[Cat.scala 29:58]
|
||||
wire [27:0] _T_1558 = {_T_1549,ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1]}; // @[Cat.scala 29:58]
|
||||
|
|
@ -371,15 +371,15 @@ module EL2_IC_DATA(
|
|||
wire [54:0] _T_1585 = {_T_1576,ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1]}; // @[Cat.scala 29:58]
|
||||
wire [63:0] _T_1594 = {_T_1585,ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1]}; // @[Cat.scala 29:58]
|
||||
wire [70:0] _T_1601 = {_T_1594,ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1]}; // @[Cat.scala 29:58]
|
||||
wire [70:0] _T_1602 = _T_1601 & wb_dout_way_pre_1[70:0]; // @[el2_lib.scala 189:94]
|
||||
wire [70:0] _T_1602 = _T_1601 & wb_dout_way_pre_1[70:0]; // @[el2_lib.scala 190:94]
|
||||
assign data_mem_0_0__T_137_addr = data_mem_0_0__T_137_addr_pipe_0;
|
||||
assign data_mem_0_0__T_137_data = data_mem_0_0[data_mem_0_0__T_137_addr]; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
assign data_mem_0_0__T_137_data = data_mem_0_0[data_mem_0_0__T_137_addr]; // @[el2_ifu_ic_mem.scala 230:29]
|
||||
assign data_mem_0_0__T_144_addr = data_mem_0_0__T_144_addr_pipe_0;
|
||||
assign data_mem_0_0__T_144_data = data_mem_0_0[data_mem_0_0__T_144_addr]; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
assign data_mem_0_0__T_144_data = data_mem_0_0[data_mem_0_0__T_144_addr]; // @[el2_ifu_ic_mem.scala 230:29]
|
||||
assign data_mem_0_0__T_151_addr = data_mem_0_0__T_151_addr_pipe_0;
|
||||
assign data_mem_0_0__T_151_data = data_mem_0_0[data_mem_0_0__T_151_addr]; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
assign data_mem_0_0__T_151_data = data_mem_0_0[data_mem_0_0__T_151_addr]; // @[el2_ifu_ic_mem.scala 230:29]
|
||||
assign data_mem_0_0__T_158_addr = data_mem_0_0__T_158_addr_pipe_0;
|
||||
assign data_mem_0_0__T_158_data = data_mem_0_0[data_mem_0_0__T_158_addr]; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
assign data_mem_0_0__T_158_data = data_mem_0_0[data_mem_0_0__T_158_addr]; // @[el2_ifu_ic_mem.scala 230:29]
|
||||
assign data_mem_0_0__T_130_data = _T_28 ? io_ic_debug_wr_data : io_ic_wr_data_1;
|
||||
assign data_mem_0_0__T_130_addr = ic_rw_addr_bank_q_0[12:4];
|
||||
assign data_mem_0_0__T_130_mask = 1'h1;
|
||||
|
|
@ -401,13 +401,13 @@ module EL2_IC_DATA(
|
|||
assign data_mem_0_0__T_156_mask = 1'h0;
|
||||
assign data_mem_0_0__T_156_en = _T_25[1] & _T_106[1];
|
||||
assign data_mem_0_1__T_137_addr = data_mem_0_1__T_137_addr_pipe_0;
|
||||
assign data_mem_0_1__T_137_data = data_mem_0_1[data_mem_0_1__T_137_addr]; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
assign data_mem_0_1__T_137_data = data_mem_0_1[data_mem_0_1__T_137_addr]; // @[el2_ifu_ic_mem.scala 230:29]
|
||||
assign data_mem_0_1__T_144_addr = data_mem_0_1__T_144_addr_pipe_0;
|
||||
assign data_mem_0_1__T_144_data = data_mem_0_1[data_mem_0_1__T_144_addr]; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
assign data_mem_0_1__T_144_data = data_mem_0_1[data_mem_0_1__T_144_addr]; // @[el2_ifu_ic_mem.scala 230:29]
|
||||
assign data_mem_0_1__T_151_addr = data_mem_0_1__T_151_addr_pipe_0;
|
||||
assign data_mem_0_1__T_151_data = data_mem_0_1[data_mem_0_1__T_151_addr]; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
assign data_mem_0_1__T_151_data = data_mem_0_1[data_mem_0_1__T_151_addr]; // @[el2_ifu_ic_mem.scala 230:29]
|
||||
assign data_mem_0_1__T_158_addr = data_mem_0_1__T_158_addr_pipe_0;
|
||||
assign data_mem_0_1__T_158_data = data_mem_0_1[data_mem_0_1__T_158_addr]; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
assign data_mem_0_1__T_158_data = data_mem_0_1[data_mem_0_1__T_158_addr]; // @[el2_ifu_ic_mem.scala 230:29]
|
||||
assign data_mem_0_1__T_130_data = 71'h0;
|
||||
assign data_mem_0_1__T_130_addr = ic_rw_addr_bank_q_0[12:4];
|
||||
assign data_mem_0_1__T_130_mask = 1'h0;
|
||||
|
|
@ -429,13 +429,13 @@ module EL2_IC_DATA(
|
|||
assign data_mem_0_1__T_156_mask = 1'h0;
|
||||
assign data_mem_0_1__T_156_en = _T_25[1] & _T_106[1];
|
||||
assign data_mem_1_0__T_137_addr = data_mem_1_0__T_137_addr_pipe_0;
|
||||
assign data_mem_1_0__T_137_data = data_mem_1_0[data_mem_1_0__T_137_addr]; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
assign data_mem_1_0__T_137_data = data_mem_1_0[data_mem_1_0__T_137_addr]; // @[el2_ifu_ic_mem.scala 230:29]
|
||||
assign data_mem_1_0__T_144_addr = data_mem_1_0__T_144_addr_pipe_0;
|
||||
assign data_mem_1_0__T_144_data = data_mem_1_0[data_mem_1_0__T_144_addr]; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
assign data_mem_1_0__T_144_data = data_mem_1_0[data_mem_1_0__T_144_addr]; // @[el2_ifu_ic_mem.scala 230:29]
|
||||
assign data_mem_1_0__T_151_addr = data_mem_1_0__T_151_addr_pipe_0;
|
||||
assign data_mem_1_0__T_151_data = data_mem_1_0[data_mem_1_0__T_151_addr]; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
assign data_mem_1_0__T_151_data = data_mem_1_0[data_mem_1_0__T_151_addr]; // @[el2_ifu_ic_mem.scala 230:29]
|
||||
assign data_mem_1_0__T_158_addr = data_mem_1_0__T_158_addr_pipe_0;
|
||||
assign data_mem_1_0__T_158_data = data_mem_1_0[data_mem_1_0__T_158_addr]; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
assign data_mem_1_0__T_158_data = data_mem_1_0[data_mem_1_0__T_158_addr]; // @[el2_ifu_ic_mem.scala 230:29]
|
||||
assign data_mem_1_0__T_130_data = 71'h0;
|
||||
assign data_mem_1_0__T_130_addr = ic_rw_addr_bank_q_0[12:4];
|
||||
assign data_mem_1_0__T_130_mask = 1'h0;
|
||||
|
|
@ -457,13 +457,13 @@ module EL2_IC_DATA(
|
|||
assign data_mem_1_0__T_156_mask = 1'h0;
|
||||
assign data_mem_1_0__T_156_en = _T_25[1] & _T_106[1];
|
||||
assign data_mem_1_1__T_137_addr = data_mem_1_1__T_137_addr_pipe_0;
|
||||
assign data_mem_1_1__T_137_data = data_mem_1_1[data_mem_1_1__T_137_addr]; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
assign data_mem_1_1__T_137_data = data_mem_1_1[data_mem_1_1__T_137_addr]; // @[el2_ifu_ic_mem.scala 230:29]
|
||||
assign data_mem_1_1__T_144_addr = data_mem_1_1__T_144_addr_pipe_0;
|
||||
assign data_mem_1_1__T_144_data = data_mem_1_1[data_mem_1_1__T_144_addr]; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
assign data_mem_1_1__T_144_data = data_mem_1_1[data_mem_1_1__T_144_addr]; // @[el2_ifu_ic_mem.scala 230:29]
|
||||
assign data_mem_1_1__T_151_addr = data_mem_1_1__T_151_addr_pipe_0;
|
||||
assign data_mem_1_1__T_151_data = data_mem_1_1[data_mem_1_1__T_151_addr]; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
assign data_mem_1_1__T_151_data = data_mem_1_1[data_mem_1_1__T_151_addr]; // @[el2_ifu_ic_mem.scala 230:29]
|
||||
assign data_mem_1_1__T_158_addr = data_mem_1_1__T_158_addr_pipe_0;
|
||||
assign data_mem_1_1__T_158_data = data_mem_1_1[data_mem_1_1__T_158_addr]; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
assign data_mem_1_1__T_158_data = data_mem_1_1[data_mem_1_1__T_158_addr]; // @[el2_ifu_ic_mem.scala 230:29]
|
||||
assign data_mem_1_1__T_130_data = 71'h0;
|
||||
assign data_mem_1_1__T_130_addr = ic_rw_addr_bank_q_0[12:4];
|
||||
assign data_mem_1_1__T_130_mask = 1'h0;
|
||||
|
|
@ -484,15 +484,15 @@ module EL2_IC_DATA(
|
|||
assign data_mem_1_1__T_156_addr = ic_rw_addr_bank_q_1[12:4];
|
||||
assign data_mem_1_1__T_156_mask = 1'h1;
|
||||
assign data_mem_1_1__T_156_en = _T_25[1] & _T_106[1];
|
||||
assign io_ic_rd_data = _T_1388 | _T_1453; // @[el2_ifu_ic_mem.scala 282:17]
|
||||
assign io_ic_debug_rd_data = _T_1530 | _T_1602; // @[el2_ifu_ic_mem.scala 278:23 el2_ifu_ic_mem.scala 284:23]
|
||||
assign io_ic_parerr = 2'h0; // @[el2_ifu_ic_mem.scala 279:16]
|
||||
assign io_ic_eccerr = 2'h0; // @[el2_ifu_ic_mem.scala 280:16]
|
||||
assign io_test_port2 = 1'h0; // @[el2_ifu_ic_mem.scala 288:17]
|
||||
assign io_test_port_0_0 = data_mem_0_0__T_137_data; // @[el2_ifu_ic_mem.scala 289:16]
|
||||
assign io_test_port_0_1 = data_mem_0_1__T_144_data; // @[el2_ifu_ic_mem.scala 289:16]
|
||||
assign io_test_port_1_0 = data_mem_1_0__T_151_data; // @[el2_ifu_ic_mem.scala 289:16]
|
||||
assign io_test_port_1_1 = data_mem_1_1__T_158_data; // @[el2_ifu_ic_mem.scala 289:16]
|
||||
assign io_ic_rd_data = _T_1388 | _T_1453; // @[el2_ifu_ic_mem.scala 267:17]
|
||||
assign io_ic_debug_rd_data = _T_1530 | _T_1602; // @[el2_ifu_ic_mem.scala 263:23 el2_ifu_ic_mem.scala 269:23]
|
||||
assign io_ic_parerr = 2'h0; // @[el2_ifu_ic_mem.scala 264:16]
|
||||
assign io_ic_eccerr = 2'h0; // @[el2_ifu_ic_mem.scala 265:16]
|
||||
assign io_test_port2 = 1'h0; // @[el2_ifu_ic_mem.scala 273:17]
|
||||
assign io_test_port_0_0 = data_mem_0_0__T_137_data; // @[el2_ifu_ic_mem.scala 274:16]
|
||||
assign io_test_port_0_1 = data_mem_0_1__T_144_data; // @[el2_ifu_ic_mem.scala 274:16]
|
||||
assign io_test_port_1_0 = data_mem_1_0__T_151_data; // @[el2_ifu_ic_mem.scala 274:16]
|
||||
assign io_test_port_1_1 = data_mem_1_1__T_158_data; // @[el2_ifu_ic_mem.scala 274:16]
|
||||
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
||||
`define RANDOMIZE
|
||||
`endif
|
||||
|
|
@ -589,76 +589,76 @@ end // initial
|
|||
`endif // SYNTHESIS
|
||||
always @(posedge clock) begin
|
||||
if(data_mem_0_0__T_130_en & data_mem_0_0__T_130_mask) begin
|
||||
data_mem_0_0[data_mem_0_0__T_130_addr] <= data_mem_0_0__T_130_data; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
data_mem_0_0[data_mem_0_0__T_130_addr] <= data_mem_0_0__T_130_data; // @[el2_ifu_ic_mem.scala 230:29]
|
||||
end
|
||||
if(data_mem_0_0__T_135_en & data_mem_0_0__T_135_mask) begin
|
||||
data_mem_0_0[data_mem_0_0__T_135_addr] <= data_mem_0_0__T_135_data; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
data_mem_0_0[data_mem_0_0__T_135_addr] <= data_mem_0_0__T_135_data; // @[el2_ifu_ic_mem.scala 230:29]
|
||||
end
|
||||
if(data_mem_0_0__T_142_en & data_mem_0_0__T_142_mask) begin
|
||||
data_mem_0_0[data_mem_0_0__T_142_addr] <= data_mem_0_0__T_142_data; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
data_mem_0_0[data_mem_0_0__T_142_addr] <= data_mem_0_0__T_142_data; // @[el2_ifu_ic_mem.scala 230:29]
|
||||
end
|
||||
if(data_mem_0_0__T_149_en & data_mem_0_0__T_149_mask) begin
|
||||
data_mem_0_0[data_mem_0_0__T_149_addr] <= data_mem_0_0__T_149_data; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
data_mem_0_0[data_mem_0_0__T_149_addr] <= data_mem_0_0__T_149_data; // @[el2_ifu_ic_mem.scala 230:29]
|
||||
end
|
||||
if(data_mem_0_0__T_156_en & data_mem_0_0__T_156_mask) begin
|
||||
data_mem_0_0[data_mem_0_0__T_156_addr] <= data_mem_0_0__T_156_data; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
data_mem_0_0[data_mem_0_0__T_156_addr] <= data_mem_0_0__T_156_data; // @[el2_ifu_ic_mem.scala 230:29]
|
||||
end
|
||||
data_mem_0_0__T_137_addr_pipe_0 <= ic_rw_addr_bank_q_0[12:4];
|
||||
data_mem_0_0__T_144_addr_pipe_0 <= ic_rw_addr_bank_q_1[12:4];
|
||||
data_mem_0_0__T_151_addr_pipe_0 <= ic_rw_addr_bank_q_0[12:4];
|
||||
data_mem_0_0__T_158_addr_pipe_0 <= ic_rw_addr_bank_q_1[12:4];
|
||||
if(data_mem_0_1__T_130_en & data_mem_0_1__T_130_mask) begin
|
||||
data_mem_0_1[data_mem_0_1__T_130_addr] <= data_mem_0_1__T_130_data; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
data_mem_0_1[data_mem_0_1__T_130_addr] <= data_mem_0_1__T_130_data; // @[el2_ifu_ic_mem.scala 230:29]
|
||||
end
|
||||
if(data_mem_0_1__T_135_en & data_mem_0_1__T_135_mask) begin
|
||||
data_mem_0_1[data_mem_0_1__T_135_addr] <= data_mem_0_1__T_135_data; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
data_mem_0_1[data_mem_0_1__T_135_addr] <= data_mem_0_1__T_135_data; // @[el2_ifu_ic_mem.scala 230:29]
|
||||
end
|
||||
if(data_mem_0_1__T_142_en & data_mem_0_1__T_142_mask) begin
|
||||
data_mem_0_1[data_mem_0_1__T_142_addr] <= data_mem_0_1__T_142_data; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
data_mem_0_1[data_mem_0_1__T_142_addr] <= data_mem_0_1__T_142_data; // @[el2_ifu_ic_mem.scala 230:29]
|
||||
end
|
||||
if(data_mem_0_1__T_149_en & data_mem_0_1__T_149_mask) begin
|
||||
data_mem_0_1[data_mem_0_1__T_149_addr] <= data_mem_0_1__T_149_data; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
data_mem_0_1[data_mem_0_1__T_149_addr] <= data_mem_0_1__T_149_data; // @[el2_ifu_ic_mem.scala 230:29]
|
||||
end
|
||||
if(data_mem_0_1__T_156_en & data_mem_0_1__T_156_mask) begin
|
||||
data_mem_0_1[data_mem_0_1__T_156_addr] <= data_mem_0_1__T_156_data; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
data_mem_0_1[data_mem_0_1__T_156_addr] <= data_mem_0_1__T_156_data; // @[el2_ifu_ic_mem.scala 230:29]
|
||||
end
|
||||
data_mem_0_1__T_137_addr_pipe_0 <= ic_rw_addr_bank_q_0[12:4];
|
||||
data_mem_0_1__T_144_addr_pipe_0 <= ic_rw_addr_bank_q_1[12:4];
|
||||
data_mem_0_1__T_151_addr_pipe_0 <= ic_rw_addr_bank_q_0[12:4];
|
||||
data_mem_0_1__T_158_addr_pipe_0 <= ic_rw_addr_bank_q_1[12:4];
|
||||
if(data_mem_1_0__T_130_en & data_mem_1_0__T_130_mask) begin
|
||||
data_mem_1_0[data_mem_1_0__T_130_addr] <= data_mem_1_0__T_130_data; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
data_mem_1_0[data_mem_1_0__T_130_addr] <= data_mem_1_0__T_130_data; // @[el2_ifu_ic_mem.scala 230:29]
|
||||
end
|
||||
if(data_mem_1_0__T_135_en & data_mem_1_0__T_135_mask) begin
|
||||
data_mem_1_0[data_mem_1_0__T_135_addr] <= data_mem_1_0__T_135_data; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
data_mem_1_0[data_mem_1_0__T_135_addr] <= data_mem_1_0__T_135_data; // @[el2_ifu_ic_mem.scala 230:29]
|
||||
end
|
||||
if(data_mem_1_0__T_142_en & data_mem_1_0__T_142_mask) begin
|
||||
data_mem_1_0[data_mem_1_0__T_142_addr] <= data_mem_1_0__T_142_data; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
data_mem_1_0[data_mem_1_0__T_142_addr] <= data_mem_1_0__T_142_data; // @[el2_ifu_ic_mem.scala 230:29]
|
||||
end
|
||||
if(data_mem_1_0__T_149_en & data_mem_1_0__T_149_mask) begin
|
||||
data_mem_1_0[data_mem_1_0__T_149_addr] <= data_mem_1_0__T_149_data; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
data_mem_1_0[data_mem_1_0__T_149_addr] <= data_mem_1_0__T_149_data; // @[el2_ifu_ic_mem.scala 230:29]
|
||||
end
|
||||
if(data_mem_1_0__T_156_en & data_mem_1_0__T_156_mask) begin
|
||||
data_mem_1_0[data_mem_1_0__T_156_addr] <= data_mem_1_0__T_156_data; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
data_mem_1_0[data_mem_1_0__T_156_addr] <= data_mem_1_0__T_156_data; // @[el2_ifu_ic_mem.scala 230:29]
|
||||
end
|
||||
data_mem_1_0__T_137_addr_pipe_0 <= ic_rw_addr_bank_q_0[12:4];
|
||||
data_mem_1_0__T_144_addr_pipe_0 <= ic_rw_addr_bank_q_1[12:4];
|
||||
data_mem_1_0__T_151_addr_pipe_0 <= ic_rw_addr_bank_q_0[12:4];
|
||||
data_mem_1_0__T_158_addr_pipe_0 <= ic_rw_addr_bank_q_1[12:4];
|
||||
if(data_mem_1_1__T_130_en & data_mem_1_1__T_130_mask) begin
|
||||
data_mem_1_1[data_mem_1_1__T_130_addr] <= data_mem_1_1__T_130_data; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
data_mem_1_1[data_mem_1_1__T_130_addr] <= data_mem_1_1__T_130_data; // @[el2_ifu_ic_mem.scala 230:29]
|
||||
end
|
||||
if(data_mem_1_1__T_135_en & data_mem_1_1__T_135_mask) begin
|
||||
data_mem_1_1[data_mem_1_1__T_135_addr] <= data_mem_1_1__T_135_data; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
data_mem_1_1[data_mem_1_1__T_135_addr] <= data_mem_1_1__T_135_data; // @[el2_ifu_ic_mem.scala 230:29]
|
||||
end
|
||||
if(data_mem_1_1__T_142_en & data_mem_1_1__T_142_mask) begin
|
||||
data_mem_1_1[data_mem_1_1__T_142_addr] <= data_mem_1_1__T_142_data; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
data_mem_1_1[data_mem_1_1__T_142_addr] <= data_mem_1_1__T_142_data; // @[el2_ifu_ic_mem.scala 230:29]
|
||||
end
|
||||
if(data_mem_1_1__T_149_en & data_mem_1_1__T_149_mask) begin
|
||||
data_mem_1_1[data_mem_1_1__T_149_addr] <= data_mem_1_1__T_149_data; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
data_mem_1_1[data_mem_1_1__T_149_addr] <= data_mem_1_1__T_149_data; // @[el2_ifu_ic_mem.scala 230:29]
|
||||
end
|
||||
if(data_mem_1_1__T_156_en & data_mem_1_1__T_156_mask) begin
|
||||
data_mem_1_1[data_mem_1_1__T_156_addr] <= data_mem_1_1__T_156_data; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
data_mem_1_1[data_mem_1_1__T_156_addr] <= data_mem_1_1__T_156_data; // @[el2_ifu_ic_mem.scala 230:29]
|
||||
end
|
||||
data_mem_1_1__T_137_addr_pipe_0 <= ic_rw_addr_bank_q_0[12:4];
|
||||
data_mem_1_1__T_144_addr_pipe_0 <= ic_rw_addr_bank_q_1[12:4];
|
||||
|
|
|
|||
|
|
@ -1,108 +1,7 @@
|
|||
[
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu_compress_ctl|el2_ifu_compress_ctl>io_l2",
|
||||
"sources":[
|
||||
"~el2_ifu_compress_ctl|el2_ifu_compress_ctl>io_l2_31",
|
||||
"~el2_ifu_compress_ctl|el2_ifu_compress_ctl>io_din"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu_compress_ctl|el2_ifu_compress_ctl>io_sjald",
|
||||
"sources":[
|
||||
"~el2_ifu_compress_ctl|el2_ifu_compress_ctl>io_din"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu_compress_ctl|el2_ifu_compress_ctl>io_dout",
|
||||
"sources":[
|
||||
"~el2_ifu_compress_ctl|el2_ifu_compress_ctl>io_l2_31",
|
||||
"~el2_ifu_compress_ctl|el2_ifu_compress_ctl>io_din"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu_compress_ctl|el2_ifu_compress_ctl>io_uimm9d",
|
||||
"sources":[
|
||||
"~el2_ifu_compress_ctl|el2_ifu_compress_ctl>io_din"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu_compress_ctl|el2_ifu_compress_ctl>io_sluimmd",
|
||||
"sources":[
|
||||
"~el2_ifu_compress_ctl|el2_ifu_compress_ctl>io_din"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu_compress_ctl|el2_ifu_compress_ctl>io_l1",
|
||||
"sources":[
|
||||
"~el2_ifu_compress_ctl|el2_ifu_compress_ctl>io_din"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu_compress_ctl|el2_ifu_compress_ctl>io_ulwspimm7d",
|
||||
"sources":[
|
||||
"~el2_ifu_compress_ctl|el2_ifu_compress_ctl>io_din"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu_compress_ctl|el2_ifu_compress_ctl>io_l2_31",
|
||||
"sources":[
|
||||
"~el2_ifu_compress_ctl|el2_ifu_compress_ctl>io_din"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu_compress_ctl|el2_ifu_compress_ctl>io_simm9d",
|
||||
"sources":[
|
||||
"~el2_ifu_compress_ctl|el2_ifu_compress_ctl>io_din"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu_compress_ctl|el2_ifu_compress_ctl>io_l3",
|
||||
"sources":[
|
||||
"~el2_ifu_compress_ctl|el2_ifu_compress_ctl>io_l2_31",
|
||||
"~el2_ifu_compress_ctl|el2_ifu_compress_ctl>io_din"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu_compress_ctl|el2_ifu_compress_ctl>io_uimm5d",
|
||||
"sources":[
|
||||
"~el2_ifu_compress_ctl|el2_ifu_compress_ctl>io_din"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu_compress_ctl|el2_ifu_compress_ctl>io_simm5d",
|
||||
"sources":[
|
||||
"~el2_ifu_compress_ctl|el2_ifu_compress_ctl>io_din"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu_compress_ctl|el2_ifu_compress_ctl>io_ulwimm6d",
|
||||
"sources":[
|
||||
"~el2_ifu_compress_ctl|el2_ifu_compress_ctl>io_din"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu_compress_ctl|el2_ifu_compress_ctl>io_o",
|
||||
"sources":[
|
||||
"~el2_ifu_compress_ctl|el2_ifu_compress_ctl>io_din"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu_compress_ctl|el2_ifu_compress_ctl>io_legal",
|
||||
"sources":[
|
||||
"~el2_ifu_compress_ctl|el2_ifu_compress_ctl>io_din"
|
||||
]
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -2,553 +2,144 @@ module el2_ifu_compress_ctl(
|
|||
input clock,
|
||||
input reset,
|
||||
input [15:0] io_din,
|
||||
output [31:0] io_dout,
|
||||
output [31:0] io_l1,
|
||||
output [31:0] io_l2,
|
||||
output [31:0] io_l3,
|
||||
output io_legal,
|
||||
output [31:0] io_o,
|
||||
output [19:0] io_sluimmd,
|
||||
output [5:0] io_uimm5d,
|
||||
output [5:0] io_ulwspimm7d,
|
||||
output [4:0] io_ulwimm6d,
|
||||
output [5:0] io_simm9d,
|
||||
output [7:0] io_uimm9d,
|
||||
output [5:0] io_simm5d,
|
||||
output [19:0] io_sjald,
|
||||
output [11:0] io_l2_31
|
||||
output [31:0] io_dout
|
||||
);
|
||||
wire _T_2 = ~io_din[14]; // @[el2_ifu_compress_ctl.scala 29:83]
|
||||
wire _T_4 = ~io_din[13]; // @[el2_ifu_compress_ctl.scala 29:83]
|
||||
wire _T_7 = ~io_din[6]; // @[el2_ifu_compress_ctl.scala 29:83]
|
||||
wire _T_9 = ~io_din[5]; // @[el2_ifu_compress_ctl.scala 29:83]
|
||||
wire _T_11 = io_din[15] & _T_2; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_12 = _T_11 & _T_4; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_13 = _T_12 & io_din[10]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_14 = _T_13 & _T_7; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_15 = _T_14 & _T_9; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_16 = _T_15 & io_din[0]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_23 = ~io_din[11]; // @[el2_ifu_compress_ctl.scala 29:83]
|
||||
wire _T_28 = _T_12 & _T_23; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_29 = _T_28 & io_din[10]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_30 = _T_29 & io_din[0]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire out_30 = _T_16 | _T_30; // @[el2_ifu_compress_ctl.scala 32:53]
|
||||
wire _T_38 = ~io_din[10]; // @[el2_ifu_compress_ctl.scala 29:83]
|
||||
wire _T_40 = ~io_din[9]; // @[el2_ifu_compress_ctl.scala 29:83]
|
||||
wire _T_42 = ~io_din[8]; // @[el2_ifu_compress_ctl.scala 29:83]
|
||||
wire _T_44 = ~io_din[7]; // @[el2_ifu_compress_ctl.scala 29:83]
|
||||
wire _T_50 = ~io_din[4]; // @[el2_ifu_compress_ctl.scala 29:83]
|
||||
wire _T_52 = ~io_din[3]; // @[el2_ifu_compress_ctl.scala 29:83]
|
||||
wire _T_54 = ~io_din[2]; // @[el2_ifu_compress_ctl.scala 29:83]
|
||||
wire _T_56 = _T_2 & io_din[12]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_57 = _T_56 & _T_23; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_58 = _T_57 & _T_38; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_59 = _T_58 & _T_40; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_60 = _T_59 & _T_42; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_61 = _T_60 & _T_44; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_62 = _T_61 & _T_7; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_63 = _T_62 & _T_9; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_64 = _T_63 & _T_50; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_65 = _T_64 & _T_52; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_66 = _T_65 & _T_54; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire out_20 = _T_66 & io_din[1]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_79 = _T_28 & io_din[0]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_90 = _T_12 & _T_38; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_91 = _T_90 & io_din[0]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_92 = _T_79 | _T_91; // @[el2_ifu_compress_ctl.scala 34:46]
|
||||
wire _T_102 = _T_12 & io_din[6]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_103 = _T_102 & io_din[0]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_104 = _T_92 | _T_103; // @[el2_ifu_compress_ctl.scala 34:80]
|
||||
wire _T_114 = _T_12 & io_din[5]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_115 = _T_114 & io_din[0]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire out_14 = _T_104 | _T_115; // @[el2_ifu_compress_ctl.scala 34:113]
|
||||
wire _T_128 = _T_12 & io_din[11]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_129 = _T_128 & _T_38; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_130 = _T_129 & io_din[0]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_142 = _T_128 & io_din[6]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_143 = _T_142 & io_din[0]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_144 = _T_130 | _T_143; // @[el2_ifu_compress_ctl.scala 36:50]
|
||||
wire _T_147 = ~io_din[0]; // @[el2_ifu_compress_ctl.scala 36:101]
|
||||
wire _T_148 = io_din[14] & _T_147; // @[el2_ifu_compress_ctl.scala 36:99]
|
||||
wire out_13 = _T_144 | _T_148; // @[el2_ifu_compress_ctl.scala 36:86]
|
||||
wire _T_161 = _T_102 & io_din[5]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_162 = _T_161 & io_din[0]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_175 = _T_162 | _T_79; // @[el2_ifu_compress_ctl.scala 37:47]
|
||||
wire _T_188 = _T_175 | _T_91; // @[el2_ifu_compress_ctl.scala 37:81]
|
||||
wire _T_190 = ~io_din[15]; // @[el2_ifu_compress_ctl.scala 29:83]
|
||||
wire _T_194 = _T_190 & _T_2; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_195 = _T_194 & io_din[1]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_196 = _T_188 | _T_195; // @[el2_ifu_compress_ctl.scala 37:115]
|
||||
wire _T_200 = io_din[15] & io_din[14]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_201 = _T_200 & io_din[13]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire out_12 = _T_196 | _T_201; // @[el2_ifu_compress_ctl.scala 38:26]
|
||||
wire _T_217 = _T_11 & _T_7; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_218 = _T_217 & _T_9; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_219 = _T_218 & _T_50; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_220 = _T_219 & _T_52; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_221 = _T_220 & _T_54; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_224 = _T_221 & _T_147; // @[el2_ifu_compress_ctl.scala 39:53]
|
||||
wire _T_228 = _T_2 & io_din[13]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_229 = _T_224 | _T_228; // @[el2_ifu_compress_ctl.scala 39:67]
|
||||
wire _T_234 = _T_200 & io_din[0]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire out_6 = _T_229 | _T_234; // @[el2_ifu_compress_ctl.scala 39:88]
|
||||
wire _T_239 = io_din[15] & _T_147; // @[el2_ifu_compress_ctl.scala 41:24]
|
||||
wire _T_243 = io_din[15] & io_din[11]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_244 = _T_243 & io_din[10]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_245 = _T_239 | _T_244; // @[el2_ifu_compress_ctl.scala 41:39]
|
||||
wire _T_249 = io_din[13] & _T_42; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_250 = _T_245 | _T_249; // @[el2_ifu_compress_ctl.scala 41:63]
|
||||
wire _T_253 = io_din[13] & io_din[7]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_254 = _T_250 | _T_253; // @[el2_ifu_compress_ctl.scala 41:83]
|
||||
wire _T_257 = io_din[13] & io_din[9]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_258 = _T_254 | _T_257; // @[el2_ifu_compress_ctl.scala 41:102]
|
||||
wire _T_261 = io_din[13] & io_din[10]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_262 = _T_258 | _T_261; // @[el2_ifu_compress_ctl.scala 42:22]
|
||||
wire _T_265 = io_din[13] & io_din[11]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_266 = _T_262 | _T_265; // @[el2_ifu_compress_ctl.scala 42:42]
|
||||
wire _T_271 = _T_266 | _T_228; // @[el2_ifu_compress_ctl.scala 42:62]
|
||||
wire out_5 = _T_271 | _T_200; // @[el2_ifu_compress_ctl.scala 42:83]
|
||||
wire _T_288 = _T_2 & _T_23; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_289 = _T_288 & _T_38; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_290 = _T_289 & _T_40; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_291 = _T_290 & _T_42; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_292 = _T_291 & _T_44; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_295 = _T_292 & _T_147; // @[el2_ifu_compress_ctl.scala 45:50]
|
||||
wire _T_303 = _T_194 & _T_147; // @[el2_ifu_compress_ctl.scala 45:87]
|
||||
wire _T_304 = _T_295 | _T_303; // @[el2_ifu_compress_ctl.scala 45:65]
|
||||
wire _T_308 = _T_2 & io_din[6]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_311 = _T_308 & _T_147; // @[el2_ifu_compress_ctl.scala 46:23]
|
||||
wire _T_312 = _T_304 | _T_311; // @[el2_ifu_compress_ctl.scala 45:102]
|
||||
wire _T_317 = _T_190 & io_din[14]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_318 = _T_317 & io_din[0]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_319 = _T_312 | _T_318; // @[el2_ifu_compress_ctl.scala 46:38]
|
||||
wire _T_323 = _T_2 & io_din[5]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_326 = _T_323 & _T_147; // @[el2_ifu_compress_ctl.scala 46:82]
|
||||
wire _T_327 = _T_319 | _T_326; // @[el2_ifu_compress_ctl.scala 46:62]
|
||||
wire _T_331 = _T_2 & io_din[4]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_334 = _T_331 & _T_147; // @[el2_ifu_compress_ctl.scala 47:23]
|
||||
wire _T_335 = _T_327 | _T_334; // @[el2_ifu_compress_ctl.scala 46:97]
|
||||
wire _T_339 = _T_2 & io_din[3]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_342 = _T_339 & _T_147; // @[el2_ifu_compress_ctl.scala 47:58]
|
||||
wire _T_343 = _T_335 | _T_342; // @[el2_ifu_compress_ctl.scala 47:38]
|
||||
wire _T_347 = _T_2 & io_din[2]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_350 = _T_347 & _T_147; // @[el2_ifu_compress_ctl.scala 47:93]
|
||||
wire _T_351 = _T_343 | _T_350; // @[el2_ifu_compress_ctl.scala 47:73]
|
||||
wire _T_357 = _T_2 & _T_4; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_358 = _T_357 & io_din[0]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire out_4 = _T_351 | _T_358; // @[el2_ifu_compress_ctl.scala 47:108]
|
||||
wire _T_380 = _T_56 & io_din[11]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_381 = _T_380 & _T_7; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_382 = _T_381 & _T_9; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_383 = _T_382 & _T_50; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_384 = _T_383 & _T_52; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_385 = _T_384 & _T_54; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_386 = _T_385 & io_din[1]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_403 = _T_56 & io_din[10]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_404 = _T_403 & _T_7; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_405 = _T_404 & _T_9; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_406 = _T_405 & _T_50; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_407 = _T_406 & _T_52; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_408 = _T_407 & _T_54; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_409 = _T_408 & io_din[1]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_410 = _T_386 | _T_409; // @[el2_ifu_compress_ctl.scala 54:59]
|
||||
wire _T_427 = _T_56 & io_din[9]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_428 = _T_427 & _T_7; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_429 = _T_428 & _T_9; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_430 = _T_429 & _T_50; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_431 = _T_430 & _T_52; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_432 = _T_431 & _T_54; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_433 = _T_432 & io_din[1]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_434 = _T_410 | _T_433; // @[el2_ifu_compress_ctl.scala 55:59]
|
||||
wire _T_451 = _T_56 & io_din[8]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_452 = _T_451 & _T_7; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_453 = _T_452 & _T_9; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_454 = _T_453 & _T_50; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_455 = _T_454 & _T_52; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_456 = _T_455 & _T_54; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_457 = _T_456 & io_din[1]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_458 = _T_434 | _T_457; // @[el2_ifu_compress_ctl.scala 56:58]
|
||||
wire _T_475 = _T_56 & io_din[7]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_476 = _T_475 & _T_7; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_477 = _T_476 & _T_9; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_478 = _T_477 & _T_50; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_479 = _T_478 & _T_52; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_480 = _T_479 & _T_54; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_481 = _T_480 & io_din[1]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_482 = _T_458 | _T_481; // @[el2_ifu_compress_ctl.scala 57:55]
|
||||
wire _T_487 = ~io_din[12]; // @[el2_ifu_compress_ctl.scala 29:83]
|
||||
wire _T_499 = _T_11 & _T_487; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_500 = _T_499 & _T_7; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_501 = _T_500 & _T_9; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_502 = _T_501 & _T_50; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_503 = _T_502 & _T_52; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_504 = _T_503 & _T_54; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_507 = _T_504 & _T_147; // @[el2_ifu_compress_ctl.scala 59:56]
|
||||
wire _T_508 = _T_482 | _T_507; // @[el2_ifu_compress_ctl.scala 58:57]
|
||||
wire _T_514 = _T_190 & io_din[13]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_515 = _T_514 & _T_42; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_516 = _T_508 | _T_515; // @[el2_ifu_compress_ctl.scala 59:71]
|
||||
wire _T_522 = _T_514 & io_din[7]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_523 = _T_516 | _T_522; // @[el2_ifu_compress_ctl.scala 60:34]
|
||||
wire _T_529 = _T_514 & io_din[9]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_530 = _T_523 | _T_529; // @[el2_ifu_compress_ctl.scala 61:33]
|
||||
wire _T_536 = _T_514 & io_din[10]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_537 = _T_530 | _T_536; // @[el2_ifu_compress_ctl.scala 62:33]
|
||||
wire _T_543 = _T_514 & io_din[11]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_544 = _T_537 | _T_543; // @[el2_ifu_compress_ctl.scala 63:34]
|
||||
wire out_2 = _T_544 | _T_228; // @[el2_ifu_compress_ctl.scala 64:34]
|
||||
wire [4:0] rs2d = io_din[6:2]; // @[el2_ifu_compress_ctl.scala 73:20]
|
||||
wire [4:0] rdd = io_din[11:7]; // @[el2_ifu_compress_ctl.scala 74:19]
|
||||
wire [4:0] rdpd = {2'h1,io_din[9:7]}; // @[Cat.scala 29:58]
|
||||
wire [4:0] rs2pd = {2'h1,io_din[4:2]}; // @[Cat.scala 29:58]
|
||||
wire _T_557 = _T_308 & io_din[1]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_564 = _T_317 & io_din[11]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_565 = _T_564 & io_din[0]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_566 = _T_557 | _T_565; // @[el2_ifu_compress_ctl.scala 78:33]
|
||||
wire _T_572 = _T_323 & io_din[1]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_573 = _T_566 | _T_572; // @[el2_ifu_compress_ctl.scala 78:58]
|
||||
wire _T_580 = _T_317 & io_din[10]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_581 = _T_580 & io_din[0]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_582 = _T_573 | _T_581; // @[el2_ifu_compress_ctl.scala 78:79]
|
||||
wire _T_588 = _T_331 & io_din[1]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_589 = _T_582 | _T_588; // @[el2_ifu_compress_ctl.scala 78:104]
|
||||
wire _T_596 = _T_317 & io_din[9]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_597 = _T_596 & io_din[0]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_598 = _T_589 | _T_597; // @[el2_ifu_compress_ctl.scala 79:24]
|
||||
wire _T_604 = _T_339 & io_din[1]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_605 = _T_598 | _T_604; // @[el2_ifu_compress_ctl.scala 79:48]
|
||||
wire _T_613 = _T_317 & _T_42; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_614 = _T_613 & io_din[0]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_615 = _T_605 | _T_614; // @[el2_ifu_compress_ctl.scala 79:69]
|
||||
wire _T_621 = _T_347 & io_din[1]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_622 = _T_615 | _T_621; // @[el2_ifu_compress_ctl.scala 79:94]
|
||||
wire _T_629 = _T_317 & io_din[7]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_630 = _T_629 & io_din[0]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_631 = _T_622 | _T_630; // @[el2_ifu_compress_ctl.scala 80:22]
|
||||
wire _T_635 = _T_190 & io_din[1]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_636 = _T_631 | _T_635; // @[el2_ifu_compress_ctl.scala 80:46]
|
||||
wire _T_642 = _T_190 & _T_4; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_643 = _T_642 & io_din[0]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire rdrd = _T_636 | _T_643; // @[el2_ifu_compress_ctl.scala 80:65]
|
||||
wire _T_651 = _T_380 & io_din[1]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_659 = _T_403 & io_din[1]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_660 = _T_651 | _T_659; // @[el2_ifu_compress_ctl.scala 82:38]
|
||||
wire _T_668 = _T_427 & io_din[1]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_669 = _T_660 | _T_668; // @[el2_ifu_compress_ctl.scala 83:28]
|
||||
wire _T_677 = _T_451 & io_din[1]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_678 = _T_669 | _T_677; // @[el2_ifu_compress_ctl.scala 84:27]
|
||||
wire _T_686 = _T_475 & io_din[1]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_687 = _T_678 | _T_686; // @[el2_ifu_compress_ctl.scala 85:27]
|
||||
wire _T_703 = _T_2 & _T_487; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_704 = _T_703 & _T_7; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_705 = _T_704 & _T_9; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_706 = _T_705 & _T_50; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_707 = _T_706 & _T_52; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_708 = _T_707 & _T_54; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_709 = _T_708 & io_din[1]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_710 = _T_687 | _T_709; // @[el2_ifu_compress_ctl.scala 86:27]
|
||||
wire _T_717 = _T_56 & io_din[6]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_718 = _T_717 & io_din[1]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_719 = _T_710 | _T_718; // @[el2_ifu_compress_ctl.scala 87:41]
|
||||
wire _T_726 = _T_56 & io_din[5]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_727 = _T_726 & io_din[1]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_728 = _T_719 | _T_727; // @[el2_ifu_compress_ctl.scala 88:27]
|
||||
wire _T_735 = _T_56 & io_din[4]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_736 = _T_735 & io_din[1]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_737 = _T_728 | _T_736; // @[el2_ifu_compress_ctl.scala 89:27]
|
||||
wire _T_744 = _T_56 & io_din[3]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_745 = _T_744 & io_din[1]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_746 = _T_737 | _T_745; // @[el2_ifu_compress_ctl.scala 90:27]
|
||||
wire _T_753 = _T_56 & io_din[2]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_754 = _T_753 & io_din[1]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_755 = _T_746 | _T_754; // @[el2_ifu_compress_ctl.scala 91:27]
|
||||
wire _T_764 = _T_194 & _T_4; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_765 = _T_764 & io_din[0]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_766 = _T_755 | _T_765; // @[el2_ifu_compress_ctl.scala 92:27]
|
||||
wire rdrs1 = _T_766 | _T_195; // @[el2_ifu_compress_ctl.scala 93:30]
|
||||
wire _T_777 = io_din[15] & io_din[6]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_778 = _T_777 & io_din[1]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_782 = io_din[15] & io_din[5]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_783 = _T_782 & io_din[1]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_784 = _T_778 | _T_783; // @[el2_ifu_compress_ctl.scala 96:34]
|
||||
wire _T_788 = io_din[15] & io_din[4]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_789 = _T_788 & io_din[1]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_790 = _T_784 | _T_789; // @[el2_ifu_compress_ctl.scala 96:54]
|
||||
wire _T_794 = io_din[15] & io_din[3]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_795 = _T_794 & io_din[1]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_796 = _T_790 | _T_795; // @[el2_ifu_compress_ctl.scala 96:74]
|
||||
wire _T_800 = io_din[15] & io_din[2]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_801 = _T_800 & io_din[1]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_802 = _T_796 | _T_801; // @[el2_ifu_compress_ctl.scala 96:94]
|
||||
wire _T_807 = _T_200 & io_din[1]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire rs2rs2 = _T_802 | _T_807; // @[el2_ifu_compress_ctl.scala 96:114]
|
||||
wire rdprd = _T_12 & io_din[0]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_820 = io_din[15] & _T_4; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_821 = _T_820 & io_din[0]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_827 = _T_821 | _T_234; // @[el2_ifu_compress_ctl.scala 100:36]
|
||||
wire _T_830 = ~io_din[1]; // @[el2_ifu_compress_ctl.scala 29:83]
|
||||
wire _T_831 = io_din[14] & _T_830; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_834 = _T_831 & _T_147; // @[el2_ifu_compress_ctl.scala 100:76]
|
||||
wire rdprs1 = _T_827 | _T_834; // @[el2_ifu_compress_ctl.scala 100:57]
|
||||
wire _T_846 = _T_128 & io_din[10]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_847 = _T_846 & io_din[0]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_851 = io_din[15] & _T_830; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_854 = _T_851 & _T_147; // @[el2_ifu_compress_ctl.scala 102:66]
|
||||
wire rs2prs2 = _T_847 | _T_854; // @[el2_ifu_compress_ctl.scala 102:47]
|
||||
wire _T_859 = _T_190 & _T_830; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire rs2prd = _T_859 & _T_147; // @[el2_ifu_compress_ctl.scala 103:33]
|
||||
wire _T_866 = _T_2 & _T_830; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire uimm9_2 = _T_866 & _T_147; // @[el2_ifu_compress_ctl.scala 104:34]
|
||||
wire _T_875 = _T_317 & _T_830; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire ulwimm6_2 = _T_875 & _T_147; // @[el2_ifu_compress_ctl.scala 105:39]
|
||||
wire ulwspimm7_2 = _T_317 & io_din[1]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_897 = _T_317 & io_din[13]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_898 = _T_897 & _T_23; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_899 = _T_898 & _T_38; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_900 = _T_899 & _T_40; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_901 = _T_900 & io_din[8]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire rdeq2 = _T_901 & _T_44; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_1027 = _T_194 & io_din[13]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire rdeq1 = _T_482 | _T_1027; // @[el2_ifu_compress_ctl.scala 110:42]
|
||||
wire _T_1050 = io_din[14] & io_din[1]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_1051 = rdeq2 | _T_1050; // @[el2_ifu_compress_ctl.scala 111:53]
|
||||
wire rs1eq2 = _T_1051 | uimm9_2; // @[el2_ifu_compress_ctl.scala 111:71]
|
||||
wire _T_1092 = _T_357 & io_din[11]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_1093 = _T_1092 & _T_38; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_1094 = _T_1093 & io_din[0]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire simm5_0 = _T_1094 | _T_643; // @[el2_ifu_compress_ctl.scala 114:45]
|
||||
wire _T_1112 = _T_897 & io_din[7]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_1121 = _T_897 & _T_42; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_1122 = _T_1112 | _T_1121; // @[el2_ifu_compress_ctl.scala 116:44]
|
||||
wire _T_1130 = _T_897 & io_din[9]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_1131 = _T_1122 | _T_1130; // @[el2_ifu_compress_ctl.scala 117:29]
|
||||
wire _T_1139 = _T_897 & io_din[10]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_1140 = _T_1131 | _T_1139; // @[el2_ifu_compress_ctl.scala 118:28]
|
||||
wire _T_1148 = _T_897 & io_din[11]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire sluimm17_12 = _T_1140 | _T_1148; // @[el2_ifu_compress_ctl.scala 119:29]
|
||||
wire uimm5_0 = _T_79 | _T_195; // @[el2_ifu_compress_ctl.scala 121:45]
|
||||
wire [6:0] l1_6 = {out_6,out_5,out_4,_T_228,out_2,1'h1,1'h1}; // @[Cat.scala 29:58]
|
||||
wire [4:0] _T_1192 = rdrd ? rdd : 5'h0; // @[Mux.scala 27:72]
|
||||
wire [4:0] _T_1193 = rdprd ? rdpd : 5'h0; // @[Mux.scala 27:72]
|
||||
wire [4:0] _T_1194 = rs2prd ? rs2pd : 5'h0; // @[Mux.scala 27:72]
|
||||
wire [4:0] _T_1195 = rdeq1 ? 5'h1 : 5'h0; // @[Mux.scala 27:72]
|
||||
wire [4:0] _T_1196 = rdeq2 ? 5'h2 : 5'h0; // @[Mux.scala 27:72]
|
||||
wire [4:0] _T_1197 = _T_1192 | _T_1193; // @[Mux.scala 27:72]
|
||||
wire [4:0] _T_1198 = _T_1197 | _T_1194; // @[Mux.scala 27:72]
|
||||
wire [4:0] _T_1199 = _T_1198 | _T_1195; // @[Mux.scala 27:72]
|
||||
wire [4:0] l1_11 = _T_1199 | _T_1196; // @[Mux.scala 27:72]
|
||||
wire [4:0] _T_1210 = rdrs1 ? rdd : 5'h0; // @[Mux.scala 27:72]
|
||||
wire [4:0] _T_1211 = rdprs1 ? rdpd : 5'h0; // @[Mux.scala 27:72]
|
||||
wire [4:0] _T_1212 = rs1eq2 ? 5'h2 : 5'h0; // @[Mux.scala 27:72]
|
||||
wire [4:0] _T_1213 = _T_1210 | _T_1211; // @[Mux.scala 27:72]
|
||||
wire [4:0] l1_19 = _T_1213 | _T_1212; // @[Mux.scala 27:72]
|
||||
wire [4:0] _T_1219 = {3'h0,1'h0,out_20}; // @[Cat.scala 29:58]
|
||||
wire [4:0] _T_1222 = rs2rs2 ? rs2d : 5'h0; // @[Mux.scala 27:72]
|
||||
wire [4:0] _T_1223 = rs2prs2 ? rs2pd : 5'h0; // @[Mux.scala 27:72]
|
||||
wire [4:0] _T_1224 = _T_1222 | _T_1223; // @[Mux.scala 27:72]
|
||||
wire [4:0] l1_24 = _T_1219 | _T_1224; // @[el2_ifu_compress_ctl.scala 134:67]
|
||||
wire [14:0] _T_1232 = {out_14,out_13,out_12,l1_11,l1_6}; // @[Cat.scala 29:58]
|
||||
wire [16:0] _T_1234 = {1'h0,out_30,2'h0,3'h0,l1_24,l1_19}; // @[Cat.scala 29:58]
|
||||
wire [31:0] l1 = {1'h0,out_30,2'h0,3'h0,l1_24,l1_19,_T_1232}; // @[Cat.scala 29:58]
|
||||
wire [5:0] simm5d = {io_din[12],rs2d}; // @[Cat.scala 29:58]
|
||||
wire [1:0] _T_1241 = {io_din[5],io_din[6]}; // @[Cat.scala 29:58]
|
||||
wire [5:0] _T_1242 = {io_din[10:7],io_din[12:11]}; // @[Cat.scala 29:58]
|
||||
wire [1:0] _T_1248 = {io_din[2],io_din[6]}; // @[Cat.scala 29:58]
|
||||
wire [3:0] _T_1250 = {io_din[12],io_din[4:3],io_din[5]}; // @[Cat.scala 29:58]
|
||||
wire [5:0] simm9d = {io_din[12],io_din[4:3],io_din[5],io_din[2],io_din[6]}; // @[Cat.scala 29:58]
|
||||
wire [3:0] _T_1254 = {io_din[5],io_din[12:10]}; // @[Cat.scala 29:58]
|
||||
wire [2:0] _T_1258 = {io_din[3:2],io_din[12]}; // @[Cat.scala 29:58]
|
||||
wire [10:0] sjald_1 = {io_din[12],io_din[8],io_din[10:9],io_din[6],io_din[7],io_din[2],io_din[11],io_din[5:4],io_din[3]}; // @[Cat.scala 29:58]
|
||||
wire [8:0] sjald_12 = io_din[12] ? 9'h1ff : 9'h0; // @[Bitwise.scala 72:12]
|
||||
wire [19:0] sjald = {sjald_12,io_din[12],io_din[8],io_din[10:9],io_din[6],io_din[7],io_din[2],io_din[11],io_din[5:4],io_din[3]}; // @[Cat.scala 29:58]
|
||||
wire [14:0] _T_1281 = io_din[12] ? 15'h7fff : 15'h0; // @[Bitwise.scala 72:12]
|
||||
wire [19:0] sluimmd = {_T_1281,rs2d}; // @[Cat.scala 29:58]
|
||||
wire [6:0] _T_1287 = simm5d[5] ? 7'h7f : 7'h0; // @[Bitwise.scala 72:12]
|
||||
wire [11:0] _T_1289 = {_T_1287,simm5d[4:0]}; // @[Cat.scala 29:58]
|
||||
wire [11:0] _T_1292 = {2'h0,io_din[10:7],io_din[12:11],io_din[5],io_din[6],2'h0}; // @[Cat.scala 29:58]
|
||||
wire [2:0] _T_1296 = simm9d[5] ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
|
||||
wire [11:0] _T_1299 = {_T_1296,simm9d[4:0],4'h0}; // @[Cat.scala 29:58]
|
||||
wire [11:0] _T_1302 = {5'h0,io_din[5],io_din[12:10],io_din[6],2'h0}; // @[Cat.scala 29:58]
|
||||
wire [11:0] _T_1305 = {4'h0,io_din[3:2],io_din[12],io_din[6:4],2'h0}; // @[Cat.scala 29:58]
|
||||
wire [11:0] _T_1307 = {6'h0,io_din[12],rs2d}; // @[Cat.scala 29:58]
|
||||
wire [11:0] _T_1312 = {sjald[19],sjald[9:0],sjald[10]}; // @[Cat.scala 29:58]
|
||||
wire [11:0] _T_1314 = simm5_0 ? _T_1289 : 12'h0; // @[Mux.scala 27:72]
|
||||
wire [11:0] _T_1315 = uimm9_2 ? _T_1292 : 12'h0; // @[Mux.scala 27:72]
|
||||
wire [11:0] _T_1316 = rdeq2 ? _T_1299 : 12'h0; // @[Mux.scala 27:72]
|
||||
wire [11:0] _T_1317 = ulwimm6_2 ? _T_1302 : 12'h0; // @[Mux.scala 27:72]
|
||||
wire [11:0] _T_1318 = ulwspimm7_2 ? _T_1305 : 12'h0; // @[Mux.scala 27:72]
|
||||
wire [11:0] _T_1319 = uimm5_0 ? _T_1307 : 12'h0; // @[Mux.scala 27:72]
|
||||
wire [11:0] _T_1320 = _T_228 ? _T_1312 : 12'h0; // @[Mux.scala 27:72]
|
||||
wire [11:0] _T_1321 = sluimm17_12 ? sluimmd[19:8] : 12'h0; // @[Mux.scala 27:72]
|
||||
wire [11:0] _T_1322 = _T_1314 | _T_1315; // @[Mux.scala 27:72]
|
||||
wire [11:0] _T_1323 = _T_1322 | _T_1316; // @[Mux.scala 27:72]
|
||||
wire [11:0] _T_1324 = _T_1323 | _T_1317; // @[Mux.scala 27:72]
|
||||
wire [11:0] _T_1325 = _T_1324 | _T_1318; // @[Mux.scala 27:72]
|
||||
wire [11:0] _T_1326 = _T_1325 | _T_1319; // @[Mux.scala 27:72]
|
||||
wire [11:0] _T_1327 = _T_1326 | _T_1320; // @[Mux.scala 27:72]
|
||||
wire [11:0] _T_1328 = _T_1327 | _T_1321; // @[Mux.scala 27:72]
|
||||
wire [8:0] _T_1336 = _T_228 ? sjald[19:11] : 9'h0; // @[Mux.scala 27:72]
|
||||
wire [7:0] _T_1337 = sluimm17_12 ? sluimmd[7:0] : 8'h0; // @[Mux.scala 27:72]
|
||||
wire [8:0] _GEN_0 = {{1'd0}, _T_1337}; // @[Mux.scala 27:72]
|
||||
wire [8:0] _T_1338 = _T_1336 | _GEN_0; // @[Mux.scala 27:72]
|
||||
wire [8:0] _GEN_1 = {{1'd0}, l1[19:12]}; // @[el2_ifu_compress_ctl.scala 162:25]
|
||||
wire [8:0] l2_19 = _GEN_1 | _T_1338; // @[el2_ifu_compress_ctl.scala 162:25]
|
||||
wire [32:0] l2 = {io_l2_31,l2_19,l1[11:0]}; // @[Cat.scala 29:58]
|
||||
wire [8:0] sbr8d = {io_din[12],io_din[6],io_din[5],io_din[2],io_din[11],io_din[10],io_din[4],io_din[3],1'h0}; // @[Cat.scala 29:58]
|
||||
wire [6:0] uswimm6d = {io_din[5],io_din[12:10],io_din[6],2'h0}; // @[Cat.scala 29:58]
|
||||
wire [7:0] uswspimm7d = {io_din[8:7],io_din[12:9],2'h0}; // @[Cat.scala 29:58]
|
||||
wire [3:0] _T_1369 = sbr8d[8] ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
||||
wire [6:0] _T_1371 = {_T_1369,sbr8d[7:5]}; // @[Cat.scala 29:58]
|
||||
wire [6:0] _T_1374 = {5'h0,uswimm6d[6:5]}; // @[Cat.scala 29:58]
|
||||
wire [6:0] _T_1377 = {4'h0,uswspimm7d[7:5]}; // @[Cat.scala 29:58]
|
||||
wire [6:0] _T_1378 = _T_234 ? _T_1371 : 7'h0; // @[Mux.scala 27:72]
|
||||
wire [6:0] _T_1379 = _T_854 ? _T_1374 : 7'h0; // @[Mux.scala 27:72]
|
||||
wire [6:0] _T_1380 = _T_807 ? _T_1377 : 7'h0; // @[Mux.scala 27:72]
|
||||
wire [6:0] _T_1381 = _T_1378 | _T_1379; // @[Mux.scala 27:72]
|
||||
wire [6:0] _T_1382 = _T_1381 | _T_1380; // @[Mux.scala 27:72]
|
||||
wire [6:0] l3_31 = l2[31:25] | _T_1382; // @[el2_ifu_compress_ctl.scala 170:25]
|
||||
wire [12:0] l3_24 = l2[24:12]; // @[el2_ifu_compress_ctl.scala 173:17]
|
||||
wire [4:0] _T_1388 = {sbr8d[4:1],sbr8d[8]}; // @[Cat.scala 29:58]
|
||||
wire [4:0] _T_1393 = _T_234 ? _T_1388 : 5'h0; // @[Mux.scala 27:72]
|
||||
wire [4:0] _T_1394 = _T_854 ? uswimm6d[4:0] : 5'h0; // @[Mux.scala 27:72]
|
||||
wire [4:0] _T_1395 = _T_807 ? uswspimm7d[4:0] : 5'h0; // @[Mux.scala 27:72]
|
||||
wire [4:0] _T_1396 = _T_1393 | _T_1394; // @[Mux.scala 27:72]
|
||||
wire [4:0] _T_1397 = _T_1396 | _T_1395; // @[Mux.scala 27:72]
|
||||
wire [4:0] l3_11 = l2[11:7] | _T_1397; // @[el2_ifu_compress_ctl.scala 174:24]
|
||||
wire [11:0] _T_1400 = {l3_11,l2[6:0]}; // @[Cat.scala 29:58]
|
||||
wire [19:0] _T_1401 = {l3_31,l3_24}; // @[Cat.scala 29:58]
|
||||
wire [31:0] l3 = {l3_31,l3_24,l3_11,l2[6:0]}; // @[Cat.scala 29:58]
|
||||
wire _T_1408 = _T_4 & _T_487; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_1409 = _T_1408 & io_din[11]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_1410 = _T_1409 & io_din[1]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_1413 = _T_1410 & _T_147; // @[el2_ifu_compress_ctl.scala 179:39]
|
||||
wire _T_1421 = _T_1408 & io_din[6]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_1422 = _T_1421 & io_din[1]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_1425 = _T_1422 & _T_147; // @[el2_ifu_compress_ctl.scala 179:79]
|
||||
wire _T_1426 = _T_1413 | _T_1425; // @[el2_ifu_compress_ctl.scala 179:54]
|
||||
wire _T_1435 = _T_642 & io_din[11]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_1436 = _T_1435 & _T_830; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_1437 = _T_1426 | _T_1436; // @[el2_ifu_compress_ctl.scala 179:94]
|
||||
wire _T_1445 = _T_1408 & io_din[5]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_1446 = _T_1445 & io_din[1]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_1449 = _T_1446 & _T_147; // @[el2_ifu_compress_ctl.scala 180:55]
|
||||
wire _T_1450 = _T_1437 | _T_1449; // @[el2_ifu_compress_ctl.scala 180:30]
|
||||
wire _T_1458 = _T_1408 & io_din[10]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_1459 = _T_1458 & io_din[1]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_1462 = _T_1459 & _T_147; // @[el2_ifu_compress_ctl.scala 180:96]
|
||||
wire _T_1463 = _T_1450 | _T_1462; // @[el2_ifu_compress_ctl.scala 180:70]
|
||||
wire _T_1472 = _T_642 & io_din[6]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_1473 = _T_1472 & _T_830; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_1474 = _T_1463 | _T_1473; // @[el2_ifu_compress_ctl.scala 180:111]
|
||||
wire _T_1481 = io_din[15] & _T_487; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_1482 = _T_1481 & _T_830; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_1483 = _T_1482 & io_din[0]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_1484 = _T_1474 | _T_1483; // @[el2_ifu_compress_ctl.scala 181:29]
|
||||
wire _T_1492 = _T_1408 & io_din[9]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_1493 = _T_1492 & io_din[1]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_1496 = _T_1493 & _T_147; // @[el2_ifu_compress_ctl.scala 181:79]
|
||||
wire _T_1497 = _T_1484 | _T_1496; // @[el2_ifu_compress_ctl.scala 181:54]
|
||||
wire _T_1504 = _T_487 & io_din[6]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_1505 = _T_1504 & _T_830; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_1506 = _T_1505 & io_din[0]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_1507 = _T_1497 | _T_1506; // @[el2_ifu_compress_ctl.scala 181:94]
|
||||
wire _T_1516 = _T_642 & io_din[5]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_1517 = _T_1516 & _T_830; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_1518 = _T_1507 | _T_1517; // @[el2_ifu_compress_ctl.scala 181:118]
|
||||
wire _T_1526 = _T_1408 & io_din[8]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_1527 = _T_1526 & io_din[1]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_1530 = _T_1527 & _T_147; // @[el2_ifu_compress_ctl.scala 182:28]
|
||||
wire _T_1531 = _T_1518 | _T_1530; // @[el2_ifu_compress_ctl.scala 181:144]
|
||||
wire _T_1538 = _T_487 & io_din[5]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_1539 = _T_1538 & _T_830; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_1540 = _T_1539 & io_din[0]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_1541 = _T_1531 | _T_1540; // @[el2_ifu_compress_ctl.scala 182:43]
|
||||
wire _T_1550 = _T_642 & io_din[10]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_1551 = _T_1550 & _T_830; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_1552 = _T_1541 | _T_1551; // @[el2_ifu_compress_ctl.scala 182:67]
|
||||
wire _T_1560 = _T_1408 & io_din[7]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_1561 = _T_1560 & io_din[1]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_1564 = _T_1561 & _T_147; // @[el2_ifu_compress_ctl.scala 183:28]
|
||||
wire _T_1565 = _T_1552 | _T_1564; // @[el2_ifu_compress_ctl.scala 182:94]
|
||||
wire _T_1573 = io_din[12] & io_din[11]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_1574 = _T_1573 & _T_38; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_1575 = _T_1574 & _T_830; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_1576 = _T_1575 & io_din[0]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_1577 = _T_1565 | _T_1576; // @[el2_ifu_compress_ctl.scala 183:43]
|
||||
wire _T_1586 = _T_642 & io_din[9]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_1587 = _T_1586 & _T_830; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_1588 = _T_1577 | _T_1587; // @[el2_ifu_compress_ctl.scala 183:71]
|
||||
wire _T_1596 = _T_1408 & io_din[4]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_1597 = _T_1596 & io_din[1]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_1600 = _T_1597 & _T_147; // @[el2_ifu_compress_ctl.scala 184:28]
|
||||
wire _T_1601 = _T_1588 | _T_1600; // @[el2_ifu_compress_ctl.scala 183:97]
|
||||
wire _T_1607 = io_din[13] & io_din[12]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_1608 = _T_1607 & _T_830; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_1609 = _T_1608 & io_din[0]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_1610 = _T_1601 | _T_1609; // @[el2_ifu_compress_ctl.scala 184:43]
|
||||
wire _T_1619 = _T_642 & io_din[8]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_1620 = _T_1619 & _T_830; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_1621 = _T_1610 | _T_1620; // @[el2_ifu_compress_ctl.scala 184:67]
|
||||
wire _T_1629 = _T_1408 & io_din[3]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_1630 = _T_1629 & io_din[1]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_1633 = _T_1630 & _T_147; // @[el2_ifu_compress_ctl.scala 185:28]
|
||||
wire _T_1634 = _T_1621 | _T_1633; // @[el2_ifu_compress_ctl.scala 184:93]
|
||||
wire _T_1640 = io_din[13] & io_din[4]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_1641 = _T_1640 & _T_830; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_1642 = _T_1641 & io_din[0]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_1643 = _T_1634 | _T_1642; // @[el2_ifu_compress_ctl.scala 185:43]
|
||||
wire _T_1651 = _T_1408 & io_din[2]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_1652 = _T_1651 & io_din[1]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_1655 = _T_1652 & _T_147; // @[el2_ifu_compress_ctl.scala 185:91]
|
||||
wire _T_1656 = _T_1643 | _T_1655; // @[el2_ifu_compress_ctl.scala 185:66]
|
||||
wire _T_1665 = _T_642 & io_din[7]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_1666 = _T_1665 & _T_830; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_1667 = _T_1656 | _T_1666; // @[el2_ifu_compress_ctl.scala 185:106]
|
||||
wire _T_1673 = io_din[13] & io_din[3]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_1674 = _T_1673 & _T_830; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_1675 = _T_1674 & io_din[0]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_1676 = _T_1667 | _T_1675; // @[el2_ifu_compress_ctl.scala 186:29]
|
||||
wire _T_1682 = io_din[13] & io_din[2]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_1683 = _T_1682 & _T_830; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_1684 = _T_1683 & io_din[0]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_1685 = _T_1676 | _T_1684; // @[el2_ifu_compress_ctl.scala 186:52]
|
||||
wire _T_1691 = io_din[14] & _T_4; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_1692 = _T_1691 & _T_830; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_1693 = _T_1685 | _T_1692; // @[el2_ifu_compress_ctl.scala 186:75]
|
||||
wire _T_1702 = _T_703 & _T_830; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_1703 = _T_1702 & io_din[0]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_1704 = _T_1693 | _T_1703; // @[el2_ifu_compress_ctl.scala 186:98]
|
||||
wire _T_1711 = _T_820 & io_din[12]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_1712 = _T_1711 & io_din[1]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_1715 = _T_1712 & _T_147; // @[el2_ifu_compress_ctl.scala 187:54]
|
||||
wire _T_1716 = _T_1704 | _T_1715; // @[el2_ifu_compress_ctl.scala 187:29]
|
||||
wire _T_1725 = _T_642 & _T_487; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_1726 = _T_1725 & io_din[1]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_1729 = _T_1726 & _T_147; // @[el2_ifu_compress_ctl.scala 187:96]
|
||||
wire _T_1730 = _T_1716 | _T_1729; // @[el2_ifu_compress_ctl.scala 187:69]
|
||||
wire _T_1739 = _T_642 & io_din[12]; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_1740 = _T_1739 & _T_830; // @[el2_ifu_compress_ctl.scala 29:110]
|
||||
wire _T_1741 = _T_1730 | _T_1740; // @[el2_ifu_compress_ctl.scala 187:111]
|
||||
wire _T_1748 = _T_1691 & _T_147; // @[el2_ifu_compress_ctl.scala 188:50]
|
||||
wire legal = _T_1741 | _T_1748; // @[el2_ifu_compress_ctl.scala 188:30]
|
||||
wire [31:0] _T_1750 = legal ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
|
||||
wire [9:0] _T_1760 = {1'h0,out_30,1'h0,1'h0,1'h0,1'h0,1'h0,1'h0,1'h0,1'h0}; // @[Cat.scala 29:58]
|
||||
wire [18:0] _T_1769 = {_T_1760,1'h0,out_20,1'h0,1'h0,1'h0,1'h0,1'h0,out_14,out_13}; // @[Cat.scala 29:58]
|
||||
wire [27:0] _T_1778 = {_T_1769,out_12,1'h0,1'h0,1'h0,1'h0,1'h0,out_6,out_5,out_4}; // @[Cat.scala 29:58]
|
||||
wire [30:0] _T_1781 = {_T_1778,_T_228,out_2,1'h1}; // @[Cat.scala 29:58]
|
||||
assign io_dout = l3 & _T_1750; // @[el2_ifu_compress_ctl.scala 190:10]
|
||||
assign io_l1 = {_T_1234,_T_1232}; // @[el2_ifu_compress_ctl.scala 191:9]
|
||||
assign io_l2 = l2[31:0]; // @[el2_ifu_compress_ctl.scala 192:9]
|
||||
assign io_l3 = {_T_1401,_T_1400}; // @[el2_ifu_compress_ctl.scala 193:9]
|
||||
assign io_legal = _T_1741 | _T_1748; // @[el2_ifu_compress_ctl.scala 194:12]
|
||||
assign io_o = {_T_1781,1'h1}; // @[el2_ifu_compress_ctl.scala 195:8]
|
||||
assign io_sluimmd = {_T_1281,rs2d}; // @[el2_ifu_compress_ctl.scala 150:14]
|
||||
assign io_uimm5d = {io_din[12],rs2d}; // @[el2_ifu_compress_ctl.scala 205:13]
|
||||
assign io_ulwspimm7d = {_T_1258,io_din[6:4]}; // @[el2_ifu_compress_ctl.scala 206:17]
|
||||
assign io_ulwimm6d = {_T_1254,io_din[6]}; // @[el2_ifu_compress_ctl.scala 207:15]
|
||||
assign io_simm9d = {_T_1250,_T_1248}; // @[el2_ifu_compress_ctl.scala 208:13]
|
||||
assign io_uimm9d = {_T_1242,_T_1241}; // @[el2_ifu_compress_ctl.scala 209:13]
|
||||
assign io_simm5d = {io_din[12],rs2d}; // @[el2_ifu_compress_ctl.scala 210:13]
|
||||
assign io_sjald = {sjald_12,sjald_1}; // @[el2_ifu_compress_ctl.scala 204:12]
|
||||
assign io_l2_31 = l1[31:20] | _T_1328; // @[el2_ifu_compress_ctl.scala 152:12]
|
||||
wire _T_1 = io_din[1:0] != 2'h3; // @[el2_ifu_compress_ctl.scala 401:27]
|
||||
wire [31:0] _T_3 = {16'h0,io_din}; // @[Cat.scala 29:58]
|
||||
wire _T_5 = |_T_3[12:5]; // @[el2_ifu_compress_ctl.scala 257:29]
|
||||
wire [6:0] _T_6 = _T_5 ? 7'h13 : 7'h1f; // @[el2_ifu_compress_ctl.scala 257:20]
|
||||
wire [29:0] _T_20 = {_T_3[10:7],_T_3[12:11],_T_3[5],_T_3[6],2'h0,5'h2,3'h0,2'h1,_T_3[4:2],_T_6}; // @[Cat.scala 29:58]
|
||||
wire [7:0] _T_30 = {_T_3[6:5],_T_3[12:10],3'h0}; // @[Cat.scala 29:58]
|
||||
wire [27:0] _T_38 = {_T_3[6:5],_T_3[12:10],3'h0,2'h1,_T_3[9:7],3'h3,2'h1,_T_3[4:2],7'h7}; // @[Cat.scala 29:58]
|
||||
wire [6:0] _T_52 = {_T_3[5],_T_3[12:10],_T_3[6],2'h0}; // @[Cat.scala 29:58]
|
||||
wire [26:0] _T_60 = {_T_3[5],_T_3[12:10],_T_3[6],2'h0,2'h1,_T_3[9:7],3'h2,2'h1,_T_3[4:2],7'h3}; // @[Cat.scala 29:58]
|
||||
wire [26:0] _T_82 = {_T_3[5],_T_3[12:10],_T_3[6],2'h0,2'h1,_T_3[9:7],3'h2,2'h1,_T_3[4:2],7'h7}; // @[Cat.scala 29:58]
|
||||
wire [26:0] _T_113 = {_T_52[6:5],2'h1,_T_3[4:2],2'h1,_T_3[9:7],3'h2,_T_52[4:0],7'h3f}; // @[Cat.scala 29:58]
|
||||
wire [27:0] _T_140 = {_T_30[7:5],2'h1,_T_3[4:2],2'h1,_T_3[9:7],3'h3,_T_30[4:0],7'h27}; // @[Cat.scala 29:58]
|
||||
wire [26:0] _T_171 = {_T_52[6:5],2'h1,_T_3[4:2],2'h1,_T_3[9:7],3'h2,_T_52[4:0],7'h23}; // @[Cat.scala 29:58]
|
||||
wire [26:0] _T_202 = {_T_52[6:5],2'h1,_T_3[4:2],2'h1,_T_3[9:7],3'h2,_T_52[4:0],7'h27}; // @[Cat.scala 29:58]
|
||||
wire [6:0] _T_213 = _T_3[12] ? 7'h7f : 7'h0; // @[Bitwise.scala 72:12]
|
||||
wire [11:0] _T_215 = {_T_213,_T_3[6:2]}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_221 = {_T_213,_T_3[6:2],_T_3[11:7],3'h0,_T_3[11:7],7'h13}; // @[Cat.scala 29:58]
|
||||
wire [9:0] _T_230 = _T_3[12] ? 10'h3ff : 10'h0; // @[Bitwise.scala 72:12]
|
||||
wire [20:0] _T_245 = {_T_230,_T_3[8],_T_3[10:9],_T_3[6],_T_3[7],_T_3[2],_T_3[11],_T_3[5:3],1'h0}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_308 = {_T_245[20],_T_245[10:1],_T_245[11],_T_245[19:12],5'h1,7'h6f}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_323 = {_T_213,_T_3[6:2],5'h0,3'h0,_T_3[11:7],7'h13}; // @[Cat.scala 29:58]
|
||||
wire _T_334 = |_T_215; // @[el2_ifu_compress_ctl.scala 294:29]
|
||||
wire [6:0] _T_335 = _T_334 ? 7'h37 : 7'h3f; // @[el2_ifu_compress_ctl.scala 294:20]
|
||||
wire [14:0] _T_338 = _T_3[12] ? 15'h7fff : 15'h0; // @[Bitwise.scala 72:12]
|
||||
wire [31:0] _T_341 = {_T_338,_T_3[6:2],12'h0}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_345 = {_T_341[31:12],_T_3[11:7],_T_335}; // @[Cat.scala 29:58]
|
||||
wire _T_353 = _T_3[11:7] == 5'h0; // @[el2_ifu_compress_ctl.scala 296:14]
|
||||
wire _T_355 = _T_3[11:7] == 5'h2; // @[el2_ifu_compress_ctl.scala 296:27]
|
||||
wire _T_356 = _T_353 | _T_355; // @[el2_ifu_compress_ctl.scala 296:21]
|
||||
wire [6:0] _T_363 = _T_334 ? 7'h13 : 7'h1f; // @[el2_ifu_compress_ctl.scala 290:20]
|
||||
wire [2:0] _T_366 = _T_3[12] ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
|
||||
wire [31:0] _T_381 = {_T_366,_T_3[4:3],_T_3[5],_T_3[2],_T_3[6],4'h0,_T_3[11:7],3'h0,_T_3[11:7],_T_363}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_388_bits = _T_356 ? _T_381 : _T_345; // @[el2_ifu_compress_ctl.scala 296:10]
|
||||
wire [25:0] _T_399 = {_T_3[12],_T_3[6:2],2'h1,_T_3[9:7],3'h5,2'h1,_T_3[9:7],7'h13}; // @[Cat.scala 29:58]
|
||||
wire [30:0] _GEN_172 = {{5'd0}, _T_399}; // @[el2_ifu_compress_ctl.scala 303:23]
|
||||
wire [30:0] _T_411 = _GEN_172 | 31'h40000000; // @[el2_ifu_compress_ctl.scala 303:23]
|
||||
wire [31:0] _T_424 = {_T_213,_T_3[6:2],2'h1,_T_3[9:7],3'h7,2'h1,_T_3[9:7],7'h13}; // @[Cat.scala 29:58]
|
||||
wire [2:0] _T_428 = {_T_3[12],_T_3[6:5]}; // @[Cat.scala 29:58]
|
||||
wire _T_430 = _T_3[6:5] == 2'h0; // @[el2_ifu_compress_ctl.scala 307:30]
|
||||
wire [30:0] _T_431 = _T_430 ? 31'h40000000 : 31'h0; // @[el2_ifu_compress_ctl.scala 307:22]
|
||||
wire [6:0] _T_433 = _T_3[12] ? 7'h3b : 7'h33; // @[el2_ifu_compress_ctl.scala 308:22]
|
||||
wire [2:0] _GEN_1 = 3'h1 == _T_428 ? 3'h4 : 3'h0; // @[Cat.scala 29:58]
|
||||
wire [2:0] _GEN_2 = 3'h2 == _T_428 ? 3'h6 : _GEN_1; // @[Cat.scala 29:58]
|
||||
wire [2:0] _GEN_3 = 3'h3 == _T_428 ? 3'h7 : _GEN_2; // @[Cat.scala 29:58]
|
||||
wire [2:0] _GEN_4 = 3'h4 == _T_428 ? 3'h0 : _GEN_3; // @[Cat.scala 29:58]
|
||||
wire [2:0] _GEN_5 = 3'h5 == _T_428 ? 3'h0 : _GEN_4; // @[Cat.scala 29:58]
|
||||
wire [2:0] _GEN_6 = 3'h6 == _T_428 ? 3'h2 : _GEN_5; // @[Cat.scala 29:58]
|
||||
wire [2:0] _GEN_7 = 3'h7 == _T_428 ? 3'h3 : _GEN_6; // @[Cat.scala 29:58]
|
||||
wire [24:0] _T_443 = {2'h1,_T_3[4:2],2'h1,_T_3[9:7],_GEN_7,2'h1,_T_3[9:7],_T_433}; // @[Cat.scala 29:58]
|
||||
wire [30:0] _GEN_173 = {{6'd0}, _T_443}; // @[el2_ifu_compress_ctl.scala 309:43]
|
||||
wire [30:0] _T_444 = _GEN_173 | _T_431; // @[el2_ifu_compress_ctl.scala 309:43]
|
||||
wire [31:0] _T_445_0 = {{6'd0}, _T_399}; // @[el2_ifu_compress_ctl.scala 311:19 el2_ifu_compress_ctl.scala 311:19]
|
||||
wire [31:0] _T_445_1 = {{1'd0}, _T_411}; // @[el2_ifu_compress_ctl.scala 311:19 el2_ifu_compress_ctl.scala 311:19]
|
||||
wire [31:0] _GEN_9 = 2'h1 == _T_3[11:10] ? _T_445_1 : _T_445_0; // @[el2_ifu_compress_ctl.scala 226:14]
|
||||
wire [31:0] _GEN_10 = 2'h2 == _T_3[11:10] ? _T_424 : _GEN_9; // @[el2_ifu_compress_ctl.scala 226:14]
|
||||
wire [31:0] _T_445_3 = {{1'd0}, _T_444}; // @[el2_ifu_compress_ctl.scala 311:19 el2_ifu_compress_ctl.scala 311:19]
|
||||
wire [31:0] _GEN_11 = 2'h3 == _T_3[11:10] ? _T_445_3 : _GEN_10; // @[el2_ifu_compress_ctl.scala 226:14]
|
||||
wire [31:0] _T_535 = {_T_245[20],_T_245[10:1],_T_245[11],_T_245[19:12],5'h0,7'h6f}; // @[Cat.scala 29:58]
|
||||
wire [4:0] _T_544 = _T_3[12] ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12]
|
||||
wire [12:0] _T_553 = {_T_544,_T_3[6:5],_T_3[2],_T_3[11:10],_T_3[4:3],1'h0}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_602 = {_T_553[12],_T_553[10:5],5'h0,2'h1,_T_3[9:7],3'h0,_T_553[4:1],_T_553[11],7'h63}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_669 = {_T_553[12],_T_553[10:5],5'h0,2'h1,_T_3[9:7],3'h1,_T_553[4:1],_T_553[11],7'h63}; // @[Cat.scala 29:58]
|
||||
wire _T_675 = |_T_3[11:7]; // @[el2_ifu_compress_ctl.scala 317:27]
|
||||
wire [6:0] _T_676 = _T_675 ? 7'h3 : 7'h1f; // @[el2_ifu_compress_ctl.scala 317:23]
|
||||
wire [25:0] _T_685 = {_T_3[12],_T_3[6:2],_T_3[11:7],3'h1,_T_3[11:7],7'h13}; // @[Cat.scala 29:58]
|
||||
wire [28:0] _T_701 = {_T_3[4:2],_T_3[12],_T_3[6:5],3'h0,5'h2,3'h3,_T_3[11:7],7'h7}; // @[Cat.scala 29:58]
|
||||
wire [27:0] _T_716 = {_T_3[3:2],_T_3[12],_T_3[6:4],2'h0,5'h2,3'h2,_T_3[11:7],_T_676}; // @[Cat.scala 29:58]
|
||||
wire [27:0] _T_731 = {_T_3[3:2],_T_3[12],_T_3[6:4],2'h0,5'h2,3'h2,_T_3[11:7],7'h7}; // @[Cat.scala 29:58]
|
||||
wire [24:0] _T_741 = {_T_3[6:2],5'h0,3'h0,_T_3[11:7],7'h33}; // @[Cat.scala 29:58]
|
||||
wire [24:0] _T_752 = {_T_3[6:2],_T_3[11:7],3'h0,_T_3[11:7],7'h33}; // @[Cat.scala 29:58]
|
||||
wire [24:0] _T_763 = {_T_3[6:2],_T_3[11:7],3'h0,12'h67}; // @[Cat.scala 29:58]
|
||||
wire [24:0] _T_765 = {_T_763[24:7],7'h1f}; // @[Cat.scala 29:58]
|
||||
wire [24:0] _T_768 = _T_675 ? _T_763 : _T_765; // @[el2_ifu_compress_ctl.scala 338:33]
|
||||
wire _T_774 = |_T_3[6:2]; // @[el2_ifu_compress_ctl.scala 339:27]
|
||||
wire [31:0] _T_745_bits = {{7'd0}, _T_741}; // @[el2_ifu_compress_ctl.scala 225:19 el2_ifu_compress_ctl.scala 226:14]
|
||||
wire [31:0] _T_772_bits = {{7'd0}, _T_768}; // @[el2_ifu_compress_ctl.scala 225:19 el2_ifu_compress_ctl.scala 226:14]
|
||||
wire [31:0] _T_775_bits = _T_774 ? _T_745_bits : _T_772_bits; // @[el2_ifu_compress_ctl.scala 339:22]
|
||||
wire [24:0] _T_781 = {_T_3[6:2],_T_3[11:7],3'h0,12'he7}; // @[Cat.scala 29:58]
|
||||
wire [24:0] _T_783 = {_T_763[24:7],7'h73}; // @[Cat.scala 29:58]
|
||||
wire [24:0] _T_784 = _T_783 | 25'h100000; // @[el2_ifu_compress_ctl.scala 341:46]
|
||||
wire [24:0] _T_787 = _T_675 ? _T_781 : _T_784; // @[el2_ifu_compress_ctl.scala 342:33]
|
||||
wire [31:0] _T_757_bits = {{7'd0}, _T_752}; // @[el2_ifu_compress_ctl.scala 225:19 el2_ifu_compress_ctl.scala 226:14]
|
||||
wire [31:0] _T_791_bits = {{7'd0}, _T_787}; // @[el2_ifu_compress_ctl.scala 225:19 el2_ifu_compress_ctl.scala 226:14]
|
||||
wire [31:0] _T_794_bits = _T_774 ? _T_757_bits : _T_791_bits; // @[el2_ifu_compress_ctl.scala 343:25]
|
||||
wire [31:0] _T_796_bits = _T_3[12] ? _T_794_bits : _T_775_bits; // @[el2_ifu_compress_ctl.scala 344:10]
|
||||
wire [8:0] _T_800 = {_T_3[9:7],_T_3[12:10],3'h0}; // @[Cat.scala 29:58]
|
||||
wire [28:0] _T_812 = {_T_800[8:5],_T_3[6:2],5'h2,3'h3,_T_800[4:0],7'h27}; // @[Cat.scala 29:58]
|
||||
wire [7:0] _T_820 = {_T_3[8:7],_T_3[12:9],2'h0}; // @[Cat.scala 29:58]
|
||||
wire [27:0] _T_832 = {_T_820[7:5],_T_3[6:2],5'h2,3'h2,_T_820[4:0],7'h23}; // @[Cat.scala 29:58]
|
||||
wire [27:0] _T_852 = {_T_820[7:5],_T_3[6:2],5'h2,3'h2,_T_820[4:0],7'h27}; // @[Cat.scala 29:58]
|
||||
wire [4:0] _T_900 = {_T_3[1:0],_T_3[15:13]}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_26_bits = {{2'd0}, _T_20}; // @[el2_ifu_compress_ctl.scala 225:19 el2_ifu_compress_ctl.scala 226:14]
|
||||
wire [31:0] _T_46_bits = {{4'd0}, _T_38}; // @[el2_ifu_compress_ctl.scala 225:19 el2_ifu_compress_ctl.scala 226:14]
|
||||
wire [31:0] _GEN_17 = 5'h1 == _T_900 ? _T_46_bits : _T_26_bits; // @[el2_ifu_compress_ctl.scala 404:19]
|
||||
wire [31:0] _T_68_bits = {{5'd0}, _T_60}; // @[el2_ifu_compress_ctl.scala 225:19 el2_ifu_compress_ctl.scala 226:14]
|
||||
wire [31:0] _GEN_22 = 5'h2 == _T_900 ? _T_68_bits : _GEN_17; // @[el2_ifu_compress_ctl.scala 404:19]
|
||||
wire [31:0] _T_90_bits = {{5'd0}, _T_82}; // @[el2_ifu_compress_ctl.scala 225:19 el2_ifu_compress_ctl.scala 226:14]
|
||||
wire [31:0] _GEN_27 = 5'h3 == _T_900 ? _T_90_bits : _GEN_22; // @[el2_ifu_compress_ctl.scala 404:19]
|
||||
wire [31:0] _T_121_bits = {{5'd0}, _T_113}; // @[el2_ifu_compress_ctl.scala 225:19 el2_ifu_compress_ctl.scala 226:14]
|
||||
wire [31:0] _GEN_32 = 5'h4 == _T_900 ? _T_121_bits : _GEN_27; // @[el2_ifu_compress_ctl.scala 404:19]
|
||||
wire [31:0] _T_148_bits = {{4'd0}, _T_140}; // @[el2_ifu_compress_ctl.scala 225:19 el2_ifu_compress_ctl.scala 226:14]
|
||||
wire [31:0] _GEN_37 = 5'h5 == _T_900 ? _T_148_bits : _GEN_32; // @[el2_ifu_compress_ctl.scala 404:19]
|
||||
wire [31:0] _T_179_bits = {{5'd0}, _T_171}; // @[el2_ifu_compress_ctl.scala 225:19 el2_ifu_compress_ctl.scala 226:14]
|
||||
wire [31:0] _GEN_42 = 5'h6 == _T_900 ? _T_179_bits : _GEN_37; // @[el2_ifu_compress_ctl.scala 404:19]
|
||||
wire [31:0] _T_210_bits = {{5'd0}, _T_202}; // @[el2_ifu_compress_ctl.scala 225:19 el2_ifu_compress_ctl.scala 226:14]
|
||||
wire [31:0] _GEN_47 = 5'h7 == _T_900 ? _T_210_bits : _GEN_42; // @[el2_ifu_compress_ctl.scala 404:19]
|
||||
wire [31:0] _GEN_52 = 5'h8 == _T_900 ? _T_221 : _GEN_47; // @[el2_ifu_compress_ctl.scala 404:19]
|
||||
wire [31:0] _GEN_57 = 5'h9 == _T_900 ? _T_308 : _GEN_52; // @[el2_ifu_compress_ctl.scala 404:19]
|
||||
wire [31:0] _GEN_62 = 5'ha == _T_900 ? _T_323 : _GEN_57; // @[el2_ifu_compress_ctl.scala 404:19]
|
||||
wire [31:0] _GEN_67 = 5'hb == _T_900 ? _T_388_bits : _GEN_62; // @[el2_ifu_compress_ctl.scala 404:19]
|
||||
wire [31:0] _GEN_72 = 5'hc == _T_900 ? _GEN_11 : _GEN_67; // @[el2_ifu_compress_ctl.scala 404:19]
|
||||
wire [31:0] _GEN_77 = 5'hd == _T_900 ? _T_535 : _GEN_72; // @[el2_ifu_compress_ctl.scala 404:19]
|
||||
wire [31:0] _GEN_82 = 5'he == _T_900 ? _T_602 : _GEN_77; // @[el2_ifu_compress_ctl.scala 404:19]
|
||||
wire [31:0] _GEN_87 = 5'hf == _T_900 ? _T_669 : _GEN_82; // @[el2_ifu_compress_ctl.scala 404:19]
|
||||
wire [31:0] _T_690_bits = {{6'd0}, _T_685}; // @[el2_ifu_compress_ctl.scala 225:19 el2_ifu_compress_ctl.scala 226:14]
|
||||
wire [31:0] _GEN_92 = 5'h10 == _T_900 ? _T_690_bits : _GEN_87; // @[el2_ifu_compress_ctl.scala 404:19]
|
||||
wire [31:0] _T_705_bits = {{3'd0}, _T_701}; // @[el2_ifu_compress_ctl.scala 225:19 el2_ifu_compress_ctl.scala 226:14]
|
||||
wire [31:0] _GEN_97 = 5'h11 == _T_900 ? _T_705_bits : _GEN_92; // @[el2_ifu_compress_ctl.scala 404:19]
|
||||
wire [31:0] _T_720_bits = {{4'd0}, _T_716}; // @[el2_ifu_compress_ctl.scala 225:19 el2_ifu_compress_ctl.scala 226:14]
|
||||
wire [31:0] _GEN_102 = 5'h12 == _T_900 ? _T_720_bits : _GEN_97; // @[el2_ifu_compress_ctl.scala 404:19]
|
||||
wire [31:0] _T_735_bits = {{4'd0}, _T_731}; // @[el2_ifu_compress_ctl.scala 225:19 el2_ifu_compress_ctl.scala 226:14]
|
||||
wire [31:0] _GEN_107 = 5'h13 == _T_900 ? _T_735_bits : _GEN_102; // @[el2_ifu_compress_ctl.scala 404:19]
|
||||
wire [31:0] _GEN_112 = 5'h14 == _T_900 ? _T_796_bits : _GEN_107; // @[el2_ifu_compress_ctl.scala 404:19]
|
||||
wire [31:0] _T_816_bits = {{3'd0}, _T_812}; // @[el2_ifu_compress_ctl.scala 225:19 el2_ifu_compress_ctl.scala 226:14]
|
||||
wire [31:0] _GEN_117 = 5'h15 == _T_900 ? _T_816_bits : _GEN_112; // @[el2_ifu_compress_ctl.scala 404:19]
|
||||
wire [31:0] _T_836_bits = {{4'd0}, _T_832}; // @[el2_ifu_compress_ctl.scala 225:19 el2_ifu_compress_ctl.scala 226:14]
|
||||
wire [31:0] _GEN_122 = 5'h16 == _T_900 ? _T_836_bits : _GEN_117; // @[el2_ifu_compress_ctl.scala 404:19]
|
||||
wire [31:0] _T_856_bits = {{4'd0}, _T_852}; // @[el2_ifu_compress_ctl.scala 225:19 el2_ifu_compress_ctl.scala 226:14]
|
||||
wire [31:0] _GEN_127 = 5'h17 == _T_900 ? _T_856_bits : _GEN_122; // @[el2_ifu_compress_ctl.scala 404:19]
|
||||
wire [31:0] _GEN_132 = 5'h18 == _T_900 ? _T_3 : _GEN_127; // @[el2_ifu_compress_ctl.scala 404:19]
|
||||
wire [31:0] _GEN_137 = 5'h19 == _T_900 ? _T_3 : _GEN_132; // @[el2_ifu_compress_ctl.scala 404:19]
|
||||
wire [31:0] _GEN_142 = 5'h1a == _T_900 ? _T_3 : _GEN_137; // @[el2_ifu_compress_ctl.scala 404:19]
|
||||
wire [31:0] _GEN_147 = 5'h1b == _T_900 ? _T_3 : _GEN_142; // @[el2_ifu_compress_ctl.scala 404:19]
|
||||
wire [31:0] _GEN_152 = 5'h1c == _T_900 ? _T_3 : _GEN_147; // @[el2_ifu_compress_ctl.scala 404:19]
|
||||
wire [31:0] _GEN_157 = 5'h1d == _T_900 ? _T_3 : _GEN_152; // @[el2_ifu_compress_ctl.scala 404:19]
|
||||
wire [31:0] _GEN_162 = 5'h1e == _T_900 ? _T_3 : _GEN_157; // @[el2_ifu_compress_ctl.scala 404:19]
|
||||
wire [31:0] _GEN_167 = 5'h1f == _T_900 ? _T_3 : _GEN_162; // @[el2_ifu_compress_ctl.scala 404:19]
|
||||
assign io_dout = _T_1 ? 32'h0 : _GEN_167; // @[el2_ifu_compress_ctl.scala 404:13]
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -362,6 +362,9 @@ class el2_ifu_bp_ctl extends Module with el2_lib {
|
|||
val btb_bank0_rd_data_way0_out = (0 until LRU_SIZE).map(i=>RegEnable(btb_wr_data,0.U,((btb_wr_addr===i.U) & btb_wr_en_way0).asBool))
|
||||
val btb_bank0_rd_data_way1_out = (0 until LRU_SIZE).map(i=>RegEnable(btb_wr_data,0.U,((btb_wr_addr===i.U) & btb_wr_en_way1).asBool))
|
||||
|
||||
// TODO:BTB_rd_mux for normal address
|
||||
|
||||
// TODO:BTB_rd_mux for p1 address
|
||||
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -3,220 +3,215 @@ package ifu
|
|||
import chisel3._
|
||||
import chisel3.util._
|
||||
|
||||
class el2_ifu_compress_ctl extends Module {
|
||||
val io = IO(new Bundle{
|
||||
val din = Input(UInt(16.W))
|
||||
val dout = Output(UInt(32.W))
|
||||
val l1 = Output(UInt(32.W))
|
||||
val l2 = Output(UInt(32.W))
|
||||
val l3 = Output(UInt(32.W))
|
||||
val legal = Output(Bool())
|
||||
val o = Output(UInt(32.W))
|
||||
val sluimmd = Output(UInt())
|
||||
|
||||
val uimm5d = Output(UInt())
|
||||
val ulwspimm7d = Output(UInt())
|
||||
val ulwimm6d = Output(UInt())
|
||||
val simm9d = Output(UInt())
|
||||
val uimm9d = Output(UInt())
|
||||
val simm5d = Output(UInt())
|
||||
val sjald = Output(UInt())
|
||||
val l2_31 = Output(UInt())
|
||||
})
|
||||
|
||||
//io.dout := (0 until 32).map(i=> 0.U.asBool)
|
||||
|
||||
def pat(y : List[Int]) = (0 until y.size).map(i=> if(y(i)>=0) io.din(y(i)) else !io.din(y(i).abs)).reduce(_&_)
|
||||
val out = Wire(Vec(32, UInt(1.W)))
|
||||
out := (0 until 32).map(i=> 0.U.asBool)
|
||||
out(30) := pat(List(15, -14, -13, 10, -6, -5, 0)) | pat(List(15, -14, -13, -11, 10, 0))
|
||||
out(20) := pat(List(-14, 12, -11, -10, -9, -8, -7, -6, -5, -4, -3, -2, 1))
|
||||
out(14) := pat(List(15, -14, -13, -11, 0)) | pat(List(15, -14, -13, -10, 0)) | pat(List(15, -14, -13, 6, 0)) |
|
||||
pat(List(15, -14, -13, 5, 0))
|
||||
out(13) := pat(List(15, -14, -13, 11, -10, 0)) | pat(List(15, -14, -13, 11, 6, 0)) | (io.din(14)&(!io.din(0)))
|
||||
out(12) := pat(List(15, -14, -13, 6, 5, 0)) | pat(List(15, -14, -13, -11, 0)) | pat(List(15, -14, -13, -10, 0)) |
|
||||
pat(List(-15, -14, 1)) | pat(List(15, 14, 13))
|
||||
out(6) := (pat(List(15, -14, -6, -5, -4, -3, -2)) & !io.din(0)) | pat(List(-14, 13)) | pat(List(15, 14, 0))
|
||||
|
||||
out(5) := (io.din(15)&(!io.din(0))) | pat(List(15, 11, 10)) | pat(List(13, -8)) | pat(List(13, 7)) |
|
||||
pat(List(13, 9)) | pat(List(13, 10)) | pat(List(13, 11)) | pat(List(-14, 13)) | pat(List(15, 14))
|
||||
|
||||
|
||||
out(4) := (pat(List(-14, -11, -10, -9, -8, -7))&(!io.din(0))) | (pat(List(-15, -14))&(!io.din(0))) |
|
||||
(pat(List(-14, 6))&(!io.din(0))) | pat(List(-15, 14, 0)) | (pat(List(-14, 5))&(!io.din(0))) |
|
||||
(pat(List(-14, 4))&(!io.din(0))) | (pat(List(-14, 3))&(!io.din(0))) | (pat(List(-14, 2))&(!io.din(0))) |
|
||||
pat(List(-14, -13, 0))
|
||||
|
||||
|
||||
|
||||
|
||||
out(3) := pat(List(-14, 13))
|
||||
out(2) := pat(List(-14, 12, 11, -6, -5, -4, -3, -2, 1)) |
|
||||
pat(List(-14, 12, 10, -6, -5, -4, -3, -2, 1)) |
|
||||
pat(List(-14, 12, 9, -6, -5, -4, -3, -2, 1)) |
|
||||
pat(List(-14, 12, 8, -6,-5,-4, -3, -2,1)) |
|
||||
pat(List(-14, 12, 7, -6, -5, -4, -3, -2,1)) |
|
||||
(pat(List(15, -14,-12, -6, -5, -4, -3, -2))&(!io.din(0))) |
|
||||
pat(List(-15,13,-8)) |
|
||||
pat(List(-15,13,7)) |
|
||||
pat(List(-15,13,9)) |
|
||||
pat(List(-15,13,10)) |
|
||||
pat(List(-15,13,11)) |
|
||||
pat(List(-14,13))
|
||||
out(1) := 1.U.asBool
|
||||
out(0) := 1.U.asBool
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
val rs2d = io.din(6,2)
|
||||
val rdd = io.din(11,7)
|
||||
val rdpd = Cat(1.U(2.W), io.din(9,7))
|
||||
val rs2pd = Cat(1.U(2.W), io.din(4,2))
|
||||
|
||||
val rdrd = pat(List(-14,6,1)) | pat(List(-15,14,11,0)) | pat(List(-14,5,1)) | pat(List(-15,14,10,0)) |
|
||||
pat(List(-14,4,1)) | pat(List(-15,14,9,0)) | pat(List(-14,3,1)) | pat(List(-15,14,-8,0)) |
|
||||
pat(List(-14,2,1)) | pat(List(-15,14,7,0)) | pat(List(-15,1)) | pat(List(-15,-13,0))
|
||||
|
||||
val rdrs1 = pat(List(-14,12,11,1)) |
|
||||
pat(List(-14,12,10,1)) |
|
||||
pat(List(-14,12,9,1)) |
|
||||
pat(List(-14,12,8,1)) |
|
||||
pat(List(-14,12,7,1)) |
|
||||
pat(List(-14,-12,-6,-5,-4,-3,-2,1)) |
|
||||
pat(List(-14,12,6,1)) |
|
||||
pat(List(-14,12,5,1)) |
|
||||
pat(List(-14,12,4,1)) |
|
||||
pat(List(-14,12,3,1)) |
|
||||
pat(List(-14,12,2,1)) |
|
||||
pat(List(-15,-14,-13,0)) |
|
||||
pat(List(-15,-14,1))
|
||||
|
||||
val rs2rs2 = pat(List(15,6,1)) | pat(List(15,5,1)) | pat(List(15,4,1)) | pat(List(15,3,1)) | pat(List(15,2,1)) | pat(List(15,14,1))
|
||||
|
||||
val rdprd = pat(List(15,-14,-13,0))
|
||||
|
||||
val rdprs1 = pat(List(15,-13,0)) | pat(List(15,14,0)) | (pat(List(14,-1))&(!io.din(0)))
|
||||
|
||||
val rs2prs2 = pat(List(15,-14,-13,11,10,0)) | (pat(List(15,-1))&(!io.din(0)))
|
||||
val rs2prd = pat(List(-15,-1))&(!io.din(0))
|
||||
val uimm9_2 = pat(List(-14,-1))&(!io.din(0))
|
||||
val ulwimm6_2 = pat(List(-15,14,-1))&(!io.din(0))
|
||||
val ulwspimm7_2 = pat(List(-15,14,1))
|
||||
val rdeq2 = pat(List(-15,14,13,-11,-10,-9,8,-7))
|
||||
val rdeq1 = pat(List(-14,12,11,-6,-5,-4,-3,-2,1)) | pat(List(-14,12,10,-6,-5,-4,-3,-2,1)) |
|
||||
pat(List(-14,12,9,-6,-5,-4,-3,-2,1)) | pat(List(-14,12,8,-6,-5,-4,-3,-2,1)) |
|
||||
pat(List(-14,12,7,-6,-5,-4,-3,-2,1)) | pat(List(-15,-14,13))
|
||||
val rs1eq2 = pat(List(-15,14,13,-11,-10,-9,8,-7)) | pat(List(14,1)) | (pat(List(-14,-1))&(!io.din(0)))
|
||||
val sbroffset8_1 = pat(List(15,14,0))
|
||||
val simm9_4 = pat(List(-15,14,13,-11,-10,-9,8,-7))
|
||||
val simm5_0 = pat(List(-14,-13,11,-10,0)) | pat(List(-15,-13,0))
|
||||
val sjaloffset11_1 = pat(List(-14,13))
|
||||
val sluimm17_12 = pat(List(-15,14,13,7)) |
|
||||
pat(List(-15,14,13,-8)) |
|
||||
pat(List(-15,14,13,9)) |
|
||||
pat(List(-15,14,13,10)) |
|
||||
pat(List(-15,14,13,11))
|
||||
val uimm5_0 = pat(List(15,-14,-13,-11,0)) | pat(List(-15,-14,1))
|
||||
val uswimm6_2 = pat(List(15,-1))&(!io.din(0))
|
||||
val uswspimm7_2 = pat(List(15,14,1))
|
||||
|
||||
val l1_6 = Cat(out(6),out(5),out(4),out(3),out(2),out(1),out(0)).asUInt()
|
||||
val l1_11 = Cat(out(11),out(10),out(9),out(8),out(7)).asUInt | Mux1H(Seq(rdrd.asBool->rdd,
|
||||
rdprd.asBool->rdpd, rs2prd.asBool->rs2pd, rdeq1.asBool->1.U(5.W), rdeq2.asBool->2.U(5.W)))
|
||||
|
||||
val l1_14 = Cat(out(14),out(13),out(12))
|
||||
|
||||
val l1_19 = Cat(out(19),out(18),out(17),out(16),out(15)).asUInt | Mux1H(Seq(rdrs1.asBool->rdd,
|
||||
rdprs1.asBool->rdpd, rs1eq2.asBool->2.U(5.W)))
|
||||
|
||||
val l1_24 = Cat(out(24),out(23),out(22),out(21),out(20)).asUInt | Mux1H(Seq(rs2rs2.asBool->rs2d,
|
||||
rs2prs2.asBool->rs2pd))
|
||||
val l1_31 = Cat(out(31),out(30),out(29),out(28),out(27),out(26),out(25)).asUInt
|
||||
val l1 = Cat(l1_31,l1_24,l1_19,l1_14,l1_11,l1_6)
|
||||
|
||||
val simm5d = Cat(io.din(12), io.din(6,2))
|
||||
val uimm9d = Cat(io.din(10,7), io.din(12,11), io.din(5), io.din(6))
|
||||
val simm9d = Cat(io.din(12), io.din(4,3), io.din(5), io.din(2), io.din(6))
|
||||
val ulwimm6d = Cat(io.din(5), io.din(12,10), io.din(6))
|
||||
val ulwspimm7d = Cat(io.din(3,2), io.din(12), io.din(6,4))
|
||||
val uimm5d = Cat(io.din(12), io.din(6,2))
|
||||
val sjald_1 = Cat(io.din(12), io.din(8), io.din(10,9), io.din(6), io.din(7), io.din(2), io.din(11),
|
||||
io.din(5,4), io.din(3))
|
||||
val sjald_12 = Fill(9, io.din(12))
|
||||
val sjald = Cat(sjald_12,sjald_1)
|
||||
val sluimmd = Cat(Fill(15, io.din(12)), io.din(6,2))
|
||||
io.sluimmd := sluimmd
|
||||
|
||||
io.l2_31 := l1(31,20)// |
|
||||
//class el2_ifu_compress_ctl extends Module {
|
||||
// val io = IO(new Bundle{
|
||||
// val din = Input(UInt(16.W))
|
||||
// val dout = Output(UInt(32.W))
|
||||
// val l1 = Output(UInt(32.W))
|
||||
// val l2 = Output(UInt(32.W))
|
||||
// val l3 = Output(UInt(32.W))
|
||||
// val legal = Output(Bool())
|
||||
// val o = Output(UInt(32.W))
|
||||
// val sluimmd = Output(UInt())
|
||||
//
|
||||
// val uimm5d = Output(UInt())
|
||||
// val ulwspimm7d = Output(UInt())
|
||||
// val ulwimm6d = Output(UInt())
|
||||
// val simm9d = Output(UInt())
|
||||
// val uimm9d = Output(UInt())
|
||||
// val simm5d = Output(UInt())
|
||||
// val sjald = Output(UInt())
|
||||
// val l2_31 = Output(UInt())
|
||||
// })
|
||||
//
|
||||
// //io.dout := (0 until 32).map(i=> 0.U.asBool)
|
||||
//
|
||||
// def pat(y : List[Int]) = (0 until y.size).map(i=> if(y(i)>=0) io.din(y(i)) else !io.din(y(i).abs)).reduce(_&_)
|
||||
// val out = Wire(Vec(32, UInt(1.W)))
|
||||
// out := (0 until 32).map(i=> 0.U.asBool)
|
||||
// out(30) := pat(List(15, -14, -13, 10, -6, -5, 0)) | pat(List(15, -14, -13, -11, 10, 0))
|
||||
// out(20) := pat(List(-14, 12, -11, -10, -9, -8, -7, -6, -5, -4, -3, -2, 1))
|
||||
// out(14) := pat(List(15, -14, -13, -11, 0)) | pat(List(15, -14, -13, -10, 0)) | pat(List(15, -14, -13, 6, 0)) |
|
||||
// pat(List(15, -14, -13, 5, 0))
|
||||
// out(13) := pat(List(15, -14, -13, 11, -10, 0)) | pat(List(15, -14, -13, 11, 6, 0)) | (io.din(14)&(!io.din(0)))
|
||||
// out(12) := pat(List(15, -14, -13, 6, 5, 0)) | pat(List(15, -14, -13, -11, 0)) | pat(List(15, -14, -13, -10, 0)) |
|
||||
// pat(List(-15, -14, 1)) | pat(List(15, 14, 13))
|
||||
// out(6) := (pat(List(15, -14, -6, -5, -4, -3, -2)) & !io.din(0)) | pat(List(-14, 13)) | pat(List(15, 14, 0))
|
||||
//
|
||||
// out(5) := (io.din(15)&(!io.din(0))) | pat(List(15, 11, 10)) | pat(List(13, -8)) | pat(List(13, 7)) |
|
||||
// pat(List(13, 9)) | pat(List(13, 10)) | pat(List(13, 11)) | pat(List(-14, 13)) | pat(List(15, 14))
|
||||
//
|
||||
//
|
||||
// out(4) := (pat(List(-14, -11, -10, -9, -8, -7))&(!io.din(0))) | (pat(List(-15, -14))&(!io.din(0))) |
|
||||
// (pat(List(-14, 6))&(!io.din(0))) | pat(List(-15, 14, 0)) | (pat(List(-14, 5))&(!io.din(0))) |
|
||||
// (pat(List(-14, 4))&(!io.din(0))) | (pat(List(-14, 3))&(!io.din(0))) | (pat(List(-14, 2))&(!io.din(0))) |
|
||||
// pat(List(-14, -13, 0))
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
// out(3) := pat(List(-14, 13))
|
||||
// out(2) := pat(List(-14, 12, 11, -6, -5, -4, -3, -2, 1)) |
|
||||
// pat(List(-14, 12, 10, -6, -5, -4, -3, -2, 1)) |
|
||||
// pat(List(-14, 12, 9, -6, -5, -4, -3, -2, 1)) |
|
||||
// pat(List(-14, 12, 8, -6,-5,-4, -3, -2,1)) |
|
||||
// pat(List(-14, 12, 7, -6, -5, -4, -3, -2,1)) |
|
||||
// (pat(List(15, -14,-12, -6, -5, -4, -3, -2))&(!io.din(0))) |
|
||||
// pat(List(-15,13,-8)) |
|
||||
// pat(List(-15,13,7)) |
|
||||
// pat(List(-15,13,9)) |
|
||||
// pat(List(-15,13,10)) |
|
||||
// pat(List(-15,13,11)) |
|
||||
// pat(List(-14,13))
|
||||
// out(1) := 1.U.asBool
|
||||
// out(0) := 1.U.asBool
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
// val rs2d = io.din(6,2)
|
||||
// val rdd = io.din(11,7)
|
||||
// val rdpd = Cat(1.U(2.W), io.din(9,7))
|
||||
// val rs2pd = Cat(1.U(2.W), io.din(4,2))
|
||||
//
|
||||
// val rdrd = pat(List(-14,6,1)) | pat(List(-15,14,11,0)) | pat(List(-14,5,1)) | pat(List(-15,14,10,0)) |
|
||||
// pat(List(-14,4,1)) | pat(List(-15,14,9,0)) | pat(List(-14,3,1)) | pat(List(-15,14,-8,0)) |
|
||||
// pat(List(-14,2,1)) | pat(List(-15,14,7,0)) | pat(List(-15,1)) | pat(List(-15,-13,0))
|
||||
//
|
||||
// val rdrs1 = pat(List(-14,12,11,1)) |
|
||||
// pat(List(-14,12,10,1)) |
|
||||
// pat(List(-14,12,9,1)) |
|
||||
// pat(List(-14,12,8,1)) |
|
||||
// pat(List(-14,12,7,1)) |
|
||||
// pat(List(-14,-12,-6,-5,-4,-3,-2,1)) |
|
||||
// pat(List(-14,12,6,1)) |
|
||||
// pat(List(-14,12,5,1)) |
|
||||
// pat(List(-14,12,4,1)) |
|
||||
// pat(List(-14,12,3,1)) |
|
||||
// pat(List(-14,12,2,1)) |
|
||||
// pat(List(-15,-14,-13,0)) |
|
||||
// pat(List(-15,-14,1))
|
||||
//
|
||||
// val rs2rs2 = pat(List(15,6,1)) | pat(List(15,5,1)) | pat(List(15,4,1)) | pat(List(15,3,1)) | pat(List(15,2,1)) | pat(List(15,14,1))
|
||||
//
|
||||
// val rdprd = pat(List(15,-14,-13,0))
|
||||
//
|
||||
// val rdprs1 = pat(List(15,-13,0)) | pat(List(15,14,0)) | (pat(List(14,-1))&(!io.din(0)))
|
||||
//
|
||||
// val rs2prs2 = pat(List(15,-14,-13,11,10,0)) | (pat(List(15,-1))&(!io.din(0)))
|
||||
// val rs2prd = pat(List(-15,-1))&(!io.din(0))
|
||||
// val uimm9_2 = pat(List(-14,-1))&(!io.din(0))
|
||||
// val ulwimm6_2 = pat(List(-15,14,-1))&(!io.din(0))
|
||||
// val ulwspimm7_2 = pat(List(-15,14,1))
|
||||
// val rdeq2 = pat(List(-15,14,13,-11,-10,-9,8,-7))
|
||||
// val rdeq1 = pat(List(-14,12,11,-6,-5,-4,-3,-2,1)) | pat(List(-14,12,10,-6,-5,-4,-3,-2,1)) |
|
||||
// pat(List(-14,12,9,-6,-5,-4,-3,-2,1)) | pat(List(-14,12,8,-6,-5,-4,-3,-2,1)) |
|
||||
// pat(List(-14,12,7,-6,-5,-4,-3,-2,1)) | pat(List(-15,-14,13))
|
||||
// val rs1eq2 = pat(List(-15,14,13,-11,-10,-9,8,-7)) | pat(List(14,1)) | (pat(List(-14,-1))&(!io.din(0)))
|
||||
// val sbroffset8_1 = pat(List(15,14,0))
|
||||
// val simm9_4 = pat(List(-15,14,13,-11,-10,-9,8,-7))
|
||||
// val simm5_0 = pat(List(-14,-13,11,-10,0)) | pat(List(-15,-13,0))
|
||||
// val sjaloffset11_1 = pat(List(-14,13))
|
||||
// val sluimm17_12 = pat(List(-15,14,13,7)) |
|
||||
// pat(List(-15,14,13,-8)) |
|
||||
// pat(List(-15,14,13,9)) |
|
||||
// pat(List(-15,14,13,10)) |
|
||||
// pat(List(-15,14,13,11))
|
||||
// val uimm5_0 = pat(List(15,-14,-13,-11,0)) | pat(List(-15,-14,1))
|
||||
// val uswimm6_2 = pat(List(15,-1))&(!io.din(0))
|
||||
// val uswspimm7_2 = pat(List(15,14,1))
|
||||
//
|
||||
// val l1_6 = Cat(out(6),out(5),out(4),out(3),out(2),out(1),out(0)).asUInt()
|
||||
// val l1_11 = Cat(out(11),out(10),out(9),out(8),out(7)).asUInt | Mux1H(Seq(rdrd.asBool->rdd,
|
||||
// rdprd.asBool->rdpd, rs2prd.asBool->rs2pd, rdeq1.asBool->1.U(5.W), rdeq2.asBool->2.U(5.W)))
|
||||
//
|
||||
// val l1_14 = Cat(out(14),out(13),out(12))
|
||||
//
|
||||
// val l1_19 = Cat(out(19),out(18),out(17),out(16),out(15)).asUInt | Mux1H(Seq(rdrs1.asBool->rdd,
|
||||
// rdprs1.asBool->rdpd, rs1eq2.asBool->2.U(5.W)))
|
||||
//
|
||||
// val l1_24 = Cat(out(24),out(23),out(22),out(21),out(20)).asUInt | Mux1H(Seq(rs2rs2.asBool->rs2d,
|
||||
// rs2prs2.asBool->rs2pd))
|
||||
// val l1_31 = Cat(out(31),out(30),out(29),out(28),out(27),out(26),out(25)).asUInt
|
||||
// val l1 = Cat(l1_31,l1_24,l1_19,l1_14,l1_11,l1_6)
|
||||
//
|
||||
// val simm5d = Cat(io.din(12), io.din(6,2))
|
||||
// val uimm9d = Cat(io.din(10,7), io.din(12,11), io.din(5), io.din(6))
|
||||
// val simm9d = Cat(io.din(12), io.din(4,3), io.din(5), io.din(2), io.din(6))
|
||||
// val ulwimm6d = Cat(io.din(5), io.din(12,10), io.din(6))
|
||||
// val ulwspimm7d = Cat(io.din(3,2), io.din(12), io.din(6,4))
|
||||
// val uimm5d = Cat(io.din(12), io.din(6,2))
|
||||
// val sjald_1 = Cat(io.din(12), io.din(8), io.din(10,9), io.din(6), io.din(7), io.din(2), io.din(11),
|
||||
// io.din(5,4), io.din(3))
|
||||
// val sjald_12 = Fill(9, io.din(12))
|
||||
// val sjald = Cat(sjald_12,sjald_1)
|
||||
// val sluimmd = Cat(Fill(15, io.din(12)), io.din(6,2))
|
||||
// io.sluimmd := sluimmd
|
||||
//
|
||||
// io.l2_31 := l1(31,20) |
|
||||
// Mux1H(Seq(simm5_0.asBool->Cat(Fill(7, simm5d(5)), simm5d(4,0)),
|
||||
// uimm9_2.asBool->Cat(0.U(2.W), uimm9d, 0.U(2.W)),
|
||||
// simm9_4.asBool->Cat(Fill(3, simm9d(5)), simm9d(4,0), 0.U(4.W)),
|
||||
// ulwimm6_2.asBool->Cat(0.U(5.W), ulwimm6d, 0.U(2.W)),
|
||||
// ulwspimm7_2.asBool->Cat(0.U(4.W), ulwspimm7d, 0.U(2.W)),
|
||||
// uimm5_0.asBool->Cat(0.U(6.W), uimm5d),
|
||||
// sjaloffset11_1->Cat(sjald(19), sjald(9,0), sjald(10)),
|
||||
// sluimm17_12->sluimmd(19,8)))
|
||||
|
||||
val l2_19 = l1(19,12) | Mux1H(Seq(sjaloffset11_1.asBool->sjald(19,11),
|
||||
sluimm17_12.asBool->sluimmd(7,0)))
|
||||
val l2 = Cat(io.l2_31, l2_19, l1(11,0))
|
||||
|
||||
|
||||
val sbr8d = Cat(io.din(12),io.din(6),io.din(5),io.din(2),io.din(11),io.din(10),io.din(4),io.din(3),0.U)
|
||||
val uswimm6d = Cat(io.din(5), io.din(12,10), io.din(6), 0.U(2.W))
|
||||
val uswspimm7d = Cat(io.din(8,7),io.din(12,9), 0.U(2.W))
|
||||
val l3_31 = l2(31,25) | Mux1H(Seq(sbroffset8_1.asBool->Cat(Fill(4,sbr8d(8)),sbr8d(7,5)),
|
||||
uswimm6_2.asBool->Cat(0.U(5.W),uswimm6d(6,5)),
|
||||
uswspimm7_2.asBool->Cat(0.U(4.W),uswspimm7d(7,5))))
|
||||
val l3_24 = l2(24,12)
|
||||
val l3_11 = l2(11,7) | Mux1H(Seq(sbroffset8_1.asBool->Cat(sbr8d(4,1), sbr8d(8)),
|
||||
uswimm6_2.asBool->uswimm6d(4,0),
|
||||
uswspimm7_2.asBool->uswspimm7d(4,0)))
|
||||
val l3 = Cat(l3_31, l3_24, l3_11, l2(6,0))
|
||||
|
||||
val legal = (pat(List(-13,-12,11,1))&(!io.din(0))) | (pat(List(-13,-12,6,1))&(!io.din(0))) |
|
||||
pat(List(-15,-13,11,-1)) | (pat(List(-13,-12,5,1))&(!io.din(0))) | (pat(List(-13,-12,10,1))&(!io.din(0))) |
|
||||
pat(List(-15,-13,6,-1)) | pat(List(15,-12,-1,0)) | (pat(List(-13,-12,9,1))&(!io.din(0))) | pat(List(-12,6,-1,0)) | pat(List(-15,-13,5,-1)) |
|
||||
(pat(List(-13,-12,8,1))&(!io.din(0))) | pat(List(-12,5,-1,0)) | pat(List(-15,-13,10,-1)) |
|
||||
(pat(List(-13,-12,7,1))&(!io.din(0))) | pat(List(12,11,-10,-1,0)) | pat(List(-15,-13,9,-1)) |
|
||||
(pat(List(-13,-12,4,1))&(!io.din(0))) | pat(List(13,12,-1,0)) | pat(List(-15,-13,8,-1)) |
|
||||
(pat(List(-13,-12,3,1))&(!io.din(0))) | pat(List(13,4,-1,0)) | (pat(List(-13,-12,2,1))&(!io.din(0))) |
|
||||
pat(List(-15,-13,7,-1)) | pat(List(13,3,-1,0)) | pat(List(13,2,-1,0)) | pat(List(14,-13,-1)) |
|
||||
pat(List(-14,-12,-1,0)) | (pat(List(15,-13,12,1))&(!io.din(0))) | (pat(List(-15,-13,-12,1))&(!io.din(0))) |
|
||||
pat(List(-15,-13,12,-1)) | (pat(List(14,-13))&(!io.din(0)))
|
||||
|
||||
io.dout:= l3 & Fill(32, legal)
|
||||
io.l1 := l1
|
||||
io.l2 := l2
|
||||
io.l3 := l3
|
||||
io.legal := legal
|
||||
io.o := out.reverse.reduce(Cat(_,_))
|
||||
// io.sluimmd := sluimmd
|
||||
// io.simm5_0 := simm5_0
|
||||
// io.uimm9_2 := uimm9_2
|
||||
// io.simm9_4 := simm9_4
|
||||
// io.ulwimm6_2 := ulwimm6_2
|
||||
// io.ulwspimm7_2 := ulwspimm7_2
|
||||
// io.uimm5_0 := uimm5_0
|
||||
// sjaloffset11_1.asBool->Cat(sjald(19), sjald(9,0), sjald(10)),
|
||||
// sluimm17_12.asBool->sluimmd(19,8)))
|
||||
//
|
||||
io.sjald := sjald
|
||||
io.uimm5d := uimm5d
|
||||
io.ulwspimm7d := ulwspimm7d
|
||||
io.ulwimm6d := ulwimm6d//Output(UInt())
|
||||
io.simm9d := simm9d//Output(UInt())
|
||||
io.uimm9d := uimm9d//Output(UInt())
|
||||
io.simm5d := simm5d//Output(UInt())
|
||||
// val l2_19 = l1(19,12) | Mux1H(Seq(sjaloffset11_1.asBool->sjald(19,11),
|
||||
// sluimm17_12.asBool->sluimmd(7,0)))
|
||||
// val l2 = Cat(io.l2_31, l2_19, l1(11,0))
|
||||
//
|
||||
//
|
||||
// val sbr8d = Cat(io.din(12),io.din(6),io.din(5),io.din(2),io.din(11),io.din(10),io.din(4),io.din(3),0.U)
|
||||
// val uswimm6d = Cat(io.din(5), io.din(12,10), io.din(6), 0.U(2.W))
|
||||
// val uswspimm7d = Cat(io.din(8,7),io.din(12,9), 0.U(2.W))
|
||||
// val l3_31 = l2(31,25) | Mux1H(Seq(sbroffset8_1.asBool->Cat(Fill(4,sbr8d(8)),sbr8d(7,5)),
|
||||
// uswimm6_2.asBool->Cat(0.U(5.W),uswimm6d(6,5)),
|
||||
// uswspimm7_2.asBool->Cat(0.U(4.W),uswspimm7d(7,5))))
|
||||
// val l3_24 = l2(24,12)
|
||||
// val l3_11 = l2(11,7) | Mux1H(Seq(sbroffset8_1.asBool->Cat(sbr8d(4,1), sbr8d(8)),
|
||||
// uswimm6_2.asBool->uswimm6d(4,0),
|
||||
// uswspimm7_2.asBool->uswspimm7d(4,0)))
|
||||
// val l3 = Cat(l3_31, l3_24, l3_11, l2(6,0))
|
||||
//
|
||||
// val legal = (pat(List(-13,-12,11,1))&(!io.din(0))) | (pat(List(-13,-12,6,1))&(!io.din(0))) |
|
||||
// pat(List(-15,-13,11,-1)) | (pat(List(-13,-12,5,1))&(!io.din(0))) | (pat(List(-13,-12,10,1))&(!io.din(0))) |
|
||||
// pat(List(-15,-13,6,-1)) | pat(List(15,-12,-1,0)) | (pat(List(-13,-12,9,1))&(!io.din(0))) | pat(List(-12,6,-1,0)) | pat(List(-15,-13,5,-1)) |
|
||||
// (pat(List(-13,-12,8,1))&(!io.din(0))) | pat(List(-12,5,-1,0)) | pat(List(-15,-13,10,-1)) |
|
||||
// (pat(List(-13,-12,7,1))&(!io.din(0))) | pat(List(12,11,-10,-1,0)) | pat(List(-15,-13,9,-1)) |
|
||||
// (pat(List(-13,-12,4,1))&(!io.din(0))) | pat(List(13,12,-1,0)) | pat(List(-15,-13,8,-1)) |
|
||||
// (pat(List(-13,-12,3,1))&(!io.din(0))) | pat(List(13,4,-1,0)) | (pat(List(-13,-12,2,1))&(!io.din(0))) |
|
||||
// pat(List(-15,-13,7,-1)) | pat(List(13,3,-1,0)) | pat(List(13,2,-1,0)) | pat(List(14,-13,-1)) |
|
||||
// pat(List(-14,-12,-1,0)) | (pat(List(15,-13,12,1))&(!io.din(0))) | (pat(List(-15,-13,-12,1))&(!io.din(0))) |
|
||||
// pat(List(-15,-13,12,-1)) | (pat(List(14,-13))&(!io.din(0)))
|
||||
//
|
||||
// io.dout:= l3 & Fill(32, legal)
|
||||
// io.l1 := l1
|
||||
// io.l2 := l2
|
||||
// io.l3 := l3
|
||||
// io.legal := legal
|
||||
// io.o := out.reverse.reduce(Cat(_,_))
|
||||
//// io.sluimmd := sluimmd
|
||||
//// io.simm5_0 := simm5_0
|
||||
//// io.uimm9_2 := uimm9_2
|
||||
//// io.simm9_4 := simm9_4
|
||||
//// io.ulwimm6_2 := ulwimm6_2
|
||||
//// io.ulwspimm7_2 := ulwspimm7_2
|
||||
//// io.uimm5_0 := uimm5_0
|
||||
////
|
||||
// io.sjald := sjald
|
||||
// io.uimm5d := uimm5d
|
||||
// io.ulwspimm7d := ulwspimm7d
|
||||
// io.ulwimm6d := ulwimm6d//Output(UInt())
|
||||
// io.simm9d := simm9d//Output(UInt())
|
||||
// io.uimm9d := uimm9d//Output(UInt())
|
||||
// io.simm5d := simm5d//Output(UInt())
|
||||
//
|
||||
//
|
||||
//}
|
||||
|
||||
|
||||
}
|
||||
|
||||
object ifu_compress extends App {
|
||||
println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu_compress_ctl()))
|
||||
}
|
||||
|
||||
/*
|
||||
class ExpandedInstruction extends Bundle {
|
||||
val bits = UInt(32.W)
|
||||
val rd = UInt(5.W)
|
||||
|
|
@ -437,5 +432,8 @@ class el2_ifu_compress_ctl( val XLen: Int, val usingCompressed: Boolean) extends
|
|||
//io.rvc := false.B
|
||||
io.dout := new RVCDecoder(io.din, XLen).passthrough
|
||||
}
|
||||
}*/
|
||||
}
|
||||
|
||||
object ifu_compress extends App {
|
||||
println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu_compress_ctl(32, true)))
|
||||
}
|
||||
|
|
|
|||
|
|
@ -63,11 +63,6 @@ class EL2_IC_TAG extends Module with el2_lib with param {
|
|||
val ic_tag_perr = Output(Bool())
|
||||
val scan_mode = Input(Bool())
|
||||
|
||||
val test = Output(UInt(26.W))
|
||||
val test_ecc_data_out = Output(Vec(ICACHE_NUM_WAYS,UInt(32.W)))
|
||||
val test_ecc_out = Output(Vec(ICACHE_NUM_WAYS,UInt(7.W)))
|
||||
val test_ecc_sb_out = Output(Vec(ICACHE_NUM_WAYS,UInt(1.W)))
|
||||
val test_ecc_db_out = Output(Vec(ICACHE_NUM_WAYS,UInt(1.W)))
|
||||
})
|
||||
|
||||
val ic_tag_wren = io.ic_wr_en & repl(ICACHE_NUM_WAYS, io.ic_rw_addr(ICACHE_BEAT_ADDR_HI,4)===
|
||||
|
|
@ -152,15 +147,6 @@ class EL2_IC_TAG extends Module with el2_lib with param {
|
|||
ecc_decode(i).io.din := Cat(0.U(11.W),ic_tag_data_raw(i)(20,0))
|
||||
ecc_decode(i).io.ecc_in := Cat(0.U(2.W),ic_tag_data_raw(i)(25,21))
|
||||
|
||||
ic_tag_corrected_data_unc := io.test_ecc_data_out
|
||||
ic_tag_corrected_ecc_unc := io.test_ecc_out
|
||||
ic_tag_single_ecc_error := io.test_ecc_sb_out
|
||||
ic_tag_double_ecc_error := io.test_ecc_db_out
|
||||
|
||||
io.test_ecc_data_out(i) := ecc_decode(i).io.dout
|
||||
io.test_ecc_out(i) := ecc_decode(i).io.ecc_out
|
||||
io.test_ecc_sb_out(i) := ecc_decode(i).io.single_ecc_error
|
||||
io.test_ecc_db_out(i) := ecc_decode(i).io.double_ecc_error
|
||||
|
||||
ic_tag_way_perr(i) := ic_tag_single_ecc_error(i) | ic_tag_double_ecc_error(i)
|
||||
}
|
||||
|
|
@ -173,7 +159,6 @@ class EL2_IC_TAG extends Module with el2_lib with param {
|
|||
repl(26,ic_debug_rd_way_en_ff(i))&ic_tag_data_raw(i)
|
||||
}
|
||||
io.ictag_debug_rd_data := temp
|
||||
io.test := w_tout.reduce(_&_)
|
||||
io.ic_tag_perr := (ic_tag_way_perr.reverse.reduce(Cat(_,_)) & io.ic_tag_valid).orR
|
||||
val w_tout_Vec = VecInit.tabulate(ICACHE_NUM_WAYS)(i=> w_tout(i))
|
||||
io.ic_rd_hit := VecInit.tabulate(ICACHE_NUM_WAYS)(i=>(w_tout_Vec(i)(31,ICACHE_TAG_LO)===ic_rw_addr_ff(31,ICACHE_TAG_LO)).asUInt() & io.ic_tag_valid).reverse.reduce(Cat(_,_))
|
||||
|
|
@ -298,6 +283,6 @@ class EL2_IC_DATA extends Module with el2_lib {
|
|||
//println(s"${DATA_MEM_LINE._2}")
|
||||
}
|
||||
|
||||
//object ifu_ic extends App {
|
||||
// println((new chisel3.stage.ChiselStage).emitVerilog(new EL2_IC_DATA()))
|
||||
//}
|
||||
object ifu_ic extends App {
|
||||
println((new chisel3.stage.ChiselStage).emitVerilog(new EL2_IC_DATA()))
|
||||
}
|
||||
|
|
@ -86,7 +86,7 @@ val io = IO(new Bundle{
|
|||
//io.test_out := io.ifc_fetch_addr_bf
|
||||
|
||||
line_wrap := 0.U//fetch_addr_next(ICACHE_TAG_INDEX_LO) ^ io.ifc_fetch_addr_f(ICACHE_TAG_INDEX_LO)
|
||||
|
||||
val fetch_addr_next_1 = Mux(line_wrap.asBool(), 0.U, io.ifc_fetch_addr_f(0))
|
||||
fetch_addr_next := Cat(io.ifc_fetch_addr_f(30,1)+1.U, 0.U) //|
|
||||
//Mux(line_wrap.asBool(), 0.U, io.ifc_fetch_addr_f(0)))
|
||||
|
||||
|
|
@ -140,7 +140,7 @@ val io = IO(new Bundle{
|
|||
fb_write_f := RegNext(fb_write_ns, 0.U)
|
||||
|
||||
io.ifu_pmu_fetch_stall := wfm | (io.ifc_fetch_req_bf_raw & ( (fb_full_f &
|
||||
~(io.ifu_fb_consume2 | io.ifu_fb_consume1 | io.exu_flush_final)) | dma_stall))
|
||||
!(io.ifu_fb_consume2 | io.ifu_fb_consume1 | io.exu_flush_final)) | dma_stall))
|
||||
|
||||
val (iccm_acc_in_region_bf, iccm_acc_in_range_bf) = if(ICCM_ENABLE)
|
||||
rvrangecheck(ICCM_SADR, ICCM_SIZE, Cat(io.ifc_fetch_addr_bf,0.U))
|
||||
|
|
|
|||
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Loading…
Reference in New Issue