lsu update
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@ -19,7 +19,7 @@ class el2_lsu_ecc extends Module with el2_lib with RequireAsyncReset {
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val lsu_addr_r = Input(UInt(DCCM_BITS.W))
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val end_addr_r = Input(UInt(DCCM_BITS.W))
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val lsu_addr_m = Input(UInt(DCCM_BITS.W))
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val lsu_addr_m = Input(UInt(DCCM_BITS.W))//6fba5e03053441e71b7d54f50a77e3b496d56173
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val end_addr_m = Input(UInt(DCCM_BITS.W))
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val dccm_rdata_hi_r = Input(UInt(DCCM_DATA_WIDTH.W))
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