Async reset done in IFC
This commit is contained in:
waleed-lm
parent
6bdc75f842
commit
2b6128eb48
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@ -7,10 +7,10 @@
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"~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_way",
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"~EL2_IC_DATA|EL2_IC_DATA>io_clk_override",
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"~EL2_IC_DATA|EL2_IC_DATA>io_ic_rw_addr",
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"~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_addr",
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"~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_rd_en",
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"~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_wr_en",
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"~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_addr",
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"~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_tag_array",
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"~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_rd_en",
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"~EL2_IC_DATA|EL2_IC_DATA>io_ic_rd_en"
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]
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},
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388
EL2_IC_DATA.fir
388
EL2_IC_DATA.fir
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@ -33,54 +33,53 @@ circuit EL2_IC_DATA :
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node _T_11 = bits(ic_rw_addr_q, 11, 3) @[el2_ifu_ic_mem.scala 208:38]
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node _T_12 = add(_T_11, UInt<1>("h01")) @[el2_ifu_ic_mem.scala 208:79]
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node ic_rw_addr_q_inc = tail(_T_12, 1) @[el2_ifu_ic_mem.scala 208:79]
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io.test <= ic_rw_addr_q_inc @[el2_ifu_ic_mem.scala 209:11]
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node _T_13 = bits(io.ic_debug_addr, 0, 0) @[el2_ifu_ic_mem.scala 211:78]
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node _T_14 = eq(_T_13, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 211:113]
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node _T_13 = bits(io.ic_debug_addr, 0, 0) @[el2_ifu_ic_mem.scala 210:78]
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node _T_14 = eq(_T_13, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 210:113]
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node _T_15 = bits(_T_14, 0, 0) @[Bitwise.scala 72:15]
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node _T_16 = mux(_T_15, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
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node _T_17 = and(ic_debug_wr_way_en, _T_16) @[el2_ifu_ic_mem.scala 211:38]
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node ic_b_sb_wren_0 = or(io.ic_wr_en, _T_17) @[el2_ifu_ic_mem.scala 211:17]
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node _T_18 = bits(io.ic_debug_addr, 0, 0) @[el2_ifu_ic_mem.scala 211:78]
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node _T_19 = eq(_T_18, UInt<1>("h01")) @[el2_ifu_ic_mem.scala 211:113]
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node _T_17 = and(ic_debug_wr_way_en, _T_16) @[el2_ifu_ic_mem.scala 210:38]
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node ic_b_sb_wren_0 = or(io.ic_wr_en, _T_17) @[el2_ifu_ic_mem.scala 210:17]
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node _T_18 = bits(io.ic_debug_addr, 0, 0) @[el2_ifu_ic_mem.scala 210:78]
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node _T_19 = eq(_T_18, UInt<1>("h01")) @[el2_ifu_ic_mem.scala 210:113]
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node _T_20 = bits(_T_19, 0, 0) @[Bitwise.scala 72:15]
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node _T_21 = mux(_T_20, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
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node _T_22 = and(ic_debug_wr_way_en, _T_21) @[el2_ifu_ic_mem.scala 211:38]
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node ic_b_sb_wren_1 = or(io.ic_wr_en, _T_22) @[el2_ifu_ic_mem.scala 211:17]
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node _T_23 = bits(io.ic_debug_addr, 0, 0) @[el2_ifu_ic_mem.scala 212:76]
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node _T_24 = eq(_T_23, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 212:111]
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node _T_25 = bits(io.ic_debug_addr, 0, 0) @[el2_ifu_ic_mem.scala 212:76]
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node _T_26 = eq(_T_25, UInt<1>("h01")) @[el2_ifu_ic_mem.scala 212:111]
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node _T_22 = and(ic_debug_wr_way_en, _T_21) @[el2_ifu_ic_mem.scala 210:38]
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node ic_b_sb_wren_1 = or(io.ic_wr_en, _T_22) @[el2_ifu_ic_mem.scala 210:17]
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node _T_23 = bits(io.ic_debug_addr, 0, 0) @[el2_ifu_ic_mem.scala 211:76]
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node _T_24 = eq(_T_23, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 211:111]
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node _T_25 = bits(io.ic_debug_addr, 0, 0) @[el2_ifu_ic_mem.scala 211:76]
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node _T_26 = eq(_T_25, UInt<1>("h01")) @[el2_ifu_ic_mem.scala 211:111]
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node ic_debug_sel_sb = cat(_T_26, _T_24) @[Cat.scala 29:58]
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node _T_27 = bits(ic_debug_sel_sb, 0, 0) @[el2_ifu_ic_mem.scala 213:77]
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node _T_28 = and(_T_27, io.ic_debug_wr_en) @[el2_ifu_ic_mem.scala 213:80]
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node _T_29 = bits(_T_28, 0, 0) @[el2_ifu_ic_mem.scala 213:100]
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node _T_30 = bits(ic_bank_wr_data, 0, 0) @[el2_ifu_ic_mem.scala 213:144]
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node ic_sb_wr_data_0 = mux(_T_29, io.ic_debug_wr_data, _T_30) @[el2_ifu_ic_mem.scala 213:60]
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node _T_31 = bits(ic_debug_sel_sb, 1, 1) @[el2_ifu_ic_mem.scala 213:77]
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node _T_32 = and(_T_31, io.ic_debug_wr_en) @[el2_ifu_ic_mem.scala 213:80]
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node _T_33 = bits(_T_32, 0, 0) @[el2_ifu_ic_mem.scala 213:100]
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node _T_34 = bits(ic_bank_wr_data, 1, 1) @[el2_ifu_ic_mem.scala 213:144]
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node ic_sb_wr_data_1 = mux(_T_33, io.ic_debug_wr_data, _T_34) @[el2_ifu_ic_mem.scala 213:60]
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node _T_35 = bits(ic_rw_addr_q, 2, 2) @[el2_ifu_ic_mem.scala 215:29]
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node _T_36 = bits(_T_35, 0, 0) @[el2_ifu_ic_mem.scala 215:48]
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node _T_37 = eq(_T_36, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 215:16]
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node _T_38 = eq(UInt<1>("h00"), UInt<1>("h00")) @[el2_ifu_ic_mem.scala 215:63]
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node _T_39 = bits(ic_rw_addr_q, 2, 2) @[el2_ifu_ic_mem.scala 216:42]
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node _T_40 = bits(_T_39, 0, 0) @[el2_ifu_ic_mem.scala 216:62]
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node _T_41 = bits(ic_rw_addr_q, 1, 0) @[el2_ifu_ic_mem.scala 216:86]
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node _T_42 = eq(_T_41, UInt<2>("h03")) @[el2_ifu_ic_mem.scala 216:91]
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node _T_43 = eq(UInt<1>("h00"), UInt<1>("h00")) @[el2_ifu_ic_mem.scala 216:103]
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node _T_44 = and(_T_42, _T_43) @[el2_ifu_ic_mem.scala 216:98]
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node _T_45 = bits(ic_rw_addr_q, 2, 2) @[el2_ifu_ic_mem.scala 217:42]
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node _T_46 = bits(_T_45, 0, 0) @[el2_ifu_ic_mem.scala 217:61]
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node _T_47 = eq(UInt<1>("h00"), UInt<1>("h01")) @[el2_ifu_ic_mem.scala 217:76]
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node _T_48 = bits(ic_rw_addr_q, 2, 2) @[el2_ifu_ic_mem.scala 218:43]
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node _T_49 = eq(_T_48, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 218:30]
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node _T_50 = bits(_T_49, 0, 0) @[el2_ifu_ic_mem.scala 218:63]
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node _T_51 = bits(ic_rw_addr_q, 1, 0) @[el2_ifu_ic_mem.scala 218:87]
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node _T_52 = eq(_T_51, UInt<2>("h03")) @[el2_ifu_ic_mem.scala 218:92]
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node _T_53 = eq(UInt<1>("h00"), UInt<1>("h01")) @[el2_ifu_ic_mem.scala 218:105]
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node _T_54 = and(_T_52, _T_53) @[el2_ifu_ic_mem.scala 218:99]
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node _T_27 = bits(ic_debug_sel_sb, 0, 0) @[el2_ifu_ic_mem.scala 212:77]
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node _T_28 = and(_T_27, io.ic_debug_wr_en) @[el2_ifu_ic_mem.scala 212:80]
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node _T_29 = bits(_T_28, 0, 0) @[el2_ifu_ic_mem.scala 212:100]
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node _T_30 = bits(ic_bank_wr_data, 0, 0) @[el2_ifu_ic_mem.scala 212:144]
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node ic_sb_wr_data_0 = mux(_T_29, io.ic_debug_wr_data, _T_30) @[el2_ifu_ic_mem.scala 212:60]
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node _T_31 = bits(ic_debug_sel_sb, 1, 1) @[el2_ifu_ic_mem.scala 212:77]
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node _T_32 = and(_T_31, io.ic_debug_wr_en) @[el2_ifu_ic_mem.scala 212:80]
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node _T_33 = bits(_T_32, 0, 0) @[el2_ifu_ic_mem.scala 212:100]
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node _T_34 = bits(ic_bank_wr_data, 1, 1) @[el2_ifu_ic_mem.scala 212:144]
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node ic_sb_wr_data_1 = mux(_T_33, io.ic_debug_wr_data, _T_34) @[el2_ifu_ic_mem.scala 212:60]
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node _T_35 = bits(ic_rw_addr_q, 2, 2) @[el2_ifu_ic_mem.scala 214:29]
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node _T_36 = bits(_T_35, 0, 0) @[el2_ifu_ic_mem.scala 214:48]
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node _T_37 = eq(_T_36, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 214:16]
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node _T_38 = eq(UInt<1>("h00"), UInt<1>("h00")) @[el2_ifu_ic_mem.scala 214:63]
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node _T_39 = bits(ic_rw_addr_q, 2, 2) @[el2_ifu_ic_mem.scala 215:42]
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node _T_40 = bits(_T_39, 0, 0) @[el2_ifu_ic_mem.scala 215:62]
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node _T_41 = bits(ic_rw_addr_q, 1, 0) @[el2_ifu_ic_mem.scala 215:86]
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node _T_42 = eq(_T_41, UInt<2>("h03")) @[el2_ifu_ic_mem.scala 215:91]
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node _T_43 = eq(UInt<1>("h00"), UInt<1>("h00")) @[el2_ifu_ic_mem.scala 215:103]
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node _T_44 = and(_T_42, _T_43) @[el2_ifu_ic_mem.scala 215:98]
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node _T_45 = bits(ic_rw_addr_q, 2, 2) @[el2_ifu_ic_mem.scala 216:42]
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node _T_46 = bits(_T_45, 0, 0) @[el2_ifu_ic_mem.scala 216:61]
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node _T_47 = eq(UInt<1>("h00"), UInt<1>("h01")) @[el2_ifu_ic_mem.scala 216:76]
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node _T_48 = bits(ic_rw_addr_q, 2, 2) @[el2_ifu_ic_mem.scala 217:43]
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node _T_49 = eq(_T_48, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 217:30]
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node _T_50 = bits(_T_49, 0, 0) @[el2_ifu_ic_mem.scala 217:63]
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node _T_51 = bits(ic_rw_addr_q, 1, 0) @[el2_ifu_ic_mem.scala 217:87]
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node _T_52 = eq(_T_51, UInt<2>("h03")) @[el2_ifu_ic_mem.scala 217:92]
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node _T_53 = eq(UInt<1>("h00"), UInt<1>("h01")) @[el2_ifu_ic_mem.scala 217:105]
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node _T_54 = and(_T_52, _T_53) @[el2_ifu_ic_mem.scala 217:99]
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node _T_55 = mux(_T_37, _T_38, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_56 = mux(_T_40, _T_44, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_57 = mux(_T_46, _T_47, UInt<1>("h00")) @[Mux.scala 27:72]
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@ -90,27 +89,27 @@ circuit EL2_IC_DATA :
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node _T_61 = or(_T_60, _T_58) @[Mux.scala 27:72]
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wire _T_62 : UInt<1> @[Mux.scala 27:72]
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_T_62 <= _T_61 @[Mux.scala 27:72]
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node _T_63 = and(_T_62, ic_rd_en_with_debug) @[el2_ifu_ic_mem.scala 218:117]
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node _T_64 = bits(ic_rw_addr_q, 2, 2) @[el2_ifu_ic_mem.scala 215:29]
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node _T_65 = bits(_T_64, 0, 0) @[el2_ifu_ic_mem.scala 215:48]
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node _T_66 = eq(_T_65, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 215:16]
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node _T_67 = eq(UInt<1>("h01"), UInt<1>("h00")) @[el2_ifu_ic_mem.scala 215:63]
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node _T_68 = bits(ic_rw_addr_q, 2, 2) @[el2_ifu_ic_mem.scala 216:42]
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node _T_69 = bits(_T_68, 0, 0) @[el2_ifu_ic_mem.scala 216:62]
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node _T_70 = bits(ic_rw_addr_q, 1, 0) @[el2_ifu_ic_mem.scala 216:86]
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node _T_71 = eq(_T_70, UInt<2>("h03")) @[el2_ifu_ic_mem.scala 216:91]
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node _T_72 = eq(UInt<1>("h01"), UInt<1>("h00")) @[el2_ifu_ic_mem.scala 216:103]
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node _T_73 = and(_T_71, _T_72) @[el2_ifu_ic_mem.scala 216:98]
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node _T_74 = bits(ic_rw_addr_q, 2, 2) @[el2_ifu_ic_mem.scala 217:42]
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node _T_75 = bits(_T_74, 0, 0) @[el2_ifu_ic_mem.scala 217:61]
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node _T_76 = eq(UInt<1>("h01"), UInt<1>("h01")) @[el2_ifu_ic_mem.scala 217:76]
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node _T_77 = bits(ic_rw_addr_q, 2, 2) @[el2_ifu_ic_mem.scala 218:43]
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node _T_78 = eq(_T_77, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 218:30]
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node _T_79 = bits(_T_78, 0, 0) @[el2_ifu_ic_mem.scala 218:63]
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node _T_80 = bits(ic_rw_addr_q, 1, 0) @[el2_ifu_ic_mem.scala 218:87]
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node _T_81 = eq(_T_80, UInt<2>("h03")) @[el2_ifu_ic_mem.scala 218:92]
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node _T_82 = eq(UInt<1>("h01"), UInt<1>("h01")) @[el2_ifu_ic_mem.scala 218:105]
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node _T_83 = and(_T_81, _T_82) @[el2_ifu_ic_mem.scala 218:99]
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node _T_63 = and(_T_62, ic_rd_en_with_debug) @[el2_ifu_ic_mem.scala 217:117]
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node _T_64 = bits(ic_rw_addr_q, 2, 2) @[el2_ifu_ic_mem.scala 214:29]
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node _T_65 = bits(_T_64, 0, 0) @[el2_ifu_ic_mem.scala 214:48]
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node _T_66 = eq(_T_65, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 214:16]
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node _T_67 = eq(UInt<1>("h01"), UInt<1>("h00")) @[el2_ifu_ic_mem.scala 214:63]
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node _T_68 = bits(ic_rw_addr_q, 2, 2) @[el2_ifu_ic_mem.scala 215:42]
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node _T_69 = bits(_T_68, 0, 0) @[el2_ifu_ic_mem.scala 215:62]
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node _T_70 = bits(ic_rw_addr_q, 1, 0) @[el2_ifu_ic_mem.scala 215:86]
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node _T_71 = eq(_T_70, UInt<2>("h03")) @[el2_ifu_ic_mem.scala 215:91]
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node _T_72 = eq(UInt<1>("h01"), UInt<1>("h00")) @[el2_ifu_ic_mem.scala 215:103]
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node _T_73 = and(_T_71, _T_72) @[el2_ifu_ic_mem.scala 215:98]
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node _T_74 = bits(ic_rw_addr_q, 2, 2) @[el2_ifu_ic_mem.scala 216:42]
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node _T_75 = bits(_T_74, 0, 0) @[el2_ifu_ic_mem.scala 216:61]
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node _T_76 = eq(UInt<1>("h01"), UInt<1>("h01")) @[el2_ifu_ic_mem.scala 216:76]
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node _T_77 = bits(ic_rw_addr_q, 2, 2) @[el2_ifu_ic_mem.scala 217:43]
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node _T_78 = eq(_T_77, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 217:30]
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node _T_79 = bits(_T_78, 0, 0) @[el2_ifu_ic_mem.scala 217:63]
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node _T_80 = bits(ic_rw_addr_q, 1, 0) @[el2_ifu_ic_mem.scala 217:87]
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node _T_81 = eq(_T_80, UInt<2>("h03")) @[el2_ifu_ic_mem.scala 217:92]
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node _T_82 = eq(UInt<1>("h01"), UInt<1>("h01")) @[el2_ifu_ic_mem.scala 217:105]
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node _T_83 = and(_T_81, _T_82) @[el2_ifu_ic_mem.scala 217:99]
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node _T_84 = mux(_T_66, _T_67, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_85 = mux(_T_69, _T_73, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_86 = mux(_T_75, _T_76, UInt<1>("h00")) @[Mux.scala 27:72]
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@ -120,140 +119,147 @@ circuit EL2_IC_DATA :
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node _T_90 = or(_T_89, _T_87) @[Mux.scala 27:72]
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wire _T_91 : UInt<1> @[Mux.scala 27:72]
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_T_91 <= _T_90 @[Mux.scala 27:72]
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node _T_92 = and(_T_91, ic_rd_en_with_debug) @[el2_ifu_ic_mem.scala 218:117]
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node _T_92 = and(_T_91, ic_rd_en_with_debug) @[el2_ifu_ic_mem.scala 217:117]
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node ic_b_rden = cat(_T_92, _T_63) @[Cat.scala 29:58]
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node _T_93 = bits(ic_b_rden, 0, 0) @[el2_ifu_ic_mem.scala 219:89]
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node _T_93 = bits(ic_b_rden, 0, 0) @[el2_ifu_ic_mem.scala 218:89]
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node _T_94 = bits(_T_93, 0, 0) @[Bitwise.scala 72:15]
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node ic_b_sb_rden_0 = mux(_T_94, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
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node _T_95 = bits(ic_b_rden, 1, 1) @[el2_ifu_ic_mem.scala 219:89]
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node _T_95 = bits(ic_b_rden, 1, 1) @[el2_ifu_ic_mem.scala 218:89]
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node _T_96 = bits(_T_95, 0, 0) @[Bitwise.scala 72:15]
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node ic_b_sb_rden_1 = mux(_T_96, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
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node _T_97 = bits(ic_b_sb_rden_0, 0, 0) @[el2_ifu_ic_mem.scala 221:21]
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node _T_98 = or(_T_97, io.clk_override) @[el2_ifu_ic_mem.scala 221:25]
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node _T_99 = bits(ic_b_sb_wren_0, 0, 0) @[el2_ifu_ic_mem.scala 221:60]
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node _T_100 = or(_T_98, _T_99) @[el2_ifu_ic_mem.scala 221:43]
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node _T_101 = bits(ic_b_sb_rden_0, 1, 1) @[el2_ifu_ic_mem.scala 221:21]
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node _T_102 = or(_T_101, io.clk_override) @[el2_ifu_ic_mem.scala 221:25]
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node _T_103 = bits(ic_b_sb_wren_0, 1, 1) @[el2_ifu_ic_mem.scala 221:60]
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node _T_104 = or(_T_102, _T_103) @[el2_ifu_ic_mem.scala 221:43]
|
||||
node _T_97 = bits(ic_b_sb_rden_0, 0, 0) @[el2_ifu_ic_mem.scala 220:21]
|
||||
node _T_98 = or(_T_97, io.clk_override) @[el2_ifu_ic_mem.scala 220:25]
|
||||
node _T_99 = bits(ic_b_sb_wren_0, 0, 0) @[el2_ifu_ic_mem.scala 220:60]
|
||||
node _T_100 = or(_T_98, _T_99) @[el2_ifu_ic_mem.scala 220:43]
|
||||
node _T_101 = bits(ic_b_sb_rden_0, 1, 1) @[el2_ifu_ic_mem.scala 220:21]
|
||||
node _T_102 = or(_T_101, io.clk_override) @[el2_ifu_ic_mem.scala 220:25]
|
||||
node _T_103 = bits(ic_b_sb_wren_0, 1, 1) @[el2_ifu_ic_mem.scala 220:60]
|
||||
node _T_104 = or(_T_102, _T_103) @[el2_ifu_ic_mem.scala 220:43]
|
||||
node ic_bank_way_clken_0 = cat(_T_100, _T_104) @[Cat.scala 29:58]
|
||||
node _T_105 = bits(ic_b_sb_rden_1, 0, 0) @[el2_ifu_ic_mem.scala 221:21]
|
||||
node _T_106 = or(_T_105, io.clk_override) @[el2_ifu_ic_mem.scala 221:25]
|
||||
node _T_107 = bits(ic_b_sb_wren_1, 0, 0) @[el2_ifu_ic_mem.scala 221:60]
|
||||
node _T_108 = or(_T_106, _T_107) @[el2_ifu_ic_mem.scala 221:43]
|
||||
node _T_109 = bits(ic_b_sb_rden_1, 1, 1) @[el2_ifu_ic_mem.scala 221:21]
|
||||
node _T_110 = or(_T_109, io.clk_override) @[el2_ifu_ic_mem.scala 221:25]
|
||||
node _T_111 = bits(ic_b_sb_wren_1, 1, 1) @[el2_ifu_ic_mem.scala 221:60]
|
||||
node _T_112 = or(_T_110, _T_111) @[el2_ifu_ic_mem.scala 221:43]
|
||||
node _T_105 = bits(ic_b_sb_rden_1, 0, 0) @[el2_ifu_ic_mem.scala 220:21]
|
||||
node _T_106 = or(_T_105, io.clk_override) @[el2_ifu_ic_mem.scala 220:25]
|
||||
node _T_107 = bits(ic_b_sb_wren_1, 0, 0) @[el2_ifu_ic_mem.scala 220:60]
|
||||
node _T_108 = or(_T_106, _T_107) @[el2_ifu_ic_mem.scala 220:43]
|
||||
node _T_109 = bits(ic_b_sb_rden_1, 1, 1) @[el2_ifu_ic_mem.scala 220:21]
|
||||
node _T_110 = or(_T_109, io.clk_override) @[el2_ifu_ic_mem.scala 220:25]
|
||||
node _T_111 = bits(ic_b_sb_wren_1, 1, 1) @[el2_ifu_ic_mem.scala 220:60]
|
||||
node _T_112 = or(_T_110, _T_111) @[el2_ifu_ic_mem.scala 220:43]
|
||||
node ic_bank_way_clken_1 = cat(_T_108, _T_112) @[Cat.scala 29:58]
|
||||
node _T_113 = orr(io.ic_wr_en) @[el2_ifu_ic_mem.scala 223:74]
|
||||
node _T_114 = eq(_T_113, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 223:61]
|
||||
node _T_115 = and(io.ic_debug_rd_en, _T_114) @[el2_ifu_ic_mem.scala 223:58]
|
||||
node _T_116 = or(io.ic_rd_en, _T_115) @[el2_ifu_ic_mem.scala 223:38]
|
||||
ic_rd_en_with_debug <= _T_116 @[el2_ifu_ic_mem.scala 223:23]
|
||||
node _T_117 = bits(ic_rw_addr_q, 2, 2) @[el2_ifu_ic_mem.scala 225:37]
|
||||
node _T_118 = bits(ic_rw_addr_q, 1, 0) @[el2_ifu_ic_mem.scala 225:71]
|
||||
node _T_119 = eq(_T_118, UInt<2>("h03")) @[el2_ifu_ic_mem.scala 225:77]
|
||||
node _T_120 = and(_T_117, _T_119) @[el2_ifu_ic_mem.scala 225:56]
|
||||
node _T_121 = and(_T_120, ic_rd_en_with_debug) @[el2_ifu_ic_mem.scala 225:86]
|
||||
node _T_122 = orr(io.ic_wr_en) @[el2_ifu_ic_mem.scala 225:124]
|
||||
node _T_123 = eq(_T_122, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 225:110]
|
||||
node ic_rw_addr_wrap = and(_T_121, _T_123) @[el2_ifu_ic_mem.scala 225:108]
|
||||
node _T_124 = eq(ic_rw_addr_wrap, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 227:40]
|
||||
node _T_125 = bits(_T_124, 0, 0) @[el2_ifu_ic_mem.scala 227:58]
|
||||
node _T_126 = bits(ic_rw_addr_q, 11, 3) @[el2_ifu_ic_mem.scala 227:77]
|
||||
node _T_127 = bits(ic_rw_addr_q, 11, 5) @[el2_ifu_ic_mem.scala 228:21]
|
||||
node _T_128 = bits(ic_rw_addr_q_inc, 4, 3) @[el2_ifu_ic_mem.scala 228:82]
|
||||
node _T_113 = orr(io.ic_wr_en) @[el2_ifu_ic_mem.scala 222:74]
|
||||
node _T_114 = eq(_T_113, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 222:61]
|
||||
node _T_115 = and(io.ic_debug_rd_en, _T_114) @[el2_ifu_ic_mem.scala 222:58]
|
||||
node _T_116 = or(io.ic_rd_en, _T_115) @[el2_ifu_ic_mem.scala 222:38]
|
||||
ic_rd_en_with_debug <= _T_116 @[el2_ifu_ic_mem.scala 222:23]
|
||||
node _T_117 = bits(ic_rw_addr_q, 2, 2) @[el2_ifu_ic_mem.scala 224:37]
|
||||
node _T_118 = bits(ic_rw_addr_q, 1, 0) @[el2_ifu_ic_mem.scala 224:71]
|
||||
node _T_119 = eq(_T_118, UInt<2>("h03")) @[el2_ifu_ic_mem.scala 224:77]
|
||||
node _T_120 = and(_T_117, _T_119) @[el2_ifu_ic_mem.scala 224:56]
|
||||
node _T_121 = and(_T_120, ic_rd_en_with_debug) @[el2_ifu_ic_mem.scala 224:86]
|
||||
node _T_122 = orr(io.ic_wr_en) @[el2_ifu_ic_mem.scala 224:124]
|
||||
node _T_123 = eq(_T_122, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 224:110]
|
||||
node ic_rw_addr_wrap = and(_T_121, _T_123) @[el2_ifu_ic_mem.scala 224:108]
|
||||
node _T_124 = eq(ic_rw_addr_wrap, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 226:40]
|
||||
node _T_125 = bits(_T_124, 0, 0) @[el2_ifu_ic_mem.scala 226:58]
|
||||
node _T_126 = bits(ic_rw_addr_q, 11, 3) @[el2_ifu_ic_mem.scala 226:77]
|
||||
node _T_127 = bits(ic_rw_addr_q, 11, 5) @[el2_ifu_ic_mem.scala 227:21]
|
||||
node _T_128 = bits(ic_rw_addr_q_inc, 4, 3) @[el2_ifu_ic_mem.scala 227:82]
|
||||
node _T_129 = cat(_T_127, _T_128) @[Cat.scala 29:58]
|
||||
node _T_130 = mux(_T_125, _T_126, _T_129) @[el2_ifu_ic_mem.scala 227:38]
|
||||
node _T_131 = bits(ic_rw_addr_q, 11, 3) @[el2_ifu_ic_mem.scala 229:17]
|
||||
wire ic_rw_addr_bank_q : UInt<9>[2] @[el2_ifu_ic_mem.scala 227:34]
|
||||
ic_rw_addr_bank_q[0] <= _T_130 @[el2_ifu_ic_mem.scala 227:34]
|
||||
ic_rw_addr_bank_q[1] <= _T_131 @[el2_ifu_ic_mem.scala 227:34]
|
||||
reg ic_b_rden_ff : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ic_mem.scala 234:29]
|
||||
ic_b_rden_ff <= ic_b_rden @[el2_ifu_ic_mem.scala 234:29]
|
||||
node _T_132 = bits(ic_rw_addr_q, 4, 0) @[el2_ifu_ic_mem.scala 235:43]
|
||||
reg ic_rw_addr_ff : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ic_mem.scala 235:30]
|
||||
ic_rw_addr_ff <= _T_132 @[el2_ifu_ic_mem.scala 235:30]
|
||||
reg ic_debug_rd_way_en_ff : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ic_mem.scala 236:38]
|
||||
ic_debug_rd_way_en_ff <= ic_debug_rd_way_en @[el2_ifu_ic_mem.scala 236:38]
|
||||
reg ic_debug_rd_en_ff : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ic_mem.scala 237:34]
|
||||
ic_debug_rd_en_ff <= io.ic_debug_rd_en @[el2_ifu_ic_mem.scala 237:34]
|
||||
node _T_133 = bits(ic_rw_addr_ff, 4, 2) @[el2_ifu_ic_mem.scala 239:43]
|
||||
node _T_130 = mux(_T_125, _T_126, _T_129) @[el2_ifu_ic_mem.scala 226:38]
|
||||
node _T_131 = bits(ic_rw_addr_q, 11, 3) @[el2_ifu_ic_mem.scala 228:17]
|
||||
wire ic_rw_addr_bank_q : UInt<9>[2] @[el2_ifu_ic_mem.scala 226:34]
|
||||
ic_rw_addr_bank_q[0] <= _T_130 @[el2_ifu_ic_mem.scala 226:34]
|
||||
ic_rw_addr_bank_q[1] <= _T_131 @[el2_ifu_ic_mem.scala 226:34]
|
||||
reg ic_b_rden_ff : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ic_mem.scala 233:29]
|
||||
ic_b_rden_ff <= ic_b_rden @[el2_ifu_ic_mem.scala 233:29]
|
||||
node _T_132 = bits(ic_rw_addr_q, 4, 0) @[el2_ifu_ic_mem.scala 234:43]
|
||||
reg ic_rw_addr_ff : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ic_mem.scala 234:30]
|
||||
ic_rw_addr_ff <= _T_132 @[el2_ifu_ic_mem.scala 234:30]
|
||||
reg ic_debug_rd_way_en_ff : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ic_mem.scala 235:38]
|
||||
ic_debug_rd_way_en_ff <= ic_debug_rd_way_en @[el2_ifu_ic_mem.scala 235:38]
|
||||
reg ic_debug_rd_en_ff : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ic_mem.scala 236:34]
|
||||
ic_debug_rd_en_ff <= io.ic_debug_rd_en @[el2_ifu_ic_mem.scala 236:34]
|
||||
node _T_133 = bits(ic_rw_addr_ff, 4, 2) @[el2_ifu_ic_mem.scala 238:43]
|
||||
node _T_134 = mux(UInt<1>("h01"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
|
||||
node ic_cacheline_wrap_ff = eq(_T_133, _T_134) @[el2_ifu_ic_mem.scala 239:84]
|
||||
io.test <= ic_rw_addr_bank_q[1] @[el2_ifu_ic_mem.scala 241:11]
|
||||
cmem data_mem : UInt<71>[2][2][512] @[el2_ifu_ic_mem.scala 246:21]
|
||||
node _T_135 = bits(ic_b_sb_wren_0, 0, 0) @[el2_ifu_ic_mem.scala 248:26]
|
||||
node _T_136 = bits(ic_bank_way_clken_0, 0, 0) @[el2_ifu_ic_mem.scala 248:50]
|
||||
node _T_137 = and(_T_135, _T_136) @[el2_ifu_ic_mem.scala 248:29]
|
||||
node _T_138 = bits(_T_137, 0, 0) @[el2_ifu_ic_mem.scala 248:55]
|
||||
when _T_138 : @[el2_ifu_ic_mem.scala 248:62]
|
||||
infer mport _T_139 = data_mem[ic_rw_addr_bank_q[0]], clock @[el2_ifu_ic_mem.scala 249:15]
|
||||
_T_139[0][0] <= io.test_in @[el2_ifu_ic_mem.scala 249:44]
|
||||
skip @[el2_ifu_ic_mem.scala 248:62]
|
||||
else : @[el2_ifu_ic_mem.scala 250:69]
|
||||
node _T_140 = bits(ic_b_sb_wren_0, 0, 0) @[el2_ifu_ic_mem.scala 250:33]
|
||||
node _T_141 = eq(_T_140, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 250:17]
|
||||
node _T_142 = bits(ic_bank_way_clken_0, 0, 0) @[el2_ifu_ic_mem.scala 250:57]
|
||||
node _T_143 = and(_T_141, _T_142) @[el2_ifu_ic_mem.scala 250:36]
|
||||
node _T_144 = bits(_T_143, 0, 0) @[el2_ifu_ic_mem.scala 250:62]
|
||||
when _T_144 : @[el2_ifu_ic_mem.scala 250:69]
|
||||
infer mport _T_145 = data_mem[ic_rw_addr_bank_q[0]], clock @[el2_ifu_ic_mem.scala 251:26]
|
||||
io.test <= _T_145[0][0] @[el2_ifu_ic_mem.scala 251:15]
|
||||
skip @[el2_ifu_ic_mem.scala 250:69]
|
||||
node _T_146 = bits(ic_b_sb_wren_1, 0, 0) @[el2_ifu_ic_mem.scala 248:26]
|
||||
node _T_147 = bits(ic_bank_way_clken_1, 0, 0) @[el2_ifu_ic_mem.scala 248:50]
|
||||
node _T_148 = and(_T_146, _T_147) @[el2_ifu_ic_mem.scala 248:29]
|
||||
node _T_149 = bits(_T_148, 0, 0) @[el2_ifu_ic_mem.scala 248:55]
|
||||
when _T_149 : @[el2_ifu_ic_mem.scala 248:62]
|
||||
infer mport _T_150 = data_mem[ic_rw_addr_bank_q[1]], clock @[el2_ifu_ic_mem.scala 249:15]
|
||||
_T_150[1][0] <= io.test_in @[el2_ifu_ic_mem.scala 249:44]
|
||||
skip @[el2_ifu_ic_mem.scala 248:62]
|
||||
else : @[el2_ifu_ic_mem.scala 250:69]
|
||||
node _T_151 = bits(ic_b_sb_wren_1, 0, 0) @[el2_ifu_ic_mem.scala 250:33]
|
||||
node _T_152 = eq(_T_151, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 250:17]
|
||||
node _T_153 = bits(ic_bank_way_clken_1, 0, 0) @[el2_ifu_ic_mem.scala 250:57]
|
||||
node _T_154 = and(_T_152, _T_153) @[el2_ifu_ic_mem.scala 250:36]
|
||||
node _T_155 = bits(_T_154, 0, 0) @[el2_ifu_ic_mem.scala 250:62]
|
||||
when _T_155 : @[el2_ifu_ic_mem.scala 250:69]
|
||||
infer mport _T_156 = data_mem[ic_rw_addr_bank_q[1]], clock @[el2_ifu_ic_mem.scala 251:26]
|
||||
io.test <= _T_156[1][0] @[el2_ifu_ic_mem.scala 251:15]
|
||||
skip @[el2_ifu_ic_mem.scala 250:69]
|
||||
node _T_157 = bits(ic_b_sb_wren_0, 1, 1) @[el2_ifu_ic_mem.scala 248:26]
|
||||
node _T_158 = bits(ic_bank_way_clken_0, 1, 1) @[el2_ifu_ic_mem.scala 248:50]
|
||||
node _T_159 = and(_T_157, _T_158) @[el2_ifu_ic_mem.scala 248:29]
|
||||
node _T_160 = bits(_T_159, 0, 0) @[el2_ifu_ic_mem.scala 248:55]
|
||||
when _T_160 : @[el2_ifu_ic_mem.scala 248:62]
|
||||
infer mport _T_161 = data_mem[ic_rw_addr_bank_q[0]], clock @[el2_ifu_ic_mem.scala 249:15]
|
||||
_T_161[0][1] <= io.test_in @[el2_ifu_ic_mem.scala 249:44]
|
||||
skip @[el2_ifu_ic_mem.scala 248:62]
|
||||
else : @[el2_ifu_ic_mem.scala 250:69]
|
||||
node _T_162 = bits(ic_b_sb_wren_0, 1, 1) @[el2_ifu_ic_mem.scala 250:33]
|
||||
node _T_163 = eq(_T_162, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 250:17]
|
||||
node _T_164 = bits(ic_bank_way_clken_0, 1, 1) @[el2_ifu_ic_mem.scala 250:57]
|
||||
node _T_165 = and(_T_163, _T_164) @[el2_ifu_ic_mem.scala 250:36]
|
||||
node _T_166 = bits(_T_165, 0, 0) @[el2_ifu_ic_mem.scala 250:62]
|
||||
when _T_166 : @[el2_ifu_ic_mem.scala 250:69]
|
||||
infer mport _T_167 = data_mem[ic_rw_addr_bank_q[0]], clock @[el2_ifu_ic_mem.scala 251:26]
|
||||
io.test <= _T_167[0][1] @[el2_ifu_ic_mem.scala 251:15]
|
||||
skip @[el2_ifu_ic_mem.scala 250:69]
|
||||
node _T_168 = bits(ic_b_sb_wren_1, 1, 1) @[el2_ifu_ic_mem.scala 248:26]
|
||||
node _T_169 = bits(ic_bank_way_clken_1, 1, 1) @[el2_ifu_ic_mem.scala 248:50]
|
||||
node _T_170 = and(_T_168, _T_169) @[el2_ifu_ic_mem.scala 248:29]
|
||||
node _T_171 = bits(_T_170, 0, 0) @[el2_ifu_ic_mem.scala 248:55]
|
||||
when _T_171 : @[el2_ifu_ic_mem.scala 248:62]
|
||||
infer mport _T_172 = data_mem[ic_rw_addr_bank_q[1]], clock @[el2_ifu_ic_mem.scala 249:15]
|
||||
_T_172[1][1] <= io.test_in @[el2_ifu_ic_mem.scala 249:44]
|
||||
skip @[el2_ifu_ic_mem.scala 248:62]
|
||||
else : @[el2_ifu_ic_mem.scala 250:69]
|
||||
node _T_173 = bits(ic_b_sb_wren_1, 1, 1) @[el2_ifu_ic_mem.scala 250:33]
|
||||
node _T_174 = eq(_T_173, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 250:17]
|
||||
node _T_175 = bits(ic_bank_way_clken_1, 1, 1) @[el2_ifu_ic_mem.scala 250:57]
|
||||
node _T_176 = and(_T_174, _T_175) @[el2_ifu_ic_mem.scala 250:36]
|
||||
node _T_177 = bits(_T_176, 0, 0) @[el2_ifu_ic_mem.scala 250:62]
|
||||
when _T_177 : @[el2_ifu_ic_mem.scala 250:69]
|
||||
infer mport _T_178 = data_mem[ic_rw_addr_bank_q[1]], clock @[el2_ifu_ic_mem.scala 251:26]
|
||||
io.test <= _T_178[1][1] @[el2_ifu_ic_mem.scala 251:15]
|
||||
skip @[el2_ifu_ic_mem.scala 250:69]
|
||||
node ic_cacheline_wrap_ff = eq(_T_133, _T_134) @[el2_ifu_ic_mem.scala 238:84]
|
||||
cmem data_mem : UInt<71>[2][2][512] @[el2_ifu_ic_mem.scala 243:21]
|
||||
node _T_135 = bits(ic_b_sb_wren_0, 0, 0) @[el2_ifu_ic_mem.scala 245:73]
|
||||
node _T_136 = bits(ic_bank_way_clken_0, 0, 0) @[el2_ifu_ic_mem.scala 246:83]
|
||||
node _T_137 = bits(ic_b_sb_wren_0, 0, 0) @[el2_ifu_ic_mem.scala 247:26]
|
||||
node _T_138 = bits(ic_bank_way_clken_0, 0, 0) @[el2_ifu_ic_mem.scala 247:52]
|
||||
node _T_139 = and(_T_137, _T_138) @[el2_ifu_ic_mem.scala 247:30]
|
||||
node _T_140 = bits(_T_139, 0, 0) @[el2_ifu_ic_mem.scala 247:57]
|
||||
when _T_140 : @[el2_ifu_ic_mem.scala 247:64]
|
||||
infer mport _T_141 = data_mem[ic_rw_addr_bank_q[0]], clock @[el2_ifu_ic_mem.scala 248:15]
|
||||
_T_141[0][0] <= io.test_in @[el2_ifu_ic_mem.scala 248:44]
|
||||
skip @[el2_ifu_ic_mem.scala 247:64]
|
||||
else : @[el2_ifu_ic_mem.scala 249:69]
|
||||
node _T_142 = bits(ic_b_sb_wren_0, 0, 0) @[el2_ifu_ic_mem.scala 249:33]
|
||||
node _T_143 = eq(_T_142, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 249:17]
|
||||
node _T_144 = bits(ic_bank_way_clken_0, 0, 0) @[el2_ifu_ic_mem.scala 249:57]
|
||||
node _T_145 = and(_T_143, _T_144) @[el2_ifu_ic_mem.scala 249:36]
|
||||
node _T_146 = bits(_T_145, 0, 0) @[el2_ifu_ic_mem.scala 249:62]
|
||||
when _T_146 : @[el2_ifu_ic_mem.scala 249:69]
|
||||
infer mport _T_147 = data_mem[ic_rw_addr_bank_q[0]], clock @[el2_ifu_ic_mem.scala 250:26]
|
||||
io.test <= _T_147[0][0] @[el2_ifu_ic_mem.scala 250:15]
|
||||
skip @[el2_ifu_ic_mem.scala 249:69]
|
||||
node _T_148 = bits(ic_b_sb_wren_1, 0, 0) @[el2_ifu_ic_mem.scala 245:73]
|
||||
node _T_149 = bits(ic_bank_way_clken_1, 0, 0) @[el2_ifu_ic_mem.scala 246:83]
|
||||
node _T_150 = bits(ic_b_sb_wren_1, 0, 0) @[el2_ifu_ic_mem.scala 247:26]
|
||||
node _T_151 = bits(ic_bank_way_clken_1, 0, 0) @[el2_ifu_ic_mem.scala 247:52]
|
||||
node _T_152 = and(_T_150, _T_151) @[el2_ifu_ic_mem.scala 247:30]
|
||||
node _T_153 = bits(_T_152, 0, 0) @[el2_ifu_ic_mem.scala 247:57]
|
||||
when _T_153 : @[el2_ifu_ic_mem.scala 247:64]
|
||||
infer mport _T_154 = data_mem[ic_rw_addr_bank_q[1]], clock @[el2_ifu_ic_mem.scala 248:15]
|
||||
_T_154[1][0] <= io.test_in @[el2_ifu_ic_mem.scala 248:44]
|
||||
skip @[el2_ifu_ic_mem.scala 247:64]
|
||||
else : @[el2_ifu_ic_mem.scala 249:69]
|
||||
node _T_155 = bits(ic_b_sb_wren_1, 0, 0) @[el2_ifu_ic_mem.scala 249:33]
|
||||
node _T_156 = eq(_T_155, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 249:17]
|
||||
node _T_157 = bits(ic_bank_way_clken_1, 0, 0) @[el2_ifu_ic_mem.scala 249:57]
|
||||
node _T_158 = and(_T_156, _T_157) @[el2_ifu_ic_mem.scala 249:36]
|
||||
node _T_159 = bits(_T_158, 0, 0) @[el2_ifu_ic_mem.scala 249:62]
|
||||
when _T_159 : @[el2_ifu_ic_mem.scala 249:69]
|
||||
infer mport _T_160 = data_mem[ic_rw_addr_bank_q[1]], clock @[el2_ifu_ic_mem.scala 250:26]
|
||||
io.test <= _T_160[1][0] @[el2_ifu_ic_mem.scala 250:15]
|
||||
skip @[el2_ifu_ic_mem.scala 249:69]
|
||||
node _T_161 = bits(ic_b_sb_wren_0, 1, 1) @[el2_ifu_ic_mem.scala 245:73]
|
||||
node _T_162 = bits(ic_bank_way_clken_0, 1, 1) @[el2_ifu_ic_mem.scala 246:83]
|
||||
node _T_163 = bits(ic_b_sb_wren_0, 1, 1) @[el2_ifu_ic_mem.scala 247:26]
|
||||
node _T_164 = bits(ic_bank_way_clken_0, 1, 1) @[el2_ifu_ic_mem.scala 247:52]
|
||||
node _T_165 = and(_T_163, _T_164) @[el2_ifu_ic_mem.scala 247:30]
|
||||
node _T_166 = bits(_T_165, 0, 0) @[el2_ifu_ic_mem.scala 247:57]
|
||||
when _T_166 : @[el2_ifu_ic_mem.scala 247:64]
|
||||
infer mport _T_167 = data_mem[ic_rw_addr_bank_q[0]], clock @[el2_ifu_ic_mem.scala 248:15]
|
||||
_T_167[0][1] <= io.test_in @[el2_ifu_ic_mem.scala 248:44]
|
||||
skip @[el2_ifu_ic_mem.scala 247:64]
|
||||
else : @[el2_ifu_ic_mem.scala 249:69]
|
||||
node _T_168 = bits(ic_b_sb_wren_0, 1, 1) @[el2_ifu_ic_mem.scala 249:33]
|
||||
node _T_169 = eq(_T_168, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 249:17]
|
||||
node _T_170 = bits(ic_bank_way_clken_0, 1, 1) @[el2_ifu_ic_mem.scala 249:57]
|
||||
node _T_171 = and(_T_169, _T_170) @[el2_ifu_ic_mem.scala 249:36]
|
||||
node _T_172 = bits(_T_171, 0, 0) @[el2_ifu_ic_mem.scala 249:62]
|
||||
when _T_172 : @[el2_ifu_ic_mem.scala 249:69]
|
||||
infer mport _T_173 = data_mem[ic_rw_addr_bank_q[0]], clock @[el2_ifu_ic_mem.scala 250:26]
|
||||
io.test <= _T_173[0][1] @[el2_ifu_ic_mem.scala 250:15]
|
||||
skip @[el2_ifu_ic_mem.scala 249:69]
|
||||
node _T_174 = bits(ic_b_sb_wren_1, 1, 1) @[el2_ifu_ic_mem.scala 245:73]
|
||||
node _T_175 = bits(ic_bank_way_clken_1, 1, 1) @[el2_ifu_ic_mem.scala 246:83]
|
||||
node _T_176 = bits(ic_b_sb_wren_1, 1, 1) @[el2_ifu_ic_mem.scala 247:26]
|
||||
node _T_177 = bits(ic_bank_way_clken_1, 1, 1) @[el2_ifu_ic_mem.scala 247:52]
|
||||
node _T_178 = and(_T_176, _T_177) @[el2_ifu_ic_mem.scala 247:30]
|
||||
node _T_179 = bits(_T_178, 0, 0) @[el2_ifu_ic_mem.scala 247:57]
|
||||
when _T_179 : @[el2_ifu_ic_mem.scala 247:64]
|
||||
infer mport _T_180 = data_mem[ic_rw_addr_bank_q[1]], clock @[el2_ifu_ic_mem.scala 248:15]
|
||||
_T_180[1][1] <= io.test_in @[el2_ifu_ic_mem.scala 248:44]
|
||||
skip @[el2_ifu_ic_mem.scala 247:64]
|
||||
else : @[el2_ifu_ic_mem.scala 249:69]
|
||||
node _T_181 = bits(ic_b_sb_wren_1, 1, 1) @[el2_ifu_ic_mem.scala 249:33]
|
||||
node _T_182 = eq(_T_181, UInt<1>("h00")) @[el2_ifu_ic_mem.scala 249:17]
|
||||
node _T_183 = bits(ic_bank_way_clken_1, 1, 1) @[el2_ifu_ic_mem.scala 249:57]
|
||||
node _T_184 = and(_T_182, _T_183) @[el2_ifu_ic_mem.scala 249:36]
|
||||
node _T_185 = bits(_T_184, 0, 0) @[el2_ifu_ic_mem.scala 249:62]
|
||||
when _T_185 : @[el2_ifu_ic_mem.scala 249:69]
|
||||
infer mport _T_186 = data_mem[ic_rw_addr_bank_q[1]], clock @[el2_ifu_ic_mem.scala 250:26]
|
||||
io.test <= _T_186[1][1] @[el2_ifu_ic_mem.scala 250:15]
|
||||
skip @[el2_ifu_ic_mem.scala 249:69]
|
||||
|
||||
|
|
|
|||
536
EL2_IC_DATA.v
536
EL2_IC_DATA.v
|
|
@ -30,106 +30,106 @@ module EL2_IC_DATA(
|
|||
reg [95:0] _RAND_2;
|
||||
reg [95:0] _RAND_3;
|
||||
`endif // RANDOMIZE_MEM_INIT
|
||||
reg [70:0] data_mem_0_0 [0:511]; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire [70:0] data_mem_0_0__T_145_data; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire [8:0] data_mem_0_0__T_145_addr; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire [70:0] data_mem_0_0__T_156_data; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire [8:0] data_mem_0_0__T_156_addr; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire [70:0] data_mem_0_0__T_167_data; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire [8:0] data_mem_0_0__T_167_addr; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire [70:0] data_mem_0_0__T_178_data; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire [8:0] data_mem_0_0__T_178_addr; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire [70:0] data_mem_0_0__T_139_data; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire [8:0] data_mem_0_0__T_139_addr; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire data_mem_0_0__T_139_mask; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire data_mem_0_0__T_139_en; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire [70:0] data_mem_0_0__T_150_data; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire [8:0] data_mem_0_0__T_150_addr; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire data_mem_0_0__T_150_mask; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire data_mem_0_0__T_150_en; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire [70:0] data_mem_0_0__T_161_data; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire [8:0] data_mem_0_0__T_161_addr; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire data_mem_0_0__T_161_mask; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire data_mem_0_0__T_161_en; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire [70:0] data_mem_0_0__T_172_data; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire [8:0] data_mem_0_0__T_172_addr; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire data_mem_0_0__T_172_mask; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire data_mem_0_0__T_172_en; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
reg [70:0] data_mem_0_1 [0:511]; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire [70:0] data_mem_0_1__T_145_data; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire [8:0] data_mem_0_1__T_145_addr; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire [70:0] data_mem_0_1__T_156_data; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire [8:0] data_mem_0_1__T_156_addr; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire [70:0] data_mem_0_1__T_167_data; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire [8:0] data_mem_0_1__T_167_addr; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire [70:0] data_mem_0_1__T_178_data; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire [8:0] data_mem_0_1__T_178_addr; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire [70:0] data_mem_0_1__T_139_data; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire [8:0] data_mem_0_1__T_139_addr; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire data_mem_0_1__T_139_mask; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire data_mem_0_1__T_139_en; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire [70:0] data_mem_0_1__T_150_data; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire [8:0] data_mem_0_1__T_150_addr; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire data_mem_0_1__T_150_mask; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire data_mem_0_1__T_150_en; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire [70:0] data_mem_0_1__T_161_data; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire [8:0] data_mem_0_1__T_161_addr; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire data_mem_0_1__T_161_mask; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire data_mem_0_1__T_161_en; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire [70:0] data_mem_0_1__T_172_data; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire [8:0] data_mem_0_1__T_172_addr; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire data_mem_0_1__T_172_mask; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire data_mem_0_1__T_172_en; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
reg [70:0] data_mem_1_0 [0:511]; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire [70:0] data_mem_1_0__T_145_data; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire [8:0] data_mem_1_0__T_145_addr; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire [70:0] data_mem_1_0__T_156_data; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire [8:0] data_mem_1_0__T_156_addr; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire [70:0] data_mem_1_0__T_167_data; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire [8:0] data_mem_1_0__T_167_addr; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire [70:0] data_mem_1_0__T_178_data; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire [8:0] data_mem_1_0__T_178_addr; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire [70:0] data_mem_1_0__T_139_data; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire [8:0] data_mem_1_0__T_139_addr; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire data_mem_1_0__T_139_mask; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire data_mem_1_0__T_139_en; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire [70:0] data_mem_1_0__T_150_data; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire [8:0] data_mem_1_0__T_150_addr; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire data_mem_1_0__T_150_mask; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire data_mem_1_0__T_150_en; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire [70:0] data_mem_1_0__T_161_data; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire [8:0] data_mem_1_0__T_161_addr; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire data_mem_1_0__T_161_mask; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire data_mem_1_0__T_161_en; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire [70:0] data_mem_1_0__T_172_data; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire [8:0] data_mem_1_0__T_172_addr; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire data_mem_1_0__T_172_mask; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire data_mem_1_0__T_172_en; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
reg [70:0] data_mem_1_1 [0:511]; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire [70:0] data_mem_1_1__T_145_data; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire [8:0] data_mem_1_1__T_145_addr; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire [70:0] data_mem_1_1__T_156_data; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire [8:0] data_mem_1_1__T_156_addr; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire [70:0] data_mem_1_1__T_167_data; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire [8:0] data_mem_1_1__T_167_addr; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire [70:0] data_mem_1_1__T_178_data; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire [8:0] data_mem_1_1__T_178_addr; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire [70:0] data_mem_1_1__T_139_data; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire [8:0] data_mem_1_1__T_139_addr; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire data_mem_1_1__T_139_mask; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire data_mem_1_1__T_139_en; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire [70:0] data_mem_1_1__T_150_data; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire [8:0] data_mem_1_1__T_150_addr; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire data_mem_1_1__T_150_mask; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire data_mem_1_1__T_150_en; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire [70:0] data_mem_1_1__T_161_data; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire [8:0] data_mem_1_1__T_161_addr; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire data_mem_1_1__T_161_mask; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire data_mem_1_1__T_161_en; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire [70:0] data_mem_1_1__T_172_data; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire [8:0] data_mem_1_1__T_172_addr; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire data_mem_1_1__T_172_mask; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire data_mem_1_1__T_172_en; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
reg [70:0] data_mem_0_0 [0:511]; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_0_0__T_147_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_0_0__T_147_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_0_0__T_160_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_0_0__T_160_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_0_0__T_173_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_0_0__T_173_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_0_0__T_186_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_0_0__T_186_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_0_0__T_141_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_0_0__T_141_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_0_0__T_141_mask; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_0_0__T_141_en; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_0_0__T_154_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_0_0__T_154_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_0_0__T_154_mask; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_0_0__T_154_en; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_0_0__T_167_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_0_0__T_167_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_0_0__T_167_mask; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_0_0__T_167_en; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_0_0__T_180_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_0_0__T_180_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_0_0__T_180_mask; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_0_0__T_180_en; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
reg [70:0] data_mem_0_1 [0:511]; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_0_1__T_147_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_0_1__T_147_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_0_1__T_160_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_0_1__T_160_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_0_1__T_173_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_0_1__T_173_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_0_1__T_186_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_0_1__T_186_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_0_1__T_141_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_0_1__T_141_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_0_1__T_141_mask; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_0_1__T_141_en; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_0_1__T_154_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_0_1__T_154_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_0_1__T_154_mask; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_0_1__T_154_en; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_0_1__T_167_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_0_1__T_167_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_0_1__T_167_mask; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_0_1__T_167_en; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_0_1__T_180_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_0_1__T_180_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_0_1__T_180_mask; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_0_1__T_180_en; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
reg [70:0] data_mem_1_0 [0:511]; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_1_0__T_147_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_1_0__T_147_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_1_0__T_160_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_1_0__T_160_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_1_0__T_173_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_1_0__T_173_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_1_0__T_186_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_1_0__T_186_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_1_0__T_141_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_1_0__T_141_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_1_0__T_141_mask; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_1_0__T_141_en; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_1_0__T_154_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_1_0__T_154_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_1_0__T_154_mask; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_1_0__T_154_en; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_1_0__T_167_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_1_0__T_167_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_1_0__T_167_mask; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_1_0__T_167_en; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_1_0__T_180_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_1_0__T_180_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_1_0__T_180_mask; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_1_0__T_180_en; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
reg [70:0] data_mem_1_1 [0:511]; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_1_1__T_147_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_1_1__T_147_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_1_1__T_160_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_1_1__T_160_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_1_1__T_173_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_1_1__T_173_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_1_1__T_186_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_1_1__T_186_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_1_1__T_141_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_1_1__T_141_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_1_1__T_141_mask; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_1_1__T_141_en; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_1_1__T_154_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_1_1__T_154_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_1_1__T_154_mask; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_1_1__T_154_en; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_1_1__T_167_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_1_1__T_167_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_1_1__T_167_mask; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_1_1__T_167_en; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [70:0] data_mem_1_1__T_180_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire [8:0] data_mem_1_1__T_180_addr; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_1_1__T_180_mask; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire data_mem_1_1__T_180_en; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
wire _T = ~io_ic_debug_tag_array; // @[el2_ifu_ic_mem.scala 200:70]
|
||||
wire _T_5 = io_ic_debug_wr_en & _T; // @[el2_ifu_ic_mem.scala 201:68]
|
||||
wire [1:0] _T_7 = {_T_5,_T_5}; // @[Cat.scala 29:58]
|
||||
|
|
@ -138,162 +138,162 @@ module EL2_IC_DATA(
|
|||
wire [10:0] _T_10 = {io_ic_debug_addr,2'h0}; // @[Cat.scala 29:58]
|
||||
wire [11:0] ic_rw_addr_q = _T_8 ? {{1'd0}, _T_10} : io_ic_rw_addr; // @[el2_ifu_ic_mem.scala 206:25]
|
||||
wire [8:0] ic_rw_addr_q_inc = ic_rw_addr_q[11:3] + 9'h1; // @[el2_ifu_ic_mem.scala 208:79]
|
||||
wire _T_14 = ~io_ic_debug_addr[0]; // @[el2_ifu_ic_mem.scala 211:113]
|
||||
wire _T_14 = ~io_ic_debug_addr[0]; // @[el2_ifu_ic_mem.scala 210:113]
|
||||
wire [1:0] _T_16 = _T_14 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
||||
wire [1:0] _T_17 = ic_debug_wr_way_en & _T_16; // @[el2_ifu_ic_mem.scala 211:38]
|
||||
wire [1:0] ic_b_sb_wren_0 = io_ic_wr_en | _T_17; // @[el2_ifu_ic_mem.scala 211:17]
|
||||
wire [1:0] _T_17 = ic_debug_wr_way_en & _T_16; // @[el2_ifu_ic_mem.scala 210:38]
|
||||
wire [1:0] ic_b_sb_wren_0 = io_ic_wr_en | _T_17; // @[el2_ifu_ic_mem.scala 210:17]
|
||||
wire [1:0] _T_21 = io_ic_debug_addr[0] ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
||||
wire [1:0] _T_22 = ic_debug_wr_way_en & _T_21; // @[el2_ifu_ic_mem.scala 211:38]
|
||||
wire [1:0] ic_b_sb_wren_1 = io_ic_wr_en | _T_22; // @[el2_ifu_ic_mem.scala 211:17]
|
||||
wire _T_37 = ~ic_rw_addr_q[2]; // @[el2_ifu_ic_mem.scala 215:16]
|
||||
wire _T_42 = ic_rw_addr_q[1:0] == 2'h3; // @[el2_ifu_ic_mem.scala 216:91]
|
||||
wire [1:0] _T_22 = ic_debug_wr_way_en & _T_21; // @[el2_ifu_ic_mem.scala 210:38]
|
||||
wire [1:0] ic_b_sb_wren_1 = io_ic_wr_en | _T_22; // @[el2_ifu_ic_mem.scala 210:17]
|
||||
wire _T_37 = ~ic_rw_addr_q[2]; // @[el2_ifu_ic_mem.scala 214:16]
|
||||
wire _T_42 = ic_rw_addr_q[1:0] == 2'h3; // @[el2_ifu_ic_mem.scala 215:91]
|
||||
wire _T_56 = ic_rw_addr_q[2] & _T_42; // @[Mux.scala 27:72]
|
||||
wire _T_59 = _T_37 | _T_56; // @[Mux.scala 27:72]
|
||||
wire _T_113 = |io_ic_wr_en; // @[el2_ifu_ic_mem.scala 223:74]
|
||||
wire _T_114 = ~_T_113; // @[el2_ifu_ic_mem.scala 223:61]
|
||||
wire _T_115 = io_ic_debug_rd_en & _T_114; // @[el2_ifu_ic_mem.scala 223:58]
|
||||
wire ic_rd_en_with_debug = io_ic_rd_en | _T_115; // @[el2_ifu_ic_mem.scala 223:38]
|
||||
wire _T_63 = _T_59 & ic_rd_en_with_debug; // @[el2_ifu_ic_mem.scala 218:117]
|
||||
wire _T_113 = |io_ic_wr_en; // @[el2_ifu_ic_mem.scala 222:74]
|
||||
wire _T_114 = ~_T_113; // @[el2_ifu_ic_mem.scala 222:61]
|
||||
wire _T_115 = io_ic_debug_rd_en & _T_114; // @[el2_ifu_ic_mem.scala 222:58]
|
||||
wire ic_rd_en_with_debug = io_ic_rd_en | _T_115; // @[el2_ifu_ic_mem.scala 222:38]
|
||||
wire _T_63 = _T_59 & ic_rd_en_with_debug; // @[el2_ifu_ic_mem.scala 217:117]
|
||||
wire _T_87 = _T_37 & _T_42; // @[Mux.scala 27:72]
|
||||
wire _T_90 = ic_rw_addr_q[2] | _T_87; // @[Mux.scala 27:72]
|
||||
wire _T_92 = _T_90 & ic_rd_en_with_debug; // @[el2_ifu_ic_mem.scala 218:117]
|
||||
wire _T_92 = _T_90 & ic_rd_en_with_debug; // @[el2_ifu_ic_mem.scala 217:117]
|
||||
wire [1:0] ic_b_rden = {_T_92,_T_63}; // @[Cat.scala 29:58]
|
||||
wire [1:0] ic_b_sb_rden_0 = ic_b_rden[0] ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
||||
wire [1:0] ic_b_sb_rden_1 = ic_b_rden[1] ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
|
||||
wire _T_98 = ic_b_sb_rden_0[0] | io_clk_override; // @[el2_ifu_ic_mem.scala 221:25]
|
||||
wire _T_100 = _T_98 | ic_b_sb_wren_0[0]; // @[el2_ifu_ic_mem.scala 221:43]
|
||||
wire _T_102 = ic_b_sb_rden_0[1] | io_clk_override; // @[el2_ifu_ic_mem.scala 221:25]
|
||||
wire _T_104 = _T_102 | ic_b_sb_wren_0[1]; // @[el2_ifu_ic_mem.scala 221:43]
|
||||
wire _T_98 = ic_b_sb_rden_0[0] | io_clk_override; // @[el2_ifu_ic_mem.scala 220:25]
|
||||
wire _T_100 = _T_98 | ic_b_sb_wren_0[0]; // @[el2_ifu_ic_mem.scala 220:43]
|
||||
wire _T_102 = ic_b_sb_rden_0[1] | io_clk_override; // @[el2_ifu_ic_mem.scala 220:25]
|
||||
wire _T_104 = _T_102 | ic_b_sb_wren_0[1]; // @[el2_ifu_ic_mem.scala 220:43]
|
||||
wire [1:0] ic_bank_way_clken_0 = {_T_100,_T_104}; // @[Cat.scala 29:58]
|
||||
wire _T_106 = ic_b_sb_rden_1[0] | io_clk_override; // @[el2_ifu_ic_mem.scala 221:25]
|
||||
wire _T_108 = _T_106 | ic_b_sb_wren_1[0]; // @[el2_ifu_ic_mem.scala 221:43]
|
||||
wire _T_110 = ic_b_sb_rden_1[1] | io_clk_override; // @[el2_ifu_ic_mem.scala 221:25]
|
||||
wire _T_112 = _T_110 | ic_b_sb_wren_1[1]; // @[el2_ifu_ic_mem.scala 221:43]
|
||||
wire _T_106 = ic_b_sb_rden_1[0] | io_clk_override; // @[el2_ifu_ic_mem.scala 220:25]
|
||||
wire _T_108 = _T_106 | ic_b_sb_wren_1[0]; // @[el2_ifu_ic_mem.scala 220:43]
|
||||
wire _T_110 = ic_b_sb_rden_1[1] | io_clk_override; // @[el2_ifu_ic_mem.scala 220:25]
|
||||
wire _T_112 = _T_110 | ic_b_sb_wren_1[1]; // @[el2_ifu_ic_mem.scala 220:43]
|
||||
wire [1:0] ic_bank_way_clken_1 = {_T_108,_T_112}; // @[Cat.scala 29:58]
|
||||
wire _T_121 = _T_56 & ic_rd_en_with_debug; // @[el2_ifu_ic_mem.scala 225:86]
|
||||
wire ic_rw_addr_wrap = _T_121 & _T_114; // @[el2_ifu_ic_mem.scala 225:108]
|
||||
wire _T_124 = ~ic_rw_addr_wrap; // @[el2_ifu_ic_mem.scala 227:40]
|
||||
wire _T_121 = _T_56 & ic_rd_en_with_debug; // @[el2_ifu_ic_mem.scala 224:86]
|
||||
wire ic_rw_addr_wrap = _T_121 & _T_114; // @[el2_ifu_ic_mem.scala 224:108]
|
||||
wire _T_124 = ~ic_rw_addr_wrap; // @[el2_ifu_ic_mem.scala 226:40]
|
||||
wire [8:0] _T_129 = {ic_rw_addr_q[11:5],ic_rw_addr_q_inc[4:3]}; // @[Cat.scala 29:58]
|
||||
wire _T_137 = ic_b_sb_wren_0[0] & ic_bank_way_clken_0[0]; // @[el2_ifu_ic_mem.scala 248:29]
|
||||
wire _T_141 = ~ic_b_sb_wren_0[0]; // @[el2_ifu_ic_mem.scala 250:17]
|
||||
wire _T_143 = _T_141 & ic_bank_way_clken_0[0]; // @[el2_ifu_ic_mem.scala 250:36]
|
||||
wire [70:0] _GEN_3 = _T_143 ? data_mem_0_0__T_145_data : {{62'd0}, ic_rw_addr_q[11:3]}; // @[el2_ifu_ic_mem.scala 250:69]
|
||||
wire [70:0] _GEN_13 = _T_137 ? {{62'd0}, ic_rw_addr_q[11:3]} : _GEN_3; // @[el2_ifu_ic_mem.scala 248:62]
|
||||
wire _T_148 = ic_b_sb_wren_1[0] & ic_bank_way_clken_1[0]; // @[el2_ifu_ic_mem.scala 248:29]
|
||||
wire _T_152 = ~ic_b_sb_wren_1[0]; // @[el2_ifu_ic_mem.scala 250:17]
|
||||
wire _T_154 = _T_152 & ic_bank_way_clken_1[0]; // @[el2_ifu_ic_mem.scala 250:36]
|
||||
wire [70:0] _GEN_17 = _T_154 ? data_mem_1_0__T_156_data : _GEN_13; // @[el2_ifu_ic_mem.scala 250:69]
|
||||
wire [70:0] _GEN_27 = _T_148 ? _GEN_13 : _GEN_17; // @[el2_ifu_ic_mem.scala 248:62]
|
||||
wire _T_159 = ic_b_sb_wren_0[1] & ic_bank_way_clken_0[1]; // @[el2_ifu_ic_mem.scala 248:29]
|
||||
wire _T_163 = ~ic_b_sb_wren_0[1]; // @[el2_ifu_ic_mem.scala 250:17]
|
||||
wire _T_165 = _T_163 & ic_bank_way_clken_0[1]; // @[el2_ifu_ic_mem.scala 250:36]
|
||||
wire [70:0] _GEN_31 = _T_165 ? data_mem_0_1__T_167_data : _GEN_27; // @[el2_ifu_ic_mem.scala 250:69]
|
||||
wire [70:0] _GEN_41 = _T_159 ? _GEN_27 : _GEN_31; // @[el2_ifu_ic_mem.scala 248:62]
|
||||
wire _T_170 = ic_b_sb_wren_1[1] & ic_bank_way_clken_1[1]; // @[el2_ifu_ic_mem.scala 248:29]
|
||||
wire _T_174 = ~ic_b_sb_wren_1[1]; // @[el2_ifu_ic_mem.scala 250:17]
|
||||
wire _T_176 = _T_174 & ic_bank_way_clken_1[1]; // @[el2_ifu_ic_mem.scala 250:36]
|
||||
wire [70:0] _GEN_45 = _T_176 ? data_mem_1_1__T_178_data : _GEN_41; // @[el2_ifu_ic_mem.scala 250:69]
|
||||
assign data_mem_0_0__T_145_addr = _T_124 ? ic_rw_addr_q[11:3] : _T_129;
|
||||
assign data_mem_0_0__T_145_data = data_mem_0_0[data_mem_0_0__T_145_addr]; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
assign data_mem_0_0__T_156_addr = ic_rw_addr_q[11:3];
|
||||
assign data_mem_0_0__T_156_data = data_mem_0_0[data_mem_0_0__T_156_addr]; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
wire _T_139 = ic_b_sb_wren_0[0] & ic_bank_way_clken_0[0]; // @[el2_ifu_ic_mem.scala 247:30]
|
||||
wire _T_143 = ~ic_b_sb_wren_0[0]; // @[el2_ifu_ic_mem.scala 249:17]
|
||||
wire _T_145 = _T_143 & ic_bank_way_clken_0[0]; // @[el2_ifu_ic_mem.scala 249:36]
|
||||
wire [70:0] _GEN_3 = _T_145 ? data_mem_0_0__T_147_data : 71'h0; // @[el2_ifu_ic_mem.scala 249:69]
|
||||
wire [70:0] _GEN_13 = _T_139 ? 71'h0 : _GEN_3; // @[el2_ifu_ic_mem.scala 247:64]
|
||||
wire _T_152 = ic_b_sb_wren_1[0] & ic_bank_way_clken_1[0]; // @[el2_ifu_ic_mem.scala 247:30]
|
||||
wire _T_156 = ~ic_b_sb_wren_1[0]; // @[el2_ifu_ic_mem.scala 249:17]
|
||||
wire _T_158 = _T_156 & ic_bank_way_clken_1[0]; // @[el2_ifu_ic_mem.scala 249:36]
|
||||
wire [70:0] _GEN_17 = _T_158 ? data_mem_1_0__T_160_data : _GEN_13; // @[el2_ifu_ic_mem.scala 249:69]
|
||||
wire [70:0] _GEN_27 = _T_152 ? _GEN_13 : _GEN_17; // @[el2_ifu_ic_mem.scala 247:64]
|
||||
wire _T_165 = ic_b_sb_wren_0[1] & ic_bank_way_clken_0[1]; // @[el2_ifu_ic_mem.scala 247:30]
|
||||
wire _T_169 = ~ic_b_sb_wren_0[1]; // @[el2_ifu_ic_mem.scala 249:17]
|
||||
wire _T_171 = _T_169 & ic_bank_way_clken_0[1]; // @[el2_ifu_ic_mem.scala 249:36]
|
||||
wire [70:0] _GEN_31 = _T_171 ? data_mem_0_1__T_173_data : _GEN_27; // @[el2_ifu_ic_mem.scala 249:69]
|
||||
wire [70:0] _GEN_41 = _T_165 ? _GEN_27 : _GEN_31; // @[el2_ifu_ic_mem.scala 247:64]
|
||||
wire _T_178 = ic_b_sb_wren_1[1] & ic_bank_way_clken_1[1]; // @[el2_ifu_ic_mem.scala 247:30]
|
||||
wire _T_182 = ~ic_b_sb_wren_1[1]; // @[el2_ifu_ic_mem.scala 249:17]
|
||||
wire _T_184 = _T_182 & ic_bank_way_clken_1[1]; // @[el2_ifu_ic_mem.scala 249:36]
|
||||
wire [70:0] _GEN_45 = _T_184 ? data_mem_1_1__T_186_data : _GEN_41; // @[el2_ifu_ic_mem.scala 249:69]
|
||||
assign data_mem_0_0__T_147_addr = _T_124 ? ic_rw_addr_q[11:3] : _T_129;
|
||||
assign data_mem_0_0__T_147_data = data_mem_0_0[data_mem_0_0__T_147_addr]; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
assign data_mem_0_0__T_160_addr = ic_rw_addr_q[11:3];
|
||||
assign data_mem_0_0__T_160_data = data_mem_0_0[data_mem_0_0__T_160_addr]; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
assign data_mem_0_0__T_173_addr = _T_124 ? ic_rw_addr_q[11:3] : _T_129;
|
||||
assign data_mem_0_0__T_173_data = data_mem_0_0[data_mem_0_0__T_173_addr]; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
assign data_mem_0_0__T_186_addr = ic_rw_addr_q[11:3];
|
||||
assign data_mem_0_0__T_186_data = data_mem_0_0[data_mem_0_0__T_186_addr]; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
assign data_mem_0_0__T_141_data = io_test_in;
|
||||
assign data_mem_0_0__T_141_addr = _T_124 ? ic_rw_addr_q[11:3] : _T_129;
|
||||
assign data_mem_0_0__T_141_mask = 1'h1;
|
||||
assign data_mem_0_0__T_141_en = ic_b_sb_wren_0[0] & ic_bank_way_clken_0[0];
|
||||
assign data_mem_0_0__T_154_data = 71'h0;
|
||||
assign data_mem_0_0__T_154_addr = ic_rw_addr_q[11:3];
|
||||
assign data_mem_0_0__T_154_mask = 1'h0;
|
||||
assign data_mem_0_0__T_154_en = ic_b_sb_wren_1[0] & ic_bank_way_clken_1[0];
|
||||
assign data_mem_0_0__T_167_data = 71'h0;
|
||||
assign data_mem_0_0__T_167_addr = _T_124 ? ic_rw_addr_q[11:3] : _T_129;
|
||||
assign data_mem_0_0__T_167_data = data_mem_0_0[data_mem_0_0__T_167_addr]; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
assign data_mem_0_0__T_178_addr = ic_rw_addr_q[11:3];
|
||||
assign data_mem_0_0__T_178_data = data_mem_0_0[data_mem_0_0__T_178_addr]; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
assign data_mem_0_0__T_139_data = io_test_in;
|
||||
assign data_mem_0_0__T_139_addr = _T_124 ? ic_rw_addr_q[11:3] : _T_129;
|
||||
assign data_mem_0_0__T_139_mask = 1'h1;
|
||||
assign data_mem_0_0__T_139_en = ic_b_sb_wren_0[0] & ic_bank_way_clken_0[0];
|
||||
assign data_mem_0_0__T_150_data = 71'h0;
|
||||
assign data_mem_0_0__T_150_addr = ic_rw_addr_q[11:3];
|
||||
assign data_mem_0_0__T_150_mask = 1'h0;
|
||||
assign data_mem_0_0__T_150_en = ic_b_sb_wren_1[0] & ic_bank_way_clken_1[0];
|
||||
assign data_mem_0_0__T_161_data = 71'h0;
|
||||
assign data_mem_0_0__T_161_addr = _T_124 ? ic_rw_addr_q[11:3] : _T_129;
|
||||
assign data_mem_0_0__T_161_mask = 1'h0;
|
||||
assign data_mem_0_0__T_161_en = ic_b_sb_wren_0[1] & ic_bank_way_clken_0[1];
|
||||
assign data_mem_0_0__T_172_data = 71'h0;
|
||||
assign data_mem_0_0__T_172_addr = ic_rw_addr_q[11:3];
|
||||
assign data_mem_0_0__T_172_mask = 1'h0;
|
||||
assign data_mem_0_0__T_172_en = ic_b_sb_wren_1[1] & ic_bank_way_clken_1[1];
|
||||
assign data_mem_0_1__T_145_addr = _T_124 ? ic_rw_addr_q[11:3] : _T_129;
|
||||
assign data_mem_0_1__T_145_data = data_mem_0_1[data_mem_0_1__T_145_addr]; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
assign data_mem_0_1__T_156_addr = ic_rw_addr_q[11:3];
|
||||
assign data_mem_0_1__T_156_data = data_mem_0_1[data_mem_0_1__T_156_addr]; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
assign data_mem_0_0__T_167_mask = 1'h0;
|
||||
assign data_mem_0_0__T_167_en = ic_b_sb_wren_0[1] & ic_bank_way_clken_0[1];
|
||||
assign data_mem_0_0__T_180_data = 71'h0;
|
||||
assign data_mem_0_0__T_180_addr = ic_rw_addr_q[11:3];
|
||||
assign data_mem_0_0__T_180_mask = 1'h0;
|
||||
assign data_mem_0_0__T_180_en = ic_b_sb_wren_1[1] & ic_bank_way_clken_1[1];
|
||||
assign data_mem_0_1__T_147_addr = _T_124 ? ic_rw_addr_q[11:3] : _T_129;
|
||||
assign data_mem_0_1__T_147_data = data_mem_0_1[data_mem_0_1__T_147_addr]; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
assign data_mem_0_1__T_160_addr = ic_rw_addr_q[11:3];
|
||||
assign data_mem_0_1__T_160_data = data_mem_0_1[data_mem_0_1__T_160_addr]; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
assign data_mem_0_1__T_173_addr = _T_124 ? ic_rw_addr_q[11:3] : _T_129;
|
||||
assign data_mem_0_1__T_173_data = data_mem_0_1[data_mem_0_1__T_173_addr]; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
assign data_mem_0_1__T_186_addr = ic_rw_addr_q[11:3];
|
||||
assign data_mem_0_1__T_186_data = data_mem_0_1[data_mem_0_1__T_186_addr]; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
assign data_mem_0_1__T_141_data = 71'h0;
|
||||
assign data_mem_0_1__T_141_addr = _T_124 ? ic_rw_addr_q[11:3] : _T_129;
|
||||
assign data_mem_0_1__T_141_mask = 1'h0;
|
||||
assign data_mem_0_1__T_141_en = ic_b_sb_wren_0[0] & ic_bank_way_clken_0[0];
|
||||
assign data_mem_0_1__T_154_data = 71'h0;
|
||||
assign data_mem_0_1__T_154_addr = ic_rw_addr_q[11:3];
|
||||
assign data_mem_0_1__T_154_mask = 1'h0;
|
||||
assign data_mem_0_1__T_154_en = ic_b_sb_wren_1[0] & ic_bank_way_clken_1[0];
|
||||
assign data_mem_0_1__T_167_data = io_test_in;
|
||||
assign data_mem_0_1__T_167_addr = _T_124 ? ic_rw_addr_q[11:3] : _T_129;
|
||||
assign data_mem_0_1__T_167_data = data_mem_0_1[data_mem_0_1__T_167_addr]; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
assign data_mem_0_1__T_178_addr = ic_rw_addr_q[11:3];
|
||||
assign data_mem_0_1__T_178_data = data_mem_0_1[data_mem_0_1__T_178_addr]; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
assign data_mem_0_1__T_139_data = 71'h0;
|
||||
assign data_mem_0_1__T_139_addr = _T_124 ? ic_rw_addr_q[11:3] : _T_129;
|
||||
assign data_mem_0_1__T_139_mask = 1'h0;
|
||||
assign data_mem_0_1__T_139_en = ic_b_sb_wren_0[0] & ic_bank_way_clken_0[0];
|
||||
assign data_mem_0_1__T_150_data = 71'h0;
|
||||
assign data_mem_0_1__T_150_addr = ic_rw_addr_q[11:3];
|
||||
assign data_mem_0_1__T_150_mask = 1'h0;
|
||||
assign data_mem_0_1__T_150_en = ic_b_sb_wren_1[0] & ic_bank_way_clken_1[0];
|
||||
assign data_mem_0_1__T_161_data = io_test_in;
|
||||
assign data_mem_0_1__T_161_addr = _T_124 ? ic_rw_addr_q[11:3] : _T_129;
|
||||
assign data_mem_0_1__T_161_mask = 1'h1;
|
||||
assign data_mem_0_1__T_161_en = ic_b_sb_wren_0[1] & ic_bank_way_clken_0[1];
|
||||
assign data_mem_0_1__T_172_data = 71'h0;
|
||||
assign data_mem_0_1__T_172_addr = ic_rw_addr_q[11:3];
|
||||
assign data_mem_0_1__T_172_mask = 1'h0;
|
||||
assign data_mem_0_1__T_172_en = ic_b_sb_wren_1[1] & ic_bank_way_clken_1[1];
|
||||
assign data_mem_1_0__T_145_addr = _T_124 ? ic_rw_addr_q[11:3] : _T_129;
|
||||
assign data_mem_1_0__T_145_data = data_mem_1_0[data_mem_1_0__T_145_addr]; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
assign data_mem_1_0__T_156_addr = ic_rw_addr_q[11:3];
|
||||
assign data_mem_1_0__T_156_data = data_mem_1_0[data_mem_1_0__T_156_addr]; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
assign data_mem_0_1__T_167_mask = 1'h1;
|
||||
assign data_mem_0_1__T_167_en = ic_b_sb_wren_0[1] & ic_bank_way_clken_0[1];
|
||||
assign data_mem_0_1__T_180_data = 71'h0;
|
||||
assign data_mem_0_1__T_180_addr = ic_rw_addr_q[11:3];
|
||||
assign data_mem_0_1__T_180_mask = 1'h0;
|
||||
assign data_mem_0_1__T_180_en = ic_b_sb_wren_1[1] & ic_bank_way_clken_1[1];
|
||||
assign data_mem_1_0__T_147_addr = _T_124 ? ic_rw_addr_q[11:3] : _T_129;
|
||||
assign data_mem_1_0__T_147_data = data_mem_1_0[data_mem_1_0__T_147_addr]; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
assign data_mem_1_0__T_160_addr = ic_rw_addr_q[11:3];
|
||||
assign data_mem_1_0__T_160_data = data_mem_1_0[data_mem_1_0__T_160_addr]; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
assign data_mem_1_0__T_173_addr = _T_124 ? ic_rw_addr_q[11:3] : _T_129;
|
||||
assign data_mem_1_0__T_173_data = data_mem_1_0[data_mem_1_0__T_173_addr]; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
assign data_mem_1_0__T_186_addr = ic_rw_addr_q[11:3];
|
||||
assign data_mem_1_0__T_186_data = data_mem_1_0[data_mem_1_0__T_186_addr]; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
assign data_mem_1_0__T_141_data = 71'h0;
|
||||
assign data_mem_1_0__T_141_addr = _T_124 ? ic_rw_addr_q[11:3] : _T_129;
|
||||
assign data_mem_1_0__T_141_mask = 1'h0;
|
||||
assign data_mem_1_0__T_141_en = ic_b_sb_wren_0[0] & ic_bank_way_clken_0[0];
|
||||
assign data_mem_1_0__T_154_data = io_test_in;
|
||||
assign data_mem_1_0__T_154_addr = ic_rw_addr_q[11:3];
|
||||
assign data_mem_1_0__T_154_mask = 1'h1;
|
||||
assign data_mem_1_0__T_154_en = ic_b_sb_wren_1[0] & ic_bank_way_clken_1[0];
|
||||
assign data_mem_1_0__T_167_data = 71'h0;
|
||||
assign data_mem_1_0__T_167_addr = _T_124 ? ic_rw_addr_q[11:3] : _T_129;
|
||||
assign data_mem_1_0__T_167_data = data_mem_1_0[data_mem_1_0__T_167_addr]; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
assign data_mem_1_0__T_178_addr = ic_rw_addr_q[11:3];
|
||||
assign data_mem_1_0__T_178_data = data_mem_1_0[data_mem_1_0__T_178_addr]; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
assign data_mem_1_0__T_139_data = 71'h0;
|
||||
assign data_mem_1_0__T_139_addr = _T_124 ? ic_rw_addr_q[11:3] : _T_129;
|
||||
assign data_mem_1_0__T_139_mask = 1'h0;
|
||||
assign data_mem_1_0__T_139_en = ic_b_sb_wren_0[0] & ic_bank_way_clken_0[0];
|
||||
assign data_mem_1_0__T_150_data = io_test_in;
|
||||
assign data_mem_1_0__T_150_addr = ic_rw_addr_q[11:3];
|
||||
assign data_mem_1_0__T_150_mask = 1'h1;
|
||||
assign data_mem_1_0__T_150_en = ic_b_sb_wren_1[0] & ic_bank_way_clken_1[0];
|
||||
assign data_mem_1_0__T_161_data = 71'h0;
|
||||
assign data_mem_1_0__T_161_addr = _T_124 ? ic_rw_addr_q[11:3] : _T_129;
|
||||
assign data_mem_1_0__T_161_mask = 1'h0;
|
||||
assign data_mem_1_0__T_161_en = ic_b_sb_wren_0[1] & ic_bank_way_clken_0[1];
|
||||
assign data_mem_1_0__T_172_data = 71'h0;
|
||||
assign data_mem_1_0__T_172_addr = ic_rw_addr_q[11:3];
|
||||
assign data_mem_1_0__T_172_mask = 1'h0;
|
||||
assign data_mem_1_0__T_172_en = ic_b_sb_wren_1[1] & ic_bank_way_clken_1[1];
|
||||
assign data_mem_1_1__T_145_addr = _T_124 ? ic_rw_addr_q[11:3] : _T_129;
|
||||
assign data_mem_1_1__T_145_data = data_mem_1_1[data_mem_1_1__T_145_addr]; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
assign data_mem_1_1__T_156_addr = ic_rw_addr_q[11:3];
|
||||
assign data_mem_1_1__T_156_data = data_mem_1_1[data_mem_1_1__T_156_addr]; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
assign data_mem_1_0__T_167_mask = 1'h0;
|
||||
assign data_mem_1_0__T_167_en = ic_b_sb_wren_0[1] & ic_bank_way_clken_0[1];
|
||||
assign data_mem_1_0__T_180_data = 71'h0;
|
||||
assign data_mem_1_0__T_180_addr = ic_rw_addr_q[11:3];
|
||||
assign data_mem_1_0__T_180_mask = 1'h0;
|
||||
assign data_mem_1_0__T_180_en = ic_b_sb_wren_1[1] & ic_bank_way_clken_1[1];
|
||||
assign data_mem_1_1__T_147_addr = _T_124 ? ic_rw_addr_q[11:3] : _T_129;
|
||||
assign data_mem_1_1__T_147_data = data_mem_1_1[data_mem_1_1__T_147_addr]; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
assign data_mem_1_1__T_160_addr = ic_rw_addr_q[11:3];
|
||||
assign data_mem_1_1__T_160_data = data_mem_1_1[data_mem_1_1__T_160_addr]; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
assign data_mem_1_1__T_173_addr = _T_124 ? ic_rw_addr_q[11:3] : _T_129;
|
||||
assign data_mem_1_1__T_173_data = data_mem_1_1[data_mem_1_1__T_173_addr]; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
assign data_mem_1_1__T_186_addr = ic_rw_addr_q[11:3];
|
||||
assign data_mem_1_1__T_186_data = data_mem_1_1[data_mem_1_1__T_186_addr]; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
assign data_mem_1_1__T_141_data = 71'h0;
|
||||
assign data_mem_1_1__T_141_addr = _T_124 ? ic_rw_addr_q[11:3] : _T_129;
|
||||
assign data_mem_1_1__T_141_mask = 1'h0;
|
||||
assign data_mem_1_1__T_141_en = ic_b_sb_wren_0[0] & ic_bank_way_clken_0[0];
|
||||
assign data_mem_1_1__T_154_data = 71'h0;
|
||||
assign data_mem_1_1__T_154_addr = ic_rw_addr_q[11:3];
|
||||
assign data_mem_1_1__T_154_mask = 1'h0;
|
||||
assign data_mem_1_1__T_154_en = ic_b_sb_wren_1[0] & ic_bank_way_clken_1[0];
|
||||
assign data_mem_1_1__T_167_data = 71'h0;
|
||||
assign data_mem_1_1__T_167_addr = _T_124 ? ic_rw_addr_q[11:3] : _T_129;
|
||||
assign data_mem_1_1__T_167_data = data_mem_1_1[data_mem_1_1__T_167_addr]; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
assign data_mem_1_1__T_178_addr = ic_rw_addr_q[11:3];
|
||||
assign data_mem_1_1__T_178_data = data_mem_1_1[data_mem_1_1__T_178_addr]; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
assign data_mem_1_1__T_139_data = 71'h0;
|
||||
assign data_mem_1_1__T_139_addr = _T_124 ? ic_rw_addr_q[11:3] : _T_129;
|
||||
assign data_mem_1_1__T_139_mask = 1'h0;
|
||||
assign data_mem_1_1__T_139_en = ic_b_sb_wren_0[0] & ic_bank_way_clken_0[0];
|
||||
assign data_mem_1_1__T_150_data = 71'h0;
|
||||
assign data_mem_1_1__T_150_addr = ic_rw_addr_q[11:3];
|
||||
assign data_mem_1_1__T_150_mask = 1'h0;
|
||||
assign data_mem_1_1__T_150_en = ic_b_sb_wren_1[0] & ic_bank_way_clken_1[0];
|
||||
assign data_mem_1_1__T_161_data = 71'h0;
|
||||
assign data_mem_1_1__T_161_addr = _T_124 ? ic_rw_addr_q[11:3] : _T_129;
|
||||
assign data_mem_1_1__T_161_mask = 1'h0;
|
||||
assign data_mem_1_1__T_161_en = ic_b_sb_wren_0[1] & ic_bank_way_clken_0[1];
|
||||
assign data_mem_1_1__T_172_data = io_test_in;
|
||||
assign data_mem_1_1__T_172_addr = ic_rw_addr_q[11:3];
|
||||
assign data_mem_1_1__T_172_mask = 1'h1;
|
||||
assign data_mem_1_1__T_172_en = ic_b_sb_wren_1[1] & ic_bank_way_clken_1[1];
|
||||
assign data_mem_1_1__T_167_mask = 1'h0;
|
||||
assign data_mem_1_1__T_167_en = ic_b_sb_wren_0[1] & ic_bank_way_clken_0[1];
|
||||
assign data_mem_1_1__T_180_data = io_test_in;
|
||||
assign data_mem_1_1__T_180_addr = ic_rw_addr_q[11:3];
|
||||
assign data_mem_1_1__T_180_mask = 1'h1;
|
||||
assign data_mem_1_1__T_180_en = ic_b_sb_wren_1[1] & ic_bank_way_clken_1[1];
|
||||
assign io_ic_rd_data = 64'h0; // @[el2_ifu_ic_mem.scala 194:17]
|
||||
assign io_ic_debug_rd_data = 71'h0; // @[el2_ifu_ic_mem.scala 195:23]
|
||||
assign io_ic_parerr = 2'h0; // @[el2_ifu_ic_mem.scala 196:16]
|
||||
assign io_ic_eccerr = 2'h0; // @[el2_ifu_ic_mem.scala 197:16]
|
||||
assign io_test = _T_170 ? _GEN_41 : _GEN_45; // @[el2_ifu_ic_mem.scala 198:11 el2_ifu_ic_mem.scala 209:11 el2_ifu_ic_mem.scala 241:11 el2_ifu_ic_mem.scala 251:15 el2_ifu_ic_mem.scala 251:15 el2_ifu_ic_mem.scala 251:15 el2_ifu_ic_mem.scala 251:15]
|
||||
assign io_test = _T_178 ? _GEN_41 : _GEN_45; // @[el2_ifu_ic_mem.scala 198:11 el2_ifu_ic_mem.scala 250:15 el2_ifu_ic_mem.scala 250:15 el2_ifu_ic_mem.scala 250:15 el2_ifu_ic_mem.scala 250:15]
|
||||
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
||||
`define RANDOMIZE
|
||||
`endif
|
||||
|
|
@ -349,53 +349,53 @@ end // initial
|
|||
`endif
|
||||
`endif // SYNTHESIS
|
||||
always @(posedge clock) begin
|
||||
if(data_mem_0_0__T_139_en & data_mem_0_0__T_139_mask) begin
|
||||
data_mem_0_0[data_mem_0_0__T_139_addr] <= data_mem_0_0__T_139_data; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
if(data_mem_0_0__T_141_en & data_mem_0_0__T_141_mask) begin
|
||||
data_mem_0_0[data_mem_0_0__T_141_addr] <= data_mem_0_0__T_141_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
end
|
||||
if(data_mem_0_0__T_150_en & data_mem_0_0__T_150_mask) begin
|
||||
data_mem_0_0[data_mem_0_0__T_150_addr] <= data_mem_0_0__T_150_data; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
if(data_mem_0_0__T_154_en & data_mem_0_0__T_154_mask) begin
|
||||
data_mem_0_0[data_mem_0_0__T_154_addr] <= data_mem_0_0__T_154_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
end
|
||||
if(data_mem_0_0__T_161_en & data_mem_0_0__T_161_mask) begin
|
||||
data_mem_0_0[data_mem_0_0__T_161_addr] <= data_mem_0_0__T_161_data; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
if(data_mem_0_0__T_167_en & data_mem_0_0__T_167_mask) begin
|
||||
data_mem_0_0[data_mem_0_0__T_167_addr] <= data_mem_0_0__T_167_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
end
|
||||
if(data_mem_0_0__T_172_en & data_mem_0_0__T_172_mask) begin
|
||||
data_mem_0_0[data_mem_0_0__T_172_addr] <= data_mem_0_0__T_172_data; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
if(data_mem_0_0__T_180_en & data_mem_0_0__T_180_mask) begin
|
||||
data_mem_0_0[data_mem_0_0__T_180_addr] <= data_mem_0_0__T_180_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
end
|
||||
if(data_mem_0_1__T_139_en & data_mem_0_1__T_139_mask) begin
|
||||
data_mem_0_1[data_mem_0_1__T_139_addr] <= data_mem_0_1__T_139_data; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
if(data_mem_0_1__T_141_en & data_mem_0_1__T_141_mask) begin
|
||||
data_mem_0_1[data_mem_0_1__T_141_addr] <= data_mem_0_1__T_141_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
end
|
||||
if(data_mem_0_1__T_150_en & data_mem_0_1__T_150_mask) begin
|
||||
data_mem_0_1[data_mem_0_1__T_150_addr] <= data_mem_0_1__T_150_data; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
if(data_mem_0_1__T_154_en & data_mem_0_1__T_154_mask) begin
|
||||
data_mem_0_1[data_mem_0_1__T_154_addr] <= data_mem_0_1__T_154_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
end
|
||||
if(data_mem_0_1__T_161_en & data_mem_0_1__T_161_mask) begin
|
||||
data_mem_0_1[data_mem_0_1__T_161_addr] <= data_mem_0_1__T_161_data; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
if(data_mem_0_1__T_167_en & data_mem_0_1__T_167_mask) begin
|
||||
data_mem_0_1[data_mem_0_1__T_167_addr] <= data_mem_0_1__T_167_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
end
|
||||
if(data_mem_0_1__T_172_en & data_mem_0_1__T_172_mask) begin
|
||||
data_mem_0_1[data_mem_0_1__T_172_addr] <= data_mem_0_1__T_172_data; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
if(data_mem_0_1__T_180_en & data_mem_0_1__T_180_mask) begin
|
||||
data_mem_0_1[data_mem_0_1__T_180_addr] <= data_mem_0_1__T_180_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
end
|
||||
if(data_mem_1_0__T_139_en & data_mem_1_0__T_139_mask) begin
|
||||
data_mem_1_0[data_mem_1_0__T_139_addr] <= data_mem_1_0__T_139_data; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
if(data_mem_1_0__T_141_en & data_mem_1_0__T_141_mask) begin
|
||||
data_mem_1_0[data_mem_1_0__T_141_addr] <= data_mem_1_0__T_141_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
end
|
||||
if(data_mem_1_0__T_150_en & data_mem_1_0__T_150_mask) begin
|
||||
data_mem_1_0[data_mem_1_0__T_150_addr] <= data_mem_1_0__T_150_data; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
if(data_mem_1_0__T_154_en & data_mem_1_0__T_154_mask) begin
|
||||
data_mem_1_0[data_mem_1_0__T_154_addr] <= data_mem_1_0__T_154_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
end
|
||||
if(data_mem_1_0__T_161_en & data_mem_1_0__T_161_mask) begin
|
||||
data_mem_1_0[data_mem_1_0__T_161_addr] <= data_mem_1_0__T_161_data; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
if(data_mem_1_0__T_167_en & data_mem_1_0__T_167_mask) begin
|
||||
data_mem_1_0[data_mem_1_0__T_167_addr] <= data_mem_1_0__T_167_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
end
|
||||
if(data_mem_1_0__T_172_en & data_mem_1_0__T_172_mask) begin
|
||||
data_mem_1_0[data_mem_1_0__T_172_addr] <= data_mem_1_0__T_172_data; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
if(data_mem_1_0__T_180_en & data_mem_1_0__T_180_mask) begin
|
||||
data_mem_1_0[data_mem_1_0__T_180_addr] <= data_mem_1_0__T_180_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
end
|
||||
if(data_mem_1_1__T_139_en & data_mem_1_1__T_139_mask) begin
|
||||
data_mem_1_1[data_mem_1_1__T_139_addr] <= data_mem_1_1__T_139_data; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
if(data_mem_1_1__T_141_en & data_mem_1_1__T_141_mask) begin
|
||||
data_mem_1_1[data_mem_1_1__T_141_addr] <= data_mem_1_1__T_141_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
end
|
||||
if(data_mem_1_1__T_150_en & data_mem_1_1__T_150_mask) begin
|
||||
data_mem_1_1[data_mem_1_1__T_150_addr] <= data_mem_1_1__T_150_data; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
if(data_mem_1_1__T_154_en & data_mem_1_1__T_154_mask) begin
|
||||
data_mem_1_1[data_mem_1_1__T_154_addr] <= data_mem_1_1__T_154_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
end
|
||||
if(data_mem_1_1__T_161_en & data_mem_1_1__T_161_mask) begin
|
||||
data_mem_1_1[data_mem_1_1__T_161_addr] <= data_mem_1_1__T_161_data; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
if(data_mem_1_1__T_167_en & data_mem_1_1__T_167_mask) begin
|
||||
data_mem_1_1[data_mem_1_1__T_167_addr] <= data_mem_1_1__T_167_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
end
|
||||
if(data_mem_1_1__T_172_en & data_mem_1_1__T_172_mask) begin
|
||||
data_mem_1_1[data_mem_1_1__T_172_addr] <= data_mem_1_1__T_172_data; // @[el2_ifu_ic_mem.scala 246:21]
|
||||
if(data_mem_1_1__T_180_en & data_mem_1_1__T_180_mask) begin
|
||||
data_mem_1_1[data_mem_1_1__T_180_addr] <= data_mem_1_1__T_180_data; // @[el2_ifu_ic_mem.scala 243:21]
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -29,18 +29,18 @@ circuit el2_ifu_bp_ctl :
|
|||
dec_tlu_way_wb <= UInt<1>("h00")
|
||||
node _T = eq(leak_one_f, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 68:43]
|
||||
node exu_mp_valid = and(io.exu_mp_pkt.misp, _T) @[el2_ifu_bp_ctl.scala 68:41]
|
||||
node _T_1 = bits(io.ifc_fetch_addr_f, 9, 2) @[el2_lib.scala 182:12]
|
||||
node _T_2 = bits(io.ifc_fetch_addr_f, 17, 10) @[el2_lib.scala 182:46]
|
||||
node _T_3 = xor(_T_1, _T_2) @[el2_lib.scala 182:42]
|
||||
node _T_4 = bits(io.ifc_fetch_addr_f, 25, 18) @[el2_lib.scala 182:80]
|
||||
node btb_rd_addr_f = xor(_T_3, _T_4) @[el2_lib.scala 182:76]
|
||||
node _T_1 = bits(io.ifc_fetch_addr_f, 9, 2) @[el2_lib.scala 179:12]
|
||||
node _T_2 = bits(io.ifc_fetch_addr_f, 17, 10) @[el2_lib.scala 179:46]
|
||||
node _T_3 = xor(_T_1, _T_2) @[el2_lib.scala 179:42]
|
||||
node _T_4 = bits(io.ifc_fetch_addr_f, 25, 18) @[el2_lib.scala 179:80]
|
||||
node btb_rd_addr_f = xor(_T_3, _T_4) @[el2_lib.scala 179:76]
|
||||
node _T_5 = add(io.ifc_fetch_addr_f, UInt<3>("h04")) @[el2_ifu_bp_ctl.scala 93:45]
|
||||
node fetch_addr_p1_f = tail(_T_5, 1) @[el2_ifu_bp_ctl.scala 93:45]
|
||||
node _T_6 = bits(fetch_addr_p1_f, 9, 2) @[el2_lib.scala 182:12]
|
||||
node _T_7 = bits(fetch_addr_p1_f, 17, 10) @[el2_lib.scala 182:46]
|
||||
node _T_8 = xor(_T_6, _T_7) @[el2_lib.scala 182:42]
|
||||
node _T_9 = bits(fetch_addr_p1_f, 25, 18) @[el2_lib.scala 182:80]
|
||||
node btb_rd_addr_p1_f = xor(_T_8, _T_9) @[el2_lib.scala 182:76]
|
||||
node _T_6 = bits(fetch_addr_p1_f, 9, 2) @[el2_lib.scala 179:12]
|
||||
node _T_7 = bits(fetch_addr_p1_f, 17, 10) @[el2_lib.scala 179:46]
|
||||
node _T_8 = xor(_T_6, _T_7) @[el2_lib.scala 179:42]
|
||||
node _T_9 = bits(fetch_addr_p1_f, 25, 18) @[el2_lib.scala 179:80]
|
||||
node btb_rd_addr_p1_f = xor(_T_8, _T_9) @[el2_lib.scala 179:76]
|
||||
node _T_10 = bits(bht_dir_f, 0, 0) @[el2_ifu_bp_ctl.scala 98:33]
|
||||
node _T_11 = not(_T_10) @[el2_ifu_bp_ctl.scala 98:23]
|
||||
node _T_12 = bits(bht_dir_f, 0, 0) @[el2_ifu_bp_ctl.scala 98:46]
|
||||
|
|
@ -55,24 +55,24 @@ circuit el2_ifu_bp_ctl :
|
|||
node branch_error_collision_p1_f = and(dec_tlu_error_wb, _T_17) @[el2_ifu_bp_ctl.scala 105:54]
|
||||
node branch_error_bank_conflict_f = and(branch_error_collision_f, dec_tlu_error_wb) @[el2_ifu_bp_ctl.scala 108:63]
|
||||
node branch_error_bank_conflict_p1_f = and(branch_error_collision_p1_f, dec_tlu_error_wb) @[el2_ifu_bp_ctl.scala 109:69]
|
||||
node _T_18 = bits(io.ifc_fetch_addr_f, 14, 10) @[el2_lib.scala 175:32]
|
||||
node _T_19 = bits(io.ifc_fetch_addr_f, 19, 15) @[el2_lib.scala 175:32]
|
||||
node _T_20 = bits(io.ifc_fetch_addr_f, 24, 20) @[el2_lib.scala 175:32]
|
||||
wire _T_21 : UInt<5>[3] @[el2_lib.scala 175:24]
|
||||
_T_21[0] <= _T_18 @[el2_lib.scala 175:24]
|
||||
_T_21[1] <= _T_19 @[el2_lib.scala 175:24]
|
||||
_T_21[2] <= _T_20 @[el2_lib.scala 175:24]
|
||||
node _T_22 = xor(_T_21[0], _T_21[1]) @[el2_lib.scala 175:111]
|
||||
node fetch_rd_tag_f = xor(_T_22, _T_21[2]) @[el2_lib.scala 175:111]
|
||||
node _T_23 = bits(fetch_addr_p1_f, 14, 10) @[el2_lib.scala 175:32]
|
||||
node _T_24 = bits(fetch_addr_p1_f, 19, 15) @[el2_lib.scala 175:32]
|
||||
node _T_25 = bits(fetch_addr_p1_f, 24, 20) @[el2_lib.scala 175:32]
|
||||
wire _T_26 : UInt<5>[3] @[el2_lib.scala 175:24]
|
||||
_T_26[0] <= _T_23 @[el2_lib.scala 175:24]
|
||||
_T_26[1] <= _T_24 @[el2_lib.scala 175:24]
|
||||
_T_26[2] <= _T_25 @[el2_lib.scala 175:24]
|
||||
node _T_27 = xor(_T_26[0], _T_26[1]) @[el2_lib.scala 175:111]
|
||||
node fetch_rd_tag_p1_f = xor(_T_27, _T_26[2]) @[el2_lib.scala 175:111]
|
||||
node _T_18 = bits(io.ifc_fetch_addr_f, 14, 10) @[el2_lib.scala 172:32]
|
||||
node _T_19 = bits(io.ifc_fetch_addr_f, 19, 15) @[el2_lib.scala 172:32]
|
||||
node _T_20 = bits(io.ifc_fetch_addr_f, 24, 20) @[el2_lib.scala 172:32]
|
||||
wire _T_21 : UInt<5>[3] @[el2_lib.scala 172:24]
|
||||
_T_21[0] <= _T_18 @[el2_lib.scala 172:24]
|
||||
_T_21[1] <= _T_19 @[el2_lib.scala 172:24]
|
||||
_T_21[2] <= _T_20 @[el2_lib.scala 172:24]
|
||||
node _T_22 = xor(_T_21[0], _T_21[1]) @[el2_lib.scala 172:111]
|
||||
node fetch_rd_tag_f = xor(_T_22, _T_21[2]) @[el2_lib.scala 172:111]
|
||||
node _T_23 = bits(fetch_addr_p1_f, 14, 10) @[el2_lib.scala 172:32]
|
||||
node _T_24 = bits(fetch_addr_p1_f, 19, 15) @[el2_lib.scala 172:32]
|
||||
node _T_25 = bits(fetch_addr_p1_f, 24, 20) @[el2_lib.scala 172:32]
|
||||
wire _T_26 : UInt<5>[3] @[el2_lib.scala 172:24]
|
||||
_T_26[0] <= _T_23 @[el2_lib.scala 172:24]
|
||||
_T_26[1] <= _T_24 @[el2_lib.scala 172:24]
|
||||
_T_26[2] <= _T_25 @[el2_lib.scala 172:24]
|
||||
node _T_27 = xor(_T_26[0], _T_26[1]) @[el2_lib.scala 172:111]
|
||||
node fetch_rd_tag_p1_f = xor(_T_27, _T_26[2]) @[el2_lib.scala 172:111]
|
||||
node _T_28 = eq(io.exu_mp_btag, fetch_rd_tag_f) @[el2_ifu_bp_ctl.scala 114:46]
|
||||
node _T_29 = and(_T_28, exu_mp_valid) @[el2_ifu_bp_ctl.scala 114:66]
|
||||
node _T_30 = and(_T_29, io.ifc_fetch_req_f) @[el2_ifu_bp_ctl.scala 114:81]
|
||||
|
|
@ -544,29 +544,29 @@ circuit el2_ifu_bp_ctl :
|
|||
node _T_384 = cat(_T_383, bp_total_branch_offset_f) @[Cat.scala 29:58]
|
||||
node _T_385 = cat(_T_384, UInt<1>("h00")) @[Cat.scala 29:58]
|
||||
node _T_386 = cat(btb_rd_tgt_f, UInt<1>("h00")) @[Cat.scala 29:58]
|
||||
node _T_387 = bits(_T_385, 12, 1) @[el2_lib.scala 199:24]
|
||||
node _T_388 = bits(_T_386, 12, 1) @[el2_lib.scala 199:40]
|
||||
node _T_389 = add(_T_387, _T_388) @[el2_lib.scala 199:31]
|
||||
node _T_390 = bits(_T_385, 31, 13) @[el2_lib.scala 200:20]
|
||||
node _T_391 = add(_T_390, UInt<1>("h01")) @[el2_lib.scala 200:27]
|
||||
node _T_392 = tail(_T_391, 1) @[el2_lib.scala 200:27]
|
||||
node _T_393 = bits(_T_385, 31, 13) @[el2_lib.scala 201:20]
|
||||
node _T_394 = add(_T_393, UInt<1>("h01")) @[el2_lib.scala 201:27]
|
||||
node _T_395 = tail(_T_394, 1) @[el2_lib.scala 201:27]
|
||||
node _T_396 = bits(_T_386, 12, 12) @[el2_lib.scala 202:22]
|
||||
node _T_397 = bits(_T_389, 12, 12) @[el2_lib.scala 203:38]
|
||||
node _T_398 = eq(_T_397, UInt<1>("h00")) @[el2_lib.scala 203:27]
|
||||
node _T_399 = xor(_T_396, _T_398) @[el2_lib.scala 203:25]
|
||||
node _T_400 = bits(_T_399, 0, 0) @[el2_lib.scala 203:63]
|
||||
node _T_401 = bits(_T_385, 31, 13) @[el2_lib.scala 203:75]
|
||||
node _T_402 = eq(_T_396, UInt<1>("h00")) @[el2_lib.scala 204:8]
|
||||
node _T_403 = bits(_T_389, 12, 12) @[el2_lib.scala 204:26]
|
||||
node _T_404 = and(_T_402, _T_403) @[el2_lib.scala 204:14]
|
||||
node _T_405 = bits(_T_404, 0, 0) @[el2_lib.scala 204:51]
|
||||
node _T_406 = bits(_T_389, 12, 12) @[el2_lib.scala 205:26]
|
||||
node _T_407 = eq(_T_406, UInt<1>("h00")) @[el2_lib.scala 205:15]
|
||||
node _T_408 = and(_T_396, _T_407) @[el2_lib.scala 205:13]
|
||||
node _T_409 = bits(_T_408, 0, 0) @[el2_lib.scala 205:51]
|
||||
node _T_387 = bits(_T_385, 12, 1) @[el2_lib.scala 196:24]
|
||||
node _T_388 = bits(_T_386, 12, 1) @[el2_lib.scala 196:40]
|
||||
node _T_389 = add(_T_387, _T_388) @[el2_lib.scala 196:31]
|
||||
node _T_390 = bits(_T_385, 31, 13) @[el2_lib.scala 197:20]
|
||||
node _T_391 = add(_T_390, UInt<1>("h01")) @[el2_lib.scala 197:27]
|
||||
node _T_392 = tail(_T_391, 1) @[el2_lib.scala 197:27]
|
||||
node _T_393 = bits(_T_385, 31, 13) @[el2_lib.scala 198:20]
|
||||
node _T_394 = add(_T_393, UInt<1>("h01")) @[el2_lib.scala 198:27]
|
||||
node _T_395 = tail(_T_394, 1) @[el2_lib.scala 198:27]
|
||||
node _T_396 = bits(_T_386, 12, 12) @[el2_lib.scala 199:22]
|
||||
node _T_397 = bits(_T_389, 12, 12) @[el2_lib.scala 200:38]
|
||||
node _T_398 = eq(_T_397, UInt<1>("h00")) @[el2_lib.scala 200:27]
|
||||
node _T_399 = xor(_T_396, _T_398) @[el2_lib.scala 200:25]
|
||||
node _T_400 = bits(_T_399, 0, 0) @[el2_lib.scala 200:63]
|
||||
node _T_401 = bits(_T_385, 31, 13) @[el2_lib.scala 200:75]
|
||||
node _T_402 = eq(_T_396, UInt<1>("h00")) @[el2_lib.scala 201:8]
|
||||
node _T_403 = bits(_T_389, 12, 12) @[el2_lib.scala 201:26]
|
||||
node _T_404 = and(_T_402, _T_403) @[el2_lib.scala 201:14]
|
||||
node _T_405 = bits(_T_404, 0, 0) @[el2_lib.scala 201:51]
|
||||
node _T_406 = bits(_T_389, 12, 12) @[el2_lib.scala 202:26]
|
||||
node _T_407 = eq(_T_406, UInt<1>("h00")) @[el2_lib.scala 202:15]
|
||||
node _T_408 = and(_T_396, _T_407) @[el2_lib.scala 202:13]
|
||||
node _T_409 = bits(_T_408, 0, 0) @[el2_lib.scala 202:51]
|
||||
node _T_410 = mux(_T_400, _T_401, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_411 = mux(_T_405, _T_392, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_412 = mux(_T_409, _T_395, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
|
|
@ -574,7 +574,7 @@ circuit el2_ifu_bp_ctl :
|
|||
node _T_414 = or(_T_413, _T_412) @[Mux.scala 27:72]
|
||||
wire _T_415 : UInt<19> @[Mux.scala 27:72]
|
||||
_T_415 <= _T_414 @[Mux.scala 27:72]
|
||||
node _T_416 = bits(_T_389, 11, 0) @[el2_lib.scala 205:83]
|
||||
node _T_416 = bits(_T_389, 11, 0) @[el2_lib.scala 202:83]
|
||||
node _T_417 = cat(_T_415, _T_416) @[Cat.scala 29:58]
|
||||
node bp_btb_target_adder_f = cat(_T_417, UInt<1>("h00")) @[Cat.scala 29:58]
|
||||
wire rets_out : UInt<32>[8] @[el2_ifu_bp_ctl.scala 304:22]
|
||||
|
|
@ -602,29 +602,29 @@ circuit el2_ifu_bp_ctl :
|
|||
node _T_430 = not(btb_rd_pc4_f) @[el2_ifu_bp_ctl.scala 311:113]
|
||||
node _T_431 = cat(_T_429, _T_430) @[Cat.scala 29:58]
|
||||
node _T_432 = cat(_T_431, UInt<1>("h00")) @[Cat.scala 29:58]
|
||||
node _T_433 = bits(_T_428, 12, 1) @[el2_lib.scala 199:24]
|
||||
node _T_434 = bits(_T_432, 12, 1) @[el2_lib.scala 199:40]
|
||||
node _T_435 = add(_T_433, _T_434) @[el2_lib.scala 199:31]
|
||||
node _T_436 = bits(_T_428, 31, 13) @[el2_lib.scala 200:20]
|
||||
node _T_437 = add(_T_436, UInt<1>("h01")) @[el2_lib.scala 200:27]
|
||||
node _T_438 = tail(_T_437, 1) @[el2_lib.scala 200:27]
|
||||
node _T_439 = bits(_T_428, 31, 13) @[el2_lib.scala 201:20]
|
||||
node _T_440 = add(_T_439, UInt<1>("h01")) @[el2_lib.scala 201:27]
|
||||
node _T_441 = tail(_T_440, 1) @[el2_lib.scala 201:27]
|
||||
node _T_442 = bits(_T_432, 12, 12) @[el2_lib.scala 202:22]
|
||||
node _T_443 = bits(_T_435, 12, 12) @[el2_lib.scala 203:38]
|
||||
node _T_444 = eq(_T_443, UInt<1>("h00")) @[el2_lib.scala 203:27]
|
||||
node _T_445 = xor(_T_442, _T_444) @[el2_lib.scala 203:25]
|
||||
node _T_446 = bits(_T_445, 0, 0) @[el2_lib.scala 203:63]
|
||||
node _T_447 = bits(_T_428, 31, 13) @[el2_lib.scala 203:75]
|
||||
node _T_448 = eq(_T_442, UInt<1>("h00")) @[el2_lib.scala 204:8]
|
||||
node _T_449 = bits(_T_435, 12, 12) @[el2_lib.scala 204:26]
|
||||
node _T_450 = and(_T_448, _T_449) @[el2_lib.scala 204:14]
|
||||
node _T_451 = bits(_T_450, 0, 0) @[el2_lib.scala 204:51]
|
||||
node _T_452 = bits(_T_435, 12, 12) @[el2_lib.scala 205:26]
|
||||
node _T_453 = eq(_T_452, UInt<1>("h00")) @[el2_lib.scala 205:15]
|
||||
node _T_454 = and(_T_442, _T_453) @[el2_lib.scala 205:13]
|
||||
node _T_455 = bits(_T_454, 0, 0) @[el2_lib.scala 205:51]
|
||||
node _T_433 = bits(_T_428, 12, 1) @[el2_lib.scala 196:24]
|
||||
node _T_434 = bits(_T_432, 12, 1) @[el2_lib.scala 196:40]
|
||||
node _T_435 = add(_T_433, _T_434) @[el2_lib.scala 196:31]
|
||||
node _T_436 = bits(_T_428, 31, 13) @[el2_lib.scala 197:20]
|
||||
node _T_437 = add(_T_436, UInt<1>("h01")) @[el2_lib.scala 197:27]
|
||||
node _T_438 = tail(_T_437, 1) @[el2_lib.scala 197:27]
|
||||
node _T_439 = bits(_T_428, 31, 13) @[el2_lib.scala 198:20]
|
||||
node _T_440 = add(_T_439, UInt<1>("h01")) @[el2_lib.scala 198:27]
|
||||
node _T_441 = tail(_T_440, 1) @[el2_lib.scala 198:27]
|
||||
node _T_442 = bits(_T_432, 12, 12) @[el2_lib.scala 199:22]
|
||||
node _T_443 = bits(_T_435, 12, 12) @[el2_lib.scala 200:38]
|
||||
node _T_444 = eq(_T_443, UInt<1>("h00")) @[el2_lib.scala 200:27]
|
||||
node _T_445 = xor(_T_442, _T_444) @[el2_lib.scala 200:25]
|
||||
node _T_446 = bits(_T_445, 0, 0) @[el2_lib.scala 200:63]
|
||||
node _T_447 = bits(_T_428, 31, 13) @[el2_lib.scala 200:75]
|
||||
node _T_448 = eq(_T_442, UInt<1>("h00")) @[el2_lib.scala 201:8]
|
||||
node _T_449 = bits(_T_435, 12, 12) @[el2_lib.scala 201:26]
|
||||
node _T_450 = and(_T_448, _T_449) @[el2_lib.scala 201:14]
|
||||
node _T_451 = bits(_T_450, 0, 0) @[el2_lib.scala 201:51]
|
||||
node _T_452 = bits(_T_435, 12, 12) @[el2_lib.scala 202:26]
|
||||
node _T_453 = eq(_T_452, UInt<1>("h00")) @[el2_lib.scala 202:15]
|
||||
node _T_454 = and(_T_442, _T_453) @[el2_lib.scala 202:13]
|
||||
node _T_455 = bits(_T_454, 0, 0) @[el2_lib.scala 202:51]
|
||||
node _T_456 = mux(_T_446, _T_447, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_457 = mux(_T_451, _T_438, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_458 = mux(_T_455, _T_441, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
|
|
@ -632,7 +632,7 @@ circuit el2_ifu_bp_ctl :
|
|||
node _T_460 = or(_T_459, _T_458) @[Mux.scala 27:72]
|
||||
wire _T_461 : UInt<19> @[Mux.scala 27:72]
|
||||
_T_461 <= _T_460 @[Mux.scala 27:72]
|
||||
node _T_462 = bits(_T_435, 11, 0) @[el2_lib.scala 205:83]
|
||||
node _T_462 = bits(_T_435, 11, 0) @[el2_lib.scala 202:83]
|
||||
node _T_463 = cat(_T_461, _T_462) @[Cat.scala 29:58]
|
||||
node bp_rs_call_target_f = cat(_T_463, UInt<1>("h00")) @[Cat.scala 29:58]
|
||||
node _T_464 = eq(btb_rd_ret_f, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 313:33]
|
||||
|
|
@ -797,21 +797,21 @@ circuit el2_ifu_bp_ctl :
|
|||
node _T_556 = cat(io.dec_tlu_br0_r_pkt.middle, _T_555) @[Cat.scala 29:58]
|
||||
node bht_wr_en2 = and(_T_554, _T_556) @[el2_ifu_bp_ctl.scala 343:46]
|
||||
node _T_557 = cat(io.exu_mp_index, UInt<2>("h00")) @[Cat.scala 29:58]
|
||||
node _T_558 = bits(_T_557, 9, 2) @[el2_lib.scala 186:16]
|
||||
node _T_559 = bits(io.exu_mp_eghr, 7, 0) @[el2_lib.scala 186:40]
|
||||
node bht_wr_addr0 = xor(_T_558, _T_559) @[el2_lib.scala 186:35]
|
||||
node _T_558 = bits(_T_557, 9, 2) @[el2_lib.scala 183:16]
|
||||
node _T_559 = bits(io.exu_mp_eghr, 7, 0) @[el2_lib.scala 183:40]
|
||||
node bht_wr_addr0 = xor(_T_558, _T_559) @[el2_lib.scala 183:35]
|
||||
node _T_560 = cat(io.exu_i0_br_index_r, UInt<2>("h00")) @[Cat.scala 29:58]
|
||||
node _T_561 = bits(_T_560, 9, 2) @[el2_lib.scala 186:16]
|
||||
node _T_562 = bits(io.exu_i0_br_fghr_r, 7, 0) @[el2_lib.scala 186:40]
|
||||
node bht_wr_addr2 = xor(_T_561, _T_562) @[el2_lib.scala 186:35]
|
||||
node _T_561 = bits(_T_560, 9, 2) @[el2_lib.scala 183:16]
|
||||
node _T_562 = bits(io.exu_i0_br_fghr_r, 7, 0) @[el2_lib.scala 183:40]
|
||||
node bht_wr_addr2 = xor(_T_561, _T_562) @[el2_lib.scala 183:35]
|
||||
node _T_563 = cat(btb_rd_addr_f, UInt<2>("h00")) @[Cat.scala 29:58]
|
||||
node _T_564 = bits(_T_563, 9, 2) @[el2_lib.scala 186:16]
|
||||
node _T_565 = bits(fghr, 7, 0) @[el2_lib.scala 186:40]
|
||||
node bht_rd_addr_f = xor(_T_564, _T_565) @[el2_lib.scala 186:35]
|
||||
node _T_564 = bits(_T_563, 9, 2) @[el2_lib.scala 183:16]
|
||||
node _T_565 = bits(fghr, 7, 0) @[el2_lib.scala 183:40]
|
||||
node bht_rd_addr_f = xor(_T_564, _T_565) @[el2_lib.scala 183:35]
|
||||
node _T_566 = cat(btb_rd_addr_p1_f, UInt<2>("h00")) @[Cat.scala 29:58]
|
||||
node _T_567 = bits(_T_566, 9, 2) @[el2_lib.scala 186:16]
|
||||
node _T_568 = bits(fghr, 7, 0) @[el2_lib.scala 186:40]
|
||||
node bht_rd_addr_hashed_p1_f = xor(_T_567, _T_568) @[el2_lib.scala 186:35]
|
||||
node _T_567 = bits(_T_566, 9, 2) @[el2_lib.scala 183:16]
|
||||
node _T_568 = bits(fghr, 7, 0) @[el2_lib.scala 183:40]
|
||||
node bht_rd_addr_hashed_p1_f = xor(_T_567, _T_568) @[el2_lib.scala 183:35]
|
||||
node _T_569 = eq(btb_wr_addr, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 360:101]
|
||||
node _T_570 = and(_T_569, btb_wr_en_way0) @[el2_ifu_bp_ctl.scala 360:109]
|
||||
node _T_571 = bits(_T_570, 0, 0) @[el2_ifu_bp_ctl.scala 360:127]
|
||||
|
|
|
|||
|
|
@ -1093,11 +1093,11 @@ module el2_ifu_bp_ctl(
|
|||
wire leak_one_f = _T_36 | _T_37; // @[el2_ifu_bp_ctl.scala 122:76]
|
||||
wire _T = ~leak_one_f; // @[el2_ifu_bp_ctl.scala 68:43]
|
||||
wire exu_mp_valid = io_exu_mp_pkt_misp & _T; // @[el2_ifu_bp_ctl.scala 68:41]
|
||||
wire [7:0] _T_3 = io_ifc_fetch_addr_f[9:2] ^ io_ifc_fetch_addr_f[17:10]; // @[el2_lib.scala 182:42]
|
||||
wire [7:0] btb_rd_addr_f = _T_3 ^ io_ifc_fetch_addr_f[25:18]; // @[el2_lib.scala 182:76]
|
||||
wire [7:0] _T_3 = io_ifc_fetch_addr_f[9:2] ^ io_ifc_fetch_addr_f[17:10]; // @[el2_lib.scala 179:42]
|
||||
wire [7:0] btb_rd_addr_f = _T_3 ^ io_ifc_fetch_addr_f[25:18]; // @[el2_lib.scala 179:76]
|
||||
wire [30:0] fetch_addr_p1_f = io_ifc_fetch_addr_f + 31'h4; // @[el2_ifu_bp_ctl.scala 93:45]
|
||||
wire [7:0] _T_8 = fetch_addr_p1_f[9:2] ^ fetch_addr_p1_f[17:10]; // @[el2_lib.scala 182:42]
|
||||
wire [7:0] btb_rd_addr_p1_f = _T_8 ^ fetch_addr_p1_f[25:18]; // @[el2_lib.scala 182:76]
|
||||
wire [7:0] _T_8 = fetch_addr_p1_f[9:2] ^ fetch_addr_p1_f[17:10]; // @[el2_lib.scala 179:42]
|
||||
wire [7:0] btb_rd_addr_p1_f = _T_8 ^ fetch_addr_p1_f[25:18]; // @[el2_lib.scala 179:76]
|
||||
wire _T_139 = ~io_ifc_fetch_addr_f[1]; // @[el2_ifu_bp_ctl.scala 169:40]
|
||||
wire _T_2105 = btb_rd_addr_f == 8'h0; // @[el2_ifu_bp_ctl.scala 363:77]
|
||||
reg [21:0] btb_bank0_rd_data_way0_out_0; // @[Reg.scala 27:20]
|
||||
|
|
@ -2122,8 +2122,8 @@ module el2_ifu_bp_ctl(
|
|||
reg [21:0] btb_bank0_rd_data_way0_out_255; // @[Reg.scala 27:20]
|
||||
wire [21:0] _T_2872 = _T_2615 ? btb_bank0_rd_data_way0_out_255 : 22'h0; // @[Mux.scala 27:72]
|
||||
wire [21:0] btb_bank0_rd_data_way0_f = _T_3126 | _T_2872; // @[Mux.scala 27:72]
|
||||
wire [4:0] _T_22 = io_ifc_fetch_addr_f[14:10] ^ io_ifc_fetch_addr_f[19:15]; // @[el2_lib.scala 175:111]
|
||||
wire [4:0] fetch_rd_tag_f = _T_22 ^ io_ifc_fetch_addr_f[24:20]; // @[el2_lib.scala 175:111]
|
||||
wire [4:0] _T_22 = io_ifc_fetch_addr_f[14:10] ^ io_ifc_fetch_addr_f[19:15]; // @[el2_lib.scala 172:111]
|
||||
wire [4:0] fetch_rd_tag_f = _T_22 ^ io_ifc_fetch_addr_f[24:20]; // @[el2_lib.scala 172:111]
|
||||
wire _T_41 = btb_bank0_rd_data_way0_f[21:17] == fetch_rd_tag_f; // @[el2_ifu_bp_ctl.scala 125:97]
|
||||
wire _T_42 = btb_bank0_rd_data_way0_f[0] & _T_41; // @[el2_ifu_bp_ctl.scala 125:55]
|
||||
reg dec_tlu_way_wb_f; // @[el2_ifu_bp_ctl.scala 118:33]
|
||||
|
|
@ -3691,8 +3691,8 @@ module el2_ifu_bp_ctl(
|
|||
wire _T_4663 = btb_rd_addr_p1_f == 8'hff; // @[el2_ifu_bp_ctl.scala 366:83]
|
||||
wire [21:0] _T_4920 = _T_4663 ? btb_bank0_rd_data_way0_out_255 : 22'h0; // @[Mux.scala 27:72]
|
||||
wire [21:0] btb_bank0_rd_data_way0_p1_f = _T_5174 | _T_4920; // @[Mux.scala 27:72]
|
||||
wire [4:0] _T_27 = fetch_addr_p1_f[14:10] ^ fetch_addr_p1_f[19:15]; // @[el2_lib.scala 175:111]
|
||||
wire [4:0] fetch_rd_tag_p1_f = _T_27 ^ fetch_addr_p1_f[24:20]; // @[el2_lib.scala 175:111]
|
||||
wire [4:0] _T_27 = fetch_addr_p1_f[14:10] ^ fetch_addr_p1_f[19:15]; // @[el2_lib.scala 172:111]
|
||||
wire [4:0] fetch_rd_tag_p1_f = _T_27 ^ fetch_addr_p1_f[24:20]; // @[el2_lib.scala 172:111]
|
||||
wire _T_59 = btb_bank0_rd_data_way0_p1_f[21:17] == fetch_rd_tag_p1_f; // @[el2_ifu_bp_ctl.scala 131:106]
|
||||
wire _T_60 = btb_bank0_rd_data_way0_p1_f[0] & _T_59; // @[el2_ifu_bp_ctl.scala 131:61]
|
||||
wire _T_63 = _T_60 & _T_44; // @[el2_ifu_bp_ctl.scala 131:129]
|
||||
|
|
@ -4241,7 +4241,7 @@ module el2_ifu_bp_ctl(
|
|||
wire _T_251 = ~io_ifc_fetch_addr_f[0]; // @[el2_ifu_bp_ctl.scala 239:40]
|
||||
wire [9:0] _T_563 = {btb_rd_addr_f,2'h0}; // @[Cat.scala 29:58]
|
||||
reg [7:0] fghr; // @[el2_ifu_bp_ctl.scala 275:18]
|
||||
wire [7:0] bht_rd_addr_f = _T_563[9:2] ^ fghr; // @[el2_lib.scala 186:35]
|
||||
wire [7:0] bht_rd_addr_f = _T_563[9:2] ^ fghr; // @[el2_lib.scala 183:35]
|
||||
wire _T_20794 = bht_rd_addr_f == 8'h0; // @[el2_ifu_bp_ctl.scala 382:106]
|
||||
reg [1:0] bht_bank_rd_data_out_1_0; // @[Reg.scala 27:20]
|
||||
wire [1:0] _T_21561 = _T_20794 ? bht_bank_rd_data_out_1_0 : 2'h0; // @[Mux.scala 27:72]
|
||||
|
|
@ -5267,7 +5267,7 @@ module el2_ifu_bp_ctl(
|
|||
wire [1:0] bht_bank1_rd_data_f = _T_22070 | _T_21816; // @[Mux.scala 27:72]
|
||||
wire [1:0] _T_254 = _T_251 ? bht_bank1_rd_data_f : 2'h0; // @[Mux.scala 27:72]
|
||||
wire [9:0] _T_566 = {btb_rd_addr_p1_f,2'h0}; // @[Cat.scala 29:58]
|
||||
wire [7:0] bht_rd_addr_hashed_p1_f = _T_566[9:2] ^ fghr; // @[el2_lib.scala 186:35]
|
||||
wire [7:0] bht_rd_addr_hashed_p1_f = _T_566[9:2] ^ fghr; // @[el2_lib.scala 183:35]
|
||||
wire _T_22074 = bht_rd_addr_hashed_p1_f == 8'h0; // @[el2_ifu_bp_ctl.scala 383:112]
|
||||
wire [1:0] _T_22841 = _T_22074 ? bht_bank_rd_data_out_1_0 : 2'h0; // @[Mux.scala 27:72]
|
||||
wire _T_22077 = bht_rd_addr_hashed_p1_f == 8'h1; // @[el2_ifu_bp_ctl.scala 383:112]
|
||||
|
|
@ -6965,13 +6965,13 @@ module el2_ifu_bp_ctl(
|
|||
wire [30:0] adder_pc_in_f = _T_381 | _GEN_1038; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_385 = {adder_pc_in_f[29:0],bp_total_branch_offset_f,1'h0}; // @[Cat.scala 29:58]
|
||||
wire [12:0] _T_386 = {btb_rd_tgt_f,1'h0}; // @[Cat.scala 29:58]
|
||||
wire [12:0] _T_389 = _T_385[12:1] + _T_386[12:1]; // @[el2_lib.scala 199:31]
|
||||
wire [18:0] _T_392 = _T_385[31:13] + 19'h1; // @[el2_lib.scala 200:27]
|
||||
wire _T_398 = ~_T_389[12]; // @[el2_lib.scala 203:27]
|
||||
wire _T_399 = _T_386[12] ^ _T_398; // @[el2_lib.scala 203:25]
|
||||
wire _T_402 = ~_T_386[12]; // @[el2_lib.scala 204:8]
|
||||
wire _T_404 = _T_402 & _T_389[12]; // @[el2_lib.scala 204:14]
|
||||
wire _T_408 = _T_386[12] & _T_398; // @[el2_lib.scala 205:13]
|
||||
wire [12:0] _T_389 = _T_385[12:1] + _T_386[12:1]; // @[el2_lib.scala 196:31]
|
||||
wire [18:0] _T_392 = _T_385[31:13] + 19'h1; // @[el2_lib.scala 197:27]
|
||||
wire _T_398 = ~_T_389[12]; // @[el2_lib.scala 200:27]
|
||||
wire _T_399 = _T_386[12] ^ _T_398; // @[el2_lib.scala 200:25]
|
||||
wire _T_402 = ~_T_386[12]; // @[el2_lib.scala 201:8]
|
||||
wire _T_404 = _T_402 & _T_389[12]; // @[el2_lib.scala 201:14]
|
||||
wire _T_408 = _T_386[12] & _T_398; // @[el2_lib.scala 202:13]
|
||||
wire [18:0] _T_410 = _T_399 ? _T_385[31:13] : 19'h0; // @[Mux.scala 27:72]
|
||||
wire [18:0] _T_411 = _T_404 ? _T_392 : 19'h0; // @[Mux.scala 27:72]
|
||||
wire [18:0] _T_412 = _T_408 ? _T_392 : 19'h0; // @[Mux.scala 27:72]
|
||||
|
|
@ -6983,12 +6983,12 @@ module el2_ifu_bp_ctl(
|
|||
reg [31:0] rets_out_0; // @[Reg.scala 27:20]
|
||||
wire _T_421 = _T_419 & rets_out_0[0]; // @[el2_ifu_bp_ctl.scala 307:64]
|
||||
wire [12:0] _T_432 = {11'h0,_T_362,1'h0}; // @[Cat.scala 29:58]
|
||||
wire [12:0] _T_435 = _T_385[12:1] + _T_432[12:1]; // @[el2_lib.scala 199:31]
|
||||
wire _T_444 = ~_T_435[12]; // @[el2_lib.scala 203:27]
|
||||
wire _T_445 = _T_432[12] ^ _T_444; // @[el2_lib.scala 203:25]
|
||||
wire _T_448 = ~_T_432[12]; // @[el2_lib.scala 204:8]
|
||||
wire _T_450 = _T_448 & _T_435[12]; // @[el2_lib.scala 204:14]
|
||||
wire _T_454 = _T_432[12] & _T_444; // @[el2_lib.scala 205:13]
|
||||
wire [12:0] _T_435 = _T_385[12:1] + _T_432[12:1]; // @[el2_lib.scala 196:31]
|
||||
wire _T_444 = ~_T_435[12]; // @[el2_lib.scala 200:27]
|
||||
wire _T_445 = _T_432[12] ^ _T_444; // @[el2_lib.scala 200:25]
|
||||
wire _T_448 = ~_T_432[12]; // @[el2_lib.scala 201:8]
|
||||
wire _T_450 = _T_448 & _T_435[12]; // @[el2_lib.scala 201:14]
|
||||
wire _T_454 = _T_432[12] & _T_444; // @[el2_lib.scala 202:13]
|
||||
wire [18:0] _T_456 = _T_445 ? _T_385[31:13] : 19'h0; // @[Mux.scala 27:72]
|
||||
wire [18:0] _T_457 = _T_450 ? _T_392 : 19'h0; // @[Mux.scala 27:72]
|
||||
wire [18:0] _T_458 = _T_454 ? _T_392 : 19'h0; // @[Mux.scala 27:72]
|
||||
|
|
@ -7065,9 +7065,9 @@ module el2_ifu_bp_ctl(
|
|||
wire [1:0] _T_556 = {io_dec_tlu_br0_r_pkt_middle,_T_555}; // @[Cat.scala 29:58]
|
||||
wire [1:0] bht_wr_en2 = _T_554 & _T_556; // @[el2_ifu_bp_ctl.scala 343:46]
|
||||
wire [9:0] _T_557 = {io_exu_mp_index,2'h0}; // @[Cat.scala 29:58]
|
||||
wire [7:0] bht_wr_addr0 = _T_557[9:2] ^ io_exu_mp_eghr; // @[el2_lib.scala 186:35]
|
||||
wire [7:0] bht_wr_addr0 = _T_557[9:2] ^ io_exu_mp_eghr; // @[el2_lib.scala 183:35]
|
||||
wire [9:0] _T_560 = {io_exu_i0_br_index_r,2'h0}; // @[Cat.scala 29:58]
|
||||
wire [7:0] bht_wr_addr2 = _T_560[9:2] ^ io_exu_i0_br_fghr_r; // @[el2_lib.scala 186:35]
|
||||
wire [7:0] bht_wr_addr2 = _T_560[9:2] ^ io_exu_i0_br_fghr_r; // @[el2_lib.scala 183:35]
|
||||
wire _T_569 = btb_wr_addr == 8'h0; // @[el2_ifu_bp_ctl.scala 360:101]
|
||||
wire _T_570 = _T_569 & btb_wr_en_way0; // @[el2_ifu_bp_ctl.scala 360:109]
|
||||
wire _T_572 = btb_wr_addr == 8'h1; // @[el2_ifu_bp_ctl.scala 360:101]
|
||||
|
|
|
|||
|
|
@ -85,186 +85,187 @@ circuit el2_ifu_ifc_ctl :
|
|||
node _T_25 = bits(io.ifc_fetch_addr_f, 30, 1) @[el2_ifu_ifc_ctl.scala 77:42]
|
||||
node _T_26 = add(_T_25, UInt<1>("h01")) @[el2_ifu_ifc_ctl.scala 77:48]
|
||||
node address_upper = tail(_T_26, 1) @[el2_ifu_ifc_ctl.scala 77:48]
|
||||
node _T_27 = bits(address_upper, 5, 5) @[el2_ifu_ifc_ctl.scala 78:38]
|
||||
node _T_28 = bits(io.ifc_fetch_addr_f, 5, 5) @[el2_ifu_ifc_ctl.scala 78:83]
|
||||
node _T_29 = xor(_T_27, _T_28) @[el2_ifu_ifc_ctl.scala 78:62]
|
||||
node _T_30 = bits(io.ifc_fetch_addr_f, 0, 0) @[el2_ifu_ifc_ctl.scala 78:129]
|
||||
node _T_31 = and(_T_29, _T_30) @[el2_ifu_ifc_ctl.scala 78:108]
|
||||
fetch_addr_next_0 <= _T_31 @[el2_ifu_ifc_ctl.scala 78:21]
|
||||
node _T_32 = cat(address_upper, fetch_addr_next_0) @[Cat.scala 29:58]
|
||||
fetch_addr_next <= _T_32 @[el2_ifu_ifc_ctl.scala 80:19]
|
||||
node _T_33 = not(idle) @[el2_ifu_ifc_ctl.scala 82:30]
|
||||
io.ifc_fetch_req_bf_raw <= _T_33 @[el2_ifu_ifc_ctl.scala 82:27]
|
||||
node _T_34 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctl.scala 84:91]
|
||||
node _T_35 = eq(_T_34, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 84:70]
|
||||
node _T_36 = and(fb_full_f_ns, _T_35) @[el2_ifu_ifc_ctl.scala 84:68]
|
||||
node _T_37 = eq(_T_36, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 84:53]
|
||||
node _T_38 = and(io.ifc_fetch_req_bf_raw, _T_37) @[el2_ifu_ifc_ctl.scala 84:51]
|
||||
node _T_39 = eq(dma_stall, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 85:5]
|
||||
node _T_40 = and(_T_38, _T_39) @[el2_ifu_ifc_ctl.scala 84:114]
|
||||
node _T_41 = eq(io.ic_write_stall, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 85:18]
|
||||
node _T_42 = and(_T_40, _T_41) @[el2_ifu_ifc_ctl.scala 85:16]
|
||||
node _T_43 = eq(io.dec_tlu_flush_noredir_wb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 85:39]
|
||||
node _T_44 = and(_T_42, _T_43) @[el2_ifu_ifc_ctl.scala 85:37]
|
||||
io.ifc_fetch_req_bf <= _T_44 @[el2_ifu_ifc_ctl.scala 84:23]
|
||||
node _T_45 = or(io.exu_flush_final, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 87:37]
|
||||
fetch_bf_en <= _T_45 @[el2_ifu_ifc_ctl.scala 87:15]
|
||||
node _T_46 = eq(io.ic_hit_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 89:34]
|
||||
node _T_47 = and(io.ifc_fetch_req_f, _T_46) @[el2_ifu_ifc_ctl.scala 89:32]
|
||||
node _T_48 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 89:49]
|
||||
node _T_49 = and(_T_47, _T_48) @[el2_ifu_ifc_ctl.scala 89:47]
|
||||
miss_f <= _T_49 @[el2_ifu_ifc_ctl.scala 89:10]
|
||||
node _T_50 = or(io.ifu_ic_mb_empty, io.exu_flush_final) @[el2_ifu_ifc_ctl.scala 91:39]
|
||||
node _T_51 = eq(dma_stall, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 91:63]
|
||||
node _T_52 = and(_T_50, _T_51) @[el2_ifu_ifc_ctl.scala 91:61]
|
||||
node _T_53 = eq(miss_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 91:76]
|
||||
node _T_54 = and(_T_52, _T_53) @[el2_ifu_ifc_ctl.scala 91:74]
|
||||
node _T_55 = eq(miss_a, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 91:86]
|
||||
node _T_56 = and(_T_54, _T_55) @[el2_ifu_ifc_ctl.scala 91:84]
|
||||
mb_empty_mod <= _T_56 @[el2_ifu_ifc_ctl.scala 91:16]
|
||||
node _T_57 = and(io.exu_flush_final, io.dec_tlu_flush_noredir_wb) @[el2_ifu_ifc_ctl.scala 93:35]
|
||||
goto_idle <= _T_57 @[el2_ifu_ifc_ctl.scala 93:13]
|
||||
node _T_58 = eq(io.dec_tlu_flush_noredir_wb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 95:38]
|
||||
node _T_59 = and(io.exu_flush_final, _T_58) @[el2_ifu_ifc_ctl.scala 95:36]
|
||||
node _T_60 = and(_T_59, idle) @[el2_ifu_ifc_ctl.scala 95:67]
|
||||
leave_idle <= _T_60 @[el2_ifu_ifc_ctl.scala 95:14]
|
||||
node _T_61 = bits(state, 1, 1) @[el2_ifu_ifc_ctl.scala 97:29]
|
||||
node _T_62 = eq(_T_61, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 97:23]
|
||||
node _T_63 = bits(state, 0, 0) @[el2_ifu_ifc_ctl.scala 97:40]
|
||||
node _T_64 = and(_T_62, _T_63) @[el2_ifu_ifc_ctl.scala 97:33]
|
||||
node _T_65 = and(_T_64, miss_f) @[el2_ifu_ifc_ctl.scala 97:44]
|
||||
node _T_66 = eq(goto_idle, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 97:55]
|
||||
node _T_67 = and(_T_65, _T_66) @[el2_ifu_ifc_ctl.scala 97:53]
|
||||
node _T_68 = bits(state, 1, 1) @[el2_ifu_ifc_ctl.scala 98:11]
|
||||
node _T_69 = eq(mb_empty_mod, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 98:17]
|
||||
node _T_70 = and(_T_68, _T_69) @[el2_ifu_ifc_ctl.scala 98:15]
|
||||
node _T_71 = eq(goto_idle, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 98:33]
|
||||
node _T_72 = and(_T_70, _T_71) @[el2_ifu_ifc_ctl.scala 98:31]
|
||||
node next_state_1 = or(_T_67, _T_72) @[el2_ifu_ifc_ctl.scala 97:67]
|
||||
node _T_73 = eq(goto_idle, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 100:23]
|
||||
node _T_74 = and(_T_73, leave_idle) @[el2_ifu_ifc_ctl.scala 100:34]
|
||||
node _T_75 = bits(state, 0, 0) @[el2_ifu_ifc_ctl.scala 100:56]
|
||||
node _T_76 = eq(goto_idle, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 100:62]
|
||||
node _T_77 = and(_T_75, _T_76) @[el2_ifu_ifc_ctl.scala 100:60]
|
||||
node next_state_0 = or(_T_74, _T_77) @[el2_ifu_ifc_ctl.scala 100:48]
|
||||
node _T_78 = cat(next_state_1, next_state_0) @[Cat.scala 29:58]
|
||||
reg _T_79 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 102:19]
|
||||
_T_79 <= _T_78 @[el2_ifu_ifc_ctl.scala 102:19]
|
||||
state <= _T_79 @[el2_ifu_ifc_ctl.scala 102:9]
|
||||
node _T_27 = bits(address_upper, 5, 5) @[el2_ifu_ifc_ctl.scala 78:39]
|
||||
node _T_28 = bits(io.ifc_fetch_addr_f, 5, 5) @[el2_ifu_ifc_ctl.scala 78:84]
|
||||
node _T_29 = xor(_T_27, _T_28) @[el2_ifu_ifc_ctl.scala 78:63]
|
||||
node _T_30 = eq(_T_29, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 78:24]
|
||||
node _T_31 = bits(io.ifc_fetch_addr_f, 0, 0) @[el2_ifu_ifc_ctl.scala 78:130]
|
||||
node _T_32 = and(_T_30, _T_31) @[el2_ifu_ifc_ctl.scala 78:109]
|
||||
fetch_addr_next_0 <= _T_32 @[el2_ifu_ifc_ctl.scala 78:21]
|
||||
node _T_33 = cat(address_upper, fetch_addr_next_0) @[Cat.scala 29:58]
|
||||
fetch_addr_next <= _T_33 @[el2_ifu_ifc_ctl.scala 80:19]
|
||||
node _T_34 = not(idle) @[el2_ifu_ifc_ctl.scala 82:30]
|
||||
io.ifc_fetch_req_bf_raw <= _T_34 @[el2_ifu_ifc_ctl.scala 82:27]
|
||||
node _T_35 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctl.scala 84:91]
|
||||
node _T_36 = eq(_T_35, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 84:70]
|
||||
node _T_37 = and(fb_full_f_ns, _T_36) @[el2_ifu_ifc_ctl.scala 84:68]
|
||||
node _T_38 = eq(_T_37, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 84:53]
|
||||
node _T_39 = and(io.ifc_fetch_req_bf_raw, _T_38) @[el2_ifu_ifc_ctl.scala 84:51]
|
||||
node _T_40 = eq(dma_stall, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 85:5]
|
||||
node _T_41 = and(_T_39, _T_40) @[el2_ifu_ifc_ctl.scala 84:114]
|
||||
node _T_42 = eq(io.ic_write_stall, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 85:18]
|
||||
node _T_43 = and(_T_41, _T_42) @[el2_ifu_ifc_ctl.scala 85:16]
|
||||
node _T_44 = eq(io.dec_tlu_flush_noredir_wb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 85:39]
|
||||
node _T_45 = and(_T_43, _T_44) @[el2_ifu_ifc_ctl.scala 85:37]
|
||||
io.ifc_fetch_req_bf <= _T_45 @[el2_ifu_ifc_ctl.scala 84:23]
|
||||
node _T_46 = or(io.exu_flush_final, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 87:37]
|
||||
fetch_bf_en <= _T_46 @[el2_ifu_ifc_ctl.scala 87:15]
|
||||
node _T_47 = eq(io.ic_hit_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 89:34]
|
||||
node _T_48 = and(io.ifc_fetch_req_f, _T_47) @[el2_ifu_ifc_ctl.scala 89:32]
|
||||
node _T_49 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 89:49]
|
||||
node _T_50 = and(_T_48, _T_49) @[el2_ifu_ifc_ctl.scala 89:47]
|
||||
miss_f <= _T_50 @[el2_ifu_ifc_ctl.scala 89:10]
|
||||
node _T_51 = or(io.ifu_ic_mb_empty, io.exu_flush_final) @[el2_ifu_ifc_ctl.scala 91:39]
|
||||
node _T_52 = eq(dma_stall, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 91:63]
|
||||
node _T_53 = and(_T_51, _T_52) @[el2_ifu_ifc_ctl.scala 91:61]
|
||||
node _T_54 = eq(miss_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 91:76]
|
||||
node _T_55 = and(_T_53, _T_54) @[el2_ifu_ifc_ctl.scala 91:74]
|
||||
node _T_56 = eq(miss_a, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 91:86]
|
||||
node _T_57 = and(_T_55, _T_56) @[el2_ifu_ifc_ctl.scala 91:84]
|
||||
mb_empty_mod <= _T_57 @[el2_ifu_ifc_ctl.scala 91:16]
|
||||
node _T_58 = and(io.exu_flush_final, io.dec_tlu_flush_noredir_wb) @[el2_ifu_ifc_ctl.scala 93:35]
|
||||
goto_idle <= _T_58 @[el2_ifu_ifc_ctl.scala 93:13]
|
||||
node _T_59 = eq(io.dec_tlu_flush_noredir_wb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 95:38]
|
||||
node _T_60 = and(io.exu_flush_final, _T_59) @[el2_ifu_ifc_ctl.scala 95:36]
|
||||
node _T_61 = and(_T_60, idle) @[el2_ifu_ifc_ctl.scala 95:67]
|
||||
leave_idle <= _T_61 @[el2_ifu_ifc_ctl.scala 95:14]
|
||||
node _T_62 = bits(state, 1, 1) @[el2_ifu_ifc_ctl.scala 97:29]
|
||||
node _T_63 = eq(_T_62, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 97:23]
|
||||
node _T_64 = bits(state, 0, 0) @[el2_ifu_ifc_ctl.scala 97:40]
|
||||
node _T_65 = and(_T_63, _T_64) @[el2_ifu_ifc_ctl.scala 97:33]
|
||||
node _T_66 = and(_T_65, miss_f) @[el2_ifu_ifc_ctl.scala 97:44]
|
||||
node _T_67 = eq(goto_idle, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 97:55]
|
||||
node _T_68 = and(_T_66, _T_67) @[el2_ifu_ifc_ctl.scala 97:53]
|
||||
node _T_69 = bits(state, 1, 1) @[el2_ifu_ifc_ctl.scala 98:11]
|
||||
node _T_70 = eq(mb_empty_mod, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 98:17]
|
||||
node _T_71 = and(_T_69, _T_70) @[el2_ifu_ifc_ctl.scala 98:15]
|
||||
node _T_72 = eq(goto_idle, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 98:33]
|
||||
node _T_73 = and(_T_71, _T_72) @[el2_ifu_ifc_ctl.scala 98:31]
|
||||
node next_state_1 = or(_T_68, _T_73) @[el2_ifu_ifc_ctl.scala 97:67]
|
||||
node _T_74 = eq(goto_idle, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 100:23]
|
||||
node _T_75 = and(_T_74, leave_idle) @[el2_ifu_ifc_ctl.scala 100:34]
|
||||
node _T_76 = bits(state, 0, 0) @[el2_ifu_ifc_ctl.scala 100:56]
|
||||
node _T_77 = eq(goto_idle, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 100:62]
|
||||
node _T_78 = and(_T_76, _T_77) @[el2_ifu_ifc_ctl.scala 100:60]
|
||||
node next_state_0 = or(_T_75, _T_78) @[el2_ifu_ifc_ctl.scala 100:48]
|
||||
node _T_79 = cat(next_state_1, next_state_0) @[Cat.scala 29:58]
|
||||
reg _T_80 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 102:19]
|
||||
_T_80 <= _T_79 @[el2_ifu_ifc_ctl.scala 102:19]
|
||||
state <= _T_80 @[el2_ifu_ifc_ctl.scala 102:9]
|
||||
flush_fb <= io.exu_flush_final @[el2_ifu_ifc_ctl.scala 104:12]
|
||||
node _T_80 = eq(io.ifu_fb_consume2, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 106:38]
|
||||
node _T_81 = and(io.ifu_fb_consume1, _T_80) @[el2_ifu_ifc_ctl.scala 106:36]
|
||||
node _T_82 = eq(io.ifc_fetch_req_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 106:61]
|
||||
node _T_83 = or(_T_82, miss_f) @[el2_ifu_ifc_ctl.scala 106:81]
|
||||
node _T_84 = and(_T_81, _T_83) @[el2_ifu_ifc_ctl.scala 106:58]
|
||||
node _T_85 = and(io.ifu_fb_consume2, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 107:25]
|
||||
node _T_86 = or(_T_84, _T_85) @[el2_ifu_ifc_ctl.scala 106:92]
|
||||
fb_right <= _T_86 @[el2_ifu_ifc_ctl.scala 106:12]
|
||||
node _T_87 = not(io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 109:39]
|
||||
node _T_88 = or(_T_87, miss_f) @[el2_ifu_ifc_ctl.scala 109:59]
|
||||
node _T_89 = and(io.ifu_fb_consume2, _T_88) @[el2_ifu_ifc_ctl.scala 109:36]
|
||||
fb_right2 <= _T_89 @[el2_ifu_ifc_ctl.scala 109:13]
|
||||
node _T_90 = or(io.ifu_fb_consume1, io.ifu_fb_consume2) @[el2_ifu_ifc_ctl.scala 110:56]
|
||||
node _T_91 = eq(_T_90, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 110:35]
|
||||
node _T_92 = and(io.ifc_fetch_req_f, _T_91) @[el2_ifu_ifc_ctl.scala 110:33]
|
||||
node _T_93 = eq(miss_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 110:80]
|
||||
node _T_94 = and(_T_92, _T_93) @[el2_ifu_ifc_ctl.scala 110:78]
|
||||
fb_left <= _T_94 @[el2_ifu_ifc_ctl.scala 110:11]
|
||||
node _T_95 = bits(flush_fb, 0, 0) @[el2_ifu_ifc_ctl.scala 112:37]
|
||||
node _T_96 = eq(flush_fb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 113:6]
|
||||
node _T_97 = and(_T_96, fb_right) @[el2_ifu_ifc_ctl.scala 113:16]
|
||||
node _T_98 = bits(_T_97, 0, 0) @[el2_ifu_ifc_ctl.scala 113:28]
|
||||
node _T_99 = bits(fb_write_f, 3, 1) @[el2_ifu_ifc_ctl.scala 113:62]
|
||||
node _T_100 = cat(UInt<1>("h00"), _T_99) @[Cat.scala 29:58]
|
||||
node _T_101 = eq(flush_fb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 114:6]
|
||||
node _T_102 = and(_T_101, fb_right2) @[el2_ifu_ifc_ctl.scala 114:16]
|
||||
node _T_103 = bits(_T_102, 0, 0) @[el2_ifu_ifc_ctl.scala 114:29]
|
||||
node _T_104 = bits(fb_write_f, 3, 2) @[el2_ifu_ifc_ctl.scala 114:63]
|
||||
node _T_105 = cat(UInt<2>("h00"), _T_104) @[Cat.scala 29:58]
|
||||
node _T_106 = eq(flush_fb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 115:6]
|
||||
node _T_107 = and(_T_106, fb_left) @[el2_ifu_ifc_ctl.scala 115:16]
|
||||
node _T_108 = bits(_T_107, 0, 0) @[el2_ifu_ifc_ctl.scala 115:27]
|
||||
node _T_109 = bits(fb_write_f, 2, 0) @[el2_ifu_ifc_ctl.scala 115:51]
|
||||
node _T_110 = cat(_T_109, UInt<1>("h00")) @[Cat.scala 29:58]
|
||||
node _T_111 = eq(flush_fb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 116:6]
|
||||
node _T_112 = eq(fb_right, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 116:18]
|
||||
node _T_113 = and(_T_111, _T_112) @[el2_ifu_ifc_ctl.scala 116:16]
|
||||
node _T_114 = eq(fb_right2, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 116:30]
|
||||
node _T_115 = and(_T_113, _T_114) @[el2_ifu_ifc_ctl.scala 116:28]
|
||||
node _T_116 = eq(fb_left, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 116:43]
|
||||
node _T_117 = and(_T_115, _T_116) @[el2_ifu_ifc_ctl.scala 116:41]
|
||||
node _T_118 = bits(_T_117, 0, 0) @[el2_ifu_ifc_ctl.scala 116:53]
|
||||
node _T_119 = bits(fb_write_f, 3, 0) @[el2_ifu_ifc_ctl.scala 116:73]
|
||||
node _T_120 = mux(_T_95, UInt<4>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_121 = mux(_T_98, _T_100, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_122 = mux(_T_103, _T_105, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_123 = mux(_T_108, _T_110, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_124 = mux(_T_118, _T_119, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_125 = or(_T_120, _T_121) @[Mux.scala 27:72]
|
||||
node _T_126 = or(_T_125, _T_122) @[Mux.scala 27:72]
|
||||
node _T_81 = eq(io.ifu_fb_consume2, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 106:38]
|
||||
node _T_82 = and(io.ifu_fb_consume1, _T_81) @[el2_ifu_ifc_ctl.scala 106:36]
|
||||
node _T_83 = eq(io.ifc_fetch_req_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 106:61]
|
||||
node _T_84 = or(_T_83, miss_f) @[el2_ifu_ifc_ctl.scala 106:81]
|
||||
node _T_85 = and(_T_82, _T_84) @[el2_ifu_ifc_ctl.scala 106:58]
|
||||
node _T_86 = and(io.ifu_fb_consume2, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 107:25]
|
||||
node _T_87 = or(_T_85, _T_86) @[el2_ifu_ifc_ctl.scala 106:92]
|
||||
fb_right <= _T_87 @[el2_ifu_ifc_ctl.scala 106:12]
|
||||
node _T_88 = not(io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 109:39]
|
||||
node _T_89 = or(_T_88, miss_f) @[el2_ifu_ifc_ctl.scala 109:59]
|
||||
node _T_90 = and(io.ifu_fb_consume2, _T_89) @[el2_ifu_ifc_ctl.scala 109:36]
|
||||
fb_right2 <= _T_90 @[el2_ifu_ifc_ctl.scala 109:13]
|
||||
node _T_91 = or(io.ifu_fb_consume1, io.ifu_fb_consume2) @[el2_ifu_ifc_ctl.scala 110:56]
|
||||
node _T_92 = eq(_T_91, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 110:35]
|
||||
node _T_93 = and(io.ifc_fetch_req_f, _T_92) @[el2_ifu_ifc_ctl.scala 110:33]
|
||||
node _T_94 = eq(miss_f, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 110:80]
|
||||
node _T_95 = and(_T_93, _T_94) @[el2_ifu_ifc_ctl.scala 110:78]
|
||||
fb_left <= _T_95 @[el2_ifu_ifc_ctl.scala 110:11]
|
||||
node _T_96 = bits(flush_fb, 0, 0) @[el2_ifu_ifc_ctl.scala 112:37]
|
||||
node _T_97 = eq(flush_fb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 113:6]
|
||||
node _T_98 = and(_T_97, fb_right) @[el2_ifu_ifc_ctl.scala 113:16]
|
||||
node _T_99 = bits(_T_98, 0, 0) @[el2_ifu_ifc_ctl.scala 113:28]
|
||||
node _T_100 = bits(fb_write_f, 3, 1) @[el2_ifu_ifc_ctl.scala 113:62]
|
||||
node _T_101 = cat(UInt<1>("h00"), _T_100) @[Cat.scala 29:58]
|
||||
node _T_102 = eq(flush_fb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 114:6]
|
||||
node _T_103 = and(_T_102, fb_right2) @[el2_ifu_ifc_ctl.scala 114:16]
|
||||
node _T_104 = bits(_T_103, 0, 0) @[el2_ifu_ifc_ctl.scala 114:29]
|
||||
node _T_105 = bits(fb_write_f, 3, 2) @[el2_ifu_ifc_ctl.scala 114:63]
|
||||
node _T_106 = cat(UInt<2>("h00"), _T_105) @[Cat.scala 29:58]
|
||||
node _T_107 = eq(flush_fb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 115:6]
|
||||
node _T_108 = and(_T_107, fb_left) @[el2_ifu_ifc_ctl.scala 115:16]
|
||||
node _T_109 = bits(_T_108, 0, 0) @[el2_ifu_ifc_ctl.scala 115:27]
|
||||
node _T_110 = bits(fb_write_f, 2, 0) @[el2_ifu_ifc_ctl.scala 115:51]
|
||||
node _T_111 = cat(_T_110, UInt<1>("h00")) @[Cat.scala 29:58]
|
||||
node _T_112 = eq(flush_fb, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 116:6]
|
||||
node _T_113 = eq(fb_right, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 116:18]
|
||||
node _T_114 = and(_T_112, _T_113) @[el2_ifu_ifc_ctl.scala 116:16]
|
||||
node _T_115 = eq(fb_right2, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 116:30]
|
||||
node _T_116 = and(_T_114, _T_115) @[el2_ifu_ifc_ctl.scala 116:28]
|
||||
node _T_117 = eq(fb_left, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 116:43]
|
||||
node _T_118 = and(_T_116, _T_117) @[el2_ifu_ifc_ctl.scala 116:41]
|
||||
node _T_119 = bits(_T_118, 0, 0) @[el2_ifu_ifc_ctl.scala 116:53]
|
||||
node _T_120 = bits(fb_write_f, 3, 0) @[el2_ifu_ifc_ctl.scala 116:73]
|
||||
node _T_121 = mux(_T_96, UInt<4>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_122 = mux(_T_99, _T_101, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_123 = mux(_T_104, _T_106, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_124 = mux(_T_109, _T_111, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_125 = mux(_T_119, _T_120, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_126 = or(_T_121, _T_122) @[Mux.scala 27:72]
|
||||
node _T_127 = or(_T_126, _T_123) @[Mux.scala 27:72]
|
||||
node _T_128 = or(_T_127, _T_124) @[Mux.scala 27:72]
|
||||
wire _T_129 : UInt<4> @[Mux.scala 27:72]
|
||||
_T_129 <= _T_128 @[Mux.scala 27:72]
|
||||
fb_write_ns <= _T_129 @[el2_ifu_ifc_ctl.scala 112:15]
|
||||
node _T_130 = bits(fb_write_ns, 3, 3) @[el2_ifu_ifc_ctl.scala 119:38]
|
||||
reg _T_131 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 119:26]
|
||||
_T_131 <= _T_130 @[el2_ifu_ifc_ctl.scala 119:26]
|
||||
fb_full_f_ns <= _T_131 @[el2_ifu_ifc_ctl.scala 119:16]
|
||||
node _T_132 = eq(state, UInt<2>("h00")) @[el2_ifu_ifc_ctl.scala 121:17]
|
||||
idle <= _T_132 @[el2_ifu_ifc_ctl.scala 121:8]
|
||||
node _T_133 = eq(state, UInt<2>("h03")) @[el2_ifu_ifc_ctl.scala 122:16]
|
||||
wfm <= _T_133 @[el2_ifu_ifc_ctl.scala 122:7]
|
||||
node _T_134 = bits(fb_write_ns, 3, 3) @[el2_ifu_ifc_ctl.scala 124:30]
|
||||
fb_full_f_ns <= _T_134 @[el2_ifu_ifc_ctl.scala 124:16]
|
||||
node _T_129 = or(_T_128, _T_125) @[Mux.scala 27:72]
|
||||
wire _T_130 : UInt<4> @[Mux.scala 27:72]
|
||||
_T_130 <= _T_129 @[Mux.scala 27:72]
|
||||
fb_write_ns <= _T_130 @[el2_ifu_ifc_ctl.scala 112:15]
|
||||
node _T_131 = bits(fb_write_ns, 3, 3) @[el2_ifu_ifc_ctl.scala 119:38]
|
||||
reg _T_132 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 119:26]
|
||||
_T_132 <= _T_131 @[el2_ifu_ifc_ctl.scala 119:26]
|
||||
fb_full_f_ns <= _T_132 @[el2_ifu_ifc_ctl.scala 119:16]
|
||||
node _T_133 = eq(state, UInt<2>("h00")) @[el2_ifu_ifc_ctl.scala 121:17]
|
||||
idle <= _T_133 @[el2_ifu_ifc_ctl.scala 121:8]
|
||||
node _T_134 = eq(state, UInt<2>("h03")) @[el2_ifu_ifc_ctl.scala 122:16]
|
||||
wfm <= _T_134 @[el2_ifu_ifc_ctl.scala 122:7]
|
||||
node _T_135 = bits(fb_write_ns, 3, 3) @[el2_ifu_ifc_ctl.scala 124:30]
|
||||
fb_full_f_ns <= _T_135 @[el2_ifu_ifc_ctl.scala 124:16]
|
||||
reg fb_full_f : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 125:26]
|
||||
fb_full_f <= fb_full_f_ns @[el2_ifu_ifc_ctl.scala 125:26]
|
||||
reg _T_135 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 126:24]
|
||||
_T_135 <= fb_write_ns @[el2_ifu_ifc_ctl.scala 126:24]
|
||||
fb_write_f <= _T_135 @[el2_ifu_ifc_ctl.scala 126:14]
|
||||
node _T_136 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctl.scala 129:40]
|
||||
node _T_137 = or(_T_136, io.exu_flush_final) @[el2_ifu_ifc_ctl.scala 129:61]
|
||||
node _T_138 = eq(_T_137, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 129:19]
|
||||
node _T_139 = and(fb_full_f, _T_138) @[el2_ifu_ifc_ctl.scala 129:17]
|
||||
node _T_140 = or(_T_139, dma_stall) @[el2_ifu_ifc_ctl.scala 129:84]
|
||||
node _T_141 = and(io.ifc_fetch_req_bf_raw, _T_140) @[el2_ifu_ifc_ctl.scala 128:60]
|
||||
node _T_142 = or(wfm, _T_141) @[el2_ifu_ifc_ctl.scala 128:33]
|
||||
io.ifu_pmu_fetch_stall <= _T_142 @[el2_ifu_ifc_ctl.scala 128:26]
|
||||
node _T_143 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
|
||||
node _T_144 = bits(_T_143, 31, 28) @[el2_lib.scala 211:25]
|
||||
node iccm_acc_in_region_bf = eq(_T_144, UInt<4>("h0e")) @[el2_lib.scala 211:47]
|
||||
node _T_145 = bits(_T_143, 31, 16) @[el2_lib.scala 214:14]
|
||||
node iccm_acc_in_range_bf = eq(_T_145, UInt<16>("h0ee00")) @[el2_lib.scala 214:29]
|
||||
reg _T_136 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 126:24]
|
||||
_T_136 <= fb_write_ns @[el2_ifu_ifc_ctl.scala 126:24]
|
||||
fb_write_f <= _T_136 @[el2_ifu_ifc_ctl.scala 126:14]
|
||||
node _T_137 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctl.scala 129:40]
|
||||
node _T_138 = or(_T_137, io.exu_flush_final) @[el2_ifu_ifc_ctl.scala 129:61]
|
||||
node _T_139 = eq(_T_138, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 129:19]
|
||||
node _T_140 = and(fb_full_f, _T_139) @[el2_ifu_ifc_ctl.scala 129:17]
|
||||
node _T_141 = or(_T_140, dma_stall) @[el2_ifu_ifc_ctl.scala 129:84]
|
||||
node _T_142 = and(io.ifc_fetch_req_bf_raw, _T_141) @[el2_ifu_ifc_ctl.scala 128:60]
|
||||
node _T_143 = or(wfm, _T_142) @[el2_ifu_ifc_ctl.scala 128:33]
|
||||
io.ifu_pmu_fetch_stall <= _T_143 @[el2_ifu_ifc_ctl.scala 128:26]
|
||||
node _T_144 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
|
||||
node _T_145 = bits(_T_144, 31, 28) @[el2_lib.scala 211:25]
|
||||
node iccm_acc_in_region_bf = eq(_T_145, UInt<4>("h0e")) @[el2_lib.scala 211:47]
|
||||
node _T_146 = bits(_T_144, 31, 16) @[el2_lib.scala 214:14]
|
||||
node iccm_acc_in_range_bf = eq(_T_146, UInt<16>("h0ee00")) @[el2_lib.scala 214:29]
|
||||
io.ifc_iccm_access_bf <= iccm_acc_in_range_bf @[el2_ifu_ifc_ctl.scala 134:25]
|
||||
node _T_146 = eq(io.ifc_iccm_access_bf, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 135:30]
|
||||
node _T_147 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctl.scala 136:39]
|
||||
node _T_148 = eq(_T_147, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 136:18]
|
||||
node _T_149 = and(fb_full_f, _T_148) @[el2_ifu_ifc_ctl.scala 136:16]
|
||||
node _T_150 = or(_T_146, _T_149) @[el2_ifu_ifc_ctl.scala 135:53]
|
||||
node _T_151 = eq(io.ifc_fetch_req_bf, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 137:13]
|
||||
node _T_152 = and(wfm, _T_151) @[el2_ifu_ifc_ctl.scala 137:11]
|
||||
node _T_153 = or(_T_150, _T_152) @[el2_ifu_ifc_ctl.scala 136:62]
|
||||
node _T_154 = or(_T_153, idle) @[el2_ifu_ifc_ctl.scala 137:35]
|
||||
node _T_155 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 137:46]
|
||||
node _T_156 = and(_T_154, _T_155) @[el2_ifu_ifc_ctl.scala 137:44]
|
||||
node _T_157 = or(_T_156, dma_iccm_stall_any_f) @[el2_ifu_ifc_ctl.scala 137:67]
|
||||
io.ifc_dma_access_ok <= _T_157 @[el2_ifu_ifc_ctl.scala 135:24]
|
||||
node _T_158 = eq(iccm_acc_in_range_bf, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 139:33]
|
||||
node _T_159 = and(_T_158, iccm_acc_in_region_bf) @[el2_ifu_ifc_ctl.scala 139:55]
|
||||
io.ifc_region_acc_fault_bf <= _T_159 @[el2_ifu_ifc_ctl.scala 139:30]
|
||||
node _T_160 = bits(io.ifc_fetch_addr_bf, 30, 27) @[el2_ifu_ifc_ctl.scala 140:78]
|
||||
node _T_161 = cat(_T_160, UInt<1>("h00")) @[Cat.scala 29:58]
|
||||
node _T_162 = dshr(io.dec_tlu_mrac_ff, _T_161) @[el2_ifu_ifc_ctl.scala 140:53]
|
||||
node _T_163 = bits(_T_162, 0, 0) @[el2_ifu_ifc_ctl.scala 140:53]
|
||||
node _T_164 = not(_T_163) @[el2_ifu_ifc_ctl.scala 140:34]
|
||||
io.ifc_fetch_uncacheable_bf <= _T_164 @[el2_ifu_ifc_ctl.scala 140:31]
|
||||
reg _T_165 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 142:32]
|
||||
_T_165 <= io.ifc_fetch_req_bf @[el2_ifu_ifc_ctl.scala 142:32]
|
||||
io.ifc_fetch_req_f <= _T_165 @[el2_ifu_ifc_ctl.scala 142:22]
|
||||
node _T_166 = or(io.exu_flush_final, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 144:88]
|
||||
reg _T_167 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when _T_166 : @[Reg.scala 28:19]
|
||||
_T_167 <= io.ifc_fetch_addr_bf @[Reg.scala 28:23]
|
||||
node _T_147 = eq(io.ifc_iccm_access_bf, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 135:30]
|
||||
node _T_148 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[el2_ifu_ifc_ctl.scala 136:39]
|
||||
node _T_149 = eq(_T_148, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 136:18]
|
||||
node _T_150 = and(fb_full_f, _T_149) @[el2_ifu_ifc_ctl.scala 136:16]
|
||||
node _T_151 = or(_T_147, _T_150) @[el2_ifu_ifc_ctl.scala 135:53]
|
||||
node _T_152 = eq(io.ifc_fetch_req_bf, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 137:13]
|
||||
node _T_153 = and(wfm, _T_152) @[el2_ifu_ifc_ctl.scala 137:11]
|
||||
node _T_154 = or(_T_151, _T_153) @[el2_ifu_ifc_ctl.scala 136:62]
|
||||
node _T_155 = or(_T_154, idle) @[el2_ifu_ifc_ctl.scala 137:35]
|
||||
node _T_156 = eq(io.exu_flush_final, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 137:46]
|
||||
node _T_157 = and(_T_155, _T_156) @[el2_ifu_ifc_ctl.scala 137:44]
|
||||
node _T_158 = or(_T_157, dma_iccm_stall_any_f) @[el2_ifu_ifc_ctl.scala 137:67]
|
||||
io.ifc_dma_access_ok <= _T_158 @[el2_ifu_ifc_ctl.scala 135:24]
|
||||
node _T_159 = eq(iccm_acc_in_range_bf, UInt<1>("h00")) @[el2_ifu_ifc_ctl.scala 139:33]
|
||||
node _T_160 = and(_T_159, iccm_acc_in_region_bf) @[el2_ifu_ifc_ctl.scala 139:55]
|
||||
io.ifc_region_acc_fault_bf <= _T_160 @[el2_ifu_ifc_ctl.scala 139:30]
|
||||
node _T_161 = bits(io.ifc_fetch_addr_bf, 30, 27) @[el2_ifu_ifc_ctl.scala 140:78]
|
||||
node _T_162 = cat(_T_161, UInt<1>("h00")) @[Cat.scala 29:58]
|
||||
node _T_163 = dshr(io.dec_tlu_mrac_ff, _T_162) @[el2_ifu_ifc_ctl.scala 140:53]
|
||||
node _T_164 = bits(_T_163, 0, 0) @[el2_ifu_ifc_ctl.scala 140:53]
|
||||
node _T_165 = not(_T_164) @[el2_ifu_ifc_ctl.scala 140:34]
|
||||
io.ifc_fetch_uncacheable_bf <= _T_165 @[el2_ifu_ifc_ctl.scala 140:31]
|
||||
reg _T_166 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_ifc_ctl.scala 142:32]
|
||||
_T_166 <= io.ifc_fetch_req_bf @[el2_ifu_ifc_ctl.scala 142:32]
|
||||
io.ifc_fetch_req_f <= _T_166 @[el2_ifu_ifc_ctl.scala 142:22]
|
||||
node _T_167 = or(io.exu_flush_final, io.ifc_fetch_req_f) @[el2_ifu_ifc_ctl.scala 144:88]
|
||||
reg _T_168 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when _T_167 : @[Reg.scala 28:19]
|
||||
_T_168 <= io.ifc_fetch_addr_bf @[Reg.scala 28:23]
|
||||
skip @[Reg.scala 28:19]
|
||||
io.ifc_fetch_addr_f <= _T_167 @[el2_ifu_ifc_ctl.scala 144:23]
|
||||
io.ifc_fetch_addr_f <= _T_168 @[el2_ifu_ifc_ctl.scala 144:23]
|
||||
|
||||
|
|
|
|||
|
|
@ -55,115 +55,116 @@ module el2_ifu_ifc_ctl(
|
|||
wire [30:0] _T_18 = sel_last_addr_bf ? io_ifc_fetch_addr_f : 31'h0; // @[Mux.scala 27:72]
|
||||
wire [30:0] _T_19 = sel_btb_addr_bf ? io_ifu_bp_btb_target_f : 31'h0; // @[Mux.scala 27:72]
|
||||
wire [29:0] address_upper = io_ifc_fetch_addr_f[30:1] + 30'h1; // @[el2_ifu_ifc_ctl.scala 77:48]
|
||||
wire _T_29 = address_upper[5] ^ io_ifc_fetch_addr_f[5]; // @[el2_ifu_ifc_ctl.scala 78:62]
|
||||
wire fetch_addr_next_0 = _T_29 & io_ifc_fetch_addr_f[0]; // @[el2_ifu_ifc_ctl.scala 78:108]
|
||||
wire _T_29 = address_upper[5] ^ io_ifc_fetch_addr_f[5]; // @[el2_ifu_ifc_ctl.scala 78:63]
|
||||
wire _T_30 = ~_T_29; // @[el2_ifu_ifc_ctl.scala 78:24]
|
||||
wire fetch_addr_next_0 = _T_30 & io_ifc_fetch_addr_f[0]; // @[el2_ifu_ifc_ctl.scala 78:109]
|
||||
wire [30:0] fetch_addr_next = {address_upper,fetch_addr_next_0}; // @[Cat.scala 29:58]
|
||||
wire [30:0] _T_20 = sel_next_addr_bf ? fetch_addr_next : 31'h0; // @[Mux.scala 27:72]
|
||||
wire [30:0] _T_21 = _T_17 | _T_18; // @[Mux.scala 27:72]
|
||||
wire [30:0] _T_22 = _T_21 | _T_19; // @[Mux.scala 27:72]
|
||||
reg [1:0] state; // @[el2_ifu_ifc_ctl.scala 102:19]
|
||||
wire idle = state == 2'h0; // @[el2_ifu_ifc_ctl.scala 121:17]
|
||||
wire _T_34 = io_ifu_fb_consume2 | io_ifu_fb_consume1; // @[el2_ifu_ifc_ctl.scala 84:91]
|
||||
wire _T_35 = ~_T_34; // @[el2_ifu_ifc_ctl.scala 84:70]
|
||||
wire [3:0] _T_120 = io_exu_flush_final ? 4'h1 : 4'h0; // @[Mux.scala 27:72]
|
||||
wire _T_80 = ~io_ifu_fb_consume2; // @[el2_ifu_ifc_ctl.scala 106:38]
|
||||
wire _T_81 = io_ifu_fb_consume1 & _T_80; // @[el2_ifu_ifc_ctl.scala 106:36]
|
||||
wire _T_47 = io_ifc_fetch_req_f & _T_4; // @[el2_ifu_ifc_ctl.scala 89:32]
|
||||
wire miss_f = _T_47 & _T_2; // @[el2_ifu_ifc_ctl.scala 89:47]
|
||||
wire _T_83 = _T_3 | miss_f; // @[el2_ifu_ifc_ctl.scala 106:81]
|
||||
wire _T_84 = _T_81 & _T_83; // @[el2_ifu_ifc_ctl.scala 106:58]
|
||||
wire _T_85 = io_ifu_fb_consume2 & io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctl.scala 107:25]
|
||||
wire fb_right = _T_84 | _T_85; // @[el2_ifu_ifc_ctl.scala 106:92]
|
||||
wire _T_97 = _T_2 & fb_right; // @[el2_ifu_ifc_ctl.scala 113:16]
|
||||
wire _T_35 = io_ifu_fb_consume2 | io_ifu_fb_consume1; // @[el2_ifu_ifc_ctl.scala 84:91]
|
||||
wire _T_36 = ~_T_35; // @[el2_ifu_ifc_ctl.scala 84:70]
|
||||
wire [3:0] _T_121 = io_exu_flush_final ? 4'h1 : 4'h0; // @[Mux.scala 27:72]
|
||||
wire _T_81 = ~io_ifu_fb_consume2; // @[el2_ifu_ifc_ctl.scala 106:38]
|
||||
wire _T_82 = io_ifu_fb_consume1 & _T_81; // @[el2_ifu_ifc_ctl.scala 106:36]
|
||||
wire _T_48 = io_ifc_fetch_req_f & _T_4; // @[el2_ifu_ifc_ctl.scala 89:32]
|
||||
wire miss_f = _T_48 & _T_2; // @[el2_ifu_ifc_ctl.scala 89:47]
|
||||
wire _T_84 = _T_3 | miss_f; // @[el2_ifu_ifc_ctl.scala 106:81]
|
||||
wire _T_85 = _T_82 & _T_84; // @[el2_ifu_ifc_ctl.scala 106:58]
|
||||
wire _T_86 = io_ifu_fb_consume2 & io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctl.scala 107:25]
|
||||
wire fb_right = _T_85 | _T_86; // @[el2_ifu_ifc_ctl.scala 106:92]
|
||||
wire _T_98 = _T_2 & fb_right; // @[el2_ifu_ifc_ctl.scala 113:16]
|
||||
reg [3:0] fb_write_f; // @[el2_ifu_ifc_ctl.scala 126:24]
|
||||
wire [3:0] _T_100 = {1'h0,fb_write_f[3:1]}; // @[Cat.scala 29:58]
|
||||
wire [3:0] _T_121 = _T_97 ? _T_100 : 4'h0; // @[Mux.scala 27:72]
|
||||
wire [3:0] _T_125 = _T_120 | _T_121; // @[Mux.scala 27:72]
|
||||
wire fb_right2 = io_ifu_fb_consume2 & _T_83; // @[el2_ifu_ifc_ctl.scala 109:36]
|
||||
wire _T_102 = _T_2 & fb_right2; // @[el2_ifu_ifc_ctl.scala 114:16]
|
||||
wire [3:0] _T_105 = {2'h0,fb_write_f[3:2]}; // @[Cat.scala 29:58]
|
||||
wire [3:0] _T_122 = _T_102 ? _T_105 : 4'h0; // @[Mux.scala 27:72]
|
||||
wire [3:0] _T_126 = _T_125 | _T_122; // @[Mux.scala 27:72]
|
||||
wire _T_90 = io_ifu_fb_consume1 | io_ifu_fb_consume2; // @[el2_ifu_ifc_ctl.scala 110:56]
|
||||
wire _T_91 = ~_T_90; // @[el2_ifu_ifc_ctl.scala 110:35]
|
||||
wire _T_92 = io_ifc_fetch_req_f & _T_91; // @[el2_ifu_ifc_ctl.scala 110:33]
|
||||
wire _T_93 = ~miss_f; // @[el2_ifu_ifc_ctl.scala 110:80]
|
||||
wire fb_left = _T_92 & _T_93; // @[el2_ifu_ifc_ctl.scala 110:78]
|
||||
wire _T_107 = _T_2 & fb_left; // @[el2_ifu_ifc_ctl.scala 115:16]
|
||||
wire [3:0] _T_110 = {fb_write_f[2:0],1'h0}; // @[Cat.scala 29:58]
|
||||
wire [3:0] _T_123 = _T_107 ? _T_110 : 4'h0; // @[Mux.scala 27:72]
|
||||
wire [3:0] _T_101 = {1'h0,fb_write_f[3:1]}; // @[Cat.scala 29:58]
|
||||
wire [3:0] _T_122 = _T_98 ? _T_101 : 4'h0; // @[Mux.scala 27:72]
|
||||
wire [3:0] _T_126 = _T_121 | _T_122; // @[Mux.scala 27:72]
|
||||
wire fb_right2 = io_ifu_fb_consume2 & _T_84; // @[el2_ifu_ifc_ctl.scala 109:36]
|
||||
wire _T_103 = _T_2 & fb_right2; // @[el2_ifu_ifc_ctl.scala 114:16]
|
||||
wire [3:0] _T_106 = {2'h0,fb_write_f[3:2]}; // @[Cat.scala 29:58]
|
||||
wire [3:0] _T_123 = _T_103 ? _T_106 : 4'h0; // @[Mux.scala 27:72]
|
||||
wire [3:0] _T_127 = _T_126 | _T_123; // @[Mux.scala 27:72]
|
||||
wire _T_112 = ~fb_right; // @[el2_ifu_ifc_ctl.scala 116:18]
|
||||
wire _T_113 = _T_2 & _T_112; // @[el2_ifu_ifc_ctl.scala 116:16]
|
||||
wire _T_114 = ~fb_right2; // @[el2_ifu_ifc_ctl.scala 116:30]
|
||||
wire _T_115 = _T_113 & _T_114; // @[el2_ifu_ifc_ctl.scala 116:28]
|
||||
wire _T_116 = ~fb_left; // @[el2_ifu_ifc_ctl.scala 116:43]
|
||||
wire _T_117 = _T_115 & _T_116; // @[el2_ifu_ifc_ctl.scala 116:41]
|
||||
wire [3:0] _T_124 = _T_117 ? fb_write_f : 4'h0; // @[Mux.scala 27:72]
|
||||
wire [3:0] fb_write_ns = _T_127 | _T_124; // @[Mux.scala 27:72]
|
||||
wire _T_91 = io_ifu_fb_consume1 | io_ifu_fb_consume2; // @[el2_ifu_ifc_ctl.scala 110:56]
|
||||
wire _T_92 = ~_T_91; // @[el2_ifu_ifc_ctl.scala 110:35]
|
||||
wire _T_93 = io_ifc_fetch_req_f & _T_92; // @[el2_ifu_ifc_ctl.scala 110:33]
|
||||
wire _T_94 = ~miss_f; // @[el2_ifu_ifc_ctl.scala 110:80]
|
||||
wire fb_left = _T_93 & _T_94; // @[el2_ifu_ifc_ctl.scala 110:78]
|
||||
wire _T_108 = _T_2 & fb_left; // @[el2_ifu_ifc_ctl.scala 115:16]
|
||||
wire [3:0] _T_111 = {fb_write_f[2:0],1'h0}; // @[Cat.scala 29:58]
|
||||
wire [3:0] _T_124 = _T_108 ? _T_111 : 4'h0; // @[Mux.scala 27:72]
|
||||
wire [3:0] _T_128 = _T_127 | _T_124; // @[Mux.scala 27:72]
|
||||
wire _T_113 = ~fb_right; // @[el2_ifu_ifc_ctl.scala 116:18]
|
||||
wire _T_114 = _T_2 & _T_113; // @[el2_ifu_ifc_ctl.scala 116:16]
|
||||
wire _T_115 = ~fb_right2; // @[el2_ifu_ifc_ctl.scala 116:30]
|
||||
wire _T_116 = _T_114 & _T_115; // @[el2_ifu_ifc_ctl.scala 116:28]
|
||||
wire _T_117 = ~fb_left; // @[el2_ifu_ifc_ctl.scala 116:43]
|
||||
wire _T_118 = _T_116 & _T_117; // @[el2_ifu_ifc_ctl.scala 116:41]
|
||||
wire [3:0] _T_125 = _T_118 ? fb_write_f : 4'h0; // @[Mux.scala 27:72]
|
||||
wire [3:0] fb_write_ns = _T_128 | _T_125; // @[Mux.scala 27:72]
|
||||
wire fb_full_f_ns = fb_write_ns[3]; // @[el2_ifu_ifc_ctl.scala 124:30]
|
||||
wire _T_36 = fb_full_f_ns & _T_35; // @[el2_ifu_ifc_ctl.scala 84:68]
|
||||
wire _T_37 = ~_T_36; // @[el2_ifu_ifc_ctl.scala 84:53]
|
||||
wire _T_38 = io_ifc_fetch_req_bf_raw & _T_37; // @[el2_ifu_ifc_ctl.scala 84:51]
|
||||
wire _T_39 = ~dma_stall; // @[el2_ifu_ifc_ctl.scala 85:5]
|
||||
wire _T_40 = _T_38 & _T_39; // @[el2_ifu_ifc_ctl.scala 84:114]
|
||||
wire _T_41 = ~io_ic_write_stall; // @[el2_ifu_ifc_ctl.scala 85:18]
|
||||
wire _T_42 = _T_40 & _T_41; // @[el2_ifu_ifc_ctl.scala 85:16]
|
||||
wire _T_43 = ~io_dec_tlu_flush_noredir_wb; // @[el2_ifu_ifc_ctl.scala 85:39]
|
||||
wire _T_37 = fb_full_f_ns & _T_36; // @[el2_ifu_ifc_ctl.scala 84:68]
|
||||
wire _T_38 = ~_T_37; // @[el2_ifu_ifc_ctl.scala 84:53]
|
||||
wire _T_39 = io_ifc_fetch_req_bf_raw & _T_38; // @[el2_ifu_ifc_ctl.scala 84:51]
|
||||
wire _T_40 = ~dma_stall; // @[el2_ifu_ifc_ctl.scala 85:5]
|
||||
wire _T_41 = _T_39 & _T_40; // @[el2_ifu_ifc_ctl.scala 84:114]
|
||||
wire _T_42 = ~io_ic_write_stall; // @[el2_ifu_ifc_ctl.scala 85:18]
|
||||
wire _T_43 = _T_41 & _T_42; // @[el2_ifu_ifc_ctl.scala 85:16]
|
||||
wire _T_44 = ~io_dec_tlu_flush_noredir_wb; // @[el2_ifu_ifc_ctl.scala 85:39]
|
||||
wire fetch_bf_en = io_exu_flush_final | io_ifc_fetch_req_f; // @[el2_ifu_ifc_ctl.scala 87:37]
|
||||
wire _T_50 = io_ifu_ic_mb_empty | io_exu_flush_final; // @[el2_ifu_ifc_ctl.scala 91:39]
|
||||
wire _T_52 = _T_50 & _T_39; // @[el2_ifu_ifc_ctl.scala 91:61]
|
||||
wire _T_54 = _T_52 & _T_93; // @[el2_ifu_ifc_ctl.scala 91:74]
|
||||
wire _T_55 = ~miss_a; // @[el2_ifu_ifc_ctl.scala 91:86]
|
||||
wire mb_empty_mod = _T_54 & _T_55; // @[el2_ifu_ifc_ctl.scala 91:84]
|
||||
wire _T_51 = io_ifu_ic_mb_empty | io_exu_flush_final; // @[el2_ifu_ifc_ctl.scala 91:39]
|
||||
wire _T_53 = _T_51 & _T_40; // @[el2_ifu_ifc_ctl.scala 91:61]
|
||||
wire _T_55 = _T_53 & _T_94; // @[el2_ifu_ifc_ctl.scala 91:74]
|
||||
wire _T_56 = ~miss_a; // @[el2_ifu_ifc_ctl.scala 91:86]
|
||||
wire mb_empty_mod = _T_55 & _T_56; // @[el2_ifu_ifc_ctl.scala 91:84]
|
||||
wire goto_idle = io_exu_flush_final & io_dec_tlu_flush_noredir_wb; // @[el2_ifu_ifc_ctl.scala 93:35]
|
||||
wire _T_59 = io_exu_flush_final & _T_43; // @[el2_ifu_ifc_ctl.scala 95:36]
|
||||
wire leave_idle = _T_59 & idle; // @[el2_ifu_ifc_ctl.scala 95:67]
|
||||
wire _T_62 = ~state[1]; // @[el2_ifu_ifc_ctl.scala 97:23]
|
||||
wire _T_64 = _T_62 & state[0]; // @[el2_ifu_ifc_ctl.scala 97:33]
|
||||
wire _T_65 = _T_64 & miss_f; // @[el2_ifu_ifc_ctl.scala 97:44]
|
||||
wire _T_66 = ~goto_idle; // @[el2_ifu_ifc_ctl.scala 97:55]
|
||||
wire _T_67 = _T_65 & _T_66; // @[el2_ifu_ifc_ctl.scala 97:53]
|
||||
wire _T_69 = ~mb_empty_mod; // @[el2_ifu_ifc_ctl.scala 98:17]
|
||||
wire _T_70 = state[1] & _T_69; // @[el2_ifu_ifc_ctl.scala 98:15]
|
||||
wire _T_72 = _T_70 & _T_66; // @[el2_ifu_ifc_ctl.scala 98:31]
|
||||
wire next_state_1 = _T_67 | _T_72; // @[el2_ifu_ifc_ctl.scala 97:67]
|
||||
wire _T_74 = _T_66 & leave_idle; // @[el2_ifu_ifc_ctl.scala 100:34]
|
||||
wire _T_77 = state[0] & _T_66; // @[el2_ifu_ifc_ctl.scala 100:60]
|
||||
wire next_state_0 = _T_74 | _T_77; // @[el2_ifu_ifc_ctl.scala 100:48]
|
||||
wire _T_60 = io_exu_flush_final & _T_44; // @[el2_ifu_ifc_ctl.scala 95:36]
|
||||
wire leave_idle = _T_60 & idle; // @[el2_ifu_ifc_ctl.scala 95:67]
|
||||
wire _T_63 = ~state[1]; // @[el2_ifu_ifc_ctl.scala 97:23]
|
||||
wire _T_65 = _T_63 & state[0]; // @[el2_ifu_ifc_ctl.scala 97:33]
|
||||
wire _T_66 = _T_65 & miss_f; // @[el2_ifu_ifc_ctl.scala 97:44]
|
||||
wire _T_67 = ~goto_idle; // @[el2_ifu_ifc_ctl.scala 97:55]
|
||||
wire _T_68 = _T_66 & _T_67; // @[el2_ifu_ifc_ctl.scala 97:53]
|
||||
wire _T_70 = ~mb_empty_mod; // @[el2_ifu_ifc_ctl.scala 98:17]
|
||||
wire _T_71 = state[1] & _T_70; // @[el2_ifu_ifc_ctl.scala 98:15]
|
||||
wire _T_73 = _T_71 & _T_67; // @[el2_ifu_ifc_ctl.scala 98:31]
|
||||
wire next_state_1 = _T_68 | _T_73; // @[el2_ifu_ifc_ctl.scala 97:67]
|
||||
wire _T_75 = _T_67 & leave_idle; // @[el2_ifu_ifc_ctl.scala 100:34]
|
||||
wire _T_78 = state[0] & _T_67; // @[el2_ifu_ifc_ctl.scala 100:60]
|
||||
wire next_state_0 = _T_75 | _T_78; // @[el2_ifu_ifc_ctl.scala 100:48]
|
||||
wire wfm = state == 2'h3; // @[el2_ifu_ifc_ctl.scala 122:16]
|
||||
reg fb_full_f; // @[el2_ifu_ifc_ctl.scala 125:26]
|
||||
wire _T_137 = _T_34 | io_exu_flush_final; // @[el2_ifu_ifc_ctl.scala 129:61]
|
||||
wire _T_138 = ~_T_137; // @[el2_ifu_ifc_ctl.scala 129:19]
|
||||
wire _T_139 = fb_full_f & _T_138; // @[el2_ifu_ifc_ctl.scala 129:17]
|
||||
wire _T_140 = _T_139 | dma_stall; // @[el2_ifu_ifc_ctl.scala 129:84]
|
||||
wire _T_141 = io_ifc_fetch_req_bf_raw & _T_140; // @[el2_ifu_ifc_ctl.scala 128:60]
|
||||
wire [31:0] _T_143 = {io_ifc_fetch_addr_bf,1'h0}; // @[Cat.scala 29:58]
|
||||
wire iccm_acc_in_region_bf = _T_143[31:28] == 4'he; // @[el2_lib.scala 211:47]
|
||||
wire iccm_acc_in_range_bf = _T_143[31:16] == 16'hee00; // @[el2_lib.scala 214:29]
|
||||
wire _T_146 = ~io_ifc_iccm_access_bf; // @[el2_ifu_ifc_ctl.scala 135:30]
|
||||
wire _T_149 = fb_full_f & _T_35; // @[el2_ifu_ifc_ctl.scala 136:16]
|
||||
wire _T_150 = _T_146 | _T_149; // @[el2_ifu_ifc_ctl.scala 135:53]
|
||||
wire _T_151 = ~io_ifc_fetch_req_bf; // @[el2_ifu_ifc_ctl.scala 137:13]
|
||||
wire _T_152 = wfm & _T_151; // @[el2_ifu_ifc_ctl.scala 137:11]
|
||||
wire _T_153 = _T_150 | _T_152; // @[el2_ifu_ifc_ctl.scala 136:62]
|
||||
wire _T_154 = _T_153 | idle; // @[el2_ifu_ifc_ctl.scala 137:35]
|
||||
wire _T_156 = _T_154 & _T_2; // @[el2_ifu_ifc_ctl.scala 137:44]
|
||||
wire _T_158 = ~iccm_acc_in_range_bf; // @[el2_ifu_ifc_ctl.scala 139:33]
|
||||
wire [4:0] _T_161 = {io_ifc_fetch_addr_bf[30:27],1'h0}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_162 = io_dec_tlu_mrac_ff >> _T_161; // @[el2_ifu_ifc_ctl.scala 140:53]
|
||||
reg _T_165; // @[el2_ifu_ifc_ctl.scala 142:32]
|
||||
reg [30:0] _T_167; // @[Reg.scala 27:20]
|
||||
assign io_ifc_fetch_addr_f = _T_167; // @[el2_ifu_ifc_ctl.scala 144:23]
|
||||
wire _T_138 = _T_35 | io_exu_flush_final; // @[el2_ifu_ifc_ctl.scala 129:61]
|
||||
wire _T_139 = ~_T_138; // @[el2_ifu_ifc_ctl.scala 129:19]
|
||||
wire _T_140 = fb_full_f & _T_139; // @[el2_ifu_ifc_ctl.scala 129:17]
|
||||
wire _T_141 = _T_140 | dma_stall; // @[el2_ifu_ifc_ctl.scala 129:84]
|
||||
wire _T_142 = io_ifc_fetch_req_bf_raw & _T_141; // @[el2_ifu_ifc_ctl.scala 128:60]
|
||||
wire [31:0] _T_144 = {io_ifc_fetch_addr_bf,1'h0}; // @[Cat.scala 29:58]
|
||||
wire iccm_acc_in_region_bf = _T_144[31:28] == 4'he; // @[el2_lib.scala 211:47]
|
||||
wire iccm_acc_in_range_bf = _T_144[31:16] == 16'hee00; // @[el2_lib.scala 214:29]
|
||||
wire _T_147 = ~io_ifc_iccm_access_bf; // @[el2_ifu_ifc_ctl.scala 135:30]
|
||||
wire _T_150 = fb_full_f & _T_36; // @[el2_ifu_ifc_ctl.scala 136:16]
|
||||
wire _T_151 = _T_147 | _T_150; // @[el2_ifu_ifc_ctl.scala 135:53]
|
||||
wire _T_152 = ~io_ifc_fetch_req_bf; // @[el2_ifu_ifc_ctl.scala 137:13]
|
||||
wire _T_153 = wfm & _T_152; // @[el2_ifu_ifc_ctl.scala 137:11]
|
||||
wire _T_154 = _T_151 | _T_153; // @[el2_ifu_ifc_ctl.scala 136:62]
|
||||
wire _T_155 = _T_154 | idle; // @[el2_ifu_ifc_ctl.scala 137:35]
|
||||
wire _T_157 = _T_155 & _T_2; // @[el2_ifu_ifc_ctl.scala 137:44]
|
||||
wire _T_159 = ~iccm_acc_in_range_bf; // @[el2_ifu_ifc_ctl.scala 139:33]
|
||||
wire [4:0] _T_162 = {io_ifc_fetch_addr_bf[30:27],1'h0}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_163 = io_dec_tlu_mrac_ff >> _T_162; // @[el2_ifu_ifc_ctl.scala 140:53]
|
||||
reg _T_166; // @[el2_ifu_ifc_ctl.scala 142:32]
|
||||
reg [30:0] _T_168; // @[Reg.scala 27:20]
|
||||
assign io_ifc_fetch_addr_f = _T_168; // @[el2_ifu_ifc_ctl.scala 144:23]
|
||||
assign io_ifc_fetch_addr_bf = _T_22 | _T_20; // @[el2_ifu_ifc_ctl.scala 72:24]
|
||||
assign io_ifc_fetch_req_f = _T_165; // @[el2_ifu_ifc_ctl.scala 142:22]
|
||||
assign io_ifu_pmu_fetch_stall = wfm | _T_141; // @[el2_ifu_ifc_ctl.scala 128:26]
|
||||
assign io_ifc_fetch_uncacheable_bf = ~_T_162[0]; // @[el2_ifu_ifc_ctl.scala 140:31]
|
||||
assign io_ifc_fetch_req_bf = _T_42 & _T_43; // @[el2_ifu_ifc_ctl.scala 84:23]
|
||||
assign io_ifc_fetch_req_f = _T_166; // @[el2_ifu_ifc_ctl.scala 142:22]
|
||||
assign io_ifu_pmu_fetch_stall = wfm | _T_142; // @[el2_ifu_ifc_ctl.scala 128:26]
|
||||
assign io_ifc_fetch_uncacheable_bf = ~_T_163[0]; // @[el2_ifu_ifc_ctl.scala 140:31]
|
||||
assign io_ifc_fetch_req_bf = _T_43 & _T_44; // @[el2_ifu_ifc_ctl.scala 84:23]
|
||||
assign io_ifc_fetch_req_bf_raw = ~idle; // @[el2_ifu_ifc_ctl.scala 82:27]
|
||||
assign io_ifc_iccm_access_bf = _T_143[31:16] == 16'hee00; // @[el2_ifu_ifc_ctl.scala 134:25]
|
||||
assign io_ifc_region_acc_fault_bf = _T_158 & iccm_acc_in_region_bf; // @[el2_ifu_ifc_ctl.scala 139:30]
|
||||
assign io_ifc_dma_access_ok = _T_156 | dma_iccm_stall_any_f; // @[el2_ifu_ifc_ctl.scala 135:24]
|
||||
assign io_ifc_iccm_access_bf = _T_144[31:16] == 16'hee00; // @[el2_ifu_ifc_ctl.scala 134:25]
|
||||
assign io_ifc_region_acc_fault_bf = _T_159 & iccm_acc_in_region_bf; // @[el2_ifu_ifc_ctl.scala 139:30]
|
||||
assign io_ifc_dma_access_ok = _T_157 | dma_iccm_stall_any_f; // @[el2_ifu_ifc_ctl.scala 135:24]
|
||||
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
||||
`define RANDOMIZE
|
||||
`endif
|
||||
|
|
@ -210,9 +211,9 @@ initial begin
|
|||
_RAND_4 = {1{`RANDOM}};
|
||||
fb_full_f = _RAND_4[0:0];
|
||||
_RAND_5 = {1{`RANDOM}};
|
||||
_T_165 = _RAND_5[0:0];
|
||||
_T_166 = _RAND_5[0:0];
|
||||
_RAND_6 = {1{`RANDOM}};
|
||||
_T_167 = _RAND_6[30:0];
|
||||
_T_168 = _RAND_6[30:0];
|
||||
`endif // RANDOMIZE_REG_INIT
|
||||
if (reset) begin
|
||||
dma_iccm_stall_any_f = 1'h0;
|
||||
|
|
@ -230,10 +231,10 @@ initial begin
|
|||
fb_full_f = 1'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
_T_165 = 1'h0;
|
||||
_T_166 = 1'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
_T_167 = 31'h0;
|
||||
_T_168 = 31'h0;
|
||||
end
|
||||
`endif // RANDOMIZE
|
||||
end // initial
|
||||
|
|
@ -252,7 +253,7 @@ end // initial
|
|||
if (reset) begin
|
||||
miss_a <= 1'h0;
|
||||
end else begin
|
||||
miss_a <= _T_47 & _T_2;
|
||||
miss_a <= _T_48 & _T_2;
|
||||
end
|
||||
end
|
||||
always @(posedge clock or posedge reset) begin
|
||||
|
|
@ -266,7 +267,7 @@ end // initial
|
|||
if (reset) begin
|
||||
fb_write_f <= 4'h0;
|
||||
end else begin
|
||||
fb_write_f <= _T_127 | _T_124;
|
||||
fb_write_f <= _T_128 | _T_125;
|
||||
end
|
||||
end
|
||||
always @(posedge clock or posedge reset) begin
|
||||
|
|
@ -278,16 +279,16 @@ end // initial
|
|||
end
|
||||
always @(posedge clock or posedge reset) begin
|
||||
if (reset) begin
|
||||
_T_165 <= 1'h0;
|
||||
_T_166 <= 1'h0;
|
||||
end else begin
|
||||
_T_165 <= io_ifc_fetch_req_bf;
|
||||
_T_166 <= io_ifc_fetch_req_bf;
|
||||
end
|
||||
end
|
||||
always @(posedge clock or posedge reset) begin
|
||||
if (reset) begin
|
||||
_T_167 <= 31'h0;
|
||||
_T_168 <= 31'h0;
|
||||
end else if (fetch_bf_en) begin
|
||||
_T_167 <= io_ifc_fetch_addr_bf;
|
||||
_T_168 <= io_ifc_fetch_addr_bf;
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -206,7 +206,6 @@ class EL2_IC_DATA extends Module with el2_lib {
|
|||
val ic_rw_addr_q = Mux((io.ic_debug_rd_en | io.ic_debug_wr_en).asBool, Cat(io.ic_debug_addr,0.U(2.W)), io.ic_rw_addr)
|
||||
|
||||
val ic_rw_addr_q_inc = ic_rw_addr_q(ICACHE_TAG_LO-2,ICACHE_DATA_INDEX_LO-1) + 1.U
|
||||
io.test := ic_rw_addr_q_inc
|
||||
val ic_b_sb_wren = (0 until ICACHE_NUM_WAYS).map(i=>
|
||||
io.ic_wr_en | ic_debug_wr_way_en & Fill(ICACHE_NUM_WAYS, io.ic_debug_addr(ICACHE_BANK_HI-3,ICACHE_BANK_LO-3)===i.U))
|
||||
val ic_debug_sel_sb = (0 until ICACHE_NUM_WAYS).map(i=> (io.ic_debug_addr(ICACHE_BANK_HI-3,ICACHE_BANK_LO-3)===i.U).asUInt).reverse.reduce(Cat(_,_))
|
||||
|
|
@ -238,18 +237,17 @@ class EL2_IC_DATA extends Module with el2_lib {
|
|||
|
||||
val ic_cacheline_wrap_ff = ic_rw_addr_ff(ICACHE_TAG_INDEX_LO-2,ICACHE_BANK_LO-1) === Fill(ICACHE_TAG_INDEX_LO-ICACHE_BANK_LO, 1.U)
|
||||
|
||||
io.test := ic_rw_addr_bank_q(1)
|
||||
|
||||
//////////////////////////////////////////// Memory stated
|
||||
val (data_mem_word, tag_mem_word, ecc_offset) = DATA_MEM_LINE
|
||||
|
||||
val wb_out = Wire(Vec(ICACHE_BANKS_WAY,Vec(ICACHE_NUM_WAYS, UInt(data_mem_word.W))))
|
||||
val data_mem = Mem(ICACHE_DATA_DEPTH, Vec(ICACHE_BANKS_WAY,Vec(ICACHE_NUM_WAYS, UInt(data_mem_word.W))))
|
||||
for(i<-0 until ICACHE_NUM_WAYS; k<-0 until ICACHE_BANKS_WAY){
|
||||
// val
|
||||
when((ic_b_sb_wren(k)(i)&ic_bank_way_clken(k)(i)).asBool){
|
||||
val WE = if(ICACHE_WAYPACK) ic_b_sb_wren(k).orR else ic_b_sb_wren(k)(i)
|
||||
val ME = if(ICACHE_WAYPACK) ic_bank_way_clken(k).orR else ic_bank_way_clken(k)(i)
|
||||
when((ic_b_sb_wren(k)(i) & ic_bank_way_clken(k)(i)).asBool){
|
||||
data_mem(ic_rw_addr_bank_q(k))(k)(i) := io.test_in
|
||||
}.elsewhen((!ic_b_sb_wren(k)(i)&ic_bank_way_clken(k)(i)).asBool){
|
||||
io.test := data_mem(ic_rw_addr_bank_q(k))(k)(i)
|
||||
wb_out := data_mem(ic_rw_addr_bank_q(k))(k)(i)
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -75,7 +75,7 @@ class el2_ifu_ifc_ctl extends Module with el2_lib with RequireAsyncReset {
|
|||
sel_next_addr_bf.asBool -> fetch_addr_next)) // PC+4
|
||||
|
||||
val address_upper = io.ifc_fetch_addr_f(30,1)+1.U
|
||||
fetch_addr_next_0 := (address_upper(ICACHE_TAG_INDEX_LO-1) ^ io.ifc_fetch_addr_f(ICACHE_TAG_INDEX_LO-1)) & io.ifc_fetch_addr_f(0)
|
||||
fetch_addr_next_0 := !(address_upper(ICACHE_TAG_INDEX_LO-1) ^ io.ifc_fetch_addr_f(ICACHE_TAG_INDEX_LO-1)) & io.ifc_fetch_addr_f(0)
|
||||
|
||||
fetch_addr_next := Cat(address_upper, fetch_addr_next_0)
|
||||
|
||||
|
|
|
|||
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Reference in New Issue