Update beh_lib.scala
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@ -99,7 +99,7 @@ class rvbsadder extends Module{ //Done for verification and testing
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io.match_out := matchvec.asUInt.andR
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}
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class rvrangecheck(CCM_SADR:Int=0, CCM_SIZE:Int=128) extends Module{
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class rvrangecheck(CCM_SADR:UInt, CCM_SIZE:Int=128) extends Module{
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val io = IO(new Bundle{
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val addr = Input(UInt(32.W))
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val in_range = Output(UInt(1.W))
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@ -107,9 +107,7 @@ class rvbsadder extends Module{ //Done for verification and testing
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})
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val REGION_BITS = 4
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val MASK_BITS = 10 + log2Ceil(CCM_SIZE)
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val start_addr = Wire(UInt(32.W))
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start_addr := CCM_SADR.U
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val start_addr = CCM_SADR
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val region = start_addr(31,(32-REGION_BITS))
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io.in_region := (io.addr(31,(32-REGION_BITS)) === region(REGION_BITS-1,0)).asUInt
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