Packets updated with Valid
This commit is contained in:
Laraib Khan
parent
7dc1174c9a
commit
37641a8a14
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@ -6,6 +6,41 @@
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"~el2_exu|el2_exu>io_dec_div_cancel"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_exu|el2_exu>io_exu_flush_final",
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"sources":[
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"~el2_exu|el2_exu>io_dec_tlu_flush_lower_r",
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"~el2_exu|el2_exu>io_dec_i0_alu_decode_d",
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"~el2_exu|el2_exu>io_i0_ap_jal",
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"~el2_exu|el2_exu>io_i0_ap_predict_t",
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"~el2_exu|el2_exu>io_i0_ap_predict_nt",
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"~el2_exu|el2_exu>io_i0_ap_bge",
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"~el2_exu|el2_exu>io_i0_ap_sub",
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"~el2_exu|el2_exu>io_i0_ap_blt",
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"~el2_exu|el2_exu>io_i0_ap_beq",
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"~el2_exu|el2_exu>io_i0_ap_bne",
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"~el2_exu|el2_exu>io_i0_ap_unsign",
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"~el2_exu|el2_exu>io_dec_i0_predict_p_d_bits_pret",
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"~el2_exu|el2_exu>io_dec_i0_predict_p_d_bits_prett",
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"~el2_exu|el2_exu>io_dec_i0_predict_p_d_bits_pja",
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"~el2_exu|el2_exu>io_dec_i0_predict_p_d_bits_pcall",
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"~el2_exu|el2_exu>io_gpr_i0_rs1_d",
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"~el2_exu|el2_exu>io_gpr_i0_rs2_d",
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"~el2_exu|el2_exu>io_dec_i0_immed_d",
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"~el2_exu|el2_exu>io_dbg_cmd_wrdata",
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"~el2_exu|el2_exu>io_dec_i0_rs1_en_d",
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"~el2_exu|el2_exu>io_dec_i0_rs2_en_d",
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"~el2_exu|el2_exu>io_dec_i0_rs2_bypass_en_d",
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"~el2_exu|el2_exu>io_dec_i0_rs2_bypass_data_d",
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"~el2_exu|el2_exu>io_exu_i0_result_x",
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"~el2_exu|el2_exu>io_dec_i0_pc_d",
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"~el2_exu|el2_exu>io_dec_debug_wdata_rs1_d",
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"~el2_exu|el2_exu>io_dec_i0_select_pc_d",
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"~el2_exu|el2_exu>io_dec_i0_rs1_bypass_en_d",
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"~el2_exu|el2_exu>io_dec_i0_rs1_bypass_data_d"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_exu|el2_exu>io_exu_mp_fghr",
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@ -28,37 +63,14 @@
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_exu|el2_exu>io_exu_flush_final",
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"sink":"~el2_exu|el2_exu>io_exu_lsu_rs2_d",
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"sources":[
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"~el2_exu|el2_exu>io_dec_tlu_flush_lower_r",
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"~el2_exu|el2_exu>io_dec_i0_alu_decode_d",
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"~el2_exu|el2_exu>io_i0_ap_jal",
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"~el2_exu|el2_exu>io_i0_ap_predict_t",
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"~el2_exu|el2_exu>io_i0_ap_predict_nt",
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"~el2_exu|el2_exu>io_i0_ap_bge",
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"~el2_exu|el2_exu>io_i0_ap_sub",
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"~el2_exu|el2_exu>io_i0_ap_blt",
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"~el2_exu|el2_exu>io_i0_ap_beq",
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"~el2_exu|el2_exu>io_i0_ap_bne",
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"~el2_exu|el2_exu>io_i0_ap_unsign",
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"~el2_exu|el2_exu>io_dec_i0_predict_p_d_pret",
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"~el2_exu|el2_exu>io_dec_i0_predict_p_d_prett",
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"~el2_exu|el2_exu>io_dec_i0_predict_p_d_pja",
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"~el2_exu|el2_exu>io_dec_i0_predict_p_d_pcall",
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"~el2_exu|el2_exu>io_gpr_i0_rs1_d",
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"~el2_exu|el2_exu>io_gpr_i0_rs2_d",
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"~el2_exu|el2_exu>io_dec_i0_immed_d",
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"~el2_exu|el2_exu>io_dbg_cmd_wrdata",
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"~el2_exu|el2_exu>io_dec_i0_rs1_en_d",
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"~el2_exu|el2_exu>io_dec_i0_rs2_en_d",
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"~el2_exu|el2_exu>io_dec_i0_rs2_bypass_en_d",
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"~el2_exu|el2_exu>io_dec_extint_stall",
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"~el2_exu|el2_exu>io_dec_i0_rs2_bypass_data_d",
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"~el2_exu|el2_exu>io_exu_i0_result_x",
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"~el2_exu|el2_exu>io_dec_i0_pc_d",
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"~el2_exu|el2_exu>io_dec_debug_wdata_rs1_d",
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"~el2_exu|el2_exu>io_dec_i0_select_pc_d",
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"~el2_exu|el2_exu>io_dec_i0_rs1_bypass_en_d",
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"~el2_exu|el2_exu>io_dec_i0_rs1_bypass_data_d"
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"~el2_exu|el2_exu>io_dec_i0_rs2_bypass_en_d"
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]
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},
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{
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@ -71,9 +83,9 @@
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"~el2_exu|el2_exu>io_i0_ap_sub",
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"~el2_exu|el2_exu>io_dec_i0_pc_d",
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"~el2_exu|el2_exu>io_dec_i0_br_immed_d",
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"~el2_exu|el2_exu>io_dec_i0_predict_p_d_pret",
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"~el2_exu|el2_exu>io_dec_i0_predict_p_d_pja",
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"~el2_exu|el2_exu>io_dec_i0_predict_p_d_pcall",
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"~el2_exu|el2_exu>io_dec_i0_predict_p_d_bits_pret",
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"~el2_exu|el2_exu>io_dec_i0_predict_p_d_bits_pja",
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"~el2_exu|el2_exu>io_dec_i0_predict_p_d_bits_pcall",
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"~el2_exu|el2_exu>io_gpr_i0_rs2_d",
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"~el2_exu|el2_exu>io_dec_i0_immed_d",
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"~el2_exu|el2_exu>io_gpr_i0_rs1_d",
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@ -89,18 +101,6 @@
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"~el2_exu|el2_exu>io_dec_i0_rs1_bypass_data_d"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_exu|el2_exu>io_exu_lsu_rs2_d",
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"sources":[
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"~el2_exu|el2_exu>io_gpr_i0_rs2_d",
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"~el2_exu|el2_exu>io_dec_i0_rs2_en_d",
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"~el2_exu|el2_exu>io_dec_extint_stall",
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"~el2_exu|el2_exu>io_dec_i0_rs2_bypass_data_d",
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"~el2_exu|el2_exu>io_exu_i0_result_x",
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"~el2_exu|el2_exu>io_dec_i0_rs2_bypass_en_d"
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]
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},
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{
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"class":"logger.LogLevelAnnotation",
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"globalLogLevel":{
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1262
el2_exu.fir
1262
el2_exu.fir
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@ -12,8 +12,8 @@
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},
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{
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"class":"firrtl.transforms.BlackBoxResourceAnno",
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"target":"el2_exu_div_ctl.TEC_RV_ICG",
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"resourceId":"/vsrc/TEC_RV_ICG.v"
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"target":"el2_exu_div_ctl.gated_latch",
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"resourceId":"/vsrc/gated_latch.v"
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},
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{
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"class":"firrtl.options.TargetDirAnnotation",
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3206
el2_exu_div_ctl.fir
3206
el2_exu_div_ctl.fir
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1010
el2_exu_div_ctl.v
1010
el2_exu_div_ctl.v
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@ -5,8 +5,8 @@
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},
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{
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"class":"firrtl.transforms.BlackBoxResourceAnno",
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"target":"el2_exu_mul_ctl.TEC_RV_ICG",
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"resourceId":"/vsrc/TEC_RV_ICG.v"
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"target":"el2_exu_mul_ctl.gated_latch",
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"resourceId":"/vsrc/gated_latch.v"
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},
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{
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"class":"firrtl.options.TargetDirAnnotation",
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@ -1,12 +1,12 @@
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;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
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circuit el2_exu_mul_ctl :
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extmodule TEC_RV_ICG :
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extmodule gated_latch :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = TEC_RV_ICG
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defname = gated_latch
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module rvclkhdr :
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@ -14,23 +14,23 @@ circuit el2_exu_mul_ctl :
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of TEC_RV_ICG @[beh_lib.scala 332:24]
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inst clkhdr of gated_latch @[el2_lib.scala 474:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[beh_lib.scala 333:12]
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clkhdr.CK <= io.clk @[beh_lib.scala 334:16]
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clkhdr.EN <= io.en @[beh_lib.scala 335:16]
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clkhdr.SE <= io.scan_mode @[beh_lib.scala 336:16]
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io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
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clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
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clkhdr.EN <= io.en @[el2_lib.scala 477:18]
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clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
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extmodule TEC_RV_ICG_1 :
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extmodule gated_latch_1 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = TEC_RV_ICG
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defname = gated_latch
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module rvclkhdr_1 :
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@ -38,23 +38,23 @@ circuit el2_exu_mul_ctl :
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of TEC_RV_ICG_1 @[beh_lib.scala 332:24]
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inst clkhdr of gated_latch_1 @[el2_lib.scala 474:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[beh_lib.scala 333:12]
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clkhdr.CK <= io.clk @[beh_lib.scala 334:16]
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clkhdr.EN <= io.en @[beh_lib.scala 335:16]
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clkhdr.SE <= io.scan_mode @[beh_lib.scala 336:16]
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io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
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clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
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clkhdr.EN <= io.en @[el2_lib.scala 477:18]
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clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
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extmodule TEC_RV_ICG_2 :
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extmodule gated_latch_2 :
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output Q : Clock
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input CK : Clock
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input EN : UInt<1>
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input SE : UInt<1>
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defname = TEC_RV_ICG
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defname = gated_latch
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module rvclkhdr_2 :
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@ -62,20 +62,20 @@ circuit el2_exu_mul_ctl :
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input reset : Reset
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output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
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inst clkhdr of TEC_RV_ICG_2 @[beh_lib.scala 332:24]
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inst clkhdr of gated_latch_2 @[el2_lib.scala 474:26]
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clkhdr.SE is invalid
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clkhdr.EN is invalid
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clkhdr.CK is invalid
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clkhdr.Q is invalid
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io.l1clk <= clkhdr.Q @[beh_lib.scala 333:12]
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clkhdr.CK <= io.clk @[beh_lib.scala 334:16]
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clkhdr.EN <= io.en @[beh_lib.scala 335:16]
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clkhdr.SE <= io.scan_mode @[beh_lib.scala 336:16]
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io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
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clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
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clkhdr.EN <= io.en @[el2_lib.scala 477:18]
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clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
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module el2_exu_mul_ctl :
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input clock : Clock
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input reset : AsyncReset
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output io : {flip scan_mode : UInt<1>, flip mul_p : {valid : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}, flip rs1_in : UInt<32>, flip rs2_in : UInt<32>, result_x : UInt<32>}
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output io : {flip scan_mode : UInt<1>, flip mul_p : {valid : UInt<1>, bits : {rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}}, flip rs1_in : UInt<32>, flip rs2_in : UInt<32>, result_x : UInt<32>}
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wire rs1_ext_in : SInt<33>
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rs1_ext_in <= asSInt(UInt<1>("h00"))
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@ -89,45 +89,45 @@ circuit el2_exu_mul_ctl :
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prod_x <= asSInt(UInt<1>("h00"))
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wire low_x : UInt<1>
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low_x <= UInt<1>("h00")
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node _T = bits(io.rs1_in, 31, 31) @[el2_exu_mul_ctl.scala 26:50]
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node _T_1 = and(io.mul_p.rs1_sign, _T) @[el2_exu_mul_ctl.scala 26:39]
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node _T = bits(io.rs1_in, 31, 31) @[el2_exu_mul_ctl.scala 26:55]
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node _T_1 = and(io.mul_p.bits.rs1_sign, _T) @[el2_exu_mul_ctl.scala 26:44]
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node _T_2 = cat(_T_1, io.rs1_in) @[Cat.scala 29:58]
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node _T_3 = asSInt(_T_2) @[el2_exu_mul_ctl.scala 26:66]
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node _T_3 = asSInt(_T_2) @[el2_exu_mul_ctl.scala 26:71]
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rs1_ext_in <= _T_3 @[el2_exu_mul_ctl.scala 26:14]
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node _T_4 = bits(io.rs2_in, 31, 31) @[el2_exu_mul_ctl.scala 27:50]
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node _T_5 = and(io.mul_p.rs2_sign, _T_4) @[el2_exu_mul_ctl.scala 27:39]
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node _T_4 = bits(io.rs2_in, 31, 31) @[el2_exu_mul_ctl.scala 27:55]
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node _T_5 = and(io.mul_p.bits.rs2_sign, _T_4) @[el2_exu_mul_ctl.scala 27:44]
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node _T_6 = cat(_T_5, io.rs2_in) @[Cat.scala 29:58]
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node _T_7 = asSInt(_T_6) @[el2_exu_mul_ctl.scala 27:66]
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node _T_7 = asSInt(_T_6) @[el2_exu_mul_ctl.scala 27:71]
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rs2_ext_in <= _T_7 @[el2_exu_mul_ctl.scala 27:14]
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node _T_8 = bits(io.mul_p.valid, 0, 0) @[el2_exu_mul_ctl.scala 36:47]
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inst rvclkhdr of rvclkhdr @[beh_lib.scala 352:21]
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node _T_8 = bits(io.mul_p.valid, 0, 0) @[el2_exu_mul_ctl.scala 36:52]
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inst rvclkhdr of rvclkhdr @[el2_lib.scala 508:23]
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rvclkhdr.clock <= clock
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rvclkhdr.reset <= reset
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rvclkhdr.io.clk <= clock @[beh_lib.scala 354:16]
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rvclkhdr.io.en <= _T_8 @[beh_lib.scala 355:15]
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rvclkhdr.io.scan_mode <= io.scan_mode @[beh_lib.scala 356:22]
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reg _T_9 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[beh_lib.scala 358:14]
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_T_9 <= io.mul_p.low @[beh_lib.scala 358:14]
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rvclkhdr.io.clk <= clock @[el2_lib.scala 510:18]
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rvclkhdr.io.en <= _T_8 @[el2_lib.scala 511:17]
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rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24]
|
||||
reg _T_9 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
|
||||
_T_9 <= io.mul_p.bits.low @[el2_lib.scala 514:16]
|
||||
low_x <= _T_9 @[el2_exu_mul_ctl.scala 36:9]
|
||||
node _T_10 = bits(io.mul_p.valid, 0, 0) @[el2_exu_mul_ctl.scala 37:44]
|
||||
inst rvclkhdr_1 of rvclkhdr_1 @[beh_lib.scala 372:21]
|
||||
inst rvclkhdr_1 of rvclkhdr_1 @[el2_lib.scala 528:23]
|
||||
rvclkhdr_1.clock <= clock
|
||||
rvclkhdr_1.reset <= reset
|
||||
rvclkhdr_1.io.clk <= clock @[beh_lib.scala 374:16]
|
||||
rvclkhdr_1.io.en <= _T_10 @[beh_lib.scala 375:15]
|
||||
rvclkhdr_1.io.scan_mode <= io.scan_mode @[beh_lib.scala 376:22]
|
||||
reg _T_11 : SInt, rvclkhdr_1.io.l1clk with : (reset => (reset, asSInt(UInt<1>("h00")))) @[beh_lib.scala 378:14]
|
||||
_T_11 <= rs1_ext_in @[beh_lib.scala 378:14]
|
||||
rvclkhdr_1.io.clk <= clock @[el2_lib.scala 530:18]
|
||||
rvclkhdr_1.io.en <= _T_10 @[el2_lib.scala 531:17]
|
||||
rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 532:24]
|
||||
reg _T_11 : SInt, rvclkhdr_1.io.l1clk with : (reset => (reset, asSInt(UInt<1>("h00")))) @[el2_lib.scala 534:16]
|
||||
_T_11 <= rs1_ext_in @[el2_lib.scala 534:16]
|
||||
rs1_x <= _T_11 @[el2_exu_mul_ctl.scala 37:9]
|
||||
node _T_12 = bits(io.mul_p.valid, 0, 0) @[el2_exu_mul_ctl.scala 38:45]
|
||||
inst rvclkhdr_2 of rvclkhdr_2 @[beh_lib.scala 372:21]
|
||||
inst rvclkhdr_2 of rvclkhdr_2 @[el2_lib.scala 528:23]
|
||||
rvclkhdr_2.clock <= clock
|
||||
rvclkhdr_2.reset <= reset
|
||||
rvclkhdr_2.io.clk <= clock @[beh_lib.scala 374:16]
|
||||
rvclkhdr_2.io.en <= _T_12 @[beh_lib.scala 375:15]
|
||||
rvclkhdr_2.io.scan_mode <= io.scan_mode @[beh_lib.scala 376:22]
|
||||
reg _T_13 : SInt, rvclkhdr_2.io.l1clk with : (reset => (reset, asSInt(UInt<1>("h00")))) @[beh_lib.scala 378:14]
|
||||
_T_13 <= rs2_ext_in @[beh_lib.scala 378:14]
|
||||
rvclkhdr_2.io.clk <= clock @[el2_lib.scala 530:18]
|
||||
rvclkhdr_2.io.en <= _T_12 @[el2_lib.scala 531:17]
|
||||
rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 532:24]
|
||||
reg _T_13 : SInt, rvclkhdr_2.io.l1clk with : (reset => (reset, asSInt(UInt<1>("h00")))) @[el2_lib.scala 534:16]
|
||||
_T_13 <= rs2_ext_in @[el2_lib.scala 534:16]
|
||||
rs2_x <= _T_13 @[el2_exu_mul_ctl.scala 38:9]
|
||||
node _T_14 = mul(rs1_x, rs2_x) @[el2_exu_mul_ctl.scala 40:20]
|
||||
prod_x <= _T_14 @[el2_exu_mul_ctl.scala 40:10]
|
||||
|
|
|
|||
|
|
@ -4,44 +4,44 @@ module rvclkhdr(
|
|||
input io_en,
|
||||
input io_scan_mode
|
||||
);
|
||||
wire clkhdr_Q; // @[beh_lib.scala 332:24]
|
||||
wire clkhdr_CK; // @[beh_lib.scala 332:24]
|
||||
wire clkhdr_EN; // @[beh_lib.scala 332:24]
|
||||
wire clkhdr_SE; // @[beh_lib.scala 332:24]
|
||||
TEC_RV_ICG clkhdr ( // @[beh_lib.scala 332:24]
|
||||
wire clkhdr_Q; // @[el2_lib.scala 474:26]
|
||||
wire clkhdr_CK; // @[el2_lib.scala 474:26]
|
||||
wire clkhdr_EN; // @[el2_lib.scala 474:26]
|
||||
wire clkhdr_SE; // @[el2_lib.scala 474:26]
|
||||
gated_latch clkhdr ( // @[el2_lib.scala 474:26]
|
||||
.Q(clkhdr_Q),
|
||||
.CK(clkhdr_CK),
|
||||
.EN(clkhdr_EN),
|
||||
.SE(clkhdr_SE)
|
||||
);
|
||||
assign io_l1clk = clkhdr_Q; // @[beh_lib.scala 333:12]
|
||||
assign clkhdr_CK = io_clk; // @[beh_lib.scala 334:16]
|
||||
assign clkhdr_EN = io_en; // @[beh_lib.scala 335:16]
|
||||
assign clkhdr_SE = io_scan_mode; // @[beh_lib.scala 336:16]
|
||||
assign io_l1clk = clkhdr_Q; // @[el2_lib.scala 475:14]
|
||||
assign clkhdr_CK = io_clk; // @[el2_lib.scala 476:18]
|
||||
assign clkhdr_EN = io_en; // @[el2_lib.scala 477:18]
|
||||
assign clkhdr_SE = io_scan_mode; // @[el2_lib.scala 478:18]
|
||||
endmodule
|
||||
module el2_exu_mul_ctl(
|
||||
input clock,
|
||||
input reset,
|
||||
input io_scan_mode,
|
||||
input io_mul_p_valid,
|
||||
input io_mul_p_rs1_sign,
|
||||
input io_mul_p_rs2_sign,
|
||||
input io_mul_p_low,
|
||||
input io_mul_p_bext,
|
||||
input io_mul_p_bdep,
|
||||
input io_mul_p_clmul,
|
||||
input io_mul_p_clmulh,
|
||||
input io_mul_p_clmulr,
|
||||
input io_mul_p_grev,
|
||||
input io_mul_p_shfl,
|
||||
input io_mul_p_unshfl,
|
||||
input io_mul_p_crc32_b,
|
||||
input io_mul_p_crc32_h,
|
||||
input io_mul_p_crc32_w,
|
||||
input io_mul_p_crc32c_b,
|
||||
input io_mul_p_crc32c_h,
|
||||
input io_mul_p_crc32c_w,
|
||||
input io_mul_p_bfp,
|
||||
input io_mul_p_bits_rs1_sign,
|
||||
input io_mul_p_bits_rs2_sign,
|
||||
input io_mul_p_bits_low,
|
||||
input io_mul_p_bits_bext,
|
||||
input io_mul_p_bits_bdep,
|
||||
input io_mul_p_bits_clmul,
|
||||
input io_mul_p_bits_clmulh,
|
||||
input io_mul_p_bits_clmulr,
|
||||
input io_mul_p_bits_grev,
|
||||
input io_mul_p_bits_shfl,
|
||||
input io_mul_p_bits_unshfl,
|
||||
input io_mul_p_bits_crc32_b,
|
||||
input io_mul_p_bits_crc32_h,
|
||||
input io_mul_p_bits_crc32_w,
|
||||
input io_mul_p_bits_crc32c_b,
|
||||
input io_mul_p_bits_crc32c_h,
|
||||
input io_mul_p_bits_crc32c_w,
|
||||
input io_mul_p_bits_bfp,
|
||||
input [31:0] io_rs1_in,
|
||||
input [31:0] io_rs2_in,
|
||||
output [31:0] io_result_x
|
||||
|
|
@ -51,55 +51,55 @@ module el2_exu_mul_ctl(
|
|||
reg [63:0] _RAND_1;
|
||||
reg [63:0] _RAND_2;
|
||||
`endif // RANDOMIZE_REG_INIT
|
||||
wire rvclkhdr_io_l1clk; // @[beh_lib.scala 352:21]
|
||||
wire rvclkhdr_io_clk; // @[beh_lib.scala 352:21]
|
||||
wire rvclkhdr_io_en; // @[beh_lib.scala 352:21]
|
||||
wire rvclkhdr_io_scan_mode; // @[beh_lib.scala 352:21]
|
||||
wire rvclkhdr_1_io_l1clk; // @[beh_lib.scala 372:21]
|
||||
wire rvclkhdr_1_io_clk; // @[beh_lib.scala 372:21]
|
||||
wire rvclkhdr_1_io_en; // @[beh_lib.scala 372:21]
|
||||
wire rvclkhdr_1_io_scan_mode; // @[beh_lib.scala 372:21]
|
||||
wire rvclkhdr_2_io_l1clk; // @[beh_lib.scala 372:21]
|
||||
wire rvclkhdr_2_io_clk; // @[beh_lib.scala 372:21]
|
||||
wire rvclkhdr_2_io_en; // @[beh_lib.scala 372:21]
|
||||
wire rvclkhdr_2_io_scan_mode; // @[beh_lib.scala 372:21]
|
||||
wire _T_1 = io_mul_p_rs1_sign & io_rs1_in[31]; // @[el2_exu_mul_ctl.scala 26:39]
|
||||
wire _T_5 = io_mul_p_rs2_sign & io_rs2_in[31]; // @[el2_exu_mul_ctl.scala 27:39]
|
||||
reg low_x; // @[beh_lib.scala 358:14]
|
||||
reg [32:0] rs1_x; // @[beh_lib.scala 378:14]
|
||||
reg [32:0] rs2_x; // @[beh_lib.scala 378:14]
|
||||
wire rvclkhdr_io_l1clk; // @[el2_lib.scala 508:23]
|
||||
wire rvclkhdr_io_clk; // @[el2_lib.scala 508:23]
|
||||
wire rvclkhdr_io_en; // @[el2_lib.scala 508:23]
|
||||
wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 508:23]
|
||||
wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 528:23]
|
||||
wire rvclkhdr_1_io_clk; // @[el2_lib.scala 528:23]
|
||||
wire rvclkhdr_1_io_en; // @[el2_lib.scala 528:23]
|
||||
wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 528:23]
|
||||
wire rvclkhdr_2_io_l1clk; // @[el2_lib.scala 528:23]
|
||||
wire rvclkhdr_2_io_clk; // @[el2_lib.scala 528:23]
|
||||
wire rvclkhdr_2_io_en; // @[el2_lib.scala 528:23]
|
||||
wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 528:23]
|
||||
wire _T_1 = io_mul_p_bits_rs1_sign & io_rs1_in[31]; // @[el2_exu_mul_ctl.scala 26:44]
|
||||
wire _T_5 = io_mul_p_bits_rs2_sign & io_rs2_in[31]; // @[el2_exu_mul_ctl.scala 27:44]
|
||||
reg low_x; // @[el2_lib.scala 514:16]
|
||||
reg [32:0] rs1_x; // @[el2_lib.scala 534:16]
|
||||
reg [32:0] rs2_x; // @[el2_lib.scala 534:16]
|
||||
wire [65:0] prod_x = $signed(rs1_x) * $signed(rs2_x); // @[el2_exu_mul_ctl.scala 40:20]
|
||||
wire _T_16 = ~low_x; // @[el2_exu_mul_ctl.scala 41:29]
|
||||
wire [31:0] _T_20 = _T_16 ? prod_x[63:32] : 32'h0; // @[Mux.scala 27:72]
|
||||
wire [31:0] _T_21 = low_x ? prod_x[31:0] : 32'h0; // @[Mux.scala 27:72]
|
||||
rvclkhdr rvclkhdr ( // @[beh_lib.scala 352:21]
|
||||
rvclkhdr rvclkhdr ( // @[el2_lib.scala 508:23]
|
||||
.io_l1clk(rvclkhdr_io_l1clk),
|
||||
.io_clk(rvclkhdr_io_clk),
|
||||
.io_en(rvclkhdr_io_en),
|
||||
.io_scan_mode(rvclkhdr_io_scan_mode)
|
||||
);
|
||||
rvclkhdr rvclkhdr_1 ( // @[beh_lib.scala 372:21]
|
||||
rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 528:23]
|
||||
.io_l1clk(rvclkhdr_1_io_l1clk),
|
||||
.io_clk(rvclkhdr_1_io_clk),
|
||||
.io_en(rvclkhdr_1_io_en),
|
||||
.io_scan_mode(rvclkhdr_1_io_scan_mode)
|
||||
);
|
||||
rvclkhdr rvclkhdr_2 ( // @[beh_lib.scala 372:21]
|
||||
rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 528:23]
|
||||
.io_l1clk(rvclkhdr_2_io_l1clk),
|
||||
.io_clk(rvclkhdr_2_io_clk),
|
||||
.io_en(rvclkhdr_2_io_en),
|
||||
.io_scan_mode(rvclkhdr_2_io_scan_mode)
|
||||
);
|
||||
assign io_result_x = _T_20 | _T_21; // @[el2_exu_mul_ctl.scala 41:15]
|
||||
assign rvclkhdr_io_clk = clock; // @[beh_lib.scala 354:16]
|
||||
assign rvclkhdr_io_en = io_mul_p_valid; // @[beh_lib.scala 355:15]
|
||||
assign rvclkhdr_io_scan_mode = io_scan_mode; // @[beh_lib.scala 356:22]
|
||||
assign rvclkhdr_1_io_clk = clock; // @[beh_lib.scala 374:16]
|
||||
assign rvclkhdr_1_io_en = io_mul_p_valid; // @[beh_lib.scala 375:15]
|
||||
assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[beh_lib.scala 376:22]
|
||||
assign rvclkhdr_2_io_clk = clock; // @[beh_lib.scala 374:16]
|
||||
assign rvclkhdr_2_io_en = io_mul_p_valid; // @[beh_lib.scala 375:15]
|
||||
assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[beh_lib.scala 376:22]
|
||||
assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 510:18]
|
||||
assign rvclkhdr_io_en = io_mul_p_valid; // @[el2_lib.scala 511:17]
|
||||
assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
||||
assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 530:18]
|
||||
assign rvclkhdr_1_io_en = io_mul_p_valid; // @[el2_lib.scala 531:17]
|
||||
assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 532:24]
|
||||
assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 530:18]
|
||||
assign rvclkhdr_2_io_en = io_mul_p_valid; // @[el2_lib.scala 531:17]
|
||||
assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 532:24]
|
||||
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
||||
`define RANDOMIZE
|
||||
`endif
|
||||
|
|
@ -161,7 +161,7 @@ end // initial
|
|||
if (reset) begin
|
||||
low_x <= 1'h0;
|
||||
end else begin
|
||||
low_x <= io_mul_p_low;
|
||||
low_x <= io_mul_p_bits_low;
|
||||
end
|
||||
end
|
||||
always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin
|
||||
|
|
|
|||
|
|
@ -0,0 +1,362 @@
|
|||
[
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu|el2_ifu>io_iccm_dma_ecc_error",
|
||||
"sources":[
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_core_ecc_disable",
|
||||
"~el2_ifu|el2_ifu>io_iccm_rd_data_ecc",
|
||||
"~el2_ifu|el2_ifu>io_exu_flush_final",
|
||||
"~el2_ifu|el2_ifu>io_ic_rd_hit",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_start_error",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_error",
|
||||
"~el2_ifu|el2_ifu>io_exu_i0_br_index_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu|el2_ifu>io_ic_rd_en",
|
||||
"sources":[
|
||||
"~el2_ifu|el2_ifu>io_exu_flush_final",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_force_halt",
|
||||
"~el2_ifu|el2_ifu>io_ic_rd_hit",
|
||||
"~el2_ifu|el2_ifu>io_exu_flush_path_final",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_noredir_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_mrac_ff",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_start_error",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_error",
|
||||
"~el2_ifu|el2_ifu>io_exu_i0_br_index_r",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_err_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_i0_commit_cmt",
|
||||
"~el2_ifu|el2_ifu>io_ic_rd_data",
|
||||
"~el2_ifu|el2_ifu>io_dec_i0_decode_d"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu|el2_ifu>io_iccm_rden",
|
||||
"sources":[
|
||||
"~el2_ifu|el2_ifu>io_dma_iccm_req",
|
||||
"~el2_ifu|el2_ifu>io_dma_mem_write",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_core_ecc_disable",
|
||||
"~el2_ifu|el2_ifu>io_iccm_rd_data_ecc",
|
||||
"~el2_ifu|el2_ifu>io_exu_flush_final",
|
||||
"~el2_ifu|el2_ifu>io_ic_rd_hit",
|
||||
"~el2_ifu|el2_ifu>io_exu_flush_path_final",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_noredir_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_start_error",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_error",
|
||||
"~el2_ifu|el2_ifu>io_exu_i0_br_index_r",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_err_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_i0_commit_cmt",
|
||||
"~el2_ifu|el2_ifu>io_ic_rd_data",
|
||||
"~el2_ifu|el2_ifu>io_dec_i0_decode_d"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu|el2_ifu>io_ic_premux_data",
|
||||
"sources":[
|
||||
"~el2_ifu|el2_ifu>io_iccm_rd_data",
|
||||
"~el2_ifu|el2_ifu>io_exu_flush_final",
|
||||
"~el2_ifu|el2_ifu>io_ic_rd_hit",
|
||||
"~el2_ifu|el2_ifu>io_ifu_axi_rid",
|
||||
"~el2_ifu|el2_ifu>io_ifu_axi_rvalid",
|
||||
"~el2_ifu|el2_ifu>io_ifu_bus_clk_en",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_start_error",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_error",
|
||||
"~el2_ifu|el2_ifu>io_exu_i0_br_index_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu|el2_ifu>io_iccm_ready",
|
||||
"sources":[
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_core_ecc_disable",
|
||||
"~el2_ifu|el2_ifu>io_iccm_rd_data_ecc",
|
||||
"~el2_ifu|el2_ifu>io_exu_flush_final",
|
||||
"~el2_ifu|el2_ifu>io_ic_rd_hit",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_noredir_wb",
|
||||
"~el2_ifu|el2_ifu>io_exu_flush_path_final",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_start_error",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_error",
|
||||
"~el2_ifu|el2_ifu>io_exu_i0_br_index_r",
|
||||
"~el2_ifu|el2_ifu>io_dec_i0_decode_d",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_err_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_i0_commit_cmt",
|
||||
"~el2_ifu|el2_ifu>io_ic_rd_data"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu|el2_ifu>io_ic_debug_addr",
|
||||
"sources":[
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_ic_diag_pkt_icache_dicawics"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu|el2_ifu>io_ic_debug_way",
|
||||
"sources":[
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_ic_diag_pkt_icache_dicawics"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu|el2_ifu>io_ic_debug_rd_en",
|
||||
"sources":[
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_ic_diag_pkt_icache_rd_valid"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu|el2_ifu>io_iccm_dma_sb_error",
|
||||
"sources":[
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_core_ecc_disable",
|
||||
"~el2_ifu|el2_ifu>io_iccm_rd_data_ecc",
|
||||
"~el2_ifu|el2_ifu>io_exu_flush_final",
|
||||
"~el2_ifu|el2_ifu>io_ic_rd_hit",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_start_error",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_error",
|
||||
"~el2_ifu|el2_ifu>io_exu_i0_br_index_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu|el2_ifu>io_ifu_ic_error_start",
|
||||
"sources":[
|
||||
"~el2_ifu|el2_ifu>io_ic_eccerr",
|
||||
"~el2_ifu|el2_ifu>io_ic_tag_perr",
|
||||
"~el2_ifu|el2_ifu>io_ic_rd_hit",
|
||||
"~el2_ifu|el2_ifu>io_exu_flush_final",
|
||||
"~el2_ifu|el2_ifu>io_ifu_axi_rid",
|
||||
"~el2_ifu|el2_ifu>io_ifu_axi_rvalid",
|
||||
"~el2_ifu|el2_ifu>io_ifu_bus_clk_en",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_start_error",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_error",
|
||||
"~el2_ifu|el2_ifu>io_exu_i0_br_index_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu|el2_ifu>io_ic_sel_premux_data",
|
||||
"sources":[
|
||||
"~el2_ifu|el2_ifu>io_exu_flush_final",
|
||||
"~el2_ifu|el2_ifu>io_ic_rd_hit",
|
||||
"~el2_ifu|el2_ifu>io_ifu_axi_rid",
|
||||
"~el2_ifu|el2_ifu>io_ifu_axi_rvalid",
|
||||
"~el2_ifu|el2_ifu>io_ifu_bus_clk_en",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_start_error",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_error",
|
||||
"~el2_ifu|el2_ifu>io_exu_i0_br_index_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu|el2_ifu>io_iccm_wr_data",
|
||||
"sources":[
|
||||
"~el2_ifu|el2_ifu>io_dma_iccm_req",
|
||||
"~el2_ifu|el2_ifu>io_dma_mem_wdata",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_core_ecc_disable",
|
||||
"~el2_ifu|el2_ifu>io_iccm_rd_data_ecc",
|
||||
"~el2_ifu|el2_ifu>io_exu_flush_final",
|
||||
"~el2_ifu|el2_ifu>io_ic_rd_hit",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_noredir_wb",
|
||||
"~el2_ifu|el2_ifu>io_exu_flush_path_final",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_start_error",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_error",
|
||||
"~el2_ifu|el2_ifu>io_exu_i0_br_index_r",
|
||||
"~el2_ifu|el2_ifu>io_dec_i0_decode_d",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_err_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_i0_commit_cmt",
|
||||
"~el2_ifu|el2_ifu>io_ic_rd_data"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu|el2_ifu>io_iccm_wr_size",
|
||||
"sources":[
|
||||
"~el2_ifu|el2_ifu>io_dma_mem_sz",
|
||||
"~el2_ifu|el2_ifu>io_dma_iccm_req"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu|el2_ifu>io_ic_debug_wr_en",
|
||||
"sources":[
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_ic_diag_pkt_icache_wr_valid"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu|el2_ifu>io_iccm_rw_addr",
|
||||
"sources":[
|
||||
"~el2_ifu|el2_ifu>io_dma_mem_addr",
|
||||
"~el2_ifu|el2_ifu>io_dma_iccm_req",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_core_ecc_disable",
|
||||
"~el2_ifu|el2_ifu>io_iccm_rd_data_ecc",
|
||||
"~el2_ifu|el2_ifu>io_exu_flush_final",
|
||||
"~el2_ifu|el2_ifu>io_ic_rd_hit",
|
||||
"~el2_ifu|el2_ifu>io_exu_flush_path_final",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_noredir_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_start_error",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_error",
|
||||
"~el2_ifu|el2_ifu>io_exu_i0_br_index_r",
|
||||
"~el2_ifu|el2_ifu>io_dec_i0_decode_d",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_err_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_i0_commit_cmt",
|
||||
"~el2_ifu|el2_ifu>io_ic_rd_data"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu|el2_ifu>io_iccm_wren",
|
||||
"sources":[
|
||||
"~el2_ifu|el2_ifu>io_dma_mem_write",
|
||||
"~el2_ifu|el2_ifu>io_dma_iccm_req",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_core_ecc_disable",
|
||||
"~el2_ifu|el2_ifu>io_iccm_rd_data_ecc",
|
||||
"~el2_ifu|el2_ifu>io_exu_flush_final",
|
||||
"~el2_ifu|el2_ifu>io_ic_rd_hit",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_noredir_wb",
|
||||
"~el2_ifu|el2_ifu>io_exu_flush_path_final",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_start_error",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_error",
|
||||
"~el2_ifu|el2_ifu>io_exu_i0_br_index_r",
|
||||
"~el2_ifu|el2_ifu>io_dec_i0_decode_d",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_err_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_i0_commit_cmt",
|
||||
"~el2_ifu|el2_ifu>io_ic_rd_data"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu|el2_ifu>io_ifu_pmu_instr_aligned",
|
||||
"sources":[
|
||||
"~el2_ifu|el2_ifu>io_dec_i0_decode_d"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu|el2_ifu>io_ifu_iccm_rd_ecc_single_err",
|
||||
"sources":[
|
||||
"~el2_ifu|el2_ifu>io_exu_flush_final",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_core_ecc_disable",
|
||||
"~el2_ifu|el2_ifu>io_iccm_rd_data_ecc",
|
||||
"~el2_ifu|el2_ifu>io_ic_rd_hit",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_start_error",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_error",
|
||||
"~el2_ifu|el2_ifu>io_exu_i0_br_index_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu|el2_ifu>io_ic_debug_tag_array",
|
||||
"sources":[
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_ic_diag_pkt_icache_dicawics"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu|el2_ifu>io_ifu_pmu_fetch_stall",
|
||||
"sources":[
|
||||
"~el2_ifu|el2_ifu>io_exu_flush_final",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_err_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_i0_commit_cmt",
|
||||
"~el2_ifu|el2_ifu>io_ic_rd_data",
|
||||
"~el2_ifu|el2_ifu>io_dec_i0_decode_d",
|
||||
"~el2_ifu|el2_ifu>io_ic_rd_hit",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_start_error",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_error",
|
||||
"~el2_ifu|el2_ifu>io_exu_i0_br_index_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu|el2_ifu>io_ic_tag_valid",
|
||||
"sources":[
|
||||
"~el2_ifu|el2_ifu>io_exu_flush_final"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu|el2_ifu>io_ic_rw_addr",
|
||||
"sources":[
|
||||
"~el2_ifu|el2_ifu>io_exu_flush_path_final",
|
||||
"~el2_ifu|el2_ifu>io_exu_flush_final",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_leak_one_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_flush_lower_wb",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_start_error",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_br0_r_pkt_bits_br_error",
|
||||
"~el2_ifu|el2_ifu>io_exu_i0_br_index_r",
|
||||
"~el2_ifu|el2_ifu>io_ic_rd_hit",
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_bpred_disable"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu|el2_ifu>io_ic_debug_wr_data",
|
||||
"sources":[
|
||||
"~el2_ifu|el2_ifu>io_dec_tlu_ic_diag_pkt_icache_wrdata"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.EmitCircuitAnnotation",
|
||||
"emitter":"firrtl.VerilogEmitter"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.BlackBoxResourceAnno",
|
||||
"target":"el2_ifu.gated_latch",
|
||||
"resourceId":"/vsrc/gated_latch.v"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.options.TargetDirAnnotation",
|
||||
"directory":"."
|
||||
},
|
||||
{
|
||||
"class":"firrtl.options.OutputAnnotationFileAnnotation",
|
||||
"file":"el2_ifu"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
|
||||
"targetDir":"."
|
||||
}
|
||||
]
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,53 @@
|
|||
[
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu_aln_ctl|el2_ifu_aln_ctl>io_i0_brp_bits_br_error",
|
||||
"sources":[
|
||||
"~el2_ifu_aln_ctl|el2_ifu_aln_ctl>io_i0_brp_valid"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu_aln_ctl|el2_ifu_aln_ctl>io_ifu_fb_consume1",
|
||||
"sources":[
|
||||
"~el2_ifu_aln_ctl|el2_ifu_aln_ctl>io_exu_flush_final",
|
||||
"~el2_ifu_aln_ctl|el2_ifu_aln_ctl>io_dec_i0_decode_d"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu_aln_ctl|el2_ifu_aln_ctl>io_ifu_pmu_instr_aligned",
|
||||
"sources":[
|
||||
"~el2_ifu_aln_ctl|el2_ifu_aln_ctl>io_dec_i0_decode_d"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu_aln_ctl|el2_ifu_aln_ctl>io_ifu_fb_consume2",
|
||||
"sources":[
|
||||
"~el2_ifu_aln_ctl|el2_ifu_aln_ctl>io_exu_flush_final",
|
||||
"~el2_ifu_aln_ctl|el2_ifu_aln_ctl>io_dec_i0_decode_d"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.EmitCircuitAnnotation",
|
||||
"emitter":"firrtl.VerilogEmitter"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.BlackBoxResourceAnno",
|
||||
"target":"el2_ifu_aln_ctl.gated_latch",
|
||||
"resourceId":"/vsrc/gated_latch.v"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.options.TargetDirAnnotation",
|
||||
"directory":"."
|
||||
},
|
||||
{
|
||||
"class":"firrtl.options.OutputAnnotationFileAnnotation",
|
||||
"file":"el2_ifu_aln_ctl"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
|
||||
"targetDir":"."
|
||||
}
|
||||
]
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -1,16 +1,144 @@
|
|||
[
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_out",
|
||||
"sink":"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifu_bp_hist0_f",
|
||||
"sources":[
|
||||
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_in",
|
||||
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_in2"
|
||||
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_addr_f"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifu_bp_hist1_f",
|
||||
"sources":[
|
||||
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_addr_f",
|
||||
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_req_f",
|
||||
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_flush_leak_one_wb",
|
||||
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_flush_lower_wb",
|
||||
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_br0_r_pkt_bits_br_start_error",
|
||||
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_br0_r_pkt_bits_br_error",
|
||||
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_exu_i0_br_index_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifu_bp_valid_f",
|
||||
"sources":[
|
||||
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_bpred_disable",
|
||||
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_addr_f",
|
||||
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_req_f",
|
||||
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_flush_leak_one_wb",
|
||||
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_flush_lower_wb",
|
||||
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_br0_r_pkt_bits_br_start_error",
|
||||
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_br0_r_pkt_bits_br_error",
|
||||
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_exu_i0_br_index_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifu_bp_inst_mask_f",
|
||||
"sources":[
|
||||
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifu_bp_hit_taken_f",
|
||||
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_bpred_disable",
|
||||
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_req_f",
|
||||
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_addr_f",
|
||||
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_flush_leak_one_wb",
|
||||
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_flush_lower_wb",
|
||||
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_br0_r_pkt_bits_br_start_error",
|
||||
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_br0_r_pkt_bits_br_error",
|
||||
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_exu_i0_br_index_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifu_bp_poffset_f",
|
||||
"sources":[
|
||||
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_addr_f",
|
||||
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_req_f",
|
||||
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_flush_leak_one_wb",
|
||||
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_flush_lower_wb",
|
||||
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_br0_r_pkt_bits_br_start_error",
|
||||
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_br0_r_pkt_bits_br_error",
|
||||
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_exu_i0_br_index_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifu_bp_ret_f",
|
||||
"sources":[
|
||||
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_addr_f",
|
||||
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_req_f",
|
||||
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_flush_leak_one_wb",
|
||||
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_flush_lower_wb",
|
||||
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_br0_r_pkt_bits_br_start_error",
|
||||
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_br0_r_pkt_bits_br_error",
|
||||
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_exu_i0_br_index_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifu_bp_btb_target_f",
|
||||
"sources":[
|
||||
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_addr_f",
|
||||
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_req_f",
|
||||
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_flush_leak_one_wb",
|
||||
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_flush_lower_wb",
|
||||
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_br0_r_pkt_bits_br_start_error",
|
||||
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_br0_r_pkt_bits_br_error",
|
||||
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_exu_i0_br_index_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifu_bp_hit_taken_f",
|
||||
"sources":[
|
||||
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_bpred_disable",
|
||||
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_req_f",
|
||||
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_addr_f",
|
||||
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_flush_leak_one_wb",
|
||||
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_flush_lower_wb",
|
||||
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_br0_r_pkt_bits_br_start_error",
|
||||
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_br0_r_pkt_bits_br_error",
|
||||
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_exu_i0_br_index_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifu_bp_way_f",
|
||||
"sources":[
|
||||
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_addr_f",
|
||||
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_req_f",
|
||||
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_exu_mp_index",
|
||||
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_flush_leak_one_wb",
|
||||
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_flush_lower_wb",
|
||||
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_exu_mp_btag",
|
||||
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_exu_mp_pkt_bits_misp",
|
||||
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_br0_r_pkt_bits_br_start_error",
|
||||
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_br0_r_pkt_bits_br_error",
|
||||
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_exu_i0_br_index_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifu_bp_pc4_f",
|
||||
"sources":[
|
||||
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_addr_f",
|
||||
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_req_f",
|
||||
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_flush_leak_one_wb",
|
||||
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_flush_lower_wb",
|
||||
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_br0_r_pkt_bits_br_start_error",
|
||||
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_br0_r_pkt_bits_br_error",
|
||||
"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_exu_i0_br_index_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.EmitCircuitAnnotation",
|
||||
"emitter":"firrtl.VerilogEmitter"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.BlackBoxResourceAnno",
|
||||
"target":"el2_ifu_bp_ctl.gated_latch",
|
||||
"resourceId":"/vsrc/gated_latch.v"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.options.TargetDirAnnotation",
|
||||
"directory":"."
|
||||
|
|
|
|||
44447
el2_ifu_bp_ctl.fir
44447
el2_ifu_bp_ctl.fir
File diff suppressed because it is too large
Load Diff
30833
el2_ifu_bp_ctl.v
30833
el2_ifu_bp_ctl.v
File diff suppressed because it is too large
Load Diff
|
|
@ -28,7 +28,103 @@
|
|||
"~el2_lsu|el2_lsu>io_dma_mem_addr",
|
||||
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
|
||||
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_bits_load_ldst_bypass_d",
|
||||
"~el2_lsu|el2_lsu>io_picm_rd_data",
|
||||
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
|
||||
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
|
||||
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
|
||||
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu|el2_lsu>io_dccm_wr_data_lo",
|
||||
"sources":[
|
||||
"~el2_lsu|el2_lsu>io_dma_dccm_req",
|
||||
"~el2_lsu|el2_lsu>io_dma_mem_write",
|
||||
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
|
||||
"~el2_lsu|el2_lsu>io_dma_mem_addr",
|
||||
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_bits_load_ldst_bypass_d",
|
||||
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_bits_dword",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_bits_half",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_bits_word",
|
||||
"~el2_lsu|el2_lsu>io_dma_mem_sz",
|
||||
"~el2_lsu|el2_lsu>io_dma_mem_wdata",
|
||||
"~el2_lsu|el2_lsu>io_picm_rd_data",
|
||||
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
|
||||
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
|
||||
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
|
||||
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu|el2_lsu>io_dccm_rden",
|
||||
"sources":[
|
||||
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
|
||||
"~el2_lsu|el2_lsu>io_dma_mem_addr",
|
||||
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_bits_load_ldst_bypass_d",
|
||||
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_bits_dword",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_bits_half",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_bits_word",
|
||||
"~el2_lsu|el2_lsu>io_dma_mem_sz",
|
||||
"~el2_lsu|el2_lsu>io_dma_dccm_req",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_valid",
|
||||
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_bits_fast_int",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_bits_load",
|
||||
"~el2_lsu|el2_lsu>io_dma_mem_write",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_bits_store",
|
||||
"~el2_lsu|el2_lsu>io_picm_rd_data",
|
||||
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
|
||||
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
|
||||
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu|el2_lsu>io_picm_mken",
|
||||
"sources":[
|
||||
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
|
||||
"~el2_lsu|el2_lsu>io_dma_mem_addr",
|
||||
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_bits_load_ldst_bypass_d",
|
||||
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_bits_dword",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_bits_half",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_bits_word",
|
||||
"~el2_lsu|el2_lsu>io_dma_mem_sz",
|
||||
"~el2_lsu|el2_lsu>io_dma_dccm_req",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_valid",
|
||||
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_bits_fast_int",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_bits_store",
|
||||
"~el2_lsu|el2_lsu>io_dma_mem_write",
|
||||
"~el2_lsu|el2_lsu>io_picm_rd_data",
|
||||
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
|
||||
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
|
||||
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu|el2_lsu>io_dccm_wr_addr_lo",
|
||||
"sources":[
|
||||
"~el2_lsu|el2_lsu>io_dma_dccm_req",
|
||||
"~el2_lsu|el2_lsu>io_dma_mem_write",
|
||||
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
|
||||
"~el2_lsu|el2_lsu>io_dma_mem_addr",
|
||||
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
|
||||
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_bits_load_ldst_bypass_d",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_bits_dword",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_bits_half",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_bits_word",
|
||||
"~el2_lsu|el2_lsu>io_dma_mem_sz",
|
||||
"~el2_lsu|el2_lsu>io_picm_rd_data",
|
||||
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
|
||||
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
|
||||
|
|
@ -69,24 +165,41 @@
|
|||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu|el2_lsu>io_dccm_wren",
|
||||
"sink":"~el2_lsu|el2_lsu>io_dccm_ready",
|
||||
"sources":[
|
||||
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu|el2_lsu>io_lsu_pmu_bus_trxn",
|
||||
"sources":[
|
||||
"~el2_lsu|el2_lsu>io_lsu_axi_arready",
|
||||
"~el2_lsu|el2_lsu>io_lsu_axi_awready",
|
||||
"~el2_lsu|el2_lsu>io_lsu_axi_wready"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu|el2_lsu>io_picm_wr_data",
|
||||
"sources":[
|
||||
"~el2_lsu|el2_lsu>io_dma_mem_wdata",
|
||||
"~el2_lsu|el2_lsu>io_dma_dccm_req",
|
||||
"~el2_lsu|el2_lsu>io_dma_mem_write",
|
||||
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
|
||||
"~el2_lsu|el2_lsu>io_dma_mem_addr",
|
||||
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_bits_load_ldst_bypass_d",
|
||||
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_dword",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_half",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_word",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_bits_dword",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_bits_half",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_bits_word",
|
||||
"~el2_lsu|el2_lsu>io_dma_mem_sz",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_valid",
|
||||
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_fast_int",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_load",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_store",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_bits_fast_int",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_bits_load",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_bits_store",
|
||||
"~el2_lsu|el2_lsu>io_picm_rd_data",
|
||||
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
|
||||
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
|
||||
|
|
@ -101,10 +214,10 @@
|
|||
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
|
||||
"~el2_lsu|el2_lsu>io_dma_mem_addr",
|
||||
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_dword",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_half",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_word",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_bits_load_ldst_bypass_d",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_bits_dword",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_bits_half",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_bits_word",
|
||||
"~el2_lsu|el2_lsu>io_dma_mem_sz",
|
||||
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
|
||||
"~el2_lsu|el2_lsu>io_picm_rd_data",
|
||||
|
|
@ -115,147 +228,11 @@
|
|||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu|el2_lsu>io_dccm_wr_data_hi",
|
||||
"sink":"~el2_lsu|el2_lsu>io_dccm_dma_ecc_error",
|
||||
"sources":[
|
||||
"~el2_lsu|el2_lsu>io_dma_dccm_req",
|
||||
"~el2_lsu|el2_lsu>io_dma_mem_write",
|
||||
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
|
||||
"~el2_lsu|el2_lsu>io_dma_mem_addr",
|
||||
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d",
|
||||
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_dword",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_half",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_word",
|
||||
"~el2_lsu|el2_lsu>io_dma_mem_sz",
|
||||
"~el2_lsu|el2_lsu>io_dma_mem_wdata",
|
||||
"~el2_lsu|el2_lsu>io_picm_rd_data",
|
||||
"~el2_lsu|el2_lsu>io_dec_tlu_core_ecc_disable",
|
||||
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
|
||||
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
|
||||
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
|
||||
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu|el2_lsu>io_dccm_rden",
|
||||
"sources":[
|
||||
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
|
||||
"~el2_lsu|el2_lsu>io_dma_mem_addr",
|
||||
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d",
|
||||
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_dword",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_half",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_word",
|
||||
"~el2_lsu|el2_lsu>io_dma_mem_sz",
|
||||
"~el2_lsu|el2_lsu>io_dma_dccm_req",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_valid",
|
||||
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_fast_int",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_load",
|
||||
"~el2_lsu|el2_lsu>io_dma_mem_write",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_store",
|
||||
"~el2_lsu|el2_lsu>io_picm_rd_data",
|
||||
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
|
||||
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
|
||||
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu|el2_lsu>io_picm_rden",
|
||||
"sources":[
|
||||
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
|
||||
"~el2_lsu|el2_lsu>io_dma_mem_addr",
|
||||
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d",
|
||||
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_dword",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_half",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_word",
|
||||
"~el2_lsu|el2_lsu>io_dma_mem_sz",
|
||||
"~el2_lsu|el2_lsu>io_dma_dccm_req",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_valid",
|
||||
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_fast_int",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_load",
|
||||
"~el2_lsu|el2_lsu>io_dma_mem_write",
|
||||
"~el2_lsu|el2_lsu>io_picm_rd_data",
|
||||
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
|
||||
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
|
||||
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu|el2_lsu>io_picm_wren",
|
||||
"sources":[
|
||||
"~el2_lsu|el2_lsu>io_dma_dccm_req",
|
||||
"~el2_lsu|el2_lsu>io_dma_mem_write",
|
||||
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r",
|
||||
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
|
||||
"~el2_lsu|el2_lsu>io_dma_mem_addr",
|
||||
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d",
|
||||
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_dword",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_half",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_word",
|
||||
"~el2_lsu|el2_lsu>io_dma_mem_sz",
|
||||
"~el2_lsu|el2_lsu>io_picm_rd_data",
|
||||
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
|
||||
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
|
||||
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu|el2_lsu>io_dccm_rd_addr_hi",
|
||||
"sources":[
|
||||
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
|
||||
"~el2_lsu|el2_lsu>io_dma_mem_addr",
|
||||
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d",
|
||||
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_dword",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_half",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_word",
|
||||
"~el2_lsu|el2_lsu>io_dma_mem_sz",
|
||||
"~el2_lsu|el2_lsu>io_picm_rd_data",
|
||||
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
|
||||
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
|
||||
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
|
||||
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu|el2_lsu>io_dccm_ready",
|
||||
"sources":[
|
||||
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu|el2_lsu>io_picm_wraddr",
|
||||
"sources":[
|
||||
"~el2_lsu|el2_lsu>io_dma_mem_addr",
|
||||
"~el2_lsu|el2_lsu>io_dma_dccm_req",
|
||||
"~el2_lsu|el2_lsu>io_dma_mem_write",
|
||||
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
|
||||
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d",
|
||||
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_dword",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_half",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_word",
|
||||
"~el2_lsu|el2_lsu>io_dma_mem_sz",
|
||||
"~el2_lsu|el2_lsu>io_picm_rd_data",
|
||||
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
|
||||
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
|
||||
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
|
||||
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
|
||||
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo"
|
||||
]
|
||||
},
|
||||
{
|
||||
|
|
@ -266,10 +243,10 @@
|
|||
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
|
||||
"~el2_lsu|el2_lsu>io_dma_mem_addr",
|
||||
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_dword",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_half",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_word",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_bits_load_ldst_bypass_d",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_bits_dword",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_bits_half",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_bits_word",
|
||||
"~el2_lsu|el2_lsu>io_dma_mem_sz",
|
||||
"~el2_lsu|el2_lsu>io_picm_rd_data",
|
||||
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
|
||||
|
|
@ -280,20 +257,24 @@
|
|||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu|el2_lsu>io_lsu_pmu_bus_trxn",
|
||||
"sink":"~el2_lsu|el2_lsu>io_dccm_wr_addr_hi",
|
||||
"sources":[
|
||||
"~el2_lsu|el2_lsu>io_lsu_axi_arready",
|
||||
"~el2_lsu|el2_lsu>io_lsu_axi_awready",
|
||||
"~el2_lsu|el2_lsu>io_lsu_axi_wready"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu|el2_lsu>io_dccm_dma_ecc_error",
|
||||
"sources":[
|
||||
"~el2_lsu|el2_lsu>io_dec_tlu_core_ecc_disable",
|
||||
"~el2_lsu|el2_lsu>io_dma_dccm_req",
|
||||
"~el2_lsu|el2_lsu>io_dma_mem_write",
|
||||
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
|
||||
"~el2_lsu|el2_lsu>io_dma_mem_addr",
|
||||
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_bits_load_ldst_bypass_d",
|
||||
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_bits_dword",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_bits_half",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_bits_word",
|
||||
"~el2_lsu|el2_lsu>io_dma_mem_sz",
|
||||
"~el2_lsu|el2_lsu>io_picm_rd_data",
|
||||
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
|
||||
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo"
|
||||
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
|
||||
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
|
||||
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
|
|
@ -314,22 +295,6 @@
|
|||
"~el2_lsu|el2_lsu>io_lsu_axi_wready"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu|el2_lsu>io_dccm_rd_addr_lo",
|
||||
"sources":[
|
||||
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
|
||||
"~el2_lsu|el2_lsu>io_dma_mem_addr",
|
||||
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
|
||||
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d",
|
||||
"~el2_lsu|el2_lsu>io_picm_rd_data",
|
||||
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
|
||||
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
|
||||
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
|
||||
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu|el2_lsu>io_lsu_result_m",
|
||||
|
|
@ -343,46 +308,58 @@
|
|||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu|el2_lsu>io_picm_wr_data",
|
||||
"sink":"~el2_lsu|el2_lsu>io_dccm_rd_addr_lo",
|
||||
"sources":[
|
||||
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
|
||||
"~el2_lsu|el2_lsu>io_dma_mem_addr",
|
||||
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
|
||||
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_bits_load_ldst_bypass_d",
|
||||
"~el2_lsu|el2_lsu>io_picm_rd_data",
|
||||
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
|
||||
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
|
||||
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
|
||||
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu|el2_lsu>io_picm_wraddr",
|
||||
"sources":[
|
||||
"~el2_lsu|el2_lsu>io_dma_mem_addr",
|
||||
"~el2_lsu|el2_lsu>io_dma_dccm_req",
|
||||
"~el2_lsu|el2_lsu>io_dma_mem_write",
|
||||
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
|
||||
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_bits_load_ldst_bypass_d",
|
||||
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_bits_dword",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_bits_half",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_bits_word",
|
||||
"~el2_lsu|el2_lsu>io_dma_mem_sz",
|
||||
"~el2_lsu|el2_lsu>io_picm_rd_data",
|
||||
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
|
||||
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
|
||||
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
|
||||
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu|el2_lsu>io_dccm_wr_data_hi",
|
||||
"sources":[
|
||||
"~el2_lsu|el2_lsu>io_dma_dccm_req",
|
||||
"~el2_lsu|el2_lsu>io_dma_mem_write",
|
||||
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
|
||||
"~el2_lsu|el2_lsu>io_dma_mem_addr",
|
||||
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_bits_load_ldst_bypass_d",
|
||||
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_bits_dword",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_bits_half",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_bits_word",
|
||||
"~el2_lsu|el2_lsu>io_dma_mem_sz",
|
||||
"~el2_lsu|el2_lsu>io_dma_mem_wdata",
|
||||
"~el2_lsu|el2_lsu>io_dma_dccm_req",
|
||||
"~el2_lsu|el2_lsu>io_dma_mem_write",
|
||||
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
|
||||
"~el2_lsu|el2_lsu>io_dma_mem_addr",
|
||||
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d",
|
||||
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_dword",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_half",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_word",
|
||||
"~el2_lsu|el2_lsu>io_dma_mem_sz",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_valid",
|
||||
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_fast_int",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_load",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_store",
|
||||
"~el2_lsu|el2_lsu>io_picm_rd_data",
|
||||
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
|
||||
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
|
||||
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu|el2_lsu>io_dccm_wr_addr_lo",
|
||||
"sources":[
|
||||
"~el2_lsu|el2_lsu>io_dma_dccm_req",
|
||||
"~el2_lsu|el2_lsu>io_dma_mem_write",
|
||||
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
|
||||
"~el2_lsu|el2_lsu>io_dma_mem_addr",
|
||||
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
|
||||
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_dword",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_half",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_word",
|
||||
"~el2_lsu|el2_lsu>io_dma_mem_sz",
|
||||
"~el2_lsu|el2_lsu>io_picm_rd_data",
|
||||
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
|
||||
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
|
||||
|
|
@ -390,31 +367,6 @@
|
|||
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu|el2_lsu>io_picm_mken",
|
||||
"sources":[
|
||||
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
|
||||
"~el2_lsu|el2_lsu>io_dma_mem_addr",
|
||||
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d",
|
||||
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_dword",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_half",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_word",
|
||||
"~el2_lsu|el2_lsu>io_dma_mem_sz",
|
||||
"~el2_lsu|el2_lsu>io_dma_dccm_req",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_valid",
|
||||
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_fast_int",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_store",
|
||||
"~el2_lsu|el2_lsu>io_dma_mem_write",
|
||||
"~el2_lsu|el2_lsu>io_picm_rd_data",
|
||||
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
|
||||
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
|
||||
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu|el2_lsu>io_lsu_nonblock_load_valid_m",
|
||||
|
|
@ -422,29 +374,6 @@
|
|||
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu|el2_lsu>io_dccm_wr_data_lo",
|
||||
"sources":[
|
||||
"~el2_lsu|el2_lsu>io_dma_dccm_req",
|
||||
"~el2_lsu|el2_lsu>io_dma_mem_write",
|
||||
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
|
||||
"~el2_lsu|el2_lsu>io_dma_mem_addr",
|
||||
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d",
|
||||
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_dword",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_half",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_word",
|
||||
"~el2_lsu|el2_lsu>io_dma_mem_sz",
|
||||
"~el2_lsu|el2_lsu>io_dma_mem_wdata",
|
||||
"~el2_lsu|el2_lsu>io_picm_rd_data",
|
||||
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
|
||||
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
|
||||
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
|
||||
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu|el2_lsu>io_lsu_pmu_bus_misaligned",
|
||||
|
|
@ -461,18 +390,67 @@
|
|||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu|el2_lsu>io_dccm_wr_addr_hi",
|
||||
"sink":"~el2_lsu|el2_lsu>io_dccm_wren",
|
||||
"sources":[
|
||||
"~el2_lsu|el2_lsu>io_dma_dccm_req",
|
||||
"~el2_lsu|el2_lsu>io_dma_mem_write",
|
||||
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
|
||||
"~el2_lsu|el2_lsu>io_dma_mem_addr",
|
||||
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_bits_load_ldst_bypass_d",
|
||||
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_dword",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_half",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_word",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_bits_dword",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_bits_half",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_bits_word",
|
||||
"~el2_lsu|el2_lsu>io_dma_mem_sz",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_valid",
|
||||
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_bits_fast_int",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_bits_load",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_bits_store",
|
||||
"~el2_lsu|el2_lsu>io_picm_rd_data",
|
||||
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
|
||||
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
|
||||
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu|el2_lsu>io_picm_rden",
|
||||
"sources":[
|
||||
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
|
||||
"~el2_lsu|el2_lsu>io_dma_mem_addr",
|
||||
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_bits_load_ldst_bypass_d",
|
||||
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_bits_dword",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_bits_half",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_bits_word",
|
||||
"~el2_lsu|el2_lsu>io_dma_mem_sz",
|
||||
"~el2_lsu|el2_lsu>io_dma_dccm_req",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_valid",
|
||||
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_bits_fast_int",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_bits_load",
|
||||
"~el2_lsu|el2_lsu>io_dma_mem_write",
|
||||
"~el2_lsu|el2_lsu>io_picm_rd_data",
|
||||
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
|
||||
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
|
||||
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu|el2_lsu>io_dccm_rd_addr_hi",
|
||||
"sources":[
|
||||
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
|
||||
"~el2_lsu|el2_lsu>io_dma_mem_addr",
|
||||
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_bits_load_ldst_bypass_d",
|
||||
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_bits_dword",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_bits_half",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_bits_word",
|
||||
"~el2_lsu|el2_lsu>io_dma_mem_sz",
|
||||
"~el2_lsu|el2_lsu>io_picm_rd_data",
|
||||
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
|
||||
|
|
@ -481,6 +459,28 @@
|
|||
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu|el2_lsu>io_picm_wren",
|
||||
"sources":[
|
||||
"~el2_lsu|el2_lsu>io_dma_dccm_req",
|
||||
"~el2_lsu|el2_lsu>io_dma_mem_write",
|
||||
"~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r",
|
||||
"~el2_lsu|el2_lsu>io_exu_lsu_rs1_d",
|
||||
"~el2_lsu|el2_lsu>io_dma_mem_addr",
|
||||
"~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_bits_load_ldst_bypass_d",
|
||||
"~el2_lsu|el2_lsu>io_dec_lsu_offset_d",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_bits_dword",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_bits_half",
|
||||
"~el2_lsu|el2_lsu>io_lsu_p_bits_word",
|
||||
"~el2_lsu|el2_lsu>io_dma_mem_sz",
|
||||
"~el2_lsu|el2_lsu>io_picm_rd_data",
|
||||
"~el2_lsu|el2_lsu>io_dccm_rd_data_hi",
|
||||
"~el2_lsu|el2_lsu>io_dccm_rd_data_lo",
|
||||
"~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.EmitCircuitAnnotation",
|
||||
"emitter":"firrtl.VerilogEmitter"
|
||||
|
|
|
|||
12652
el2_lsu.fir
12652
el2_lsu.fir
File diff suppressed because it is too large
Load Diff
|
|
@ -1,4 +1,41 @@
|
|||
[
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_dccm_wren",
|
||||
"sources":[
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_ld_single_ecc_error_r_ff",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_dma_dccm_wen",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_stbuf_commit_any",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_stbuf_reqvld_any",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_addr_in_dccm_d",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_valid",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_bits_load",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_bits_store",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_stbuf_addr_any",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_addr_d",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_end_addr_d",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_bits_word",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_bits_dword"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_stbuf_commit_any",
|
||||
"sources":[
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_stbuf_reqvld_any",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_ld_single_ecc_error_r_ff",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_addr_in_dccm_d",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_dma_dccm_wen",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_valid",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_bits_load",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_bits_store",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_stbuf_addr_any",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_addr_d",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_end_addr_d",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_bits_word",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_bits_dword"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_dccm_wr_data_lo",
|
||||
|
|
@ -32,28 +69,6 @@
|
|||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_dccm_rd_data_lo"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_picm_mken",
|
||||
"sources":[
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_addr_in_pic_d",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_valid",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_store"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_store_data_r",
|
||||
"sources":[
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_store_data_hi_r",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_store_data_lo_r",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_addr_r",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_r_store",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_r_word",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_r_by",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_r_half"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_dccm_wr_addr_hi",
|
||||
|
|
@ -66,40 +81,11 @@
|
|||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_store_datafn_lo_r",
|
||||
"sink":"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_picm_mken",
|
||||
"sources":[
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_stbuf_data_any",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_store_data_lo_r",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_stbuf_commit_any",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_addr_in_dccm_r",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_stbuf_reqvld_any",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_stbuf_addr_any",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_addr_r",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_ld_single_ecc_error_r_ff",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_addr_in_dccm_d",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_dma_dccm_wen",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_addr_in_pic_d",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_valid",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_load",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_r_store",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_store",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_addr_d",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_end_addr_d",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_r_word",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_r_by",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_r_half",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_word",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_dword"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_picm_wren",
|
||||
"sources":[
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_dma_pic_wen",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_commit_r",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_addr_in_pic_r",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_r_valid",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_r_store"
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_bits_store"
|
||||
]
|
||||
},
|
||||
{
|
||||
|
|
@ -130,6 +116,33 @@
|
|||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_sec_data_lo_m"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_store_datafn_lo_r",
|
||||
"sources":[
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_stbuf_data_any",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_store_data_lo_r",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_stbuf_commit_any",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_addr_in_dccm_r",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_stbuf_reqvld_any",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_stbuf_addr_any",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_addr_r",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_ld_single_ecc_error_r_ff",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_addr_in_dccm_d",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_dma_dccm_wen",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_valid",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_bits_load",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_r_bits_store",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_bits_store",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_addr_d",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_end_addr_d",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_r_bits_word",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_r_bits_by",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_r_bits_half",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_bits_word",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_bits_dword"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_dccm_rdata_hi_m",
|
||||
|
|
@ -137,6 +150,34 @@
|
|||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_dccm_rd_data_hi"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_store_datafn_hi_r",
|
||||
"sources":[
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_stbuf_data_any",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_store_data_hi_r",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_stbuf_commit_any",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_addr_in_dccm_r",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_stbuf_reqvld_any",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_stbuf_addr_any",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_end_addr_r",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_addr_r",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_ld_single_ecc_error_r_ff",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_addr_in_dccm_d",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_dma_dccm_wen",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_valid",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_bits_load",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_r_bits_store",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_bits_store",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_addr_d",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_end_addr_d",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_r_bits_word",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_r_bits_by",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_r_bits_half",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_bits_word",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_bits_dword"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_picm_wraddr",
|
||||
|
|
@ -155,77 +196,39 @@
|
|||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_stbuf_commit_any",
|
||||
"sources":[
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_stbuf_reqvld_any",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_ld_single_ecc_error_r_ff",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_addr_in_dccm_d",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_dma_dccm_wen",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_valid",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_load",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_store",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_stbuf_addr_any",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_addr_d",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_end_addr_d",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_word",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_dword"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_picm_wr_data",
|
||||
"sink":"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_picm_wren",
|
||||
"sources":[
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_dma_pic_wen",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_dma_mem_wdata",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_store_datafn_lo_r",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_stbuf_data_any",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_store_data_lo_r",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_stbuf_commit_any",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_addr_in_dccm_r",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_stbuf_reqvld_any",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_stbuf_addr_any",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_addr_r",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_ld_single_ecc_error_r_ff",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_addr_in_dccm_d",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_dma_dccm_wen",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_valid",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_load",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_r_store",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_store",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_addr_d",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_end_addr_d",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_r_word",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_r_by",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_r_half",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_word",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_dword"
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_commit_r",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_addr_in_pic_r",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_r_valid",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_r_bits_store"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_store_datafn_hi_r",
|
||||
"sink":"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_dccm_rden",
|
||||
"sources":[
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_stbuf_data_any",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_store_data_hi_r",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_stbuf_commit_any",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_addr_in_dccm_r",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_stbuf_reqvld_any",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_stbuf_addr_any",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_addr_r",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_ld_single_ecc_error_r_ff",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_addr_in_dccm_d",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_dma_dccm_wen",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_valid",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_load",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_r_store",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_store",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_addr_d",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_end_addr_d",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_r_word",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_r_by",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_r_half",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_word",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_dword"
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_bits_load",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_bits_store",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_bits_word",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_bits_dword",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_addr_d"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_store_data_r",
|
||||
"sources":[
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_store_data_hi_r",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_store_data_lo_r",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_addr_r",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_r_bits_store",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_r_bits_word",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_r_bits_by",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_r_bits_half"
|
||||
]
|
||||
},
|
||||
{
|
||||
|
|
@ -235,25 +238,6 @@
|
|||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_addr_d"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_dccm_wren",
|
||||
"sources":[
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_ld_single_ecc_error_r_ff",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_dma_dccm_wen",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_stbuf_commit_any",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_stbuf_reqvld_any",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_addr_in_dccm_d",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_valid",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_load",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_store",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_stbuf_addr_any",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_addr_d",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_end_addr_d",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_word",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_dword"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_dccm_dma_ecc_error",
|
||||
|
|
@ -277,6 +261,15 @@
|
|||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_stbuf_data_any"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_picm_rden",
|
||||
"sources":[
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_addr_in_pic_d",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_valid",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_bits_load"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_dccm_rd_addr_lo",
|
||||
|
|
@ -286,23 +279,32 @@
|
|||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_ld_single_ecc_error_r",
|
||||
"sink":"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_picm_wr_data",
|
||||
"sources":[
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_double_ecc_error_r",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_r_load",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_single_ecc_error_lo_r",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_raw_fwd_lo_r",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_single_ecc_error_hi_r",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_raw_fwd_hi_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_dccm_dma_rvalid",
|
||||
"sources":[
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_m_dma",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_m_valid",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_m_load"
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_dma_pic_wen",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_dma_mem_wdata",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_store_datafn_lo_r",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_stbuf_data_any",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_store_data_lo_r",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_stbuf_commit_any",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_addr_in_dccm_r",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_stbuf_reqvld_any",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_stbuf_addr_any",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_addr_r",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_ld_single_ecc_error_r_ff",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_addr_in_dccm_d",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_dma_dccm_wen",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_valid",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_bits_load",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_r_bits_store",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_bits_store",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_addr_d",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_end_addr_d",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_r_bits_word",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_r_bits_by",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_r_bits_half",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_bits_word",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_bits_dword"
|
||||
]
|
||||
},
|
||||
{
|
||||
|
|
@ -331,15 +333,11 @@
|
|||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_dccm_rden",
|
||||
"sink":"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_dccm_dma_rvalid",
|
||||
"sources":[
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_addr_in_dccm_d",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_valid",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_load",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_store",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_word",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_dword",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_addr_d"
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_m_bits_dma",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_m_valid",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_m_bits_load"
|
||||
]
|
||||
},
|
||||
{
|
||||
|
|
@ -351,11 +349,14 @@
|
|||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_picm_rden",
|
||||
"sink":"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_ld_single_ecc_error_r",
|
||||
"sources":[
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_addr_in_pic_d",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_valid",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_d_load"
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_double_ecc_error_r",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_pkt_r_bits_load",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_single_ecc_error_lo_r",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_raw_fwd_lo_r",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_single_ecc_error_hi_r",
|
||||
"~el2_lsu_dccm_ctl|el2_lsu_dccm_ctl>io_lsu_raw_fwd_hi_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
|
|
@ -364,8 +365,8 @@
|
|||
},
|
||||
{
|
||||
"class":"firrtl.transforms.BlackBoxResourceAnno",
|
||||
"target":"el2_lsu_dccm_ctl.TEC_RV_ICG",
|
||||
"resourceId":"/vsrc/TEC_RV_ICG.v"
|
||||
"target":"el2_lsu_dccm_ctl.gated_latch",
|
||||
"resourceId":"/vsrc/gated_latch.v"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.options.TargetDirAnnotation",
|
||||
|
|
|
|||
|
|
@ -1,12 +1,12 @@
|
|||
;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
|
||||
circuit el2_lsu_dccm_ctl :
|
||||
extmodule TEC_RV_ICG :
|
||||
extmodule gated_latch :
|
||||
output Q : Clock
|
||||
input CK : Clock
|
||||
input EN : UInt<1>
|
||||
input SE : UInt<1>
|
||||
|
||||
defname = TEC_RV_ICG
|
||||
defname = gated_latch
|
||||
|
||||
|
||||
module rvclkhdr :
|
||||
|
|
@ -14,23 +14,23 @@ circuit el2_lsu_dccm_ctl :
|
|||
input reset : Reset
|
||||
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||||
|
||||
inst clkhdr of TEC_RV_ICG @[beh_lib.scala 332:24]
|
||||
inst clkhdr of gated_latch @[el2_lib.scala 474:26]
|
||||
clkhdr.SE is invalid
|
||||
clkhdr.EN is invalid
|
||||
clkhdr.CK is invalid
|
||||
clkhdr.Q is invalid
|
||||
io.l1clk <= clkhdr.Q @[beh_lib.scala 333:12]
|
||||
clkhdr.CK <= io.clk @[beh_lib.scala 334:16]
|
||||
clkhdr.EN <= io.en @[beh_lib.scala 335:16]
|
||||
clkhdr.SE <= io.scan_mode @[beh_lib.scala 336:16]
|
||||
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
|
||||
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
|
||||
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
|
||||
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
|
||||
|
||||
extmodule TEC_RV_ICG_1 :
|
||||
extmodule gated_latch_1 :
|
||||
output Q : Clock
|
||||
input CK : Clock
|
||||
input EN : UInt<1>
|
||||
input SE : UInt<1>
|
||||
|
||||
defname = TEC_RV_ICG
|
||||
defname = gated_latch
|
||||
|
||||
|
||||
module rvclkhdr_1 :
|
||||
|
|
@ -38,20 +38,20 @@ circuit el2_lsu_dccm_ctl :
|
|||
input reset : Reset
|
||||
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||||
|
||||
inst clkhdr of TEC_RV_ICG_1 @[beh_lib.scala 332:24]
|
||||
inst clkhdr of gated_latch_1 @[el2_lib.scala 474:26]
|
||||
clkhdr.SE is invalid
|
||||
clkhdr.EN is invalid
|
||||
clkhdr.CK is invalid
|
||||
clkhdr.Q is invalid
|
||||
io.l1clk <= clkhdr.Q @[beh_lib.scala 333:12]
|
||||
clkhdr.CK <= io.clk @[beh_lib.scala 334:16]
|
||||
clkhdr.EN <= io.en @[beh_lib.scala 335:16]
|
||||
clkhdr.SE <= io.scan_mode @[beh_lib.scala 336:16]
|
||||
io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14]
|
||||
clkhdr.CK <= io.clk @[el2_lib.scala 476:18]
|
||||
clkhdr.EN <= io.en @[el2_lib.scala 477:18]
|
||||
clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18]
|
||||
|
||||
module el2_lsu_dccm_ctl :
|
||||
input clock : Clock
|
||||
input reset : AsyncReset
|
||||
output io : {flip lsu_c2_m_clk : Clock, flip lsu_c2_r_clk : Clock, flip lsu_free_c2_clk : Clock, flip lsu_c1_r_clk : Clock, flip lsu_store_c1_r_clk : Clock, flip lsu_pkt_d : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip lsu_pkt_m : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip lsu_pkt_r : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip addr_in_dccm_d : UInt<1>, flip addr_in_dccm_m : UInt<1>, flip addr_in_dccm_r : UInt<1>, flip addr_in_pic_d : UInt<1>, flip addr_in_pic_m : UInt<1>, flip addr_in_pic_r : UInt<1>, flip lsu_raw_fwd_lo_r : UInt<1>, flip lsu_raw_fwd_hi_r : UInt<1>, flip lsu_commit_r : UInt<1>, flip lsu_addr_d : UInt<32>, flip lsu_addr_m : UInt<16>, flip lsu_addr_r : UInt<32>, flip end_addr_d : UInt<16>, flip end_addr_m : UInt<16>, flip end_addr_r : UInt<16>, flip stbuf_reqvld_any : UInt<1>, flip stbuf_addr_any : UInt<16>, flip stbuf_data_any : UInt<32>, flip stbuf_ecc_any : UInt<7>, flip stbuf_fwddata_hi_m : UInt<32>, flip stbuf_fwddata_lo_m : UInt<32>, flip stbuf_fwdbyteen_lo_m : UInt<4>, flip stbuf_fwdbyteen_hi_m : UInt<4>, dccm_rdata_hi_r : UInt<32>, dccm_rdata_lo_r : UInt<32>, dccm_data_ecc_hi_r : UInt<7>, dccm_data_ecc_lo_r : UInt<7>, lsu_ld_data_r : UInt<32>, lsu_ld_data_corr_r : UInt<32>, flip lsu_double_ecc_error_r : UInt<1>, flip single_ecc_error_hi_r : UInt<1>, flip single_ecc_error_lo_r : UInt<1>, flip sec_data_hi_r : UInt<32>, flip sec_data_lo_r : UInt<32>, flip sec_data_hi_r_ff : UInt<32>, flip sec_data_lo_r_ff : UInt<32>, flip sec_data_ecc_hi_r_ff : UInt<7>, flip sec_data_ecc_lo_r_ff : UInt<7>, dccm_rdata_hi_m : UInt<32>, dccm_rdata_lo_m : UInt<32>, dccm_data_ecc_hi_m : UInt<7>, dccm_data_ecc_lo_m : UInt<7>, lsu_ld_data_m : UInt<32>, flip lsu_double_ecc_error_m : UInt<1>, flip sec_data_hi_m : UInt<32>, flip sec_data_lo_m : UInt<32>, flip store_data_m : UInt<32>, flip dma_dccm_wen : UInt<1>, flip dma_pic_wen : UInt<1>, flip dma_mem_tag_m : UInt<3>, flip dma_mem_addr : UInt<32>, flip dma_mem_wdata : UInt<64>, flip dma_dccm_wdata_lo : UInt<32>, flip dma_dccm_wdata_hi : UInt<32>, flip dma_dccm_wdata_ecc_hi : UInt<7>, flip dma_dccm_wdata_ecc_lo : UInt<7>, store_data_hi_r : UInt<32>, store_data_lo_r : UInt<32>, store_datafn_hi_r : UInt<32>, store_datafn_lo_r : UInt<32>, store_data_r : UInt<32>, ld_single_ecc_error_r : UInt<1>, ld_single_ecc_error_r_ff : UInt<1>, picm_mask_data_m : UInt<32>, lsu_stbuf_commit_any : UInt<1>, lsu_dccm_rden_m : UInt<1>, lsu_dccm_rden_r : UInt<1>, dccm_dma_rvalid : UInt<1>, dccm_dma_ecc_error : UInt<1>, dccm_dma_rtag : UInt<3>, dccm_dma_rdata : UInt<64>, dccm_wren : UInt<1>, dccm_rden : UInt<1>, dccm_wr_addr_lo : UInt<16>, dccm_wr_data_lo : UInt<39>, dccm_rd_addr_lo : UInt<16>, flip dccm_rd_data_lo : UInt<39>, dccm_wr_addr_hi : UInt<16>, dccm_wr_data_hi : UInt<39>, dccm_rd_addr_hi : UInt<16>, flip dccm_rd_data_hi : UInt<39>, picm_wren : UInt<1>, picm_rden : UInt<1>, picm_mken : UInt<1>, picm_rdaddr : UInt<32>, picm_wraddr : UInt<32>, picm_wr_data : UInt<32>, flip picm_rd_data : UInt<32>, flip scan_mode : UInt<1>}
|
||||
output io : {flip lsu_c2_m_clk : Clock, flip lsu_c2_r_clk : Clock, flip lsu_free_c2_clk : Clock, flip lsu_c1_r_clk : Clock, flip lsu_store_c1_r_clk : Clock, flip lsu_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_pkt_r : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip addr_in_dccm_d : UInt<1>, flip addr_in_dccm_m : UInt<1>, flip addr_in_dccm_r : UInt<1>, flip addr_in_pic_d : UInt<1>, flip addr_in_pic_m : UInt<1>, flip addr_in_pic_r : UInt<1>, flip lsu_raw_fwd_lo_r : UInt<1>, flip lsu_raw_fwd_hi_r : UInt<1>, flip lsu_commit_r : UInt<1>, flip lsu_addr_d : UInt<32>, flip lsu_addr_m : UInt<16>, flip lsu_addr_r : UInt<32>, flip end_addr_d : UInt<16>, flip end_addr_m : UInt<16>, flip end_addr_r : UInt<16>, flip stbuf_reqvld_any : UInt<1>, flip stbuf_addr_any : UInt<16>, flip stbuf_data_any : UInt<32>, flip stbuf_ecc_any : UInt<7>, flip stbuf_fwddata_hi_m : UInt<32>, flip stbuf_fwddata_lo_m : UInt<32>, flip stbuf_fwdbyteen_lo_m : UInt<4>, flip stbuf_fwdbyteen_hi_m : UInt<4>, dccm_rdata_hi_r : UInt<32>, dccm_rdata_lo_r : UInt<32>, dccm_data_ecc_hi_r : UInt<7>, dccm_data_ecc_lo_r : UInt<7>, lsu_ld_data_r : UInt<32>, lsu_ld_data_corr_r : UInt<32>, flip lsu_double_ecc_error_r : UInt<1>, flip single_ecc_error_hi_r : UInt<1>, flip single_ecc_error_lo_r : UInt<1>, flip sec_data_hi_r : UInt<32>, flip sec_data_lo_r : UInt<32>, flip sec_data_hi_r_ff : UInt<32>, flip sec_data_lo_r_ff : UInt<32>, flip sec_data_ecc_hi_r_ff : UInt<7>, flip sec_data_ecc_lo_r_ff : UInt<7>, dccm_rdata_hi_m : UInt<32>, dccm_rdata_lo_m : UInt<32>, dccm_data_ecc_hi_m : UInt<7>, dccm_data_ecc_lo_m : UInt<7>, lsu_ld_data_m : UInt<32>, flip lsu_double_ecc_error_m : UInt<1>, flip sec_data_hi_m : UInt<32>, flip sec_data_lo_m : UInt<32>, flip store_data_m : UInt<32>, flip dma_dccm_wen : UInt<1>, flip dma_pic_wen : UInt<1>, flip dma_mem_tag_m : UInt<3>, flip dma_mem_addr : UInt<32>, flip dma_mem_wdata : UInt<64>, flip dma_dccm_wdata_lo : UInt<32>, flip dma_dccm_wdata_hi : UInt<32>, flip dma_dccm_wdata_ecc_hi : UInt<7>, flip dma_dccm_wdata_ecc_lo : UInt<7>, store_data_hi_r : UInt<32>, store_data_lo_r : UInt<32>, store_datafn_hi_r : UInt<32>, store_datafn_lo_r : UInt<32>, store_data_r : UInt<32>, ld_single_ecc_error_r : UInt<1>, ld_single_ecc_error_r_ff : UInt<1>, picm_mask_data_m : UInt<32>, lsu_stbuf_commit_any : UInt<1>, lsu_dccm_rden_m : UInt<1>, lsu_dccm_rden_r : UInt<1>, dccm_dma_rvalid : UInt<1>, dccm_dma_ecc_error : UInt<1>, dccm_dma_rtag : UInt<3>, dccm_dma_rdata : UInt<64>, dccm_wren : UInt<1>, dccm_rden : UInt<1>, dccm_wr_addr_lo : UInt<16>, dccm_wr_data_lo : UInt<39>, dccm_rd_addr_lo : UInt<16>, flip dccm_rd_data_lo : UInt<39>, dccm_wr_addr_hi : UInt<16>, dccm_wr_data_hi : UInt<39>, dccm_rd_addr_hi : UInt<16>, flip dccm_rd_data_hi : UInt<39>, picm_wren : UInt<1>, picm_rden : UInt<1>, picm_mken : UInt<1>, picm_rdaddr : UInt<32>, picm_wraddr : UInt<32>, picm_wr_data : UInt<32>, flip picm_rd_data : UInt<32>, flip scan_mode : UInt<1>}
|
||||
|
||||
node picm_rd_data_m = cat(io.picm_rd_data, io.picm_rd_data) @[Cat.scala 29:58]
|
||||
node dccm_rdata_corr_r = cat(io.sec_data_hi_r, io.sec_data_lo_r) @[Cat.scala 29:58]
|
||||
|
|
@ -76,8 +76,8 @@ circuit el2_lsu_dccm_ctl :
|
|||
picm_rd_data_r <= UInt<1>("h00")
|
||||
wire lsu_ld_data_corr_m : UInt<64>
|
||||
lsu_ld_data_corr_m <= UInt<1>("h00")
|
||||
node _T = and(io.lsu_pkt_m.valid, io.lsu_pkt_m.load) @[el2_lsu_dccm_ctl.scala 161:50]
|
||||
node _T_1 = and(_T, io.lsu_pkt_m.dma) @[el2_lsu_dccm_ctl.scala 161:70]
|
||||
node _T = and(io.lsu_pkt_m.valid, io.lsu_pkt_m.bits.load) @[el2_lsu_dccm_ctl.scala 161:50]
|
||||
node _T_1 = and(_T, io.lsu_pkt_m.bits.dma) @[el2_lsu_dccm_ctl.scala 161:75]
|
||||
io.dccm_dma_rvalid <= _T_1 @[el2_lsu_dccm_ctl.scala 161:28]
|
||||
io.dccm_dma_ecc_error <= io.lsu_double_ecc_error_m @[el2_lsu_dccm_ctl.scala 162:28]
|
||||
io.dccm_dma_rdata <= lsu_rdata_corr_m @[el2_lsu_dccm_ctl.scala 163:28]
|
||||
|
|
@ -882,9 +882,9 @@ circuit el2_lsu_dccm_ctl :
|
|||
node _T_772 = eq(_T_770, _T_771) @[el2_lsu_dccm_ctl.scala 179:133]
|
||||
node _T_773 = or(_T_769, _T_772) @[el2_lsu_dccm_ctl.scala 179:101]
|
||||
node _T_774 = and(_T_773, io.lsu_pkt_d.valid) @[el2_lsu_dccm_ctl.scala 179:175]
|
||||
node _T_775 = and(_T_774, io.lsu_pkt_d.store) @[el2_lsu_dccm_ctl.scala 179:196]
|
||||
node _T_776 = and(_T_775, io.lsu_pkt_d.dma) @[el2_lsu_dccm_ctl.scala 179:217]
|
||||
node _T_777 = and(_T_776, io.addr_in_dccm_d) @[el2_lsu_dccm_ctl.scala 179:236]
|
||||
node _T_775 = and(_T_774, io.lsu_pkt_d.bits.store) @[el2_lsu_dccm_ctl.scala 179:196]
|
||||
node _T_776 = and(_T_775, io.lsu_pkt_d.bits.dma) @[el2_lsu_dccm_ctl.scala 179:222]
|
||||
node _T_777 = and(_T_776, io.addr_in_dccm_d) @[el2_lsu_dccm_ctl.scala 179:246]
|
||||
node _T_778 = bits(io.lsu_addr_m, 15, 2) @[el2_lsu_dccm_ctl.scala 180:21]
|
||||
node _T_779 = bits(io.lsu_addr_r, 15, 2) @[el2_lsu_dccm_ctl.scala 180:54]
|
||||
node _T_780 = eq(_T_778, _T_779) @[el2_lsu_dccm_ctl.scala 180:37]
|
||||
|
|
@ -893,10 +893,10 @@ circuit el2_lsu_dccm_ctl :
|
|||
node _T_783 = eq(_T_781, _T_782) @[el2_lsu_dccm_ctl.scala 180:110]
|
||||
node _T_784 = or(_T_780, _T_783) @[el2_lsu_dccm_ctl.scala 180:78]
|
||||
node _T_785 = and(_T_784, io.lsu_pkt_m.valid) @[el2_lsu_dccm_ctl.scala 180:152]
|
||||
node _T_786 = and(_T_785, io.lsu_pkt_m.store) @[el2_lsu_dccm_ctl.scala 180:173]
|
||||
node _T_787 = and(_T_786, io.lsu_pkt_m.dma) @[el2_lsu_dccm_ctl.scala 180:194]
|
||||
node _T_788 = and(_T_787, io.addr_in_dccm_m) @[el2_lsu_dccm_ctl.scala 180:213]
|
||||
node kill_ecc_corr_lo_r = or(_T_777, _T_788) @[el2_lsu_dccm_ctl.scala 179:257]
|
||||
node _T_786 = and(_T_785, io.lsu_pkt_m.bits.store) @[el2_lsu_dccm_ctl.scala 180:173]
|
||||
node _T_787 = and(_T_786, io.lsu_pkt_m.bits.dma) @[el2_lsu_dccm_ctl.scala 180:199]
|
||||
node _T_788 = and(_T_787, io.addr_in_dccm_m) @[el2_lsu_dccm_ctl.scala 180:223]
|
||||
node kill_ecc_corr_lo_r = or(_T_777, _T_788) @[el2_lsu_dccm_ctl.scala 179:267]
|
||||
node _T_789 = bits(io.lsu_addr_d, 15, 2) @[el2_lsu_dccm_ctl.scala 182:44]
|
||||
node _T_790 = bits(io.end_addr_r, 15, 2) @[el2_lsu_dccm_ctl.scala 182:77]
|
||||
node _T_791 = eq(_T_789, _T_790) @[el2_lsu_dccm_ctl.scala 182:60]
|
||||
|
|
@ -905,9 +905,9 @@ circuit el2_lsu_dccm_ctl :
|
|||
node _T_794 = eq(_T_792, _T_793) @[el2_lsu_dccm_ctl.scala 182:133]
|
||||
node _T_795 = or(_T_791, _T_794) @[el2_lsu_dccm_ctl.scala 182:101]
|
||||
node _T_796 = and(_T_795, io.lsu_pkt_d.valid) @[el2_lsu_dccm_ctl.scala 182:175]
|
||||
node _T_797 = and(_T_796, io.lsu_pkt_d.store) @[el2_lsu_dccm_ctl.scala 182:196]
|
||||
node _T_798 = and(_T_797, io.lsu_pkt_d.dma) @[el2_lsu_dccm_ctl.scala 182:217]
|
||||
node _T_799 = and(_T_798, io.addr_in_dccm_d) @[el2_lsu_dccm_ctl.scala 182:236]
|
||||
node _T_797 = and(_T_796, io.lsu_pkt_d.bits.store) @[el2_lsu_dccm_ctl.scala 182:196]
|
||||
node _T_798 = and(_T_797, io.lsu_pkt_d.bits.dma) @[el2_lsu_dccm_ctl.scala 182:222]
|
||||
node _T_799 = and(_T_798, io.addr_in_dccm_d) @[el2_lsu_dccm_ctl.scala 182:246]
|
||||
node _T_800 = bits(io.lsu_addr_m, 15, 2) @[el2_lsu_dccm_ctl.scala 183:21]
|
||||
node _T_801 = bits(io.end_addr_r, 15, 2) @[el2_lsu_dccm_ctl.scala 183:54]
|
||||
node _T_802 = eq(_T_800, _T_801) @[el2_lsu_dccm_ctl.scala 183:37]
|
||||
|
|
@ -916,28 +916,28 @@ circuit el2_lsu_dccm_ctl :
|
|||
node _T_805 = eq(_T_803, _T_804) @[el2_lsu_dccm_ctl.scala 183:110]
|
||||
node _T_806 = or(_T_802, _T_805) @[el2_lsu_dccm_ctl.scala 183:78]
|
||||
node _T_807 = and(_T_806, io.lsu_pkt_m.valid) @[el2_lsu_dccm_ctl.scala 183:152]
|
||||
node _T_808 = and(_T_807, io.lsu_pkt_m.store) @[el2_lsu_dccm_ctl.scala 183:173]
|
||||
node _T_809 = and(_T_808, io.lsu_pkt_m.dma) @[el2_lsu_dccm_ctl.scala 183:194]
|
||||
node _T_810 = and(_T_809, io.addr_in_dccm_m) @[el2_lsu_dccm_ctl.scala 183:213]
|
||||
node kill_ecc_corr_hi_r = or(_T_799, _T_810) @[el2_lsu_dccm_ctl.scala 182:257]
|
||||
node _T_811 = and(io.lsu_pkt_r.load, io.single_ecc_error_lo_r) @[el2_lsu_dccm_ctl.scala 185:55]
|
||||
node _T_812 = eq(io.lsu_raw_fwd_lo_r, UInt<1>("h00")) @[el2_lsu_dccm_ctl.scala 185:84]
|
||||
node ld_single_ecc_error_lo_r = and(_T_811, _T_812) @[el2_lsu_dccm_ctl.scala 185:82]
|
||||
node _T_813 = and(io.lsu_pkt_r.load, io.single_ecc_error_hi_r) @[el2_lsu_dccm_ctl.scala 186:55]
|
||||
node _T_814 = eq(io.lsu_raw_fwd_hi_r, UInt<1>("h00")) @[el2_lsu_dccm_ctl.scala 186:84]
|
||||
node ld_single_ecc_error_hi_r = and(_T_813, _T_814) @[el2_lsu_dccm_ctl.scala 186:82]
|
||||
node _T_808 = and(_T_807, io.lsu_pkt_m.bits.store) @[el2_lsu_dccm_ctl.scala 183:173]
|
||||
node _T_809 = and(_T_808, io.lsu_pkt_m.bits.dma) @[el2_lsu_dccm_ctl.scala 183:199]
|
||||
node _T_810 = and(_T_809, io.addr_in_dccm_m) @[el2_lsu_dccm_ctl.scala 183:223]
|
||||
node kill_ecc_corr_hi_r = or(_T_799, _T_810) @[el2_lsu_dccm_ctl.scala 182:267]
|
||||
node _T_811 = and(io.lsu_pkt_r.bits.load, io.single_ecc_error_lo_r) @[el2_lsu_dccm_ctl.scala 185:60]
|
||||
node _T_812 = eq(io.lsu_raw_fwd_lo_r, UInt<1>("h00")) @[el2_lsu_dccm_ctl.scala 185:89]
|
||||
node ld_single_ecc_error_lo_r = and(_T_811, _T_812) @[el2_lsu_dccm_ctl.scala 185:87]
|
||||
node _T_813 = and(io.lsu_pkt_r.bits.load, io.single_ecc_error_hi_r) @[el2_lsu_dccm_ctl.scala 186:60]
|
||||
node _T_814 = eq(io.lsu_raw_fwd_hi_r, UInt<1>("h00")) @[el2_lsu_dccm_ctl.scala 186:89]
|
||||
node ld_single_ecc_error_hi_r = and(_T_813, _T_814) @[el2_lsu_dccm_ctl.scala 186:87]
|
||||
node _T_815 = or(ld_single_ecc_error_lo_r, ld_single_ecc_error_hi_r) @[el2_lsu_dccm_ctl.scala 187:63]
|
||||
node _T_816 = eq(io.lsu_double_ecc_error_r, UInt<1>("h00")) @[el2_lsu_dccm_ctl.scala 187:93]
|
||||
node _T_817 = and(_T_815, _T_816) @[el2_lsu_dccm_ctl.scala 187:91]
|
||||
io.ld_single_ecc_error_r <= _T_817 @[el2_lsu_dccm_ctl.scala 187:34]
|
||||
node _T_818 = or(io.lsu_commit_r, io.lsu_pkt_r.dma) @[el2_lsu_dccm_ctl.scala 188:81]
|
||||
node _T_818 = or(io.lsu_commit_r, io.lsu_pkt_r.bits.dma) @[el2_lsu_dccm_ctl.scala 188:81]
|
||||
node _T_819 = and(ld_single_ecc_error_lo_r, _T_818) @[el2_lsu_dccm_ctl.scala 188:62]
|
||||
node _T_820 = eq(kill_ecc_corr_lo_r, UInt<1>("h00")) @[el2_lsu_dccm_ctl.scala 188:103]
|
||||
node ld_single_ecc_error_lo_r_ns = and(_T_819, _T_820) @[el2_lsu_dccm_ctl.scala 188:101]
|
||||
node _T_821 = or(io.lsu_commit_r, io.lsu_pkt_r.dma) @[el2_lsu_dccm_ctl.scala 189:81]
|
||||
node _T_820 = eq(kill_ecc_corr_lo_r, UInt<1>("h00")) @[el2_lsu_dccm_ctl.scala 188:108]
|
||||
node ld_single_ecc_error_lo_r_ns = and(_T_819, _T_820) @[el2_lsu_dccm_ctl.scala 188:106]
|
||||
node _T_821 = or(io.lsu_commit_r, io.lsu_pkt_r.bits.dma) @[el2_lsu_dccm_ctl.scala 189:81]
|
||||
node _T_822 = and(ld_single_ecc_error_hi_r, _T_821) @[el2_lsu_dccm_ctl.scala 189:62]
|
||||
node _T_823 = eq(kill_ecc_corr_hi_r, UInt<1>("h00")) @[el2_lsu_dccm_ctl.scala 189:103]
|
||||
node ld_single_ecc_error_hi_r_ns = and(_T_822, _T_823) @[el2_lsu_dccm_ctl.scala 189:101]
|
||||
node _T_823 = eq(kill_ecc_corr_hi_r, UInt<1>("h00")) @[el2_lsu_dccm_ctl.scala 189:108]
|
||||
node ld_single_ecc_error_hi_r_ns = and(_T_822, _T_823) @[el2_lsu_dccm_ctl.scala 189:106]
|
||||
reg lsu_double_ecc_error_r_ff : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_dccm_ctl.scala 191:74]
|
||||
lsu_double_ecc_error_r_ff <= io.lsu_double_ecc_error_r @[el2_lsu_dccm_ctl.scala 191:74]
|
||||
reg ld_single_ecc_error_hi_r_ff : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_dccm_ctl.scala 192:74]
|
||||
|
|
@ -947,34 +947,34 @@ circuit el2_lsu_dccm_ctl :
|
|||
node _T_824 = bits(io.end_addr_r, 15, 0) @[el2_lsu_dccm_ctl.scala 195:49]
|
||||
node _T_825 = bits(io.ld_single_ecc_error_r, 0, 0) @[el2_lsu_dccm_ctl.scala 195:90]
|
||||
node _T_826 = bits(io.scan_mode, 0, 0) @[el2_lsu_dccm_ctl.scala 195:116]
|
||||
inst rvclkhdr of rvclkhdr @[beh_lib.scala 352:21]
|
||||
inst rvclkhdr of rvclkhdr @[el2_lib.scala 508:23]
|
||||
rvclkhdr.clock <= clock
|
||||
rvclkhdr.reset <= reset
|
||||
rvclkhdr.io.clk <= clock @[beh_lib.scala 354:16]
|
||||
rvclkhdr.io.en <= _T_825 @[beh_lib.scala 355:15]
|
||||
rvclkhdr.io.scan_mode <= _T_826 @[beh_lib.scala 356:22]
|
||||
reg ld_sec_addr_hi_r_ff : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[beh_lib.scala 358:14]
|
||||
ld_sec_addr_hi_r_ff <= _T_824 @[beh_lib.scala 358:14]
|
||||
rvclkhdr.io.clk <= clock @[el2_lib.scala 510:18]
|
||||
rvclkhdr.io.en <= _T_825 @[el2_lib.scala 511:17]
|
||||
rvclkhdr.io.scan_mode <= _T_826 @[el2_lib.scala 512:24]
|
||||
reg ld_sec_addr_hi_r_ff : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
|
||||
ld_sec_addr_hi_r_ff <= _T_824 @[el2_lib.scala 514:16]
|
||||
node _T_827 = bits(io.lsu_addr_r, 15, 0) @[el2_lsu_dccm_ctl.scala 196:49]
|
||||
node _T_828 = bits(io.ld_single_ecc_error_r, 0, 0) @[el2_lsu_dccm_ctl.scala 196:90]
|
||||
node _T_829 = bits(io.scan_mode, 0, 0) @[el2_lsu_dccm_ctl.scala 196:116]
|
||||
inst rvclkhdr_1 of rvclkhdr_1 @[beh_lib.scala 352:21]
|
||||
inst rvclkhdr_1 of rvclkhdr_1 @[el2_lib.scala 508:23]
|
||||
rvclkhdr_1.clock <= clock
|
||||
rvclkhdr_1.reset <= reset
|
||||
rvclkhdr_1.io.clk <= clock @[beh_lib.scala 354:16]
|
||||
rvclkhdr_1.io.en <= _T_828 @[beh_lib.scala 355:15]
|
||||
rvclkhdr_1.io.scan_mode <= _T_829 @[beh_lib.scala 356:22]
|
||||
reg ld_sec_addr_lo_r_ff : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[beh_lib.scala 358:14]
|
||||
ld_sec_addr_lo_r_ff <= _T_827 @[beh_lib.scala 358:14]
|
||||
node _T_830 = or(io.lsu_pkt_d.word, io.lsu_pkt_d.dword) @[el2_lsu_dccm_ctl.scala 197:110]
|
||||
node _T_831 = eq(_T_830, UInt<1>("h00")) @[el2_lsu_dccm_ctl.scala 197:90]
|
||||
node _T_832 = bits(io.lsu_addr_d, 1, 0) @[el2_lsu_dccm_ctl.scala 197:148]
|
||||
node _T_833 = neq(_T_832, UInt<2>("h00")) @[el2_lsu_dccm_ctl.scala 197:154]
|
||||
node _T_834 = or(_T_831, _T_833) @[el2_lsu_dccm_ctl.scala 197:132]
|
||||
node _T_835 = and(io.lsu_pkt_d.store, _T_834) @[el2_lsu_dccm_ctl.scala 197:87]
|
||||
node _T_836 = or(io.lsu_pkt_d.load, _T_835) @[el2_lsu_dccm_ctl.scala 197:65]
|
||||
rvclkhdr_1.io.clk <= clock @[el2_lib.scala 510:18]
|
||||
rvclkhdr_1.io.en <= _T_828 @[el2_lib.scala 511:17]
|
||||
rvclkhdr_1.io.scan_mode <= _T_829 @[el2_lib.scala 512:24]
|
||||
reg ld_sec_addr_lo_r_ff : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16]
|
||||
ld_sec_addr_lo_r_ff <= _T_827 @[el2_lib.scala 514:16]
|
||||
node _T_830 = or(io.lsu_pkt_d.bits.word, io.lsu_pkt_d.bits.dword) @[el2_lsu_dccm_ctl.scala 197:125]
|
||||
node _T_831 = eq(_T_830, UInt<1>("h00")) @[el2_lsu_dccm_ctl.scala 197:100]
|
||||
node _T_832 = bits(io.lsu_addr_d, 1, 0) @[el2_lsu_dccm_ctl.scala 197:168]
|
||||
node _T_833 = neq(_T_832, UInt<2>("h00")) @[el2_lsu_dccm_ctl.scala 197:174]
|
||||
node _T_834 = or(_T_831, _T_833) @[el2_lsu_dccm_ctl.scala 197:152]
|
||||
node _T_835 = and(io.lsu_pkt_d.bits.store, _T_834) @[el2_lsu_dccm_ctl.scala 197:97]
|
||||
node _T_836 = or(io.lsu_pkt_d.bits.load, _T_835) @[el2_lsu_dccm_ctl.scala 197:70]
|
||||
node _T_837 = and(io.lsu_pkt_d.valid, _T_836) @[el2_lsu_dccm_ctl.scala 197:44]
|
||||
node lsu_dccm_rden_d = and(_T_837, io.addr_in_dccm_d) @[el2_lsu_dccm_ctl.scala 197:171]
|
||||
node lsu_dccm_rden_d = and(_T_837, io.addr_in_dccm_d) @[el2_lsu_dccm_ctl.scala 197:191]
|
||||
node _T_838 = or(ld_single_ecc_error_lo_r_ff, ld_single_ecc_error_hi_r_ff) @[el2_lsu_dccm_ctl.scala 200:63]
|
||||
node _T_839 = eq(lsu_double_ecc_error_r_ff, UInt<1>("h00")) @[el2_lsu_dccm_ctl.scala 200:96]
|
||||
node _T_840 = and(_T_838, _T_839) @[el2_lsu_dccm_ctl.scala 200:94]
|
||||
|
|
@ -1026,7 +1026,7 @@ circuit el2_lsu_dccm_ctl :
|
|||
node _T_879 = bits(io.end_addr_d, 15, 0) @[el2_lsu_dccm_ctl.scala 219:38]
|
||||
io.dccm_rd_addr_hi <= _T_879 @[el2_lsu_dccm_ctl.scala 219:22]
|
||||
node _T_880 = bits(io.ld_single_ecc_error_r_ff, 0, 0) @[el2_lsu_dccm_ctl.scala 221:57]
|
||||
node _T_881 = eq(ld_single_ecc_error_lo_r_ff, UInt<1>("h00")) @[el2_lsu_dccm_ctl.scala 222:36]
|
||||
node _T_881 = eq(ld_single_ecc_error_lo_r_ff, UInt<1>("h01")) @[el2_lsu_dccm_ctl.scala 222:36]
|
||||
node _T_882 = bits(io.sec_data_ecc_lo_r_ff, 6, 0) @[el2_lsu_dccm_ctl.scala 222:70]
|
||||
node _T_883 = bits(io.sec_data_lo_r_ff, 31, 0) @[el2_lsu_dccm_ctl.scala 222:110]
|
||||
node _T_884 = cat(_T_882, _T_883) @[Cat.scala 29:58]
|
||||
|
|
@ -1045,7 +1045,7 @@ circuit el2_lsu_dccm_ctl :
|
|||
node _T_897 = mux(_T_880, _T_888, _T_896) @[el2_lsu_dccm_ctl.scala 221:28]
|
||||
io.dccm_wr_data_lo <= _T_897 @[el2_lsu_dccm_ctl.scala 221:22]
|
||||
node _T_898 = bits(io.ld_single_ecc_error_r_ff, 0, 0) @[el2_lsu_dccm_ctl.scala 227:57]
|
||||
node _T_899 = eq(ld_single_ecc_error_hi_r_ff, UInt<1>("h00")) @[el2_lsu_dccm_ctl.scala 228:36]
|
||||
node _T_899 = eq(ld_single_ecc_error_hi_r_ff, UInt<1>("h01")) @[el2_lsu_dccm_ctl.scala 228:36]
|
||||
node _T_900 = bits(io.sec_data_ecc_hi_r_ff, 6, 0) @[el2_lsu_dccm_ctl.scala 228:71]
|
||||
node _T_901 = bits(io.sec_data_hi_r_ff, 31, 0) @[el2_lsu_dccm_ctl.scala 228:111]
|
||||
node _T_902 = cat(_T_900, _T_901) @[Cat.scala 29:58]
|
||||
|
|
@ -1063,46 +1063,46 @@ circuit el2_lsu_dccm_ctl :
|
|||
node _T_914 = mux(_T_907, _T_910, _T_913) @[el2_lsu_dccm_ctl.scala 230:8]
|
||||
node _T_915 = mux(_T_898, _T_906, _T_914) @[el2_lsu_dccm_ctl.scala 227:28]
|
||||
io.dccm_wr_data_hi <= _T_915 @[el2_lsu_dccm_ctl.scala 227:22]
|
||||
node _T_916 = bits(io.lsu_pkt_m.store, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_916 = bits(io.lsu_pkt_m.bits.store, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_917 = mux(_T_916, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_918 = bits(io.lsu_pkt_m.by, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_918 = bits(io.lsu_pkt_m.bits.by, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_919 = mux(_T_918, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_920 = and(_T_919, UInt<4>("h01")) @[el2_lsu_dccm_ctl.scala 234:84]
|
||||
node _T_921 = bits(io.lsu_pkt_m.half, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_920 = and(_T_919, UInt<4>("h01")) @[el2_lsu_dccm_ctl.scala 234:94]
|
||||
node _T_921 = bits(io.lsu_pkt_m.bits.half, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_922 = mux(_T_921, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_923 = and(_T_922, UInt<4>("h03")) @[el2_lsu_dccm_ctl.scala 235:33]
|
||||
node _T_924 = or(_T_920, _T_923) @[el2_lsu_dccm_ctl.scala 234:97]
|
||||
node _T_925 = bits(io.lsu_pkt_m.word, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_923 = and(_T_922, UInt<4>("h03")) @[el2_lsu_dccm_ctl.scala 235:38]
|
||||
node _T_924 = or(_T_920, _T_923) @[el2_lsu_dccm_ctl.scala 234:107]
|
||||
node _T_925 = bits(io.lsu_pkt_m.bits.word, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_926 = mux(_T_925, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_927 = and(_T_926, UInt<4>("h0f")) @[el2_lsu_dccm_ctl.scala 236:33]
|
||||
node _T_928 = or(_T_924, _T_927) @[el2_lsu_dccm_ctl.scala 235:46]
|
||||
node store_byteen_m = and(_T_917, _T_928) @[el2_lsu_dccm_ctl.scala 234:53]
|
||||
node _T_929 = bits(io.lsu_pkt_r.store, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_927 = and(_T_926, UInt<4>("h0f")) @[el2_lsu_dccm_ctl.scala 236:38]
|
||||
node _T_928 = or(_T_924, _T_927) @[el2_lsu_dccm_ctl.scala 235:51]
|
||||
node store_byteen_m = and(_T_917, _T_928) @[el2_lsu_dccm_ctl.scala 234:58]
|
||||
node _T_929 = bits(io.lsu_pkt_r.bits.store, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_930 = mux(_T_929, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_931 = bits(io.lsu_pkt_r.by, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_931 = bits(io.lsu_pkt_r.bits.by, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_932 = mux(_T_931, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_933 = and(_T_932, UInt<4>("h01")) @[el2_lsu_dccm_ctl.scala 238:84]
|
||||
node _T_934 = bits(io.lsu_pkt_r.half, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_933 = and(_T_932, UInt<4>("h01")) @[el2_lsu_dccm_ctl.scala 238:94]
|
||||
node _T_934 = bits(io.lsu_pkt_r.bits.half, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_935 = mux(_T_934, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_936 = and(_T_935, UInt<4>("h03")) @[el2_lsu_dccm_ctl.scala 239:33]
|
||||
node _T_937 = or(_T_933, _T_936) @[el2_lsu_dccm_ctl.scala 238:97]
|
||||
node _T_938 = bits(io.lsu_pkt_r.word, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_936 = and(_T_935, UInt<4>("h03")) @[el2_lsu_dccm_ctl.scala 239:38]
|
||||
node _T_937 = or(_T_933, _T_936) @[el2_lsu_dccm_ctl.scala 238:107]
|
||||
node _T_938 = bits(io.lsu_pkt_r.bits.word, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_939 = mux(_T_938, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_940 = and(_T_939, UInt<4>("h0f")) @[el2_lsu_dccm_ctl.scala 240:33]
|
||||
node _T_941 = or(_T_937, _T_940) @[el2_lsu_dccm_ctl.scala 239:46]
|
||||
node store_byteen_r = and(_T_930, _T_941) @[el2_lsu_dccm_ctl.scala 238:53]
|
||||
node _T_940 = and(_T_939, UInt<4>("h0f")) @[el2_lsu_dccm_ctl.scala 240:38]
|
||||
node _T_941 = or(_T_937, _T_940) @[el2_lsu_dccm_ctl.scala 239:51]
|
||||
node store_byteen_r = and(_T_930, _T_941) @[el2_lsu_dccm_ctl.scala 238:58]
|
||||
wire store_byteen_ext_m : UInt<8>
|
||||
store_byteen_ext_m <= UInt<1>("h00")
|
||||
node _T_942 = bits(store_byteen_m, 3, 0) @[el2_lsu_dccm_ctl.scala 242:43]
|
||||
node _T_943 = bits(io.lsu_addr_m, 1, 0) @[el2_lsu_dccm_ctl.scala 242:65]
|
||||
node _T_944 = dshl(_T_942, _T_943) @[el2_lsu_dccm_ctl.scala 242:49]
|
||||
store_byteen_ext_m <= _T_944 @[el2_lsu_dccm_ctl.scala 242:26]
|
||||
node _T_942 = bits(store_byteen_m, 3, 0) @[el2_lsu_dccm_ctl.scala 242:39]
|
||||
node _T_943 = bits(io.lsu_addr_m, 1, 0) @[el2_lsu_dccm_ctl.scala 242:61]
|
||||
node _T_944 = dshl(_T_942, _T_943) @[el2_lsu_dccm_ctl.scala 242:45]
|
||||
store_byteen_ext_m <= _T_944 @[el2_lsu_dccm_ctl.scala 242:22]
|
||||
wire store_byteen_ext_r : UInt<8>
|
||||
store_byteen_ext_r <= UInt<1>("h00")
|
||||
node _T_945 = bits(store_byteen_r, 3, 0) @[el2_lsu_dccm_ctl.scala 244:43]
|
||||
node _T_946 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_dccm_ctl.scala 244:65]
|
||||
node _T_947 = dshl(_T_945, _T_946) @[el2_lsu_dccm_ctl.scala 244:49]
|
||||
store_byteen_ext_r <= _T_947 @[el2_lsu_dccm_ctl.scala 244:26]
|
||||
node _T_945 = bits(store_byteen_r, 3, 0) @[el2_lsu_dccm_ctl.scala 244:39]
|
||||
node _T_946 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_dccm_ctl.scala 244:61]
|
||||
node _T_947 = dshl(_T_945, _T_946) @[el2_lsu_dccm_ctl.scala 244:45]
|
||||
store_byteen_ext_r <= _T_947 @[el2_lsu_dccm_ctl.scala 244:22]
|
||||
node _T_948 = bits(io.stbuf_addr_any, 15, 2) @[el2_lsu_dccm_ctl.scala 247:51]
|
||||
node _T_949 = bits(io.lsu_addr_m, 15, 2) @[el2_lsu_dccm_ctl.scala 247:84]
|
||||
node _T_950 = eq(_T_948, _T_949) @[el2_lsu_dccm_ctl.scala 247:67]
|
||||
|
|
@ -1780,13 +1780,13 @@ circuit el2_lsu_dccm_ctl :
|
|||
node _T_1579 = and(_T_1577, _T_1578) @[Bitwise.scala 103:75]
|
||||
node _T_1580 = or(_T_1575, _T_1579) @[Bitwise.scala 103:39]
|
||||
io.store_datafn_lo_r <= _T_1580 @[el2_lsu_dccm_ctl.scala 285:29]
|
||||
node _T_1581 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_r_lo) @[el2_lsu_dccm_ctl.scala 286:105]
|
||||
node _T_1582 = bits(store_byteen_ext_r, 0, 0) @[el2_lsu_dccm_ctl.scala 286:150]
|
||||
node _T_1581 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_r_hi) @[el2_lsu_dccm_ctl.scala 286:105]
|
||||
node _T_1582 = bits(store_byteen_ext_r, 4, 4) @[el2_lsu_dccm_ctl.scala 286:150]
|
||||
node _T_1583 = eq(_T_1582, UInt<1>("h00")) @[el2_lsu_dccm_ctl.scala 286:131]
|
||||
node _T_1584 = and(_T_1581, _T_1583) @[el2_lsu_dccm_ctl.scala 286:129]
|
||||
node _T_1585 = bits(_T_1584, 0, 0) @[el2_lsu_dccm_ctl.scala 286:155]
|
||||
node _T_1586 = bits(io.stbuf_data_any, 7, 0) @[el2_lsu_dccm_ctl.scala 286:179]
|
||||
node _T_1587 = bits(io.store_data_hi_r, 7, 0) @[el2_lsu_dccm_ctl.scala 286:211]
|
||||
node _T_1585 = bits(_T_1584, 0, 0) @[el2_lsu_dccm_ctl.scala 286:157]
|
||||
node _T_1586 = bits(io.stbuf_data_any, 7, 0) @[el2_lsu_dccm_ctl.scala 286:181]
|
||||
node _T_1587 = bits(io.store_data_hi_r, 7, 0) @[el2_lsu_dccm_ctl.scala 286:213]
|
||||
node _T_1588 = mux(_T_1585, _T_1586, _T_1587) @[el2_lsu_dccm_ctl.scala 286:79]
|
||||
node _T_1589 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
|
||||
node _T_1590 = xor(UInt<8>("h0ff"), _T_1589) @[Bitwise.scala 102:21]
|
||||
|
|
@ -1817,13 +1817,13 @@ circuit el2_lsu_dccm_ctl :
|
|||
node _T_1615 = not(_T_1610) @[Bitwise.scala 103:77]
|
||||
node _T_1616 = and(_T_1614, _T_1615) @[Bitwise.scala 103:75]
|
||||
node _T_1617 = or(_T_1612, _T_1616) @[Bitwise.scala 103:39]
|
||||
node _T_1618 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_r_lo) @[el2_lsu_dccm_ctl.scala 286:105]
|
||||
node _T_1619 = bits(store_byteen_ext_r, 1, 1) @[el2_lsu_dccm_ctl.scala 286:150]
|
||||
node _T_1618 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_r_hi) @[el2_lsu_dccm_ctl.scala 286:105]
|
||||
node _T_1619 = bits(store_byteen_ext_r, 5, 5) @[el2_lsu_dccm_ctl.scala 286:150]
|
||||
node _T_1620 = eq(_T_1619, UInt<1>("h00")) @[el2_lsu_dccm_ctl.scala 286:131]
|
||||
node _T_1621 = and(_T_1618, _T_1620) @[el2_lsu_dccm_ctl.scala 286:129]
|
||||
node _T_1622 = bits(_T_1621, 0, 0) @[el2_lsu_dccm_ctl.scala 286:155]
|
||||
node _T_1623 = bits(io.stbuf_data_any, 15, 8) @[el2_lsu_dccm_ctl.scala 286:179]
|
||||
node _T_1624 = bits(io.store_data_hi_r, 15, 8) @[el2_lsu_dccm_ctl.scala 286:211]
|
||||
node _T_1622 = bits(_T_1621, 0, 0) @[el2_lsu_dccm_ctl.scala 286:157]
|
||||
node _T_1623 = bits(io.stbuf_data_any, 15, 8) @[el2_lsu_dccm_ctl.scala 286:181]
|
||||
node _T_1624 = bits(io.store_data_hi_r, 15, 8) @[el2_lsu_dccm_ctl.scala 286:213]
|
||||
node _T_1625 = mux(_T_1622, _T_1623, _T_1624) @[el2_lsu_dccm_ctl.scala 286:79]
|
||||
node _T_1626 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
|
||||
node _T_1627 = xor(UInt<8>("h0ff"), _T_1626) @[Bitwise.scala 102:21]
|
||||
|
|
@ -1854,13 +1854,13 @@ circuit el2_lsu_dccm_ctl :
|
|||
node _T_1652 = not(_T_1647) @[Bitwise.scala 103:77]
|
||||
node _T_1653 = and(_T_1651, _T_1652) @[Bitwise.scala 103:75]
|
||||
node _T_1654 = or(_T_1649, _T_1653) @[Bitwise.scala 103:39]
|
||||
node _T_1655 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_r_lo) @[el2_lsu_dccm_ctl.scala 286:105]
|
||||
node _T_1656 = bits(store_byteen_ext_r, 2, 2) @[el2_lsu_dccm_ctl.scala 286:150]
|
||||
node _T_1655 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_r_hi) @[el2_lsu_dccm_ctl.scala 286:105]
|
||||
node _T_1656 = bits(store_byteen_ext_r, 6, 6) @[el2_lsu_dccm_ctl.scala 286:150]
|
||||
node _T_1657 = eq(_T_1656, UInt<1>("h00")) @[el2_lsu_dccm_ctl.scala 286:131]
|
||||
node _T_1658 = and(_T_1655, _T_1657) @[el2_lsu_dccm_ctl.scala 286:129]
|
||||
node _T_1659 = bits(_T_1658, 0, 0) @[el2_lsu_dccm_ctl.scala 286:155]
|
||||
node _T_1660 = bits(io.stbuf_data_any, 23, 16) @[el2_lsu_dccm_ctl.scala 286:179]
|
||||
node _T_1661 = bits(io.store_data_hi_r, 23, 16) @[el2_lsu_dccm_ctl.scala 286:211]
|
||||
node _T_1659 = bits(_T_1658, 0, 0) @[el2_lsu_dccm_ctl.scala 286:157]
|
||||
node _T_1660 = bits(io.stbuf_data_any, 23, 16) @[el2_lsu_dccm_ctl.scala 286:181]
|
||||
node _T_1661 = bits(io.store_data_hi_r, 23, 16) @[el2_lsu_dccm_ctl.scala 286:213]
|
||||
node _T_1662 = mux(_T_1659, _T_1660, _T_1661) @[el2_lsu_dccm_ctl.scala 286:79]
|
||||
node _T_1663 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
|
||||
node _T_1664 = xor(UInt<8>("h0ff"), _T_1663) @[Bitwise.scala 102:21]
|
||||
|
|
@ -1891,13 +1891,13 @@ circuit el2_lsu_dccm_ctl :
|
|||
node _T_1689 = not(_T_1684) @[Bitwise.scala 103:77]
|
||||
node _T_1690 = and(_T_1688, _T_1689) @[Bitwise.scala 103:75]
|
||||
node _T_1691 = or(_T_1686, _T_1690) @[Bitwise.scala 103:39]
|
||||
node _T_1692 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_r_lo) @[el2_lsu_dccm_ctl.scala 286:105]
|
||||
node _T_1693 = bits(store_byteen_ext_r, 3, 3) @[el2_lsu_dccm_ctl.scala 286:150]
|
||||
node _T_1692 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_r_hi) @[el2_lsu_dccm_ctl.scala 286:105]
|
||||
node _T_1693 = bits(store_byteen_ext_r, 7, 7) @[el2_lsu_dccm_ctl.scala 286:150]
|
||||
node _T_1694 = eq(_T_1693, UInt<1>("h00")) @[el2_lsu_dccm_ctl.scala 286:131]
|
||||
node _T_1695 = and(_T_1692, _T_1694) @[el2_lsu_dccm_ctl.scala 286:129]
|
||||
node _T_1696 = bits(_T_1695, 0, 0) @[el2_lsu_dccm_ctl.scala 286:155]
|
||||
node _T_1697 = bits(io.stbuf_data_any, 31, 24) @[el2_lsu_dccm_ctl.scala 286:179]
|
||||
node _T_1698 = bits(io.store_data_hi_r, 31, 24) @[el2_lsu_dccm_ctl.scala 286:211]
|
||||
node _T_1696 = bits(_T_1695, 0, 0) @[el2_lsu_dccm_ctl.scala 286:157]
|
||||
node _T_1697 = bits(io.stbuf_data_any, 31, 24) @[el2_lsu_dccm_ctl.scala 286:181]
|
||||
node _T_1698 = bits(io.store_data_hi_r, 31, 24) @[el2_lsu_dccm_ctl.scala 286:213]
|
||||
node _T_1699 = mux(_T_1696, _T_1697, _T_1698) @[el2_lsu_dccm_ctl.scala 286:79]
|
||||
node _T_1700 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47]
|
||||
node _T_1701 = xor(UInt<8>("h0ff"), _T_1700) @[Bitwise.scala 102:21]
|
||||
|
|
@ -2071,29 +2071,29 @@ circuit el2_lsu_dccm_ctl :
|
|||
io.dccm_data_ecc_lo_m <= _T_1856 @[el2_lsu_dccm_ctl.scala 291:27]
|
||||
node _T_1857 = bits(io.dccm_rd_data_hi, 38, 32) @[el2_lsu_dccm_ctl.scala 292:48]
|
||||
io.dccm_data_ecc_hi_m <= _T_1857 @[el2_lsu_dccm_ctl.scala 292:27]
|
||||
node _T_1858 = and(io.lsu_pkt_r.valid, io.lsu_pkt_r.store) @[el2_lsu_dccm_ctl.scala 294:50]
|
||||
node _T_1859 = and(_T_1858, io.addr_in_pic_r) @[el2_lsu_dccm_ctl.scala 294:71]
|
||||
node _T_1860 = and(_T_1859, io.lsu_commit_r) @[el2_lsu_dccm_ctl.scala 294:90]
|
||||
node _T_1861 = or(_T_1860, io.dma_pic_wen) @[el2_lsu_dccm_ctl.scala 294:109]
|
||||
node _T_1858 = and(io.lsu_pkt_r.valid, io.lsu_pkt_r.bits.store) @[el2_lsu_dccm_ctl.scala 294:50]
|
||||
node _T_1859 = and(_T_1858, io.addr_in_pic_r) @[el2_lsu_dccm_ctl.scala 294:76]
|
||||
node _T_1860 = and(_T_1859, io.lsu_commit_r) @[el2_lsu_dccm_ctl.scala 294:95]
|
||||
node _T_1861 = or(_T_1860, io.dma_pic_wen) @[el2_lsu_dccm_ctl.scala 294:114]
|
||||
io.picm_wren <= _T_1861 @[el2_lsu_dccm_ctl.scala 294:27]
|
||||
node _T_1862 = and(io.lsu_pkt_d.valid, io.lsu_pkt_d.load) @[el2_lsu_dccm_ctl.scala 295:50]
|
||||
node _T_1863 = and(_T_1862, io.addr_in_pic_d) @[el2_lsu_dccm_ctl.scala 295:71]
|
||||
node _T_1862 = and(io.lsu_pkt_d.valid, io.lsu_pkt_d.bits.load) @[el2_lsu_dccm_ctl.scala 295:50]
|
||||
node _T_1863 = and(_T_1862, io.addr_in_pic_d) @[el2_lsu_dccm_ctl.scala 295:76]
|
||||
io.picm_rden <= _T_1863 @[el2_lsu_dccm_ctl.scala 295:27]
|
||||
node _T_1864 = and(io.lsu_pkt_d.valid, io.lsu_pkt_d.store) @[el2_lsu_dccm_ctl.scala 296:50]
|
||||
node _T_1865 = and(_T_1864, io.addr_in_pic_d) @[el2_lsu_dccm_ctl.scala 296:71]
|
||||
node _T_1864 = and(io.lsu_pkt_d.valid, io.lsu_pkt_d.bits.store) @[el2_lsu_dccm_ctl.scala 296:50]
|
||||
node _T_1865 = and(_T_1864, io.addr_in_pic_d) @[el2_lsu_dccm_ctl.scala 296:76]
|
||||
io.picm_mken <= _T_1865 @[el2_lsu_dccm_ctl.scala 296:27]
|
||||
node _T_1866 = mux(UInt<1>("h00"), UInt<17>("h01ffff"), UInt<17>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_1867 = bits(io.lsu_addr_d, 14, 0) @[el2_lsu_dccm_ctl.scala 297:85]
|
||||
node _T_1867 = bits(io.lsu_addr_d, 14, 0) @[el2_lsu_dccm_ctl.scala 297:95]
|
||||
node _T_1868 = cat(_T_1866, _T_1867) @[Cat.scala 29:58]
|
||||
node _T_1869 = or(UInt<32>("h0f00c0000"), _T_1868) @[el2_lsu_dccm_ctl.scala 297:44]
|
||||
node _T_1869 = or(UInt<32>("h0f00c0000"), _T_1868) @[el2_lsu_dccm_ctl.scala 297:54]
|
||||
io.picm_rdaddr <= _T_1869 @[el2_lsu_dccm_ctl.scala 297:27]
|
||||
node _T_1870 = mux(UInt<1>("h00"), UInt<17>("h01ffff"), UInt<17>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_1871 = bits(io.dma_pic_wen, 0, 0) @[el2_lsu_dccm_ctl.scala 298:91]
|
||||
node _T_1872 = bits(io.dma_mem_addr, 14, 0) @[el2_lsu_dccm_ctl.scala 298:113]
|
||||
node _T_1873 = bits(io.lsu_addr_r, 14, 0) @[el2_lsu_dccm_ctl.scala 298:141]
|
||||
node _T_1874 = mux(_T_1871, _T_1872, _T_1873) @[el2_lsu_dccm_ctl.scala 298:75]
|
||||
node _T_1871 = bits(io.dma_pic_wen, 0, 0) @[el2_lsu_dccm_ctl.scala 298:101]
|
||||
node _T_1872 = bits(io.dma_mem_addr, 14, 0) @[el2_lsu_dccm_ctl.scala 298:123]
|
||||
node _T_1873 = bits(io.lsu_addr_r, 14, 0) @[el2_lsu_dccm_ctl.scala 298:151]
|
||||
node _T_1874 = mux(_T_1871, _T_1872, _T_1873) @[el2_lsu_dccm_ctl.scala 298:85]
|
||||
node _T_1875 = cat(_T_1870, _T_1874) @[Cat.scala 29:58]
|
||||
node _T_1876 = or(UInt<32>("h0f00c0000"), _T_1875) @[el2_lsu_dccm_ctl.scala 298:44]
|
||||
node _T_1876 = or(UInt<32>("h0f00c0000"), _T_1875) @[el2_lsu_dccm_ctl.scala 298:54]
|
||||
io.picm_wraddr <= _T_1876 @[el2_lsu_dccm_ctl.scala 298:27]
|
||||
node _T_1877 = bits(picm_rd_data_m, 31, 0) @[el2_lsu_dccm_ctl.scala 299:44]
|
||||
io.picm_mask_data_m <= _T_1877 @[el2_lsu_dccm_ctl.scala 299:27]
|
||||
|
|
|
|||
|
|
@ -4,20 +4,20 @@ module rvclkhdr(
|
|||
input io_en,
|
||||
input io_scan_mode
|
||||
);
|
||||
wire clkhdr_Q; // @[beh_lib.scala 332:24]
|
||||
wire clkhdr_CK; // @[beh_lib.scala 332:24]
|
||||
wire clkhdr_EN; // @[beh_lib.scala 332:24]
|
||||
wire clkhdr_SE; // @[beh_lib.scala 332:24]
|
||||
TEC_RV_ICG clkhdr ( // @[beh_lib.scala 332:24]
|
||||
wire clkhdr_Q; // @[el2_lib.scala 474:26]
|
||||
wire clkhdr_CK; // @[el2_lib.scala 474:26]
|
||||
wire clkhdr_EN; // @[el2_lib.scala 474:26]
|
||||
wire clkhdr_SE; // @[el2_lib.scala 474:26]
|
||||
gated_latch clkhdr ( // @[el2_lib.scala 474:26]
|
||||
.Q(clkhdr_Q),
|
||||
.CK(clkhdr_CK),
|
||||
.EN(clkhdr_EN),
|
||||
.SE(clkhdr_SE)
|
||||
);
|
||||
assign io_l1clk = clkhdr_Q; // @[beh_lib.scala 333:12]
|
||||
assign clkhdr_CK = io_clk; // @[beh_lib.scala 334:16]
|
||||
assign clkhdr_EN = io_en; // @[beh_lib.scala 335:16]
|
||||
assign clkhdr_SE = io_scan_mode; // @[beh_lib.scala 336:16]
|
||||
assign io_l1clk = clkhdr_Q; // @[el2_lib.scala 475:14]
|
||||
assign clkhdr_CK = io_clk; // @[el2_lib.scala 476:18]
|
||||
assign clkhdr_EN = io_en; // @[el2_lib.scala 477:18]
|
||||
assign clkhdr_SE = io_scan_mode; // @[el2_lib.scala 478:18]
|
||||
endmodule
|
||||
module el2_lsu_dccm_ctl(
|
||||
input clock,
|
||||
|
|
@ -27,45 +27,45 @@ module el2_lsu_dccm_ctl(
|
|||
input io_lsu_free_c2_clk,
|
||||
input io_lsu_c1_r_clk,
|
||||
input io_lsu_store_c1_r_clk,
|
||||
input io_lsu_pkt_d_fast_int,
|
||||
input io_lsu_pkt_d_by,
|
||||
input io_lsu_pkt_d_half,
|
||||
input io_lsu_pkt_d_word,
|
||||
input io_lsu_pkt_d_dword,
|
||||
input io_lsu_pkt_d_load,
|
||||
input io_lsu_pkt_d_store,
|
||||
input io_lsu_pkt_d_unsign,
|
||||
input io_lsu_pkt_d_dma,
|
||||
input io_lsu_pkt_d_store_data_bypass_d,
|
||||
input io_lsu_pkt_d_load_ldst_bypass_d,
|
||||
input io_lsu_pkt_d_store_data_bypass_m,
|
||||
input io_lsu_pkt_d_valid,
|
||||
input io_lsu_pkt_m_fast_int,
|
||||
input io_lsu_pkt_m_by,
|
||||
input io_lsu_pkt_m_half,
|
||||
input io_lsu_pkt_m_word,
|
||||
input io_lsu_pkt_m_dword,
|
||||
input io_lsu_pkt_m_load,
|
||||
input io_lsu_pkt_m_store,
|
||||
input io_lsu_pkt_m_unsign,
|
||||
input io_lsu_pkt_m_dma,
|
||||
input io_lsu_pkt_m_store_data_bypass_d,
|
||||
input io_lsu_pkt_m_load_ldst_bypass_d,
|
||||
input io_lsu_pkt_m_store_data_bypass_m,
|
||||
input io_lsu_pkt_d_bits_fast_int,
|
||||
input io_lsu_pkt_d_bits_by,
|
||||
input io_lsu_pkt_d_bits_half,
|
||||
input io_lsu_pkt_d_bits_word,
|
||||
input io_lsu_pkt_d_bits_dword,
|
||||
input io_lsu_pkt_d_bits_load,
|
||||
input io_lsu_pkt_d_bits_store,
|
||||
input io_lsu_pkt_d_bits_unsign,
|
||||
input io_lsu_pkt_d_bits_dma,
|
||||
input io_lsu_pkt_d_bits_store_data_bypass_d,
|
||||
input io_lsu_pkt_d_bits_load_ldst_bypass_d,
|
||||
input io_lsu_pkt_d_bits_store_data_bypass_m,
|
||||
input io_lsu_pkt_m_valid,
|
||||
input io_lsu_pkt_r_fast_int,
|
||||
input io_lsu_pkt_r_by,
|
||||
input io_lsu_pkt_r_half,
|
||||
input io_lsu_pkt_r_word,
|
||||
input io_lsu_pkt_r_dword,
|
||||
input io_lsu_pkt_r_load,
|
||||
input io_lsu_pkt_r_store,
|
||||
input io_lsu_pkt_r_unsign,
|
||||
input io_lsu_pkt_r_dma,
|
||||
input io_lsu_pkt_r_store_data_bypass_d,
|
||||
input io_lsu_pkt_r_load_ldst_bypass_d,
|
||||
input io_lsu_pkt_r_store_data_bypass_m,
|
||||
input io_lsu_pkt_m_bits_fast_int,
|
||||
input io_lsu_pkt_m_bits_by,
|
||||
input io_lsu_pkt_m_bits_half,
|
||||
input io_lsu_pkt_m_bits_word,
|
||||
input io_lsu_pkt_m_bits_dword,
|
||||
input io_lsu_pkt_m_bits_load,
|
||||
input io_lsu_pkt_m_bits_store,
|
||||
input io_lsu_pkt_m_bits_unsign,
|
||||
input io_lsu_pkt_m_bits_dma,
|
||||
input io_lsu_pkt_m_bits_store_data_bypass_d,
|
||||
input io_lsu_pkt_m_bits_load_ldst_bypass_d,
|
||||
input io_lsu_pkt_m_bits_store_data_bypass_m,
|
||||
input io_lsu_pkt_r_valid,
|
||||
input io_lsu_pkt_r_bits_fast_int,
|
||||
input io_lsu_pkt_r_bits_by,
|
||||
input io_lsu_pkt_r_bits_half,
|
||||
input io_lsu_pkt_r_bits_word,
|
||||
input io_lsu_pkt_r_bits_dword,
|
||||
input io_lsu_pkt_r_bits_load,
|
||||
input io_lsu_pkt_r_bits_store,
|
||||
input io_lsu_pkt_r_bits_unsign,
|
||||
input io_lsu_pkt_r_bits_dma,
|
||||
input io_lsu_pkt_r_bits_store_data_bypass_d,
|
||||
input io_lsu_pkt_r_bits_load_ldst_bypass_d,
|
||||
input io_lsu_pkt_r_bits_store_data_bypass_m,
|
||||
input io_addr_in_dccm_d,
|
||||
input io_addr_in_dccm_m,
|
||||
input io_addr_in_dccm_r,
|
||||
|
|
@ -168,18 +168,18 @@ module el2_lsu_dccm_ctl(
|
|||
reg [31:0] _RAND_8;
|
||||
reg [31:0] _RAND_9;
|
||||
`endif // RANDOMIZE_REG_INIT
|
||||
wire rvclkhdr_io_l1clk; // @[beh_lib.scala 352:21]
|
||||
wire rvclkhdr_io_clk; // @[beh_lib.scala 352:21]
|
||||
wire rvclkhdr_io_en; // @[beh_lib.scala 352:21]
|
||||
wire rvclkhdr_io_scan_mode; // @[beh_lib.scala 352:21]
|
||||
wire rvclkhdr_1_io_l1clk; // @[beh_lib.scala 352:21]
|
||||
wire rvclkhdr_1_io_clk; // @[beh_lib.scala 352:21]
|
||||
wire rvclkhdr_1_io_en; // @[beh_lib.scala 352:21]
|
||||
wire rvclkhdr_1_io_scan_mode; // @[beh_lib.scala 352:21]
|
||||
wire rvclkhdr_io_l1clk; // @[el2_lib.scala 508:23]
|
||||
wire rvclkhdr_io_clk; // @[el2_lib.scala 508:23]
|
||||
wire rvclkhdr_io_en; // @[el2_lib.scala 508:23]
|
||||
wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 508:23]
|
||||
wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 508:23]
|
||||
wire rvclkhdr_1_io_clk; // @[el2_lib.scala 508:23]
|
||||
wire rvclkhdr_1_io_en; // @[el2_lib.scala 508:23]
|
||||
wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 508:23]
|
||||
wire [63:0] picm_rd_data_m = {io_picm_rd_data,io_picm_rd_data}; // @[Cat.scala 29:58]
|
||||
wire [63:0] dccm_rdata_corr_m = {io_sec_data_hi_m,io_sec_data_lo_m}; // @[Cat.scala 29:58]
|
||||
wire [63:0] dccm_rdata_m = {io_dccm_rdata_hi_m,io_dccm_rdata_lo_m}; // @[Cat.scala 29:58]
|
||||
wire _T = io_lsu_pkt_m_valid & io_lsu_pkt_m_load; // @[el2_lsu_dccm_ctl.scala 161:50]
|
||||
wire _T = io_lsu_pkt_m_valid & io_lsu_pkt_m_bits_load; // @[el2_lsu_dccm_ctl.scala 161:50]
|
||||
reg [63:0] _T_2; // @[el2_lsu_dccm_ctl.scala 171:65]
|
||||
wire [7:0] _T_3 = {io_stbuf_fwdbyteen_hi_m,io_stbuf_fwdbyteen_lo_m}; // @[Cat.scala 29:58]
|
||||
wire [63:0] _T_6 = {io_stbuf_fwddata_hi_m,io_stbuf_fwddata_lo_m}; // @[Cat.scala 29:58]
|
||||
|
|
@ -506,58 +506,58 @@ module el2_lsu_dccm_ctl(
|
|||
wire _T_772 = io_end_addr_d[15:2] == io_lsu_addr_r[15:2]; // @[el2_lsu_dccm_ctl.scala 179:133]
|
||||
wire _T_773 = _T_769 | _T_772; // @[el2_lsu_dccm_ctl.scala 179:101]
|
||||
wire _T_774 = _T_773 & io_lsu_pkt_d_valid; // @[el2_lsu_dccm_ctl.scala 179:175]
|
||||
wire _T_775 = _T_774 & io_lsu_pkt_d_store; // @[el2_lsu_dccm_ctl.scala 179:196]
|
||||
wire _T_776 = _T_775 & io_lsu_pkt_d_dma; // @[el2_lsu_dccm_ctl.scala 179:217]
|
||||
wire _T_777 = _T_776 & io_addr_in_dccm_d; // @[el2_lsu_dccm_ctl.scala 179:236]
|
||||
wire _T_775 = _T_774 & io_lsu_pkt_d_bits_store; // @[el2_lsu_dccm_ctl.scala 179:196]
|
||||
wire _T_776 = _T_775 & io_lsu_pkt_d_bits_dma; // @[el2_lsu_dccm_ctl.scala 179:222]
|
||||
wire _T_777 = _T_776 & io_addr_in_dccm_d; // @[el2_lsu_dccm_ctl.scala 179:246]
|
||||
wire _T_780 = io_lsu_addr_m[15:2] == io_lsu_addr_r[15:2]; // @[el2_lsu_dccm_ctl.scala 180:37]
|
||||
wire _T_783 = io_end_addr_m[15:2] == io_lsu_addr_r[15:2]; // @[el2_lsu_dccm_ctl.scala 180:110]
|
||||
wire _T_784 = _T_780 | _T_783; // @[el2_lsu_dccm_ctl.scala 180:78]
|
||||
wire _T_785 = _T_784 & io_lsu_pkt_m_valid; // @[el2_lsu_dccm_ctl.scala 180:152]
|
||||
wire _T_786 = _T_785 & io_lsu_pkt_m_store; // @[el2_lsu_dccm_ctl.scala 180:173]
|
||||
wire _T_787 = _T_786 & io_lsu_pkt_m_dma; // @[el2_lsu_dccm_ctl.scala 180:194]
|
||||
wire _T_788 = _T_787 & io_addr_in_dccm_m; // @[el2_lsu_dccm_ctl.scala 180:213]
|
||||
wire kill_ecc_corr_lo_r = _T_777 | _T_788; // @[el2_lsu_dccm_ctl.scala 179:257]
|
||||
wire _T_786 = _T_785 & io_lsu_pkt_m_bits_store; // @[el2_lsu_dccm_ctl.scala 180:173]
|
||||
wire _T_787 = _T_786 & io_lsu_pkt_m_bits_dma; // @[el2_lsu_dccm_ctl.scala 180:199]
|
||||
wire _T_788 = _T_787 & io_addr_in_dccm_m; // @[el2_lsu_dccm_ctl.scala 180:223]
|
||||
wire kill_ecc_corr_lo_r = _T_777 | _T_788; // @[el2_lsu_dccm_ctl.scala 179:267]
|
||||
wire _T_791 = io_lsu_addr_d[15:2] == io_end_addr_r[15:2]; // @[el2_lsu_dccm_ctl.scala 182:60]
|
||||
wire _T_794 = io_end_addr_d[15:2] == io_end_addr_r[15:2]; // @[el2_lsu_dccm_ctl.scala 182:133]
|
||||
wire _T_795 = _T_791 | _T_794; // @[el2_lsu_dccm_ctl.scala 182:101]
|
||||
wire _T_796 = _T_795 & io_lsu_pkt_d_valid; // @[el2_lsu_dccm_ctl.scala 182:175]
|
||||
wire _T_797 = _T_796 & io_lsu_pkt_d_store; // @[el2_lsu_dccm_ctl.scala 182:196]
|
||||
wire _T_798 = _T_797 & io_lsu_pkt_d_dma; // @[el2_lsu_dccm_ctl.scala 182:217]
|
||||
wire _T_799 = _T_798 & io_addr_in_dccm_d; // @[el2_lsu_dccm_ctl.scala 182:236]
|
||||
wire _T_797 = _T_796 & io_lsu_pkt_d_bits_store; // @[el2_lsu_dccm_ctl.scala 182:196]
|
||||
wire _T_798 = _T_797 & io_lsu_pkt_d_bits_dma; // @[el2_lsu_dccm_ctl.scala 182:222]
|
||||
wire _T_799 = _T_798 & io_addr_in_dccm_d; // @[el2_lsu_dccm_ctl.scala 182:246]
|
||||
wire _T_802 = io_lsu_addr_m[15:2] == io_end_addr_r[15:2]; // @[el2_lsu_dccm_ctl.scala 183:37]
|
||||
wire _T_805 = io_end_addr_m[15:2] == io_end_addr_r[15:2]; // @[el2_lsu_dccm_ctl.scala 183:110]
|
||||
wire _T_806 = _T_802 | _T_805; // @[el2_lsu_dccm_ctl.scala 183:78]
|
||||
wire _T_807 = _T_806 & io_lsu_pkt_m_valid; // @[el2_lsu_dccm_ctl.scala 183:152]
|
||||
wire _T_808 = _T_807 & io_lsu_pkt_m_store; // @[el2_lsu_dccm_ctl.scala 183:173]
|
||||
wire _T_809 = _T_808 & io_lsu_pkt_m_dma; // @[el2_lsu_dccm_ctl.scala 183:194]
|
||||
wire _T_810 = _T_809 & io_addr_in_dccm_m; // @[el2_lsu_dccm_ctl.scala 183:213]
|
||||
wire kill_ecc_corr_hi_r = _T_799 | _T_810; // @[el2_lsu_dccm_ctl.scala 182:257]
|
||||
wire _T_811 = io_lsu_pkt_r_load & io_single_ecc_error_lo_r; // @[el2_lsu_dccm_ctl.scala 185:55]
|
||||
wire _T_812 = ~io_lsu_raw_fwd_lo_r; // @[el2_lsu_dccm_ctl.scala 185:84]
|
||||
wire ld_single_ecc_error_lo_r = _T_811 & _T_812; // @[el2_lsu_dccm_ctl.scala 185:82]
|
||||
wire _T_813 = io_lsu_pkt_r_load & io_single_ecc_error_hi_r; // @[el2_lsu_dccm_ctl.scala 186:55]
|
||||
wire _T_814 = ~io_lsu_raw_fwd_hi_r; // @[el2_lsu_dccm_ctl.scala 186:84]
|
||||
wire ld_single_ecc_error_hi_r = _T_813 & _T_814; // @[el2_lsu_dccm_ctl.scala 186:82]
|
||||
wire _T_808 = _T_807 & io_lsu_pkt_m_bits_store; // @[el2_lsu_dccm_ctl.scala 183:173]
|
||||
wire _T_809 = _T_808 & io_lsu_pkt_m_bits_dma; // @[el2_lsu_dccm_ctl.scala 183:199]
|
||||
wire _T_810 = _T_809 & io_addr_in_dccm_m; // @[el2_lsu_dccm_ctl.scala 183:223]
|
||||
wire kill_ecc_corr_hi_r = _T_799 | _T_810; // @[el2_lsu_dccm_ctl.scala 182:267]
|
||||
wire _T_811 = io_lsu_pkt_r_bits_load & io_single_ecc_error_lo_r; // @[el2_lsu_dccm_ctl.scala 185:60]
|
||||
wire _T_812 = ~io_lsu_raw_fwd_lo_r; // @[el2_lsu_dccm_ctl.scala 185:89]
|
||||
wire ld_single_ecc_error_lo_r = _T_811 & _T_812; // @[el2_lsu_dccm_ctl.scala 185:87]
|
||||
wire _T_813 = io_lsu_pkt_r_bits_load & io_single_ecc_error_hi_r; // @[el2_lsu_dccm_ctl.scala 186:60]
|
||||
wire _T_814 = ~io_lsu_raw_fwd_hi_r; // @[el2_lsu_dccm_ctl.scala 186:89]
|
||||
wire ld_single_ecc_error_hi_r = _T_813 & _T_814; // @[el2_lsu_dccm_ctl.scala 186:87]
|
||||
wire _T_815 = ld_single_ecc_error_lo_r | ld_single_ecc_error_hi_r; // @[el2_lsu_dccm_ctl.scala 187:63]
|
||||
wire _T_816 = ~io_lsu_double_ecc_error_r; // @[el2_lsu_dccm_ctl.scala 187:93]
|
||||
wire _T_818 = io_lsu_commit_r | io_lsu_pkt_r_dma; // @[el2_lsu_dccm_ctl.scala 188:81]
|
||||
wire _T_818 = io_lsu_commit_r | io_lsu_pkt_r_bits_dma; // @[el2_lsu_dccm_ctl.scala 188:81]
|
||||
wire _T_819 = ld_single_ecc_error_lo_r & _T_818; // @[el2_lsu_dccm_ctl.scala 188:62]
|
||||
wire _T_820 = ~kill_ecc_corr_lo_r; // @[el2_lsu_dccm_ctl.scala 188:103]
|
||||
wire _T_820 = ~kill_ecc_corr_lo_r; // @[el2_lsu_dccm_ctl.scala 188:108]
|
||||
wire _T_822 = ld_single_ecc_error_hi_r & _T_818; // @[el2_lsu_dccm_ctl.scala 189:62]
|
||||
wire _T_823 = ~kill_ecc_corr_hi_r; // @[el2_lsu_dccm_ctl.scala 189:103]
|
||||
wire _T_823 = ~kill_ecc_corr_hi_r; // @[el2_lsu_dccm_ctl.scala 189:108]
|
||||
reg lsu_double_ecc_error_r_ff; // @[el2_lsu_dccm_ctl.scala 191:74]
|
||||
reg ld_single_ecc_error_hi_r_ff; // @[el2_lsu_dccm_ctl.scala 192:74]
|
||||
reg ld_single_ecc_error_lo_r_ff; // @[el2_lsu_dccm_ctl.scala 193:74]
|
||||
reg [15:0] ld_sec_addr_hi_r_ff; // @[beh_lib.scala 358:14]
|
||||
reg [15:0] ld_sec_addr_lo_r_ff; // @[beh_lib.scala 358:14]
|
||||
wire _T_830 = io_lsu_pkt_d_word | io_lsu_pkt_d_dword; // @[el2_lsu_dccm_ctl.scala 197:110]
|
||||
wire _T_831 = ~_T_830; // @[el2_lsu_dccm_ctl.scala 197:90]
|
||||
wire _T_833 = io_lsu_addr_d[1:0] != 2'h0; // @[el2_lsu_dccm_ctl.scala 197:154]
|
||||
wire _T_834 = _T_831 | _T_833; // @[el2_lsu_dccm_ctl.scala 197:132]
|
||||
wire _T_835 = io_lsu_pkt_d_store & _T_834; // @[el2_lsu_dccm_ctl.scala 197:87]
|
||||
wire _T_836 = io_lsu_pkt_d_load | _T_835; // @[el2_lsu_dccm_ctl.scala 197:65]
|
||||
reg [15:0] ld_sec_addr_hi_r_ff; // @[el2_lib.scala 514:16]
|
||||
reg [15:0] ld_sec_addr_lo_r_ff; // @[el2_lib.scala 514:16]
|
||||
wire _T_830 = io_lsu_pkt_d_bits_word | io_lsu_pkt_d_bits_dword; // @[el2_lsu_dccm_ctl.scala 197:125]
|
||||
wire _T_831 = ~_T_830; // @[el2_lsu_dccm_ctl.scala 197:100]
|
||||
wire _T_833 = io_lsu_addr_d[1:0] != 2'h0; // @[el2_lsu_dccm_ctl.scala 197:174]
|
||||
wire _T_834 = _T_831 | _T_833; // @[el2_lsu_dccm_ctl.scala 197:152]
|
||||
wire _T_835 = io_lsu_pkt_d_bits_store & _T_834; // @[el2_lsu_dccm_ctl.scala 197:97]
|
||||
wire _T_836 = io_lsu_pkt_d_bits_load | _T_835; // @[el2_lsu_dccm_ctl.scala 197:70]
|
||||
wire _T_837 = io_lsu_pkt_d_valid & _T_836; // @[el2_lsu_dccm_ctl.scala 197:44]
|
||||
wire lsu_dccm_rden_d = _T_837 & io_addr_in_dccm_d; // @[el2_lsu_dccm_ctl.scala 197:171]
|
||||
wire lsu_dccm_rden_d = _T_837 & io_addr_in_dccm_d; // @[el2_lsu_dccm_ctl.scala 197:191]
|
||||
wire _T_838 = ld_single_ecc_error_lo_r_ff | ld_single_ecc_error_hi_r_ff; // @[el2_lsu_dccm_ctl.scala 200:63]
|
||||
wire _T_839 = ~lsu_double_ecc_error_r_ff; // @[el2_lsu_dccm_ctl.scala 200:96]
|
||||
wire _T_841 = lsu_dccm_rden_d | io_dma_dccm_wen; // @[el2_lsu_dccm_ctl.scala 201:75]
|
||||
|
|
@ -574,52 +574,52 @@ module el2_lsu_dccm_ctl(
|
|||
wire [15:0] _T_866 = io_dma_dccm_wen ? io_lsu_addr_d[15:0] : io_stbuf_addr_any; // @[el2_lsu_dccm_ctl.scala 212:8]
|
||||
wire [15:0] _T_872 = ld_single_ecc_error_hi_r_ff ? ld_sec_addr_hi_r_ff : ld_sec_addr_lo_r_ff; // @[el2_lsu_dccm_ctl.scala 215:8]
|
||||
wire [15:0] _T_876 = io_dma_dccm_wen ? io_end_addr_d : io_stbuf_addr_any; // @[el2_lsu_dccm_ctl.scala 216:8]
|
||||
wire _T_881 = ~ld_single_ecc_error_lo_r_ff; // @[el2_lsu_dccm_ctl.scala 222:36]
|
||||
wire [38:0] _T_884 = {io_sec_data_ecc_lo_r_ff,io_sec_data_lo_r_ff}; // @[Cat.scala 29:58]
|
||||
wire [38:0] _T_887 = {io_sec_data_ecc_hi_r_ff,io_sec_data_hi_r_ff}; // @[Cat.scala 29:58]
|
||||
wire [38:0] _T_888 = _T_881 ? _T_884 : _T_887; // @[el2_lsu_dccm_ctl.scala 222:8]
|
||||
wire [38:0] _T_888 = ld_single_ecc_error_lo_r_ff ? _T_884 : _T_887; // @[el2_lsu_dccm_ctl.scala 222:8]
|
||||
wire [38:0] _T_892 = {io_dma_dccm_wdata_ecc_lo,io_dma_dccm_wdata_lo}; // @[Cat.scala 29:58]
|
||||
wire [38:0] _T_895 = {io_stbuf_ecc_any,io_stbuf_data_any}; // @[Cat.scala 29:58]
|
||||
wire [38:0] _T_896 = io_dma_dccm_wen ? _T_892 : _T_895; // @[el2_lsu_dccm_ctl.scala 224:8]
|
||||
wire _T_899 = ~ld_single_ecc_error_hi_r_ff; // @[el2_lsu_dccm_ctl.scala 228:36]
|
||||
wire [38:0] _T_906 = _T_899 ? _T_887 : _T_884; // @[el2_lsu_dccm_ctl.scala 228:8]
|
||||
wire [38:0] _T_906 = ld_single_ecc_error_hi_r_ff ? _T_887 : _T_884; // @[el2_lsu_dccm_ctl.scala 228:8]
|
||||
wire [38:0] _T_910 = {io_dma_dccm_wdata_ecc_hi,io_dma_dccm_wdata_hi}; // @[Cat.scala 29:58]
|
||||
wire [38:0] _T_914 = io_dma_dccm_wen ? _T_910 : _T_895; // @[el2_lsu_dccm_ctl.scala 230:8]
|
||||
wire [3:0] _T_917 = io_lsu_pkt_m_store ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
||||
wire [3:0] _T_919 = io_lsu_pkt_m_by ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
||||
wire [3:0] _T_920 = _T_919 & 4'h1; // @[el2_lsu_dccm_ctl.scala 234:84]
|
||||
wire [3:0] _T_922 = io_lsu_pkt_m_half ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
||||
wire [3:0] _T_923 = _T_922 & 4'h3; // @[el2_lsu_dccm_ctl.scala 235:33]
|
||||
wire [3:0] _T_924 = _T_920 | _T_923; // @[el2_lsu_dccm_ctl.scala 234:97]
|
||||
wire [3:0] _T_926 = io_lsu_pkt_m_word ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
||||
wire [3:0] _T_928 = _T_924 | _T_926; // @[el2_lsu_dccm_ctl.scala 235:46]
|
||||
wire [3:0] store_byteen_m = _T_917 & _T_928; // @[el2_lsu_dccm_ctl.scala 234:53]
|
||||
wire [3:0] _T_930 = io_lsu_pkt_r_store ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
||||
wire [3:0] _T_932 = io_lsu_pkt_r_by ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
||||
wire [3:0] _T_933 = _T_932 & 4'h1; // @[el2_lsu_dccm_ctl.scala 238:84]
|
||||
wire [3:0] _T_935 = io_lsu_pkt_r_half ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
||||
wire [3:0] _T_936 = _T_935 & 4'h3; // @[el2_lsu_dccm_ctl.scala 239:33]
|
||||
wire [3:0] _T_937 = _T_933 | _T_936; // @[el2_lsu_dccm_ctl.scala 238:97]
|
||||
wire [3:0] _T_939 = io_lsu_pkt_r_word ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
||||
wire [3:0] _T_941 = _T_937 | _T_939; // @[el2_lsu_dccm_ctl.scala 239:46]
|
||||
wire [3:0] store_byteen_r = _T_930 & _T_941; // @[el2_lsu_dccm_ctl.scala 238:53]
|
||||
wire [6:0] _GEN_44 = {{3'd0}, store_byteen_m}; // @[el2_lsu_dccm_ctl.scala 242:49]
|
||||
wire [6:0] _T_944 = _GEN_44 << io_lsu_addr_m[1:0]; // @[el2_lsu_dccm_ctl.scala 242:49]
|
||||
wire [6:0] _GEN_45 = {{3'd0}, store_byteen_r}; // @[el2_lsu_dccm_ctl.scala 244:49]
|
||||
wire [6:0] _T_947 = _GEN_45 << io_lsu_addr_r[1:0]; // @[el2_lsu_dccm_ctl.scala 244:49]
|
||||
wire [3:0] _T_917 = io_lsu_pkt_m_bits_store ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
||||
wire [3:0] _T_919 = io_lsu_pkt_m_bits_by ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
||||
wire [3:0] _T_920 = _T_919 & 4'h1; // @[el2_lsu_dccm_ctl.scala 234:94]
|
||||
wire [3:0] _T_922 = io_lsu_pkt_m_bits_half ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
||||
wire [3:0] _T_923 = _T_922 & 4'h3; // @[el2_lsu_dccm_ctl.scala 235:38]
|
||||
wire [3:0] _T_924 = _T_920 | _T_923; // @[el2_lsu_dccm_ctl.scala 234:107]
|
||||
wire [3:0] _T_926 = io_lsu_pkt_m_bits_word ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
||||
wire [3:0] _T_928 = _T_924 | _T_926; // @[el2_lsu_dccm_ctl.scala 235:51]
|
||||
wire [3:0] store_byteen_m = _T_917 & _T_928; // @[el2_lsu_dccm_ctl.scala 234:58]
|
||||
wire [3:0] _T_930 = io_lsu_pkt_r_bits_store ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
||||
wire [3:0] _T_932 = io_lsu_pkt_r_bits_by ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
||||
wire [3:0] _T_933 = _T_932 & 4'h1; // @[el2_lsu_dccm_ctl.scala 238:94]
|
||||
wire [3:0] _T_935 = io_lsu_pkt_r_bits_half ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
||||
wire [3:0] _T_936 = _T_935 & 4'h3; // @[el2_lsu_dccm_ctl.scala 239:38]
|
||||
wire [3:0] _T_937 = _T_933 | _T_936; // @[el2_lsu_dccm_ctl.scala 238:107]
|
||||
wire [3:0] _T_939 = io_lsu_pkt_r_bits_word ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
|
||||
wire [3:0] _T_941 = _T_937 | _T_939; // @[el2_lsu_dccm_ctl.scala 239:51]
|
||||
wire [3:0] store_byteen_r = _T_930 & _T_941; // @[el2_lsu_dccm_ctl.scala 238:58]
|
||||
wire [6:0] _GEN_44 = {{3'd0}, store_byteen_m}; // @[el2_lsu_dccm_ctl.scala 242:45]
|
||||
wire [6:0] _T_944 = _GEN_44 << io_lsu_addr_m[1:0]; // @[el2_lsu_dccm_ctl.scala 242:45]
|
||||
wire [6:0] _GEN_45 = {{3'd0}, store_byteen_r}; // @[el2_lsu_dccm_ctl.scala 244:45]
|
||||
wire [6:0] _T_947 = _GEN_45 << io_lsu_addr_r[1:0]; // @[el2_lsu_dccm_ctl.scala 244:45]
|
||||
wire _T_950 = io_stbuf_addr_any[15:2] == io_lsu_addr_m[15:2]; // @[el2_lsu_dccm_ctl.scala 247:67]
|
||||
wire dccm_wr_bypass_d_m_lo = _T_950 & io_addr_in_dccm_m; // @[el2_lsu_dccm_ctl.scala 247:101]
|
||||
wire _T_953 = io_stbuf_addr_any[15:2] == io_end_addr_m[15:2]; // @[el2_lsu_dccm_ctl.scala 248:67]
|
||||
wire dccm_wr_bypass_d_m_hi = _T_953 & io_addr_in_dccm_m; // @[el2_lsu_dccm_ctl.scala 248:101]
|
||||
wire _T_956 = io_stbuf_addr_any[15:2] == io_lsu_addr_r[15:2]; // @[el2_lsu_dccm_ctl.scala 250:67]
|
||||
wire dccm_wr_bypass_d_r_lo = _T_956 & io_addr_in_dccm_r; // @[el2_lsu_dccm_ctl.scala 250:101]
|
||||
wire _T_959 = io_stbuf_addr_any[15:2] == io_end_addr_r[15:2]; // @[el2_lsu_dccm_ctl.scala 251:67]
|
||||
wire dccm_wr_bypass_d_r_hi = _T_959 & io_addr_in_dccm_r; // @[el2_lsu_dccm_ctl.scala 251:101]
|
||||
wire [63:0] _T_962 = {32'h0,io_store_data_m}; // @[Cat.scala 29:58]
|
||||
wire [126:0] _GEN_47 = {{63'd0}, _T_962}; // @[el2_lsu_dccm_ctl.scala 280:72]
|
||||
wire [126:0] _T_965 = _GEN_47 << _T_762; // @[el2_lsu_dccm_ctl.scala 280:72]
|
||||
wire [63:0] store_data_pre_m = _T_965[63:0]; // @[el2_lsu_dccm_ctl.scala 280:29]
|
||||
wire [31:0] store_data_hi_m = store_data_pre_m[63:32]; // @[el2_lsu_dccm_ctl.scala 281:48]
|
||||
wire [31:0] store_data_lo_m = store_data_pre_m[31:0]; // @[el2_lsu_dccm_ctl.scala 282:48]
|
||||
wire [7:0] store_byteen_ext_m = {{1'd0}, _T_944}; // @[el2_lsu_dccm_ctl.scala 242:26]
|
||||
wire [7:0] store_byteen_ext_m = {{1'd0}, _T_944}; // @[el2_lsu_dccm_ctl.scala 242:22]
|
||||
wire _T_971 = io_lsu_stbuf_commit_any & dccm_wr_bypass_d_m_lo; // @[el2_lsu_dccm_ctl.scala 283:211]
|
||||
wire [7:0] _T_975 = _T_971 ? io_stbuf_data_any[7:0] : io_sec_data_lo_m[7:0]; // @[el2_lsu_dccm_ctl.scala 283:185]
|
||||
wire [7:0] _T_976 = store_byteen_ext_m[0] ? store_data_lo_m[7:0] : _T_975; // @[el2_lsu_dccm_ctl.scala 283:120]
|
||||
|
|
@ -801,7 +801,7 @@ module el2_lsu_dccm_ctl(
|
|||
wire [31:0] _T_1377 = _T_1375 & 32'haaaaaaaa; // @[Bitwise.scala 103:75]
|
||||
reg [31:0] _T_1379; // @[el2_lsu_dccm_ctl.scala 284:72]
|
||||
wire _T_1380 = io_lsu_stbuf_commit_any & dccm_wr_bypass_d_r_lo; // @[el2_lsu_dccm_ctl.scala 285:105]
|
||||
wire [7:0] store_byteen_ext_r = {{1'd0}, _T_947}; // @[el2_lsu_dccm_ctl.scala 244:26]
|
||||
wire [7:0] store_byteen_ext_r = {{1'd0}, _T_947}; // @[el2_lsu_dccm_ctl.scala 244:22]
|
||||
wire _T_1382 = ~store_byteen_ext_r[0]; // @[el2_lsu_dccm_ctl.scala 285:131]
|
||||
wire _T_1383 = _T_1380 & _T_1382; // @[el2_lsu_dccm_ctl.scala 285:129]
|
||||
wire [7:0] _T_1387 = _T_1383 ? io_stbuf_data_any[7:0] : io_store_data_lo_r[7:0]; // @[el2_lsu_dccm_ctl.scala 285:79]
|
||||
|
|
@ -894,7 +894,10 @@ module el2_lsu_dccm_ctl(
|
|||
wire [31:0] _T_1575 = _GEN_83 & 32'h55555555; // @[Bitwise.scala 103:31]
|
||||
wire [31:0] _T_1577 = {_T_1570[30:0], 1'h0}; // @[Bitwise.scala 103:65]
|
||||
wire [31:0] _T_1579 = _T_1577 & 32'haaaaaaaa; // @[Bitwise.scala 103:75]
|
||||
wire [7:0] _T_1588 = _T_1383 ? io_stbuf_data_any[7:0] : io_store_data_hi_r[7:0]; // @[el2_lsu_dccm_ctl.scala 286:79]
|
||||
wire _T_1581 = io_lsu_stbuf_commit_any & dccm_wr_bypass_d_r_hi; // @[el2_lsu_dccm_ctl.scala 286:105]
|
||||
wire _T_1583 = ~store_byteen_ext_r[4]; // @[el2_lsu_dccm_ctl.scala 286:131]
|
||||
wire _T_1584 = _T_1581 & _T_1583; // @[el2_lsu_dccm_ctl.scala 286:129]
|
||||
wire [7:0] _T_1588 = _T_1584 ? io_stbuf_data_any[7:0] : io_store_data_hi_r[7:0]; // @[el2_lsu_dccm_ctl.scala 286:79]
|
||||
wire [7:0] _T_1592 = {{4'd0}, _T_1588[7:4]}; // @[Bitwise.scala 103:31]
|
||||
wire [7:0] _T_1594 = {_T_1588[3:0], 4'h0}; // @[Bitwise.scala 103:65]
|
||||
wire [7:0] _T_1596 = _T_1594 & 8'hf0; // @[Bitwise.scala 103:75]
|
||||
|
|
@ -909,7 +912,9 @@ module el2_lsu_dccm_ctl(
|
|||
wire [7:0] _T_1614 = {_T_1607[6:0], 1'h0}; // @[Bitwise.scala 103:65]
|
||||
wire [7:0] _T_1616 = _T_1614 & 8'haa; // @[Bitwise.scala 103:75]
|
||||
wire [7:0] _T_1617 = _T_1612 | _T_1616; // @[Bitwise.scala 103:39]
|
||||
wire [7:0] _T_1625 = _T_1420 ? io_stbuf_data_any[15:8] : io_store_data_hi_r[15:8]; // @[el2_lsu_dccm_ctl.scala 286:79]
|
||||
wire _T_1620 = ~store_byteen_ext_r[5]; // @[el2_lsu_dccm_ctl.scala 286:131]
|
||||
wire _T_1621 = _T_1581 & _T_1620; // @[el2_lsu_dccm_ctl.scala 286:129]
|
||||
wire [7:0] _T_1625 = _T_1621 ? io_stbuf_data_any[15:8] : io_store_data_hi_r[15:8]; // @[el2_lsu_dccm_ctl.scala 286:79]
|
||||
wire [7:0] _T_1629 = {{4'd0}, _T_1625[7:4]}; // @[Bitwise.scala 103:31]
|
||||
wire [7:0] _T_1631 = {_T_1625[3:0], 4'h0}; // @[Bitwise.scala 103:65]
|
||||
wire [7:0] _T_1633 = _T_1631 & 8'hf0; // @[Bitwise.scala 103:75]
|
||||
|
|
@ -924,7 +929,9 @@ module el2_lsu_dccm_ctl(
|
|||
wire [7:0] _T_1651 = {_T_1644[6:0], 1'h0}; // @[Bitwise.scala 103:65]
|
||||
wire [7:0] _T_1653 = _T_1651 & 8'haa; // @[Bitwise.scala 103:75]
|
||||
wire [7:0] _T_1654 = _T_1649 | _T_1653; // @[Bitwise.scala 103:39]
|
||||
wire [7:0] _T_1662 = _T_1457 ? io_stbuf_data_any[23:16] : io_store_data_hi_r[23:16]; // @[el2_lsu_dccm_ctl.scala 286:79]
|
||||
wire _T_1657 = ~store_byteen_ext_r[6]; // @[el2_lsu_dccm_ctl.scala 286:131]
|
||||
wire _T_1658 = _T_1581 & _T_1657; // @[el2_lsu_dccm_ctl.scala 286:129]
|
||||
wire [7:0] _T_1662 = _T_1658 ? io_stbuf_data_any[23:16] : io_store_data_hi_r[23:16]; // @[el2_lsu_dccm_ctl.scala 286:79]
|
||||
wire [7:0] _T_1666 = {{4'd0}, _T_1662[7:4]}; // @[Bitwise.scala 103:31]
|
||||
wire [7:0] _T_1668 = {_T_1662[3:0], 4'h0}; // @[Bitwise.scala 103:65]
|
||||
wire [7:0] _T_1670 = _T_1668 & 8'hf0; // @[Bitwise.scala 103:75]
|
||||
|
|
@ -939,7 +946,9 @@ module el2_lsu_dccm_ctl(
|
|||
wire [7:0] _T_1688 = {_T_1681[6:0], 1'h0}; // @[Bitwise.scala 103:65]
|
||||
wire [7:0] _T_1690 = _T_1688 & 8'haa; // @[Bitwise.scala 103:75]
|
||||
wire [7:0] _T_1691 = _T_1686 | _T_1690; // @[Bitwise.scala 103:39]
|
||||
wire [7:0] _T_1699 = _T_1494 ? io_stbuf_data_any[31:24] : io_store_data_hi_r[31:24]; // @[el2_lsu_dccm_ctl.scala 286:79]
|
||||
wire _T_1694 = ~store_byteen_ext_r[7]; // @[el2_lsu_dccm_ctl.scala 286:131]
|
||||
wire _T_1695 = _T_1581 & _T_1694; // @[el2_lsu_dccm_ctl.scala 286:129]
|
||||
wire [7:0] _T_1699 = _T_1695 ? io_stbuf_data_any[31:24] : io_store_data_hi_r[31:24]; // @[el2_lsu_dccm_ctl.scala 286:79]
|
||||
wire [7:0] _T_1703 = {{4'd0}, _T_1699[7:4]}; // @[Bitwise.scala 103:31]
|
||||
wire [7:0] _T_1705 = {_T_1699[3:0], 4'h0}; // @[Bitwise.scala 103:65]
|
||||
wire [7:0] _T_1707 = _T_1705 & 8'hf0; // @[Bitwise.scala 103:75]
|
||||
|
|
@ -1013,23 +1022,23 @@ module el2_lsu_dccm_ctl(
|
|||
wire [31:0] _T_1852 = _T_1847 | _T_1851; // @[Bitwise.scala 103:39]
|
||||
wire [63:0] _GEN_101 = {{32'd0}, _T_1852}; // @[el2_lsu_dccm_ctl.scala 287:115]
|
||||
wire [63:0] _T_1853 = _T_1787 & _GEN_101; // @[el2_lsu_dccm_ctl.scala 287:115]
|
||||
wire _T_1858 = io_lsu_pkt_r_valid & io_lsu_pkt_r_store; // @[el2_lsu_dccm_ctl.scala 294:50]
|
||||
wire _T_1859 = _T_1858 & io_addr_in_pic_r; // @[el2_lsu_dccm_ctl.scala 294:71]
|
||||
wire _T_1860 = _T_1859 & io_lsu_commit_r; // @[el2_lsu_dccm_ctl.scala 294:90]
|
||||
wire _T_1862 = io_lsu_pkt_d_valid & io_lsu_pkt_d_load; // @[el2_lsu_dccm_ctl.scala 295:50]
|
||||
wire _T_1864 = io_lsu_pkt_d_valid & io_lsu_pkt_d_store; // @[el2_lsu_dccm_ctl.scala 296:50]
|
||||
wire _T_1858 = io_lsu_pkt_r_valid & io_lsu_pkt_r_bits_store; // @[el2_lsu_dccm_ctl.scala 294:50]
|
||||
wire _T_1859 = _T_1858 & io_addr_in_pic_r; // @[el2_lsu_dccm_ctl.scala 294:76]
|
||||
wire _T_1860 = _T_1859 & io_lsu_commit_r; // @[el2_lsu_dccm_ctl.scala 294:95]
|
||||
wire _T_1862 = io_lsu_pkt_d_valid & io_lsu_pkt_d_bits_load; // @[el2_lsu_dccm_ctl.scala 295:50]
|
||||
wire _T_1864 = io_lsu_pkt_d_valid & io_lsu_pkt_d_bits_store; // @[el2_lsu_dccm_ctl.scala 296:50]
|
||||
wire [31:0] _T_1868 = {17'h0,io_lsu_addr_d[14:0]}; // @[Cat.scala 29:58]
|
||||
wire [14:0] _T_1874 = io_dma_pic_wen ? io_dma_mem_addr[14:0] : io_lsu_addr_r[14:0]; // @[el2_lsu_dccm_ctl.scala 298:75]
|
||||
wire [14:0] _T_1874 = io_dma_pic_wen ? io_dma_mem_addr[14:0] : io_lsu_addr_r[14:0]; // @[el2_lsu_dccm_ctl.scala 298:85]
|
||||
wire [31:0] _T_1875 = {17'h0,_T_1874}; // @[Cat.scala 29:58]
|
||||
reg _T_1882; // @[el2_lsu_dccm_ctl.scala 303:61]
|
||||
reg _T_1883; // @[el2_lsu_dccm_ctl.scala 304:61]
|
||||
rvclkhdr rvclkhdr ( // @[beh_lib.scala 352:21]
|
||||
rvclkhdr rvclkhdr ( // @[el2_lib.scala 508:23]
|
||||
.io_l1clk(rvclkhdr_io_l1clk),
|
||||
.io_clk(rvclkhdr_io_clk),
|
||||
.io_en(rvclkhdr_io_en),
|
||||
.io_scan_mode(rvclkhdr_io_scan_mode)
|
||||
);
|
||||
rvclkhdr rvclkhdr_1 ( // @[beh_lib.scala 352:21]
|
||||
rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 508:23]
|
||||
.io_l1clk(rvclkhdr_1_io_l1clk),
|
||||
.io_clk(rvclkhdr_1_io_clk),
|
||||
.io_en(rvclkhdr_1_io_en),
|
||||
|
|
@ -1057,7 +1066,7 @@ module el2_lsu_dccm_ctl(
|
|||
assign io_lsu_stbuf_commit_any = io_stbuf_reqvld_any & _T_853; // @[el2_lsu_dccm_ctl.scala 201:31]
|
||||
assign io_lsu_dccm_rden_m = _T_1882; // @[el2_lsu_dccm_ctl.scala 303:24]
|
||||
assign io_lsu_dccm_rden_r = _T_1883; // @[el2_lsu_dccm_ctl.scala 304:24]
|
||||
assign io_dccm_dma_rvalid = _T & io_lsu_pkt_m_dma; // @[el2_lsu_dccm_ctl.scala 161:28]
|
||||
assign io_dccm_dma_rvalid = _T & io_lsu_pkt_m_bits_dma; // @[el2_lsu_dccm_ctl.scala 161:28]
|
||||
assign io_dccm_dma_ecc_error = io_lsu_double_ecc_error_m; // @[el2_lsu_dccm_ctl.scala 162:28]
|
||||
assign io_dccm_dma_rtag = io_dma_mem_tag_m; // @[el2_lsu_dccm_ctl.scala 164:28]
|
||||
assign io_dccm_dma_rdata = _T_376 | _T_380; // @[el2_lsu_dccm_ctl.scala 163:28]
|
||||
|
|
@ -1075,12 +1084,12 @@ module el2_lsu_dccm_ctl(
|
|||
assign io_picm_rdaddr = 32'hf00c0000 | _T_1868; // @[el2_lsu_dccm_ctl.scala 297:27]
|
||||
assign io_picm_wraddr = 32'hf00c0000 | _T_1875; // @[el2_lsu_dccm_ctl.scala 298:27]
|
||||
assign io_picm_wr_data = io_dma_pic_wen ? io_dma_mem_wdata[31:0] : io_store_datafn_lo_r; // @[el2_lsu_dccm_ctl.scala 300:27]
|
||||
assign rvclkhdr_io_clk = clock; // @[beh_lib.scala 354:16]
|
||||
assign rvclkhdr_io_en = io_ld_single_ecc_error_r; // @[beh_lib.scala 355:15]
|
||||
assign rvclkhdr_io_scan_mode = io_scan_mode; // @[beh_lib.scala 356:22]
|
||||
assign rvclkhdr_1_io_clk = clock; // @[beh_lib.scala 354:16]
|
||||
assign rvclkhdr_1_io_en = io_ld_single_ecc_error_r; // @[beh_lib.scala 355:15]
|
||||
assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[beh_lib.scala 356:22]
|
||||
assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 510:18]
|
||||
assign rvclkhdr_io_en = io_ld_single_ecc_error_r; // @[el2_lib.scala 511:17]
|
||||
assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
||||
assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 510:18]
|
||||
assign rvclkhdr_1_io_en = io_ld_single_ecc_error_r; // @[el2_lib.scala 511:17]
|
||||
assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24]
|
||||
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
||||
`define RANDOMIZE
|
||||
`endif
|
||||
|
|
|
|||
|
|
@ -5,37 +5,37 @@ circuit el2_lsu_lsc_ctl :
|
|||
input reset : AsyncReset
|
||||
output io : {flip lsu_c2_m_clk : Clock, flip start_addr_d : UInt<32>, flip end_addr_d : UInt<32>, flip lsu_pkt_d : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip dec_tlu_mrac_ff : UInt<32>, flip rs1_region_d : UInt<4>, flip rs1_d : UInt<32>, is_sideeffects_m : UInt<1>, addr_in_dccm_d : UInt<1>, addr_in_pic_d : UInt<1>, addr_external_d : UInt<1>, access_fault_d : UInt<1>, misaligned_fault_d : UInt<1>, exc_mscause_d : UInt<4>, fir_dccm_access_error_d : UInt<1>, fir_nondccm_access_error_d : UInt<1>, flip scan_mode : UInt<1>}
|
||||
|
||||
node _T = bits(io.start_addr_d, 31, 28) @[el2_lib.scala 253:27]
|
||||
node start_addr_in_dccm_region_d = eq(_T, UInt<4>("h0f")) @[el2_lib.scala 253:49]
|
||||
wire start_addr_in_dccm_d : UInt<1> @[el2_lib.scala 254:26]
|
||||
node _T_1 = bits(io.start_addr_d, 31, 16) @[el2_lib.scala 258:24]
|
||||
node _T_2 = eq(_T_1, UInt<16>("h0f004")) @[el2_lib.scala 258:39]
|
||||
start_addr_in_dccm_d <= _T_2 @[el2_lib.scala 258:16]
|
||||
node _T_3 = bits(io.end_addr_d, 31, 28) @[el2_lib.scala 253:27]
|
||||
node end_addr_in_dccm_region_d = eq(_T_3, UInt<4>("h0f")) @[el2_lib.scala 253:49]
|
||||
wire end_addr_in_dccm_d : UInt<1> @[el2_lib.scala 254:26]
|
||||
node _T_4 = bits(io.end_addr_d, 31, 16) @[el2_lib.scala 258:24]
|
||||
node _T_5 = eq(_T_4, UInt<16>("h0f004")) @[el2_lib.scala 258:39]
|
||||
end_addr_in_dccm_d <= _T_5 @[el2_lib.scala 258:16]
|
||||
node _T = bits(io.start_addr_d, 31, 28) @[el2_lib.scala 496:27]
|
||||
node start_addr_in_dccm_region_d = eq(_T, UInt<4>("h0f")) @[el2_lib.scala 496:49]
|
||||
wire start_addr_in_dccm_d : UInt<1> @[el2_lib.scala 497:26]
|
||||
node _T_1 = bits(io.start_addr_d, 31, 16) @[el2_lib.scala 501:24]
|
||||
node _T_2 = eq(_T_1, UInt<16>("h0f004")) @[el2_lib.scala 501:39]
|
||||
start_addr_in_dccm_d <= _T_2 @[el2_lib.scala 501:16]
|
||||
node _T_3 = bits(io.end_addr_d, 31, 28) @[el2_lib.scala 496:27]
|
||||
node end_addr_in_dccm_region_d = eq(_T_3, UInt<4>("h0f")) @[el2_lib.scala 496:49]
|
||||
wire end_addr_in_dccm_d : UInt<1> @[el2_lib.scala 497:26]
|
||||
node _T_4 = bits(io.end_addr_d, 31, 16) @[el2_lib.scala 501:24]
|
||||
node _T_5 = eq(_T_4, UInt<16>("h0f004")) @[el2_lib.scala 501:39]
|
||||
end_addr_in_dccm_d <= _T_5 @[el2_lib.scala 501:16]
|
||||
wire addr_in_iccm : UInt<1>
|
||||
addr_in_iccm <= UInt<1>("h00")
|
||||
node _T_6 = bits(io.start_addr_d, 31, 28) @[el2_lsu_addrcheck.scala 42:37]
|
||||
node _T_7 = eq(_T_6, UInt<4>("h0e")) @[el2_lsu_addrcheck.scala 42:45]
|
||||
addr_in_iccm <= _T_7 @[el2_lsu_addrcheck.scala 42:18]
|
||||
node _T_8 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 50:89]
|
||||
node _T_9 = bits(_T_8, 31, 28) @[el2_lib.scala 253:27]
|
||||
node start_addr_in_pic_region_d = eq(_T_9, UInt<4>("h0f")) @[el2_lib.scala 253:49]
|
||||
wire start_addr_in_pic_d : UInt<1> @[el2_lib.scala 254:26]
|
||||
node _T_10 = bits(_T_8, 31, 15) @[el2_lib.scala 258:24]
|
||||
node _T_11 = eq(_T_10, UInt<17>("h01e018")) @[el2_lib.scala 258:39]
|
||||
start_addr_in_pic_d <= _T_11 @[el2_lib.scala 258:16]
|
||||
node _T_9 = bits(_T_8, 31, 28) @[el2_lib.scala 496:27]
|
||||
node start_addr_in_pic_region_d = eq(_T_9, UInt<4>("h0f")) @[el2_lib.scala 496:49]
|
||||
wire start_addr_in_pic_d : UInt<1> @[el2_lib.scala 497:26]
|
||||
node _T_10 = bits(_T_8, 31, 15) @[el2_lib.scala 501:24]
|
||||
node _T_11 = eq(_T_10, UInt<17>("h01e018")) @[el2_lib.scala 501:39]
|
||||
start_addr_in_pic_d <= _T_11 @[el2_lib.scala 501:16]
|
||||
node _T_12 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 52:83]
|
||||
node _T_13 = bits(_T_12, 31, 28) @[el2_lib.scala 253:27]
|
||||
node end_addr_in_pic_region_d = eq(_T_13, UInt<4>("h0f")) @[el2_lib.scala 253:49]
|
||||
wire end_addr_in_pic_d : UInt<1> @[el2_lib.scala 254:26]
|
||||
node _T_14 = bits(_T_12, 31, 15) @[el2_lib.scala 258:24]
|
||||
node _T_15 = eq(_T_14, UInt<17>("h01e018")) @[el2_lib.scala 258:39]
|
||||
end_addr_in_pic_d <= _T_15 @[el2_lib.scala 258:16]
|
||||
node _T_13 = bits(_T_12, 31, 28) @[el2_lib.scala 496:27]
|
||||
node end_addr_in_pic_region_d = eq(_T_13, UInt<4>("h0f")) @[el2_lib.scala 496:49]
|
||||
wire end_addr_in_pic_d : UInt<1> @[el2_lib.scala 497:26]
|
||||
node _T_14 = bits(_T_12, 31, 15) @[el2_lib.scala 501:24]
|
||||
node _T_15 = eq(_T_14, UInt<17>("h01e018")) @[el2_lib.scala 501:39]
|
||||
end_addr_in_pic_d <= _T_15 @[el2_lib.scala 501:16]
|
||||
node start_addr_dccm_or_pic = or(start_addr_in_dccm_region_d, start_addr_in_pic_region_d) @[el2_lsu_addrcheck.scala 54:60]
|
||||
node _T_16 = bits(io.rs1_region_d, 3, 0) @[el2_lsu_addrcheck.scala 55:48]
|
||||
node _T_17 = eq(_T_16, UInt<4>("h0f")) @[el2_lsu_addrcheck.scala 55:54]
|
||||
|
|
@ -75,104 +75,104 @@ circuit el2_lsu_lsc_ctl :
|
|||
node _T_44 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 29:58]
|
||||
node _T_45 = cat(_T_44, _T_43) @[Cat.scala 29:58]
|
||||
node _T_46 = cat(_T_45, _T_42) @[Cat.scala 29:58]
|
||||
node _T_47 = orr(_T_46) @[el2_lsu_addrcheck.scala 66:87]
|
||||
node _T_47 = orr(_T_46) @[el2_lsu_addrcheck.scala 66:99]
|
||||
node _T_48 = eq(_T_47, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 65:33]
|
||||
node _T_49 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 67:47]
|
||||
node _T_50 = or(_T_49, UInt<32>("h07fffffff")) @[el2_lsu_addrcheck.scala 67:54]
|
||||
node _T_51 = or(UInt<32>("h00"), UInt<32>("h07fffffff")) @[el2_lsu_addrcheck.scala 67:99]
|
||||
node _T_52 = eq(_T_50, _T_51) @[el2_lsu_addrcheck.scala 67:76]
|
||||
node _T_53 = and(UInt<1>("h01"), _T_52) @[el2_lsu_addrcheck.scala 67:28]
|
||||
node _T_54 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 68:47]
|
||||
node _T_55 = or(_T_54, UInt<32>("h03fffffff")) @[el2_lsu_addrcheck.scala 68:54]
|
||||
node _T_56 = or(UInt<32>("h0c0000000"), UInt<32>("h03fffffff")) @[el2_lsu_addrcheck.scala 68:99]
|
||||
node _T_57 = eq(_T_55, _T_56) @[el2_lsu_addrcheck.scala 68:76]
|
||||
node _T_58 = and(UInt<1>("h01"), _T_57) @[el2_lsu_addrcheck.scala 68:28]
|
||||
node _T_59 = or(_T_53, _T_58) @[el2_lsu_addrcheck.scala 67:121]
|
||||
node _T_60 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 69:47]
|
||||
node _T_61 = or(_T_60, UInt<32>("h01fffffff")) @[el2_lsu_addrcheck.scala 69:54]
|
||||
node _T_62 = or(UInt<32>("h0a0000000"), UInt<32>("h01fffffff")) @[el2_lsu_addrcheck.scala 69:99]
|
||||
node _T_63 = eq(_T_61, _T_62) @[el2_lsu_addrcheck.scala 69:76]
|
||||
node _T_64 = and(UInt<1>("h01"), _T_63) @[el2_lsu_addrcheck.scala 69:28]
|
||||
node _T_65 = or(_T_59, _T_64) @[el2_lsu_addrcheck.scala 68:121]
|
||||
node _T_66 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 70:47]
|
||||
node _T_67 = or(_T_66, UInt<32>("h0fffffff")) @[el2_lsu_addrcheck.scala 70:54]
|
||||
node _T_68 = or(UInt<32>("h080000000"), UInt<32>("h0fffffff")) @[el2_lsu_addrcheck.scala 70:99]
|
||||
node _T_69 = eq(_T_67, _T_68) @[el2_lsu_addrcheck.scala 70:76]
|
||||
node _T_70 = and(UInt<1>("h01"), _T_69) @[el2_lsu_addrcheck.scala 70:28]
|
||||
node _T_71 = or(_T_65, _T_70) @[el2_lsu_addrcheck.scala 69:121]
|
||||
node _T_72 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 71:47]
|
||||
node _T_73 = or(_T_72, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 71:54]
|
||||
node _T_74 = or(UInt<32>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 71:99]
|
||||
node _T_75 = eq(_T_73, _T_74) @[el2_lsu_addrcheck.scala 71:76]
|
||||
node _T_76 = and(UInt<1>("h00"), _T_75) @[el2_lsu_addrcheck.scala 71:28]
|
||||
node _T_77 = or(_T_71, _T_76) @[el2_lsu_addrcheck.scala 70:121]
|
||||
node _T_78 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 72:47]
|
||||
node _T_79 = or(_T_78, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 72:54]
|
||||
node _T_80 = or(UInt<32>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 72:99]
|
||||
node _T_81 = eq(_T_79, _T_80) @[el2_lsu_addrcheck.scala 72:76]
|
||||
node _T_82 = and(UInt<1>("h00"), _T_81) @[el2_lsu_addrcheck.scala 72:28]
|
||||
node _T_83 = or(_T_77, _T_82) @[el2_lsu_addrcheck.scala 71:121]
|
||||
node _T_84 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 73:47]
|
||||
node _T_85 = or(_T_84, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 73:54]
|
||||
node _T_86 = or(UInt<32>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 73:99]
|
||||
node _T_87 = eq(_T_85, _T_86) @[el2_lsu_addrcheck.scala 73:76]
|
||||
node _T_88 = and(UInt<1>("h00"), _T_87) @[el2_lsu_addrcheck.scala 73:28]
|
||||
node _T_89 = or(_T_83, _T_88) @[el2_lsu_addrcheck.scala 72:121]
|
||||
node _T_90 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 74:47]
|
||||
node _T_91 = or(_T_90, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 74:54]
|
||||
node _T_92 = or(UInt<32>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 74:99]
|
||||
node _T_93 = eq(_T_91, _T_92) @[el2_lsu_addrcheck.scala 74:76]
|
||||
node _T_94 = and(UInt<1>("h00"), _T_93) @[el2_lsu_addrcheck.scala 74:28]
|
||||
node _T_95 = or(_T_89, _T_94) @[el2_lsu_addrcheck.scala 73:121]
|
||||
node _T_96 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 76:46]
|
||||
node _T_97 = or(_T_96, UInt<32>("h07fffffff")) @[el2_lsu_addrcheck.scala 76:55]
|
||||
node _T_98 = or(UInt<32>("h00"), UInt<32>("h07fffffff")) @[el2_lsu_addrcheck.scala 76:100]
|
||||
node _T_99 = eq(_T_97, _T_98) @[el2_lsu_addrcheck.scala 76:77]
|
||||
node _T_100 = and(UInt<1>("h01"), _T_99) @[el2_lsu_addrcheck.scala 76:29]
|
||||
node _T_101 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 77:47]
|
||||
node _T_102 = or(_T_101, UInt<32>("h03fffffff")) @[el2_lsu_addrcheck.scala 77:56]
|
||||
node _T_103 = or(UInt<32>("h0c0000000"), UInt<32>("h03fffffff")) @[el2_lsu_addrcheck.scala 77:101]
|
||||
node _T_104 = eq(_T_102, _T_103) @[el2_lsu_addrcheck.scala 77:78]
|
||||
node _T_105 = and(UInt<1>("h01"), _T_104) @[el2_lsu_addrcheck.scala 77:30]
|
||||
node _T_106 = or(_T_100, _T_105) @[el2_lsu_addrcheck.scala 76:122]
|
||||
node _T_107 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 78:47]
|
||||
node _T_108 = or(_T_107, UInt<32>("h01fffffff")) @[el2_lsu_addrcheck.scala 78:56]
|
||||
node _T_109 = or(UInt<32>("h0a0000000"), UInt<32>("h01fffffff")) @[el2_lsu_addrcheck.scala 78:101]
|
||||
node _T_110 = eq(_T_108, _T_109) @[el2_lsu_addrcheck.scala 78:78]
|
||||
node _T_111 = and(UInt<1>("h01"), _T_110) @[el2_lsu_addrcheck.scala 78:30]
|
||||
node _T_112 = or(_T_106, _T_111) @[el2_lsu_addrcheck.scala 77:123]
|
||||
node _T_113 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 79:47]
|
||||
node _T_114 = or(_T_113, UInt<32>("h0fffffff")) @[el2_lsu_addrcheck.scala 79:56]
|
||||
node _T_115 = or(UInt<32>("h080000000"), UInt<32>("h0fffffff")) @[el2_lsu_addrcheck.scala 79:101]
|
||||
node _T_116 = eq(_T_114, _T_115) @[el2_lsu_addrcheck.scala 79:78]
|
||||
node _T_117 = and(UInt<1>("h01"), _T_116) @[el2_lsu_addrcheck.scala 79:30]
|
||||
node _T_118 = or(_T_112, _T_117) @[el2_lsu_addrcheck.scala 78:123]
|
||||
node _T_119 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 80:47]
|
||||
node _T_120 = or(_T_119, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 80:56]
|
||||
node _T_121 = or(UInt<32>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 80:101]
|
||||
node _T_122 = eq(_T_120, _T_121) @[el2_lsu_addrcheck.scala 80:78]
|
||||
node _T_123 = and(UInt<1>("h00"), _T_122) @[el2_lsu_addrcheck.scala 80:30]
|
||||
node _T_124 = or(_T_118, _T_123) @[el2_lsu_addrcheck.scala 79:123]
|
||||
node _T_125 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 81:47]
|
||||
node _T_126 = or(_T_125, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 81:56]
|
||||
node _T_127 = or(UInt<32>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 81:101]
|
||||
node _T_128 = eq(_T_126, _T_127) @[el2_lsu_addrcheck.scala 81:78]
|
||||
node _T_129 = and(UInt<1>("h00"), _T_128) @[el2_lsu_addrcheck.scala 81:30]
|
||||
node _T_130 = or(_T_124, _T_129) @[el2_lsu_addrcheck.scala 80:123]
|
||||
node _T_131 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 82:47]
|
||||
node _T_132 = or(_T_131, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 82:56]
|
||||
node _T_133 = or(UInt<32>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 82:101]
|
||||
node _T_134 = eq(_T_132, _T_133) @[el2_lsu_addrcheck.scala 82:78]
|
||||
node _T_135 = and(UInt<1>("h00"), _T_134) @[el2_lsu_addrcheck.scala 82:30]
|
||||
node _T_136 = or(_T_130, _T_135) @[el2_lsu_addrcheck.scala 81:123]
|
||||
node _T_137 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 83:47]
|
||||
node _T_138 = or(_T_137, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 83:56]
|
||||
node _T_139 = or(UInt<32>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 83:101]
|
||||
node _T_140 = eq(_T_138, _T_139) @[el2_lsu_addrcheck.scala 83:78]
|
||||
node _T_141 = and(UInt<1>("h00"), _T_140) @[el2_lsu_addrcheck.scala 83:30]
|
||||
node _T_142 = or(_T_136, _T_141) @[el2_lsu_addrcheck.scala 82:123]
|
||||
node _T_49 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 67:49]
|
||||
node _T_50 = or(_T_49, UInt<31>("h07fffffff")) @[el2_lsu_addrcheck.scala 67:56]
|
||||
node _T_51 = or(UInt<1>("h00"), UInt<31>("h07fffffff")) @[el2_lsu_addrcheck.scala 67:121]
|
||||
node _T_52 = eq(_T_50, _T_51) @[el2_lsu_addrcheck.scala 67:88]
|
||||
node _T_53 = and(UInt<1>("h01"), _T_52) @[el2_lsu_addrcheck.scala 67:30]
|
||||
node _T_54 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 68:49]
|
||||
node _T_55 = or(_T_54, UInt<30>("h03fffffff")) @[el2_lsu_addrcheck.scala 68:56]
|
||||
node _T_56 = or(UInt<32>("h0c0000000"), UInt<30>("h03fffffff")) @[el2_lsu_addrcheck.scala 68:121]
|
||||
node _T_57 = eq(_T_55, _T_56) @[el2_lsu_addrcheck.scala 68:88]
|
||||
node _T_58 = and(UInt<1>("h01"), _T_57) @[el2_lsu_addrcheck.scala 68:30]
|
||||
node _T_59 = or(_T_53, _T_58) @[el2_lsu_addrcheck.scala 67:153]
|
||||
node _T_60 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 69:49]
|
||||
node _T_61 = or(_T_60, UInt<29>("h01fffffff")) @[el2_lsu_addrcheck.scala 69:56]
|
||||
node _T_62 = or(UInt<32>("h0a0000000"), UInt<29>("h01fffffff")) @[el2_lsu_addrcheck.scala 69:121]
|
||||
node _T_63 = eq(_T_61, _T_62) @[el2_lsu_addrcheck.scala 69:88]
|
||||
node _T_64 = and(UInt<1>("h01"), _T_63) @[el2_lsu_addrcheck.scala 69:30]
|
||||
node _T_65 = or(_T_59, _T_64) @[el2_lsu_addrcheck.scala 68:153]
|
||||
node _T_66 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 70:49]
|
||||
node _T_67 = or(_T_66, UInt<28>("h0fffffff")) @[el2_lsu_addrcheck.scala 70:56]
|
||||
node _T_68 = or(UInt<32>("h080000000"), UInt<28>("h0fffffff")) @[el2_lsu_addrcheck.scala 70:121]
|
||||
node _T_69 = eq(_T_67, _T_68) @[el2_lsu_addrcheck.scala 70:88]
|
||||
node _T_70 = and(UInt<1>("h01"), _T_69) @[el2_lsu_addrcheck.scala 70:30]
|
||||
node _T_71 = or(_T_65, _T_70) @[el2_lsu_addrcheck.scala 69:153]
|
||||
node _T_72 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 71:49]
|
||||
node _T_73 = or(_T_72, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 71:56]
|
||||
node _T_74 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 71:121]
|
||||
node _T_75 = eq(_T_73, _T_74) @[el2_lsu_addrcheck.scala 71:88]
|
||||
node _T_76 = and(UInt<1>("h00"), _T_75) @[el2_lsu_addrcheck.scala 71:30]
|
||||
node _T_77 = or(_T_71, _T_76) @[el2_lsu_addrcheck.scala 70:153]
|
||||
node _T_78 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 72:49]
|
||||
node _T_79 = or(_T_78, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 72:56]
|
||||
node _T_80 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 72:121]
|
||||
node _T_81 = eq(_T_79, _T_80) @[el2_lsu_addrcheck.scala 72:88]
|
||||
node _T_82 = and(UInt<1>("h00"), _T_81) @[el2_lsu_addrcheck.scala 72:30]
|
||||
node _T_83 = or(_T_77, _T_82) @[el2_lsu_addrcheck.scala 71:153]
|
||||
node _T_84 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 73:49]
|
||||
node _T_85 = or(_T_84, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 73:56]
|
||||
node _T_86 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 73:121]
|
||||
node _T_87 = eq(_T_85, _T_86) @[el2_lsu_addrcheck.scala 73:88]
|
||||
node _T_88 = and(UInt<1>("h00"), _T_87) @[el2_lsu_addrcheck.scala 73:30]
|
||||
node _T_89 = or(_T_83, _T_88) @[el2_lsu_addrcheck.scala 72:153]
|
||||
node _T_90 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 74:49]
|
||||
node _T_91 = or(_T_90, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 74:56]
|
||||
node _T_92 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 74:121]
|
||||
node _T_93 = eq(_T_91, _T_92) @[el2_lsu_addrcheck.scala 74:88]
|
||||
node _T_94 = and(UInt<1>("h00"), _T_93) @[el2_lsu_addrcheck.scala 74:30]
|
||||
node _T_95 = or(_T_89, _T_94) @[el2_lsu_addrcheck.scala 73:153]
|
||||
node _T_96 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 76:48]
|
||||
node _T_97 = or(_T_96, UInt<31>("h07fffffff")) @[el2_lsu_addrcheck.scala 76:57]
|
||||
node _T_98 = or(UInt<1>("h00"), UInt<31>("h07fffffff")) @[el2_lsu_addrcheck.scala 76:122]
|
||||
node _T_99 = eq(_T_97, _T_98) @[el2_lsu_addrcheck.scala 76:89]
|
||||
node _T_100 = and(UInt<1>("h01"), _T_99) @[el2_lsu_addrcheck.scala 76:31]
|
||||
node _T_101 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 77:49]
|
||||
node _T_102 = or(_T_101, UInt<30>("h03fffffff")) @[el2_lsu_addrcheck.scala 77:58]
|
||||
node _T_103 = or(UInt<32>("h0c0000000"), UInt<30>("h03fffffff")) @[el2_lsu_addrcheck.scala 77:123]
|
||||
node _T_104 = eq(_T_102, _T_103) @[el2_lsu_addrcheck.scala 77:90]
|
||||
node _T_105 = and(UInt<1>("h01"), _T_104) @[el2_lsu_addrcheck.scala 77:32]
|
||||
node _T_106 = or(_T_100, _T_105) @[el2_lsu_addrcheck.scala 76:154]
|
||||
node _T_107 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 78:49]
|
||||
node _T_108 = or(_T_107, UInt<29>("h01fffffff")) @[el2_lsu_addrcheck.scala 78:58]
|
||||
node _T_109 = or(UInt<32>("h0a0000000"), UInt<29>("h01fffffff")) @[el2_lsu_addrcheck.scala 78:123]
|
||||
node _T_110 = eq(_T_108, _T_109) @[el2_lsu_addrcheck.scala 78:90]
|
||||
node _T_111 = and(UInt<1>("h01"), _T_110) @[el2_lsu_addrcheck.scala 78:32]
|
||||
node _T_112 = or(_T_106, _T_111) @[el2_lsu_addrcheck.scala 77:155]
|
||||
node _T_113 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 79:49]
|
||||
node _T_114 = or(_T_113, UInt<28>("h0fffffff")) @[el2_lsu_addrcheck.scala 79:58]
|
||||
node _T_115 = or(UInt<32>("h080000000"), UInt<28>("h0fffffff")) @[el2_lsu_addrcheck.scala 79:123]
|
||||
node _T_116 = eq(_T_114, _T_115) @[el2_lsu_addrcheck.scala 79:90]
|
||||
node _T_117 = and(UInt<1>("h01"), _T_116) @[el2_lsu_addrcheck.scala 79:32]
|
||||
node _T_118 = or(_T_112, _T_117) @[el2_lsu_addrcheck.scala 78:155]
|
||||
node _T_119 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 80:49]
|
||||
node _T_120 = or(_T_119, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 80:58]
|
||||
node _T_121 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 80:123]
|
||||
node _T_122 = eq(_T_120, _T_121) @[el2_lsu_addrcheck.scala 80:90]
|
||||
node _T_123 = and(UInt<1>("h00"), _T_122) @[el2_lsu_addrcheck.scala 80:32]
|
||||
node _T_124 = or(_T_118, _T_123) @[el2_lsu_addrcheck.scala 79:155]
|
||||
node _T_125 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 81:49]
|
||||
node _T_126 = or(_T_125, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 81:58]
|
||||
node _T_127 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 81:123]
|
||||
node _T_128 = eq(_T_126, _T_127) @[el2_lsu_addrcheck.scala 81:90]
|
||||
node _T_129 = and(UInt<1>("h00"), _T_128) @[el2_lsu_addrcheck.scala 81:32]
|
||||
node _T_130 = or(_T_124, _T_129) @[el2_lsu_addrcheck.scala 80:155]
|
||||
node _T_131 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 82:49]
|
||||
node _T_132 = or(_T_131, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 82:58]
|
||||
node _T_133 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 82:123]
|
||||
node _T_134 = eq(_T_132, _T_133) @[el2_lsu_addrcheck.scala 82:90]
|
||||
node _T_135 = and(UInt<1>("h00"), _T_134) @[el2_lsu_addrcheck.scala 82:32]
|
||||
node _T_136 = or(_T_130, _T_135) @[el2_lsu_addrcheck.scala 81:155]
|
||||
node _T_137 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 83:49]
|
||||
node _T_138 = or(_T_137, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 83:58]
|
||||
node _T_139 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 83:123]
|
||||
node _T_140 = eq(_T_138, _T_139) @[el2_lsu_addrcheck.scala 83:90]
|
||||
node _T_141 = and(UInt<1>("h00"), _T_140) @[el2_lsu_addrcheck.scala 83:32]
|
||||
node _T_142 = or(_T_136, _T_141) @[el2_lsu_addrcheck.scala 82:155]
|
||||
node _T_143 = and(_T_95, _T_142) @[el2_lsu_addrcheck.scala 75:7]
|
||||
node non_dccm_access_ok = or(_T_48, _T_143) @[el2_lsu_addrcheck.scala 66:92]
|
||||
node non_dccm_access_ok = or(_T_48, _T_143) @[el2_lsu_addrcheck.scala 66:104]
|
||||
node regpred_access_fault_d = xor(start_addr_dccm_or_pic, base_reg_dccm_or_pic) @[el2_lsu_addrcheck.scala 85:57]
|
||||
node _T_144 = bits(io.start_addr_d, 1, 0) @[el2_lsu_addrcheck.scala 86:70]
|
||||
node _T_145 = neq(_T_144, UInt<2>("h00")) @[el2_lsu_addrcheck.scala 86:76]
|
||||
|
|
@ -246,19 +246,19 @@ circuit el2_lsu_lsc_ctl :
|
|||
node _T_198 = and(_T_197, io.lsu_pkt_d.valid) @[el2_lsu_addrcheck.scala 119:95]
|
||||
node _T_199 = and(_T_198, io.lsu_pkt_d.fast_int) @[el2_lsu_addrcheck.scala 119:116]
|
||||
io.fir_nondccm_access_error_d <= _T_199 @[el2_lsu_addrcheck.scala 119:33]
|
||||
reg _T_200 : UInt, io.lsu_c2_m_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_addrcheck.scala 121:60]
|
||||
reg _T_200 : UInt<1>, io.lsu_c2_m_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_addrcheck.scala 121:60]
|
||||
_T_200 <= is_sideeffects_d @[el2_lsu_addrcheck.scala 121:60]
|
||||
io.is_sideeffects_m <= _T_200 @[el2_lsu_addrcheck.scala 121:50]
|
||||
|
||||
module el2_lsu_lsc_ctl :
|
||||
input clock : Clock
|
||||
input reset : AsyncReset
|
||||
output io : {flip lsu_c1_m_clk : Clock, flip lsu_c1_r_clk : Clock, flip lsu_c2_m_clk : Clock, flip lsu_c2_r_clk : Clock, flip lsu_store_c1_m_clk : Clock, flip lsu_ld_data_r : UInt<32>, flip lsu_ld_data_corr_r : UInt<32>, flip lsu_single_ecc_error_r : UInt<1>, flip lsu_double_ecc_error_r : UInt<1>, flip lsu_ld_data_m : UInt<32>, flip lsu_single_ecc_error_m : UInt<1>, flip lsu_double_ecc_error_m : UInt<1>, flip flush_m_up : UInt<1>, flip flush_r : UInt<1>, flip exu_lsu_rs1_d : UInt<32>, flip exu_lsu_rs2_d : UInt<32>, flip lsu_p : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip dec_lsu_valid_raw_d : UInt<1>, flip dec_lsu_offset_d : UInt<12>, flip picm_mask_data_m : UInt<32>, flip bus_read_data_m : UInt<32>, lsu_result_m : UInt<32>, lsu_result_corr_r : UInt<32>, lsu_addr_d : UInt<32>, lsu_addr_m : UInt<32>, lsu_addr_r : UInt<32>, end_addr_d : UInt<32>, end_addr_m : UInt<32>, end_addr_r : UInt<32>, store_data_m : UInt<32>, flip dec_tlu_mrac_ff : UInt<32>, lsu_exc_m : UInt<1>, is_sideeffects_m : UInt<1>, lsu_commit_r : UInt<1>, lsu_single_ecc_error_incr : UInt<1>, lsu_error_pkt_r : {exc_valid : UInt<1>, single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}, lsu_fir_addr : UInt<31>, lsu_fir_error : UInt<2>, addr_in_dccm_d : UInt<1>, addr_in_dccm_m : UInt<1>, addr_in_dccm_r : UInt<1>, addr_in_pic_d : UInt<1>, addr_in_pic_m : UInt<1>, addr_in_pic_r : UInt<1>, addr_external_m : UInt<1>, flip dma_dccm_req : UInt<1>, flip dma_mem_addr : UInt<32>, flip dma_mem_sz : UInt<3>, flip dma_mem_write : UInt<1>, flip dma_mem_wdata : UInt<64>, lsu_pkt_d : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, lsu_pkt_m : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, lsu_pkt_r : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip scan_mode : UInt<1>}
|
||||
output io : {flip lsu_c1_m_clk : Clock, flip lsu_c1_r_clk : Clock, flip lsu_c2_m_clk : Clock, flip lsu_c2_r_clk : Clock, flip lsu_store_c1_m_clk : Clock, flip lsu_ld_data_r : UInt<32>, flip lsu_ld_data_corr_r : UInt<32>, flip lsu_single_ecc_error_r : UInt<1>, flip lsu_double_ecc_error_r : UInt<1>, flip lsu_ld_data_m : UInt<32>, flip lsu_single_ecc_error_m : UInt<1>, flip lsu_double_ecc_error_m : UInt<1>, flip flush_m_up : UInt<1>, flip flush_r : UInt<1>, flip exu_lsu_rs1_d : UInt<32>, flip exu_lsu_rs2_d : UInt<32>, flip lsu_p : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip dec_lsu_valid_raw_d : UInt<1>, flip dec_lsu_offset_d : UInt<12>, flip picm_mask_data_m : UInt<32>, flip bus_read_data_m : UInt<32>, lsu_result_m : UInt<32>, lsu_result_corr_r : UInt<32>, lsu_addr_d : UInt<32>, lsu_addr_m : UInt<32>, lsu_addr_r : UInt<32>, end_addr_d : UInt<32>, end_addr_m : UInt<32>, end_addr_r : UInt<32>, store_data_m : UInt<32>, flip dec_tlu_mrac_ff : UInt<32>, lsu_exc_m : UInt<1>, is_sideeffects_m : UInt<1>, lsu_commit_r : UInt<1>, lsu_single_ecc_error_incr : UInt<1>, lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<1>, addr : UInt<1>}}, lsu_fir_addr : UInt<31>, lsu_fir_error : UInt<2>, addr_in_dccm_d : UInt<1>, addr_in_dccm_m : UInt<1>, addr_in_dccm_r : UInt<1>, addr_in_pic_d : UInt<1>, addr_in_pic_m : UInt<1>, addr_in_pic_r : UInt<1>, addr_external_m : UInt<1>, flip dma_dccm_req : UInt<1>, flip dma_mem_addr : UInt<32>, flip dma_mem_sz : UInt<3>, flip dma_mem_write : UInt<1>, flip dma_mem_wdata : UInt<64>, lsu_pkt_d : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, lsu_pkt_m : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, lsu_pkt_r : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip scan_mode : UInt<1>}
|
||||
|
||||
wire dma_pkt_d : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>} @[el2_lsu_lsc_ctl.scala 96:29]
|
||||
wire lsu_pkt_m_in : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>} @[el2_lsu_lsc_ctl.scala 97:29]
|
||||
wire lsu_pkt_r_in : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>} @[el2_lsu_lsc_ctl.scala 98:29]
|
||||
wire lsu_error_pkt_m : {exc_valid : UInt<1>, single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>} @[el2_lsu_lsc_ctl.scala 99:29]
|
||||
wire lsu_error_pkt_m : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<1>, addr : UInt<1>}} @[el2_lsu_lsc_ctl.scala 99:29]
|
||||
node _T = bits(io.dec_lsu_valid_raw_d, 0, 0) @[el2_lsu_lsc_ctl.scala 101:52]
|
||||
node lsu_rs1_d = mux(_T, io.exu_lsu_rs1_d, io.dma_mem_addr) @[el2_lsu_lsc_ctl.scala 101:28]
|
||||
node _T_1 = bits(io.dec_lsu_offset_d, 11, 0) @[el2_lsu_lsc_ctl.scala 102:44]
|
||||
|
|
@ -267,43 +267,43 @@ circuit el2_lsu_lsc_ctl :
|
|||
node lsu_offset_d = and(_T_1, _T_3) @[el2_lsu_lsc_ctl.scala 102:51]
|
||||
node _T_4 = bits(io.lsu_pkt_d.load_ldst_bypass_d, 0, 0) @[el2_lsu_lsc_ctl.scala 105:61]
|
||||
node rs1_d = mux(_T_4, io.lsu_result_m, lsu_rs1_d) @[el2_lsu_lsc_ctl.scala 105:28]
|
||||
node _T_5 = bits(rs1_d, 11, 0) @[el2_lib.scala 195:31]
|
||||
node _T_5 = bits(rs1_d, 11, 0) @[el2_lib.scala 232:31]
|
||||
node _T_6 = cat(UInt<1>("h00"), _T_5) @[Cat.scala 29:58]
|
||||
node _T_7 = bits(lsu_offset_d, 11, 0) @[el2_lib.scala 195:60]
|
||||
node _T_7 = bits(lsu_offset_d, 11, 0) @[el2_lib.scala 232:60]
|
||||
node _T_8 = cat(UInt<1>("h00"), _T_7) @[Cat.scala 29:58]
|
||||
node _T_9 = add(_T_6, _T_8) @[el2_lib.scala 195:39]
|
||||
node _T_10 = tail(_T_9, 1) @[el2_lib.scala 195:39]
|
||||
node _T_11 = bits(lsu_offset_d, 11, 11) @[el2_lib.scala 196:41]
|
||||
node _T_12 = bits(_T_10, 12, 12) @[el2_lib.scala 196:50]
|
||||
node _T_13 = xor(_T_11, _T_12) @[el2_lib.scala 196:46]
|
||||
node _T_14 = not(_T_13) @[el2_lib.scala 196:33]
|
||||
node _T_9 = add(_T_6, _T_8) @[el2_lib.scala 232:39]
|
||||
node _T_10 = tail(_T_9, 1) @[el2_lib.scala 232:39]
|
||||
node _T_11 = bits(lsu_offset_d, 11, 11) @[el2_lib.scala 233:41]
|
||||
node _T_12 = bits(_T_10, 12, 12) @[el2_lib.scala 233:50]
|
||||
node _T_13 = xor(_T_11, _T_12) @[el2_lib.scala 233:46]
|
||||
node _T_14 = not(_T_13) @[el2_lib.scala 233:33]
|
||||
node _T_15 = bits(_T_14, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_16 = mux(_T_15, UInt<20>("h0fffff"), UInt<20>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_17 = bits(rs1_d, 31, 12) @[el2_lib.scala 196:63]
|
||||
node _T_18 = and(_T_16, _T_17) @[el2_lib.scala 196:58]
|
||||
node _T_19 = bits(lsu_offset_d, 11, 11) @[el2_lib.scala 197:25]
|
||||
node _T_20 = not(_T_19) @[el2_lib.scala 197:18]
|
||||
node _T_21 = bits(_T_10, 12, 12) @[el2_lib.scala 197:34]
|
||||
node _T_22 = and(_T_20, _T_21) @[el2_lib.scala 197:30]
|
||||
node _T_17 = bits(rs1_d, 31, 12) @[el2_lib.scala 233:63]
|
||||
node _T_18 = and(_T_16, _T_17) @[el2_lib.scala 233:58]
|
||||
node _T_19 = bits(lsu_offset_d, 11, 11) @[el2_lib.scala 234:25]
|
||||
node _T_20 = not(_T_19) @[el2_lib.scala 234:18]
|
||||
node _T_21 = bits(_T_10, 12, 12) @[el2_lib.scala 234:34]
|
||||
node _T_22 = and(_T_20, _T_21) @[el2_lib.scala 234:30]
|
||||
node _T_23 = bits(_T_22, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_24 = mux(_T_23, UInt<20>("h0fffff"), UInt<20>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_25 = bits(rs1_d, 31, 12) @[el2_lib.scala 197:47]
|
||||
node _T_26 = add(_T_25, UInt<1>("h01")) @[el2_lib.scala 197:54]
|
||||
node _T_27 = tail(_T_26, 1) @[el2_lib.scala 197:54]
|
||||
node _T_28 = and(_T_24, _T_27) @[el2_lib.scala 197:41]
|
||||
node _T_29 = or(_T_18, _T_28) @[el2_lib.scala 196:72]
|
||||
node _T_30 = bits(lsu_offset_d, 11, 11) @[el2_lib.scala 198:24]
|
||||
node _T_31 = bits(_T_10, 12, 12) @[el2_lib.scala 198:34]
|
||||
node _T_32 = not(_T_31) @[el2_lib.scala 198:31]
|
||||
node _T_33 = and(_T_30, _T_32) @[el2_lib.scala 198:29]
|
||||
node _T_25 = bits(rs1_d, 31, 12) @[el2_lib.scala 234:47]
|
||||
node _T_26 = add(_T_25, UInt<1>("h01")) @[el2_lib.scala 234:54]
|
||||
node _T_27 = tail(_T_26, 1) @[el2_lib.scala 234:54]
|
||||
node _T_28 = and(_T_24, _T_27) @[el2_lib.scala 234:41]
|
||||
node _T_29 = or(_T_18, _T_28) @[el2_lib.scala 233:72]
|
||||
node _T_30 = bits(lsu_offset_d, 11, 11) @[el2_lib.scala 235:24]
|
||||
node _T_31 = bits(_T_10, 12, 12) @[el2_lib.scala 235:34]
|
||||
node _T_32 = not(_T_31) @[el2_lib.scala 235:31]
|
||||
node _T_33 = and(_T_30, _T_32) @[el2_lib.scala 235:29]
|
||||
node _T_34 = bits(_T_33, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_35 = mux(_T_34, UInt<20>("h0fffff"), UInt<20>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_36 = bits(rs1_d, 31, 12) @[el2_lib.scala 198:47]
|
||||
node _T_37 = sub(_T_36, UInt<1>("h01")) @[el2_lib.scala 198:54]
|
||||
node _T_38 = tail(_T_37, 1) @[el2_lib.scala 198:54]
|
||||
node _T_39 = and(_T_35, _T_38) @[el2_lib.scala 198:41]
|
||||
node _T_40 = or(_T_29, _T_39) @[el2_lib.scala 197:61]
|
||||
node _T_41 = bits(_T_10, 11, 0) @[el2_lib.scala 199:22]
|
||||
node _T_36 = bits(rs1_d, 31, 12) @[el2_lib.scala 235:47]
|
||||
node _T_37 = sub(_T_36, UInt<1>("h01")) @[el2_lib.scala 235:54]
|
||||
node _T_38 = tail(_T_37, 1) @[el2_lib.scala 235:54]
|
||||
node _T_39 = and(_T_35, _T_38) @[el2_lib.scala 235:41]
|
||||
node _T_40 = or(_T_29, _T_39) @[el2_lib.scala 234:61]
|
||||
node _T_41 = bits(_T_10, 11, 0) @[el2_lib.scala 236:22]
|
||||
node full_addr_d = cat(_T_40, _T_41) @[Cat.scala 29:58]
|
||||
node _T_42 = bits(io.lsu_pkt_d.half, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_43 = mux(_T_42, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
|
||||
|
|
@ -396,34 +396,34 @@ circuit el2_lsu_lsc_ctl :
|
|||
node _T_73 = and(_T_71, _T_72) @[el2_lsu_lsc_ctl.scala 157:92]
|
||||
node _T_74 = and(_T_73, io.lsu_pkt_r.valid) @[el2_lsu_lsc_ctl.scala 157:131]
|
||||
io.lsu_single_ecc_error_incr <= _T_74 @[el2_lsu_lsc_ctl.scala 157:32]
|
||||
node _T_75 = or(access_fault_m, misaligned_fault_m) @[el2_lsu_lsc_ctl.scala 179:50]
|
||||
node _T_76 = or(_T_75, io.lsu_double_ecc_error_m) @[el2_lsu_lsc_ctl.scala 179:71]
|
||||
node _T_77 = and(_T_76, io.lsu_pkt_m.valid) @[el2_lsu_lsc_ctl.scala 179:100]
|
||||
node _T_78 = eq(io.lsu_pkt_m.dma, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 179:123]
|
||||
node _T_79 = and(_T_77, _T_78) @[el2_lsu_lsc_ctl.scala 179:121]
|
||||
node _T_80 = eq(io.lsu_pkt_m.fast_int, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 179:143]
|
||||
node _T_81 = and(_T_79, _T_80) @[el2_lsu_lsc_ctl.scala 179:141]
|
||||
node _T_82 = eq(io.flush_m_up, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 179:168]
|
||||
node _T_83 = and(_T_81, _T_82) @[el2_lsu_lsc_ctl.scala 179:166]
|
||||
lsu_error_pkt_m.exc_valid <= _T_83 @[el2_lsu_lsc_ctl.scala 179:31]
|
||||
node _T_84 = eq(lsu_error_pkt_m.exc_valid, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 180:70]
|
||||
node _T_85 = and(io.lsu_single_ecc_error_m, _T_84) @[el2_lsu_lsc_ctl.scala 180:68]
|
||||
node _T_86 = eq(io.lsu_pkt_m.dma, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 180:100]
|
||||
node _T_87 = and(_T_85, _T_86) @[el2_lsu_lsc_ctl.scala 180:98]
|
||||
lsu_error_pkt_m.single_ecc_error <= _T_87 @[el2_lsu_lsc_ctl.scala 180:38]
|
||||
lsu_error_pkt_m.inst_type <= io.lsu_pkt_m.store @[el2_lsu_lsc_ctl.scala 181:38]
|
||||
node _T_88 = not(misaligned_fault_m) @[el2_lsu_lsc_ctl.scala 182:41]
|
||||
lsu_error_pkt_m.exc_type <= _T_88 @[el2_lsu_lsc_ctl.scala 182:38]
|
||||
node _T_89 = eq(misaligned_fault_m, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 183:75]
|
||||
node _T_90 = and(io.lsu_double_ecc_error_m, _T_89) @[el2_lsu_lsc_ctl.scala 183:73]
|
||||
node _T_91 = eq(access_fault_m, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 183:97]
|
||||
node _T_92 = and(_T_90, _T_91) @[el2_lsu_lsc_ctl.scala 183:95]
|
||||
node _T_93 = eq(_T_92, UInt<1>("h01")) @[el2_lsu_lsc_ctl.scala 183:113]
|
||||
node _T_94 = bits(exc_mscause_m, 3, 0) @[el2_lsu_lsc_ctl.scala 183:144]
|
||||
node _T_95 = mux(_T_93, UInt<4>("h01"), _T_94) @[el2_lsu_lsc_ctl.scala 183:44]
|
||||
lsu_error_pkt_m.mscause <= _T_95 @[el2_lsu_lsc_ctl.scala 183:38]
|
||||
node _T_96 = bits(io.lsu_addr_m, 31, 0) @[el2_lsu_lsc_ctl.scala 184:54]
|
||||
lsu_error_pkt_m.addr <= _T_96 @[el2_lsu_lsc_ctl.scala 184:38]
|
||||
node _T_75 = or(access_fault_m, misaligned_fault_m) @[el2_lsu_lsc_ctl.scala 179:46]
|
||||
node _T_76 = or(_T_75, io.lsu_double_ecc_error_m) @[el2_lsu_lsc_ctl.scala 179:67]
|
||||
node _T_77 = and(_T_76, io.lsu_pkt_m.valid) @[el2_lsu_lsc_ctl.scala 179:96]
|
||||
node _T_78 = eq(io.lsu_pkt_m.dma, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 179:119]
|
||||
node _T_79 = and(_T_77, _T_78) @[el2_lsu_lsc_ctl.scala 179:117]
|
||||
node _T_80 = eq(io.lsu_pkt_m.fast_int, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 179:139]
|
||||
node _T_81 = and(_T_79, _T_80) @[el2_lsu_lsc_ctl.scala 179:137]
|
||||
node _T_82 = eq(io.flush_m_up, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 179:164]
|
||||
node _T_83 = and(_T_81, _T_82) @[el2_lsu_lsc_ctl.scala 179:162]
|
||||
lsu_error_pkt_m.valid <= _T_83 @[el2_lsu_lsc_ctl.scala 179:27]
|
||||
node _T_84 = eq(lsu_error_pkt_m.valid, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 180:75]
|
||||
node _T_85 = and(io.lsu_single_ecc_error_m, _T_84) @[el2_lsu_lsc_ctl.scala 180:73]
|
||||
node _T_86 = eq(io.lsu_pkt_m.dma, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 180:101]
|
||||
node _T_87 = and(_T_85, _T_86) @[el2_lsu_lsc_ctl.scala 180:99]
|
||||
lsu_error_pkt_m.bits.single_ecc_error <= _T_87 @[el2_lsu_lsc_ctl.scala 180:43]
|
||||
lsu_error_pkt_m.bits.inst_type <= io.lsu_pkt_m.store @[el2_lsu_lsc_ctl.scala 181:43]
|
||||
node _T_88 = not(misaligned_fault_m) @[el2_lsu_lsc_ctl.scala 182:46]
|
||||
lsu_error_pkt_m.bits.exc_type <= _T_88 @[el2_lsu_lsc_ctl.scala 182:43]
|
||||
node _T_89 = eq(misaligned_fault_m, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 183:80]
|
||||
node _T_90 = and(io.lsu_double_ecc_error_m, _T_89) @[el2_lsu_lsc_ctl.scala 183:78]
|
||||
node _T_91 = eq(access_fault_m, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 183:102]
|
||||
node _T_92 = and(_T_90, _T_91) @[el2_lsu_lsc_ctl.scala 183:100]
|
||||
node _T_93 = eq(_T_92, UInt<1>("h01")) @[el2_lsu_lsc_ctl.scala 183:118]
|
||||
node _T_94 = bits(exc_mscause_m, 3, 0) @[el2_lsu_lsc_ctl.scala 183:149]
|
||||
node _T_95 = mux(_T_93, UInt<4>("h01"), _T_94) @[el2_lsu_lsc_ctl.scala 183:49]
|
||||
lsu_error_pkt_m.bits.mscause <= _T_95 @[el2_lsu_lsc_ctl.scala 183:43]
|
||||
node _T_96 = bits(io.lsu_addr_m, 31, 0) @[el2_lsu_lsc_ctl.scala 184:59]
|
||||
lsu_error_pkt_m.bits.addr <= _T_96 @[el2_lsu_lsc_ctl.scala 184:43]
|
||||
node _T_97 = bits(fir_nondccm_access_error_m, 0, 0) @[el2_lsu_lsc_ctl.scala 185:72]
|
||||
node _T_98 = bits(fir_dccm_access_error_m, 0, 0) @[el2_lsu_lsc_ctl.scala 185:117]
|
||||
node _T_99 = and(io.lsu_pkt_m.fast_int, io.lsu_double_ecc_error_m) @[el2_lsu_lsc_ctl.scala 185:161]
|
||||
|
|
@ -432,26 +432,26 @@ circuit el2_lsu_lsc_ctl :
|
|||
node _T_102 = mux(_T_98, UInt<2>("h02"), _T_101) @[el2_lsu_lsc_ctl.scala 185:92]
|
||||
node _T_103 = mux(_T_97, UInt<2>("h03"), _T_102) @[el2_lsu_lsc_ctl.scala 185:44]
|
||||
lsu_fir_error_m <= _T_103 @[el2_lsu_lsc_ctl.scala 185:38]
|
||||
wire _T_104 : {exc_valid : UInt<1>, single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>} @[el2_lsu_lsc_ctl.scala 186:104]
|
||||
_T_104.addr <= UInt<32>("h00") @[el2_lsu_lsc_ctl.scala 186:104]
|
||||
_T_104.mscause <= UInt<4>("h00") @[el2_lsu_lsc_ctl.scala 186:104]
|
||||
_T_104.exc_type <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 186:104]
|
||||
_T_104.inst_type <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 186:104]
|
||||
_T_104.single_ecc_error <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 186:104]
|
||||
_T_104.exc_valid <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 186:104]
|
||||
reg _T_105 : {exc_valid : UInt<1>, single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}, io.lsu_c2_r_clk with : (reset => (reset, _T_104)) @[el2_lsu_lsc_ctl.scala 186:75]
|
||||
_T_105.addr <= lsu_error_pkt_m.addr @[el2_lsu_lsc_ctl.scala 186:75]
|
||||
_T_105.mscause <= lsu_error_pkt_m.mscause @[el2_lsu_lsc_ctl.scala 186:75]
|
||||
_T_105.exc_type <= lsu_error_pkt_m.exc_type @[el2_lsu_lsc_ctl.scala 186:75]
|
||||
_T_105.inst_type <= lsu_error_pkt_m.inst_type @[el2_lsu_lsc_ctl.scala 186:75]
|
||||
_T_105.single_ecc_error <= lsu_error_pkt_m.single_ecc_error @[el2_lsu_lsc_ctl.scala 186:75]
|
||||
_T_105.exc_valid <= lsu_error_pkt_m.exc_valid @[el2_lsu_lsc_ctl.scala 186:75]
|
||||
io.lsu_error_pkt_r.addr <= _T_105.addr @[el2_lsu_lsc_ctl.scala 186:38]
|
||||
io.lsu_error_pkt_r.mscause <= _T_105.mscause @[el2_lsu_lsc_ctl.scala 186:38]
|
||||
io.lsu_error_pkt_r.exc_type <= _T_105.exc_type @[el2_lsu_lsc_ctl.scala 186:38]
|
||||
io.lsu_error_pkt_r.inst_type <= _T_105.inst_type @[el2_lsu_lsc_ctl.scala 186:38]
|
||||
io.lsu_error_pkt_r.single_ecc_error <= _T_105.single_ecc_error @[el2_lsu_lsc_ctl.scala 186:38]
|
||||
io.lsu_error_pkt_r.exc_valid <= _T_105.exc_valid @[el2_lsu_lsc_ctl.scala 186:38]
|
||||
wire _T_104 : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<1>, addr : UInt<1>}} @[el2_lsu_lsc_ctl.scala 186:104]
|
||||
_T_104.bits.addr <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 186:104]
|
||||
_T_104.bits.mscause <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 186:104]
|
||||
_T_104.bits.exc_type <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 186:104]
|
||||
_T_104.bits.inst_type <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 186:104]
|
||||
_T_104.bits.single_ecc_error <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 186:104]
|
||||
_T_104.valid <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 186:104]
|
||||
reg _T_105 : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<1>, addr : UInt<1>}}, io.lsu_c2_r_clk with : (reset => (reset, _T_104)) @[el2_lsu_lsc_ctl.scala 186:75]
|
||||
_T_105.bits.addr <= lsu_error_pkt_m.bits.addr @[el2_lsu_lsc_ctl.scala 186:75]
|
||||
_T_105.bits.mscause <= lsu_error_pkt_m.bits.mscause @[el2_lsu_lsc_ctl.scala 186:75]
|
||||
_T_105.bits.exc_type <= lsu_error_pkt_m.bits.exc_type @[el2_lsu_lsc_ctl.scala 186:75]
|
||||
_T_105.bits.inst_type <= lsu_error_pkt_m.bits.inst_type @[el2_lsu_lsc_ctl.scala 186:75]
|
||||
_T_105.bits.single_ecc_error <= lsu_error_pkt_m.bits.single_ecc_error @[el2_lsu_lsc_ctl.scala 186:75]
|
||||
_T_105.valid <= lsu_error_pkt_m.valid @[el2_lsu_lsc_ctl.scala 186:75]
|
||||
io.lsu_error_pkt_r.bits.addr <= _T_105.bits.addr @[el2_lsu_lsc_ctl.scala 186:38]
|
||||
io.lsu_error_pkt_r.bits.mscause <= _T_105.bits.mscause @[el2_lsu_lsc_ctl.scala 186:38]
|
||||
io.lsu_error_pkt_r.bits.exc_type <= _T_105.bits.exc_type @[el2_lsu_lsc_ctl.scala 186:38]
|
||||
io.lsu_error_pkt_r.bits.inst_type <= _T_105.bits.inst_type @[el2_lsu_lsc_ctl.scala 186:38]
|
||||
io.lsu_error_pkt_r.bits.single_ecc_error <= _T_105.bits.single_ecc_error @[el2_lsu_lsc_ctl.scala 186:38]
|
||||
io.lsu_error_pkt_r.valid <= _T_105.valid @[el2_lsu_lsc_ctl.scala 186:38]
|
||||
reg _T_106 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_lsc_ctl.scala 187:75]
|
||||
_T_106 <= lsu_fir_error_m @[el2_lsu_lsc_ctl.scala 187:75]
|
||||
io.lsu_fir_error <= _T_106 @[el2_lsu_lsc_ctl.scala 187:38]
|
||||
|
|
@ -622,10 +622,10 @@ circuit el2_lsu_lsc_ctl :
|
|||
io.lsu_pkt_r.half <= _T_134.half @[el2_lsu_lsc_ctl.scala 216:28]
|
||||
io.lsu_pkt_r.by <= _T_134.by @[el2_lsu_lsc_ctl.scala 216:28]
|
||||
io.lsu_pkt_r.fast_int <= _T_134.fast_int @[el2_lsu_lsc_ctl.scala 216:28]
|
||||
reg _T_135 : UInt, io.lsu_c2_m_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_lsc_ctl.scala 217:65]
|
||||
reg _T_135 : UInt<1>, io.lsu_c2_m_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_lsc_ctl.scala 217:65]
|
||||
_T_135 <= lsu_pkt_m_in.valid @[el2_lsu_lsc_ctl.scala 217:65]
|
||||
io.lsu_pkt_m.valid <= _T_135 @[el2_lsu_lsc_ctl.scala 217:28]
|
||||
reg _T_136 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_lsc_ctl.scala 218:65]
|
||||
reg _T_136 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_lsc_ctl.scala 218:65]
|
||||
_T_136 <= lsu_pkt_r_in.valid @[el2_lsu_lsc_ctl.scala 218:65]
|
||||
io.lsu_pkt_r.valid <= _T_136 @[el2_lsu_lsc_ctl.scala 218:28]
|
||||
node _T_137 = bits(io.dma_mem_wdata, 63, 0) @[el2_lsu_lsc_ctl.scala 220:47]
|
||||
|
|
@ -642,33 +642,33 @@ circuit el2_lsu_lsc_ctl :
|
|||
node store_data_m_in = mux(_T_143, _T_144, _T_145) @[el2_lsu_lsc_ctl.scala 222:34]
|
||||
reg store_data_pre_m : UInt, io.lsu_store_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_lsc_ctl.scala 224:72]
|
||||
store_data_pre_m <= store_data_m_in @[el2_lsu_lsc_ctl.scala 224:72]
|
||||
reg _T_146 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_lsc_ctl.scala 225:66]
|
||||
_T_146 <= io.lsu_addr_d @[el2_lsu_lsc_ctl.scala 225:66]
|
||||
io.lsu_addr_m <= _T_146 @[el2_lsu_lsc_ctl.scala 225:28]
|
||||
reg _T_147 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_lsc_ctl.scala 226:66]
|
||||
_T_147 <= io.lsu_addr_m @[el2_lsu_lsc_ctl.scala 226:66]
|
||||
io.lsu_addr_r <= _T_147 @[el2_lsu_lsc_ctl.scala 226:28]
|
||||
reg _T_148 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_lsc_ctl.scala 227:66]
|
||||
_T_148 <= io.end_addr_d @[el2_lsu_lsc_ctl.scala 227:66]
|
||||
io.end_addr_m <= _T_148 @[el2_lsu_lsc_ctl.scala 227:28]
|
||||
reg _T_149 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_lsc_ctl.scala 228:66]
|
||||
_T_149 <= io.end_addr_m @[el2_lsu_lsc_ctl.scala 228:66]
|
||||
io.end_addr_r <= _T_149 @[el2_lsu_lsc_ctl.scala 228:28]
|
||||
reg _T_150 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_lsc_ctl.scala 229:66]
|
||||
_T_150 <= io.addr_in_dccm_d @[el2_lsu_lsc_ctl.scala 229:66]
|
||||
io.addr_in_dccm_m <= _T_150 @[el2_lsu_lsc_ctl.scala 229:28]
|
||||
reg _T_151 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_lsc_ctl.scala 230:66]
|
||||
_T_151 <= io.addr_in_dccm_m @[el2_lsu_lsc_ctl.scala 230:66]
|
||||
io.addr_in_dccm_r <= _T_151 @[el2_lsu_lsc_ctl.scala 230:28]
|
||||
reg _T_152 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_lsc_ctl.scala 231:66]
|
||||
_T_152 <= io.addr_in_pic_d @[el2_lsu_lsc_ctl.scala 231:66]
|
||||
io.addr_in_pic_m <= _T_152 @[el2_lsu_lsc_ctl.scala 231:28]
|
||||
reg _T_153 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_lsc_ctl.scala 232:66]
|
||||
_T_153 <= io.addr_in_pic_m @[el2_lsu_lsc_ctl.scala 232:66]
|
||||
io.addr_in_pic_r <= _T_153 @[el2_lsu_lsc_ctl.scala 232:28]
|
||||
reg _T_154 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_lsc_ctl.scala 233:66]
|
||||
_T_154 <= addrcheck.io.addr_external_d @[el2_lsu_lsc_ctl.scala 233:66]
|
||||
io.addr_external_m <= _T_154 @[el2_lsu_lsc_ctl.scala 233:28]
|
||||
reg _T_146 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_lsc_ctl.scala 225:62]
|
||||
_T_146 <= io.lsu_addr_d @[el2_lsu_lsc_ctl.scala 225:62]
|
||||
io.lsu_addr_m <= _T_146 @[el2_lsu_lsc_ctl.scala 225:24]
|
||||
reg _T_147 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_lsc_ctl.scala 226:62]
|
||||
_T_147 <= io.lsu_addr_m @[el2_lsu_lsc_ctl.scala 226:62]
|
||||
io.lsu_addr_r <= _T_147 @[el2_lsu_lsc_ctl.scala 226:24]
|
||||
reg _T_148 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_lsc_ctl.scala 227:62]
|
||||
_T_148 <= io.end_addr_d @[el2_lsu_lsc_ctl.scala 227:62]
|
||||
io.end_addr_m <= _T_148 @[el2_lsu_lsc_ctl.scala 227:24]
|
||||
reg _T_149 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_lsc_ctl.scala 228:62]
|
||||
_T_149 <= io.end_addr_m @[el2_lsu_lsc_ctl.scala 228:62]
|
||||
io.end_addr_r <= _T_149 @[el2_lsu_lsc_ctl.scala 228:24]
|
||||
reg _T_150 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_lsc_ctl.scala 229:62]
|
||||
_T_150 <= io.addr_in_dccm_d @[el2_lsu_lsc_ctl.scala 229:62]
|
||||
io.addr_in_dccm_m <= _T_150 @[el2_lsu_lsc_ctl.scala 229:24]
|
||||
reg _T_151 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_lsc_ctl.scala 230:62]
|
||||
_T_151 <= io.addr_in_dccm_m @[el2_lsu_lsc_ctl.scala 230:62]
|
||||
io.addr_in_dccm_r <= _T_151 @[el2_lsu_lsc_ctl.scala 230:24]
|
||||
reg _T_152 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_lsc_ctl.scala 231:62]
|
||||
_T_152 <= io.addr_in_pic_d @[el2_lsu_lsc_ctl.scala 231:62]
|
||||
io.addr_in_pic_m <= _T_152 @[el2_lsu_lsc_ctl.scala 231:24]
|
||||
reg _T_153 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_lsc_ctl.scala 232:62]
|
||||
_T_153 <= io.addr_in_pic_m @[el2_lsu_lsc_ctl.scala 232:62]
|
||||
io.addr_in_pic_r <= _T_153 @[el2_lsu_lsc_ctl.scala 232:24]
|
||||
reg _T_154 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_lsc_ctl.scala 233:62]
|
||||
_T_154 <= addrcheck.io.addr_external_d @[el2_lsu_lsc_ctl.scala 233:62]
|
||||
io.addr_external_m <= _T_154 @[el2_lsu_lsc_ctl.scala 233:24]
|
||||
reg addr_external_r : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_lsc_ctl.scala 234:66]
|
||||
addr_external_r <= io.addr_external_m @[el2_lsu_lsc_ctl.scala 234:66]
|
||||
reg bus_read_data_r : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_lsc_ctl.scala 235:66]
|
||||
|
|
|
|||
|
|
@ -26,13 +26,13 @@ module el2_lsu_addrcheck(
|
|||
`ifdef RANDOMIZE_REG_INIT
|
||||
reg [31:0] _RAND_0;
|
||||
`endif // RANDOMIZE_REG_INIT
|
||||
wire start_addr_in_dccm_region_d = io_start_addr_d[31:28] == 4'hf; // @[el2_lib.scala 253:49]
|
||||
wire start_addr_in_dccm_d = io_start_addr_d[31:16] == 16'hf004; // @[el2_lib.scala 258:39]
|
||||
wire end_addr_in_dccm_region_d = io_end_addr_d[31:28] == 4'hf; // @[el2_lib.scala 253:49]
|
||||
wire end_addr_in_dccm_d = io_end_addr_d[31:16] == 16'hf004; // @[el2_lib.scala 258:39]
|
||||
wire start_addr_in_dccm_region_d = io_start_addr_d[31:28] == 4'hf; // @[el2_lib.scala 496:49]
|
||||
wire start_addr_in_dccm_d = io_start_addr_d[31:16] == 16'hf004; // @[el2_lib.scala 501:39]
|
||||
wire end_addr_in_dccm_region_d = io_end_addr_d[31:28] == 4'hf; // @[el2_lib.scala 496:49]
|
||||
wire end_addr_in_dccm_d = io_end_addr_d[31:16] == 16'hf004; // @[el2_lib.scala 501:39]
|
||||
wire addr_in_iccm = io_start_addr_d[31:28] == 4'he; // @[el2_lsu_addrcheck.scala 42:45]
|
||||
wire start_addr_in_pic_d = io_start_addr_d[31:15] == 17'h1e018; // @[el2_lib.scala 258:39]
|
||||
wire end_addr_in_pic_d = io_end_addr_d[31:15] == 17'h1e018; // @[el2_lib.scala 258:39]
|
||||
wire start_addr_in_pic_d = io_start_addr_d[31:15] == 17'h1e018; // @[el2_lib.scala 501:39]
|
||||
wire end_addr_in_pic_d = io_end_addr_d[31:15] == 17'h1e018; // @[el2_lib.scala 501:39]
|
||||
wire start_addr_dccm_or_pic = start_addr_in_dccm_region_d | start_addr_in_dccm_region_d; // @[el2_lsu_addrcheck.scala 54:60]
|
||||
wire _T_17 = io_rs1_region_d == 4'hf; // @[el2_lsu_addrcheck.scala 55:54]
|
||||
wire base_reg_dccm_or_pic = _T_17 | _T_17; // @[el2_lsu_addrcheck.scala 55:73]
|
||||
|
|
@ -50,28 +50,28 @@ module el2_lsu_addrcheck(
|
|||
wire _T_38 = io_lsu_pkt_d_half & _T_37; // @[el2_lsu_addrcheck.scala 62:106]
|
||||
wire _T_39 = _T_35 | _T_38; // @[el2_lsu_addrcheck.scala 62:85]
|
||||
wire is_aligned_d = _T_39 | io_lsu_pkt_d_by; // @[el2_lsu_addrcheck.scala 62:138]
|
||||
wire [31:0] _T_50 = io_start_addr_d | 32'h7fffffff; // @[el2_lsu_addrcheck.scala 67:54]
|
||||
wire _T_52 = _T_50 == 32'h7fffffff; // @[el2_lsu_addrcheck.scala 67:76]
|
||||
wire [31:0] _T_55 = io_start_addr_d | 32'h3fffffff; // @[el2_lsu_addrcheck.scala 68:54]
|
||||
wire _T_57 = _T_55 == 32'hffffffff; // @[el2_lsu_addrcheck.scala 68:76]
|
||||
wire _T_59 = _T_52 | _T_57; // @[el2_lsu_addrcheck.scala 67:121]
|
||||
wire [31:0] _T_61 = io_start_addr_d | 32'h1fffffff; // @[el2_lsu_addrcheck.scala 69:54]
|
||||
wire _T_63 = _T_61 == 32'hbfffffff; // @[el2_lsu_addrcheck.scala 69:76]
|
||||
wire _T_65 = _T_59 | _T_63; // @[el2_lsu_addrcheck.scala 68:121]
|
||||
wire [31:0] _T_67 = io_start_addr_d | 32'hfffffff; // @[el2_lsu_addrcheck.scala 70:54]
|
||||
wire _T_69 = _T_67 == 32'h8fffffff; // @[el2_lsu_addrcheck.scala 70:76]
|
||||
wire _T_71 = _T_65 | _T_69; // @[el2_lsu_addrcheck.scala 69:121]
|
||||
wire [31:0] _T_97 = io_end_addr_d | 32'h7fffffff; // @[el2_lsu_addrcheck.scala 76:55]
|
||||
wire _T_99 = _T_97 == 32'h7fffffff; // @[el2_lsu_addrcheck.scala 76:77]
|
||||
wire [31:0] _T_102 = io_end_addr_d | 32'h3fffffff; // @[el2_lsu_addrcheck.scala 77:56]
|
||||
wire _T_104 = _T_102 == 32'hffffffff; // @[el2_lsu_addrcheck.scala 77:78]
|
||||
wire _T_106 = _T_99 | _T_104; // @[el2_lsu_addrcheck.scala 76:122]
|
||||
wire [31:0] _T_108 = io_end_addr_d | 32'h1fffffff; // @[el2_lsu_addrcheck.scala 78:56]
|
||||
wire _T_110 = _T_108 == 32'hbfffffff; // @[el2_lsu_addrcheck.scala 78:78]
|
||||
wire _T_112 = _T_106 | _T_110; // @[el2_lsu_addrcheck.scala 77:123]
|
||||
wire [31:0] _T_114 = io_end_addr_d | 32'hfffffff; // @[el2_lsu_addrcheck.scala 79:56]
|
||||
wire _T_116 = _T_114 == 32'h8fffffff; // @[el2_lsu_addrcheck.scala 79:78]
|
||||
wire _T_118 = _T_112 | _T_116; // @[el2_lsu_addrcheck.scala 78:123]
|
||||
wire [31:0] _T_50 = io_start_addr_d | 32'h7fffffff; // @[el2_lsu_addrcheck.scala 67:56]
|
||||
wire _T_52 = _T_50 == 32'h7fffffff; // @[el2_lsu_addrcheck.scala 67:88]
|
||||
wire [31:0] _T_55 = io_start_addr_d | 32'h3fffffff; // @[el2_lsu_addrcheck.scala 68:56]
|
||||
wire _T_57 = _T_55 == 32'hffffffff; // @[el2_lsu_addrcheck.scala 68:88]
|
||||
wire _T_59 = _T_52 | _T_57; // @[el2_lsu_addrcheck.scala 67:153]
|
||||
wire [31:0] _T_61 = io_start_addr_d | 32'h1fffffff; // @[el2_lsu_addrcheck.scala 69:56]
|
||||
wire _T_63 = _T_61 == 32'hbfffffff; // @[el2_lsu_addrcheck.scala 69:88]
|
||||
wire _T_65 = _T_59 | _T_63; // @[el2_lsu_addrcheck.scala 68:153]
|
||||
wire [31:0] _T_67 = io_start_addr_d | 32'hfffffff; // @[el2_lsu_addrcheck.scala 70:56]
|
||||
wire _T_69 = _T_67 == 32'h8fffffff; // @[el2_lsu_addrcheck.scala 70:88]
|
||||
wire _T_71 = _T_65 | _T_69; // @[el2_lsu_addrcheck.scala 69:153]
|
||||
wire [31:0] _T_97 = io_end_addr_d | 32'h7fffffff; // @[el2_lsu_addrcheck.scala 76:57]
|
||||
wire _T_99 = _T_97 == 32'h7fffffff; // @[el2_lsu_addrcheck.scala 76:89]
|
||||
wire [31:0] _T_102 = io_end_addr_d | 32'h3fffffff; // @[el2_lsu_addrcheck.scala 77:58]
|
||||
wire _T_104 = _T_102 == 32'hffffffff; // @[el2_lsu_addrcheck.scala 77:90]
|
||||
wire _T_106 = _T_99 | _T_104; // @[el2_lsu_addrcheck.scala 76:154]
|
||||
wire [31:0] _T_108 = io_end_addr_d | 32'h1fffffff; // @[el2_lsu_addrcheck.scala 78:58]
|
||||
wire _T_110 = _T_108 == 32'hbfffffff; // @[el2_lsu_addrcheck.scala 78:90]
|
||||
wire _T_112 = _T_106 | _T_110; // @[el2_lsu_addrcheck.scala 77:155]
|
||||
wire [31:0] _T_114 = io_end_addr_d | 32'hfffffff; // @[el2_lsu_addrcheck.scala 79:58]
|
||||
wire _T_116 = _T_114 == 32'h8fffffff; // @[el2_lsu_addrcheck.scala 79:90]
|
||||
wire _T_118 = _T_112 | _T_116; // @[el2_lsu_addrcheck.scala 78:155]
|
||||
wire non_dccm_access_ok = _T_71 & _T_118; // @[el2_lsu_addrcheck.scala 75:7]
|
||||
wire regpred_access_fault_d = start_addr_dccm_or_pic ^ base_reg_dccm_or_pic; // @[el2_lsu_addrcheck.scala 85:57]
|
||||
wire _T_145 = io_start_addr_d[1:0] != 2'h0; // @[el2_lsu_addrcheck.scala 86:76]
|
||||
|
|
@ -233,12 +233,12 @@ module el2_lsu_lsc_ctl(
|
|||
output io_is_sideeffects_m,
|
||||
output io_lsu_commit_r,
|
||||
output io_lsu_single_ecc_error_incr,
|
||||
output io_lsu_error_pkt_r_exc_valid,
|
||||
output io_lsu_error_pkt_r_single_ecc_error,
|
||||
output io_lsu_error_pkt_r_inst_type,
|
||||
output io_lsu_error_pkt_r_exc_type,
|
||||
output [3:0] io_lsu_error_pkt_r_mscause,
|
||||
output [31:0] io_lsu_error_pkt_r_addr,
|
||||
output io_lsu_error_pkt_r_valid,
|
||||
output io_lsu_error_pkt_r_bits_single_ecc_error,
|
||||
output io_lsu_error_pkt_r_bits_inst_type,
|
||||
output io_lsu_error_pkt_r_bits_exc_type,
|
||||
output io_lsu_error_pkt_r_bits_mscause,
|
||||
output io_lsu_error_pkt_r_bits_addr,
|
||||
output [30:0] io_lsu_fir_addr,
|
||||
output [1:0] io_lsu_fir_error,
|
||||
output io_addr_in_dccm_d,
|
||||
|
|
@ -375,23 +375,23 @@ module el2_lsu_lsc_ctl(
|
|||
wire [31:0] rs1_d = io_lsu_pkt_d_load_ldst_bypass_d ? io_lsu_result_m : lsu_rs1_d; // @[el2_lsu_lsc_ctl.scala 105:28]
|
||||
wire [12:0] _T_6 = {1'h0,rs1_d[11:0]}; // @[Cat.scala 29:58]
|
||||
wire [12:0] _T_8 = {1'h0,lsu_offset_d}; // @[Cat.scala 29:58]
|
||||
wire [12:0] _T_10 = _T_6 + _T_8; // @[el2_lib.scala 195:39]
|
||||
wire _T_13 = lsu_offset_d[11] ^ _T_10[12]; // @[el2_lib.scala 196:46]
|
||||
wire _T_14 = ~_T_13; // @[el2_lib.scala 196:33]
|
||||
wire [12:0] _T_10 = _T_6 + _T_8; // @[el2_lib.scala 232:39]
|
||||
wire _T_13 = lsu_offset_d[11] ^ _T_10[12]; // @[el2_lib.scala 233:46]
|
||||
wire _T_14 = ~_T_13; // @[el2_lib.scala 233:33]
|
||||
wire [19:0] _T_16 = _T_14 ? 20'hfffff : 20'h0; // @[Bitwise.scala 72:12]
|
||||
wire [19:0] _T_18 = _T_16 & rs1_d[31:12]; // @[el2_lib.scala 196:58]
|
||||
wire _T_20 = ~lsu_offset_d[11]; // @[el2_lib.scala 197:18]
|
||||
wire _T_22 = _T_20 & _T_10[12]; // @[el2_lib.scala 197:30]
|
||||
wire [19:0] _T_18 = _T_16 & rs1_d[31:12]; // @[el2_lib.scala 233:58]
|
||||
wire _T_20 = ~lsu_offset_d[11]; // @[el2_lib.scala 234:18]
|
||||
wire _T_22 = _T_20 & _T_10[12]; // @[el2_lib.scala 234:30]
|
||||
wire [19:0] _T_24 = _T_22 ? 20'hfffff : 20'h0; // @[Bitwise.scala 72:12]
|
||||
wire [19:0] _T_27 = rs1_d[31:12] + 20'h1; // @[el2_lib.scala 197:54]
|
||||
wire [19:0] _T_28 = _T_24 & _T_27; // @[el2_lib.scala 197:41]
|
||||
wire [19:0] _T_29 = _T_18 | _T_28; // @[el2_lib.scala 196:72]
|
||||
wire _T_32 = ~_T_10[12]; // @[el2_lib.scala 198:31]
|
||||
wire _T_33 = lsu_offset_d[11] & _T_32; // @[el2_lib.scala 198:29]
|
||||
wire [19:0] _T_27 = rs1_d[31:12] + 20'h1; // @[el2_lib.scala 234:54]
|
||||
wire [19:0] _T_28 = _T_24 & _T_27; // @[el2_lib.scala 234:41]
|
||||
wire [19:0] _T_29 = _T_18 | _T_28; // @[el2_lib.scala 233:72]
|
||||
wire _T_32 = ~_T_10[12]; // @[el2_lib.scala 235:31]
|
||||
wire _T_33 = lsu_offset_d[11] & _T_32; // @[el2_lib.scala 235:29]
|
||||
wire [19:0] _T_35 = _T_33 ? 20'hfffff : 20'h0; // @[Bitwise.scala 72:12]
|
||||
wire [19:0] _T_38 = rs1_d[31:12] - 20'h1; // @[el2_lib.scala 198:54]
|
||||
wire [19:0] _T_39 = _T_35 & _T_38; // @[el2_lib.scala 198:41]
|
||||
wire [19:0] _T_40 = _T_29 | _T_39; // @[el2_lib.scala 197:61]
|
||||
wire [19:0] _T_38 = rs1_d[31:12] - 20'h1; // @[el2_lib.scala 235:54]
|
||||
wire [19:0] _T_39 = _T_35 & _T_38; // @[el2_lib.scala 235:41]
|
||||
wire [19:0] _T_40 = _T_29 | _T_39; // @[el2_lib.scala 234:61]
|
||||
wire [2:0] _T_43 = io_lsu_pkt_d_half ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
|
||||
wire [2:0] _T_44 = _T_43 & 3'h1; // @[el2_lsu_lsc_ctl.scala 110:53]
|
||||
wire [2:0] _T_46 = io_lsu_pkt_d_word ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
|
||||
|
|
@ -415,27 +415,28 @@ module el2_lsu_lsc_ctl(
|
|||
wire _T_71 = io_lsu_single_ecc_error_r & _T_70; // @[el2_lsu_lsc_ctl.scala 157:62]
|
||||
wire _T_72 = io_lsu_commit_r | io_lsu_pkt_r_dma; // @[el2_lsu_lsc_ctl.scala 157:111]
|
||||
wire _T_73 = _T_71 & _T_72; // @[el2_lsu_lsc_ctl.scala 157:92]
|
||||
wire _T_76 = _T_69 | io_lsu_double_ecc_error_m; // @[el2_lsu_lsc_ctl.scala 179:71]
|
||||
wire _T_77 = _T_76 & io_lsu_pkt_m_valid; // @[el2_lsu_lsc_ctl.scala 179:100]
|
||||
wire _T_78 = ~io_lsu_pkt_m_dma; // @[el2_lsu_lsc_ctl.scala 179:123]
|
||||
wire _T_79 = _T_77 & _T_78; // @[el2_lsu_lsc_ctl.scala 179:121]
|
||||
wire _T_80 = ~io_lsu_pkt_m_fast_int; // @[el2_lsu_lsc_ctl.scala 179:143]
|
||||
wire _T_81 = _T_79 & _T_80; // @[el2_lsu_lsc_ctl.scala 179:141]
|
||||
wire _T_82 = ~io_flush_m_up; // @[el2_lsu_lsc_ctl.scala 179:168]
|
||||
wire lsu_error_pkt_m_exc_valid = _T_81 & _T_82; // @[el2_lsu_lsc_ctl.scala 179:166]
|
||||
wire _T_84 = ~lsu_error_pkt_m_exc_valid; // @[el2_lsu_lsc_ctl.scala 180:70]
|
||||
wire _T_85 = io_lsu_single_ecc_error_m & _T_84; // @[el2_lsu_lsc_ctl.scala 180:68]
|
||||
wire lsu_error_pkt_m_exc_type = ~misaligned_fault_m; // @[el2_lsu_lsc_ctl.scala 182:41]
|
||||
wire _T_90 = io_lsu_double_ecc_error_m & lsu_error_pkt_m_exc_type; // @[el2_lsu_lsc_ctl.scala 183:73]
|
||||
wire _T_91 = ~access_fault_m; // @[el2_lsu_lsc_ctl.scala 183:97]
|
||||
wire _T_92 = _T_90 & _T_91; // @[el2_lsu_lsc_ctl.scala 183:95]
|
||||
wire _T_76 = _T_69 | io_lsu_double_ecc_error_m; // @[el2_lsu_lsc_ctl.scala 179:67]
|
||||
wire _T_77 = _T_76 & io_lsu_pkt_m_valid; // @[el2_lsu_lsc_ctl.scala 179:96]
|
||||
wire _T_78 = ~io_lsu_pkt_m_dma; // @[el2_lsu_lsc_ctl.scala 179:119]
|
||||
wire _T_79 = _T_77 & _T_78; // @[el2_lsu_lsc_ctl.scala 179:117]
|
||||
wire _T_80 = ~io_lsu_pkt_m_fast_int; // @[el2_lsu_lsc_ctl.scala 179:139]
|
||||
wire _T_81 = _T_79 & _T_80; // @[el2_lsu_lsc_ctl.scala 179:137]
|
||||
wire _T_82 = ~io_flush_m_up; // @[el2_lsu_lsc_ctl.scala 179:164]
|
||||
wire lsu_error_pkt_m_valid = _T_81 & _T_82; // @[el2_lsu_lsc_ctl.scala 179:162]
|
||||
wire _T_84 = ~lsu_error_pkt_m_valid; // @[el2_lsu_lsc_ctl.scala 180:75]
|
||||
wire _T_85 = io_lsu_single_ecc_error_m & _T_84; // @[el2_lsu_lsc_ctl.scala 180:73]
|
||||
wire lsu_error_pkt_m_bits_exc_type = ~misaligned_fault_m; // @[el2_lsu_lsc_ctl.scala 182:46]
|
||||
wire _T_90 = io_lsu_double_ecc_error_m & lsu_error_pkt_m_bits_exc_type; // @[el2_lsu_lsc_ctl.scala 183:78]
|
||||
wire _T_91 = ~access_fault_m; // @[el2_lsu_lsc_ctl.scala 183:102]
|
||||
wire _T_92 = _T_90 & _T_91; // @[el2_lsu_lsc_ctl.scala 183:100]
|
||||
wire [3:0] _T_95 = _T_92 ? 4'h1 : exc_mscause_m; // @[el2_lsu_lsc_ctl.scala 183:49]
|
||||
wire _T_99 = io_lsu_pkt_m_fast_int & io_lsu_double_ecc_error_m; // @[el2_lsu_lsc_ctl.scala 185:161]
|
||||
reg _T_105_exc_valid; // @[el2_lsu_lsc_ctl.scala 186:75]
|
||||
reg _T_105_single_ecc_error; // @[el2_lsu_lsc_ctl.scala 186:75]
|
||||
reg _T_105_inst_type; // @[el2_lsu_lsc_ctl.scala 186:75]
|
||||
reg _T_105_exc_type; // @[el2_lsu_lsc_ctl.scala 186:75]
|
||||
reg [3:0] _T_105_mscause; // @[el2_lsu_lsc_ctl.scala 186:75]
|
||||
reg [31:0] _T_105_addr; // @[el2_lsu_lsc_ctl.scala 186:75]
|
||||
reg _T_105_valid; // @[el2_lsu_lsc_ctl.scala 186:75]
|
||||
reg _T_105_bits_single_ecc_error; // @[el2_lsu_lsc_ctl.scala 186:75]
|
||||
reg _T_105_bits_inst_type; // @[el2_lsu_lsc_ctl.scala 186:75]
|
||||
reg _T_105_bits_exc_type; // @[el2_lsu_lsc_ctl.scala 186:75]
|
||||
reg _T_105_bits_mscause; // @[el2_lsu_lsc_ctl.scala 186:75]
|
||||
reg _T_105_bits_addr; // @[el2_lsu_lsc_ctl.scala 186:75]
|
||||
reg [1:0] _T_106; // @[el2_lsu_lsc_ctl.scala 187:75]
|
||||
wire dma_pkt_d_load = ~io_dma_mem_write; // @[el2_lsu_lsc_ctl.scala 194:25]
|
||||
wire dma_pkt_d_by = io_dma_mem_sz == 3'h0; // @[el2_lsu_lsc_ctl.scala 195:45]
|
||||
|
|
@ -480,15 +481,15 @@ module el2_lsu_lsc_ctl(
|
|||
wire [5:0] _T_139 = {io_dma_mem_addr[2:0],3'h0}; // @[Cat.scala 29:58]
|
||||
wire [63:0] dma_mem_wdata_shifted = io_dma_mem_wdata >> _T_139; // @[el2_lsu_lsc_ctl.scala 220:54]
|
||||
reg [31:0] store_data_pre_m; // @[el2_lsu_lsc_ctl.scala 224:72]
|
||||
reg [31:0] _T_146; // @[el2_lsu_lsc_ctl.scala 225:66]
|
||||
reg [31:0] _T_147; // @[el2_lsu_lsc_ctl.scala 226:66]
|
||||
reg [31:0] _T_148; // @[el2_lsu_lsc_ctl.scala 227:66]
|
||||
reg [31:0] _T_149; // @[el2_lsu_lsc_ctl.scala 228:66]
|
||||
reg _T_150; // @[el2_lsu_lsc_ctl.scala 229:66]
|
||||
reg _T_151; // @[el2_lsu_lsc_ctl.scala 230:66]
|
||||
reg _T_152; // @[el2_lsu_lsc_ctl.scala 231:66]
|
||||
reg _T_153; // @[el2_lsu_lsc_ctl.scala 232:66]
|
||||
reg _T_154; // @[el2_lsu_lsc_ctl.scala 233:66]
|
||||
reg [31:0] _T_146; // @[el2_lsu_lsc_ctl.scala 225:62]
|
||||
reg [31:0] _T_147; // @[el2_lsu_lsc_ctl.scala 226:62]
|
||||
reg [31:0] _T_148; // @[el2_lsu_lsc_ctl.scala 227:62]
|
||||
reg [31:0] _T_149; // @[el2_lsu_lsc_ctl.scala 228:62]
|
||||
reg _T_150; // @[el2_lsu_lsc_ctl.scala 229:62]
|
||||
reg _T_151; // @[el2_lsu_lsc_ctl.scala 230:62]
|
||||
reg _T_152; // @[el2_lsu_lsc_ctl.scala 231:62]
|
||||
reg _T_153; // @[el2_lsu_lsc_ctl.scala 232:62]
|
||||
reg _T_154; // @[el2_lsu_lsc_ctl.scala 233:62]
|
||||
reg addr_external_r; // @[el2_lsu_lsc_ctl.scala 234:66]
|
||||
reg [31:0] bus_read_data_r; // @[el2_lsu_lsc_ctl.scala 235:66]
|
||||
wire _T_156 = io_lsu_pkt_r_store | io_lsu_pkt_r_load; // @[el2_lsu_lsc_ctl.scala 241:63]
|
||||
|
|
@ -578,31 +579,31 @@ module el2_lsu_lsc_ctl(
|
|||
assign io_lsu_result_m = _T_208 | _T_212; // @[el2_lsu_lsc_ctl.scala 265:27]
|
||||
assign io_lsu_result_corr_r = _T_248 | _T_252; // @[el2_lsu_lsc_ctl.scala 270:27]
|
||||
assign io_lsu_addr_d = {_T_40,_T_10[11:0]}; // @[el2_lsu_lsc_ctl.scala 239:28]
|
||||
assign io_lsu_addr_m = _T_146; // @[el2_lsu_lsc_ctl.scala 225:28]
|
||||
assign io_lsu_addr_r = _T_147; // @[el2_lsu_lsc_ctl.scala 226:28]
|
||||
assign io_lsu_addr_m = _T_146; // @[el2_lsu_lsc_ctl.scala 225:24]
|
||||
assign io_lsu_addr_r = _T_147; // @[el2_lsu_lsc_ctl.scala 226:24]
|
||||
assign io_end_addr_d = rs1_d + _T_64; // @[el2_lsu_lsc_ctl.scala 116:24]
|
||||
assign io_end_addr_m = _T_148; // @[el2_lsu_lsc_ctl.scala 227:28]
|
||||
assign io_end_addr_r = _T_149; // @[el2_lsu_lsc_ctl.scala 228:28]
|
||||
assign io_end_addr_m = _T_148; // @[el2_lsu_lsc_ctl.scala 227:24]
|
||||
assign io_end_addr_r = _T_149; // @[el2_lsu_lsc_ctl.scala 228:24]
|
||||
assign io_store_data_m = _T_166 & _T_168; // @[el2_lsu_lsc_ctl.scala 242:29]
|
||||
assign io_lsu_exc_m = access_fault_m | misaligned_fault_m; // @[el2_lsu_lsc_ctl.scala 156:16]
|
||||
assign io_is_sideeffects_m = addrcheck_io_is_sideeffects_m; // @[el2_lsu_lsc_ctl.scala 129:42]
|
||||
assign io_lsu_commit_r = _T_159 & _T_160; // @[el2_lsu_lsc_ctl.scala 241:19]
|
||||
assign io_lsu_single_ecc_error_incr = _T_73 & io_lsu_pkt_r_valid; // @[el2_lsu_lsc_ctl.scala 157:32]
|
||||
assign io_lsu_error_pkt_r_exc_valid = _T_105_exc_valid; // @[el2_lsu_lsc_ctl.scala 186:38]
|
||||
assign io_lsu_error_pkt_r_single_ecc_error = _T_105_single_ecc_error; // @[el2_lsu_lsc_ctl.scala 186:38]
|
||||
assign io_lsu_error_pkt_r_inst_type = _T_105_inst_type; // @[el2_lsu_lsc_ctl.scala 186:38]
|
||||
assign io_lsu_error_pkt_r_exc_type = _T_105_exc_type; // @[el2_lsu_lsc_ctl.scala 186:38]
|
||||
assign io_lsu_error_pkt_r_mscause = _T_105_mscause; // @[el2_lsu_lsc_ctl.scala 186:38]
|
||||
assign io_lsu_error_pkt_r_addr = _T_105_addr; // @[el2_lsu_lsc_ctl.scala 186:38]
|
||||
assign io_lsu_error_pkt_r_valid = _T_105_valid; // @[el2_lsu_lsc_ctl.scala 186:38]
|
||||
assign io_lsu_error_pkt_r_bits_single_ecc_error = _T_105_bits_single_ecc_error; // @[el2_lsu_lsc_ctl.scala 186:38]
|
||||
assign io_lsu_error_pkt_r_bits_inst_type = _T_105_bits_inst_type; // @[el2_lsu_lsc_ctl.scala 186:38]
|
||||
assign io_lsu_error_pkt_r_bits_exc_type = _T_105_bits_exc_type; // @[el2_lsu_lsc_ctl.scala 186:38]
|
||||
assign io_lsu_error_pkt_r_bits_mscause = _T_105_bits_mscause; // @[el2_lsu_lsc_ctl.scala 186:38]
|
||||
assign io_lsu_error_pkt_r_bits_addr = _T_105_bits_addr; // @[el2_lsu_lsc_ctl.scala 186:38]
|
||||
assign io_lsu_fir_addr = io_lsu_ld_data_corr_r[31:1]; // @[el2_lsu_lsc_ctl.scala 237:28]
|
||||
assign io_lsu_fir_error = _T_106; // @[el2_lsu_lsc_ctl.scala 187:38]
|
||||
assign io_addr_in_dccm_d = addrcheck_io_addr_in_dccm_d; // @[el2_lsu_lsc_ctl.scala 130:42]
|
||||
assign io_addr_in_dccm_m = _T_150; // @[el2_lsu_lsc_ctl.scala 229:28]
|
||||
assign io_addr_in_dccm_r = _T_151; // @[el2_lsu_lsc_ctl.scala 230:28]
|
||||
assign io_addr_in_dccm_m = _T_150; // @[el2_lsu_lsc_ctl.scala 229:24]
|
||||
assign io_addr_in_dccm_r = _T_151; // @[el2_lsu_lsc_ctl.scala 230:24]
|
||||
assign io_addr_in_pic_d = addrcheck_io_addr_in_pic_d; // @[el2_lsu_lsc_ctl.scala 131:42]
|
||||
assign io_addr_in_pic_m = _T_152; // @[el2_lsu_lsc_ctl.scala 231:28]
|
||||
assign io_addr_in_pic_r = _T_153; // @[el2_lsu_lsc_ctl.scala 232:28]
|
||||
assign io_addr_external_m = _T_154; // @[el2_lsu_lsc_ctl.scala 233:28]
|
||||
assign io_addr_in_pic_m = _T_152; // @[el2_lsu_lsc_ctl.scala 231:24]
|
||||
assign io_addr_in_pic_r = _T_153; // @[el2_lsu_lsc_ctl.scala 232:24]
|
||||
assign io_addr_external_m = _T_154; // @[el2_lsu_lsc_ctl.scala 233:24]
|
||||
assign io_lsu_pkt_d_fast_int = io_dec_lsu_valid_raw_d & io_lsu_p_fast_int; // @[el2_lsu_lsc_ctl.scala 207:20]
|
||||
assign io_lsu_pkt_d_by = io_dec_lsu_valid_raw_d ? io_lsu_p_by : dma_pkt_d_by; // @[el2_lsu_lsc_ctl.scala 207:20]
|
||||
assign io_lsu_pkt_d_half = io_dec_lsu_valid_raw_d ? io_lsu_p_half : dma_pkt_d_half; // @[el2_lsu_lsc_ctl.scala 207:20]
|
||||
|
|
@ -702,17 +703,17 @@ initial begin
|
|||
_RAND_4 = {1{`RANDOM}};
|
||||
fir_nondccm_access_error_m = _RAND_4[0:0];
|
||||
_RAND_5 = {1{`RANDOM}};
|
||||
_T_105_exc_valid = _RAND_5[0:0];
|
||||
_T_105_valid = _RAND_5[0:0];
|
||||
_RAND_6 = {1{`RANDOM}};
|
||||
_T_105_single_ecc_error = _RAND_6[0:0];
|
||||
_T_105_bits_single_ecc_error = _RAND_6[0:0];
|
||||
_RAND_7 = {1{`RANDOM}};
|
||||
_T_105_inst_type = _RAND_7[0:0];
|
||||
_T_105_bits_inst_type = _RAND_7[0:0];
|
||||
_RAND_8 = {1{`RANDOM}};
|
||||
_T_105_exc_type = _RAND_8[0:0];
|
||||
_T_105_bits_exc_type = _RAND_8[0:0];
|
||||
_RAND_9 = {1{`RANDOM}};
|
||||
_T_105_mscause = _RAND_9[3:0];
|
||||
_T_105_bits_mscause = _RAND_9[0:0];
|
||||
_RAND_10 = {1{`RANDOM}};
|
||||
_T_105_addr = _RAND_10[31:0];
|
||||
_T_105_bits_addr = _RAND_10[0:0];
|
||||
_RAND_11 = {1{`RANDOM}};
|
||||
_T_106 = _RAND_11[1:0];
|
||||
_RAND_12 = {1{`RANDOM}};
|
||||
|
|
@ -808,22 +809,22 @@ initial begin
|
|||
fir_nondccm_access_error_m = 1'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
_T_105_exc_valid = 1'h0;
|
||||
_T_105_valid = 1'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
_T_105_single_ecc_error = 1'h0;
|
||||
_T_105_bits_single_ecc_error = 1'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
_T_105_inst_type = 1'h0;
|
||||
_T_105_bits_inst_type = 1'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
_T_105_exc_type = 1'h0;
|
||||
_T_105_bits_exc_type = 1'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
_T_105_mscause = 4'h0;
|
||||
_T_105_bits_mscause = 1'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
_T_105_addr = 32'h0;
|
||||
_T_105_bits_addr = 1'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
_T_106 = 2'h0;
|
||||
|
|
@ -985,46 +986,44 @@ end // initial
|
|||
end
|
||||
always @(posedge io_lsu_c2_r_clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
_T_105_exc_valid <= 1'h0;
|
||||
_T_105_valid <= 1'h0;
|
||||
end else begin
|
||||
_T_105_exc_valid <= _T_81 & _T_82;
|
||||
_T_105_valid <= _T_81 & _T_82;
|
||||
end
|
||||
end
|
||||
always @(posedge io_lsu_c2_r_clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
_T_105_single_ecc_error <= 1'h0;
|
||||
_T_105_bits_single_ecc_error <= 1'h0;
|
||||
end else begin
|
||||
_T_105_single_ecc_error <= _T_85 & _T_78;
|
||||
_T_105_bits_single_ecc_error <= _T_85 & _T_78;
|
||||
end
|
||||
end
|
||||
always @(posedge io_lsu_c2_r_clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
_T_105_inst_type <= 1'h0;
|
||||
_T_105_bits_inst_type <= 1'h0;
|
||||
end else begin
|
||||
_T_105_inst_type <= io_lsu_pkt_m_store;
|
||||
_T_105_bits_inst_type <= io_lsu_pkt_m_store;
|
||||
end
|
||||
end
|
||||
always @(posedge io_lsu_c2_r_clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
_T_105_exc_type <= 1'h0;
|
||||
_T_105_bits_exc_type <= 1'h0;
|
||||
end else begin
|
||||
_T_105_exc_type <= ~misaligned_fault_m;
|
||||
_T_105_bits_exc_type <= ~misaligned_fault_m;
|
||||
end
|
||||
end
|
||||
always @(posedge io_lsu_c2_r_clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
_T_105_mscause <= 4'h0;
|
||||
end else if (_T_92) begin
|
||||
_T_105_mscause <= 4'h1;
|
||||
_T_105_bits_mscause <= 1'h0;
|
||||
end else begin
|
||||
_T_105_mscause <= exc_mscause_m;
|
||||
_T_105_bits_mscause <= _T_95[0];
|
||||
end
|
||||
end
|
||||
always @(posedge io_lsu_c2_r_clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
_T_105_addr <= 32'h0;
|
||||
_T_105_bits_addr <= 1'h0;
|
||||
end else begin
|
||||
_T_105_addr <= io_lsu_addr_m;
|
||||
_T_105_bits_addr <= io_lsu_addr_m[0];
|
||||
end
|
||||
end
|
||||
always @(posedge io_lsu_c2_r_clk or posedge reset) begin
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
File diff suppressed because one or more lines are too long
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,333 @@
|
|||
//********************************************************************************
|
||||
// SPDX-License-Identifier: Apache-2.0
|
||||
// Copyright 2020 Western Digital Corporation or it's affiliates.
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
//********************************************************************************
|
||||
|
||||
//********************************************************************************
|
||||
// Icache closely coupled memory --- ICCM
|
||||
//********************************************************************************
|
||||
|
||||
module el2_ifu_iccm_mem
|
||||
#(
|
||||
parameter ICCM_BITS,
|
||||
parameter ICCM_BANK_INDEX_LO,
|
||||
parameter ICCM_INDEX_BITS,
|
||||
parameter ICCM_BANK_HI,
|
||||
parameter ICCM_NUM_BANKS,
|
||||
parameter ICCM_BANK_BITS )(
|
||||
input logic clk,
|
||||
input logic rst_l,
|
||||
input logic clk_override,
|
||||
|
||||
input logic iccm_wren,
|
||||
input logic iccm_rden,
|
||||
input logic [ICCM_BITS-1:1] iccm_rw_addr,
|
||||
input logic iccm_buf_correct_ecc, // ICCM is doing a single bit error correct cycle
|
||||
input logic iccm_correction_state, // We are under a correction - This is needed to guard replacements when hit
|
||||
input logic [2:0] iccm_wr_size,
|
||||
input logic [77:0] iccm_wr_data,
|
||||
|
||||
|
||||
output logic [63:0] iccm_rd_data,
|
||||
output logic [77:0] iccm_rd_data_ecc,
|
||||
input logic scan_mode
|
||||
|
||||
);
|
||||
|
||||
|
||||
logic [ICCM_NUM_BANKS-1:0] wren_bank;
|
||||
logic [ICCM_NUM_BANKS-1:0] rden_bank;
|
||||
logic [ICCM_NUM_BANKS-1:0] iccm_clken;
|
||||
logic [ICCM_NUM_BANKS-1:0] [ICCM_BITS-1:ICCM_BANK_INDEX_LO] addr_bank;
|
||||
|
||||
logic [ICCM_NUM_BANKS-1:0] [38:0] iccm_bank_dout, iccm_bank_dout_fn;
|
||||
logic [ICCM_NUM_BANKS-1:0] [38:0] iccm_bank_wr_data;
|
||||
logic [ICCM_BITS-1:1] addr_bank_inc;
|
||||
logic [ICCM_BANK_HI : 2] iccm_rd_addr_hi_q;
|
||||
logic [ICCM_BANK_HI : 1] iccm_rd_addr_lo_q;
|
||||
logic [63:0] iccm_rd_data_pre;
|
||||
logic [63:0] iccm_data;
|
||||
logic [1:0] addr_incr;
|
||||
logic [ICCM_NUM_BANKS-1:0] [38:0] iccm_bank_wr_data_vec;
|
||||
|
||||
// logic to handle hard persisten faults
|
||||
logic [1:0] [ICCM_BITS-1:2] redundant_address;
|
||||
logic [1:0] [38:0] redundant_data;
|
||||
logic [1:0] redundant_valid;
|
||||
logic [ICCM_NUM_BANKS-1:0] sel_red1, sel_red0, sel_red1_q, sel_red0_q;
|
||||
|
||||
|
||||
logic [38:0] redundant_data0_in, redundant_data1_in;
|
||||
logic redundant_lru, redundant_lru_in, redundant_lru_en;
|
||||
logic redundant_data0_en;
|
||||
logic redundant_data1_en;
|
||||
logic r0_addr_en, r1_addr_en;
|
||||
|
||||
assign addr_incr[1:0] = (iccm_wr_size[1:0] == 2'b11) ? 2'b10: 2'b01;
|
||||
assign addr_bank_inc[ICCM_BITS-1 : 1] = iccm_rw_addr[ICCM_BITS-1 : 1] + addr_incr[1:0];
|
||||
|
||||
for (genvar i=0; i<32'(ICCM_NUM_BANKS)/2; i++) begin: mem_bank_data
|
||||
assign iccm_bank_wr_data_vec[(2*i)] = iccm_wr_data[38:0];
|
||||
assign iccm_bank_wr_data_vec[(2*i)+1] = iccm_wr_data[77:39];
|
||||
end
|
||||
|
||||
for (genvar i=0; i<32'(ICCM_NUM_BANKS); i++) begin: mem_bank
|
||||
assign wren_bank[i] = iccm_wren & ((iccm_rw_addr[ICCM_BANK_HI:2] == i) | (addr_bank_inc[ICCM_BANK_HI:2] == i));
|
||||
assign iccm_bank_wr_data[i] = iccm_bank_wr_data_vec[i];
|
||||
assign rden_bank[i] = iccm_rden & ( (iccm_rw_addr[ICCM_BANK_HI:2] == i) | (addr_bank_inc[ICCM_BANK_HI:2] == i));
|
||||
assign iccm_clken[i] = wren_bank[i] | rden_bank[i] | clk_override;
|
||||
assign addr_bank[i][ICCM_BITS-1 : ICCM_BANK_INDEX_LO] = wren_bank[i] ? iccm_rw_addr[ICCM_BITS-1 : ICCM_BANK_INDEX_LO] :
|
||||
((addr_bank_inc[ICCM_BANK_HI:2] == i) ?
|
||||
addr_bank_inc[ICCM_BITS-1 : ICCM_BANK_INDEX_LO] :
|
||||
iccm_rw_addr[ICCM_BITS-1 : ICCM_BANK_INDEX_LO]);
|
||||
`ifdef VERILATOR
|
||||
|
||||
el2_ram #(.depth(1<<ICCM_INDEX_BITS), .width(39)) iccm_bank (
|
||||
// Primary ports
|
||||
.ME(iccm_clken[i]),
|
||||
.CLK(clk),
|
||||
.WE(wren_bank[i]),
|
||||
.ADR(addr_bank[i]),
|
||||
.D(iccm_bank_wr_data[i][38:0]),
|
||||
.Q(iccm_bank_dout[i][38:0])
|
||||
|
||||
);
|
||||
`else
|
||||
|
||||
if (ICCM_INDEX_BITS == 6 ) begin : iccm
|
||||
ram_64x39 iccm_bank (
|
||||
// Primary ports
|
||||
.CLK(clk),
|
||||
.ME(iccm_clken[i]),
|
||||
.WE(wren_bank[i]),
|
||||
.ADR(addr_bank[i]),
|
||||
.D(iccm_bank_wr_data[i][38:0]),
|
||||
.Q(iccm_bank_dout[i][38:0])
|
||||
|
||||
);
|
||||
end // block: iccm
|
||||
|
||||
else if (ICCM_INDEX_BITS == 7 ) begin : iccm
|
||||
ram_128x39 iccm_bank (
|
||||
// Primary ports
|
||||
.CLK(clk),
|
||||
.ME(iccm_clken[i]),
|
||||
.WE(wren_bank[i]),
|
||||
.ADR(addr_bank[i]),
|
||||
.D(iccm_bank_wr_data[i][38:0]),
|
||||
.Q(iccm_bank_dout[i][38:0])
|
||||
|
||||
);
|
||||
end // block: iccm
|
||||
|
||||
else if (ICCM_INDEX_BITS == 8 ) begin : iccm
|
||||
ram_256x39 iccm_bank (
|
||||
// Primary ports
|
||||
.CLK(clk),
|
||||
.ME(iccm_clken[i]),
|
||||
.WE(wren_bank[i]),
|
||||
.ADR(addr_bank[i]),
|
||||
.D(iccm_bank_wr_data[i][38:0]),
|
||||
.Q(iccm_bank_dout[i][38:0])
|
||||
|
||||
);
|
||||
end // block: iccm
|
||||
else if (ICCM_INDEX_BITS == 9 ) begin : iccm
|
||||
ram_512x39 iccm_bank (
|
||||
// Primary ports
|
||||
.CLK(clk),
|
||||
.ME(iccm_clken[i]),
|
||||
.WE(wren_bank[i]),
|
||||
.ADR(addr_bank[i]),
|
||||
.D(iccm_bank_wr_data[i][38:0]),
|
||||
.Q(iccm_bank_dout[i][38:0])
|
||||
|
||||
);
|
||||
end // block: iccm
|
||||
else if (ICCM_INDEX_BITS == 10 ) begin : iccm
|
||||
ram_1024x39 iccm_bank (
|
||||
// Primary ports
|
||||
.CLK(clk),
|
||||
.ME(iccm_clken[i]),
|
||||
.WE(wren_bank[i]),
|
||||
.ADR(addr_bank[i]),
|
||||
.D(iccm_bank_wr_data[i][38:0]),
|
||||
.Q(iccm_bank_dout[i][38:0])
|
||||
|
||||
);
|
||||
end // block: iccm
|
||||
else if (ICCM_INDEX_BITS == 11 ) begin : iccm
|
||||
ram_2048x39 iccm_bank (
|
||||
// Primary ports
|
||||
.CLK(clk),
|
||||
.ME(iccm_clken[i]),
|
||||
.WE(wren_bank[i]),
|
||||
.ADR(addr_bank[i]),
|
||||
.D(iccm_bank_wr_data[i][38:0]),
|
||||
.Q(iccm_bank_dout[i][38:0])
|
||||
|
||||
);
|
||||
end // block: iccm
|
||||
else if (ICCM_INDEX_BITS == 12 ) begin : iccm
|
||||
ram_4096x39 iccm_bank (
|
||||
// Primary ports
|
||||
.CLK(clk),
|
||||
.ME(iccm_clken[i]),
|
||||
.WE(wren_bank[i]),
|
||||
.ADR(addr_bank[i]),
|
||||
.D(iccm_bank_wr_data[i][38:0]),
|
||||
.Q(iccm_bank_dout[i][38:0])
|
||||
|
||||
);
|
||||
end // block: iccm
|
||||
else if (ICCM_INDEX_BITS == 13 ) begin : iccm
|
||||
ram_8192x39 iccm_bank (
|
||||
// Primary ports
|
||||
.CLK(clk),
|
||||
.ME(iccm_clken[i]),
|
||||
.WE(wren_bank[i]),
|
||||
.ADR(addr_bank[i]),
|
||||
.D(iccm_bank_wr_data[i][38:0]),
|
||||
.Q(iccm_bank_dout[i][38:0])
|
||||
|
||||
);
|
||||
end // block: iccm
|
||||
else if (ICCM_INDEX_BITS == 14 ) begin : iccm
|
||||
ram_16384x39 iccm_bank (
|
||||
// Primary ports
|
||||
.CLK(clk),
|
||||
.ME(iccm_clken[i]),
|
||||
.WE(wren_bank[i]),
|
||||
.ADR(addr_bank[i]),
|
||||
.D(iccm_bank_wr_data[i][38:0]),
|
||||
.Q(iccm_bank_dout[i][38:0])
|
||||
|
||||
);
|
||||
end // block: iccm
|
||||
else begin : iccm
|
||||
ram_32768x39 iccm_bank (
|
||||
// Primary ports
|
||||
.CLK(clk),
|
||||
.ME(iccm_clken[i]),
|
||||
.WE(wren_bank[i]),
|
||||
.ADR(addr_bank[i]),
|
||||
.D(iccm_bank_wr_data[i][38:0]),
|
||||
.Q(iccm_bank_dout[i][38:0])
|
||||
|
||||
);
|
||||
end // block: iccm
|
||||
`endif
|
||||
|
||||
// match the redundant rows
|
||||
assign sel_red1[i] = (redundant_valid[1] & (((iccm_rw_addr[ICCM_BITS-1:2] == redundant_address[1][ICCM_BITS-1:2]) & (iccm_rw_addr[3:2] == i)) |
|
||||
((addr_bank_inc[ICCM_BITS-1:2]== redundant_address[1][ICCM_BITS-1:2]) & (addr_bank_inc[3:2] == i))));
|
||||
|
||||
assign sel_red0[i] = (redundant_valid[0] & (((iccm_rw_addr[ICCM_BITS-1:2] == redundant_address[0][ICCM_BITS-1:2]) & (iccm_rw_addr[3:2] == i)) |
|
||||
((addr_bank_inc[ICCM_BITS-1:2]== redundant_address[0][ICCM_BITS-1:2]) & (addr_bank_inc[3:2] == i))));
|
||||
|
||||
rvdff #(1) selred0 (.*,
|
||||
.clk(clk),
|
||||
.din(sel_red0[i]),
|
||||
.dout(sel_red0_q[i]));
|
||||
|
||||
rvdff #(1) selred1 (.*,
|
||||
.clk(clk),
|
||||
.din(sel_red1[i]),
|
||||
.dout(sel_red1_q[i]));
|
||||
|
||||
|
||||
// muxing out the memory data with the redundant data if the address matches
|
||||
assign iccm_bank_dout_fn[i][38:0] = ({39{sel_red1_q[i]}} & redundant_data[1][38:0]) |
|
||||
({39{sel_red0_q[i]}} & redundant_data[0][38:0]) |
|
||||
({39{~sel_red0_q[i] & ~sel_red1_q[i]}} & iccm_bank_dout[i][38:0]);
|
||||
|
||||
|
||||
end : mem_bank
|
||||
// This section does the redundancy for tolerating single bit errors
|
||||
// 2x 39 bit data values with address[hi:2] and a valid bit is needed to CAM and sub out the reads/writes to the particular locations
|
||||
// Also a LRU flop is kept to decide which of the redundant element to replace.
|
||||
assign r0_addr_en = ~redundant_lru & iccm_buf_correct_ecc;
|
||||
assign r1_addr_en = redundant_lru & iccm_buf_correct_ecc;
|
||||
assign redundant_lru_en = iccm_buf_correct_ecc | (((|sel_red0[ICCM_NUM_BANKS-1:0]) | (|sel_red1[ICCM_NUM_BANKS-1:0])) & iccm_rden & iccm_correction_state);
|
||||
assign redundant_lru_in = iccm_buf_correct_ecc ? ~redundant_lru : (|sel_red0[ICCM_NUM_BANKS-1:0]) ? 1'b1 : 1'b0;
|
||||
|
||||
rvdffs #() red_lru (.*, // LRU flop for the redundant replacements
|
||||
.clk(clk),
|
||||
.en(redundant_lru_en),
|
||||
.din(redundant_lru_in),
|
||||
.dout(redundant_lru));
|
||||
|
||||
rvdffs #(ICCM_BITS-2) r0_address (.*, // Redundant Row 0 address
|
||||
.clk(clk),
|
||||
.en(r0_addr_en),
|
||||
.din(iccm_rw_addr[ICCM_BITS-1:2]),
|
||||
.dout(redundant_address[0][ICCM_BITS-1:2]));
|
||||
|
||||
rvdffs #(ICCM_BITS-2) r1_address (.*, // Redundant Row 0 address
|
||||
.clk(clk),
|
||||
.en(r1_addr_en),
|
||||
.din(iccm_rw_addr[ICCM_BITS-1:2]),
|
||||
.dout(redundant_address[1][ICCM_BITS-1:2]));
|
||||
|
||||
rvdffs #(1) r0_valid (.*,
|
||||
.clk(clk), // Redundant Row 0 Valid
|
||||
.en(r0_addr_en),
|
||||
.din(1'b1),
|
||||
.dout(redundant_valid[0]));
|
||||
|
||||
rvdffs #(1) r1_valid (.*, // Redundant Row 1 Valid
|
||||
.clk(clk),
|
||||
.en(r1_addr_en),
|
||||
.din(1'b1),
|
||||
.dout(redundant_valid[1]));
|
||||
|
||||
|
||||
|
||||
// We will have to update the Redundant copies in addition to the memory on subsequent writes to this memory location.
|
||||
// The data gets updated on : 1) correction cycle, 2) Future writes - this could be W writes from DMA ( match up till addr[2]) or DW writes ( match till address[3])
|
||||
// The data to pick also depends on the current address[2], size and the addr[2] stored in the address field of the redundant flop. Correction cycle is always W write and the data is splat on both legs, so choosing lower Word
|
||||
|
||||
assign redundant_data0_en = ((iccm_rw_addr[ICCM_BITS-1:3] == redundant_address[0][ICCM_BITS-1:3]) & ((iccm_rw_addr[2] == redundant_address[0][2]) | (iccm_wr_size[1:0] == 2'b11)) & redundant_valid[0] & iccm_wren) |
|
||||
(~redundant_lru & iccm_buf_correct_ecc);
|
||||
|
||||
assign redundant_data0_in[38:0] = (((iccm_rw_addr[2] == redundant_address[0][2]) & iccm_rw_addr[2]) | (redundant_address[0][2] & (iccm_wr_size[1:0] == 2'b11))) ? iccm_wr_data[77:39] : iccm_wr_data[38:0];
|
||||
|
||||
rvdffs #(39) r0_data (.*, // Redundant Row 1 data
|
||||
.clk(clk),
|
||||
.en(redundant_data0_en),
|
||||
.din(redundant_data0_in[38:0]),
|
||||
.dout(redundant_data[0][38:0]));
|
||||
|
||||
assign redundant_data1_en = ((iccm_rw_addr[ICCM_BITS-1:3] == redundant_address[1][ICCM_BITS-1:3]) & ((iccm_rw_addr[2] == redundant_address[1][2]) | (iccm_wr_size[1:0] == 2'b11)) & redundant_valid[1] & iccm_wren) |
|
||||
(redundant_lru & iccm_buf_correct_ecc);
|
||||
|
||||
assign redundant_data1_in[38:0] = (((iccm_rw_addr[2] == redundant_address[1][2]) & iccm_rw_addr[2]) | (redundant_address[1][2] & (iccm_wr_size[1:0] == 2'b11))) ? iccm_wr_data[77:39] : iccm_wr_data[38:0];
|
||||
|
||||
rvdffs #(39) r1_data (.*, // Redundant Row 1 data
|
||||
.clk(clk),
|
||||
.en(redundant_data1_en),
|
||||
.din(redundant_data1_in[38:0]),
|
||||
.dout(redundant_data[1][38:0]));
|
||||
|
||||
|
||||
rvdffs #(ICCM_BANK_HI) rd_addr_lo_ff (.*, .din(iccm_rw_addr [ICCM_BANK_HI:1]), .dout(iccm_rd_addr_lo_q[ICCM_BANK_HI:1]), .en(1'b1)); // bit 0 of address is always 0
|
||||
rvdffs #(ICCM_BANK_BITS) rd_addr_hi_ff (.*, .din(addr_bank_inc[ICCM_BANK_HI:2]), .dout(iccm_rd_addr_hi_q[ICCM_BANK_HI:2]), .en(1'b1));
|
||||
|
||||
assign iccm_rd_data_pre[63:0] = {iccm_bank_dout_fn[iccm_rd_addr_hi_q][31:0], iccm_bank_dout_fn[iccm_rd_addr_lo_q[ICCM_BANK_HI:2]][31:0]};
|
||||
assign iccm_data[63:0] = 64'({16'b0, (iccm_rd_data_pre[63:0] >> (16*iccm_rd_addr_lo_q[1]))});
|
||||
assign iccm_rd_data[63:0] = {iccm_data[63:0]};
|
||||
assign iccm_rd_data_ecc[77:0] = {iccm_bank_dout_fn[iccm_rd_addr_hi_q][38:0], iccm_bank_dout_fn[iccm_rd_addr_lo_q[ICCM_BANK_HI:2]][38:0]};
|
||||
|
||||
endmodule // el2_ifu_iccm_mem
|
||||
|
|
@ -0,0 +1,235 @@
|
|||
// SPDX-License-Identifier: Apache-2.0
|
||||
// Copyright 2020 Western Digital Corporation or it's affiliates.
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
//********************************************************************************
|
||||
// $Id$
|
||||
//
|
||||
//
|
||||
// Owner:
|
||||
// Function: DCCM for LSU pipe
|
||||
// Comments: Single ported memory
|
||||
//
|
||||
//
|
||||
// DC1 -> DC2 -> DC3 -> DC4 (Commit)
|
||||
//
|
||||
// //********************************************************************************
|
||||
|
||||
|
||||
module el2_lsu_dccm_mem
|
||||
#(
|
||||
parameter DCCM_BYTE_WIDTH,
|
||||
parameter DCCM_BITS,
|
||||
parameter DCCM_NUM_BANKS,
|
||||
parameter DCCM_BANK_BITS,
|
||||
parameter DCCM_SIZE,
|
||||
parameter DCCM_FDATA_WIDTH )(
|
||||
input logic clk, // clock
|
||||
input logic rst_l,
|
||||
input logic clk_override, // clock override
|
||||
|
||||
input logic dccm_wren, // write enable
|
||||
input logic dccm_rden, // read enable
|
||||
input logic [DCCM_BITS-1:0] dccm_wr_addr_lo, // write address
|
||||
input logic [DCCM_BITS-1:0] dccm_wr_addr_hi, // write address
|
||||
input logic [DCCM_BITS-1:0] dccm_rd_addr_lo, // read address
|
||||
input logic [DCCM_BITS-1:0] dccm_rd_addr_hi, // read address for the upper bank in case of a misaligned access
|
||||
input logic [DCCM_FDATA_WIDTH-1:0] dccm_wr_data_lo, // write data
|
||||
input logic [DCCM_FDATA_WIDTH-1:0] dccm_wr_data_hi, // write data
|
||||
|
||||
output logic [DCCM_FDATA_WIDTH-1:0] dccm_rd_data_lo, // read data from the lo bank
|
||||
output logic [DCCM_FDATA_WIDTH-1:0] dccm_rd_data_hi, // read data from the hi bank
|
||||
|
||||
input logic scan_mode
|
||||
);
|
||||
|
||||
|
||||
localparam DCCM_WIDTH_BITS = $clog2(DCCM_BYTE_WIDTH);
|
||||
localparam DCCM_INDEX_BITS = (DCCM_BITS - DCCM_BANK_BITS - DCCM_WIDTH_BITS);
|
||||
localparam DCCM_INDEX_DEPTH = ((DCCM_SIZE)*1024)/((DCCM_BYTE_WIDTH)*(DCCM_NUM_BANKS)); // Depth of memory bank
|
||||
|
||||
logic [DCCM_NUM_BANKS-1:0] wren_bank;
|
||||
logic [DCCM_NUM_BANKS-1:0] rden_bank;
|
||||
logic [DCCM_NUM_BANKS-1:0] [DCCM_BITS-1:(DCCM_BANK_BITS+2)] addr_bank;
|
||||
logic [DCCM_BITS-1:(DCCM_BANK_BITS+DCCM_WIDTH_BITS)] rd_addr_even, rd_addr_odd;
|
||||
logic rd_unaligned, wr_unaligned;
|
||||
logic [DCCM_NUM_BANKS-1:0] [DCCM_FDATA_WIDTH-1:0] dccm_bank_dout;
|
||||
logic [DCCM_FDATA_WIDTH-1:0] wrdata;
|
||||
|
||||
logic [DCCM_NUM_BANKS-1:0][DCCM_FDATA_WIDTH-1:0] wr_data_bank;
|
||||
|
||||
logic [(DCCM_WIDTH_BITS+DCCM_BANK_BITS-1):DCCM_WIDTH_BITS] dccm_rd_addr_lo_q;
|
||||
logic [(DCCM_WIDTH_BITS+DCCM_BANK_BITS-1):DCCM_WIDTH_BITS] dccm_rd_addr_hi_q;
|
||||
|
||||
logic [DCCM_NUM_BANKS-1:0] dccm_clken;
|
||||
|
||||
assign rd_unaligned = (dccm_rd_addr_lo[DCCM_WIDTH_BITS+:DCCM_BANK_BITS] != dccm_rd_addr_hi[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]);
|
||||
assign wr_unaligned = (dccm_wr_addr_lo[DCCM_WIDTH_BITS+:DCCM_BANK_BITS] != dccm_wr_addr_hi[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]);
|
||||
|
||||
// Align the read data
|
||||
assign dccm_rd_data_lo[DCCM_FDATA_WIDTH-1:0] = dccm_bank_dout[dccm_rd_addr_lo_q[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]][DCCM_FDATA_WIDTH-1:0];
|
||||
assign dccm_rd_data_hi[DCCM_FDATA_WIDTH-1:0] = dccm_bank_dout[dccm_rd_addr_hi_q[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]][DCCM_FDATA_WIDTH-1:0];
|
||||
|
||||
// Generate even/odd address
|
||||
|
||||
// 8 Banks, 16KB each (2048 x 72)
|
||||
for (genvar i=0; i<32'(DCCM_NUM_BANKS); i++) begin: mem_bank
|
||||
assign wren_bank[i] = dccm_wren & ((dccm_wr_addr_hi[2+:DCCM_BANK_BITS] == i) | (dccm_wr_addr_lo[2+:DCCM_BANK_BITS] == i));
|
||||
assign rden_bank[i] = dccm_rden & ((dccm_rd_addr_hi[2+:DCCM_BANK_BITS] == i) | (dccm_rd_addr_lo[2+:DCCM_BANK_BITS] == i));
|
||||
assign addr_bank[i][(DCCM_BANK_BITS+DCCM_WIDTH_BITS)+:DCCM_INDEX_BITS] = wren_bank[i] ? (((dccm_wr_addr_hi[2+:DCCM_BANK_BITS] == i) & wr_unaligned) ?
|
||||
dccm_wr_addr_hi[(DCCM_BANK_BITS+DCCM_WIDTH_BITS)+:DCCM_INDEX_BITS] :
|
||||
dccm_wr_addr_lo[(DCCM_BANK_BITS+DCCM_WIDTH_BITS)+:DCCM_INDEX_BITS]) :
|
||||
(((dccm_rd_addr_hi[2+:DCCM_BANK_BITS] == i) & rd_unaligned) ?
|
||||
dccm_rd_addr_hi[(DCCM_BANK_BITS+DCCM_WIDTH_BITS)+:DCCM_INDEX_BITS] :
|
||||
dccm_rd_addr_lo[(DCCM_BANK_BITS+DCCM_WIDTH_BITS)+:DCCM_INDEX_BITS]);
|
||||
|
||||
assign wr_data_bank[i] = ((dccm_wr_addr_hi[2+:DCCM_BANK_BITS] == i) & wr_unaligned) ? dccm_wr_data_hi[DCCM_FDATA_WIDTH-1:0] : dccm_wr_data_lo[DCCM_FDATA_WIDTH-1:0];
|
||||
|
||||
// clock gating section
|
||||
assign dccm_clken[i] = (wren_bank[i] | rden_bank[i] | clk_override) ;
|
||||
// end clock gating section
|
||||
|
||||
`ifdef VERILATOR
|
||||
el2_ram #(DCCM_INDEX_DEPTH,39) ram (
|
||||
// Primary ports
|
||||
.ME(dccm_clken[i]),
|
||||
.CLK(clk),
|
||||
.WE(wren_bank[i]),
|
||||
.ADR(addr_bank[i]),
|
||||
.D(wr_data_bank[i][DCCM_FDATA_WIDTH-1:0]),
|
||||
.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
|
||||
.*
|
||||
);
|
||||
|
||||
`else
|
||||
if (DCCM_INDEX_DEPTH == 32768) begin : dccm
|
||||
ram_32768x39 dccm_bank (
|
||||
// Primary ports
|
||||
.ME(dccm_clken[i]),
|
||||
.CLK(clk),
|
||||
.WE(wren_bank[i]),
|
||||
.ADR(addr_bank[i]),
|
||||
.D(wr_data_bank[i][DCCM_FDATA_WIDTH-1:0]),
|
||||
.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
|
||||
.*
|
||||
);
|
||||
end
|
||||
else if (DCCM_INDEX_DEPTH == 16384) begin : dccm
|
||||
ram_16384x39 dccm_bank (
|
||||
// Primary ports
|
||||
.ME(dccm_clken[i]),
|
||||
.CLK(clk),
|
||||
.WE(wren_bank[i]),
|
||||
.ADR(addr_bank[i]),
|
||||
.D(wr_data_bank[i][DCCM_FDATA_WIDTH-1:0]),
|
||||
.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
|
||||
.*
|
||||
);
|
||||
end
|
||||
else if (DCCM_INDEX_DEPTH == 8192) begin : dccm
|
||||
ram_8192x39 dccm_bank (
|
||||
// Primary ports
|
||||
.ME(dccm_clken[i]),
|
||||
.CLK(clk),
|
||||
.WE(wren_bank[i]),
|
||||
.ADR(addr_bank[i]),
|
||||
.D(wr_data_bank[i][DCCM_FDATA_WIDTH-1:0]),
|
||||
.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
|
||||
.*
|
||||
);
|
||||
end
|
||||
else if (DCCM_INDEX_DEPTH == 4096) begin : dccm
|
||||
ram_4096x39 dccm_bank (
|
||||
// Primary ports
|
||||
.ME(dccm_clken[i]),
|
||||
.CLK(clk),
|
||||
.WE(wren_bank[i]),
|
||||
.ADR(addr_bank[i]),
|
||||
.D(wr_data_bank[i][DCCM_FDATA_WIDTH-1:0]),
|
||||
.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
|
||||
.*
|
||||
);
|
||||
end
|
||||
else if (DCCM_INDEX_DEPTH == 3072) begin : dccm
|
||||
ram_3072x39 dccm_bank (
|
||||
// Primary ports
|
||||
.ME(dccm_clken[i]),
|
||||
.CLK(clk),
|
||||
.WE(wren_bank[i]),
|
||||
.ADR(addr_bank[i]),
|
||||
.D(wr_data_bank[i][DCCM_FDATA_WIDTH-1:0]),
|
||||
.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
|
||||
.*
|
||||
);
|
||||
end
|
||||
else if (DCCM_INDEX_DEPTH == 2048) begin : dccm
|
||||
ram_2048x39 dccm_bank (
|
||||
// Primary ports
|
||||
.ME(dccm_clken[i]),
|
||||
.CLK(clk),
|
||||
.WE(wren_bank[i]),
|
||||
.ADR(addr_bank[i]),
|
||||
.D(wr_data_bank[i][DCCM_FDATA_WIDTH-1:0]),
|
||||
.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
|
||||
.*
|
||||
);
|
||||
end
|
||||
else if (DCCM_INDEX_DEPTH == 1024) begin : dccm
|
||||
ram_1024x39 dccm_bank (
|
||||
// Primary ports
|
||||
.ME(dccm_clken[i]),
|
||||
.CLK(clk),
|
||||
.WE(wren_bank[i]),
|
||||
.ADR(addr_bank[i]),
|
||||
.D(wr_data_bank[i][DCCM_FDATA_WIDTH-1:0]),
|
||||
.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
|
||||
.*
|
||||
);
|
||||
end
|
||||
else if (DCCM_INDEX_DEPTH == 512) begin : dccm
|
||||
ram_512x39 dccm_bank (
|
||||
// Primary ports
|
||||
.ME(dccm_clken[i]),
|
||||
.CLK(clk),
|
||||
.WE(wren_bank[i]),
|
||||
.ADR(addr_bank[i]),
|
||||
.D(wr_data_bank[i][DCCM_FDATA_WIDTH-1:0]),
|
||||
.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
|
||||
.*
|
||||
);
|
||||
end
|
||||
else if (DCCM_INDEX_DEPTH == 256) begin : dccm
|
||||
ram_256x39 dccm_bank (
|
||||
// Primary ports
|
||||
.ME(dccm_clken[i]),
|
||||
.CLK(clk),
|
||||
.WE(wren_bank[i]),
|
||||
.ADR(addr_bank[i]),
|
||||
.D(wr_data_bank[i][DCCM_FDATA_WIDTH-1:0]),
|
||||
.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
|
||||
.*
|
||||
);
|
||||
end
|
||||
`endif // VERILATOR
|
||||
end : mem_bank
|
||||
|
||||
// Flops
|
||||
rvdffs #(DCCM_BANK_BITS) rd_addr_lo_ff (.*, .din(dccm_rd_addr_lo[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]), .dout(dccm_rd_addr_lo_q[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]), .en(1'b1));
|
||||
rvdffs #(DCCM_BANK_BITS) rd_addr_hi_ff (.*, .din(dccm_rd_addr_hi[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]), .dout(dccm_rd_addr_hi_q[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]), .en(1'b1));
|
||||
|
||||
`undef EL2_LOCAL_DCCM_RAM_TEST_PORTS
|
||||
|
||||
endmodule // el2_lsu_dccm_mem
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,169 @@
|
|||
|
||||
module el2_mem #(
|
||||
parameter ICACHE_BEAT_BITS,
|
||||
parameter ICCM_BITS,
|
||||
parameter ICACHE_NUM_WAYS,
|
||||
parameter DCCM_BYTE_WIDTH,
|
||||
parameter ICCM_BANK_INDEX_LO,
|
||||
parameter ICACHE_BANK_BITS,
|
||||
parameter DCCM_BITS,
|
||||
parameter ICACHE_BEAT_ADDR_HI,
|
||||
parameter ICCM_INDEX_BITS,
|
||||
parameter ICCM_BANK_HI,
|
||||
parameter ICACHE_BANKS_WAY,
|
||||
parameter ICACHE_INDEX_HI,
|
||||
parameter DCCM_NUM_BANKS,
|
||||
parameter ICACHE_BANK_HI,
|
||||
parameter ICACHE_BANK_LO,
|
||||
parameter DCCM_ENABLE,
|
||||
parameter ICACHE_TAG_LO,
|
||||
parameter ICACHE_DATA_INDEX_LO,
|
||||
parameter ICCM_NUM_BANKS,
|
||||
parameter ICACHE_ECC,
|
||||
parameter ICACHE_ENABLE,
|
||||
parameter DCCM_BANK_BITS,
|
||||
parameter ICCM_ENABLE,
|
||||
parameter ICCM_BANK_BITS,
|
||||
parameter ICACHE_TAG_DEPTH,
|
||||
parameter ICACHE_WAYPACK,
|
||||
parameter DCCM_SIZE,
|
||||
parameter DCCM_FDATA_WIDTH,
|
||||
parameter ICACHE_TAG_INDEX_LO,
|
||||
parameter ICACHE_DATA_DEPTH)
|
||||
(
|
||||
input logic clk,
|
||||
input logic rst_l,
|
||||
input logic dccm_clk_override,
|
||||
input logic icm_clk_override,
|
||||
input logic dec_tlu_core_ecc_disable,
|
||||
|
||||
//DCCM ports
|
||||
input logic dccm_wren,
|
||||
input logic dccm_rden,
|
||||
input logic [DCCM_BITS-1:0] dccm_wr_addr_lo,
|
||||
input logic [DCCM_BITS-1:0] dccm_wr_addr_hi,
|
||||
input logic [DCCM_BITS-1:0] dccm_rd_addr_lo,
|
||||
input logic [DCCM_BITS-1:0] dccm_rd_addr_hi,
|
||||
input logic [DCCM_FDATA_WIDTH-1:0] dccm_wr_data_lo,
|
||||
input logic [DCCM_FDATA_WIDTH-1:0] dccm_wr_data_hi,
|
||||
|
||||
|
||||
output logic [DCCM_FDATA_WIDTH-1:0] dccm_rd_data_lo,
|
||||
output logic [DCCM_FDATA_WIDTH-1:0] dccm_rd_data_hi,
|
||||
|
||||
//`ifdef DCCM_ENABLE
|
||||
|
||||
//`endif
|
||||
|
||||
//ICCM ports
|
||||
|
||||
input logic [ICCM_BITS-1:1] iccm_rw_addr,
|
||||
input logic iccm_buf_correct_ecc, // ICCM is doing a single bit error correct cycle
|
||||
input logic iccm_correction_state, // ICCM is doing a single bit error correct cycle
|
||||
input logic iccm_wren,
|
||||
input logic iccm_rden,
|
||||
input logic [2:0] iccm_wr_size,
|
||||
input logic [77:0] iccm_wr_data,
|
||||
|
||||
output logic [63:0] iccm_rd_data,
|
||||
output logic [77:0] iccm_rd_data_ecc,
|
||||
|
||||
// Icache and Itag Ports
|
||||
|
||||
input logic [31:1] ic_rw_addr,
|
||||
input logic [ICACHE_NUM_WAYS-1:0] ic_tag_valid,
|
||||
input logic [ICACHE_NUM_WAYS-1:0] ic_wr_en,
|
||||
input logic ic_rd_en,
|
||||
input logic [63:0] ic_premux_data, // Premux data to be muxed with each way of the Icache.
|
||||
input logic ic_sel_premux_data, // Premux data sel
|
||||
|
||||
input logic [ICACHE_BANKS_WAY-1:0][70:0] ic_wr_data, // Data to fill to the Icache. With ECC
|
||||
input logic [70:0] ic_debug_wr_data, // Debug wr cache.
|
||||
output logic [70:0] ic_debug_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
|
||||
input logic [ICACHE_INDEX_HI:3] ic_debug_addr, // Read/Write addresss to the Icache.
|
||||
input logic ic_debug_rd_en, // Icache debug rd
|
||||
input logic ic_debug_wr_en, // Icache debug wr
|
||||
input logic ic_debug_tag_array, // Debug tag array
|
||||
input logic [ICACHE_NUM_WAYS-1:0] ic_debug_way, // Debug way. Rd or Wr.
|
||||
|
||||
output logic [63:0] ic_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC
|
||||
output logic [25:0] ictag_debug_rd_data,// Debug icache tag.
|
||||
|
||||
|
||||
output logic [ICACHE_BANKS_WAY-1:0] ic_eccerr, // ecc error per bank
|
||||
output logic [ICACHE_BANKS_WAY-1:0] ic_parerr, // parity error per bank
|
||||
output logic [ICACHE_NUM_WAYS-1:0] ic_rd_hit,
|
||||
output logic ic_tag_perr, // Icache Tag parity error
|
||||
|
||||
|
||||
input logic scan_mode
|
||||
|
||||
);
|
||||
|
||||
// DCCM Instantiation
|
||||
if (DCCM_ENABLE == 1) begin: Gen_dccm_enable
|
||||
el2_lsu_dccm_mem #(
|
||||
.DCCM_BYTE_WIDTH(DCCM_BYTE_WIDTH),
|
||||
.DCCM_BITS(DCCM_BITS),
|
||||
.DCCM_NUM_BANKS(DCCM_NUM_BANKS),
|
||||
.DCCM_BANK_BITS(DCCM_BANK_BITS),
|
||||
.DCCM_SIZE(DCCM_SIZE),
|
||||
.DCCM_FDATA_WIDTH(DCCM_FDATA_WIDTH)) dccm (
|
||||
.clk_override(dccm_clk_override),
|
||||
.*
|
||||
);
|
||||
end else begin: Gen_dccm_disable
|
||||
assign dccm_rd_data_lo = '0;
|
||||
assign dccm_rd_data_hi = '0;
|
||||
end
|
||||
|
||||
if ( ICACHE_ENABLE ) begin: icache
|
||||
el2_ifu_ic_mem #(
|
||||
.ICACHE_BEAT_BITS(ICACHE_BEAT_BITS),
|
||||
.ICACHE_NUM_WAYS(ICACHE_NUM_WAYS),
|
||||
.ICACHE_BANK_BITS(ICACHE_BANK_BITS),
|
||||
.ICACHE_BEAT_ADDR_HI(ICACHE_BEAT_ADDR_HI),
|
||||
.ICACHE_BANKS_WAY(ICACHE_BANKS_WAY),
|
||||
.ICACHE_INDEX_HI(ICACHE_INDEX_HI),
|
||||
.ICACHE_BANK_HI(ICACHE_BANK_HI),
|
||||
.ICACHE_BANK_LO(ICACHE_BANK_LO),
|
||||
.ICACHE_TAG_LO(ICACHE_TAG_LO),
|
||||
.ICACHE_DATA_INDEX_LO(ICACHE_DATA_INDEX_LO),
|
||||
.ICACHE_ECC(ICACHE_ECC),
|
||||
.ICACHE_TAG_DEPTH(ICACHE_TAG_DEPTH),
|
||||
.ICACHE_WAYPACK(ICACHE_WAYPACK),
|
||||
.ICACHE_TAG_INDEX_LO(ICACHE_TAG_INDEX_LO),
|
||||
.ICACHE_DATA_DEPTH(ICACHE_DATA_DEPTH)) icm (
|
||||
.clk_override(icm_clk_override),
|
||||
.*
|
||||
);
|
||||
end
|
||||
else begin
|
||||
assign ic_rd_hit[ICACHE_NUM_WAYS-1:0] = '0;
|
||||
assign ic_tag_perr = '0 ;
|
||||
assign ic_rd_data = '0 ;
|
||||
assign ictag_debug_rd_data = '0 ;
|
||||
end // else: !if( ICACHE_ENABLE )
|
||||
|
||||
|
||||
|
||||
if (ICCM_ENABLE) begin : iccm
|
||||
el2_ifu_iccm_mem #(
|
||||
.ICCM_BITS(ICCM_BITS),
|
||||
.ICCM_BANK_INDEX_LO(ICCM_BANK_INDEX_LO),
|
||||
.ICCM_INDEX_BITS(ICCM_INDEX_BITS),
|
||||
.ICCM_BANK_HI(ICCM_BANK_HI),
|
||||
.ICCM_NUM_BANKS(ICCM_NUM_BANKS),
|
||||
.ICCM_BANK_BITS(ICCM_BANK_BITS)) iccm (.*,
|
||||
.clk_override(icm_clk_override),
|
||||
.iccm_rw_addr(iccm_rw_addr[ICCM_BITS-1:1]),
|
||||
.iccm_rd_data(iccm_rd_data[63:0])
|
||||
);
|
||||
end
|
||||
else begin
|
||||
assign iccm_rd_data = '0 ;
|
||||
assign iccm_rd_data_ecc = '0 ;
|
||||
end
|
||||
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,705 @@
|
|||
import chisel3._
|
||||
import el2_mem._
|
||||
import chisel3.util._
|
||||
import dmi._
|
||||
import lib._
|
||||
class el2_swerv_wrapper extends Module with el2_lib with RequireAsyncReset {
|
||||
val io = IO(new Bundle{
|
||||
val dbg_rst_l = Input(AsyncReset())
|
||||
val rst_vec = Input(UInt(31.W))
|
||||
val nmi_int = Input(Bool())
|
||||
val nmi_vec = Input(UInt(31.W))
|
||||
val jtag_id = Input(UInt(31.W))
|
||||
|
||||
val trace_rv_i_insn_ip = Output(UInt(32.W))
|
||||
val trace_rv_i_address_ip = Output(UInt(32.W))
|
||||
val trace_rv_i_valid_ip = Output(UInt(2.W))
|
||||
val trace_rv_i_exception_ip = Output(UInt(2.W))
|
||||
val trace_rv_i_ecause_ip = Output(UInt(5.W))
|
||||
val trace_rv_i_interrupt_ip = Output(UInt(2.W))
|
||||
val trace_rv_i_tval_ip = Output(UInt(32.W))
|
||||
|
||||
// AXI Signals
|
||||
val lsu_axi_awvalid = Output(Bool())
|
||||
val lsu_axi_awready = Input(Bool())
|
||||
val lsu_axi_awid = Output(UInt(LSU_BUS_TAG.W))
|
||||
val lsu_axi_awaddr = Output(UInt(32.W))
|
||||
val lsu_axi_awregion = Output(UInt(4.W))
|
||||
val lsu_axi_awlen = Output(UInt(8.W))
|
||||
val lsu_axi_awsize = Output(UInt(3.W))
|
||||
val lsu_axi_awburst = Output(UInt(2.W))
|
||||
val lsu_axi_awlock = Output(Bool())
|
||||
val lsu_axi_awcache = Output(UInt(4.W))
|
||||
val lsu_axi_awprot = Output(UInt(3.W))
|
||||
val lsu_axi_awqos = Output(UInt(4.W))
|
||||
val lsu_axi_wvalid = Output(Bool())
|
||||
val lsu_axi_wready = Input(Bool())
|
||||
val lsu_axi_wdata = Output(UInt(64.W))
|
||||
val lsu_axi_wstrb = Output(UInt(8.W))
|
||||
val lsu_axi_wlast = Output(Bool())
|
||||
|
||||
val lsu_axi_bvalid = Input(Bool())
|
||||
val lsu_axi_bready = Output(Bool())
|
||||
val lsu_axi_bresp = Input(UInt(2.W))
|
||||
val lsu_axi_bid = Input(UInt(LSU_BUS_TAG.W))
|
||||
|
||||
val lsu_axi_arvalid = Output(Bool())
|
||||
val lsu_axi_arready = Input(Bool())
|
||||
val lsu_axi_arid = Output(UInt(LSU_BUS_TAG.W))
|
||||
val lsu_axi_araddr = Output(UInt(32.W))
|
||||
val lsu_axi_arregion = Output(UInt(4.W))
|
||||
val lsu_axi_arlen = Output(UInt(8.W))
|
||||
val lsu_axi_arsize = Output(UInt(3.W))
|
||||
val lsu_axi_arburst = Output(UInt(2.W))
|
||||
val lsu_axi_arlock = Output(Bool())
|
||||
val lsu_axi_arcache = Output(UInt(4.W))
|
||||
val lsu_axi_arprot = Output(UInt(3.W))
|
||||
val lsu_axi_arqos = Output(UInt(4.W))
|
||||
|
||||
val lsu_axi_rvalid = Input(Bool())
|
||||
val lsu_axi_rready = Output(Bool())
|
||||
val lsu_axi_rid = Input(UInt(LSU_BUS_TAG.W))
|
||||
val lsu_axi_rdata = Input(UInt(64.W))
|
||||
val lsu_axi_rresp = Input(UInt(2.W))
|
||||
val lsu_axi_rlast = Input(Bool())
|
||||
|
||||
|
||||
// AXI IFU Signals
|
||||
val ifu_axi_awvalid = Output(Bool())
|
||||
val ifu_axi_awready = Input(Bool())
|
||||
val ifu_axi_awid = Output(UInt(IFU_BUS_TAG.W))
|
||||
val ifu_axi_awaddr = Output(UInt(32.W))
|
||||
val ifu_axi_awregion = Output(UInt(4.W))
|
||||
val ifu_axi_awlen = Output(UInt(8.W))
|
||||
val ifu_axi_awsize = Output(UInt(3.W))
|
||||
val ifu_axi_awburst = Output(UInt(2.W))
|
||||
val ifu_axi_awlock = Output(Bool())
|
||||
val ifu_axi_awcache = Output(UInt(4.W))
|
||||
val ifu_axi_awprot = Output(UInt(3.W))
|
||||
val ifu_axi_awqos = Output(UInt(4.W))
|
||||
|
||||
val ifu_axi_wvalid = Output(Bool())
|
||||
val ifu_axi_wready = Input(Bool())
|
||||
val ifu_axi_wdata = Output(UInt(64.W))
|
||||
val ifu_axi_wstrb = Output(UInt(8.W))
|
||||
val ifu_axi_wlast = Output(Bool())
|
||||
|
||||
val ifu_axi_bvalid = Input(Bool())
|
||||
val ifu_axi_bready = Output(Bool())
|
||||
val ifu_axi_bresp = Input(UInt(2.W))
|
||||
val ifu_axi_bid = Input(UInt(IFU_BUS_TAG.W))
|
||||
|
||||
val ifu_axi_arvalid = Output(Bool())
|
||||
val ifu_axi_arready = Input(Bool())
|
||||
val ifu_axi_arid = Output(UInt(IFU_BUS_TAG.W))
|
||||
val ifu_axi_araddr = Output(UInt(32.W))
|
||||
val ifu_axi_arregion = Output(UInt(4.W))
|
||||
val ifu_axi_arlen = Output(UInt(8.W))
|
||||
val ifu_axi_arsize = Output(UInt(3.W))
|
||||
val ifu_axi_arburst = Output(UInt(2.W))
|
||||
val ifu_axi_arlock = Output(Bool())
|
||||
val ifu_axi_arcache = Output(UInt(4.W))
|
||||
val ifu_axi_arprot = Output(UInt(3.W))
|
||||
val ifu_axi_arqos = Output(UInt(4.W))
|
||||
|
||||
val ifu_axi_rvalid = Input(Bool())
|
||||
val ifu_axi_rready = Output(Bool())
|
||||
val ifu_axi_rid = Input(UInt(IFU_BUS_TAG.W))
|
||||
val ifu_axi_rdata = Input(UInt(64.W))
|
||||
val ifu_axi_rresp = Input(UInt(2.W))
|
||||
val ifu_axi_rlast = Input(Bool())
|
||||
|
||||
// SB AXI Signals
|
||||
val sb_axi_awvalid = Output(Bool())
|
||||
val sb_axi_awready = Input(Bool())
|
||||
val sb_axi_awid = Output(UInt(SB_BUS_TAG.W))
|
||||
val sb_axi_awaddr = Output(UInt(32.W))
|
||||
val sb_axi_awregion = Output(UInt(4.W))
|
||||
val sb_axi_awlen = Output(UInt(8.W))
|
||||
val sb_axi_awsize = Output(UInt(3.W))
|
||||
val sb_axi_awburst = Output(UInt(2.W))
|
||||
val sb_axi_awlock = Output(Bool())
|
||||
val sb_axi_awcache = Output(UInt(4.W))
|
||||
val sb_axi_awprot = Output(UInt(3.W))
|
||||
val sb_axi_awqos = Output(UInt(4.W))
|
||||
|
||||
val sb_axi_wvalid = Output(Bool())
|
||||
val sb_axi_wready = Input(Bool())
|
||||
val sb_axi_wdata = Output(UInt(64.W))
|
||||
val sb_axi_wstrb = Output(UInt(8.W))
|
||||
val sb_axi_wlast = Output(Bool())
|
||||
|
||||
val sb_axi_bvalid = Input(Bool())
|
||||
val sb_axi_bready = Output(Bool())
|
||||
val sb_axi_bresp = Input(UInt(2.W))
|
||||
val sb_axi_bid = Input(UInt(SB_BUS_TAG.W))
|
||||
|
||||
val sb_axi_arvalid = Output(Bool())
|
||||
val sb_axi_arready = Input(Bool())
|
||||
val sb_axi_arid = Output(UInt(SB_BUS_TAG.W))
|
||||
val sb_axi_araddr = Output(UInt(32.W))
|
||||
val sb_axi_arregion = Output(UInt(4.W))
|
||||
val sb_axi_arlen = Output(UInt(8.W))
|
||||
val sb_axi_arsize = Output(UInt(3.W))
|
||||
val sb_axi_arburst = Output(UInt(2.W))
|
||||
val sb_axi_arlock = Output(Bool())
|
||||
val sb_axi_arcache = Output(UInt(4.W))
|
||||
val sb_axi_arprot = Output(UInt(3.W))
|
||||
val sb_axi_arqos = Output(UInt(4.W))
|
||||
|
||||
val sb_axi_rvalid = Input(Bool())
|
||||
val sb_axi_rready = Output(Bool())
|
||||
val sb_axi_rid = Input(UInt(SB_BUS_TAG.W))
|
||||
val sb_axi_rdata = Input(UInt(64.W))
|
||||
val sb_axi_rresp = Input(UInt(2.W))
|
||||
val sb_axi_rlast = Input(Bool())
|
||||
|
||||
// DMA signals
|
||||
val dma_axi_awvalid = Input(Bool())
|
||||
val dma_axi_awready = Output(Bool())
|
||||
val dma_axi_awid = Input(UInt(DMA_BUS_TAG.W))
|
||||
val dma_axi_awaddr = Input(UInt(32.W))
|
||||
val dma_axi_awsize = Input(UInt(3.W))
|
||||
val dma_axi_awprot = Input(UInt(3.W))
|
||||
val dma_axi_awlen = Input(UInt(8.W))
|
||||
val dma_axi_awburst = Input(UInt(2.W))
|
||||
|
||||
val dma_axi_wvalid = Input(Bool())
|
||||
val dma_axi_wready = Output(Bool())
|
||||
val dma_axi_wdata = Input(UInt(64.W))
|
||||
val dma_axi_wstrb = Input(UInt(8.W))
|
||||
val dma_axi_wlast = Input(Bool())
|
||||
|
||||
val dma_axi_bvalid = Output(Bool())
|
||||
val dma_axi_bready = Input(Bool())
|
||||
val dma_axi_bresp = Output(UInt(2.W))
|
||||
val dma_axi_bid = Output(UInt(DMA_BUS_TAG.W))
|
||||
|
||||
// AXI Read Channels
|
||||
val dma_axi_arvalid = Input(Bool())
|
||||
val dma_axi_arready = Output(Bool())
|
||||
val dma_axi_arid = Input(UInt(DMA_BUS_TAG.W))
|
||||
val dma_axi_araddr = Input(UInt(32.W))
|
||||
val dma_axi_arsize = Input(UInt(3.W))
|
||||
val dma_axi_arprot = Input(UInt(3.W))
|
||||
val dma_axi_arlen = Input(UInt(8.W))
|
||||
val dma_axi_arburst = Input(UInt(2.W))
|
||||
|
||||
val dma_axi_rvalid = Output(Bool())
|
||||
val dma_axi_rready = Input(Bool())
|
||||
val dma_axi_rid = Output(UInt(DMA_BUS_TAG.W))
|
||||
val dma_axi_rdata = Output(UInt(64.W))
|
||||
val dma_axi_rresp = Output(UInt(2.W))
|
||||
val dma_axi_rlast = Output(Bool())
|
||||
|
||||
// AHB Lite Bus
|
||||
// val haddr = Output(UInt(32.W))
|
||||
// val hburst = Output(UInt(3.W))
|
||||
// val hmastlock = Output(Bool())
|
||||
// val hprot = Output(UInt(4.W))
|
||||
// val hsize = Output(UInt(3.W))
|
||||
// val htrans = Output(UInt(2.W))
|
||||
// val hwrite = Output(Bool())
|
||||
// val hrdata = Input(UInt(64.W))
|
||||
// val hready = Input(Bool())
|
||||
// val hresp = Input(Bool())
|
||||
//
|
||||
// // AHB Master
|
||||
// val lsu_haddr = Output(UInt(32.W))
|
||||
// val lsu_hburst = Output(UInt(3.W))
|
||||
// val lsu_hmastlock = Output(Bool())
|
||||
// val lsu_hprot = Output(UInt(4.W))
|
||||
// val lsu_hsize = Output(UInt(3.W))
|
||||
// val lsu_htrans = Output(UInt(2.W))
|
||||
// val lsu_hwrite = Output(Bool())
|
||||
// val lsu_hwdata = Output(UInt(64.W))
|
||||
// val lsu_hrdata = Input(UInt(64.W))
|
||||
// val lsu_hready = Input(Bool())
|
||||
// val lsu_hresp = Input(Bool())
|
||||
|
||||
// System Bus Debug Master
|
||||
// val sb_haddr = Output(UInt(32.W))
|
||||
// val sb_hburst = Output(UInt(3.W))
|
||||
// val sb_hmastlock = Output(Bool())
|
||||
// val sb_hprot = Output(UInt(4.W))
|
||||
// val sb_hsize = Output(UInt(3.W))
|
||||
// val sb_htrans = Output(UInt(2.W))
|
||||
// val sb_hwrite = Output(Bool())
|
||||
// val sb_hwdata = Output(UInt(64.W))
|
||||
// val sb_hrdata = Input(UInt(64.W))
|
||||
// val sb_hready = Input(Bool())
|
||||
// val sb_hresp = Input(Bool())
|
||||
|
||||
// DMA slave
|
||||
val dma_hsel = Input(Bool())
|
||||
val dma_haddr = Input(UInt(32.W))
|
||||
val dma_hburst = Input(UInt(3.W))
|
||||
val dma_hmastlock = Input(Bool())
|
||||
val dma_hprot = Input(UInt(4.W))
|
||||
val dma_hsize = Input(UInt(3.W))
|
||||
val dma_htrans = Input(UInt(2.W))
|
||||
val dma_hwrite = Input(Bool())
|
||||
val dma_hwdata = Input(UInt(64.W))
|
||||
val dma_hreadyin = Input(Bool())
|
||||
val dma_hrdata = Output(UInt(64.W))
|
||||
val dma_hreadyout = Output(Bool())
|
||||
val dma_hresp = Output(Bool())
|
||||
|
||||
val lsu_bus_clk_en = Input(Bool())
|
||||
val ifu_bus_clk_en = Input(Bool())
|
||||
val dbg_bus_clk_en = Input(Bool())
|
||||
val dma_bus_clk_en = Input(Bool())
|
||||
|
||||
val timer_int = Input(Bool())
|
||||
val soft_int = Input(Bool())
|
||||
|
||||
val extintsrc_req = Input(UInt(PIC_TOTAL_INT.W))
|
||||
|
||||
val dec_tlu_perfcnt0 = Output(Bool())
|
||||
val dec_tlu_perfcnt1 = Output(Bool())
|
||||
val dec_tlu_perfcnt2 = Output(Bool())
|
||||
val dec_tlu_perfcnt3 = Output(Bool())
|
||||
|
||||
val jtag_tck = Input(Clock())
|
||||
val jtag_tms = Input(Bool())
|
||||
val jtag_tdi = Input(Bool())
|
||||
val jtag_trst_n = Input(Bool())
|
||||
val jtag_tdo = Output(Bool())
|
||||
|
||||
val core_id = Input(UInt(28.W))
|
||||
|
||||
val mpc_debug_halt_req = Input(Bool())
|
||||
val mpc_debug_run_req = Input(Bool())
|
||||
val mpc_reset_run_req = Input(Bool())
|
||||
val mpc_debug_halt_ack = Output(Bool())
|
||||
val mpc_debug_run_ack = Output(Bool())
|
||||
val debug_brkpt_status = Output(Bool())
|
||||
|
||||
val i_cpu_halt_req = Input(Bool())
|
||||
val i_cpu_run_req = Input(Bool())
|
||||
val o_cpu_halt_ack = Output(Bool())
|
||||
val o_cpu_halt_status = Output(Bool())
|
||||
val o_debug_mode_status = Output(Bool())
|
||||
val o_cpu_run_ack = Output(Bool())
|
||||
val mbist_mode = Input(Bool())
|
||||
|
||||
val scan_mode = Input(Bool())
|
||||
|
||||
// AHB signals
|
||||
/*val haddr = Output(UInt(32.W))
|
||||
val hburst = Output(UInt(3.W))
|
||||
val hmastlock = Output(Bool())
|
||||
val hprot = Output(UInt(4.W))
|
||||
val hsize = Output(UInt(3.W))
|
||||
val htrans = Output(UInt(2.W))
|
||||
val hwrite = Output(Bool())
|
||||
|
||||
val hrdata = Input(UInt(64.W))
|
||||
val hready = Input(Bool())
|
||||
val hresp = Input(Bool())
|
||||
|
||||
// LSU AHB Master
|
||||
val lsu_haddr = Output(UInt(32.W))
|
||||
val lsu_hburst = Output(UInt(3.W))
|
||||
val lsu_hmastlock = Output(Bool())
|
||||
val lsu_hprot = Output(UInt(4.W))
|
||||
val lsu_hsize = Output(UInt(3.W))
|
||||
val lsu_htrans = Output(UInt(2.W))
|
||||
val lsu_hwrite = Output(Bool())
|
||||
val lsu_hwdata = Output(UInt(64.W))
|
||||
|
||||
val lsu_hrdata = Input(UInt(64.W))
|
||||
val lsu_hready = Input(Bool())
|
||||
val lsu_hresp = Input(Bool())
|
||||
// Debug Syster Bus AHB
|
||||
val sb_haddr = Output(UInt(32.W))
|
||||
val sb_hburst = Output(UInt(3.W))
|
||||
val sb_hmastlock = Output(Bool())
|
||||
val sb_hprot = Output(UInt(4.W))
|
||||
val sb_hsize = Output(UInt(3.W))
|
||||
val sb_htrans = Output(UInt(2.W))
|
||||
val sb_hwrite = Output(Bool())
|
||||
val sb_hwdata = Output(UInt(64.W))
|
||||
|
||||
val sb_hrdata = Input(UInt(64.W))
|
||||
val sb_hready = Input(Bool())
|
||||
val sb_hresp = Input(Bool())
|
||||
|
||||
// DMA Slave
|
||||
val dma_hsel = Input(Bool())
|
||||
val dma_haddr = Input(UInt(32.W))
|
||||
val dma_hburst = Input(UInt(3.W))
|
||||
val dma_hmastlock = Input(Bool())
|
||||
val dma_hprot = Input(UInt(4.W))
|
||||
val dma_hsize = Input(UInt(3.W))
|
||||
val dma_htrans = Input(UInt(2.W))
|
||||
val dma_hwrite = Input(Bool())
|
||||
val dma_hwdata = Input(UInt(64.W))
|
||||
val dma_hreadyin = Input(Bool())
|
||||
|
||||
val dma_hrdata = Output(UInt(64.W))
|
||||
val dma_hreadyout = Output(Bool())
|
||||
val dma_hresp = Output(Bool())
|
||||
*/
|
||||
})
|
||||
val mem = Module(new waleed.el2_mem())
|
||||
val dmi_wrapper = Module(new dmi_wrapper())
|
||||
val swerv = Module(new el2_swerv())
|
||||
dmi_wrapper.io.trst_n := io.jtag_trst_n
|
||||
dmi_wrapper.io.tck := io.jtag_tck
|
||||
dmi_wrapper.io.tms := io.jtag_tms
|
||||
dmi_wrapper.io.tdi := io.jtag_tdi
|
||||
dmi_wrapper.io.core_clk := clock
|
||||
dmi_wrapper.io.jtag_id := io.jtag_id
|
||||
dmi_wrapper.io.rd_data := swerv.io.dmi_reg_rdata
|
||||
|
||||
|
||||
dmi_wrapper.io.core_rst_n := io.dbg_rst_l
|
||||
swerv.io.dmi_reg_wdata := dmi_wrapper.io.reg_wr_data
|
||||
swerv.io.dmi_reg_addr := dmi_wrapper.io.reg_wr_addr
|
||||
swerv.io.dmi_reg_en := dmi_wrapper.io.reg_en
|
||||
swerv.io.dmi_reg_wr_en := dmi_wrapper.io.reg_wr_en
|
||||
swerv.io.dmi_hard_reset := dmi_wrapper.io.dmi_hard_reset
|
||||
io.jtag_tdo := dmi_wrapper.io.tdo
|
||||
|
||||
// Memory signals
|
||||
mem.io.dccm_clk_override := swerv.io.dccm_clk_override
|
||||
mem.io.icm_clk_override := swerv.io.icm_clk_override
|
||||
mem.io.dec_tlu_core_ecc_disable := swerv.io.dec_tlu_core_ecc_disable
|
||||
mem.io.dccm_wren := swerv.io.dccm_wren
|
||||
mem.io.dccm_rden := swerv.io.dccm_rden
|
||||
mem.io.dccm_wr_addr_lo := swerv.io.dccm_wr_addr_lo
|
||||
mem.io.dccm_wr_addr_hi := swerv.io.dccm_wr_addr_hi
|
||||
mem.io.dccm_rd_addr_lo := swerv.io.dccm_rd_addr_lo
|
||||
|
||||
mem.io.dccm_wr_data_lo := swerv.io.dccm_wr_data_lo
|
||||
mem.io.dccm_wr_data_hi := swerv.io.dccm_wr_data_hi
|
||||
swerv.io.dccm_rd_data_lo := mem.io.dccm_rd_data_lo
|
||||
mem.io.dccm_rd_addr_hi := swerv.io.dccm_rd_addr_hi
|
||||
mem.io.iccm_rw_addr := swerv.io.iccm_rw_addr
|
||||
mem.io.iccm_buf_correct_ecc := swerv.io.iccm_buf_correct_ecc
|
||||
mem.io.iccm_correction_state := swerv.io.iccm_correction_state
|
||||
mem.io.iccm_wren := swerv.io.iccm_wren
|
||||
mem.io.iccm_rden := swerv.io.iccm_rden
|
||||
mem.io.iccm_wr_size := swerv.io.iccm_wr_size
|
||||
mem.io.iccm_wr_data := swerv.io.iccm_wr_data
|
||||
|
||||
|
||||
mem.io.ic_rw_addr := swerv.io.ic_rw_addr
|
||||
mem.io.ic_tag_valid := swerv.io.ic_tag_valid
|
||||
mem.io.ic_wr_en := swerv.io.ic_wr_en
|
||||
mem.io.ic_rd_en := swerv.io.ic_rd_en
|
||||
mem.io.ic_premux_data := swerv.io.ic_premux_data
|
||||
mem.io.ic_sel_premux_data := swerv.io.ic_sel_premux_data
|
||||
mem.io.ic_wr_data := swerv.io.ic_wr_data
|
||||
mem.io.ic_debug_wr_data := swerv.io.ic_debug_wr_data
|
||||
|
||||
mem.io.ic_debug_addr := swerv.io.ic_debug_addr
|
||||
mem.io.ic_debug_rd_en := swerv.io.ic_debug_rd_en
|
||||
mem.io.ic_debug_wr_en := swerv.io.ic_debug_wr_en
|
||||
mem.io.ic_debug_tag_array := swerv.io.ic_debug_tag_array
|
||||
mem.io.ic_debug_way := swerv.io.ic_debug_way
|
||||
mem.io.rst_l := reset
|
||||
mem.io.clk := clock
|
||||
mem.io.scan_mode := io.scan_mode
|
||||
// Memory outputs
|
||||
swerv.io.dbg_rst_l := io.dbg_rst_l
|
||||
swerv.io.iccm_rd_data_ecc := mem.io.iccm_rd_data_ecc
|
||||
swerv.io.dccm_rd_data_hi := mem.io.dccm_rd_data_hi
|
||||
swerv.io.ic_rd_data := mem.io.ic_rd_data
|
||||
swerv.io.ictag_debug_rd_data := mem.io.ictag_debug_rd_data
|
||||
swerv.io.ic_eccerr := mem.io.ic_eccerr
|
||||
swerv.io.ic_parerr := mem.io.ic_parerr
|
||||
swerv.io.ic_rd_hit := mem.io.ic_rd_hit
|
||||
swerv.io.ic_tag_perr := mem.io.ic_tag_perr
|
||||
swerv.io.ic_debug_rd_data := mem.io.ic_debug_rd_data
|
||||
swerv.io.iccm_rd_data := mem.io.iccm_rd_data
|
||||
swerv.io.sb_hready := 0.U
|
||||
swerv.io.hrdata := 0.U
|
||||
swerv.io.sb_hresp := 0.U
|
||||
swerv.io.lsu_hrdata := 0.U
|
||||
swerv.io.lsu_hresp := 0.U
|
||||
swerv.io.lsu_hready := 0.U
|
||||
swerv.io.hready := 0.U
|
||||
swerv.io.hresp := 0.U
|
||||
swerv.io.sb_hrdata := 0.U
|
||||
swerv.io.scan_mode := io.scan_mode
|
||||
// SweRV Inputs
|
||||
swerv.io.dbg_rst_l := io.dbg_rst_l
|
||||
swerv.io.rst_vec := io.rst_vec
|
||||
swerv.io.nmi_int := io.nmi_int
|
||||
swerv.io.nmi_vec := io.nmi_vec
|
||||
|
||||
// external halt/run interface
|
||||
swerv.io.i_cpu_halt_req := io.i_cpu_halt_req
|
||||
swerv.io.i_cpu_run_req := io.i_cpu_run_req
|
||||
swerv.io.core_id := io.core_id
|
||||
|
||||
// external MPC halt/run interface
|
||||
swerv.io.mpc_debug_halt_req := io.mpc_debug_halt_req
|
||||
swerv.io.mpc_debug_run_req := io.mpc_debug_run_req
|
||||
swerv.io.mpc_reset_run_req := io.mpc_reset_run_req
|
||||
|
||||
//-------------------------- LSU AXI signals--------------------------
|
||||
// AXI Write Channels
|
||||
swerv.io.lsu_axi_awready := io.lsu_axi_awready
|
||||
swerv.io.lsu_axi_wready := io.lsu_axi_wready
|
||||
|
||||
swerv.io.lsu_axi_bvalid := io.lsu_axi_bvalid
|
||||
swerv.io.lsu_axi_bresp := io.lsu_axi_bresp
|
||||
swerv.io.lsu_axi_bid := io.lsu_axi_bid
|
||||
|
||||
// AXI Read Channels
|
||||
swerv.io.lsu_axi_arready := io.lsu_axi_arready
|
||||
swerv.io.lsu_axi_rvalid := io.lsu_axi_rvalid
|
||||
swerv.io.lsu_axi_rid := io.lsu_axi_rid
|
||||
swerv.io.lsu_axi_rdata := io.lsu_axi_rdata
|
||||
swerv.io.lsu_axi_rresp := io.lsu_axi_rresp
|
||||
swerv.io.lsu_axi_rlast := io.lsu_axi_rlast
|
||||
|
||||
//-------------------------- IFU AXI signals--------------------------
|
||||
// AXI Write Channels
|
||||
swerv.io.ifu_axi_awready := io.ifu_axi_awready
|
||||
swerv.io.ifu_axi_wready := io.ifu_axi_wready
|
||||
swerv.io.ifu_axi_bvalid := io.ifu_axi_bvalid
|
||||
swerv.io.ifu_axi_bresp := io.ifu_axi_bresp
|
||||
swerv.io.ifu_axi_bid := io.ifu_axi_bid
|
||||
|
||||
// AXI Read Channels
|
||||
swerv.io.ifu_axi_arready := io.ifu_axi_arready
|
||||
swerv.io.ifu_axi_rvalid := io.ifu_axi_rvalid
|
||||
swerv.io.ifu_axi_rid := io.ifu_axi_rid
|
||||
swerv.io.ifu_axi_rdata := io.ifu_axi_rdata
|
||||
swerv.io.ifu_axi_rresp := io.ifu_axi_rresp
|
||||
swerv.io.ifu_axi_rlast := io.ifu_axi_rlast
|
||||
|
||||
//-------------------------- SB AXI signals--------------------------
|
||||
// AXI Write Channels
|
||||
swerv.io.sb_axi_awready := io.sb_axi_awready
|
||||
swerv.io.sb_axi_wready := io.sb_axi_wready
|
||||
|
||||
swerv.io.sb_axi_bvalid := io.sb_axi_bvalid
|
||||
swerv.io.sb_axi_bresp := io.sb_axi_bresp
|
||||
swerv.io.sb_axi_bid := io.sb_axi_bid
|
||||
|
||||
// AXI Read Channels
|
||||
swerv.io.sb_axi_arready := io.sb_axi_arready
|
||||
swerv.io.sb_axi_rvalid := io.sb_axi_rvalid
|
||||
swerv.io.sb_axi_rid := io.sb_axi_rid
|
||||
swerv.io.sb_axi_rdata := io.sb_axi_rdata
|
||||
swerv.io.sb_axi_rresp := io.sb_axi_rresp
|
||||
swerv.io.sb_axi_rlast := io.sb_axi_rlast
|
||||
|
||||
//-------------------------- DMA AXI signals--------------------------
|
||||
// AXI Write Channels
|
||||
swerv.io.dma_axi_awvalid := io.dma_axi_awvalid
|
||||
swerv.io.dma_axi_awid := io.dma_axi_awid
|
||||
swerv.io.dma_axi_awaddr := io.dma_axi_awaddr
|
||||
swerv.io.dma_axi_awsize := io.dma_axi_awsize
|
||||
swerv.io.dma_axi_awprot := io.dma_axi_awprot
|
||||
swerv.io.dma_axi_awlen := io.dma_axi_awlen
|
||||
swerv.io.dma_axi_awburst := io.dma_axi_awburst
|
||||
|
||||
swerv.io.dma_axi_wvalid := io.dma_axi_wvalid
|
||||
swerv.io.dma_axi_wdata := io.dma_axi_wdata
|
||||
swerv.io.dma_axi_wstrb := io.dma_axi_wstrb
|
||||
swerv.io.dma_axi_wlast := io.dma_axi_wlast
|
||||
swerv.io.dma_axi_bready := io.dma_axi_bready
|
||||
|
||||
// AXI Read Channels
|
||||
swerv.io.dma_axi_arvalid := io.dma_axi_arvalid
|
||||
swerv.io.dma_axi_arid := io.dma_axi_arid
|
||||
swerv.io.dma_axi_araddr := io.dma_axi_araddr
|
||||
swerv.io.dma_axi_arsize := io.dma_axi_arsize
|
||||
swerv.io.dma_axi_arprot := io.dma_axi_arprot
|
||||
swerv.io.dma_axi_arlen := io.dma_axi_arlen
|
||||
swerv.io.dma_axi_arburst := io.dma_axi_arburst
|
||||
swerv.io.dma_axi_rready := io.dma_axi_rready
|
||||
|
||||
// DMA Slave
|
||||
swerv.io.dma_hsel := io.dma_hsel
|
||||
swerv.io.dma_haddr := io.dma_haddr
|
||||
swerv.io.dma_hburst := io.dma_hburst
|
||||
swerv.io.dma_hmastlock := io.dma_hmastlock
|
||||
swerv.io.dma_hprot := io.dma_hprot
|
||||
swerv.io.dma_hsize := io.dma_hsize
|
||||
swerv.io.dma_htrans := io.dma_htrans
|
||||
swerv.io.dma_hwrite := io.dma_hwrite
|
||||
swerv.io.dma_hwdata := io.dma_hwdata
|
||||
swerv.io.dma_hreadyin := io.dma_hreadyin
|
||||
|
||||
swerv.io.lsu_bus_clk_en
|
||||
swerv.io.ifu_bus_clk_en
|
||||
swerv.io.dbg_bus_clk_en
|
||||
swerv.io.dma_bus_clk_en
|
||||
|
||||
swerv.io.dmi_reg_en
|
||||
swerv.io.dmi_reg_addr
|
||||
swerv.io.dmi_reg_wr_en
|
||||
swerv.io.dmi_reg_wdata
|
||||
swerv.io.dmi_hard_reset
|
||||
|
||||
swerv.io.extintsrc_req
|
||||
swerv.io.timer_int
|
||||
swerv.io.soft_int
|
||||
swerv.io.scan_mode
|
||||
|
||||
swerv.io.lsu_bus_clk_en := io.lsu_bus_clk_en
|
||||
swerv.io.ifu_bus_clk_en := io.ifu_bus_clk_en
|
||||
swerv.io.dbg_bus_clk_en := io.dbg_bus_clk_en
|
||||
swerv.io.dma_bus_clk_en := io.dma_bus_clk_en
|
||||
|
||||
swerv.io.timer_int := io.timer_int
|
||||
swerv.io.soft_int := io.soft_int
|
||||
swerv.io.extintsrc_req := io.extintsrc_req
|
||||
|
||||
// Outputs
|
||||
val core_rst_l = swerv.io.core_rst_l
|
||||
io.trace_rv_i_insn_ip := swerv.io.trace_rv_i_insn_ip
|
||||
io.trace_rv_i_address_ip := swerv.io.trace_rv_i_address_ip
|
||||
io.trace_rv_i_valid_ip := swerv.io.trace_rv_i_valid_ip
|
||||
io.trace_rv_i_exception_ip := swerv.io.trace_rv_i_exception_ip
|
||||
io.trace_rv_i_ecause_ip := swerv.io.trace_rv_i_ecause_ip
|
||||
io.trace_rv_i_interrupt_ip := swerv.io.trace_rv_i_interrupt_ip
|
||||
io.trace_rv_i_tval_ip := swerv.io.trace_rv_i_tval_ip
|
||||
|
||||
// external halt/run interface
|
||||
io.o_cpu_halt_ack := swerv.io.o_cpu_halt_ack
|
||||
io.o_cpu_halt_status := swerv.io.o_cpu_halt_status
|
||||
io.o_cpu_run_ack := swerv.io.o_cpu_run_ack
|
||||
io.o_debug_mode_status := swerv.io.o_debug_mode_status
|
||||
|
||||
io.mpc_debug_halt_ack := swerv.io.mpc_debug_halt_ack
|
||||
io.mpc_debug_run_ack := swerv.io.mpc_debug_run_ack
|
||||
io.debug_brkpt_status := swerv.io.debug_brkpt_status
|
||||
|
||||
io.dec_tlu_perfcnt0 := swerv.io.dec_tlu_perfcnt0
|
||||
io.dec_tlu_perfcnt1 := swerv.io.dec_tlu_perfcnt1
|
||||
io.dec_tlu_perfcnt2 := swerv.io.dec_tlu_perfcnt2
|
||||
io.dec_tlu_perfcnt3 := swerv.io.dec_tlu_perfcnt3
|
||||
|
||||
|
||||
//-------------------------- LSU AXI signals--------------------------
|
||||
// AXI Write Channels
|
||||
io.lsu_axi_awvalid := swerv.io.lsu_axi_awvalid
|
||||
io.lsu_axi_awid := swerv.io.lsu_axi_awid
|
||||
io.lsu_axi_awaddr := swerv.io.lsu_axi_awaddr
|
||||
io.lsu_axi_awregion := swerv.io.lsu_axi_awregion
|
||||
io.lsu_axi_awlen := swerv.io.lsu_axi_awlen
|
||||
io.lsu_axi_awsize := swerv.io.lsu_axi_awsize
|
||||
io.lsu_axi_awburst := swerv.io.lsu_axi_awburst
|
||||
io.lsu_axi_awlock := swerv.io.lsu_axi_awlock
|
||||
io.lsu_axi_awcache := swerv.io.lsu_axi_awcache
|
||||
io.lsu_axi_awprot := swerv.io.lsu_axi_awprot
|
||||
io.lsu_axi_awqos := swerv.io.lsu_axi_awqos
|
||||
|
||||
io.lsu_axi_wvalid := swerv.io.lsu_axi_wvalid
|
||||
io.lsu_axi_wdata := swerv.io.lsu_axi_wdata
|
||||
io.lsu_axi_wstrb := swerv.io.lsu_axi_wstrb
|
||||
io.lsu_axi_wlast := swerv.io.lsu_axi_wlast
|
||||
io.lsu_axi_bready := swerv.io.lsu_axi_bready
|
||||
|
||||
// AXI Read Channels
|
||||
io.lsu_axi_arvalid := swerv.io.lsu_axi_arvalid
|
||||
io.lsu_axi_arid := swerv.io.lsu_axi_arid
|
||||
io.lsu_axi_araddr := swerv.io.lsu_axi_araddr
|
||||
io.lsu_axi_arregion := swerv.io.lsu_axi_arregion
|
||||
io.lsu_axi_arlen := swerv.io.lsu_axi_arlen
|
||||
io.lsu_axi_arsize := swerv.io.lsu_axi_arsize
|
||||
io.lsu_axi_arburst := swerv.io.lsu_axi_arburst
|
||||
io.lsu_axi_arlock := swerv.io.lsu_axi_arlock
|
||||
io.lsu_axi_arcache := swerv.io.lsu_axi_arcache
|
||||
io.lsu_axi_arprot := swerv.io.lsu_axi_arprot
|
||||
io.lsu_axi_arqos := swerv.io.lsu_axi_arqos
|
||||
io.lsu_axi_rready := swerv.io.lsu_axi_rready
|
||||
// AXI Write Channels
|
||||
io.ifu_axi_awvalid := swerv.io.ifu_axi_awvalid
|
||||
io.ifu_axi_awid := swerv.io.ifu_axi_awid
|
||||
io.ifu_axi_awaddr := swerv.io.ifu_axi_awaddr
|
||||
io.ifu_axi_awregion := swerv.io.ifu_axi_awregion
|
||||
io.ifu_axi_awlen := swerv.io.ifu_axi_awlen
|
||||
io.ifu_axi_awsize := swerv.io.ifu_axi_awsize
|
||||
io.ifu_axi_awburst := swerv.io.ifu_axi_awburst
|
||||
io.ifu_axi_awlock := swerv.io.ifu_axi_awlock
|
||||
io.ifu_axi_awcache := swerv.io.ifu_axi_awcache
|
||||
io.ifu_axi_awprot := swerv.io.ifu_axi_awprot
|
||||
io.ifu_axi_awqos := swerv.io.ifu_axi_awqos
|
||||
io.ifu_axi_wvalid := swerv.io.ifu_axi_wvalid
|
||||
io.ifu_axi_wdata := swerv.io.ifu_axi_wdata
|
||||
io.ifu_axi_wstrb := swerv.io.ifu_axi_wstrb
|
||||
io.ifu_axi_wlast := swerv.io.ifu_axi_wlast
|
||||
|
||||
io.ifu_axi_bready := swerv.io.ifu_axi_bready
|
||||
|
||||
// AXI Read Channels
|
||||
io.ifu_axi_arvalid := swerv.io.ifu_axi_arvalid
|
||||
io.ifu_axi_arid := swerv.io.ifu_axi_arid
|
||||
io.ifu_axi_araddr := swerv.io.ifu_axi_araddr
|
||||
io.ifu_axi_arregion := swerv.io.ifu_axi_arregion
|
||||
io.ifu_axi_arlen := swerv.io.ifu_axi_arlen
|
||||
io.ifu_axi_arsize := swerv.io.ifu_axi_arsize
|
||||
io.ifu_axi_arburst := swerv.io.ifu_axi_arburst
|
||||
io.ifu_axi_arlock := swerv.io.ifu_axi_arlock
|
||||
io.ifu_axi_arcache := swerv.io.ifu_axi_arcache
|
||||
io.ifu_axi_arprot := swerv.io.ifu_axi_arprot
|
||||
io.ifu_axi_arqos := swerv.io.ifu_axi_arqos
|
||||
io.ifu_axi_rready := swerv.io.ifu_axi_rready
|
||||
//-------------------------- SB AXI signals--------------------------
|
||||
// AXI Write Channels
|
||||
io.sb_axi_awvalid := swerv.io.sb_axi_awvalid
|
||||
io.sb_axi_awid := swerv.io.sb_axi_awid
|
||||
io.sb_axi_awaddr := swerv.io.sb_axi_awaddr
|
||||
io.sb_axi_awregion := swerv.io.sb_axi_awregion
|
||||
io.sb_axi_awlen := swerv.io.sb_axi_awlen
|
||||
io.sb_axi_awsize := swerv.io.sb_axi_awsize
|
||||
io.sb_axi_awburst := swerv.io.sb_axi_awburst
|
||||
io.sb_axi_awlock := swerv.io.sb_axi_awlock
|
||||
io.sb_axi_awcache := swerv.io.sb_axi_awcache
|
||||
io.sb_axi_awprot := swerv.io.sb_axi_awprot
|
||||
io.sb_axi_awqos := swerv.io.sb_axi_awqos
|
||||
|
||||
io.sb_axi_wvalid:= swerv.io.sb_axi_wvalid
|
||||
io.sb_axi_wdata := swerv.io.sb_axi_wdata
|
||||
io.sb_axi_wstrb := swerv.io.sb_axi_wstrb
|
||||
io.sb_axi_wlast := swerv.io.sb_axi_wlast
|
||||
io.sb_axi_bready := swerv.io.sb_axi_bready
|
||||
|
||||
// AXI Read Channels
|
||||
io.sb_axi_arvalid := swerv.io.sb_axi_arvalid
|
||||
io.sb_axi_arid := swerv.io.sb_axi_arid
|
||||
io.sb_axi_araddr := swerv.io.sb_axi_araddr
|
||||
io.sb_axi_arregion := swerv.io.sb_axi_arregion
|
||||
io.sb_axi_arlen := swerv.io.sb_axi_arlen
|
||||
io.sb_axi_arsize := swerv.io.sb_axi_arsize
|
||||
io.sb_axi_arburst := swerv.io.sb_axi_arburst
|
||||
io.sb_axi_arlock := swerv.io.sb_axi_arlock
|
||||
io.sb_axi_arcache := swerv.io.sb_axi_arcache
|
||||
io.sb_axi_arprot := swerv.io.sb_axi_arprot
|
||||
io.sb_axi_arqos := swerv.io.sb_axi_arqos
|
||||
io.sb_axi_rready := swerv.io.sb_axi_rready
|
||||
//-------------------------- DMA AXI signals--------------------------
|
||||
// AXI Write Channels
|
||||
io.dma_axi_awready := swerv.io.dma_axi_awready
|
||||
io.dma_axi_wready := swerv.io.dma_axi_wready
|
||||
|
||||
io.dma_axi_bvalid := swerv.io.dma_axi_bvalid
|
||||
io.dma_axi_bresp := swerv.io.dma_axi_bresp
|
||||
io.dma_axi_bid := swerv.io.dma_axi_bid
|
||||
|
||||
// AXI Read Channels
|
||||
io.dma_axi_arready := swerv.io.dma_axi_arready
|
||||
io.dma_axi_rvalid := swerv.io.dma_axi_rvalid
|
||||
io.dma_axi_rid := swerv.io.dma_axi_rid
|
||||
io.dma_axi_rdata := swerv.io.dma_axi_rdata
|
||||
io.dma_axi_rresp := swerv.io.dma_axi_rresp
|
||||
io.dma_axi_rlast := swerv.io.dma_axi_rlast
|
||||
|
||||
// DMA Slave
|
||||
io.dma_hrdata := swerv.io.dma_hrdata
|
||||
io.dma_hreadyout := swerv.io.dma_hreadyout
|
||||
io.dma_hresp := swerv.io.dma_hresp
|
||||
|
||||
}
|
||||
object SWERV_Wrp extends App {
|
||||
println((new chisel3.stage.ChiselStage).emitVerilog(new el2_swerv_wrapper()))
|
||||
}
|
||||
|
|
@ -96,12 +96,12 @@ class el2_dec_IO extends Bundle with el2_lib {
|
|||
|
||||
val lsu_idle_any = Input(Bool()) // lsu idle for halting
|
||||
|
||||
val i0_brp = Input(new el2_br_pkt_t) // branch packet
|
||||
val i0_brp = Flipped(Valid(new el2_br_pkt_t)) // branch packet
|
||||
val ifu_i0_bp_index = Input(UInt(BTB_ADDR_HI.W)) // BP index
|
||||
val ifu_i0_bp_fghr = Input(UInt(BHT_GHR_SIZE.W)) // BP FGHR
|
||||
val ifu_i0_bp_btag = Input(UInt(BTB_BTAG_SIZE.W)) // BP tag
|
||||
|
||||
val lsu_error_pkt_r = Input(new el2_lsu_error_pkt_t) // LSU exception/error packet
|
||||
val lsu_error_pkt_r = Flipped(Valid(new el2_lsu_error_pkt_t)) // LSU exception/error packet
|
||||
val lsu_single_ecc_error_incr = Input(Bool())// LSU inc SB error counter
|
||||
|
||||
val lsu_imprecise_error_load_any = Input(Bool()) // LSU imprecise load bus error
|
||||
|
|
@ -206,9 +206,9 @@ class el2_dec_IO extends Bundle with el2_lib {
|
|||
val dec_i0_rs1_bypass_data_d = Output(UInt(32.W)) // rs1 bypass data
|
||||
val dec_i0_rs2_bypass_data_d = Output(UInt(32.W)) // rs2 bypass data
|
||||
|
||||
val lsu_p = Output(new el2_lsu_pkt_t) // lsu packet
|
||||
val mul_p = Output(new el2_mul_pkt_t) // mul packet
|
||||
val div_p = Output(new el2_div_pkt_t) // div packet
|
||||
val lsu_p = Valid(new el2_lsu_pkt_t) // lsu packet
|
||||
val mul_p = Valid(new el2_mul_pkt_t) // mul packet
|
||||
val div_p = Valid(new el2_div_pkt_t) // div packet
|
||||
val dec_div_cancel = Output(Bool()) // cancel divide operation
|
||||
|
||||
val dec_lsu_offset_d = Output(UInt(12.W)) // 12b offset for load/store addresses
|
||||
|
|
@ -223,14 +223,14 @@ class el2_dec_IO extends Bundle with el2_lib {
|
|||
|
||||
val pred_correct_npc_x = Output(UInt(32.W)) // npc if prediction is correct at e2 stage
|
||||
|
||||
val dec_tlu_br0_r_pkt = Output(new el2_br_tlu_pkt_t) // slot 0 branch predictor update packet
|
||||
val dec_tlu_br0_r_pkt = Valid(new el2_br_tlu_pkt_t) // slot 0 branch predictor update packet
|
||||
|
||||
val dec_tlu_perfcnt0 = Output(Bool()) // toggles when slot0 perf counter 0 has an event inc
|
||||
val dec_tlu_perfcnt1 = Output(Bool()) // toggles when slot0 perf counter 1 has an event inc
|
||||
val dec_tlu_perfcnt2 = Output(Bool()) // toggles when slot0 perf counter 2 has an event inc
|
||||
val dec_tlu_perfcnt3 = Output(Bool()) // toggles when slot0 perf counter 3 has an event inc
|
||||
|
||||
val dec_i0_predict_p_d = Output(new el2_predict_pkt_t) // prediction packet to alus
|
||||
val dec_i0_predict_p_d = Valid(new el2_predict_pkt_t) // prediction packet to alus
|
||||
val i0_predict_fghr_d = Output(UInt(BHT_GHR_SIZE.W)) // DEC predict fghr
|
||||
val i0_predict_index_d = Output(UInt(BHT_ADDR_HI.W)) // DEC predict index
|
||||
val i0_predict_btag_d = Output(UInt(BTB_BTAG_SIZE.W)) // DEC predict branch tag
|
||||
|
|
@ -398,7 +398,7 @@ class el2_dec extends Module with param with RequireAsyncReset{
|
|||
//dec_trigger.io <> io
|
||||
//inputs
|
||||
dec_trigger.io.dec_i0_pc_d := instbuff.io.dec_i0_pc_d
|
||||
dec_trigger.io.trigger_pkt_any := tlu.io.trigger_pkt_any
|
||||
dec_trigger.io.trigger_pkt_any <> tlu.io.trigger_pkt_any
|
||||
//output
|
||||
val dec_i0_trigger_match_d = dec_trigger.io.dec_i0_trigger_match_d
|
||||
dontTouch(dec_i0_trigger_match_d)
|
||||
|
|
@ -592,7 +592,7 @@ class el2_dec extends Module with param with RequireAsyncReset{
|
|||
tlu.io.lsu_fir_addr := io.lsu_fir_addr
|
||||
tlu.io.lsu_fir_error := io.lsu_fir_error
|
||||
tlu.io.iccm_dma_sb_error := io.iccm_dma_sb_error
|
||||
tlu.io.lsu_error_pkt_r := io.lsu_error_pkt_r
|
||||
tlu.io.lsu_error_pkt_r <> io.lsu_error_pkt_r
|
||||
tlu.io.lsu_single_ecc_error_incr := io.lsu_single_ecc_error_incr
|
||||
tlu.io.dec_pause_state := decode.io.dec_pause_state
|
||||
tlu.io.lsu_imprecise_error_store_any := io.lsu_imprecise_error_store_any
|
||||
|
|
@ -650,8 +650,8 @@ class el2_dec extends Module with param with RequireAsyncReset{
|
|||
io.dec_tlu_flush_err_r := tlu.io.dec_tlu_flush_err_r
|
||||
decode.io.dec_tlu_flush_extint := tlu.io.dec_tlu_flush_extint
|
||||
io.dec_tlu_meihap := tlu.io.dec_tlu_meihap
|
||||
io.trigger_pkt_any := tlu.io.trigger_pkt_any
|
||||
io.dec_tlu_ic_diag_pkt := tlu.io.dec_tlu_ic_diag_pkt
|
||||
io.trigger_pkt_any <> tlu.io.trigger_pkt_any
|
||||
io.dec_tlu_ic_diag_pkt <> tlu.io.dec_tlu_ic_diag_pkt
|
||||
io.o_cpu_halt_status := tlu.io.o_cpu_halt_status
|
||||
io.o_cpu_halt_ack := tlu.io.o_cpu_halt_ack
|
||||
io.o_cpu_run_ack := tlu.io.o_cpu_run_ack
|
||||
|
|
@ -663,7 +663,7 @@ class el2_dec extends Module with param with RequireAsyncReset{
|
|||
io.dec_tlu_meipt := tlu.io.dec_tlu_meipt
|
||||
decode.io.dec_csr_rddata_d := tlu.io.dec_csr_rddata_d
|
||||
decode.io.dec_csr_legal_d := tlu.io.dec_csr_legal_d
|
||||
io.dec_tlu_br0_r_pkt := tlu.io.dec_tlu_br0_r_pkt
|
||||
io.dec_tlu_br0_r_pkt <> tlu.io.dec_tlu_br0_r_pkt
|
||||
decode.io.dec_tlu_i0_kill_writeb_wb := tlu.io.dec_tlu_i0_kill_writeb_wb
|
||||
decode.io.dec_tlu_flush_lower_wb := tlu.io.dec_tlu_flush_lower_wb
|
||||
io.dec_tlu_i0_commit_cmt := tlu.io.dec_tlu_i0_commit_cmt
|
||||
|
|
|
|||
|
|
@ -35,7 +35,7 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
|
|||
val dec_i0_icaf_f1_d = Input(Bool()) // i0 instruction access fault at decode for f1 fetch group
|
||||
val dec_i0_icaf_type_d = Input(UInt(2.W)) // i0 instruction access fault type
|
||||
val dec_i0_dbecc_d = Input(Bool()) // icache/iccm double-bit error
|
||||
val dec_i0_brp = Input(new el2_br_pkt_t) // branch packet
|
||||
val dec_i0_brp = Flipped(Valid(new el2_br_pkt_t)) // branch packet
|
||||
val dec_i0_bp_index = Input(UInt(((BTB_ADDR_HI-BTB_ADDR_LO)+1).W)) // i0 branch index
|
||||
val dec_i0_bp_fghr = Input(UInt(BHT_GHR_SIZE.W)) // BP FGHR
|
||||
val dec_i0_bp_btag = Input(UInt(BTB_BTAG_SIZE.W)) // BP tag
|
||||
|
|
@ -84,9 +84,9 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
|
|||
val dec_i0_select_pc_d = Output(Bool()) // i0 select pc for rs1 - branches
|
||||
val dec_i0_rs1_bypass_en_d = Output(UInt(2.W)) // i0 rs1 bypass enable
|
||||
val dec_i0_rs2_bypass_en_d = Output(UInt(2.W)) // i0 rs2 bypass enable
|
||||
val lsu_p = Output(new el2_lsu_pkt_t) // load/store packet
|
||||
val mul_p = Output(new el2_mul_pkt_t) // multiply packet
|
||||
val div_p = Output(new el2_div_pkt_t) // divide packet
|
||||
val lsu_p = Valid(new el2_lsu_pkt_t) // load/store packet
|
||||
val mul_p = Valid(new el2_mul_pkt_t) // multiply packet
|
||||
val div_p = Valid(new el2_div_pkt_t) // divide packet
|
||||
val div_waddr_wb = Output(UInt(5.W)) // DIV write address to GPR
|
||||
val dec_div_cancel = Output(Bool()) // cancel the divide operation
|
||||
val dec_lsu_valid_raw_d = Output(Bool())
|
||||
|
|
@ -104,7 +104,7 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
|
|||
val dec_tlu_i0_pc_r = Output(UInt(31.W)) // i0 trap pc
|
||||
val dec_illegal_inst = Output(UInt(32.W)) // illegal inst
|
||||
val pred_correct_npc_x = Output(UInt(31.W)) // npc e2 if the prediction is correct
|
||||
val dec_i0_predict_p_d = Output(new el2_predict_pkt_t) // i0 predict packet decode
|
||||
val dec_i0_predict_p_d = Valid(new el2_predict_pkt_t) // i0 predict packet decode
|
||||
val i0_predict_fghr_d = Output(UInt(BHT_GHR_SIZE.W)) // i0 predict fghr
|
||||
val i0_predict_index_d = Output(UInt(((BHT_ADDR_HI-BHT_ADDR_LO)+1).W)) // i0 predict index
|
||||
val i0_predict_btag_d = Output(UInt(BTB_BTAG_SIZE.W)) // i0_predict branch tag
|
||||
|
|
@ -133,24 +133,24 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
|
|||
val x_t_in = Wire(new el2_trap_pkt_t)
|
||||
val r_t = Wire(new el2_trap_pkt_t)
|
||||
val r_t_in = Wire(new el2_trap_pkt_t)
|
||||
val d_d = Wire(new el2_dest_pkt_t)
|
||||
val x_d = Wire(new el2_dest_pkt_t)
|
||||
val r_d = Wire(new el2_dest_pkt_t)
|
||||
val r_d_in = Wire(new el2_dest_pkt_t)
|
||||
val wbd = Wire(new el2_dest_pkt_t)
|
||||
val d_d = Wire(Valid(new el2_dest_pkt_t))
|
||||
val x_d = Wire(Valid(new el2_dest_pkt_t))
|
||||
val r_d = Wire(Valid(new el2_dest_pkt_t))
|
||||
val r_d_in = Wire(Valid(new el2_dest_pkt_t))
|
||||
val wbd = Wire(Valid(new el2_dest_pkt_t))
|
||||
val i0_d_c = Wire(new el2_class_pkt_t)
|
||||
val i0_rs1_class_d = Wire(new el2_class_pkt_t)
|
||||
val i0_rs2_class_d = Wire(new el2_class_pkt_t)
|
||||
val i0_rs1_depth_d = WireInit(UInt(2.W),0.U)
|
||||
val i0_rs2_depth_d = WireInit(UInt(2.W),0.U)
|
||||
val cam_wen=WireInit(UInt(LSU_NUM_NBLOAD.W), 0.U)
|
||||
val cam = Wire(Vec(LSU_NUM_NBLOAD,new el2_load_cam_pkt_t))
|
||||
val cam = Wire(Vec(LSU_NUM_NBLOAD,Valid(new el2_load_cam_pkt_t)))
|
||||
val cam_write=WireInit(UInt(1.W), 0.U)
|
||||
val cam_inv_reset_val=Wire(Vec(LSU_NUM_NBLOAD,UInt(1.W)))
|
||||
val cam_data_reset_val=Wire(Vec(LSU_NUM_NBLOAD,UInt(1.W)))
|
||||
val nonblock_load_write=Wire(Vec(LSU_NUM_NBLOAD,UInt(1.W)))
|
||||
val cam_raw =Wire(Vec(LSU_NUM_NBLOAD,new el2_load_cam_pkt_t))
|
||||
val cam_in =Wire(Vec(LSU_NUM_NBLOAD,new el2_load_cam_pkt_t))
|
||||
val cam_raw =Wire(Vec(LSU_NUM_NBLOAD,Valid(new el2_load_cam_pkt_t)))
|
||||
val cam_in =Wire(Vec(LSU_NUM_NBLOAD,Valid(new el2_load_cam_pkt_t)))
|
||||
//val i0_temp = Wire(new el2_inst_pkt_t)
|
||||
val i0_dp= Wire(new el2_dec_pkt_t)
|
||||
val i0_dp_raw= Wire(new el2_dec_pkt_t)
|
||||
|
|
@ -228,30 +228,30 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
|
|||
// End - Data gating }}
|
||||
|
||||
val i0_brp_valid = io.dec_i0_brp.valid & !leak1_mode
|
||||
io.dec_i0_predict_p_d.misp :=0.U
|
||||
io.dec_i0_predict_p_d.ataken :=0.U
|
||||
io.dec_i0_predict_p_d.boffset :=0.U
|
||||
io.dec_i0_predict_p_d.pcall := i0_pcall // don't mark as pcall if branch error
|
||||
io.dec_i0_predict_p_d.pja := i0_pja
|
||||
io.dec_i0_predict_p_d.pret := i0_pret
|
||||
io.dec_i0_predict_p_d.prett := io.dec_i0_brp.prett
|
||||
io.dec_i0_predict_p_d.pc4 := io.dec_i0_pc4_d
|
||||
io.dec_i0_predict_p_d.hist := io.dec_i0_brp.hist
|
||||
io.dec_i0_predict_p_d.bits.misp :=0.U
|
||||
io.dec_i0_predict_p_d.bits.ataken :=0.U
|
||||
io.dec_i0_predict_p_d.bits.boffset :=0.U
|
||||
io.dec_i0_predict_p_d.bits.pcall := i0_pcall // don't mark as pcall if branch error
|
||||
io.dec_i0_predict_p_d.bits.pja := i0_pja
|
||||
io.dec_i0_predict_p_d.bits.pret := i0_pret
|
||||
io.dec_i0_predict_p_d.bits.prett := io.dec_i0_brp.bits.prett
|
||||
io.dec_i0_predict_p_d.bits.pc4 := io.dec_i0_pc4_d
|
||||
io.dec_i0_predict_p_d.bits.hist := io.dec_i0_brp.bits.hist
|
||||
io.dec_i0_predict_p_d.valid := i0_brp_valid & i0_legal_decode_d
|
||||
val i0_notbr_error = i0_brp_valid & !(i0_dp_raw.condbr | i0_pcall_raw | i0_pja_raw | i0_pret_raw)
|
||||
|
||||
// no toffset error for a pret
|
||||
val i0_br_toffset_error = i0_brp_valid & io.dec_i0_brp.hist(1) & (io.dec_i0_brp.toffset =/= i0_br_offset) & !i0_pret_raw
|
||||
val i0_ret_error = i0_brp_valid & io.dec_i0_brp.ret & !i0_pret_raw;
|
||||
val i0_br_error = io.dec_i0_brp.br_error | i0_notbr_error | i0_br_toffset_error | i0_ret_error
|
||||
io.dec_i0_predict_p_d.br_error := i0_br_error & i0_legal_decode_d & !leak1_mode
|
||||
io.dec_i0_predict_p_d.br_start_error := io.dec_i0_brp.br_start_error & i0_legal_decode_d & !leak1_mode
|
||||
val i0_br_toffset_error = i0_brp_valid & io.dec_i0_brp.bits.hist(1) & (io.dec_i0_brp.bits.toffset =/= i0_br_offset) & !i0_pret_raw
|
||||
val i0_ret_error = i0_brp_valid & io.dec_i0_brp.bits.ret & !i0_pret_raw;
|
||||
val i0_br_error = io.dec_i0_brp.bits.br_error | i0_notbr_error | i0_br_toffset_error | i0_ret_error
|
||||
io.dec_i0_predict_p_d.bits.br_error := i0_br_error & i0_legal_decode_d & !leak1_mode
|
||||
io.dec_i0_predict_p_d.bits.br_start_error := io.dec_i0_brp.bits.br_start_error & i0_legal_decode_d & !leak1_mode
|
||||
io.i0_predict_index_d := io.dec_i0_bp_index
|
||||
io.i0_predict_btag_d := io.dec_i0_bp_btag
|
||||
val i0_br_error_all = (i0_br_error | io.dec_i0_brp.br_start_error) & !leak1_mode
|
||||
io.dec_i0_predict_p_d.toffset := i0_br_offset
|
||||
val i0_br_error_all = (i0_br_error | io.dec_i0_brp.bits.br_start_error) & !leak1_mode
|
||||
io.dec_i0_predict_p_d.bits.toffset := i0_br_offset
|
||||
io.i0_predict_fghr_d := io.dec_i0_bp_fghr
|
||||
io.dec_i0_predict_p_d.way := io.dec_i0_brp.way
|
||||
io.dec_i0_predict_p_d.bits.way := io.dec_i0_brp.bits.way
|
||||
// end
|
||||
|
||||
// on br error turn anything into a nop
|
||||
|
|
@ -277,8 +277,8 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
|
|||
// branches that can be predicted
|
||||
val i0_predict_br = i0_dp.condbr | i0_pcall | i0_pja | i0_pret;
|
||||
|
||||
val i0_predict_nt = !(io.dec_i0_brp.hist(1) & i0_brp_valid) & i0_predict_br
|
||||
val i0_predict_t = (io.dec_i0_brp.hist(1) & i0_brp_valid) & i0_predict_br
|
||||
val i0_predict_nt = !(io.dec_i0_brp.bits.hist(1) & i0_brp_valid) & i0_predict_br
|
||||
val i0_predict_t = (io.dec_i0_brp.bits.hist(1) & i0_brp_valid) & i0_predict_br
|
||||
val i0_ap_pc2 = !io.dec_i0_pc4_d
|
||||
val i0_ap_pc4 = io.dec_i0_pc4_d
|
||||
io.i0_ap.predict_nt := i0_predict_nt
|
||||
|
|
@ -315,15 +315,15 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
|
|||
val cam_data_reset = io.lsu_nonblock_load_data_valid | io.lsu_nonblock_load_data_error
|
||||
val cam_data_reset_tag = io.lsu_nonblock_load_data_tag(LSU_NUM_NBLOAD_WIDTH-1,0)
|
||||
|
||||
val nonblock_load_rd = Mux(x_d.i0load.asBool, x_d.i0rd, 0.U(5.W)) // rd data
|
||||
val nonblock_load_rd = Mux(x_d.bits.i0load.asBool, x_d.bits.i0rd, 0.U(5.W)) // rd data
|
||||
val load_data_tag = io.lsu_nonblock_load_data_tag
|
||||
// case of multiple loads to same dest ie. x1 ... you have to invalidate the older one
|
||||
// don't writeback a nonblock load
|
||||
val nonblock_load_valid_m_delay=withClock(io.active_clk){RegEnable(io.lsu_nonblock_load_valid_m,0.U, i0_r_ctl_en.asBool)}
|
||||
val i0_load_kill_wen_r = nonblock_load_valid_m_delay & r_d.i0load
|
||||
val i0_load_kill_wen_r = nonblock_load_valid_m_delay & r_d.bits.i0load
|
||||
for(i <- 0 until LSU_NUM_NBLOAD){
|
||||
cam_inv_reset_val(i) := cam_inv_reset & (cam_inv_reset_tag === cam(i).tag) & cam(i).valid
|
||||
cam_data_reset_val(i) := cam_data_reset & (cam_data_reset_tag === cam(i).tag) & cam_raw(i).valid
|
||||
cam_inv_reset_val(i) := cam_inv_reset & (cam_inv_reset_tag === cam(i).bits.tag) & cam(i).valid
|
||||
cam_data_reset_val(i) := cam_data_reset & (cam_data_reset_tag === cam(i).bits.tag) & cam_raw(i).valid
|
||||
cam_in(i):=0.U.asTypeOf(cam(0))
|
||||
cam(i):=cam_raw(i)
|
||||
|
||||
|
|
@ -332,16 +332,16 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
|
|||
}
|
||||
when(cam_wen(i).asBool){
|
||||
cam_in(i).valid := 1.U(1.W)
|
||||
cam_in(i).wb := 0.U(1.W)
|
||||
cam_in(i).tag := cam_write_tag
|
||||
cam_in(i).rd := nonblock_load_rd
|
||||
}.elsewhen(cam_inv_reset_val(i).asBool || (i0_wen_r.asBool && (r_d_in.i0rd === cam(i).rd) && cam(i).wb.asBool)){
|
||||
cam_in(i).bits.wb := 0.U(1.W)
|
||||
cam_in(i).bits.tag := cam_write_tag
|
||||
cam_in(i).bits.rd := nonblock_load_rd
|
||||
}.elsewhen(cam_inv_reset_val(i).asBool || (i0_wen_r.asBool && (r_d_in.bits.i0rd === cam(i).bits.rd) && cam(i).bits.wb.asBool)){
|
||||
cam_in(i).valid := 0.U
|
||||
}.otherwise{
|
||||
cam_in(i) := cam(i)
|
||||
}
|
||||
when(nonblock_load_valid_m_delay===1.U && (io.lsu_nonblock_load_inv_tag_r === cam(i).tag) && cam(i).valid===1.U){
|
||||
cam_in(i).wb := 1.U
|
||||
when(nonblock_load_valid_m_delay===1.U && (io.lsu_nonblock_load_inv_tag_r === cam(i).bits.tag) && cam(i).valid===1.U){
|
||||
cam_in(i).bits.wb := 1.U
|
||||
}
|
||||
// force debug halt forces cam valids to 0; highest priority
|
||||
when(io.dec_tlu_force_halt){
|
||||
|
|
@ -349,18 +349,18 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
|
|||
}
|
||||
|
||||
cam_raw(i):=withClock(io.free_clk){RegNext(cam_in(i),0.U.asTypeOf(cam(0)))}
|
||||
nonblock_load_write(i) := (load_data_tag === cam_raw(i).tag) & cam_raw(i).valid
|
||||
nonblock_load_write(i) := (load_data_tag === cam_raw(i).bits.tag) & cam_raw(i).valid
|
||||
}
|
||||
|
||||
io.dec_nonblock_load_waddr:=0.U(5.W)
|
||||
// cancel if any younger inst (including another nonblock) committing this cycle
|
||||
val nonblock_load_cancel = ((r_d_in.i0rd === io.dec_nonblock_load_waddr) & i0_wen_r)
|
||||
val nonblock_load_cancel = ((r_d_in.bits.i0rd === io.dec_nonblock_load_waddr) & i0_wen_r)
|
||||
io.dec_nonblock_load_wen := (io.lsu_nonblock_load_data_valid && nonblock_load_write.reduce(_|_).asBool && !nonblock_load_cancel)
|
||||
val i0_nonblock_boundary_stall = ((nonblock_load_rd===i0r.rs1) & io.lsu_nonblock_load_valid_m & io.dec_i0_rs1_en_d)|((nonblock_load_rd===i0r.rs2) & io.lsu_nonblock_load_valid_m & io.dec_i0_rs2_en_d)
|
||||
|
||||
i0_nonblock_load_stall := i0_nonblock_boundary_stall
|
||||
|
||||
val cal_temp= for(i <-0 until LSU_NUM_NBLOAD) yield ((Fill(5,nonblock_load_write(i)) & cam(i).rd), io.dec_i0_rs1_en_d & cam(i).valid & (cam(i).rd === i0r.rs1), io.dec_i0_rs2_en_d & cam(i).valid & (cam(i).rd === i0r.rs2))
|
||||
val cal_temp= for(i <-0 until LSU_NUM_NBLOAD) yield ((Fill(5,nonblock_load_write(i)) & cam(i).bits.rd), io.dec_i0_rs1_en_d & cam(i).valid & (cam(i).bits.rd === i0r.rs1), io.dec_i0_rs2_en_d & cam(i).valid & (cam(i).bits.rd === i0r.rs2))
|
||||
val (waddr, ld_stall_1, ld_stall_2) = (cal_temp.map(_._1).reduce(_|_) , cal_temp.map(_._2).reduce(_|_), cal_temp.map(_._3).reduce(_|_) )
|
||||
io.dec_nonblock_load_waddr:=waddr
|
||||
i0_nonblock_load_stall:=ld_stall_1 | ld_stall_2 | i0_nonblock_boundary_stall
|
||||
|
|
@ -425,33 +425,33 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
|
|||
///////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
io.div_p.valid := div_decode_d
|
||||
io.div_p.unsign := i0_dp.unsign
|
||||
io.div_p.rem := i0_dp.rem
|
||||
io.div_p.bits.unsign := i0_dp.unsign
|
||||
io.div_p.bits.rem := i0_dp.rem
|
||||
|
||||
io.mul_p.valid := mul_decode_d
|
||||
io.mul_p.rs1_sign := i0_dp.rs1_sign
|
||||
io.mul_p.rs2_sign := i0_dp.rs2_sign
|
||||
io.mul_p.low := i0_dp.low
|
||||
io.mul_p.bits.rs1_sign := i0_dp.rs1_sign
|
||||
io.mul_p.bits.rs2_sign := i0_dp.rs2_sign
|
||||
io.mul_p.bits.low := i0_dp.low
|
||||
|
||||
io.dec_extint_stall := withClock(data_gate_clk){RegNext(io.dec_tlu_flush_extint,0.U)}
|
||||
|
||||
io.lsu_p := 0.U.asTypeOf(io.lsu_p)
|
||||
when (io.dec_extint_stall){
|
||||
io.lsu_p.load := 1.U(1.W)
|
||||
io.lsu_p.word := 1.U(1.W)
|
||||
io.lsu_p.fast_int := 1.U(1.W)
|
||||
io.lsu_p.bits.load := 1.U(1.W)
|
||||
io.lsu_p.bits.word := 1.U(1.W)
|
||||
io.lsu_p.bits.fast_int := 1.U(1.W)
|
||||
io.lsu_p.valid := 1.U(1.W)
|
||||
}.otherwise {
|
||||
io.lsu_p.valid := lsu_decode_d
|
||||
io.lsu_p.load := i0_dp.load
|
||||
io.lsu_p.store := i0_dp.store
|
||||
io.lsu_p.by := i0_dp.by
|
||||
io.lsu_p.half := i0_dp.half
|
||||
io.lsu_p.word := i0_dp.word
|
||||
io.lsu_p.load_ldst_bypass_d := load_ldst_bypass_d
|
||||
io.lsu_p.store_data_bypass_d := store_data_bypass_d
|
||||
io.lsu_p.store_data_bypass_m := store_data_bypass_m
|
||||
io.lsu_p.unsign := i0_dp.unsign
|
||||
io.lsu_p.bits.load := i0_dp.load
|
||||
io.lsu_p.bits.store := i0_dp.store
|
||||
io.lsu_p.bits.by := i0_dp.by
|
||||
io.lsu_p.bits.half := i0_dp.half
|
||||
io.lsu_p.bits.word := i0_dp.word
|
||||
io.lsu_p.bits.load_ldst_bypass_d := load_ldst_bypass_d
|
||||
io.lsu_p.bits.store_data_bypass_d := store_data_bypass_d
|
||||
io.lsu_p.bits.store_data_bypass_m := store_data_bypass_m
|
||||
io.lsu_p.bits.unsign := i0_dp.unsign
|
||||
}
|
||||
|
||||
//////////////////////////////////////
|
||||
|
|
@ -468,14 +468,14 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
|
|||
//dec_csr_wen_unq_d assigned as csr_write above
|
||||
|
||||
io.dec_csr_rdaddr_d := i0(31,20)
|
||||
io.dec_csr_wraddr_r := r_d.csrwaddr //r_d is a el2_dest_pkt
|
||||
io.dec_csr_wraddr_r := r_d.bits.csrwaddr //r_d is a el2_dest_pkt
|
||||
|
||||
// make sure csr doesn't write same cycle as dec_tlu_flush_lower_wb
|
||||
// also use valid so it's flushable
|
||||
io.dec_csr_wen_r := r_d.csrwen & r_d.i0valid & !io.dec_tlu_i0_kill_writeb_r;
|
||||
io.dec_csr_wen_r := r_d.bits.csrwen & r_d.valid & !io.dec_tlu_i0_kill_writeb_r;
|
||||
|
||||
// If we are writing MIE or MSTATUS, hold off the external interrupt for a cycle on the write.
|
||||
io.dec_csr_stall_int_ff := ((r_d.csrwaddr === "h300".U) | (r_d.csrwaddr === "h304".U)) & r_d.csrwen & r_d.i0valid & !io.dec_tlu_i0_kill_writeb_wb;
|
||||
io.dec_csr_stall_int_ff := ((r_d.bits.csrwaddr === "h300".U) | (r_d.bits.csrwaddr === "h304".U)) & r_d.bits.csrwen & r_d.valid & !io.dec_tlu_i0_kill_writeb_wb;
|
||||
|
||||
val csr_read_x = withClock(io.active_clk){RegNext(csr_ren_qual_d,init=0.B)}
|
||||
val csr_clr_x = withClock(io.active_clk){RegNext(csr_clr_d, init=0.B)}
|
||||
|
|
@ -515,9 +515,9 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
|
|||
val pause_stall = pause_state
|
||||
|
||||
// for csr write only data is produced by the alu
|
||||
io.dec_csr_wrdata_r := Mux(r_d.csrwonly.asBool,i0_result_corr_r,write_csr_data)
|
||||
io.dec_csr_wrdata_r := Mux(r_d.bits.csrwonly.asBool,i0_result_corr_r,write_csr_data)
|
||||
|
||||
val prior_csr_write = x_d.csrwonly | r_d.csrwonly | wbd.csrwonly;
|
||||
val prior_csr_write = x_d.bits.csrwonly | r_d.bits.csrwonly | wbd.bits.csrwonly;
|
||||
|
||||
val debug_fence_i = io.dec_debug_fence_d & io.dbg_cmd_wrdata(0)
|
||||
val debug_fence_raw = io.dec_debug_fence_d & io.dbg_cmd_wrdata(1)
|
||||
|
|
@ -563,8 +563,8 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
|
|||
io.dec_pmu_postsync_stall := postsync_stall.asBool
|
||||
io.dec_pmu_presync_stall := presync_stall.asBool
|
||||
|
||||
val prior_inflight_x = x_d.i0valid
|
||||
val prior_inflight_wb = r_d.i0valid
|
||||
val prior_inflight_x = x_d.valid
|
||||
val prior_inflight_wb = r_d.valid
|
||||
val prior_inflight = prior_inflight_x | prior_inflight_wb
|
||||
val prior_inflight_eff = Mux(i0_dp.div,prior_inflight_x,prior_inflight)
|
||||
|
||||
|
|
@ -579,7 +579,7 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
|
|||
mul_decode_d := i0_exulegal_decode_d & i0_dp.mul
|
||||
div_decode_d := i0_exulegal_decode_d & i0_dp.div
|
||||
|
||||
io.dec_tlu_i0_valid_r := r_d.i0valid & !io.dec_tlu_flush_lower_wb
|
||||
io.dec_tlu_i0_valid_r := r_d.valid & !io.dec_tlu_flush_lower_wb
|
||||
|
||||
//traps for TLU (tlu stuff)
|
||||
d_t.legal := i0_legal_decode_d
|
||||
|
|
@ -608,13 +608,13 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
|
|||
|
||||
r_t_in := r_t
|
||||
|
||||
r_t_in.i0trigger := (repl(4,(r_d.i0load | r_d.i0store)) & lsu_trigger_match_r) | r_t.i0trigger
|
||||
r_t_in.i0trigger := (repl(4,(r_d.bits.i0load | r_d.bits.i0store)) & lsu_trigger_match_r) | r_t.i0trigger
|
||||
r_t_in.pmu_lsu_misaligned := lsu_pmu_misaligned_r // only valid if a load/store is valid in DC3 stage
|
||||
|
||||
when (io.dec_tlu_flush_lower_wb.asBool) {r_t_in := 0.U.asTypeOf(r_t_in) }
|
||||
|
||||
io.dec_tlu_packet_r := r_t_in
|
||||
io.dec_tlu_packet_r.pmu_divide := r_d.i0div & r_d.i0valid
|
||||
io.dec_tlu_packet_r.pmu_divide := r_d.bits.i0div & r_d.valid
|
||||
// end tlu stuff
|
||||
|
||||
flush_final_r := withClock(data_gate_clk){RegNext(io.exu_flush_final, 0.U)}
|
||||
|
|
@ -666,52 +666,52 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
|
|||
io.dec_data_en := Cat(i0_x_data_en, i0_r_data_en)
|
||||
io.dec_ctl_en := Cat(i0_x_ctl_en, i0_r_ctl_en)
|
||||
|
||||
d_d.i0rd := i0r.rd
|
||||
d_d.i0v := i0_rd_en_d & i0_legal_decode_d
|
||||
d_d.i0valid := io.dec_i0_decode_d // has flush_final_r
|
||||
d_d.bits.i0rd := i0r.rd
|
||||
d_d.bits.i0v := i0_rd_en_d & i0_legal_decode_d
|
||||
d_d.valid := io.dec_i0_decode_d // has flush_final_r
|
||||
|
||||
d_d.i0load := i0_dp.load & i0_legal_decode_d
|
||||
d_d.i0store := i0_dp.store & i0_legal_decode_d
|
||||
d_d.i0div := i0_dp.div & i0_legal_decode_d
|
||||
d_d.bits.i0load := i0_dp.load & i0_legal_decode_d
|
||||
d_d.bits.i0store := i0_dp.store & i0_legal_decode_d
|
||||
d_d.bits.i0div := i0_dp.div & i0_legal_decode_d
|
||||
|
||||
d_d.csrwen := io.dec_csr_wen_unq_d & i0_legal_decode_d
|
||||
d_d.csrwonly := i0_csr_write_only_d & io.dec_i0_decode_d
|
||||
d_d.csrwaddr := i0(31,20)
|
||||
d_d.bits.csrwen := io.dec_csr_wen_unq_d & i0_legal_decode_d
|
||||
d_d.bits.csrwonly := i0_csr_write_only_d & io.dec_i0_decode_d
|
||||
d_d.bits.csrwaddr := i0(31,20)
|
||||
|
||||
x_d := rvdffe(d_d, i0_x_ctl_en.asBool,clock,io.scan_mode)
|
||||
val x_d_in = Wire(new el2_dest_pkt_t)
|
||||
val x_d_in = Wire(Valid(new el2_dest_pkt_t))
|
||||
x_d_in := x_d
|
||||
x_d_in.i0v := x_d.i0v & !io.dec_tlu_flush_lower_wb & !io.dec_tlu_flush_lower_r
|
||||
x_d_in.i0valid := x_d.i0valid & !io.dec_tlu_flush_lower_wb & !io.dec_tlu_flush_lower_r
|
||||
x_d_in.bits.i0v := x_d.bits.i0v & !io.dec_tlu_flush_lower_wb & !io.dec_tlu_flush_lower_r
|
||||
x_d_in.valid := x_d.valid & !io.dec_tlu_flush_lower_wb & !io.dec_tlu_flush_lower_r
|
||||
|
||||
r_d := rvdffe(x_d_in,i0_r_ctl_en.asBool,clock,io.scan_mode)
|
||||
r_d_in := r_d
|
||||
r_d_in.i0rd := r_d.i0rd
|
||||
r_d_in.bits.i0rd := r_d.bits.i0rd
|
||||
|
||||
r_d_in.i0v := (r_d.i0v & !io.dec_tlu_flush_lower_wb)
|
||||
r_d_in.i0valid := (r_d.i0valid & !io.dec_tlu_flush_lower_wb)
|
||||
r_d_in.i0load := r_d.i0load & !io.dec_tlu_flush_lower_wb
|
||||
r_d_in.i0store := r_d.i0store & !io.dec_tlu_flush_lower_wb
|
||||
r_d_in.bits.i0v := (r_d.bits.i0v & !io.dec_tlu_flush_lower_wb)
|
||||
r_d_in.valid := (r_d.valid & !io.dec_tlu_flush_lower_wb)
|
||||
r_d_in.bits.i0load := r_d.bits.i0load & !io.dec_tlu_flush_lower_wb
|
||||
r_d_in.bits.i0store := r_d.bits.i0store & !io.dec_tlu_flush_lower_wb
|
||||
|
||||
wbd := rvdffe(r_d_in,i0_wb_ctl_en.asBool,clock,io.scan_mode)
|
||||
|
||||
io.dec_i0_waddr_r := r_d_in.i0rd
|
||||
i0_wen_r := r_d_in.i0v & !io.dec_tlu_i0_kill_writeb_r
|
||||
io.dec_i0_wen_r := i0_wen_r & !r_d_in.i0div & !i0_load_kill_wen_r // don't write a nonblock load 1st time down the pipe
|
||||
io.dec_i0_waddr_r := r_d_in.bits.i0rd
|
||||
i0_wen_r := r_d_in.bits.i0v & !io.dec_tlu_i0_kill_writeb_r
|
||||
io.dec_i0_wen_r := i0_wen_r & !r_d_in.bits.i0div & !i0_load_kill_wen_r // don't write a nonblock load 1st time down the pipe
|
||||
io.dec_i0_wdata_r := i0_result_corr_r
|
||||
|
||||
val i0_result_r_raw = rvdffe(i0_result_x,i0_r_data_en.asBool,clock,io.scan_mode)
|
||||
if ( LOAD_TO_USE_PLUS1 == 1 ) {
|
||||
i0_result_x := io.exu_i0_result_x
|
||||
i0_result_r := Mux((r_d.i0v & r_d.i0load).asBool,io.lsu_result_m, i0_result_r_raw)
|
||||
i0_result_r := Mux((r_d.bits.i0v & r_d.bits.i0load).asBool,io.lsu_result_m, i0_result_r_raw)
|
||||
}
|
||||
else {
|
||||
i0_result_x := Mux((x_d.i0v & x_d.i0load).asBool,io.lsu_result_m,io.exu_i0_result_x)
|
||||
i0_result_x := Mux((x_d.bits.i0v & x_d.bits.i0load).asBool,io.lsu_result_m,io.exu_i0_result_x)
|
||||
i0_result_r := i0_result_r_raw
|
||||
}
|
||||
|
||||
// correct lsu load data - don't use for bypass, do pass down the pipe
|
||||
i0_result_corr_r := Mux((r_d.i0v & r_d.i0load).asBool,io.lsu_result_corr_r,i0_result_r_raw)
|
||||
i0_result_corr_r := Mux((r_d.bits.i0v & r_d.bits.i0load).asBool,io.lsu_result_corr_r,i0_result_r_raw)
|
||||
io.dec_i0_br_immed_d := Mux((io.i0_ap.predict_nt & !i0_dp.jal).asBool,i0_br_offset,Cat(repl(10,0.U),i0_ap_pc4,i0_ap_pc2))
|
||||
val last_br_immed_d = WireInit(UInt(12.W),0.U)
|
||||
last_br_immed_d := Mux((io.i0_ap.predict_nt).asBool,Cat(repl(10,0.U),i0_ap_pc4,i0_ap_pc2),i0_br_offset)
|
||||
|
|
@ -720,16 +720,16 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
|
|||
|
||||
// divide stuff
|
||||
|
||||
val div_e1_to_r = (x_d.i0div & x_d.i0valid) | (r_d.i0div & r_d.i0valid)
|
||||
val div_e1_to_r = (x_d.bits.i0div & x_d.valid) | (r_d.bits.i0div & r_d.valid)
|
||||
|
||||
val div_flush = (x_d.i0div & x_d.i0valid & (x_d.i0rd === 0.U(5.W))) |
|
||||
(x_d.i0div & x_d.i0valid & io.dec_tlu_flush_lower_r ) |
|
||||
(r_d.i0div & r_d.i0valid & io.dec_tlu_flush_lower_r & io.dec_tlu_i0_kill_writeb_r)
|
||||
val div_flush = (x_d.bits.i0div & x_d.valid & (x_d.bits.i0rd === 0.U(5.W))) |
|
||||
(x_d.bits.i0div & x_d.valid & io.dec_tlu_flush_lower_r ) |
|
||||
(r_d.bits.i0div & r_d.valid & io.dec_tlu_flush_lower_r & io.dec_tlu_i0_kill_writeb_r)
|
||||
|
||||
// cancel if any younger inst committing this cycle to same dest as nonblock divide
|
||||
|
||||
val nonblock_div_cancel = (io.dec_div_active & div_flush) |
|
||||
(io.dec_div_active & !div_e1_to_r & (r_d.i0rd === io.div_waddr_wb) & i0_wen_r)
|
||||
(io.dec_div_active & !div_e1_to_r & (r_d.bits.i0rd === io.div_waddr_wb) & i0_wen_r)
|
||||
|
||||
io.dec_div_cancel := nonblock_div_cancel.asBool
|
||||
val i0_div_decode_d = i0_legal_decode_d & i0_dp.div
|
||||
|
|
@ -769,11 +769,11 @@ class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{
|
|||
|
||||
// scheduling logic for primary alu's
|
||||
|
||||
val i0_rs1_depend_i0_x = io.dec_i0_rs1_en_d & x_d.i0v & (x_d.i0rd === i0r.rs1)
|
||||
val i0_rs1_depend_i0_r = io.dec_i0_rs1_en_d & r_d.i0v & (r_d.i0rd === i0r.rs1)
|
||||
val i0_rs1_depend_i0_x = io.dec_i0_rs1_en_d & x_d.bits.i0v & (x_d.bits.i0rd === i0r.rs1)
|
||||
val i0_rs1_depend_i0_r = io.dec_i0_rs1_en_d & r_d.bits.i0v & (r_d.bits.i0rd === i0r.rs1)
|
||||
|
||||
val i0_rs2_depend_i0_x = io.dec_i0_rs2_en_d & x_d.i0v & (x_d.i0rd === i0r.rs2)
|
||||
val i0_rs2_depend_i0_r = io.dec_i0_rs2_en_d & r_d.i0v & (r_d.i0rd === i0r.rs2)
|
||||
val i0_rs2_depend_i0_x = io.dec_i0_rs2_en_d & x_d.bits.i0v & (x_d.bits.i0rd === i0r.rs2)
|
||||
val i0_rs2_depend_i0_r = io.dec_i0_rs2_en_d & r_d.bits.i0v & (r_d.bits.i0rd === i0r.rs2)
|
||||
// order the producers as follows: , i0_x, i0_r, i0_wb
|
||||
i0_rs1_class_d := Mux(i0_rs1_depend_i0_x.asBool,i0_x_c,Mux(i0_rs1_depend_i0_r.asBool, i0_r_c, 0.U.asTypeOf(i0_rs1_class_d)))
|
||||
i0_rs1_depth_d := Mux(i0_rs1_depend_i0_x.asBool,1.U(2.W),Mux(i0_rs1_depend_i0_r.asBool, 2.U(2.W), 0.U))
|
||||
|
|
|
|||
|
|
@ -9,7 +9,7 @@ class el2_dec_ib_ctl_IO extends Bundle with param{
|
|||
val dbg_cmd_write =Input(UInt(1.W)) // dbg cmd is write
|
||||
val dbg_cmd_type =Input(UInt(2.W)) // dbg type
|
||||
val dbg_cmd_addr =Input(UInt(32.W)) // expand to 31:0
|
||||
val i0_brp =Input(new el2_br_pkt_t) // i0 branch packet from aligner
|
||||
val i0_brp =Flipped(Valid(new el2_br_pkt_t)) // i0 branch packet from aligner
|
||||
val ifu_i0_bp_index =Input(UInt(((BTB_ADDR_HI-BTB_ADDR_LO)+1).W)) // BP index(Changed size)
|
||||
val ifu_i0_bp_fghr =Input(UInt((BHT_GHR_SIZE).W)) // BP FGHR
|
||||
val ifu_i0_bp_btag =Input(UInt((BTB_BTAG_SIZE).W)) // BP tag
|
||||
|
|
@ -27,7 +27,7 @@ class el2_dec_ib_ctl_IO extends Bundle with param{
|
|||
val dec_i0_instr_d =Output(UInt(32.W)) // i0 inst at decode
|
||||
val dec_i0_pc_d =Output(UInt(31.W)) // i0 pc at decode
|
||||
val dec_i0_pc4_d =Output(UInt(1.W)) // i0 is 4B inst else 2B
|
||||
val dec_i0_brp =Output(new el2_br_pkt_t) // i0 branch packet at decode
|
||||
val dec_i0_brp =Valid(new el2_br_pkt_t) // i0 branch packet at decode
|
||||
val dec_i0_bp_index =Output(UInt(((BTB_ADDR_HI-BTB_ADDR_LO)+1).W)) // i0 branch index
|
||||
val dec_i0_bp_fghr =Output(UInt(BHT_GHR_SIZE.W)) // BP FGHR
|
||||
val dec_i0_bp_btag =Output(UInt(BTB_BTAG_SIZE.W)) // BP tag
|
||||
|
|
@ -46,7 +46,7 @@ class el2_dec_ib_ctl extends Module with param{
|
|||
io.dec_i0_pc_d :=io.ifu_i0_pc
|
||||
io.dec_i0_pc4_d :=io.ifu_i0_pc4
|
||||
io.dec_i0_icaf_type_d :=io.ifu_i0_icaf_type
|
||||
io.dec_i0_brp :=io.i0_brp
|
||||
io.dec_i0_brp <>io.i0_brp
|
||||
io.dec_i0_bp_index :=io.ifu_i0_bp_index
|
||||
io.dec_i0_bp_fghr :=io.ifu_i0_bp_fghr
|
||||
io.dec_i0_bp_btag :=io.ifu_i0_bp_btag
|
||||
|
|
|
|||
|
|
@ -89,7 +89,7 @@ class el2_dec_tlu_ctl_IO extends Bundle with el2_lib {
|
|||
|
||||
val iccm_dma_sb_error = Input(UInt(1.W)) // I side dma single bit error
|
||||
|
||||
val lsu_error_pkt_r = Input(new el2_lsu_error_pkt_t)// lsu precise exception/error packet
|
||||
val lsu_error_pkt_r = Flipped(Valid(new el2_lsu_error_pkt_t))// lsu precise exception/error packet
|
||||
val lsu_single_ecc_error_incr = Input(UInt(1.W)) // LSU inc SB error counter
|
||||
|
||||
val dec_pause_state = Input(UInt(1.W)) // Pause counter not zero
|
||||
|
|
@ -188,7 +188,7 @@ class el2_dec_tlu_ctl_IO extends Bundle with el2_lib {
|
|||
val dec_tlu_meipt = Output(UInt(4.W)) // to PIC
|
||||
val dec_csr_rddata_d = Output(UInt(32.W)) // csr read data at wb
|
||||
val dec_csr_legal_d = Output(UInt(1.W)) // csr indicates legal operation
|
||||
val dec_tlu_br0_r_pkt = Output(new el2_br_tlu_pkt_t) // branch pkt to bp
|
||||
val dec_tlu_br0_r_pkt = Valid(new el2_br_tlu_pkt_t) // branch pkt to bp
|
||||
val dec_tlu_i0_kill_writeb_wb = Output(UInt(1.W)) // I0 is flushed, don't writeback any results to arch state
|
||||
val dec_tlu_flush_lower_wb = Output(UInt(1.W)) // commit has a flush (exception, int, mispredict at e4)
|
||||
val dec_tlu_i0_commit_cmt = Output(UInt(1.W)) // committed an instruction
|
||||
|
|
@ -389,7 +389,7 @@ class el2_dec_tlu_ctl extends Module with el2_lib with RequireAsyncReset with CS
|
|||
|
||||
// for CSRs that have inpipe writes only
|
||||
val csr_wr_clk=rvclkhdr(clock,(dec_csr_wen_r_mod | clk_override).asBool,io.scan_mode)
|
||||
val lsu_r_wb_clk=rvclkhdr(clock,(io.lsu_error_pkt_r.exc_valid | lsu_exc_valid_r_d1 | clk_override).asBool,io.scan_mode)
|
||||
val lsu_r_wb_clk=rvclkhdr(clock,(io.lsu_error_pkt_r.valid | lsu_exc_valid_r_d1 | clk_override).asBool,io.scan_mode)
|
||||
|
||||
val e4_valid = io.dec_tlu_i0_valid_r
|
||||
val e4e5_valid = e4_valid | e5_valid
|
||||
|
|
@ -685,20 +685,20 @@ class el2_dec_tlu_ctl extends Module with el2_lib with RequireAsyncReset with CS
|
|||
val lsu_single_ecc_error_r =io.lsu_single_ecc_error_incr
|
||||
mdseac_locked_f :=withClock(io.free_clk){RegNext(mdseac_locked_ns,0.U)}
|
||||
val lsu_single_ecc_error_r_d1 =withClock(io.free_clk){RegNext(lsu_single_ecc_error_r,0.U)}
|
||||
val lsu_error_pkt_addr_r =io.lsu_error_pkt_r.addr
|
||||
val lsu_exc_valid_r_raw = io.lsu_error_pkt_r.exc_valid & ~io.dec_tlu_flush_lower_wb
|
||||
lsu_i0_exc_r_raw := io.lsu_error_pkt_r.exc_valid
|
||||
val lsu_error_pkt_addr_r =io.lsu_error_pkt_r.bits.addr
|
||||
val lsu_exc_valid_r_raw = io.lsu_error_pkt_r.valid & ~io.dec_tlu_flush_lower_wb
|
||||
lsu_i0_exc_r_raw := io.lsu_error_pkt_r.valid
|
||||
val lsu_i0_exc_r = lsu_i0_exc_r_raw & lsu_exc_valid_r_raw & ~i0_trigger_hit_r & ~rfpc_i0_r
|
||||
val lsu_exc_valid_r = lsu_i0_exc_r
|
||||
lsu_exc_valid_r_d1 :=withClock(lsu_r_wb_clk){RegNext(lsu_exc_valid_r,0.U)}
|
||||
val lsu_i0_exc_r_d1 =withClock(lsu_r_wb_clk){RegNext(lsu_i0_exc_r,0.U)}
|
||||
val lsu_exc_ma_r = lsu_i0_exc_r & ~io.lsu_error_pkt_r.exc_type
|
||||
val lsu_exc_acc_r = lsu_i0_exc_r & io.lsu_error_pkt_r.exc_type
|
||||
val lsu_exc_st_r = lsu_i0_exc_r & io.lsu_error_pkt_r.inst_type
|
||||
val lsu_exc_ma_r = lsu_i0_exc_r & ~io.lsu_error_pkt_r.bits.exc_type
|
||||
val lsu_exc_acc_r = lsu_i0_exc_r & io.lsu_error_pkt_r.bits.exc_type
|
||||
val lsu_exc_st_r = lsu_i0_exc_r & io.lsu_error_pkt_r.bits.inst_type
|
||||
|
||||
// Single bit ECC errors on loads are RFNPC corrected, with the corrected data written to the GPR.
|
||||
// LSU turns the load into a store and patches the data in the DCCM
|
||||
val lsu_i0_rfnpc_r = io.dec_tlu_i0_valid_r & ~i0_trigger_hit_r & (~io.lsu_error_pkt_r.inst_type & io.lsu_error_pkt_r.single_ecc_error)
|
||||
val lsu_i0_rfnpc_r = io.dec_tlu_i0_valid_r & ~i0_trigger_hit_r & (~io.lsu_error_pkt_r.bits.inst_type & io.lsu_error_pkt_r.bits.single_ecc_error)
|
||||
|
||||
// Final commit valids
|
||||
val tlu_i0_commit_cmt = io.dec_tlu_i0_valid_r & ~rfpc_i0_r & ~lsu_i0_exc_r & ~inst_acc_r & ~io.dec_tlu_dbg_halted & ~request_debug_mode_r_d1 & ~i0_trigger_hit_r
|
||||
|
|
@ -727,12 +727,12 @@ class el2_dec_tlu_ctl extends Module with el2_lib with RequireAsyncReset with CS
|
|||
val dec_tlu_br0_v_r = io.exu_i0_br_valid_r & io.dec_tlu_i0_valid_r & ~tlu_flush_lower_r_d1 & (~io.exu_i0_br_mp_r | ~io.exu_pmu_i0_br_ataken)
|
||||
|
||||
|
||||
io.dec_tlu_br0_r_pkt.hist := io.exu_i0_br_hist_r
|
||||
io.dec_tlu_br0_r_pkt.br_error := dec_tlu_br0_error_r
|
||||
io.dec_tlu_br0_r_pkt.br_start_error := dec_tlu_br0_start_error_r
|
||||
io.dec_tlu_br0_r_pkt.bits.hist := io.exu_i0_br_hist_r
|
||||
io.dec_tlu_br0_r_pkt.bits.br_error := dec_tlu_br0_error_r
|
||||
io.dec_tlu_br0_r_pkt.bits.br_start_error := dec_tlu_br0_start_error_r
|
||||
io.dec_tlu_br0_r_pkt.valid := dec_tlu_br0_v_r
|
||||
io.dec_tlu_br0_r_pkt.way := io.exu_i0_br_way_r
|
||||
io.dec_tlu_br0_r_pkt.middle := io.exu_i0_br_middle_r
|
||||
io.dec_tlu_br0_r_pkt.bits.way := io.exu_i0_br_way_r
|
||||
io.dec_tlu_br0_r_pkt.bits.middle := io.exu_i0_br_middle_r
|
||||
|
||||
|
||||
ebreak_r := (io.dec_tlu_packet_r.pmu_i0_itype === EBREAK) & io.dec_tlu_i0_valid_r & ~i0_trigger_hit_r & ~dcsr(DCSR_EBREAKM) & ~rfpc_i0_r
|
||||
|
|
@ -1343,7 +1343,7 @@ class el2_CSR_IO extends Bundle with el2_lib {
|
|||
val dec_tlu_external_ldfwd_disable = Output(UInt(1.W))
|
||||
val dec_tlu_dma_qos_prty = Output(UInt(3.W))
|
||||
val dec_illegal_inst = Input(UInt(32.W))
|
||||
val lsu_error_pkt_r = Input(new el2_lsu_error_pkt_t)
|
||||
val lsu_error_pkt_r = Flipped(Valid(new el2_lsu_error_pkt_t))
|
||||
val mexintpend = Input(UInt(1.W))
|
||||
val exu_npc_r = Input(UInt(31.W))
|
||||
val mpc_reset_run_req = Input(UInt(1.W))
|
||||
|
|
@ -1741,7 +1741,7 @@ class csr_tlu extends Module with el2_lib with CSRs {
|
|||
val ifu_mscause = Mux((io.dec_tlu_packet_r.icaf_type === 0.U(2.W)), "b1001".U, Cat(0.U(2.W) , io.dec_tlu_packet_r.icaf_type))
|
||||
|
||||
val mscause_type = Mux1H( Seq(
|
||||
io.lsu_i0_exc_r.asBool -> io.lsu_error_pkt_r.mscause,
|
||||
io.lsu_i0_exc_r.asBool -> io.lsu_error_pkt_r.bits.mscause,
|
||||
io.i0_trigger_hit_r.asBool -> "b0001".U,
|
||||
io.ebreak_r.asBool -> "b0010".U,
|
||||
io.inst_acc_r.asBool -> ifu_mscause ))
|
||||
|
|
|
|||
|
|
@ -1,65 +1,51 @@
|
|||
package dmi
|
||||
import chisel3._
|
||||
import scala.collection._
|
||||
import chisel3.util._
|
||||
import include._
|
||||
import lib._
|
||||
|
||||
class dmi_wrapper extends Module with el2_lib with RequireAsyncReset {
|
||||
class dmi_wrapper extends BlackBox with HasBlackBoxResource{
|
||||
val io = IO(new Bundle{
|
||||
// JTAG signals
|
||||
val trst_n = Input(AsyncReset())
|
||||
val tck = Input(Clock()) // JTAG clock
|
||||
val tms =Input(UInt(1.W)) // Test mode select
|
||||
val tdi =Input(UInt(1.W)) // Test Data Input
|
||||
val tdo =Output(UInt(1.W)) // Test Data Output
|
||||
val tdoEnable =Output(UInt(1.W)) // Test Data Output enable
|
||||
|
||||
// Processor Signals
|
||||
// val core_rst_n =Input(UInt(1.W)) // Core reset
|
||||
// val core_clk =Input(UInt(1.W)) // Core clock
|
||||
val jtag_id = Input(UInt(32.W)) // JTAG ID
|
||||
val rd_data = Input(UInt(32.W)) // 32 bit Read data from Processor
|
||||
val reg_wr_data = Output(UInt(32.W)) // 32 bit Write data to Processor
|
||||
val reg_wr_addr = Output(UInt(7.W)) // 7 bit reg address to Processor
|
||||
val reg_en = Output(UInt(1.W)) // 1 bit Read enable to Processor
|
||||
val reg_wr_en = Output(UInt(1.W)) // 1 bit Write enable to Processor
|
||||
val trst_n = Input(Bool())
|
||||
val tck = Input(Clock())
|
||||
val tms = Input(UInt(1.W))
|
||||
val tdi = Input(UInt(1.W))
|
||||
val tdo = Output(UInt(1.W))
|
||||
val tdoEnable = Output(UInt(1.W))
|
||||
val core_rst_n = Input(AsyncReset())
|
||||
val core_clk = Input(Clock())
|
||||
val jtag_id = Input(UInt(31.W))
|
||||
val rd_data = Input(UInt(32.W))
|
||||
val reg_wr_data = Output(UInt(32.W))
|
||||
val reg_wr_addr = Output(UInt(7.W))
|
||||
val reg_en = Output(UInt(1.W))
|
||||
val reg_wr_en = Output(UInt(1.W))
|
||||
val dmi_hard_reset = Output(UInt(1.W))
|
||||
})
|
||||
//Wire Declaration
|
||||
val rd_en = WireInit(0.U(1.W))
|
||||
val wr_en = WireInit(0.U(1.W))
|
||||
val dmireset = WireInit(0.U(1.W))
|
||||
|
||||
//jtag_tap instantiation
|
||||
val i_jtag_tap = Module(new rvjtag_tap())
|
||||
i_jtag_tap.io.trst := io.trst_n // dedicated JTAG TRST (active low) pad signal or asynchronous active low power on reset
|
||||
i_jtag_tap.io.tck := io.tck // dedicated JTAG TCK pad signal
|
||||
i_jtag_tap.io.tms := io.tms // dedicated JTAG TMS pad signal
|
||||
i_jtag_tap.io.tdi := io.tdi // dedicated JTAG TDI pad signal
|
||||
io.tdo := i_jtag_tap.io.tdo // dedicated JTAG TDO pad signal
|
||||
io.tdoEnable := i_jtag_tap.io.tdoEnable // enable for TDO pad
|
||||
io.reg_wr_data := i_jtag_tap.io.wr_data // 32 bit Write data
|
||||
io.reg_wr_addr := i_jtag_tap.io.wr_addr // 7 bit Write address
|
||||
rd_en := i_jtag_tap.io.rd_en // 1 bit read enable
|
||||
wr_en := i_jtag_tap.io.wr_en // 1 bit Write enable
|
||||
i_jtag_tap.io.rd_data := io.rd_data // 32 bit Read data
|
||||
i_jtag_tap.io.rd_status := 0.U(2.W)
|
||||
i_jtag_tap.io.idle := 0.U(3.W) // no need to wait to sample data
|
||||
i_jtag_tap.io.dmi_stat := 0.U(2.W) // no need to wait or error possible
|
||||
i_jtag_tap.io.version := 1.U(4.W) // debug spec 0.13 compliant
|
||||
i_jtag_tap.io.jtag_id := io.jtag_id
|
||||
io.dmi_hard_reset := i_jtag_tap.io.dmi_hard_reset
|
||||
dmireset := i_jtag_tap.io.dmi_reset
|
||||
|
||||
// dmi_jtag_to_core_sync instantiation
|
||||
val i_dmi_jtag_to_core_sync = Module(new dmi_jtag_to_core_sync())
|
||||
i_dmi_jtag_to_core_sync.io.wr_en := wr_en // 1 bit Write enable
|
||||
i_dmi_jtag_to_core_sync.io.rd_en := rd_en // 1 bit Read enable
|
||||
io.reg_en :=i_dmi_jtag_to_core_sync.io.reg_en // 1 bit Write interface bit
|
||||
io.reg_wr_en := i_dmi_jtag_to_core_sync.io.reg_wr_en // 1 bit Write enable
|
||||
addResource("/vsrc/dmi_wrapper.sv")
|
||||
}
|
||||
class dmi_wrapper_module extends Module{
|
||||
val io = IO(new Bundle{
|
||||
val trst_n = Input(Bool())
|
||||
val tck = Input(Clock())
|
||||
val tms = Input(UInt(1.W))
|
||||
val tdi = Input(UInt(1.W))
|
||||
val tdo = Output(UInt(1.W))
|
||||
val tdoEnable = Output(UInt(1.W))
|
||||
val core_rst_n = Input(AsyncReset())
|
||||
val core_clk = Input(Clock())
|
||||
val jtag_id = Input(UInt(32.W))
|
||||
val rd_data = Input(UInt(32.W))
|
||||
val reg_wr_data = Output(UInt(32.W))
|
||||
val reg_wr_addr = Output(UInt(7.W))
|
||||
val reg_en = Output(UInt(1.W))
|
||||
val reg_wr_en = Output(UInt(1.W))
|
||||
val dmi_hard_reset = Output(UInt(1.W))
|
||||
})
|
||||
//addResource("/vsrc/dmi_wrapper.v")
|
||||
val dwrap = Module(new dmi_wrapper)
|
||||
dwrap.io <> io
|
||||
}
|
||||
object dmiwrapper_main extends App{
|
||||
println("Generate Verilog")
|
||||
println((new chisel3.stage.ChiselStage).emitVerilog(new dmi_wrapper()))
|
||||
println((new chisel3.stage.ChiselStage).emitVerilog(new dmi_wrapper_module()))
|
||||
}
|
||||
|
|
|
|||
|
|
@ -234,15 +234,15 @@ class el2_dma_ctrl extends Module with el2_lib with RequireAsyncReset {
|
|||
|
||||
// DCCM Address check
|
||||
|
||||
val (dma_mem_addr_in_dccm,dma_mem_addr_in_dccm_region_nc) = rvrangecheck_ch(dma_mem_addr_int(31,0),DCCM_SADR.U,DCCM_SIZE)
|
||||
val (dma_mem_addr_in_dccm,dma_mem_addr_in_dccm_region_nc) = rvrangecheck_ch(dma_mem_addr_int(31,0),aslong(DCCM_SADR).U,DCCM_SIZE)
|
||||
|
||||
// PIC memory address check
|
||||
|
||||
val (dma_mem_addr_in_pic,dma_mem_addr_in_pic_region_nc) = rvrangecheck_ch(dma_mem_addr_int(31,0),PIC_BASE_ADDR.U,PIC_SIZE)
|
||||
val (dma_mem_addr_in_pic,dma_mem_addr_in_pic_region_nc) = rvrangecheck_ch(dma_mem_addr_int(31,0),aslong(PIC_BASE_ADDR).U,PIC_SIZE)
|
||||
|
||||
// ICCM Address check
|
||||
|
||||
val (dma_mem_addr_in_iccm,dma_mem_addr_in_iccm_region_nc) = if(ICCM_ENABLE) rvrangecheck_ch(dma_mem_addr_int(31,0),ICCM_SADR.U,ICCM_SIZE) else (0.U,0.U)
|
||||
val (dma_mem_addr_in_iccm,dma_mem_addr_in_iccm_region_nc) = if(ICCM_ENABLE) rvrangecheck_ch(dma_mem_addr_int(31,0),aslong(ICCM_SADR).U,ICCM_SIZE) else (0.U,0.U)
|
||||
|
||||
// FIFO inputs
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,101 @@
|
|||
package el2_mem
|
||||
import chisel3._
|
||||
import chisel3.util.HasBlackBoxResource
|
||||
import lib._
|
||||
class Mem_bundle extends Bundle with el2_lib {
|
||||
val clk = Input(Clock())
|
||||
val rst_l = Input(AsyncReset())
|
||||
val dccm_clk_override = Input(Bool())
|
||||
val icm_clk_override = Input(Bool())
|
||||
val dec_tlu_core_ecc_disable = Input(Bool())
|
||||
val dccm_wren = Input(Bool())
|
||||
val dccm_rden = Input(Bool())
|
||||
val dccm_wr_addr_lo = Input(UInt(DCCM_BITS.W))
|
||||
val dccm_wr_addr_hi = Input(UInt(DCCM_BITS.W))
|
||||
val dccm_rd_addr_lo = Input(UInt(DCCM_BITS.W))
|
||||
val dccm_rd_addr_hi = Input(UInt(DCCM_BITS.W))
|
||||
val dccm_wr_data_lo = Input(UInt(DCCM_FDATA_WIDTH.W))
|
||||
val dccm_wr_data_hi = Input(UInt(DCCM_FDATA_WIDTH.W))
|
||||
val dccm_rd_data_lo = Output(UInt(DCCM_FDATA_WIDTH.W))
|
||||
|
||||
val iccm_rw_addr = Input(UInt((ICCM_BITS-1).W))
|
||||
val iccm_buf_correct_ecc = Input(Bool())
|
||||
val iccm_correction_state = Input(Bool())
|
||||
val iccm_wren = Input(Bool())
|
||||
val iccm_rden = Input(Bool())
|
||||
val iccm_wr_size = Input(UInt(3.W))
|
||||
val iccm_wr_data = Input(UInt(78.W))
|
||||
|
||||
|
||||
val ic_rw_addr = Input(UInt(31.W))
|
||||
val ic_tag_valid = Input(UInt(ICACHE_NUM_WAYS.W))
|
||||
val ic_wr_en = Input(UInt(ICACHE_NUM_WAYS.W))
|
||||
val ic_rd_en = Input(Bool())
|
||||
val ic_premux_data = Input(UInt(64.W))
|
||||
val ic_sel_premux_data = Input(Bool())
|
||||
val ic_wr_data = Input(Vec(ICACHE_BANKS_WAY, UInt(71.W)))
|
||||
val ic_debug_wr_data = Input(UInt(71.W))
|
||||
|
||||
val ic_debug_addr = Input(UInt((ICACHE_INDEX_HI-2).W))
|
||||
val ic_debug_rd_en = Input(Bool())
|
||||
val ic_debug_wr_en = Input(Bool())
|
||||
val ic_debug_tag_array = Input(Bool())
|
||||
val ic_debug_way = Input(UInt(ICACHE_NUM_WAYS.W))
|
||||
val scan_mode = Input(Bool())
|
||||
|
||||
val iccm_rd_data_ecc = Output(UInt(78.W))
|
||||
val dccm_rd_data_hi = Output(UInt(DCCM_FDATA_WIDTH.W))
|
||||
val ic_rd_data = Output(UInt(64.W))
|
||||
val ictag_debug_rd_data = Output(UInt(26.W))
|
||||
val ic_eccerr = Output(UInt(ICACHE_BANKS_WAY.W))
|
||||
val ic_parerr = Output(UInt(ICACHE_BANKS_WAY.W))
|
||||
val ic_rd_hit = Output(UInt(ICACHE_NUM_WAYS.W))
|
||||
val ic_tag_perr = Output(Bool())
|
||||
val ic_debug_rd_data = Output(UInt(71.W))
|
||||
val iccm_rd_data = Output(UInt(64.W))
|
||||
|
||||
}
|
||||
object waleed extends el2_lib {
|
||||
class el2_mem extends BlackBox(Map("DCCM_BITS" -> DCCM_BITS,
|
||||
"DCCM_FDATA_WIDTH" -> DCCM_FDATA_WIDTH,
|
||||
"ICCM_BITS" -> ICCM_BITS,
|
||||
"ICACHE_NUM_WAYS" -> ICACHE_NUM_WAYS,
|
||||
"ICACHE_BANKS_WAY" -> ICACHE_BANKS_WAY,
|
||||
"ICACHE_INDEX_HI" -> ICACHE_INDEX_HI,
|
||||
"DCCM_ENABLE" -> bool2int(DCCM_ENABLE),
|
||||
"ICACHE_ENABLE" -> bool2int(ICCM_ENABLE),
|
||||
"ICCM_ENABLE" -> bool2int(ICCM_ENABLE),
|
||||
"ICACHE_TAG_INDEX_LO" -> ICACHE_TAG_INDEX_LO,
|
||||
"ICACHE_DATA_INDEX_LO" -> ICACHE_DATA_INDEX_LO,
|
||||
"ICACHE_TAG_LO" -> ICACHE_TAG_LO,
|
||||
"ICACHE_BANK_LO" -> ICACHE_BANK_LO,
|
||||
"ICACHE_BANK_HI" -> ICACHE_BANK_HI,
|
||||
"ICACHE_WAYPACK" -> bool2int(ICACHE_WAYPACK),
|
||||
"ICACHE_ECC" -> bool2int(ICACHE_ECC),
|
||||
"ICACHE_DATA_DEPTH" -> ICACHE_DATA_DEPTH,
|
||||
"ICACHE_BANK_BITS" -> ICACHE_BANK_BITS,
|
||||
"ICACHE_BEAT_ADDR_HI" -> ICACHE_BEAT_ADDR_HI,
|
||||
"ICACHE_BEAT_BITS" -> ICACHE_BEAT_BITS,
|
||||
"ICACHE_TAG_DEPTH" -> ICACHE_TAG_DEPTH,
|
||||
"ICCM_BANK_INDEX_LO" -> ICCM_BANK_INDEX_LO,
|
||||
"ICCM_NUM_BANKS" -> ICCM_NUM_BANKS,
|
||||
"ICCM_BANK_HI" -> ICCM_BANK_HI,
|
||||
"ICCM_INDEX_BITS" -> ICCM_INDEX_BITS,
|
||||
"ICCM_BANK_BITS" -> ICCM_BANK_BITS,
|
||||
"DCCM_BYTE_WIDTH" -> DCCM_BYTE_WIDTH,
|
||||
"DCCM_BANK_BITS" -> DCCM_BANK_BITS,
|
||||
"DCCM_SIZE" -> DCCM_SIZE,
|
||||
"DCCM_NUM_BANKS" -> DCCM_NUM_BANKS)) with HasBlackBoxResource {
|
||||
val io = IO(new Mem_bundle)
|
||||
addResource("/vsrc/el2_mem.sv")
|
||||
}
|
||||
}
|
||||
class blackbox_mem extends Module with el2_lib {
|
||||
val io = IO(new Mem_bundle)
|
||||
val it = Module(new waleed.el2_mem)
|
||||
io <> it.io
|
||||
}
|
||||
|
||||
object mem extends App {
|
||||
println((new chisel3.stage.ChiselStage).emitVerilog(new blackbox_mem))
|
||||
}
|
||||
|
|
@ -29,16 +29,8 @@ class el2_pic_ctrl extends Module with RequireAsyncReset with el2_lib {
|
|||
|
||||
})
|
||||
|
||||
//def el2_cmp_and_mux (a_id : UInt, a_priority : UInt, b_id : UInt, b_priority : UInt) =
|
||||
// (Mux(a_priority<b_priority, b_id, a_id), Mux(a_priority<b_priority, b_priority, a_priority))
|
||||
|
||||
def el2_cmp_and_mux (a_id : UInt, a_priority : UInt, b_id : UInt, b_priority : UInt) = {
|
||||
val out_id = WireInit(UInt(ID_BITS.W),init= 0.U)
|
||||
val out_priority = WireInit(UInt(INTPRIORITY_BITS.W),init= 0.U)
|
||||
out_id := Mux(a_priority<b_priority, b_id, a_id)
|
||||
out_priority := Mux(a_priority<b_priority, b_priority, a_priority)
|
||||
(out_id,out_priority)
|
||||
}
|
||||
def el2_cmp_and_mux (a_id : UInt, a_priority : UInt, b_id : UInt, b_priority : UInt) =
|
||||
(Mux(a_priority<b_priority, b_id, a_id), Mux(a_priority<b_priority, b_priority, a_priority))
|
||||
|
||||
def el2_configurable_gw (extintsrc_req_sync : UInt, meigwctrl_polarity : UInt, meigwctrl_type : UInt, meigwclr : UInt) = {
|
||||
val gw_int_pending = WireInit(UInt(1.W),0.U)
|
||||
|
|
|
|||
|
|
@ -8,7 +8,69 @@ import chisel3.experimental.chiselName
|
|||
|
||||
@chiselName
|
||||
class el2_exu extends Module with el2_lib with RequireAsyncReset{
|
||||
val io=IO(new el2_exu_IO)
|
||||
val io=IO(new Bundle{
|
||||
val scan_mode =Input(Bool()) // Scan control
|
||||
val dec_data_en =Input(UInt(2.W)) // Clock enable {x,r}, one cycle pulse
|
||||
val dec_ctl_en =Input(UInt(2.W)) // Clock enable {x,r}, two cycle pulse
|
||||
val dbg_cmd_wrdata =Input(UInt(32.W)) // Debug data to primary I0 RS1
|
||||
val i0_ap =Input(new el2_alu_pkt_t) // DEC alu {valid,predecodes}
|
||||
val dec_debug_wdata_rs1_d =Input(UInt(1.W)) // Debug select to primary I0 RS1
|
||||
val dec_i0_predict_p_d =Flipped(Valid(new el2_predict_pkt_t)) // DEC branch predict packet
|
||||
val i0_predict_fghr_d =Input(UInt(BHT_GHR_SIZE.W)) // DEC predict fghr
|
||||
val i0_predict_index_d =Input(UInt(((BTB_ADDR_HI-BTB_ADDR_LO)+1).W)) // DEC predict index
|
||||
val i0_predict_btag_d =Input(UInt(BTB_BTAG_SIZE.W)) // DEC predict branch tag
|
||||
val dec_i0_rs1_en_d =Input(UInt(1.W)) // Qualify GPR RS1 data
|
||||
val dec_i0_rs2_en_d =Input(UInt(1.W)) // Qualify GPR RS2 data
|
||||
val gpr_i0_rs1_d =Input(UInt(32.W)) // DEC data gpr
|
||||
val gpr_i0_rs2_d =Input(UInt(32.W)) // DEC data gpr
|
||||
val dec_i0_immed_d =Input(UInt(32.W)) // DEC data immediate
|
||||
val dec_i0_rs1_bypass_data_d=Input(UInt(32.W)) // DEC bypass data
|
||||
val dec_i0_rs2_bypass_data_d=Input(UInt(32.W)) // DEC bypass data
|
||||
val dec_i0_br_immed_d =Input(UInt(12.W)) // Branch immediate
|
||||
val dec_i0_alu_decode_d =Input(UInt(1.W)) // Valid to X-stage ALU
|
||||
val dec_i0_select_pc_d =Input(UInt(1.W)) // PC select to RS1
|
||||
val dec_i0_pc_d =Input(UInt(31.W)) // Instruction PC
|
||||
val dec_i0_rs1_bypass_en_d =Input(UInt(2.W)) // DEC bypass select 1 - X-stage, 0 - dec bypass data
|
||||
val dec_i0_rs2_bypass_en_d =Input(UInt(2.W)) // DEC bypass select 1 - X-stage, 0 - dec bypass data
|
||||
val dec_csr_ren_d =Input(UInt(1.W)) // Clear I0 RS1 primary
|
||||
val mul_p =Flipped(Valid(new el2_mul_pkt_t)) // DEC {valid, operand signs, low, operand bypass}
|
||||
val div_p =Flipped(Valid(new el2_div_pkt_t)) // DEC {valid, unsigned, rem}
|
||||
val dec_div_cancel =Input(UInt(1.W)) // Cancel the divide operation
|
||||
val pred_correct_npc_x =Input(UInt(31.W)) // DEC NPC for correctly predicted branch
|
||||
val dec_tlu_flush_lower_r =Input(UInt(1.W)) // Flush divide and secondary ALUs
|
||||
val dec_tlu_flush_path_r =Input(UInt(31.W)) // Redirect target
|
||||
val dec_extint_stall =Input(UInt(1.W)) // External stall mux select
|
||||
val dec_tlu_meihap =Input(UInt(30.W)) // External stall mux data
|
||||
val exu_lsu_rs1_d =Output(UInt(32.W)) // LSU operand
|
||||
val exu_lsu_rs2_d =Output(UInt(32.W)) // LSU operand
|
||||
|
||||
val exu_flush_final =Output(UInt(1.W)) // Pipe is being flushed this cycle
|
||||
val exu_flush_path_final =Output(UInt(31.W)) // Target for the oldest flush source
|
||||
val exu_i0_result_x =Output(UInt(32.W)) // Primary ALU result to DEC
|
||||
val exu_i0_pc_x =Output(UInt(31.W)) // Primary PC result to DEC
|
||||
val exu_csr_rs1_x =Output(UInt(32.W)) // RS1 source for a CSR instruction
|
||||
val exu_npc_r =Output(UInt(31.W)) // Divide NPC
|
||||
val exu_i0_br_hist_r =Output(UInt(2.W)) // to DEC I0 branch history
|
||||
val exu_i0_br_error_r =Output(UInt(1.W)) // to DEC I0 branch error
|
||||
val exu_i0_br_start_error_r =Output(UInt(1.W)) // to DEC I0 branch start error
|
||||
val exu_i0_br_index_r =Output(UInt(((BTB_ADDR_HI-BTB_ADDR_LO)+1).W)) // to DEC I0 branch index
|
||||
val exu_i0_br_valid_r =Output(UInt(1.W)) // to DEC I0 branch valid
|
||||
val exu_i0_br_mp_r =Output(UInt(1.W)) // to DEC I0 branch mispredict
|
||||
val exu_i0_br_middle_r =Output(UInt(1.W)) // to DEC I0 branch middle
|
||||
val exu_i0_br_fghr_r =Output(UInt(BHT_GHR_SIZE.W)) // to DEC I0 branch fghr
|
||||
val exu_i0_br_way_r =Output(UInt(1.W)) // to DEC I0 branch way
|
||||
val exu_mp_pkt =Valid(new el2_predict_pkt_t) // Mispredict branch packet
|
||||
val exu_mp_eghr =Output(UInt(BHT_GHR_SIZE.W)) // Mispredict global history
|
||||
val exu_mp_fghr =Output(UInt(BHT_GHR_SIZE.W)) // Mispredict fghr
|
||||
val exu_mp_index =Output(UInt(((BTB_ADDR_HI-BTB_ADDR_LO)+1).W)) // Mispredict index
|
||||
val exu_mp_btag =Output(UInt(BTB_BTAG_SIZE.W)) // Mispredict btag
|
||||
val exu_pmu_i0_br_misp =Output(UInt(1.W)) // to PMU - I0 E4 branch mispredict
|
||||
val exu_pmu_i0_br_ataken =Output(UInt(1.W)) // to PMU - I0 E4 taken
|
||||
val exu_pmu_i0_pc4 =Output(UInt(1.W)) // to PMU - I0 E4 PC
|
||||
val exu_div_result =Output(UInt(32.W)) // Divide result
|
||||
val exu_div_wren =Output(UInt(1.W)) // Divide write enable to GPR
|
||||
})
|
||||
|
||||
val PREDPIPESIZE = BTB_ADDR_HI - BTB_ADDR_LO + BHT_GHR_SIZE + BTB_BTAG_SIZE +1
|
||||
val ghr_x_ns = Wire(UInt(BHT_GHR_SIZE.W))
|
||||
val ghr_d_ns = Wire(UInt(BHT_GHR_SIZE.W))
|
||||
|
|
@ -19,20 +81,20 @@ class el2_exu extends Module with el2_lib with RequireAsyncReset{
|
|||
val flush_lower_ff =Wire(UInt(1.W))
|
||||
val data_gate_en =Wire(UInt(1.W))
|
||||
val csr_rs1_in_d =Wire(UInt(32.W))
|
||||
val i0_predict_newp_d =Wire(new el2_predict_pkt_t)
|
||||
val i0_predict_newp_d =Wire(Valid(new el2_predict_pkt_t))
|
||||
val i0_flush_path_d =Wire(UInt(31.W))
|
||||
val i0_predict_p_d =Wire(new el2_predict_pkt_t)
|
||||
val i0_pp_r =Wire(new el2_predict_pkt_t)
|
||||
val i0_predict_p_x =Wire(new el2_predict_pkt_t)
|
||||
val final_predict_mp =Wire(new el2_predict_pkt_t)
|
||||
val i0_predict_p_d =Wire(Valid(new el2_predict_pkt_t))
|
||||
val i0_pp_r =Wire(Valid(new el2_predict_pkt_t))
|
||||
val i0_predict_p_x =Wire(Valid(new el2_predict_pkt_t))
|
||||
val final_predict_mp =Wire(Valid(new el2_predict_pkt_t))
|
||||
val pred_correct_npc_r =Wire(UInt(32.W))
|
||||
val i0_pred_correct_upper_d =Wire(UInt(1.W))
|
||||
val i0_flush_upper_d =Wire(UInt(1.W))
|
||||
io.exu_mp_pkt.prett :=0.U
|
||||
io.exu_mp_pkt.br_start_error:=0.U
|
||||
io.exu_mp_pkt.br_error :=0.U
|
||||
io.exu_mp_pkt.bits.prett :=0.U
|
||||
io.exu_mp_pkt.bits.br_start_error:=0.U
|
||||
io.exu_mp_pkt.bits.br_error :=0.U
|
||||
io.exu_mp_pkt.valid :=0.U
|
||||
i0_pp_r.toffset := 0.U
|
||||
i0_pp_r.bits.toffset := 0.U
|
||||
|
||||
val x_data_en = io.dec_data_en(1)
|
||||
val r_data_en = io.dec_data_en(0)
|
||||
|
|
@ -85,37 +147,37 @@ class el2_exu extends Module with el2_lib with RequireAsyncReset{
|
|||
|
||||
val i0_rs1_d = Mux1H(Seq(
|
||||
i0_rs1_bypass_en_d.asBool -> i0_rs1_bypass_data_d,
|
||||
(~i0_rs1_bypass_en_d & io.dec_i0_select_pc_d).asBool -> Cat(io.dec_i0_pc_d,0.U(1.W)),
|
||||
(~i0_rs1_bypass_en_d & io.dec_debug_wdata_rs1_d).asBool -> io.dbg_cmd_wrdata,
|
||||
(~i0_rs1_bypass_en_d & ~io.dec_debug_wdata_rs1_d & io.dec_i0_rs1_en_d).asBool -> io.gpr_i0_rs1_d
|
||||
(!i0_rs1_bypass_en_d & io.dec_i0_select_pc_d).asBool -> Cat(io.dec_i0_pc_d,0.U(1.W)),
|
||||
(!i0_rs1_bypass_en_d & io.dec_debug_wdata_rs1_d).asBool -> io.dbg_cmd_wrdata,
|
||||
(!i0_rs1_bypass_en_d & !io.dec_debug_wdata_rs1_d & io.dec_i0_rs1_en_d).asBool -> io.gpr_i0_rs1_d
|
||||
))
|
||||
|
||||
val i0_rs2_d = Mux1H(Seq(
|
||||
(~i0_rs2_bypass_en_d & io.dec_i0_rs2_en_d).asBool -> io.gpr_i0_rs2_d,
|
||||
(~i0_rs2_bypass_en_d).asBool -> io.dec_i0_immed_d,
|
||||
(!i0_rs2_bypass_en_d & io.dec_i0_rs2_en_d).asBool -> io.gpr_i0_rs2_d,
|
||||
(!i0_rs2_bypass_en_d).asBool -> io.dec_i0_immed_d,
|
||||
(i0_rs2_bypass_en_d).asBool -> i0_rs2_bypass_data_d
|
||||
))
|
||||
dontTouch(i0_rs2_d)
|
||||
|
||||
io.exu_lsu_rs1_d:=Mux1H(Seq(
|
||||
(~i0_rs1_bypass_en_d & ~io.dec_extint_stall & io.dec_i0_rs1_en_d).asBool -> io.gpr_i0_rs1_d,
|
||||
(i0_rs1_bypass_en_d & ~io.dec_extint_stall).asBool -> i0_rs1_bypass_data_d,
|
||||
(!i0_rs1_bypass_en_d & !io.dec_extint_stall & io.dec_i0_rs1_en_d).asBool -> io.gpr_i0_rs1_d,
|
||||
(i0_rs1_bypass_en_d & !io.dec_extint_stall).asBool -> i0_rs1_bypass_data_d,
|
||||
(io.dec_extint_stall).asBool -> Cat(io.dec_tlu_meihap,0.U(2.W))
|
||||
))
|
||||
|
||||
io.exu_lsu_rs2_d:=Mux1H(Seq(
|
||||
(~i0_rs2_bypass_en_d & ~io.dec_extint_stall & io.dec_i0_rs2_en_d).asBool -> io.gpr_i0_rs2_d,
|
||||
(i0_rs2_bypass_en_d & ~io.dec_extint_stall).asBool -> i0_rs2_bypass_data_d
|
||||
(!i0_rs2_bypass_en_d & !io.dec_extint_stall & io.dec_i0_rs2_en_d).asBool -> io.gpr_i0_rs2_d,
|
||||
(i0_rs2_bypass_en_d & !io.dec_extint_stall).asBool -> i0_rs2_bypass_data_d
|
||||
))
|
||||
|
||||
val muldiv_rs1_d=Mux1H(Seq(
|
||||
(~i0_rs1_bypass_en_d & io.dec_i0_rs1_en_d).asBool -> io.gpr_i0_rs1_d,
|
||||
(!i0_rs1_bypass_en_d & io.dec_i0_rs1_en_d).asBool -> io.gpr_i0_rs1_d,
|
||||
(i0_rs1_bypass_en_d).asBool -> i0_rs1_bypass_data_d
|
||||
))
|
||||
|
||||
val muldiv_rs2_d=Mux1H(Seq(
|
||||
(~i0_rs2_bypass_en_d & io.dec_i0_rs2_en_d).asBool -> io.gpr_i0_rs2_d,
|
||||
(~i0_rs2_bypass_en_d).asBool -> io.dec_i0_immed_d,
|
||||
(!i0_rs2_bypass_en_d & io.dec_i0_rs2_en_d).asBool -> io.gpr_i0_rs2_d,
|
||||
(!i0_rs2_bypass_en_d).asBool -> io.dec_i0_immed_d,
|
||||
(i0_rs2_bypass_en_d).asBool -> i0_rs2_bypass_data_d
|
||||
))
|
||||
|
||||
|
|
@ -161,22 +223,22 @@ class el2_exu extends Module with el2_lib with RequireAsyncReset{
|
|||
|
||||
io.exu_i0_result_x := Mux(mul_valid_x.asBool, mul_result_x, alu_result_x)
|
||||
i0_predict_newp_d := io.dec_i0_predict_p_d
|
||||
i0_predict_newp_d.boffset := io.dec_i0_pc_d(0) // from the start of inst
|
||||
i0_predict_newp_d.bits.boffset := io.dec_i0_pc_d(0) // from the start of inst
|
||||
|
||||
io.exu_pmu_i0_br_misp := i0_pp_r.misp
|
||||
io.exu_pmu_i0_br_ataken := i0_pp_r.ataken
|
||||
io.exu_pmu_i0_pc4 := i0_pp_r.pc4
|
||||
io.exu_pmu_i0_br_misp := i0_pp_r.bits.misp
|
||||
io.exu_pmu_i0_br_ataken := i0_pp_r.bits.ataken
|
||||
io.exu_pmu_i0_pc4 := i0_pp_r.bits.pc4
|
||||
|
||||
|
||||
i0_valid_d := i0_predict_p_d.valid & io.dec_i0_alu_decode_d & ~io.dec_tlu_flush_lower_r
|
||||
i0_taken_d := (i0_predict_p_d.ataken & io.dec_i0_alu_decode_d)
|
||||
i0_valid_d := i0_predict_p_d.valid & io.dec_i0_alu_decode_d & !io.dec_tlu_flush_lower_r
|
||||
i0_taken_d := (i0_predict_p_d.bits.ataken & io.dec_i0_alu_decode_d)
|
||||
|
||||
|
||||
|
||||
// maintain GHR at D
|
||||
ghr_d_ns:=Mux1H(Seq(
|
||||
(~io.dec_tlu_flush_lower_r & i0_valid_d).asBool -> Cat(ghr_d(BHT_GHR_SIZE-2,0),i0_taken_d),
|
||||
(~io.dec_tlu_flush_lower_r & ~i0_valid_d).asBool -> ghr_d,
|
||||
(!io.dec_tlu_flush_lower_r & i0_valid_d).asBool -> Cat(ghr_d(BHT_GHR_SIZE-2,0),i0_taken_d),
|
||||
(!io.dec_tlu_flush_lower_r & !i0_valid_d).asBool -> ghr_d,
|
||||
(io.dec_tlu_flush_lower_r).asBool -> ghr_x
|
||||
))
|
||||
|
||||
|
|
@ -184,30 +246,30 @@ class el2_exu extends Module with el2_lib with RequireAsyncReset{
|
|||
ghr_x_ns:=Mux(i0_valid_x===1.U, Cat(ghr_x(BHT_GHR_SIZE-2,0),i0_taken_x), ghr_x )
|
||||
|
||||
io.exu_i0_br_valid_r := i0_pp_r.valid
|
||||
io.exu_i0_br_mp_r := i0_pp_r.misp
|
||||
io.exu_i0_br_way_r := i0_pp_r.way
|
||||
io.exu_i0_br_hist_r := i0_pp_r.hist
|
||||
io.exu_i0_br_error_r := i0_pp_r.br_error
|
||||
io.exu_i0_br_middle_r := i0_pp_r.pc4 ^ i0_pp_r.boffset
|
||||
io.exu_i0_br_start_error_r := i0_pp_r.br_start_error
|
||||
io.exu_i0_br_mp_r := i0_pp_r.bits.misp
|
||||
io.exu_i0_br_way_r := i0_pp_r.bits.way
|
||||
io.exu_i0_br_hist_r := i0_pp_r.bits.hist
|
||||
io.exu_i0_br_error_r := i0_pp_r.bits.br_error
|
||||
io.exu_i0_br_middle_r := i0_pp_r.bits.pc4 ^ i0_pp_r.bits.boffset
|
||||
io.exu_i0_br_start_error_r := i0_pp_r.bits.br_start_error
|
||||
io.exu_i0_br_fghr_r := predpipe_r(PREDPIPESIZE-1,BTB_ADDR_HI+BTB_BTAG_SIZE-BTB_ADDR_LO+1)
|
||||
io.exu_i0_br_index_r := predpipe_r(BTB_ADDR_HI+BTB_BTAG_SIZE-BTB_ADDR_LO,BTB_BTAG_SIZE)
|
||||
final_predict_mp := Mux(i0_flush_upper_x===1.U,i0_predict_p_x,0.U.asTypeOf(i0_predict_p_x))
|
||||
val final_predpipe_mp = Mux(i0_flush_upper_x===1.U,predpipe_x,0.U)
|
||||
|
||||
val after_flush_eghr = Mux((i0_flush_upper_x===1.U & ~(io.dec_tlu_flush_lower_r===1.U)), ghr_d, ghr_x)
|
||||
val after_flush_eghr = Mux((i0_flush_upper_x===1.U & !(io.dec_tlu_flush_lower_r===1.U)), ghr_d, ghr_x)
|
||||
|
||||
|
||||
io.exu_mp_pkt.way := final_predict_mp.way
|
||||
io.exu_mp_pkt.misp := final_predict_mp.misp
|
||||
io.exu_mp_pkt.pcall := final_predict_mp.pcall
|
||||
io.exu_mp_pkt.pja := final_predict_mp.pja
|
||||
io.exu_mp_pkt.pret := final_predict_mp.pret
|
||||
io.exu_mp_pkt.ataken := final_predict_mp.ataken
|
||||
io.exu_mp_pkt.boffset := final_predict_mp.boffset
|
||||
io.exu_mp_pkt.pc4 := final_predict_mp.pc4
|
||||
io.exu_mp_pkt.hist := final_predict_mp.hist(1,0)
|
||||
io.exu_mp_pkt.toffset := final_predict_mp.toffset(11,0)
|
||||
io.exu_mp_pkt.bits.way := final_predict_mp.bits.way
|
||||
io.exu_mp_pkt.bits.misp := final_predict_mp.bits.misp
|
||||
io.exu_mp_pkt.bits.pcall := final_predict_mp.bits.pcall
|
||||
io.exu_mp_pkt.bits.pja := final_predict_mp.bits.pja
|
||||
io.exu_mp_pkt.bits.pret := final_predict_mp.bits.pret
|
||||
io.exu_mp_pkt.bits.ataken := final_predict_mp.bits.ataken
|
||||
io.exu_mp_pkt.bits.boffset := final_predict_mp.bits.boffset
|
||||
io.exu_mp_pkt.bits.pc4 := final_predict_mp.bits.pc4
|
||||
io.exu_mp_pkt.bits.hist := final_predict_mp.bits.hist(1,0)
|
||||
io.exu_mp_pkt.bits.toffset := final_predict_mp.bits.toffset(11,0)
|
||||
io.exu_mp_fghr := after_flush_eghr
|
||||
io.exu_mp_index := final_predpipe_mp(PREDPIPESIZE-BHT_GHR_SIZE-1,BTB_BTAG_SIZE)
|
||||
io.exu_mp_btag := final_predpipe_mp(BTB_BTAG_SIZE-1,0)
|
||||
|
|
@ -215,85 +277,6 @@ class el2_exu extends Module with el2_lib with RequireAsyncReset{
|
|||
io.exu_flush_path_final := Mux(io.dec_tlu_flush_lower_r.asBool, io.dec_tlu_flush_path_r, i0_flush_path_d)
|
||||
io.exu_npc_r := Mux(i0_pred_correct_upper_r===1.U, pred_correct_npc_r, i0_flush_path_upper_r)
|
||||
}
|
||||
class el2_exu_IO extends Bundle with param{
|
||||
val scan_mode =Input(Bool()) // Scan control
|
||||
|
||||
val dec_data_en =Input(UInt(2.W)) // Clock enable {x,r}, one cycle pulse
|
||||
val dec_ctl_en =Input(UInt(2.W)) // Clock enable {x,r}, two cycle pulse
|
||||
val dbg_cmd_wrdata =Input(UInt(32.W)) // Debug data to primary I0 RS1
|
||||
val i0_ap =Input(new el2_alu_pkt_t) // DEC alu {valid,predecodes}
|
||||
|
||||
val dec_debug_wdata_rs1_d =Input(UInt(1.W)) // Debug select to primary I0 RS1
|
||||
val dec_i0_predict_p_d =Input(new el2_predict_pkt_t) // DEC branch predict packet
|
||||
|
||||
val i0_predict_fghr_d =Input(UInt(BHT_GHR_SIZE.W)) // DEC predict fghr
|
||||
val i0_predict_index_d =Input(UInt(((BTB_ADDR_HI-BTB_ADDR_LO)+1).W)) // DEC predict index
|
||||
val i0_predict_btag_d =Input(UInt(BTB_BTAG_SIZE.W)) // DEC predict branch tag
|
||||
|
||||
val dec_i0_rs1_en_d =Input(UInt(1.W)) // Qualify GPR RS1 data
|
||||
val dec_i0_rs2_en_d =Input(UInt(1.W)) // Qualify GPR RS2 data
|
||||
val gpr_i0_rs1_d =Input(UInt(32.W)) // DEC data gpr
|
||||
val gpr_i0_rs2_d =Input(UInt(32.W)) // DEC data gpr
|
||||
val dec_i0_immed_d =Input(UInt(32.W)) // DEC data immediate
|
||||
val dec_i0_rs1_bypass_data_d=Input(UInt(32.W)) // DEC bypass data
|
||||
val dec_i0_rs2_bypass_data_d=Input(UInt(32.W)) // DEC bypass data
|
||||
val dec_i0_br_immed_d =Input(UInt(12.W)) // Branch immediate
|
||||
val dec_i0_alu_decode_d =Input(UInt(1.W)) // Valid to X-stage ALU
|
||||
val dec_i0_select_pc_d =Input(UInt(1.W)) // PC select to RS1
|
||||
val dec_i0_pc_d =Input(UInt(31.W)) // Instruction PC
|
||||
val dec_i0_rs1_bypass_en_d =Input(UInt(2.W)) // DEC bypass select 1 - X-stage, 0 - dec bypass data
|
||||
val dec_i0_rs2_bypass_en_d =Input(UInt(2.W)) // DEC bypass select 1 - X-stage, 0 - dec bypass data
|
||||
val dec_csr_ren_d =Input(UInt(1.W)) // Clear I0 RS1 primary
|
||||
|
||||
val mul_p =Input(new el2_mul_pkt_t) // DEC {valid, operand signs, low, operand bypass}
|
||||
val div_p =Input(new el2_div_pkt_t) // DEC {valid, unsigned, rem}
|
||||
val dec_div_cancel =Input(UInt(1.W)) // Cancel the divide operation
|
||||
|
||||
val pred_correct_npc_x =Input(UInt(31.W)) // DEC NPC for correctly predicted branch
|
||||
|
||||
val dec_tlu_flush_lower_r =Input(UInt(1.W)) // Flush divide and secondary ALUs
|
||||
val dec_tlu_flush_path_r =Input(UInt(31.W)) // Redirect target
|
||||
|
||||
|
||||
val dec_extint_stall =Input(UInt(1.W)) // External stall mux select
|
||||
val dec_tlu_meihap =Input(UInt(30.W)) // External stall mux data
|
||||
|
||||
|
||||
val exu_lsu_rs1_d =Output(UInt(32.W)) // LSU operand
|
||||
val exu_lsu_rs2_d =Output(UInt(32.W)) // LSU operand
|
||||
|
||||
val exu_flush_final =Output(UInt(1.W)) // Pipe is being flushed this cycle
|
||||
val exu_flush_path_final =Output(UInt(31.W)) // Target for the oldest flush source
|
||||
|
||||
val exu_i0_result_x =Output(UInt(32.W)) // Primary ALU result to DEC
|
||||
val exu_i0_pc_x =Output(UInt(31.W)) // Primary PC result to DEC
|
||||
val exu_csr_rs1_x =Output(UInt(32.W)) // RS1 source for a CSR instruction
|
||||
|
||||
val exu_npc_r =Output(UInt(31.W)) // Divide NPC
|
||||
val exu_i0_br_hist_r =Output(UInt(2.W)) // to DEC I0 branch history
|
||||
val exu_i0_br_error_r =Output(UInt(1.W)) // to DEC I0 branch error
|
||||
val exu_i0_br_start_error_r =Output(UInt(1.W)) // to DEC I0 branch start error
|
||||
val exu_i0_br_index_r =Output(UInt(((BTB_ADDR_HI-BTB_ADDR_LO)+1).W)) // to DEC I0 branch index
|
||||
val exu_i0_br_valid_r =Output(UInt(1.W)) // to DEC I0 branch valid
|
||||
val exu_i0_br_mp_r =Output(UInt(1.W)) // to DEC I0 branch mispredict
|
||||
val exu_i0_br_middle_r =Output(UInt(1.W)) // to DEC I0 branch middle
|
||||
val exu_i0_br_fghr_r =Output(UInt(BHT_GHR_SIZE.W)) // to DEC I0 branch fghr
|
||||
val exu_i0_br_way_r =Output(UInt(1.W)) // to DEC I0 branch way
|
||||
val exu_mp_pkt =Output(new el2_predict_pkt_t) // Mispredict branch packet
|
||||
val exu_mp_eghr =Output(UInt(BHT_GHR_SIZE.W)) // Mispredict global history
|
||||
val exu_mp_fghr =Output(UInt(BHT_GHR_SIZE.W)) // Mispredict fghr
|
||||
val exu_mp_index =Output(UInt(((BTB_ADDR_HI-BTB_ADDR_LO)+1).W)) // Mispredict index
|
||||
val exu_mp_btag =Output(UInt(BTB_BTAG_SIZE.W)) // Mispredict btag
|
||||
|
||||
|
||||
val exu_pmu_i0_br_misp =Output(UInt(1.W)) // to PMU - I0 E4 branch mispredict
|
||||
val exu_pmu_i0_br_ataken =Output(UInt(1.W)) // to PMU - I0 E4 taken
|
||||
val exu_pmu_i0_pc4 =Output(UInt(1.W)) // to PMU - I0 E4 PC
|
||||
|
||||
|
||||
val exu_div_result =Output(UInt(32.W)) // Divide result
|
||||
val exu_div_wren =Output(UInt(1.W)) // Divide write enable to GPR
|
||||
}
|
||||
|
||||
object exu_gen extends App{
|
||||
println(chisel3.Driver.emitVerilog(new el2_exu()))
|
||||
|
|
|
|||
|
|
@ -20,7 +20,7 @@ class el2_exu_alu_ctl extends Module with el2_lib with RequireAsyncReset{
|
|||
val a_in = Input(SInt(32.W)) // A operand
|
||||
val b_in = Input(UInt(32.W)) // B operand
|
||||
val pc_in = Input(UInt(31.W)) // for pc=pc+2,4 calculations
|
||||
val pp_in = Input(new el2_predict_pkt_t) // Predicted branch structure
|
||||
val pp_in = Flipped(Valid(new el2_predict_pkt_t)) // Predicted branch structure
|
||||
val brimm_in = Input(UInt(12.W)) // Branch offset
|
||||
////////// Outputs /////////
|
||||
val result_ff = Output(UInt(32.W)) // final result
|
||||
|
|
@ -29,7 +29,7 @@ class el2_exu_alu_ctl extends Module with el2_lib with RequireAsyncReset{
|
|||
val flush_path_out = Output(UInt(31.W)) // Branch flush PC
|
||||
val pc_ff = Output(UInt(31.W)) // flopped PC
|
||||
val pred_correct_out = Output(UInt(1.W)) // NPC control
|
||||
val predict_p_out = Output(new el2_predict_pkt_t) // Predicted branch structure
|
||||
val predict_p_out = Valid(new el2_predict_pkt_t) // Predicted branch structure
|
||||
})
|
||||
|
||||
io.pc_ff := rvdffe(io.pc_in,io.enable,clock,io.scan_mode.asBool) // any PC is run through here - doesn't have to be alu
|
||||
|
|
@ -42,13 +42,13 @@ class el2_exu_alu_ctl extends Module with el2_lib with RequireAsyncReset{
|
|||
aout := Mux(io.ap.sub.asBool,(Cat(0.U(1.W),io.a_in) + Cat(0.U(1.W),~io.b_in) + Cat(0.U(32.W),io.ap.sub)), (Cat(0.U(1.W),io.a_in) + Cat(0.U(1.W), io.b_in) + Cat(0.U(32.W),io.ap.sub)))
|
||||
val cout = aout(32)
|
||||
|
||||
val ov = (~io.a_in(31) & ~bm(31) & aout(31)) | ( io.a_in(31) & bm(31) & ~aout(31) ) //overflow check from last bits
|
||||
val ov = (!io.a_in(31) & !bm(31) & aout(31)) | ( io.a_in(31) & bm(31) & !aout(31) ) //overflow check from last bits
|
||||
|
||||
val eq = (io.a_in === io.b_in.asSInt)
|
||||
val ne = ~eq
|
||||
val neg = aout(31)// check for the last signed bit (for neg)
|
||||
val lt = (~io.ap.unsign & (neg ^ ov)) | ( io.ap.unsign & ~cout) //if alu packet sends unsigned and there is no cout(i.e no overflow and unsigned pkt)
|
||||
val ge = ~lt // if not less then
|
||||
val lt = (!io.ap.unsign & (neg ^ ov)) | ( io.ap.unsign & !cout) //if alu packet sends unsigned and there is no cout(i.e no overflow and unsigned pkt)
|
||||
val ge = !lt // if not less then
|
||||
|
||||
|
||||
val lout = Mux1H(Seq(
|
||||
|
|
@ -75,8 +75,8 @@ class el2_exu_alu_ctl extends Module with el2_lib with RequireAsyncReset{
|
|||
|
||||
|
||||
val sel_shift = io.ap.sll | io.ap.srl | io.ap.sra
|
||||
val sel_adder = (io.ap.add | io.ap.sub) & ~io.ap.slt
|
||||
val sel_pc = io.ap.jal | io.pp_in.pcall | io.pp_in.pja | io.pp_in.pret
|
||||
val sel_adder = (io.ap.add | io.ap.sub) & !io.ap.slt
|
||||
val sel_pc = io.ap.jal | io.pp_in.bits.pcall | io.pp_in.bits.pja | io.pp_in.bits.pret
|
||||
val csr_write_data = Mux(io.ap.csr_imm.asBool, io.b_in.asSInt, io.a_in)
|
||||
|
||||
val slt_one = io.ap.slt & lt
|
||||
|
|
@ -94,9 +94,9 @@ class el2_exu_alu_ctl extends Module with el2_lib with RequireAsyncReset{
|
|||
// *** branch handling ***
|
||||
|
||||
val any_jal = io.ap.jal | //jal
|
||||
io.pp_in.pcall | //branch is a call inst
|
||||
io.pp_in.pja | //branch is a jump always
|
||||
io.pp_in.pret //return inst
|
||||
io.pp_in.bits.pcall | //branch is a call inst
|
||||
io.pp_in.bits.pja | //branch is a jump always
|
||||
io.pp_in.bits.pret //return inst
|
||||
|
||||
val actual_taken = (io.ap.beq & eq) | (io.ap.bne & ne.asUInt) | (io.ap.blt & lt) | (io.ap.bge & ge) | any_jal
|
||||
|
||||
|
|
@ -111,7 +111,7 @@ class el2_exu_alu_ctl extends Module with el2_lib with RequireAsyncReset{
|
|||
val cond_mispredict = (io.ap.predict_t & !actual_taken) | (io.ap.predict_nt & actual_taken.asUInt)
|
||||
|
||||
// target mispredicts on ret's
|
||||
val target_mispredict = io.pp_in.pret & (io.pp_in.prett =/= aout(31,1)) //predicted return target != aout
|
||||
val target_mispredict = io.pp_in.bits.pret & (io.pp_in.bits.prett =/= aout(31,1)) //predicted return target != aout
|
||||
|
||||
io.flush_upper_out := (io.ap.jal | cond_mispredict | target_mispredict) & io.valid_in & !io.flush_upper_x & !io.flush_lower_r
|
||||
//there was no entire pipe flush (& previous cycle flush ofc(why check?)) therfore signAL 1 to flush instruction before X stage
|
||||
|
|
@ -119,13 +119,13 @@ class el2_exu_alu_ctl extends Module with el2_lib with RequireAsyncReset{
|
|||
//there was entire pipe flush or (there is mispred or a jal) therfore signAL 1 to flush entire pipe
|
||||
|
||||
val newhist = WireInit(UInt(2.W),0.U)
|
||||
newhist := Cat((io.pp_in.hist(1) & io.pp_in.hist(0)) | (~io.pp_in.hist(0) & actual_taken),//newhist[1]
|
||||
(~io.pp_in.hist(1) & ~actual_taken) | (io.pp_in.hist(1) & actual_taken)) //newhist[0]
|
||||
newhist := Cat((io.pp_in.bits.hist(1) & io.pp_in.bits.hist(0)) | (!io.pp_in.bits.hist(0) & actual_taken),//newhist[1]
|
||||
(!io.pp_in.bits.hist(1) & !actual_taken) | (io.pp_in.bits.hist(1) & actual_taken)) //newhist[0]
|
||||
|
||||
io.predict_p_out := io.pp_in
|
||||
io.predict_p_out.misp := ~io.flush_upper_x & ~io.flush_lower_r & (cond_mispredict | target_mispredict);// if 1 tells that it was a misprediction becauseprevious cycle was not a flush and these was no master flush(lower pipe flush) and ifu predicted taken but actually its nt
|
||||
io.predict_p_out.ataken := actual_taken; // send a control signal telling it branch taken or not
|
||||
io.predict_p_out.hist := newhist
|
||||
io.predict_p_out.bits.misp := !io.flush_upper_x & !io.flush_lower_r & (cond_mispredict | target_mispredict)// if 1 tells that it was a misprediction becauseprevious cycle was not a flush and these was no master flush(lower pipe flush) and ifu predicted taken but actually its nt
|
||||
io.predict_p_out.bits.ataken := actual_taken; // send a control signal telling it branch taken or not
|
||||
io.predict_p_out.bits.hist := newhist
|
||||
}
|
||||
|
||||
object alu extends App{
|
||||
|
|
|
|||
|
|
@ -10,7 +10,7 @@ import lib._
|
|||
class el2_exu_div_ctl extends Module with RequireAsyncReset with el2_lib {
|
||||
val io = IO(new Bundle{
|
||||
val scan_mode = Input(Bool())
|
||||
val dp = Input(new el2_div_pkt_t )
|
||||
val dp = Flipped(Valid(new el2_div_pkt_t ))
|
||||
val dividend = Input(UInt(32.W))
|
||||
val divisor = Input(UInt(32.W))
|
||||
val cancel = Input(UInt(1.W))
|
||||
|
|
@ -163,7 +163,7 @@ class el2_exu_div_ctl extends Module with RequireAsyncReset with el2_lib {
|
|||
//io.test := count_in
|
||||
|
||||
io.finish_dly := finish_ff & !io.cancel
|
||||
val sign_eff = !io.dp.unsign & (io.divisor =/= 0.U(32.W))
|
||||
val sign_eff = !io.dp.bits.unsign & (io.divisor =/= 0.U(32.W))
|
||||
|
||||
|
||||
q_in := Mux1H(Seq(
|
||||
|
|
@ -208,7 +208,7 @@ class el2_exu_div_ctl extends Module with RequireAsyncReset with el2_lib {
|
|||
dividend_neg_ff := RegEnable(io.dividend(31), 0.U, io.dp.valid.asBool)
|
||||
divisor_neg_ff := RegEnable(io.divisor(31), 0.U, io.dp.valid.asBool)
|
||||
sign_ff := RegEnable(sign_eff, 0.U, io.dp.valid.asBool)
|
||||
rem_ff := RegEnable(io.dp.rem, 0.U, io.dp.valid.asBool)
|
||||
rem_ff := RegEnable(io.dp.bits.rem, 0.U, io.dp.valid.asBool)
|
||||
smallnum_case_ff := RegNext(smallnum_case, 0.U)
|
||||
smallnum_ff := RegNext(smallnum, 0.U)
|
||||
shortq_enable_ff := RegNext(shortq_enable, 0.U)
|
||||
|
|
@ -216,7 +216,7 @@ class el2_exu_div_ctl extends Module with RequireAsyncReset with el2_lib {
|
|||
}
|
||||
q_ff := rvdffe(q_in, qff_enable.asBool,clock,io.scan_mode)
|
||||
a_ff := rvdffe(a_in, aff_enable.asBool,clock,io.scan_mode)
|
||||
m_ff := rvdffe(Cat(!io.dp.unsign & io.divisor(31), io.divisor), io.dp.valid.asBool,clock,io.scan_mode)
|
||||
m_ff := rvdffe(Cat(!io.dp.bits.unsign & io.divisor(31), io.divisor), io.dp.valid.asBool,clock,io.scan_mode)
|
||||
|
||||
}
|
||||
object div_main extends App{
|
||||
|
|
|
|||
|
|
@ -9,7 +9,7 @@ import lib._
|
|||
class el2_exu_mul_ctl extends Module with RequireAsyncReset with el2_lib {
|
||||
val io = IO(new Bundle{
|
||||
val scan_mode = Input(Bool())
|
||||
val mul_p = Input(new el2_mul_pkt_t )
|
||||
val mul_p = Flipped(Valid(new el2_mul_pkt_t ))
|
||||
val rs1_in = Input(UInt(32.W))
|
||||
val rs2_in = Input(UInt(32.W))
|
||||
val result_x = Output(UInt(32.W))
|
||||
|
|
@ -23,17 +23,10 @@ class el2_exu_mul_ctl extends Module with RequireAsyncReset with el2_lib {
|
|||
val low_x = WireInit(0.U(1.W))
|
||||
|
||||
val mul_x_enable = io.mul_p.valid
|
||||
rs1_ext_in := Cat(io.mul_p.rs1_sign & io.rs1_in(31),io.rs1_in).asSInt
|
||||
rs2_ext_in := Cat(io.mul_p.rs2_sign & io.rs2_in(31),io.rs2_in).asSInt
|
||||
rs1_ext_in := Cat(io.mul_p.bits.rs1_sign & io.rs1_in(31),io.rs1_in).asSInt
|
||||
rs2_ext_in := Cat(io.mul_p.bits.rs2_sign & io.rs2_in(31),io.rs2_in).asSInt
|
||||
|
||||
// --------------------------- Multiply ----------------------------------
|
||||
// val gated_clock = rvclkhdr(clock,mul_x_enable.asBool(),io.scan_mode)
|
||||
// withClock(gated_clock) {
|
||||
// low_x := RegNext(io.mul_p.low, 0.U)
|
||||
//rs1_x := RegNext(rs1_ext_in, 0.S)
|
||||
// rs2_x := RegNext(rs2_ext_in, 0.S)
|
||||
// }
|
||||
low_x := rvdffe (io.mul_p.low, mul_x_enable.asBool,clock,io.scan_mode)
|
||||
low_x := rvdffe (io.mul_p.bits.low, mul_x_enable.asBool,clock,io.scan_mode)
|
||||
rs1_x := rvdffe(rs1_ext_in, mul_x_enable.asBool,clock,io.scan_mode)
|
||||
rs2_x := rvdffe (rs2_ext_in, mul_x_enable.asBool,clock,io.scan_mode)
|
||||
|
||||
|
|
|
|||
|
|
@ -122,17 +122,17 @@ class el2_ifu extends Module with el2_lib with RequireAsyncReset {
|
|||
val ifu_i0_pc4 = Output(Bool())
|
||||
val ifu_miss_state_idle = Output(Bool())
|
||||
// Aligner branch data
|
||||
val i0_brp = Output(new el2_br_pkt_t)
|
||||
val i0_brp = Valid(new el2_br_pkt_t)
|
||||
val ifu_i0_bp_index = Output(UInt((BTB_ADDR_HI-BTB_ADDR_LO+1).W))
|
||||
val ifu_i0_bp_fghr = Output(UInt(BHT_GHR_SIZE.W))
|
||||
val ifu_i0_bp_btag = Output(UInt(BTB_BTAG_SIZE.W))
|
||||
// BP Inputs
|
||||
val exu_mp_pkt = Input(new el2_predict_pkt_t)
|
||||
val exu_mp_pkt = Flipped(Valid(new el2_predict_pkt_t))
|
||||
val exu_mp_eghr = Input(UInt(BHT_GHR_SIZE.W))
|
||||
val exu_mp_fghr = Input(UInt(BHT_GHR_SIZE.W))
|
||||
val exu_mp_index = Input(UInt((BTB_ADDR_HI-BTB_ADDR_LO+1).W)) // Misprediction index
|
||||
val exu_mp_btag = Input(UInt(BTB_BTAG_SIZE.W))
|
||||
val dec_tlu_br0_r_pkt = Input(new el2_br_tlu_pkt_t)
|
||||
val dec_tlu_br0_r_pkt = Flipped(Valid(new el2_br_tlu_pkt_t))
|
||||
val exu_i0_br_fghr_r = Input(UInt(BHT_GHR_SIZE.W)) // Updated GHR from the exu
|
||||
val exu_i0_br_index_r = Input(UInt((BTB_ADDR_HI-BTB_ADDR_LO+1).W))
|
||||
val dec_tlu_flush_lower_wb = Input(Bool())
|
||||
|
|
|
|||
|
|
@ -42,7 +42,7 @@ class el2_ifu_aln_ctl extends Module with el2_lib with RequireAsyncReset {
|
|||
val ifu_i0_bp_btag = Output(UInt(BTB_BTAG_SIZE.W))
|
||||
val ifu_pmu_instr_aligned = Output(Bool())
|
||||
val ifu_i0_cinst = Output(UInt(16.W))
|
||||
val i0_brp = Output(new el2_br_pkt_t)
|
||||
val i0_brp = Valid(new el2_br_pkt_t)
|
||||
})
|
||||
io.ifu_i0_valid := 0.U
|
||||
io.ifu_i0_icaf := 0.U
|
||||
|
|
@ -377,25 +377,25 @@ class el2_ifu_aln_ctl extends Module with el2_lib with RequireAsyncReset {
|
|||
|
||||
io.i0_brp.valid :=(first2B & alignbrend(0)) | (first4B & alignbrend(1)) | (first4B & alignval(1) & alignbrend(0))
|
||||
|
||||
io.i0_brp.ret := (first2B & alignret(0)) | (first4B & alignret(1))
|
||||
io.i0_brp.bits.ret := (first2B & alignret(0)) | (first4B & alignret(1))
|
||||
|
||||
val i0_brp_pc4 = (first2B & alignpc4(0)) | (first4B & alignpc4(1))
|
||||
|
||||
io.i0_brp.way := Mux((first2B | alignbrend(0)).asBool, alignway(0), alignway(1))
|
||||
io.i0_brp.bits.way := Mux((first2B | alignbrend(0)).asBool, alignway(0), alignway(1))
|
||||
|
||||
io.i0_brp.hist := Cat((first2B & alignhist1(0)) | (first4B & alignhist1(1)),
|
||||
io.i0_brp.bits.hist := Cat((first2B & alignhist1(0)) | (first4B & alignhist1(1)),
|
||||
(first2B & alignhist0(0)) | (first4B & alignhist0(1)))
|
||||
|
||||
val i0_ends_f1 = first4B & alignfromf1
|
||||
io.i0_brp.toffset := Mux(i0_ends_f1.asBool, f1poffset, f0poffset)
|
||||
io.i0_brp.bits.toffset := Mux(i0_ends_f1.asBool, f1poffset, f0poffset)
|
||||
|
||||
io.i0_brp.prett := Mux(i0_ends_f1.asBool, f1prett, f0prett)
|
||||
io.i0_brp.bits.prett := Mux(i0_ends_f1.asBool, f1prett, f0prett)
|
||||
|
||||
io.i0_brp.br_start_error := (first4B & alignval(1) & alignbrend(0))
|
||||
io.i0_brp.bits.br_start_error := (first4B & alignval(1) & alignbrend(0))
|
||||
|
||||
io.i0_brp.bank := Mux((first2B | alignbrend(0)).asBool, firstpc(0), secondpc(0))
|
||||
io.i0_brp.bits.bank := Mux((first2B | alignbrend(0)).asBool, firstpc(0), secondpc(0))
|
||||
|
||||
io.i0_brp.br_error := (io.i0_brp.valid & i0_brp_pc4 & first2B) | (io.i0_brp.valid & !i0_brp_pc4 & first4B)
|
||||
io.i0_brp.bits.br_error := (io.i0_brp.valid & i0_brp_pc4 & first2B) | (io.i0_brp.valid & !i0_brp_pc4 & first4B)
|
||||
|
||||
io.ifu_i0_bp_index := Mux((first2B | alignbrend(0)).asBool, firstpc_hash, secondpc_hash)
|
||||
|
||||
|
|
|
|||
|
|
@ -13,14 +13,14 @@ class el2_ifu_bp_ctl extends Module with el2_lib with RequireAsyncReset {
|
|||
val ifc_fetch_addr_f = Input(UInt(31.W))
|
||||
val ifc_fetch_req_f = Input(Bool()) // Fetch request generated by the IFC
|
||||
// Decode packet containing information if its a brnach or not
|
||||
val dec_tlu_br0_r_pkt = Input(new el2_br_tlu_pkt_t)
|
||||
val dec_tlu_br0_r_pkt = Flipped(Valid(new el2_br_tlu_pkt_t))
|
||||
val exu_i0_br_fghr_r = Input(UInt(BHT_GHR_SIZE.W)) // Updated GHR from the exu
|
||||
val exu_i0_br_index_r = Input(UInt((BTB_ADDR_HI-BTB_ADDR_LO+1).W)) // Way from where the btb got a hit
|
||||
val dec_tlu_flush_lower_wb = Input(Bool())
|
||||
val dec_tlu_flush_leak_one_wb = Input(Bool())
|
||||
val dec_tlu_bpred_disable = Input(Bool())
|
||||
// Exu misprediction packet
|
||||
val exu_mp_pkt = Input(new el2_predict_pkt_t)
|
||||
val exu_mp_pkt = Flipped(Valid(new el2_predict_pkt_t))
|
||||
val exu_mp_eghr = Input(UInt(BHT_GHR_SIZE.W))
|
||||
val exu_mp_fghr = Input(UInt(BHT_GHR_SIZE.W))
|
||||
val exu_mp_index = Input(UInt((BTB_ADDR_HI-BTB_ADDR_LO+1).W)) // Misprediction index
|
||||
|
|
@ -69,26 +69,26 @@ class el2_ifu_bp_ctl extends Module with el2_lib with RequireAsyncReset {
|
|||
val dec_tlu_way_wb = WireInit(Bool(), 0.U)
|
||||
/////////////////////////////////////////////////////////
|
||||
// Misprediction packet
|
||||
val exu_mp_valid = io.exu_mp_pkt.misp & !leak_one_f
|
||||
val exu_mp_boffset = io.exu_mp_pkt.boffset
|
||||
val exu_mp_pc4 = io.exu_mp_pkt.pc4
|
||||
val exu_mp_call = io.exu_mp_pkt.pcall
|
||||
val exu_mp_ret = io.exu_mp_pkt.pret
|
||||
val exu_mp_ja = io.exu_mp_pkt.pja
|
||||
val exu_mp_way = io.exu_mp_pkt.way
|
||||
val exu_mp_hist = io.exu_mp_pkt.hist
|
||||
val exu_mp_tgt = io.exu_mp_pkt.toffset
|
||||
val exu_mp_valid = io.exu_mp_pkt.bits.misp & !leak_one_f
|
||||
val exu_mp_boffset = io.exu_mp_pkt.bits.boffset
|
||||
val exu_mp_pc4 = io.exu_mp_pkt.bits.pc4
|
||||
val exu_mp_call = io.exu_mp_pkt.bits.pcall
|
||||
val exu_mp_ret = io.exu_mp_pkt.bits.pret
|
||||
val exu_mp_ja = io.exu_mp_pkt.bits.pja
|
||||
val exu_mp_way = io.exu_mp_pkt.bits.way
|
||||
val exu_mp_hist = io.exu_mp_pkt.bits.hist
|
||||
val exu_mp_tgt = io.exu_mp_pkt.bits.toffset
|
||||
val exu_mp_addr = io.exu_mp_index
|
||||
val exu_mp_ataken = io.exu_mp_pkt.ataken
|
||||
val exu_mp_ataken = io.exu_mp_pkt.bits.ataken
|
||||
|
||||
// Its a commit or update packet
|
||||
val dec_tlu_br0_v_wb = io.dec_tlu_br0_r_pkt.valid
|
||||
val dec_tlu_br0_hist_wb = io.dec_tlu_br0_r_pkt.hist
|
||||
val dec_tlu_br0_hist_wb = io.dec_tlu_br0_r_pkt.bits.hist
|
||||
val dec_tlu_br0_addr_wb = io.exu_i0_br_index_r
|
||||
val dec_tlu_br0_error_wb = io.dec_tlu_br0_r_pkt.br_error
|
||||
val dec_tlu_br0_middle_wb = io.dec_tlu_br0_r_pkt.middle
|
||||
val dec_tlu_br0_way_wb = io.dec_tlu_br0_r_pkt.way
|
||||
val dec_tlu_br0_start_error_wb = io.dec_tlu_br0_r_pkt.br_start_error
|
||||
val dec_tlu_br0_error_wb = io.dec_tlu_br0_r_pkt.bits.br_error
|
||||
val dec_tlu_br0_middle_wb = io.dec_tlu_br0_r_pkt.bits.middle
|
||||
val dec_tlu_br0_way_wb = io.dec_tlu_br0_r_pkt.bits.way
|
||||
val dec_tlu_br0_start_error_wb = io.dec_tlu_br0_r_pkt.bits.br_start_error
|
||||
val exu_i0_br_fghr_wb = io.exu_i0_br_fghr_r
|
||||
|
||||
dec_tlu_error_wb := dec_tlu_br0_start_error_wb | dec_tlu_br0_error_wb
|
||||
|
|
|
|||
|
|
@ -839,14 +839,14 @@ class el2_ifu_mem_ctl extends Module with el2_lib {
|
|||
ic_debug_rd_en_ff := withClock(io.free_clk){RegNext(io.ic_debug_rd_en, false.B)}
|
||||
io.ifu_ic_debug_rd_data_valid := withClock(io.free_clk){RegEnable(ic_debug_rd_en_ff, 0.U, ic_debug_rd_en_ff.asBool)}
|
||||
val ifc_region_acc_okay = Cat(INST_ACCESS_ENABLE0.U,INST_ACCESS_ENABLE1.U,INST_ACCESS_ENABLE2.U,INST_ACCESS_ENABLE3.U,INST_ACCESS_ENABLE4.U,INST_ACCESS_ENABLE5.U,INST_ACCESS_ENABLE6.U,INST_ACCESS_ENABLE7.U).orR() |
|
||||
INST_ACCESS_ENABLE0.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK0).U) === (INST_ACCESS_ADDR0.U | aslong(INST_ACCESS_MASK0).U)) |
|
||||
INST_ACCESS_ENABLE1.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK1).U) === (INST_ACCESS_ADDR1.U | aslong(INST_ACCESS_MASK1).U)) |
|
||||
INST_ACCESS_ENABLE2.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK2).U) === (INST_ACCESS_ADDR2.U | aslong(INST_ACCESS_MASK2).U)) |
|
||||
INST_ACCESS_ENABLE3.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK3).U) === (INST_ACCESS_ADDR3.U | aslong(INST_ACCESS_MASK3).U)) |
|
||||
INST_ACCESS_ENABLE4.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK4).U) === (INST_ACCESS_ADDR4.U | aslong(INST_ACCESS_MASK4).U)) |
|
||||
INST_ACCESS_ENABLE5.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK5).U) === (INST_ACCESS_ADDR5.U | aslong(INST_ACCESS_MASK5).U)) |
|
||||
INST_ACCESS_ENABLE6.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK6).U) === (INST_ACCESS_ADDR6.U | aslong(INST_ACCESS_MASK6).U)) |
|
||||
INST_ACCESS_ENABLE7.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK7).U) === (INST_ACCESS_ADDR7.U | aslong(INST_ACCESS_MASK7).U))
|
||||
INST_ACCESS_ENABLE0.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK0).U) === (aslong(INST_ACCESS_ADDR0).U | aslong(INST_ACCESS_MASK0).U)) |
|
||||
INST_ACCESS_ENABLE1.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK1).U) === (aslong(INST_ACCESS_ADDR1).U | aslong(INST_ACCESS_MASK1).U)) |
|
||||
INST_ACCESS_ENABLE2.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK2).U) === (aslong(INST_ACCESS_ADDR2).U | aslong(INST_ACCESS_MASK2).U)) |
|
||||
INST_ACCESS_ENABLE3.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK3).U) === (aslong(INST_ACCESS_ADDR3).U | aslong(INST_ACCESS_MASK3).U)) |
|
||||
INST_ACCESS_ENABLE4.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK4).U) === (aslong(INST_ACCESS_ADDR4).U | aslong(INST_ACCESS_MASK4).U)) |
|
||||
INST_ACCESS_ENABLE5.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK5).U) === (aslong(INST_ACCESS_ADDR5).U | aslong(INST_ACCESS_MASK5).U)) |
|
||||
INST_ACCESS_ENABLE6.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK6).U) === (aslong(INST_ACCESS_ADDR6).U | aslong(INST_ACCESS_MASK6).U)) |
|
||||
INST_ACCESS_ENABLE7.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK7).U) === (aslong(INST_ACCESS_ADDR7).U | aslong(INST_ACCESS_MASK7).U))
|
||||
val ifc_region_acc_fault_memory_bf = !io.ifc_iccm_access_bf & !ifc_region_acc_okay & io.ifc_fetch_req_bf
|
||||
ifc_region_acc_fault_final_bf := io.ifc_region_acc_fault_bf | ifc_region_acc_fault_memory_bf
|
||||
ifc_region_acc_fault_memory_f := withClock(io.free_clk){RegNext(ifc_region_acc_fault_memory_bf, false.B)}
|
||||
|
|
|
|||
|
|
@ -34,29 +34,8 @@ object el2_inst_pkt_t extends Enumeration{
|
|||
val JAL = "b1110".U(4.W)
|
||||
val BITMANIPU = "b1111".U(4.W)
|
||||
}
|
||||
/*
|
||||
class el2_inst_pkt_t extends Bundle{
|
||||
val NULL = "b0000".U(4.W)
|
||||
val MUL = "b0001".U(4.W)
|
||||
val LOAD = "b0010".U(4.W)
|
||||
val STORE = "b0011".U(4.W)
|
||||
val ALU = "b0100".U(4.W)
|
||||
val CSRREAD = "b0101".U(4.W)
|
||||
val CSRWRITE = "b0110".U(4.W)
|
||||
val CSRRW = "b0111".U(4.W)
|
||||
val EBREAK = "b1000".U(4.W)
|
||||
val ECALL = "b1001".U(4.W)
|
||||
val FENCE = "b1010".U(4.W)
|
||||
val FENCEI = "b1011".U(4.W)
|
||||
val MRET = "b1100".U(4.W)
|
||||
val CONDBR = "b1101".U(4.W)
|
||||
val JAL = "b1110".U(4.W)
|
||||
val BITMANIPU = "b1111".U(4.W)
|
||||
}
|
||||
|
||||
*/
|
||||
class el2_load_cam_pkt_t extends Bundle {
|
||||
val valid = UInt(1.W)
|
||||
val wb = UInt(1.W)
|
||||
val tag = UInt(3.W)
|
||||
val rd = UInt(5.W)
|
||||
|
|
@ -69,7 +48,6 @@ class el2_rets_pkt_t extends Bundle {
|
|||
}
|
||||
|
||||
class el2_br_pkt_t extends Bundle {
|
||||
val valid = UInt(1.W)
|
||||
val toffset = UInt(12.W)
|
||||
val hist = UInt(2.W)
|
||||
val br_error = UInt(1.W)
|
||||
|
|
@ -82,7 +60,6 @@ class el2_br_pkt_t extends Bundle {
|
|||
|
||||
|
||||
class el2_br_tlu_pkt_t extends Bundle {
|
||||
val valid = UInt(1.W)
|
||||
val hist = UInt(2.W)
|
||||
val br_error = UInt(1.W)
|
||||
val br_start_error = UInt(1.W)
|
||||
|
|
@ -97,7 +74,6 @@ class el2_predict_pkt_t extends Bundle {
|
|||
val pc4 = UInt(1.W)
|
||||
val hist = UInt(2.W)
|
||||
val toffset = UInt(12.W)
|
||||
val valid = UInt(1.W)
|
||||
val br_error = UInt(1.W)
|
||||
val br_start_error = UInt(1.W)
|
||||
val prett = UInt(31.W)
|
||||
|
|
@ -127,7 +103,6 @@ class el2_dest_pkt_t extends Bundle {
|
|||
val i0store = UInt(1.W)
|
||||
val i0div = UInt(1.W)
|
||||
val i0v = UInt(1.W)
|
||||
val i0valid = UInt(1.W)
|
||||
val csrwen = UInt(1.W)
|
||||
val csrwonly = UInt(1.W)
|
||||
val csrwaddr = UInt(12.W)
|
||||
|
|
@ -181,11 +156,9 @@ class el2_lsu_pkt_t extends Bundle {
|
|||
val store_data_bypass_d = Bool()
|
||||
val load_ldst_bypass_d = Bool()
|
||||
val store_data_bypass_m = Bool()
|
||||
val valid = Bool()
|
||||
}
|
||||
|
||||
class el2_lsu_error_pkt_t extends Bundle {
|
||||
val exc_valid = UInt(1.W)
|
||||
val single_ecc_error = UInt(1.W)
|
||||
val inst_type = UInt(1.W) //0: Load, 1: Store
|
||||
val exc_type = UInt(1.W) //0: MisAligned, 1: Access Fault
|
||||
|
|
@ -247,7 +220,6 @@ class el2_dec_pkt_t extends Bundle {
|
|||
}
|
||||
|
||||
class el2_mul_pkt_t extends Bundle {
|
||||
val valid = UInt(1.W)
|
||||
val rs1_sign = UInt(1.W)
|
||||
val rs2_sign = UInt(1.W)
|
||||
val low = UInt(1.W)
|
||||
|
|
@ -269,7 +241,6 @@ class el2_mul_pkt_t extends Bundle {
|
|||
}
|
||||
|
||||
class el2_div_pkt_t extends Bundle {
|
||||
val valid = UInt(1.W)
|
||||
val unsign = UInt(1.W)
|
||||
val rem = UInt(1.W)
|
||||
}
|
||||
|
|
@ -278,7 +249,6 @@ class el2_ccm_ext_in_pkt_t extends Bundle {
|
|||
val TEST1 = UInt(1.W)
|
||||
val RME = UInt(1.W)
|
||||
val RM = UInt(4.W)
|
||||
|
||||
val LS = UInt(1.W)
|
||||
val DS = UInt(1.W)
|
||||
val SD = UInt(1.W)
|
||||
|
|
|
|||
|
|
@ -6,16 +6,16 @@ import chisel3.util._
|
|||
|
||||
class rvdff(WIDTH:Int=1,SHORT:Int=0) extends Module{
|
||||
val io = IO(new Bundle{
|
||||
val din = Input(UInt(WIDTH.W))
|
||||
val dout = Output(UInt(WIDTH.W))
|
||||
})
|
||||
val din = Input(UInt(WIDTH.W))
|
||||
val dout = Output(UInt(WIDTH.W))
|
||||
})
|
||||
|
||||
val flop = RegNext(io.din,0.U)
|
||||
val flop = RegNext(io.din,0.U)
|
||||
|
||||
if(SHORT == 1)
|
||||
{io.dout := io.din}
|
||||
else
|
||||
{io.dout := flop}
|
||||
if(SHORT == 1)
|
||||
{io.dout := io.din}
|
||||
else
|
||||
{io.dout := flop}
|
||||
}
|
||||
|
||||
class rvdffsc extends Module with el2_lib {
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
package lib
|
||||
import chisel3._
|
||||
import chisel3.util._
|
||||
import el2_mem.waleed.{DCCM_ENABLE, ICACHE_ECC, ICACHE_WAYPACK, ICCM_ENABLE, bool2int}
|
||||
trait param {
|
||||
val BHT_ADDR_HI = 9
|
||||
val BHT_ADDR_LO = 2
|
||||
|
|
@ -176,7 +177,6 @@ trait el2_lib extends param{
|
|||
def apply(din:UInt,clk:Clock) =withClock(clk){RegNext(withClock(clk){RegNext(din,0.U)},0.U)}
|
||||
}
|
||||
|
||||
|
||||
///////////////////////////////////////////////////////////////////
|
||||
def el2_btb_tag_hash(pc : UInt) =
|
||||
VecInit.tabulate(3)(i => pc(BTB_ADDR_HI-1+((i+1)*(BTB_BTAG_SIZE)),BTB_ADDR_HI+(i*BTB_BTAG_SIZE))).reduce(_^_)
|
||||
|
|
@ -203,7 +203,7 @@ trait el2_lib extends param{
|
|||
def rveven_paritygen(data_in : UInt) =
|
||||
data_in.xorR.asUInt
|
||||
///////////////////////////////////////////////////////////////////
|
||||
//rvbradder(Cat(pc, 0.U), Cat(offset, 0.U))
|
||||
//rvbradder(Cat(pc, 0.U), Cat(offset, 0.U))
|
||||
def rvbradder (pc:UInt, offset:UInt) = {
|
||||
val dout_lower = pc(12,1) +& offset(12,1)
|
||||
val pc_inc = pc(31,13)+1.U
|
||||
|
|
@ -216,10 +216,10 @@ trait el2_lib extends param{
|
|||
|
||||
///////////////////////////////////////////////////////////////////
|
||||
// RV range
|
||||
def rvrangecheck(CCM_SADR:Long, CCM_SIZE:Int, addr:UInt) = {
|
||||
def rvrangecheck(CCM_SADR:Int, CCM_SIZE:Int, addr:UInt) = {
|
||||
val REGION_BITS = 4;
|
||||
val MASK_BITS = 10 + log2Ceil(CCM_SIZE)
|
||||
val start_addr = CCM_SADR.U(32.W)
|
||||
val start_addr = aslong(CCM_SADR).U(32.W)
|
||||
val region = start_addr(31,32-REGION_BITS)
|
||||
val in_region = addr(31,(32-REGION_BITS)) === region
|
||||
val in_range = if(CCM_SIZE==48)
|
||||
|
|
@ -545,4 +545,6 @@ trait el2_lib extends param{
|
|||
Cat(temp.asUInt,din(0))
|
||||
}
|
||||
|
||||
//implicit def bool2int(b:Boolean): Int = if (b) 1 else 0
|
||||
|
||||
}
|
||||
|
|
|
|||
|
|
@ -20,7 +20,7 @@ class el2_lsu extends Module with RequireAsyncReset with param with el2_lib {
|
|||
val exu_lsu_rs1_d = Input(UInt(32.W))
|
||||
val exu_lsu_rs2_d = Input(UInt(32.W))
|
||||
val dec_lsu_offset_d = Input(UInt(12.W))
|
||||
val lsu_p = Input(new el2_lsu_pkt_t)
|
||||
val lsu_p = Flipped(Valid(new el2_lsu_pkt_t))
|
||||
val trigger_pkt_any = Input(Vec(4, new el2_trigger_pkt_t))
|
||||
|
||||
val dec_lsu_valid_raw_d = Input(Bool())
|
||||
|
|
@ -36,7 +36,7 @@ class el2_lsu extends Module with RequireAsyncReset with param with el2_lib {
|
|||
val lsu_fir_addr = Output(UInt(31.W))
|
||||
val lsu_fir_error = Output(UInt(2.W))
|
||||
val lsu_single_ecc_error_incr = Output(Bool())
|
||||
val lsu_error_pkt_r = Output(new el2_lsu_error_pkt_t)
|
||||
val lsu_error_pkt_r = Valid(new el2_lsu_error_pkt_t)
|
||||
val lsu_imprecise_error_load_any = Output(Bool())
|
||||
val lsu_imprecise_error_store_any = Output(Bool())
|
||||
val lsu_imprecise_error_addr_any = Output(UInt(32.W))
|
||||
|
|
@ -172,7 +172,7 @@ class el2_lsu extends Module with RequireAsyncReset with param with el2_lib {
|
|||
// Ready to accept dma trxns
|
||||
// There can't be any inpipe forwarding from non-dma packet to dma packet since they can be flushed so we can't have st in r when dma is in m
|
||||
val dma_mem_tag_d = io.dma_mem_tag
|
||||
val ldst_nodma_mtor = lsu_lsc_ctl.io.lsu_pkt_m.valid & !lsu_lsc_ctl.io.lsu_pkt_m.dma & (lsu_lsc_ctl.io.addr_in_dccm_m | lsu_lsc_ctl.io.addr_in_pic_m) & lsu_lsc_ctl.io.lsu_pkt_m.store
|
||||
val ldst_nodma_mtor = lsu_lsc_ctl.io.lsu_pkt_m.valid & !lsu_lsc_ctl.io.lsu_pkt_m.bits.dma & (lsu_lsc_ctl.io.addr_in_dccm_m | lsu_lsc_ctl.io.addr_in_pic_m) & lsu_lsc_ctl.io.lsu_pkt_m.bits.store
|
||||
io.dccm_ready := !(io.dec_lsu_valid_raw_d | ldst_nodma_mtor | dccm_ctl.io.ld_single_ecc_error_r_ff)
|
||||
val dma_dccm_wen = io.dma_dccm_req & io.dma_mem_write & lsu_lsc_ctl.io.addr_in_dccm_d
|
||||
val dma_pic_wen = io.dma_dccm_req & io.dma_mem_write & lsu_lsc_ctl.io.addr_in_pic_d
|
||||
|
|
@ -187,17 +187,17 @@ class el2_lsu extends Module with RequireAsyncReset with param with el2_lib {
|
|||
// Indicates non-idle if there is a instruction valid in d-r or read/write buffers are non-empty since they can come with error
|
||||
// Store buffer now have only non-dma dccm stores
|
||||
// stbuf_empty not needed since it has only dccm stores
|
||||
io.lsu_idle_any := !((lsu_lsc_ctl.io.lsu_pkt_m.valid & !lsu_lsc_ctl.io.lsu_pkt_m.dma) | (lsu_lsc_ctl.io.lsu_pkt_r.valid & !lsu_lsc_ctl.io.lsu_pkt_r.dma)) & bus_intf.io.lsu_bus_buffer_empty_any & bus_intf.io.lsu_bus_idle_any
|
||||
io.lsu_idle_any := !((lsu_lsc_ctl.io.lsu_pkt_m.valid & !lsu_lsc_ctl.io.lsu_pkt_m.bits.dma) | (lsu_lsc_ctl.io.lsu_pkt_r.valid & !lsu_lsc_ctl.io.lsu_pkt_r.bits.dma)) & bus_intf.io.lsu_bus_buffer_empty_any & bus_intf.io.lsu_bus_idle_any
|
||||
// Instantiate the store buffer
|
||||
val store_stbuf_reqvld_r = lsu_lsc_ctl.io.lsu_pkt_r.valid & lsu_lsc_ctl.io.lsu_pkt_r.store & lsu_lsc_ctl.io.addr_in_dccm_r & !flush_r & !lsu_lsc_ctl.io.lsu_pkt_r.dma
|
||||
val store_stbuf_reqvld_r = lsu_lsc_ctl.io.lsu_pkt_r.valid & lsu_lsc_ctl.io.lsu_pkt_r.bits.store & lsu_lsc_ctl.io.addr_in_dccm_r & !flush_r & !lsu_lsc_ctl.io.lsu_pkt_r.bits.dma
|
||||
// Disable Forwarding for now
|
||||
val lsu_cmpen_m = lsu_lsc_ctl.io.lsu_pkt_m.valid & (lsu_lsc_ctl.io.lsu_pkt_m.load | lsu_lsc_ctl.io.lsu_pkt_m.store) & (lsu_lsc_ctl.io.addr_in_dccm_m | lsu_lsc_ctl.io.addr_in_pic_m)
|
||||
val lsu_cmpen_m = lsu_lsc_ctl.io.lsu_pkt_m.valid & (lsu_lsc_ctl.io.lsu_pkt_m.bits.load | lsu_lsc_ctl.io.lsu_pkt_m.bits.store) & (lsu_lsc_ctl.io.addr_in_dccm_m | lsu_lsc_ctl.io.addr_in_pic_m)
|
||||
// Bus signals
|
||||
val lsu_busreq_m = lsu_lsc_ctl.io.lsu_pkt_m.valid & ((lsu_lsc_ctl.io.lsu_pkt_m.load | lsu_lsc_ctl.io.lsu_pkt_m.store) & lsu_lsc_ctl.io.addr_external_m) & !flush_m_up & !lsu_lsc_ctl.io.lsu_exc_m & !lsu_lsc_ctl.io.lsu_pkt_m.fast_int
|
||||
val lsu_busreq_m = lsu_lsc_ctl.io.lsu_pkt_m.valid & ((lsu_lsc_ctl.io.lsu_pkt_m.bits.load | lsu_lsc_ctl.io.lsu_pkt_m.bits.store) & lsu_lsc_ctl.io.addr_external_m) & !flush_m_up & !lsu_lsc_ctl.io.lsu_exc_m & !lsu_lsc_ctl.io.lsu_pkt_m.bits.fast_int
|
||||
// PMU signals
|
||||
io.lsu_pmu_misaligned_m := lsu_lsc_ctl.io.lsu_pkt_m.valid & ((lsu_lsc_ctl.io.lsu_pkt_m.half & lsu_lsc_ctl.io.lsu_addr_m(0)) | (lsu_lsc_ctl.io.lsu_pkt_m.word & lsu_lsc_ctl.io.lsu_addr_m(1,0).orR))
|
||||
io.lsu_pmu_load_external_m := lsu_lsc_ctl.io.lsu_pkt_m.valid & lsu_lsc_ctl.io.lsu_pkt_m.load & lsu_lsc_ctl.io.addr_external_m
|
||||
io.lsu_pmu_store_external_m := lsu_lsc_ctl.io.lsu_pkt_m.valid & lsu_lsc_ctl.io.lsu_pkt_m.store & lsu_lsc_ctl.io.addr_external_m
|
||||
io.lsu_pmu_misaligned_m := lsu_lsc_ctl.io.lsu_pkt_m.valid & ((lsu_lsc_ctl.io.lsu_pkt_m.bits.half & lsu_lsc_ctl.io.lsu_addr_m(0)) | (lsu_lsc_ctl.io.lsu_pkt_m.bits.word & lsu_lsc_ctl.io.lsu_addr_m(1,0).orR))
|
||||
io.lsu_pmu_load_external_m := lsu_lsc_ctl.io.lsu_pkt_m.valid & lsu_lsc_ctl.io.lsu_pkt_m.bits.load & lsu_lsc_ctl.io.addr_external_m
|
||||
io.lsu_pmu_store_external_m := lsu_lsc_ctl.io.lsu_pkt_m.valid & lsu_lsc_ctl.io.lsu_pkt_m.bits.store & lsu_lsc_ctl.io.addr_external_m
|
||||
|
||||
//LSU_LSC_Control
|
||||
//Inputs
|
||||
|
|
@ -217,7 +217,7 @@ class el2_lsu extends Module with RequireAsyncReset with param with el2_lib {
|
|||
lsu_lsc_ctl.io.flush_r := flush_r
|
||||
lsu_lsc_ctl.io.exu_lsu_rs1_d := io.exu_lsu_rs1_d
|
||||
lsu_lsc_ctl.io.exu_lsu_rs2_d := io.exu_lsu_rs2_d
|
||||
lsu_lsc_ctl.io.lsu_p := io.lsu_p
|
||||
lsu_lsc_ctl.io.lsu_p <> io.lsu_p
|
||||
lsu_lsc_ctl.io.dec_lsu_valid_raw_d := io.dec_lsu_valid_raw_d
|
||||
lsu_lsc_ctl.io.dec_lsu_offset_d := io.dec_lsu_offset_d
|
||||
lsu_lsc_ctl.io.picm_mask_data_m := dccm_ctl.io.picm_mask_data_m
|
||||
|
|
@ -232,9 +232,9 @@ class el2_lsu extends Module with RequireAsyncReset with param with el2_lib {
|
|||
//Outputs
|
||||
|
||||
io.lsu_single_ecc_error_incr := lsu_lsc_ctl.io.lsu_single_ecc_error_incr
|
||||
io.lsu_error_pkt_r := lsu_lsc_ctl.io.lsu_error_pkt_r
|
||||
io.lsu_fir_addr := lsu_lsc_ctl.io.lsu_fir_addr
|
||||
io.lsu_fir_error := lsu_lsc_ctl.io.lsu_fir_error
|
||||
io.lsu_error_pkt_r <> lsu_lsc_ctl.io.lsu_error_pkt_r
|
||||
io.lsu_fir_addr <> lsu_lsc_ctl.io.lsu_fir_addr
|
||||
io.lsu_fir_error <> lsu_lsc_ctl.io.lsu_fir_error
|
||||
// DCCM Control
|
||||
//Inputs
|
||||
dccm_ctl.io.lsu_c2_m_clk := clkdomain.io.lsu_c2_m_clk
|
||||
|
|
@ -243,9 +243,9 @@ class el2_lsu extends Module with RequireAsyncReset with param with el2_lib {
|
|||
dccm_ctl.io.lsu_c1_r_clk := clkdomain.io.lsu_free_c2_clk
|
||||
dccm_ctl.io.lsu_store_c1_r_clk := clkdomain.io.lsu_c1_r_clk
|
||||
//dccm_ctl.io.clk := clock
|
||||
dccm_ctl.io.lsu_pkt_d := lsu_lsc_ctl.io.lsu_pkt_d
|
||||
dccm_ctl.io.lsu_pkt_m := lsu_lsc_ctl.io.lsu_pkt_m
|
||||
dccm_ctl.io.lsu_pkt_r := lsu_lsc_ctl.io.lsu_pkt_r
|
||||
dccm_ctl.io.lsu_pkt_d <> lsu_lsc_ctl.io.lsu_pkt_d
|
||||
dccm_ctl.io.lsu_pkt_m <> lsu_lsc_ctl.io.lsu_pkt_m
|
||||
dccm_ctl.io.lsu_pkt_r <> lsu_lsc_ctl.io.lsu_pkt_r
|
||||
dccm_ctl.io.addr_in_dccm_d := lsu_lsc_ctl.io.addr_in_dccm_d
|
||||
dccm_ctl.io.addr_in_dccm_m := lsu_lsc_ctl.io.addr_in_dccm_m
|
||||
dccm_ctl.io.addr_in_dccm_r := lsu_lsc_ctl.io.addr_in_dccm_r
|
||||
|
|
@ -320,8 +320,8 @@ class el2_lsu extends Module with RequireAsyncReset with param with el2_lib {
|
|||
stbuf.io.lsu_c1_r_clk := clkdomain.io.lsu_c1_m_clk
|
||||
stbuf.io.lsu_stbuf_c1_clk := clkdomain.io.lsu_stbuf_c1_clk
|
||||
stbuf.io.lsu_free_c2_clk := clkdomain.io.lsu_free_c2_clk
|
||||
stbuf.io.lsu_pkt_m := lsu_lsc_ctl.io.lsu_pkt_m
|
||||
stbuf.io.lsu_pkt_r := lsu_lsc_ctl.io.lsu_pkt_r
|
||||
stbuf.io.lsu_pkt_m <> lsu_lsc_ctl.io.lsu_pkt_m
|
||||
stbuf.io.lsu_pkt_r <> lsu_lsc_ctl.io.lsu_pkt_r
|
||||
stbuf.io.store_stbuf_reqvld_r := store_stbuf_reqvld_r
|
||||
stbuf.io.lsu_commit_r := lsu_lsc_ctl.io.lsu_commit_r
|
||||
stbuf.io.dec_lsu_valid_raw_d := io.dec_lsu_valid_raw_d
|
||||
|
|
@ -344,8 +344,8 @@ class el2_lsu extends Module with RequireAsyncReset with param with el2_lib {
|
|||
// ECC
|
||||
//Inputs
|
||||
ecc.io.lsu_c2_r_clk := clkdomain.io.lsu_c2_r_clk
|
||||
ecc.io.lsu_pkt_m := lsu_lsc_ctl.io.lsu_pkt_m
|
||||
ecc.io.lsu_pkt_r := lsu_lsc_ctl.io.lsu_pkt_r
|
||||
ecc.io.lsu_pkt_m <> lsu_lsc_ctl.io.lsu_pkt_m
|
||||
ecc.io.lsu_pkt_r <> lsu_lsc_ctl.io.lsu_pkt_r
|
||||
ecc.io.stbuf_data_any := stbuf.io.stbuf_data_any
|
||||
ecc.io.dec_tlu_core_ecc_disable := io.dec_tlu_core_ecc_disable
|
||||
ecc.io.lsu_dccm_rden_r := dccm_ctl.io.lsu_dccm_rden_r
|
||||
|
|
@ -373,8 +373,8 @@ class el2_lsu extends Module with RequireAsyncReset with param with el2_lib {
|
|||
|
||||
//Trigger
|
||||
//Inputs
|
||||
trigger.io.trigger_pkt_any := io.trigger_pkt_any
|
||||
trigger.io.lsu_pkt_m := lsu_lsc_ctl.io.lsu_pkt_m
|
||||
trigger.io.trigger_pkt_any <> io.trigger_pkt_any
|
||||
trigger.io.lsu_pkt_m <> lsu_lsc_ctl.io.lsu_pkt_m
|
||||
trigger.io.lsu_addr_m := lsu_lsc_ctl.io.lsu_addr_m
|
||||
trigger.io.store_data_m := lsu_lsc_ctl.io.store_data_m
|
||||
//Outputs
|
||||
|
|
@ -395,9 +395,9 @@ class el2_lsu extends Module with RequireAsyncReset with param with el2_lib {
|
|||
clkdomain.io.lsu_stbuf_empty_any := stbuf.io.lsu_stbuf_empty_any
|
||||
clkdomain.io.lsu_bus_clk_en := io.lsu_bus_clk_en
|
||||
clkdomain.io.lsu_p := io.lsu_p
|
||||
clkdomain.io.lsu_pkt_d := lsu_lsc_ctl.io.lsu_pkt_d
|
||||
clkdomain.io.lsu_pkt_m := lsu_lsc_ctl.io.lsu_pkt_m
|
||||
clkdomain.io.lsu_pkt_r := lsu_lsc_ctl.io.lsu_pkt_r
|
||||
clkdomain.io.lsu_pkt_d <> lsu_lsc_ctl.io.lsu_pkt_d
|
||||
clkdomain.io.lsu_pkt_m <> lsu_lsc_ctl.io.lsu_pkt_m
|
||||
clkdomain.io.lsu_pkt_r <> lsu_lsc_ctl.io.lsu_pkt_r
|
||||
clkdomain.io.scan_mode := io.scan_mode
|
||||
|
||||
//Bus Interface
|
||||
|
|
|
|||
|
|
@ -13,7 +13,7 @@ class el2_lsu_addrcheck extends Module with RequireAsyncReset with el2_lib
|
|||
|
||||
val start_addr_d = Input(UInt(32.W))
|
||||
val end_addr_d = Input(UInt(32.W))
|
||||
val lsu_pkt_d = Input(new el2_lsu_pkt_t)
|
||||
val lsu_pkt_d = Flipped(Valid(new el2_lsu_pkt_t))
|
||||
val dec_tlu_mrac_ff = Input(UInt(32.W))
|
||||
val rs1_region_d = Input(UInt(4.W))
|
||||
val rs1_d = Input(UInt(32.W))
|
||||
|
|
@ -58,8 +58,8 @@ class el2_lsu_addrcheck extends Module with RequireAsyncReset with el2_lib
|
|||
|
||||
io.addr_external_d := ~(start_addr_in_dccm_region_d | start_addr_in_pic_region_d); //if start address does not belong to dccm/pic
|
||||
val csr_idx = Cat(io.start_addr_d(31,28),1.U)
|
||||
val is_sideeffects_d = io.dec_tlu_mrac_ff(csr_idx) & !(start_addr_in_dccm_region_d | start_addr_in_pic_region_d | addr_in_iccm) & io.lsu_pkt_d.valid & (io.lsu_pkt_d.store | io.lsu_pkt_d.load) //every region has the 2 LSB indicating ( 1: sideeffects/no_side effects, and 0: cacheable ). Ignored in internal regions
|
||||
val is_aligned_d = (io.lsu_pkt_d.word & (io.start_addr_d(1,0) === 0.U)) | (io.lsu_pkt_d.half & (io.start_addr_d(0) === 0.U)) | io.lsu_pkt_d.by
|
||||
val is_sideeffects_d = io.dec_tlu_mrac_ff(csr_idx) & !(start_addr_in_dccm_region_d | start_addr_in_pic_region_d | addr_in_iccm) & io.lsu_pkt_d.valid & (io.lsu_pkt_d.bits.store | io.lsu_pkt_d.bits.load) //every region has the 2 LSB indicating ( 1: sideeffects/no_side effects, and 0: cacheable ). Ignored in internal regions
|
||||
val is_aligned_d = (io.lsu_pkt_d.bits.word & (io.start_addr_d(1,0) === 0.U)) | (io.lsu_pkt_d.bits.half & (io.start_addr_d(0) === 0.U)) | io.lsu_pkt_d.bits.by
|
||||
|
||||
|
||||
val non_dccm_access_ok = (!(Cat(DATA_ACCESS_ENABLE0.B ,DATA_ACCESS_ENABLE1.B ,DATA_ACCESS_ENABLE2.B ,DATA_ACCESS_ENABLE3.B ,
|
||||
|
|
@ -83,7 +83,7 @@ class el2_lsu_addrcheck extends Module with RequireAsyncReset with el2_lib
|
|||
(DATA_ACCESS_ENABLE7.B & ((io.end_addr_d(31,0) | aslong(DATA_ACCESS_MASK7).U)) === (aslong(DATA_ACCESS_ADDR7).U | aslong(DATA_ACCESS_MASK7).U))))
|
||||
|
||||
val regpred_access_fault_d = (start_addr_dccm_or_pic ^ base_reg_dccm_or_pic)
|
||||
val picm_access_fault_d = (io.addr_in_pic_d & ((io.start_addr_d(1,0) =/= 0.U(2.W)) | !io.lsu_pkt_d.word))
|
||||
val picm_access_fault_d = (io.addr_in_pic_d & ((io.start_addr_d(1,0) =/= 0.U(2.W)) | !io.lsu_pkt_d.bits.word))
|
||||
|
||||
val unmapped_access_fault_d = WireInit(1.U(1.W))
|
||||
val mpu_access_fault_d = WireInit(1.U(1.W))
|
||||
|
|
@ -108,15 +108,15 @@ class el2_lsu_addrcheck extends Module with RequireAsyncReset with el2_lib
|
|||
}
|
||||
|
||||
//check width of access_fault_mscause_d
|
||||
io.access_fault_d := (unmapped_access_fault_d | mpu_access_fault_d | picm_access_fault_d | regpred_access_fault_d) & io.lsu_pkt_d.valid & !io.lsu_pkt_d.dma
|
||||
io.access_fault_d := (unmapped_access_fault_d | mpu_access_fault_d | picm_access_fault_d | regpred_access_fault_d) & io.lsu_pkt_d.valid & !io.lsu_pkt_d.bits.dma
|
||||
val access_fault_mscause_d = Mux(unmapped_access_fault_d.asBool,2.U(4.W), Mux(mpu_access_fault_d.asBool,3.U(4.W), Mux(regpred_access_fault_d.asBool,5.U(4.W), Mux(picm_access_fault_d.asBool,6.U(4.W),0.U(4.W)))))
|
||||
val regcross_misaligned_fault_d = (io.start_addr_d(31,28) =/= io.end_addr_d(31,28))
|
||||
val sideeffect_misaligned_fault_d = (is_sideeffects_d & !is_aligned_d)
|
||||
io.misaligned_fault_d := (regcross_misaligned_fault_d | (sideeffect_misaligned_fault_d & io.addr_external_d)) & io.lsu_pkt_d.valid & !io.lsu_pkt_d.dma
|
||||
io.misaligned_fault_d := (regcross_misaligned_fault_d | (sideeffect_misaligned_fault_d & io.addr_external_d)) & io.lsu_pkt_d.valid & !io.lsu_pkt_d.bits.dma
|
||||
val misaligned_fault_mscause_d = Mux(regcross_misaligned_fault_d,2.U(4.W),Mux(sideeffect_misaligned_fault_d.asBool,1.U(4.W),0.U(4.W)))
|
||||
io.exc_mscause_d := Mux(io.misaligned_fault_d.asBool, misaligned_fault_mscause_d(3,0), access_fault_mscause_d(3,0))
|
||||
io.fir_dccm_access_error_d := ((start_addr_in_dccm_region_d & !start_addr_in_dccm_d)|(end_addr_in_dccm_region_d & !end_addr_in_dccm_d)) & io.lsu_pkt_d.valid & io.lsu_pkt_d.fast_int
|
||||
io.fir_nondccm_access_error_d := !(start_addr_in_dccm_region_d & end_addr_in_dccm_region_d) & io.lsu_pkt_d.valid & io.lsu_pkt_d.fast_int
|
||||
io.fir_dccm_access_error_d := ((start_addr_in_dccm_region_d & !start_addr_in_dccm_d)|(end_addr_in_dccm_region_d & !end_addr_in_dccm_d)) & io.lsu_pkt_d.valid & io.lsu_pkt_d.bits.fast_int
|
||||
io.fir_nondccm_access_error_d := !(start_addr_in_dccm_region_d & end_addr_in_dccm_region_d) & io.lsu_pkt_d.valid & io.lsu_pkt_d.bits.fast_int
|
||||
|
||||
withClock(io.lsu_c2_m_clk){io.is_sideeffects_m := RegNext(is_sideeffects_d,0.U)} //TBD for clock and reset
|
||||
}
|
||||
|
|
|
|||
|
|
@ -21,8 +21,8 @@ class el2_lsu_bus_buffer extends Module with RequireAsyncReset with el2_lib {
|
|||
val lsu_free_c2_clk = Input(Clock())
|
||||
val lsu_busm_clk = Input(Clock())
|
||||
val dec_lsu_valid_raw_d = Input(Bool())
|
||||
val lsu_pkt_m = Input(new el2_lsu_pkt_t)
|
||||
val lsu_pkt_r = Input(new el2_lsu_pkt_t)
|
||||
val lsu_pkt_m = Flipped(Valid(new el2_lsu_pkt_t))
|
||||
val lsu_pkt_r = Flipped(Valid(new el2_lsu_pkt_t))
|
||||
val lsu_addr_m = Input(UInt(32.W))
|
||||
val end_addr_m = Input(UInt(32.W))
|
||||
val lsu_addr_r = Input(UInt(32.W))
|
||||
|
|
@ -186,6 +186,7 @@ class el2_lsu_bus_buffer extends Module with RequireAsyncReset with el2_lib {
|
|||
val buf_write_in = WireInit(UInt(DEPTH.W), 0.U)
|
||||
val buf_unsign = WireInit(UInt(DEPTH.W), 0.U)
|
||||
val buf_error = WireInit(UInt(DEPTH.W), 0.U)
|
||||
val CmdPtr1 = WireInit(UInt(DEPTH_LOG2.W), 0.U)
|
||||
|
||||
val ibuf_data = WireInit(UInt(32.W), 0.U)
|
||||
io.ld_byte_hit_buf_lo := (0 until 4).map(i => (ld_byte_hitvecfn_lo(i).orR | ld_byte_ibuf_hit_lo(i)).asUInt).reverse.reduce(Cat(_, _))
|
||||
|
|
@ -228,9 +229,9 @@ class el2_lsu_bus_buffer extends Module with RequireAsyncReset with el2_lib {
|
|||
(ld_fwddata_buf_hi_initial & ibuf_data)
|
||||
|
||||
val bus_coalescing_disable = io.dec_tlu_wb_coalescing_disable | BUILD_AHB_LITE.B
|
||||
val ldst_byteen_r = Mux1H(Seq(io.lsu_pkt_r.by -> 1.U(4.W),
|
||||
io.lsu_pkt_r.half -> 3.U(4.W),
|
||||
io.lsu_pkt_r.word -> 15.U(4.W)))
|
||||
val ldst_byteen_r = Mux1H(Seq(io.lsu_pkt_r.bits.by -> 1.U(4.W),
|
||||
io.lsu_pkt_r.bits.half -> 3.U(4.W),
|
||||
io.lsu_pkt_r.bits.word -> 15.U(4.W)))
|
||||
|
||||
val ldst_byteen_hi_r = Mux1H(Seq((io.lsu_addr_r(1,0)===0.U)->0.U(4.W),
|
||||
(io.lsu_addr_r(1,0)===1.U)->Cat(0.U(3.W), ldst_byteen_r(3)),
|
||||
|
|
@ -253,14 +254,14 @@ class el2_lsu_bus_buffer extends Module with RequireAsyncReset with el2_lib {
|
|||
|
||||
|
||||
val ldst_samedw_r = io.lsu_addr_r(3) === io.end_addr_r(3)
|
||||
val is_aligned_r = Mux1H(Seq(io.lsu_pkt_r.word -> (io.lsu_addr_r(1, 0) === 0.U),
|
||||
io.lsu_pkt_r.half -> !io.lsu_addr_r(0),
|
||||
io.lsu_pkt_r.by -> 1.U))
|
||||
val ibuf_byp = io.lsu_busreq_r & (io.lsu_pkt_r.load | io.no_word_merge_r) & !ibuf_valid
|
||||
val is_aligned_r = Mux1H(Seq(io.lsu_pkt_r.bits.word -> (io.lsu_addr_r(1, 0) === 0.U),
|
||||
io.lsu_pkt_r.bits.half -> !io.lsu_addr_r(0),
|
||||
io.lsu_pkt_r.bits.by -> 1.U))
|
||||
val ibuf_byp = io.lsu_busreq_r & (io.lsu_pkt_r.bits.load | io.no_word_merge_r) & !ibuf_valid
|
||||
val ibuf_wr_en = io.lsu_busreq_r & io.lsu_commit_r & !ibuf_byp
|
||||
val ibuf_drain_vld = WireInit(Bool(), false.B)
|
||||
val ibuf_rst = (ibuf_drain_vld & !ibuf_wr_en) | io.dec_tlu_force_halt
|
||||
val ibuf_force_drain = io.lsu_busreq_m & !io.lsu_busreq_r & ibuf_valid & (io.lsu_pkt_m.load | (ibuf_addr(31, 2) =/= io.lsu_addr_m(31, 2)))
|
||||
val ibuf_force_drain = io.lsu_busreq_m & !io.lsu_busreq_r & ibuf_valid & (io.lsu_pkt_m.bits.load | (ibuf_addr(31, 2) =/= io.lsu_addr_m(31, 2)))
|
||||
val ibuf_sideeffect = WireInit(Bool(), false.B)
|
||||
val ibuf_timer = WireInit(UInt(TIMER_LOG2.W), 0.U)
|
||||
val ibuf_merge_en = WireInit(Bool(), false.B)
|
||||
|
|
@ -273,7 +274,7 @@ class el2_lsu_bus_buffer extends Module with RequireAsyncReset with el2_lib {
|
|||
|
||||
val ibuf_tag_in = Mux(ibuf_merge_en & ibuf_merge_in, ibuf_tag, Mux(io.ldst_dual_r, WrPtr1_r, WrPtr0_r))
|
||||
val ibuf_dualtag_in = WrPtr0_r
|
||||
val ibuf_sz_in = Cat(io.lsu_pkt_r.word, io.lsu_pkt_r.half)
|
||||
val ibuf_sz_in = Cat(io.lsu_pkt_r.bits.word, io.lsu_pkt_r.bits.half)
|
||||
val ibuf_addr_in = Mux(io.ldst_dual_r, io.end_addr_r, io.lsu_addr_r)
|
||||
val ibuf_byteen_in = Mux(ibuf_merge_en & ibuf_merge_in, ibuf_byteen(3, 0) | ldst_byteen_lo_r(3, 0),
|
||||
Mux(io.ldst_dual_r, ldst_byteen_hi_r(3, 0), ldst_byteen_lo_r(3, 0)))
|
||||
|
|
@ -284,7 +285,7 @@ class el2_lsu_bus_buffer extends Module with RequireAsyncReset with el2_lib {
|
|||
Mux(io.ldst_dual_r, store_data_hi_r((8 * i) + 7, 8 * i), store_data_lo_r((8 * i) + 7, 8 * i)))).reverse.reduce(Cat(_, _))
|
||||
val ibuf_timer_in = Mux(ibuf_wr_en, 0.U, Mux((ibuf_timer<TIMER_MAX.U).asBool(), ibuf_timer+1.U, ibuf_timer))
|
||||
|
||||
ibuf_merge_en := io.lsu_busreq_r & io.lsu_commit_r & io.lsu_pkt_r.store & ibuf_valid & ibuf_write & (io.lsu_addr_r(31,2) === ibuf_addr(31,2)) & !io.is_sideeffects_r & !bus_coalescing_disable
|
||||
ibuf_merge_en := io.lsu_busreq_r & io.lsu_commit_r & io.lsu_pkt_r.bits.store & ibuf_valid & ibuf_write & (io.lsu_addr_r(31,2) === ibuf_addr(31,2)) & !io.is_sideeffects_r & !bus_coalescing_disable
|
||||
ibuf_merge_in := !io.ldst_dual_r
|
||||
val ibuf_byteen_out = (0 until 4).map(i=>(Mux(ibuf_merge_en & !ibuf_merge_in, ibuf_byteen(i) | ldst_byteen_lo_r(i), ibuf_byteen(i))).asUInt).reverse.reduce(Cat(_,_))
|
||||
val ibuf_data_out = (0 until 4).map(i=>Mux(ibuf_merge_en & !ibuf_merge_in, Mux(ldst_byteen_lo_r(i), store_data_lo_r((8*i)+7, 8*i), ibuf_data((8*i)+7, 8*i)), ibuf_data((8*i)+7, 8*i))).reverse.reduce(Cat(_,_))
|
||||
|
|
@ -296,8 +297,8 @@ class el2_lsu_bus_buffer extends Module with RequireAsyncReset with el2_lib {
|
|||
val ibuf_samedw = withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(ldst_samedw_r, 0.U, ibuf_wr_en)}
|
||||
val ibuf_nomerge = withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(io.no_dword_merge_r, 0.U, ibuf_wr_en)}
|
||||
ibuf_sideeffect := withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(io.is_sideeffects_r, 0.U, ibuf_wr_en)}
|
||||
val ibuf_unsign = withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(io.lsu_pkt_r.unsign, 0.U, ibuf_wr_en)}
|
||||
ibuf_write := withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(io.lsu_pkt_r.store, 0.U, ibuf_wr_en)}
|
||||
val ibuf_unsign = withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(io.lsu_pkt_r.bits.unsign, 0.U, ibuf_wr_en)}
|
||||
ibuf_write := withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(io.lsu_pkt_r.bits.store, 0.U, ibuf_wr_en)}
|
||||
val ibuf_sz = withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(ibuf_sz_in, 0.U, ibuf_wr_en)}
|
||||
ibuf_addr := rvdffe(ibuf_addr_in, ibuf_wr_en, clock, io.scan_mode)
|
||||
ibuf_byteen := withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(ibuf_byteen_in, 0.U, ibuf_wr_en)}
|
||||
|
|
@ -318,7 +319,7 @@ class el2_lsu_bus_buffer extends Module with RequireAsyncReset with el2_lib {
|
|||
val obuf_wr_timer_in = Mux(obuf_wr_en, 0.U(3.W), Mux(buf_numvld_cmd_any.orR & (obuf_wr_timer<TIMER_MAX.U), obuf_wr_timer+1.U, obuf_wr_timer))
|
||||
obuf_force_wr_en := io.lsu_busreq_m & !io.lsu_busreq_r & !ibuf_valid & (buf_numvld_cmd_any===1.U) & (io.lsu_addr_m(31,2)=/=Mux1H((0 until math.pow(2,LSU_NUM_NBLOAD_WIDTH).asInstanceOf[Int]).map(i=>(CmdPtr0===i.U)->buf_addr(i)(31,2))))
|
||||
val buf_numvld_pend_any = WireInit(UInt(4.W), 0.U)
|
||||
val ibuf_buf_byp = ibuf_byp & (buf_numvld_pend_any===0.U) & (!io.lsu_pkt_r.store | io.no_dword_merge_r)
|
||||
val ibuf_buf_byp = ibuf_byp & (buf_numvld_pend_any===0.U) & (!io.lsu_pkt_r.bits.store | io.no_dword_merge_r)
|
||||
val bus_sideeffect_pend = WireInit(Bool(), false.B)
|
||||
val found_cmdptr0 = WireInit(Bool(), false.B)
|
||||
val buf_cmd_state_bus_en = Wire(Vec(DEPTH, Bool()))
|
||||
|
|
@ -340,18 +341,18 @@ class el2_lsu_bus_buffer extends Module with RequireAsyncReset with el2_lib {
|
|||
obuf_force_wr_en))) & (bus_cmd_ready | !obuf_valid | obuf_nosend) & !obuf_wr_wait & !lsu_bus_cntr_overflow & !bus_addr_match_pending & io.lsu_bus_clk_en
|
||||
val bus_cmd_sent = WireInit(Bool(), false.B)
|
||||
val obuf_rst = ((bus_cmd_sent | (obuf_valid & obuf_nosend)) & !obuf_wr_en & io.lsu_bus_clk_en) | io.dec_tlu_force_halt
|
||||
val obuf_write_in = Mux(ibuf_buf_byp, io.lsu_pkt_r.store, indexing(buf_write, CmdPtr0))
|
||||
val obuf_write_in = Mux(ibuf_buf_byp, io.lsu_pkt_r.bits.store, indexing(buf_write, CmdPtr0))
|
||||
val obuf_sideeffect_in = Mux(ibuf_buf_byp, io.is_sideeffects_r, indexing(buf_sideeffect, CmdPtr0))
|
||||
val obuf_addr_in = Mux(ibuf_buf_byp, io.lsu_addr_r, indexing(buf_addr, CmdPtr0))
|
||||
val buf_sz = Wire(Vec(DEPTH, UInt(2.W)))
|
||||
buf_sz := buf_sz.map(i=> 0.U)
|
||||
val obuf_sz_in = Mux(ibuf_buf_byp, Cat(io.lsu_pkt_r.word, io.lsu_pkt_r.half), indexing(buf_sz, CmdPtr0))
|
||||
val obuf_sz_in = Mux(ibuf_buf_byp, Cat(io.lsu_pkt_r.bits.word, io.lsu_pkt_r.bits.half), indexing(buf_sz, CmdPtr0))
|
||||
val obuf_merge_en = WireInit(Bool(), false.B)
|
||||
val obuf_merge_in = obuf_merge_en
|
||||
val obuf_tag0_in = Mux(ibuf_buf_byp, WrPtr0_r, CmdPtr0)
|
||||
val Cmdptr1 = WireInit(UInt(DEPTH_LOG2.W), 0.U)
|
||||
//val Cmdptr1 = WireInit(UInt(DEPTH_LOG2.W), 0.U)
|
||||
|
||||
val obuf_tag1_in = Mux(ibuf_buf_byp, WrPtr1_r, Cmdptr1)
|
||||
val obuf_tag1_in = Mux(ibuf_buf_byp, WrPtr1_r, CmdPtr1)
|
||||
val obuf_cmd_done = WireInit(Bool(), false.B)
|
||||
val bus_wcmd_sent = WireInit(Bool(), false.B)
|
||||
val obuf_cmd_done_in = !(obuf_wr_en | obuf_rst) & (obuf_cmd_done | bus_wcmd_sent)
|
||||
|
|
@ -377,21 +378,21 @@ class el2_lsu_bus_buffer extends Module with RequireAsyncReset with el2_lib {
|
|||
val obuf_byteen0_in = Mux(ibuf_buf_byp, Mux(io.lsu_addr_r(2), Cat(ldst_byteen_lo_r, 0.U(4.W)), Cat(0.U(4.W), ldst_byteen_lo_r)),
|
||||
Mux(indexing(buf_addr, CmdPtr0)(2).asBool(), Cat(indexing(buf_byteen, CmdPtr0), 0.U(4.W)), Cat(0.U(4.W),indexing(buf_byteen, CmdPtr0))))
|
||||
val obuf_byteen1_in = Mux(ibuf_buf_byp, Mux(io.end_addr_r(2), Cat(ldst_byteen_hi_r, 0.U(4.W)), Cat(0.U(4.W), ldst_byteen_hi_r)),
|
||||
Mux(indexing(buf_addr, Cmdptr1)(2).asBool(), Cat(indexing(buf_byteen, Cmdptr1), 0.U(4.W)), Cat(0.U(4.W),indexing(buf_byteen, Cmdptr1))))
|
||||
Mux(indexing(buf_addr, CmdPtr1)(2).asBool(), Cat(indexing(buf_byteen, CmdPtr1), 0.U(4.W)), Cat(0.U(4.W),indexing(buf_byteen, CmdPtr1))))
|
||||
|
||||
val obuf_data0_in = Mux(ibuf_buf_byp, Mux(io.lsu_addr_r(2), Cat(store_data_lo_r, 0.U(32.W)), Cat(0.U(32.W), store_data_lo_r)),
|
||||
Mux(indexing(buf_addr, CmdPtr0)(2).asBool(), Cat(indexing(buf_data, CmdPtr0), 0.U(32.W)), Cat(0.U(32.W),indexing(buf_data, CmdPtr0))))
|
||||
val obuf_data1_in = Mux(ibuf_buf_byp, Mux(io.lsu_addr_r(2), Cat(store_data_hi_r, 0.U(32.W)), Cat(0.U(32.W), store_data_hi_r)),
|
||||
Mux(indexing(buf_addr, Cmdptr1)(2).asBool(), Cat(indexing(buf_data, Cmdptr1), 0.U(32.W)), Cat(0.U(32.W),indexing(buf_data, Cmdptr1))))
|
||||
Mux(indexing(buf_addr, CmdPtr1)(2).asBool(), Cat(indexing(buf_data, CmdPtr1), 0.U(32.W)), Cat(0.U(32.W),indexing(buf_data, CmdPtr1))))
|
||||
val obuf_byteen_in = (0 until 8).map(i=>(obuf_byteen0_in(i) | (obuf_merge_en & obuf_byteen1_in(i))).asUInt).reverse.reduce(Cat(_,_))
|
||||
val obuf_data_in = (0 until 8).map(i=>Mux(obuf_merge_en & obuf_byteen1_in(i), obuf_data1_in((8*i)+7, 8*i), obuf_data0_in((8*i)+7, 8*i))).reverse.reduce(Cat(_,_))
|
||||
|
||||
val buf_dualhi = Wire(Vec(DEPTH, Bool()))
|
||||
buf_dualhi := buf_dualhi.map(i=> false.B)
|
||||
obuf_merge_en := ((CmdPtr0 =/= Cmdptr1) & found_cmdptr0 & found_cmdptr1 & (indexing(buf_state, CmdPtr0) === cmd_C) & (indexing(buf_state, Cmdptr1) === cmd_C) &
|
||||
obuf_merge_en := ((CmdPtr0 =/= CmdPtr1) & found_cmdptr0 & found_cmdptr1 & (indexing(buf_state, CmdPtr0) === cmd_C) & (indexing(buf_state, CmdPtr1) === cmd_C) &
|
||||
!indexing(buf_cmd_state_bus_en.map(_.asUInt).reverse.reduce(Cat(_,_)), CmdPtr0) & !indexing(buf_sideeffect, CmdPtr0) &
|
||||
((indexing(buf_write, CmdPtr0) & indexing(buf_write, Cmdptr1) &
|
||||
(indexing(buf_addr, CmdPtr0)(31,3)===indexing(buf_addr, Cmdptr1)(31,3)) & !bus_coalescing_disable & !BUILD_AXI_NATIVE.B) |
|
||||
((indexing(buf_write, CmdPtr0) & indexing(buf_write, CmdPtr1) &
|
||||
(indexing(buf_addr, CmdPtr0)(31,3)===indexing(buf_addr, CmdPtr1)(31,3)) & !bus_coalescing_disable & !BUILD_AXI_NATIVE.B) |
|
||||
(!indexing(buf_write, CmdPtr0) & indexing(buf_dual.map(_.asUInt).reverse.reduce(Cat(_,_)), CmdPtr0) & !indexing(buf_dualhi.map(_.asUInt).reverse.reduce(Cat(_,_)), CmdPtr0) & indexing(buf_samedw.map(_.asUInt).reverse.reduce(Cat(_,_)), CmdPtr0)))) |
|
||||
(ibuf_buf_byp & ldst_samedw_r & io.ldst_dual_r)
|
||||
|
||||
|
|
@ -439,7 +440,7 @@ class el2_lsu_bus_buffer extends Module with RequireAsyncReset with el2_lib {
|
|||
def Enc8x3(in: UInt) : UInt = Cat(in(4)|in(5)|in(6)|in(7), in(2)|in(3)|in(6)|in(7), in(1)|in(3)|in(5)|in(7))
|
||||
|
||||
|
||||
val CmdPtr1 = WireInit(UInt(DEPTH_LOG2.W), 0.U)
|
||||
|
||||
val RspPtr = WireInit(UInt(DEPTH_LOG2.W), 0.U)
|
||||
CmdPtr0 := Enc8x3(Cat(Fill(8-DEPTH, 0.U),CmdPtr0Dec))
|
||||
|
||||
|
|
@ -486,9 +487,9 @@ class el2_lsu_bus_buffer extends Module with RequireAsyncReset with el2_lib {
|
|||
buf_dualhi_in := (0 until DEPTH).map(i=>(Mux(ibuf_drainvec_vld(i), ibuf_dual ,ibuf_byp & io.ldst_dual_r & (WrPtr1_r===i.U))).asUInt).reverse.reduce(Cat(_,_))
|
||||
buf_dualtag_in := (0 until DEPTH).map(i=>Mux(ibuf_drainvec_vld(i), ibuf_dualtag, Mux(ibuf_byp & io.ldst_dual_r & (WrPtr1_r===i.U), WrPtr0_r, WrPtr1_r)))
|
||||
buf_sideeffect_in := (0 until DEPTH).map(i=>(Mux(ibuf_drainvec_vld(i), ibuf_sideeffect, io.is_sideeffects_r)).asUInt).reverse.reduce(Cat(_,_))
|
||||
buf_unsign_in := (0 until DEPTH).map(i=>(Mux(ibuf_drainvec_vld(i), ibuf_unsign, io.lsu_pkt_r.unsign)).asUInt).reverse.reduce(Cat(_,_))
|
||||
buf_sz_in := (0 until DEPTH).map(i=>Mux(ibuf_drainvec_vld(i), ibuf_sz, Cat(io.lsu_pkt_r.word, io.lsu_pkt_r.half)))
|
||||
buf_write_in := (0 until DEPTH).map(i=>(Mux(ibuf_drainvec_vld(i), ibuf_write, io.lsu_pkt_r.store)).asUInt).reverse.reduce(Cat(_,_))
|
||||
buf_unsign_in := (0 until DEPTH).map(i=>(Mux(ibuf_drainvec_vld(i), ibuf_unsign, io.lsu_pkt_r.bits.unsign)).asUInt).reverse.reduce(Cat(_,_))
|
||||
buf_sz_in := (0 until DEPTH).map(i=>Mux(ibuf_drainvec_vld(i), ibuf_sz, Cat(io.lsu_pkt_r.bits.word, io.lsu_pkt_r.bits.half)))
|
||||
buf_write_in := (0 until DEPTH).map(i=>(Mux(ibuf_drainvec_vld(i), ibuf_write, io.lsu_pkt_r.bits.store)).asUInt).reverse.reduce(Cat(_,_))
|
||||
|
||||
for(i<- 0 until DEPTH) {
|
||||
switch(buf_state(i)) {
|
||||
|
|
@ -580,7 +581,7 @@ class el2_lsu_bus_buffer extends Module with RequireAsyncReset with el2_lib {
|
|||
io.lsu_bus_buffer_full_any := Mux(io.ldst_dual_d & io.dec_lsu_valid_raw_d, buf_numvld_any>=(DEPTH-1).U, buf_numvld_any===DEPTH.U)
|
||||
io.lsu_bus_buffer_empty_any := !(buf_state.map(_.orR).reduce(_|_)) & !ibuf_valid & !obuf_valid
|
||||
|
||||
io.lsu_nonblock_load_valid_m := io.lsu_busreq_m & io.lsu_pkt_m.valid & io.lsu_pkt_m.load & !io.flush_m_up & !io.ld_full_hit_m
|
||||
io.lsu_nonblock_load_valid_m := io.lsu_busreq_m & io.lsu_pkt_m.valid & io.lsu_pkt_m.bits.load & !io.flush_m_up & !io.ld_full_hit_m
|
||||
io.lsu_nonblock_load_tag_m := WrPtr0_m
|
||||
val lsu_nonblock_load_valid_r = WireInit(Bool(), false.B)
|
||||
io.lsu_nonblock_load_inv_r := lsu_nonblock_load_valid_r & !io.lsu_commit_r
|
||||
|
|
|
|||
|
|
@ -24,8 +24,8 @@ class el2_lsu_bus_intf extends Module with RequireAsyncReset with el2_lib {
|
|||
val dec_lsu_valid_raw_d = Input(Bool())
|
||||
val lsu_busreq_m = Input(Bool())
|
||||
|
||||
val lsu_pkt_m = Input(new el2_lsu_pkt_t)
|
||||
val lsu_pkt_r = Input(new el2_lsu_pkt_t)
|
||||
val lsu_pkt_m = Flipped(Valid(new el2_lsu_pkt_t))
|
||||
val lsu_pkt_r = Flipped(Valid(new el2_lsu_pkt_t))
|
||||
|
||||
val lsu_addr_d = Input(UInt(32.W))
|
||||
val lsu_addr_m = Input(UInt(32.W))
|
||||
|
|
@ -273,12 +273,12 @@ class el2_lsu_bus_intf extends Module with RequireAsyncReset with el2_lib {
|
|||
|
||||
|
||||
|
||||
ldst_byteen_m := Mux1H(Seq(io.lsu_pkt_m.word.asBool -> 15.U(4.W), io.lsu_pkt_m.half.asBool -> 3.U(4.W), io.lsu_pkt_m.by.asBool -> 1.U(4.W)))
|
||||
ldst_byteen_m := Mux1H(Seq(io.lsu_pkt_m.bits.word.asBool -> 15.U(4.W), io.lsu_pkt_m.bits.half.asBool -> 3.U(4.W), io.lsu_pkt_m.bits.by.asBool -> 1.U(4.W)))
|
||||
ldst_dual_d := io.lsu_addr_d(2) =/= io.end_addr_d(2)
|
||||
addr_match_dw_lo_r_m := (io.lsu_addr_r(31,3) === io.lsu_addr_m(31,3))
|
||||
addr_match_word_lo_r_m := addr_match_dw_lo_r_m & !(io.lsu_addr_r(2)^io.lsu_addr_m(2))
|
||||
no_word_merge_r := io.lsu_busreq_r & !ldst_dual_r & io.lsu_busreq_m & (io.lsu_pkt_m.load | !addr_match_word_lo_r_m)
|
||||
no_dword_merge_r := io.lsu_busreq_r & !ldst_dual_r & io.lsu_busreq_m & (io.lsu_pkt_m.load | !addr_match_dw_lo_r_m)
|
||||
no_word_merge_r := io.lsu_busreq_r & !ldst_dual_r & io.lsu_busreq_m & (io.lsu_pkt_m.bits.load | !addr_match_word_lo_r_m)
|
||||
no_dword_merge_r := io.lsu_busreq_r & !ldst_dual_r & io.lsu_busreq_m & (io.lsu_pkt_m.bits.load | !addr_match_dw_lo_r_m)
|
||||
|
||||
ldst_byteen_ext_m := ldst_byteen_m(3,0) << io.lsu_addr_m(1,0)
|
||||
ldst_byteen_ext_r := ldst_byteen_r(3,0) << io.lsu_addr_r(1,0)
|
||||
|
|
@ -290,10 +290,10 @@ class el2_lsu_bus_intf extends Module with RequireAsyncReset with el2_lib {
|
|||
|
||||
store_data_hi_r := store_data_ext_r(63,32)
|
||||
store_data_lo_r := store_data_ext_r(31,0)
|
||||
ld_addr_rhit_lo_lo := (io.lsu_addr_m(31,2) === io.lsu_addr_r(31,2)) & io.lsu_pkt_r.valid & io.lsu_pkt_r.store & io.lsu_busreq_m
|
||||
ld_addr_rhit_lo_hi := (io.end_addr_m(31,2) === io.lsu_addr_r(31,2)) & io.lsu_pkt_r.valid & io.lsu_pkt_r.store & io.lsu_busreq_m
|
||||
ld_addr_rhit_hi_lo := (io.lsu_addr_m(31,2) === io.end_addr_r(31,2)) & io.lsu_pkt_r.valid & io.lsu_pkt_r.store & io.lsu_busreq_m
|
||||
ld_addr_rhit_hi_hi := (io.end_addr_m(31,2) === io.end_addr_r(31,2)) & io.lsu_pkt_r.valid & io.lsu_pkt_r.store & io.lsu_busreq_m
|
||||
ld_addr_rhit_lo_lo := (io.lsu_addr_m(31,2) === io.lsu_addr_r(31,2)) & io.lsu_pkt_r.valid & io.lsu_pkt_r.bits.store & io.lsu_busreq_m
|
||||
ld_addr_rhit_lo_hi := (io.end_addr_m(31,2) === io.lsu_addr_r(31,2)) & io.lsu_pkt_r.valid & io.lsu_pkt_r.bits.store & io.lsu_busreq_m
|
||||
ld_addr_rhit_hi_lo := (io.lsu_addr_m(31,2) === io.end_addr_r(31,2)) & io.lsu_pkt_r.valid & io.lsu_pkt_r.bits.store & io.lsu_busreq_m
|
||||
ld_addr_rhit_hi_hi := (io.end_addr_m(31,2) === io.end_addr_r(31,2)) & io.lsu_pkt_r.valid & io.lsu_pkt_r.bits.store & io.lsu_busreq_m
|
||||
|
||||
ld_byte_rhit_lo_lo := (0 until 4).map(i =>(ld_addr_rhit_lo_lo & ldst_byteen_lo_r(i) & ldst_byteen_lo_m(i)).asUInt).reverse.reduce(Cat(_,_))
|
||||
ld_byte_rhit_lo_hi := (0 until 4).map(i =>(ld_addr_rhit_lo_hi & ldst_byteen_lo_r(i) & ldst_byteen_hi_m(i)).asUInt).reverse.reduce(Cat(_,_))
|
||||
|
|
@ -310,7 +310,7 @@ class el2_lsu_bus_intf extends Module with RequireAsyncReset with el2_lib {
|
|||
ld_fwddata_hi := (0 until 4).map(i =>(Mux(ld_byte_rhit_hi(i), ld_fwddata_rpipe_hi((8*i)+7,(8*i)), ld_fwddata_buf_hi((8*i)+7,(8*i)))).asUInt).reverse.reduce(Cat(_,_))
|
||||
ld_full_hit_lo_m := (0 until 4).map(i =>((ld_byte_hit_lo(i) | !ldst_byteen_lo_m(i))).asUInt).reduce(_&_)
|
||||
ld_full_hit_hi_m := (0 until 4).map(i =>((ld_byte_hit_hi(i) | !ldst_byteen_hi_m(i))).asUInt).reduce(_&_)
|
||||
ld_full_hit_m := ld_full_hit_lo_m & ld_full_hit_hi_m & io.lsu_busreq_m & io.lsu_pkt_m.load & !io.is_sideeffects_m
|
||||
ld_full_hit_m := ld_full_hit_lo_m & ld_full_hit_hi_m & io.lsu_busreq_m & io.lsu_pkt_m.bits.load & !io.is_sideeffects_m
|
||||
ld_fwddata_m := Cat(ld_fwddata_hi(31,0), ld_fwddata_lo(31,0)) >> (8.U*io.lsu_addr_m(1,0))
|
||||
io.bus_read_data_m := ld_fwddata_m(31,0)
|
||||
|
||||
|
|
|
|||
|
|
@ -26,10 +26,10 @@ class el2_lsu_clkdomain extends Module with RequireAsyncReset with el2_lib{
|
|||
|
||||
val lsu_bus_clk_en = Input(Bool()) // bus clock enable
|
||||
|
||||
val lsu_p = Input(new el2_lsu_pkt_t) // lsu packet in decode
|
||||
val lsu_pkt_d = Input(new el2_lsu_pkt_t) // lsu packet in d
|
||||
val lsu_pkt_m = Input(new el2_lsu_pkt_t) // lsu packet in m
|
||||
val lsu_pkt_r = Input(new el2_lsu_pkt_t) // lsu packet in r
|
||||
val lsu_p = Flipped(Valid(new el2_lsu_pkt_t)) // lsu packet in decode
|
||||
val lsu_pkt_d = Flipped(Valid(new el2_lsu_pkt_t)) // lsu packet in d
|
||||
val lsu_pkt_m = Flipped(Valid(new el2_lsu_pkt_t)) // lsu packet in m
|
||||
val lsu_pkt_r = Flipped(Valid(new el2_lsu_pkt_t)) // lsu packet in r
|
||||
|
||||
// Outputs
|
||||
val lsu_c1_m_clk = Output(Clock()) // m pipe single pulse clock
|
||||
|
|
@ -67,8 +67,8 @@ class el2_lsu_clkdomain extends Module with RequireAsyncReset with el2_lib{
|
|||
val lsu_c2_m_clken = lsu_c1_m_clken | lsu_c1_m_clken_q | io.clk_override
|
||||
val lsu_c2_r_clken = lsu_c1_r_clken | lsu_c1_r_clken_q | io.clk_override
|
||||
|
||||
val lsu_store_c1_m_clken = ((lsu_c1_m_clken & io.lsu_pkt_d.store) | io.clk_override)
|
||||
val lsu_store_c1_r_clken = ((lsu_c1_r_clken & io.lsu_pkt_m.store) | io.clk_override)
|
||||
val lsu_store_c1_m_clken = ((lsu_c1_m_clken & io.lsu_pkt_d.bits.store) | io.clk_override)
|
||||
val lsu_store_c1_r_clken = ((lsu_c1_r_clken & io.lsu_pkt_m.bits.store) | io.clk_override)
|
||||
val lsu_stbuf_c1_clken = io.ldst_stbuf_reqvld_r | io.stbuf_reqvld_any | io.stbuf_reqvld_flushed_any | io.clk_override
|
||||
val lsu_bus_ibuf_c1_clken = io.lsu_busreq_r | io.clk_override
|
||||
val lsu_bus_obuf_c1_clken = (io.lsu_bus_buffer_pend_any | io.lsu_busreq_r | io.clk_override) & io.lsu_bus_clk_en
|
||||
|
|
|
|||
|
|
@ -19,9 +19,9 @@ class el2_lsu_dccm_ctl extends Module with RequireAsyncReset with el2_lib
|
|||
val lsu_store_c1_r_clk = Input(Clock())
|
||||
// val clk = Input(Clock()) //tbd
|
||||
|
||||
val lsu_pkt_d = Input(new el2_lsu_pkt_t())
|
||||
val lsu_pkt_m = Input(new el2_lsu_pkt_t())
|
||||
val lsu_pkt_r = Input(new el2_lsu_pkt_t())
|
||||
val lsu_pkt_d = Flipped(Valid(new el2_lsu_pkt_t()))
|
||||
val lsu_pkt_m = Flipped(Valid(new el2_lsu_pkt_t()))
|
||||
val lsu_pkt_r = Flipped(Valid(new el2_lsu_pkt_t()))
|
||||
|
||||
val addr_in_dccm_d = Input(UInt(1.W))
|
||||
val addr_in_dccm_m = Input(UInt(1.W))
|
||||
|
|
@ -137,7 +137,7 @@ class el2_lsu_dccm_ctl extends Module with RequireAsyncReset with el2_lib
|
|||
|
||||
//Forwarding stbuf
|
||||
if (LOAD_TO_USE_PLUS1 == 1){
|
||||
io.dccm_dma_rvalid := io.lsu_pkt_r.valid & io.lsu_pkt_r.load & io.lsu_pkt_r.dma
|
||||
io.dccm_dma_rvalid := io.lsu_pkt_r.valid & io.lsu_pkt_r.bits.load & io.lsu_pkt_r.bits.dma
|
||||
io.dccm_dma_ecc_error := io.lsu_double_ecc_error_r //from ecc
|
||||
io.dccm_dma_rdata := lsu_rdata_corr_r
|
||||
//Registers
|
||||
|
|
@ -158,7 +158,7 @@ class el2_lsu_dccm_ctl extends Module with RequireAsyncReset with el2_lib
|
|||
}
|
||||
|
||||
else{
|
||||
io.dccm_dma_rvalid := io.lsu_pkt_m.valid & io.lsu_pkt_m.load & io.lsu_pkt_m.dma
|
||||
io.dccm_dma_rvalid := io.lsu_pkt_m.valid & io.lsu_pkt_m.bits.load & io.lsu_pkt_m.bits.dma
|
||||
io.dccm_dma_ecc_error := io.lsu_double_ecc_error_m //from ecc
|
||||
io.dccm_dma_rdata := lsu_rdata_corr_m
|
||||
io.dccm_dma_rtag := io.dma_mem_tag_m
|
||||
|
|
@ -176,17 +176,17 @@ class el2_lsu_dccm_ctl extends Module with RequireAsyncReset with el2_lib
|
|||
}
|
||||
|
||||
//Ecc error kill
|
||||
val kill_ecc_corr_lo_r = (((io.lsu_addr_d(DCCM_BITS-1,2) === io.lsu_addr_r(DCCM_BITS-1,2)).asUInt | (io.end_addr_d(DCCM_BITS-1,2) === io.lsu_addr_r(DCCM_BITS-1,2)).asUInt) & io.lsu_pkt_d.valid & io.lsu_pkt_d.store & io.lsu_pkt_d.dma & io.addr_in_dccm_d) |
|
||||
(((io.lsu_addr_m(DCCM_BITS-1,2) === io.lsu_addr_r(DCCM_BITS-1,2)).asUInt | (io.end_addr_m(DCCM_BITS-1,2) === io.lsu_addr_r(DCCM_BITS-1,2)).asUInt) & io.lsu_pkt_m.valid & io.lsu_pkt_m.store & io.lsu_pkt_m.dma & io.addr_in_dccm_m)
|
||||
val kill_ecc_corr_lo_r = (((io.lsu_addr_d(DCCM_BITS-1,2) === io.lsu_addr_r(DCCM_BITS-1,2)).asUInt | (io.end_addr_d(DCCM_BITS-1,2) === io.lsu_addr_r(DCCM_BITS-1,2)).asUInt) & io.lsu_pkt_d.valid & io.lsu_pkt_d.bits.store & io.lsu_pkt_d.bits.dma & io.addr_in_dccm_d) |
|
||||
(((io.lsu_addr_m(DCCM_BITS-1,2) === io.lsu_addr_r(DCCM_BITS-1,2)).asUInt | (io.end_addr_m(DCCM_BITS-1,2) === io.lsu_addr_r(DCCM_BITS-1,2)).asUInt) & io.lsu_pkt_m.valid & io.lsu_pkt_m.bits.store & io.lsu_pkt_m.bits.dma & io.addr_in_dccm_m)
|
||||
|
||||
val kill_ecc_corr_hi_r = (((io.lsu_addr_d(DCCM_BITS-1,2) === io.end_addr_r(DCCM_BITS-1,2)).asUInt | (io.end_addr_d(DCCM_BITS-1,2) === io.end_addr_r(DCCM_BITS-1,2)).asUInt) & io.lsu_pkt_d.valid & io.lsu_pkt_d.store & io.lsu_pkt_d.dma & io.addr_in_dccm_d) |
|
||||
(((io.lsu_addr_m(DCCM_BITS-1,2) === io.end_addr_r(DCCM_BITS-1,2)).asUInt | (io.end_addr_m(DCCM_BITS-1,2) === io.end_addr_r(DCCM_BITS-1,2)).asUInt) & io.lsu_pkt_m.valid & io.lsu_pkt_m.store & io.lsu_pkt_m.dma & io.addr_in_dccm_m)
|
||||
val kill_ecc_corr_hi_r = (((io.lsu_addr_d(DCCM_BITS-1,2) === io.end_addr_r(DCCM_BITS-1,2)).asUInt | (io.end_addr_d(DCCM_BITS-1,2) === io.end_addr_r(DCCM_BITS-1,2)).asUInt) & io.lsu_pkt_d.valid & io.lsu_pkt_d.bits.store & io.lsu_pkt_d.bits.dma & io.addr_in_dccm_d) |
|
||||
(((io.lsu_addr_m(DCCM_BITS-1,2) === io.end_addr_r(DCCM_BITS-1,2)).asUInt | (io.end_addr_m(DCCM_BITS-1,2) === io.end_addr_r(DCCM_BITS-1,2)).asUInt) & io.lsu_pkt_m.valid & io.lsu_pkt_m.bits.store & io.lsu_pkt_m.bits.dma & io.addr_in_dccm_m)
|
||||
|
||||
val ld_single_ecc_error_lo_r = io.lsu_pkt_r.load & io.single_ecc_error_lo_r & !io.lsu_raw_fwd_lo_r
|
||||
val ld_single_ecc_error_hi_r = io.lsu_pkt_r.load & io.single_ecc_error_hi_r & !io.lsu_raw_fwd_hi_r
|
||||
val ld_single_ecc_error_lo_r = io.lsu_pkt_r.bits.load & io.single_ecc_error_lo_r & !io.lsu_raw_fwd_lo_r
|
||||
val ld_single_ecc_error_hi_r = io.lsu_pkt_r.bits.load & io.single_ecc_error_hi_r & !io.lsu_raw_fwd_hi_r
|
||||
io.ld_single_ecc_error_r := (ld_single_ecc_error_lo_r | ld_single_ecc_error_hi_r) & !io.lsu_double_ecc_error_r
|
||||
val ld_single_ecc_error_lo_r_ns = ld_single_ecc_error_lo_r & (io.lsu_commit_r | io.lsu_pkt_r.dma) & !kill_ecc_corr_lo_r
|
||||
val ld_single_ecc_error_hi_r_ns = ld_single_ecc_error_hi_r & (io.lsu_commit_r | io.lsu_pkt_r.dma) & !kill_ecc_corr_hi_r
|
||||
val ld_single_ecc_error_lo_r_ns = ld_single_ecc_error_lo_r & (io.lsu_commit_r | io.lsu_pkt_r.bits.dma) & !kill_ecc_corr_lo_r
|
||||
val ld_single_ecc_error_hi_r_ns = ld_single_ecc_error_hi_r & (io.lsu_commit_r | io.lsu_pkt_r.bits.dma) & !kill_ecc_corr_hi_r
|
||||
|
||||
val lsu_double_ecc_error_r_ff = withClock(io.lsu_free_c2_clk){RegNext(io.lsu_double_ecc_error_r,0.U)}
|
||||
val ld_single_ecc_error_hi_r_ff = withClock(io.lsu_free_c2_clk){RegNext(ld_single_ecc_error_hi_r_ns,0.U)}
|
||||
|
|
@ -194,7 +194,7 @@ class el2_lsu_dccm_ctl extends Module with RequireAsyncReset with el2_lib
|
|||
|
||||
val ld_sec_addr_hi_r_ff = rvdffe(io.end_addr_r(DCCM_BITS-1,0),io.ld_single_ecc_error_r.asBool,clock,io.scan_mode.asBool)
|
||||
val ld_sec_addr_lo_r_ff = rvdffe(io.lsu_addr_r(DCCM_BITS-1,0),io.ld_single_ecc_error_r.asBool,clock,io.scan_mode.asBool)
|
||||
val lsu_dccm_rden_d = io.lsu_pkt_d.valid & (io.lsu_pkt_d.load | (io.lsu_pkt_d.store & (!(io.lsu_pkt_d.word | io.lsu_pkt_d.dword) | (io.lsu_addr_d(1,0) =/= 0.U(2.W))))) & io.addr_in_dccm_d
|
||||
val lsu_dccm_rden_d = io.lsu_pkt_d.valid & (io.lsu_pkt_d.bits.load | (io.lsu_pkt_d.bits.store & (!(io.lsu_pkt_d.bits.word | io.lsu_pkt_d.bits.dword) | (io.lsu_addr_d(1,0) =/= 0.U(2.W))))) & io.addr_in_dccm_d
|
||||
val lsu_dccm_wren_d = io.dma_dccm_wen
|
||||
|
||||
io.ld_single_ecc_error_r_ff := (ld_single_ecc_error_lo_r_ff | ld_single_ecc_error_hi_r_ff) & !lsu_double_ecc_error_r_ff
|
||||
|
|
@ -231,13 +231,13 @@ class el2_lsu_dccm_ctl extends Module with RequireAsyncReset with el2_lib
|
|||
Cat(io.stbuf_ecc_any(DCCM_ECC_WIDTH-1,0),io.stbuf_data_any(DCCM_DATA_WIDTH-1,0))))
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
// DCCM outputs
|
||||
val store_byteen_m = (Fill(4,io.lsu_pkt_m.store)) & ((Fill(4,io.lsu_pkt_m.by) & 1.U(4.W)) |
|
||||
(Fill(4,io.lsu_pkt_m.half) & 3.U(4.W)) |
|
||||
(Fill(4,io.lsu_pkt_m.word) & 15.U(4.W)))
|
||||
val store_byteen_m = (Fill(4,io.lsu_pkt_m.bits.store)) & ((Fill(4,io.lsu_pkt_m.bits.by) & 1.U(4.W)) |
|
||||
(Fill(4,io.lsu_pkt_m.bits.half) & 3.U(4.W)) |
|
||||
(Fill(4,io.lsu_pkt_m.bits.word) & 15.U(4.W)))
|
||||
|
||||
val store_byteen_r = (Fill(4,io.lsu_pkt_r.store)) & ((Fill(4,io.lsu_pkt_r.by) & 1.U(4.W)) |
|
||||
(Fill(4,io.lsu_pkt_r.half) & 3.U(4.W)) |
|
||||
(Fill(4,io.lsu_pkt_r.word) & 15.U(4.W)))
|
||||
val store_byteen_r = (Fill(4,io.lsu_pkt_r.bits.store)) & ((Fill(4,io.lsu_pkt_r.bits.by) & 1.U(4.W)) |
|
||||
(Fill(4,io.lsu_pkt_r.bits.half) & 3.U(4.W)) |
|
||||
(Fill(4,io.lsu_pkt_r.bits.word) & 15.U(4.W)))
|
||||
val store_byteen_ext_m = WireInit(UInt(8.W),0.U)
|
||||
store_byteen_ext_m := store_byteen_m(3,0) << io.lsu_addr_m(1,0) // The packet in m
|
||||
val store_byteen_ext_r = WireInit(UInt(8.W),0.U)
|
||||
|
|
@ -291,9 +291,9 @@ class el2_lsu_dccm_ctl extends Module with RequireAsyncReset with el2_lib
|
|||
io.dccm_data_ecc_lo_m := io.dccm_rd_data_lo(DCCM_FDATA_WIDTH-1,DCCM_DATA_WIDTH)
|
||||
io.dccm_data_ecc_hi_m := io.dccm_rd_data_hi(DCCM_FDATA_WIDTH-1,DCCM_DATA_WIDTH)
|
||||
|
||||
io.picm_wren := (io.lsu_pkt_r.valid & io.lsu_pkt_r.store & io.addr_in_pic_r & io.lsu_commit_r) | io.dma_pic_wen
|
||||
io.picm_rden := io.lsu_pkt_d.valid & io.lsu_pkt_d.load & io.addr_in_pic_d
|
||||
io.picm_mken := io.lsu_pkt_d.valid & io.lsu_pkt_d.store & io.addr_in_pic_d
|
||||
io.picm_wren := (io.lsu_pkt_r.valid & io.lsu_pkt_r.bits.store & io.addr_in_pic_r & io.lsu_commit_r) | io.dma_pic_wen
|
||||
io.picm_rden := io.lsu_pkt_d.valid & io.lsu_pkt_d.bits.load & io.addr_in_pic_d
|
||||
io.picm_mken := io.lsu_pkt_d.valid & io.lsu_pkt_d.bits.store & io.addr_in_pic_d
|
||||
io.picm_rdaddr := aslong(PIC_BASE_ADDR).U | Cat(Fill(32-PIC_BITS,0.U),io.lsu_addr_d(PIC_BITS-1,0))
|
||||
io.picm_wraddr := aslong(PIC_BASE_ADDR).U | Cat(Fill(32-PIC_BITS,0.U),Mux(io.dma_pic_wen.asBool,io.dma_mem_addr(PIC_BITS-1,0),io.lsu_addr_r(PIC_BITS-1,0)))
|
||||
io.picm_mask_data_m := picm_rd_data_m(31,0)
|
||||
|
|
|
|||
|
|
@ -10,8 +10,8 @@ class el2_lsu_ecc extends Module with el2_lib with RequireAsyncReset {
|
|||
val io = IO(new Bundle{
|
||||
|
||||
val lsu_c2_r_clk = Input(Clock())
|
||||
val lsu_pkt_m = Input(new el2_lsu_pkt_t)
|
||||
val lsu_pkt_r = Input(new el2_lsu_pkt_t)
|
||||
val lsu_pkt_m = Flipped(Valid(new el2_lsu_pkt_t))
|
||||
val lsu_pkt_r = Flipped(Valid(new el2_lsu_pkt_t))
|
||||
val stbuf_data_any = Input(UInt(DCCM_DATA_WIDTH.W))
|
||||
val dec_tlu_core_ecc_disable = Input(Bool())
|
||||
val lsu_dccm_rden_r = Input(Bool())
|
||||
|
|
@ -19,7 +19,7 @@ class el2_lsu_ecc extends Module with el2_lib with RequireAsyncReset {
|
|||
|
||||
val lsu_addr_r = Input(UInt(DCCM_BITS.W))
|
||||
val end_addr_r = Input(UInt(DCCM_BITS.W))
|
||||
val lsu_addr_m = Input(UInt(DCCM_BITS.W))//6fba5e03053441e71b7d54f50a77e3b496d56173
|
||||
val lsu_addr_m = Input(UInt(DCCM_BITS.W))
|
||||
val end_addr_m = Input(UInt(DCCM_BITS.W))
|
||||
|
||||
val dccm_rdata_hi_r = Input(UInt(DCCM_DATA_WIDTH.W))
|
||||
|
|
@ -102,9 +102,9 @@ class el2_lsu_ecc extends Module with el2_lib with RequireAsyncReset {
|
|||
|
||||
when (LOAD_TO_USE_PLUS1.B) {
|
||||
ldst_dual_r := io.lsu_addr_r(2) =/= io.end_addr_r(2)
|
||||
is_ldst_r := io.lsu_pkt_r.valid & (io.lsu_pkt_r.load | io.lsu_pkt_r.store) & io.addr_in_dccm_r & io.lsu_dccm_rden_r
|
||||
is_ldst_r := io.lsu_pkt_r.valid & (io.lsu_pkt_r.bits.load | io.lsu_pkt_r.bits.store) & io.addr_in_dccm_r & io.lsu_dccm_rden_r
|
||||
is_ldst_lo_r := is_ldst_r & !io.dec_tlu_core_ecc_disable
|
||||
is_ldst_hi_r := is_ldst_r & (ldst_dual_r | io.lsu_pkt_r.dma) & !io.dec_tlu_core_ecc_disable
|
||||
is_ldst_hi_r := is_ldst_r & (ldst_dual_r | io.lsu_pkt_r.bits.dma) & !io.dec_tlu_core_ecc_disable
|
||||
is_ldst_hi_any := is_ldst_hi_r
|
||||
dccm_rdata_hi_any := io.dccm_rdata_hi_r
|
||||
dccm_data_ecc_hi_any := io.dccm_data_ecc_hi_r
|
||||
|
|
@ -122,9 +122,9 @@ class el2_lsu_ecc extends Module with el2_lib with RequireAsyncReset {
|
|||
}
|
||||
.otherwise {
|
||||
ldst_dual_m := io.lsu_addr_m(2) =/= io.end_addr_m(2)
|
||||
is_ldst_m := io.lsu_pkt_m.valid & (io.lsu_pkt_m.load | io.lsu_pkt_m.store) & io.addr_in_dccm_m & io.lsu_dccm_rden_m
|
||||
is_ldst_m := io.lsu_pkt_m.valid & (io.lsu_pkt_m.bits.load | io.lsu_pkt_m.bits.store) & io.addr_in_dccm_m & io.lsu_dccm_rden_m
|
||||
is_ldst_lo_m := is_ldst_m & !io.dec_tlu_core_ecc_disable
|
||||
is_ldst_hi_m := is_ldst_m & (ldst_dual_m | io.lsu_pkt_m.dma) & !io.dec_tlu_core_ecc_disable
|
||||
is_ldst_hi_m := is_ldst_m & (ldst_dual_m | io.lsu_pkt_m.bits.dma) & !io.dec_tlu_core_ecc_disable
|
||||
is_ldst_hi_any := is_ldst_hi_m
|
||||
dccm_rdata_hi_any := io.dccm_rdata_hi_m
|
||||
dccm_data_ecc_hi_any := io.dccm_data_ecc_hi_m
|
||||
|
|
|
|||
|
|
@ -32,7 +32,7 @@ class el2_lsu_lsc_ctl extends Module with RequireAsyncReset with el2_lib
|
|||
val exu_lsu_rs1_d = Input(UInt(32.W)) // address
|
||||
val exu_lsu_rs2_d = Input(UInt(32.W)) // store data
|
||||
|
||||
val lsu_p = Input(new el2_lsu_pkt_t()) // lsu control packet //coming from decode
|
||||
val lsu_p = Flipped(Valid(new el2_lsu_pkt_t())) // lsu control packet //coming from decode
|
||||
val dec_lsu_valid_raw_d = Input(UInt(1.W)) // Raw valid for address computation
|
||||
val dec_lsu_offset_d = Input(UInt(12.W))
|
||||
|
||||
|
|
@ -61,7 +61,7 @@ class el2_lsu_lsc_ctl extends Module with RequireAsyncReset with el2_lib
|
|||
val is_sideeffects_m = Output(UInt(1.W))
|
||||
val lsu_commit_r = Output(UInt(1.W))
|
||||
val lsu_single_ecc_error_incr = Output(UInt(1.W))
|
||||
val lsu_error_pkt_r = Output(new el2_lsu_error_pkt_t())
|
||||
val lsu_error_pkt_r = Valid(new el2_lsu_error_pkt_t())
|
||||
|
||||
val lsu_fir_addr = Output(UInt(31.W)) //(31:1) in sv // fast interrupt address TBD
|
||||
val lsu_fir_error = Output(UInt(2.W)) // Error during fast interrupt lookup TBD
|
||||
|
|
@ -85,31 +85,31 @@ class el2_lsu_lsc_ctl extends Module with RequireAsyncReset with el2_lib
|
|||
val dma_mem_wdata = Input(UInt(64.W))
|
||||
|
||||
// Store buffer related signals
|
||||
val lsu_pkt_d = Output(new el2_lsu_pkt_t())
|
||||
val lsu_pkt_m = Output(new el2_lsu_pkt_t())
|
||||
val lsu_pkt_r = Output(new el2_lsu_pkt_t())
|
||||
val lsu_pkt_d = Valid(new el2_lsu_pkt_t())
|
||||
val lsu_pkt_m = Valid(new el2_lsu_pkt_t())
|
||||
val lsu_pkt_r = Valid(new el2_lsu_pkt_t())
|
||||
|
||||
val scan_mode = Input(UInt(1.W))
|
||||
})
|
||||
|
||||
|
||||
val dma_pkt_d = Wire(new el2_lsu_pkt_t())
|
||||
val lsu_pkt_m_in = Wire(new el2_lsu_pkt_t())
|
||||
val lsu_pkt_r_in = Wire(new el2_lsu_pkt_t())
|
||||
val lsu_error_pkt_m = Wire(new el2_lsu_error_pkt_t())
|
||||
val dma_pkt_d = Wire(Valid(new el2_lsu_pkt_t()))
|
||||
val lsu_pkt_m_in = Wire(Valid(new el2_lsu_pkt_t()))
|
||||
val lsu_pkt_r_in = Wire(Valid(new el2_lsu_pkt_t()))
|
||||
val lsu_error_pkt_m = Wire(Valid(new el2_lsu_error_pkt_t()))
|
||||
|
||||
val lsu_rs1_d = Mux(io.dec_lsu_valid_raw_d.asBool,io.exu_lsu_rs1_d,io.dma_mem_addr)
|
||||
val lsu_offset_d = io.dec_lsu_offset_d(11,0) & Fill(12,io.dec_lsu_valid_raw_d)
|
||||
val rs1_d_raw = lsu_rs1_d
|
||||
val offset_d = lsu_offset_d
|
||||
val rs1_d = Mux(io.lsu_pkt_d.load_ldst_bypass_d.asBool,io.lsu_result_m,rs1_d_raw)
|
||||
val rs1_d = Mux(io.lsu_pkt_d.bits.load_ldst_bypass_d.asBool,io.lsu_result_m,rs1_d_raw)
|
||||
|
||||
// generate the ls address
|
||||
val full_addr_d = rvlsadder(rs1_d,offset_d)
|
||||
|
||||
val addr_offset_d = ((Fill(3,io.lsu_pkt_d.half)) & 1.U(3.W)) |
|
||||
((Fill(3,io.lsu_pkt_d.word)) & 3.U(3.W)) |
|
||||
((Fill(3,io.lsu_pkt_d.dword)) & 7.U(3.W))
|
||||
val addr_offset_d = ((Fill(3,io.lsu_pkt_d.bits.half)) & 1.U(3.W)) |
|
||||
((Fill(3,io.lsu_pkt_d.bits.word)) & 3.U(3.W)) |
|
||||
((Fill(3,io.lsu_pkt_d.bits.dword)) & 7.U(3.W))
|
||||
|
||||
val end_addr_offset_d = Cat(offset_d(11),offset_d(11,0)) + Cat(Fill(9,0.U),addr_offset_d(2,0))
|
||||
val full_end_addr_d = rs1_d(31,0) + Cat(Fill(19,end_addr_offset_d(12)),end_addr_offset_d(12,0))
|
||||
|
|
@ -154,17 +154,17 @@ class el2_lsu_lsc_ctl extends Module with RequireAsyncReset with el2_lib
|
|||
fir_nondccm_access_error_m := withClock(io.lsu_c1_m_clk){RegNext(fir_nondccm_access_error_d,0.U)}
|
||||
|
||||
io.lsu_exc_m := access_fault_m | misaligned_fault_m
|
||||
io.lsu_single_ecc_error_incr := (io.lsu_single_ecc_error_r & !io.lsu_double_ecc_error_r) & (io.lsu_commit_r | io.lsu_pkt_r.dma) & io.lsu_pkt_r.valid
|
||||
io.lsu_single_ecc_error_incr := (io.lsu_single_ecc_error_r & !io.lsu_double_ecc_error_r) & (io.lsu_commit_r | io.lsu_pkt_r.bits.dma) & io.lsu_pkt_r.valid
|
||||
|
||||
if (LOAD_TO_USE_PLUS1 == 1){
|
||||
// Generate exception packet
|
||||
io.lsu_error_pkt_r.exc_valid := (access_fault_r | misaligned_fault_r | io.lsu_double_ecc_error_r) & io.lsu_pkt_r.valid & !io.lsu_pkt_r.dma & !io.lsu_pkt_r.fast_int //TBD(lsu_pkt_r.fast_int)
|
||||
io.lsu_error_pkt_r.single_ecc_error := io.lsu_single_ecc_error_r & !io.lsu_error_pkt_r.exc_valid & !io.lsu_pkt_r.dma
|
||||
io.lsu_error_pkt_r.inst_type := io.lsu_pkt_r.store
|
||||
io.lsu_error_pkt_r.exc_type := ~misaligned_fault_r
|
||||
io.lsu_error_pkt_r.mscause := Mux((io.lsu_double_ecc_error_r & !misaligned_fault_r & !access_fault_r).asBool,1.U(4.W), exc_mscause_r(3,0))
|
||||
io.lsu_error_pkt_r.addr := io.lsu_addr_r(31,0)//lsu_addr_d->lsu_full_addr
|
||||
io.lsu_fir_error := Mux(fir_nondccm_access_error_r.asBool,3.U(2.W), Mux(fir_dccm_access_error_r.asBool,2.U(2.W), Mux((io.lsu_pkt_r.fast_int & io.lsu_double_ecc_error_r).asBool,1.U(2.W),0.U(2.W))))
|
||||
io.lsu_error_pkt_r.valid := (access_fault_r | misaligned_fault_r | io.lsu_double_ecc_error_r) & io.lsu_pkt_r.valid & !io.lsu_pkt_r.bits.dma & !io.lsu_pkt_r.bits.fast_int //TBD(lsu_pkt_r.fast_int)
|
||||
io.lsu_error_pkt_r.bits.single_ecc_error := io.lsu_single_ecc_error_r & !io.lsu_error_pkt_r.valid & !io.lsu_pkt_r.bits.dma
|
||||
io.lsu_error_pkt_r.bits.inst_type := io.lsu_pkt_r.bits.store
|
||||
io.lsu_error_pkt_r.bits.exc_type := ~misaligned_fault_r
|
||||
io.lsu_error_pkt_r.bits.mscause := Mux((io.lsu_double_ecc_error_r & !misaligned_fault_r & !access_fault_r).asBool,1.U(4.W), exc_mscause_r(3,0))
|
||||
io.lsu_error_pkt_r.bits.addr := io.lsu_addr_r(31,0)//lsu_addr_d->lsu_full_addr
|
||||
io.lsu_fir_error := Mux(fir_nondccm_access_error_r.asBool,3.U(2.W), Mux(fir_dccm_access_error_r.asBool,2.U(2.W), Mux((io.lsu_pkt_r.bits.fast_int & io.lsu_double_ecc_error_r).asBool,1.U(2.W),0.U(2.W))))
|
||||
|
||||
access_fault_r := withClock(io.lsu_c1_r_clk){RegNext(access_fault_m,0.U)}
|
||||
exc_mscause_r := withClock(io.lsu_c1_r_clk){RegNext(exc_mscause_m,0.U)}
|
||||
|
|
@ -176,29 +176,29 @@ class el2_lsu_lsc_ctl extends Module with RequireAsyncReset with el2_lib
|
|||
else //L2U_Plus1_0
|
||||
{
|
||||
// Generate exception packet
|
||||
lsu_error_pkt_m.exc_valid := (access_fault_m | misaligned_fault_m | io.lsu_double_ecc_error_m) & io.lsu_pkt_m.valid & !io.lsu_pkt_m.dma & !io.lsu_pkt_m.fast_int & !io.flush_m_up //TBD(lsu_pkt_r.fast_int)
|
||||
lsu_error_pkt_m.single_ecc_error := io.lsu_single_ecc_error_m & !lsu_error_pkt_m.exc_valid & !io.lsu_pkt_m.dma
|
||||
lsu_error_pkt_m.inst_type := io.lsu_pkt_m.store
|
||||
lsu_error_pkt_m.exc_type := ~misaligned_fault_m
|
||||
lsu_error_pkt_m.mscause := Mux(((io.lsu_double_ecc_error_m & !misaligned_fault_m & !access_fault_m)===1.U),1.U(4.W), exc_mscause_m(3,0))
|
||||
lsu_error_pkt_m.addr := io.lsu_addr_m(31,0)//lsu_addr_d->lsu_full_addr
|
||||
lsu_fir_error_m := Mux(fir_nondccm_access_error_m.asBool,3.U(2.W), Mux(fir_dccm_access_error_m.asBool,2.U(2.W), Mux((io.lsu_pkt_m.fast_int & io.lsu_double_ecc_error_m).asBool,1.U(2.W),0.U(2.W))))
|
||||
lsu_error_pkt_m.valid := (access_fault_m | misaligned_fault_m | io.lsu_double_ecc_error_m) & io.lsu_pkt_m.valid & !io.lsu_pkt_m.bits.dma & !io.lsu_pkt_m.bits.fast_int & !io.flush_m_up //TBD(lsu_pkt_r.fast_int)
|
||||
lsu_error_pkt_m.bits.single_ecc_error := io.lsu_single_ecc_error_m & !lsu_error_pkt_m.valid & !io.lsu_pkt_m.bits.dma
|
||||
lsu_error_pkt_m.bits.inst_type := io.lsu_pkt_m.bits.store
|
||||
lsu_error_pkt_m.bits.exc_type := ~misaligned_fault_m
|
||||
lsu_error_pkt_m.bits.mscause := Mux(((io.lsu_double_ecc_error_m & !misaligned_fault_m & !access_fault_m)===1.U),1.U(4.W), exc_mscause_m(3,0))
|
||||
lsu_error_pkt_m.bits.addr := io.lsu_addr_m(31,0)//lsu_addr_d->lsu_full_addr
|
||||
lsu_fir_error_m := Mux(fir_nondccm_access_error_m.asBool,3.U(2.W), Mux(fir_dccm_access_error_m.asBool,2.U(2.W), Mux((io.lsu_pkt_m.bits.fast_int & io.lsu_double_ecc_error_m).asBool,1.U(2.W),0.U(2.W))))
|
||||
io.lsu_error_pkt_r := withClock(io.lsu_c2_r_clk){RegNext(lsu_error_pkt_m,0.U.asTypeOf(lsu_error_pkt_m.cloneType))}
|
||||
io.lsu_fir_error := withClock(io.lsu_c2_r_clk){RegNext(lsu_fir_error_m,0.U)}
|
||||
}
|
||||
dma_pkt_d.unsign := 0.U
|
||||
dma_pkt_d.fast_int := 0.U
|
||||
dma_pkt_d.bits.unsign := 0.U
|
||||
dma_pkt_d.bits.fast_int := 0.U
|
||||
dma_pkt_d.valid := io.dma_dccm_req
|
||||
dma_pkt_d.dma := 1.U
|
||||
dma_pkt_d.store := io.dma_mem_write
|
||||
dma_pkt_d.load := ~io.dma_mem_write
|
||||
dma_pkt_d.by := (io.dma_mem_sz(2,0) === 0.U(3.W))
|
||||
dma_pkt_d.half := (io.dma_mem_sz(2,0) === 1.U(3.W))
|
||||
dma_pkt_d.word := (io.dma_mem_sz(2,0) === 2.U(3.W))
|
||||
dma_pkt_d.dword := (io.dma_mem_sz(2,0) === 3.U(3.W))
|
||||
dma_pkt_d.store_data_bypass_d := 0.U
|
||||
dma_pkt_d.load_ldst_bypass_d := 0.U
|
||||
dma_pkt_d.store_data_bypass_m := 0.U
|
||||
dma_pkt_d.bits.dma := 1.U
|
||||
dma_pkt_d.bits.store := io.dma_mem_write
|
||||
dma_pkt_d.bits.load := ~io.dma_mem_write
|
||||
dma_pkt_d.bits.by := (io.dma_mem_sz(2,0) === 0.U(3.W))
|
||||
dma_pkt_d.bits.half := (io.dma_mem_sz(2,0) === 1.U(3.W))
|
||||
dma_pkt_d.bits.word := (io.dma_mem_sz(2,0) === 2.U(3.W))
|
||||
dma_pkt_d.bits.dword := (io.dma_mem_sz(2,0) === 3.U(3.W))
|
||||
dma_pkt_d.bits.store_data_bypass_d := 0.U
|
||||
dma_pkt_d.bits.load_ldst_bypass_d := 0.U
|
||||
dma_pkt_d.bits.store_data_bypass_m := 0.U
|
||||
|
||||
val lsu_ld_datafn_r = WireInit(0.U(32.W))
|
||||
val lsu_ld_datafn_corr_r = WireInit(0.U(32.W))
|
||||
|
|
@ -208,9 +208,9 @@ class el2_lsu_lsc_ctl extends Module with RequireAsyncReset with el2_lib
|
|||
lsu_pkt_m_in := io.lsu_pkt_d
|
||||
lsu_pkt_r_in := io.lsu_pkt_m
|
||||
|
||||
io.lsu_pkt_d.valid := (io.lsu_p.valid & !(io.flush_m_up & !io.lsu_p.fast_int)) | io.dma_dccm_req
|
||||
lsu_pkt_m_in.valid := io.lsu_pkt_d.valid & !(io.flush_m_up & !io.lsu_pkt_d.dma)
|
||||
lsu_pkt_r_in.valid := io.lsu_pkt_m.valid & !(io.flush_m_up & !io.lsu_pkt_m.dma)
|
||||
io.lsu_pkt_d.valid := (io.lsu_p.valid & !(io.flush_m_up & !io.lsu_p.bits.fast_int)) | io.dma_dccm_req
|
||||
lsu_pkt_m_in.valid := io.lsu_pkt_d.valid & !(io.flush_m_up & !io.lsu_pkt_d.bits.dma)
|
||||
lsu_pkt_r_in.valid := io.lsu_pkt_m.valid & !(io.flush_m_up & !io.lsu_pkt_m.bits.dma)
|
||||
|
||||
io.lsu_pkt_m := withClock(io.lsu_c1_m_clk){RegNext(lsu_pkt_m_in,0.U.asTypeOf(lsu_pkt_m_in.cloneType))}
|
||||
io.lsu_pkt_r := withClock(io.lsu_c1_r_clk){RegNext(lsu_pkt_r_in,0.U.asTypeOf(lsu_pkt_r_in.cloneType))}
|
||||
|
|
@ -219,7 +219,7 @@ class el2_lsu_lsc_ctl extends Module with RequireAsyncReset with el2_lib
|
|||
|
||||
val dma_mem_wdata_shifted = io.dma_mem_wdata(63,0) >> Cat(io.dma_mem_addr(2,0), 0.U(3.W)) // Shift the dma data to lower bits to make it consistent to lsu stores
|
||||
val store_data_d = Mux(io.dma_dccm_req.asBool,dma_mem_wdata_shifted(31,0),io.exu_lsu_rs2_d(31,0)) // Write to PIC still happens in r stage
|
||||
val store_data_m_in = Mux(io.lsu_pkt_d.store_data_bypass_d.asBool,io.lsu_result_m(31,0),store_data_d(31,0))
|
||||
val store_data_m_in = Mux(io.lsu_pkt_d.bits.store_data_bypass_d.asBool,io.lsu_result_m(31,0),store_data_d(31,0))
|
||||
|
||||
val store_data_pre_m = withClock(io.lsu_store_c1_m_clk){RegNext(store_data_m_in,0.U)}
|
||||
io.lsu_addr_m := withClock(io.lsu_c1_m_clk){RegNext(io.lsu_addr_d,0.U)}
|
||||
|
|
@ -238,40 +238,40 @@ class el2_lsu_lsc_ctl extends Module with RequireAsyncReset with el2_lib
|
|||
// absence load/store all 0's
|
||||
io.lsu_addr_d := full_addr_d
|
||||
// Interrupt as a flush source allows the WB to occur
|
||||
io.lsu_commit_r := io.lsu_pkt_r.valid & (io.lsu_pkt_r.store | io.lsu_pkt_r.load) & !io.flush_r & !io.lsu_pkt_r.dma
|
||||
io.store_data_m := (io.picm_mask_data_m(31,0) | Fill(32,!io.addr_in_pic_m)) & Mux(io.lsu_pkt_m.store_data_bypass_m.asBool,io.lsu_result_m,store_data_pre_m)
|
||||
io.lsu_commit_r := io.lsu_pkt_r.valid & (io.lsu_pkt_r.bits.store | io.lsu_pkt_r.bits.load) & !io.flush_r & !io.lsu_pkt_r.bits.dma
|
||||
io.store_data_m := (io.picm_mask_data_m(31,0) | Fill(32,!io.addr_in_pic_m)) & Mux(io.lsu_pkt_m.bits.store_data_bypass_m.asBool,io.lsu_result_m,store_data_pre_m)
|
||||
|
||||
if (LOAD_TO_USE_PLUS1 == 1){
|
||||
//bus_read_data_r coming from bus interface, lsu_ld_data_r -> coming from dccm_ctl
|
||||
lsu_ld_datafn_r := Mux(addr_external_r.asBool, bus_read_data_r,io.lsu_ld_data_r)
|
||||
lsu_ld_datafn_corr_r := Mux(addr_external_r.asBool, bus_read_data_r,io.lsu_ld_data_corr_r)
|
||||
// this is really R stage but don't want to make all the changes to support M,R buses
|
||||
io.lsu_result_m := ((Fill(32,io.lsu_pkt_r.unsign & io.lsu_pkt_r.by)) & Cat(0.U(24.W),lsu_ld_datafn_r(7,0))) |
|
||||
((Fill(32,io.lsu_pkt_r.unsign & io.lsu_pkt_r.half)) & Cat(0.U(16.W),lsu_ld_datafn_r(15,0))) |
|
||||
((Fill(32,!io.lsu_pkt_r.unsign & io.lsu_pkt_r.by)) & Cat((Fill(24, lsu_ld_datafn_r(7))) ,lsu_ld_datafn_r(7,0))) |
|
||||
((Fill(32,!io.lsu_pkt_r.unsign & io.lsu_pkt_r.half)) & Cat((Fill(16,lsu_ld_datafn_r(15))) ,lsu_ld_datafn_r(15,0))) |
|
||||
((Fill(32,io.lsu_pkt_r.word)) & lsu_ld_datafn_r(31,0))
|
||||
io.lsu_result_m := ((Fill(32,io.lsu_pkt_r.bits.unsign & io.lsu_pkt_r.bits.by)) & Cat(0.U(24.W),lsu_ld_datafn_r(7,0))) |
|
||||
((Fill(32,io.lsu_pkt_r.bits.unsign & io.lsu_pkt_r.bits.half)) & Cat(0.U(16.W),lsu_ld_datafn_r(15,0))) |
|
||||
((Fill(32,!io.lsu_pkt_r.bits.unsign & io.lsu_pkt_r.bits.by)) & Cat((Fill(24, lsu_ld_datafn_r(7))) ,lsu_ld_datafn_r(7,0))) |
|
||||
((Fill(32,!io.lsu_pkt_r.bits.unsign & io.lsu_pkt_r.bits.half)) & Cat((Fill(16,lsu_ld_datafn_r(15))) ,lsu_ld_datafn_r(15,0))) |
|
||||
((Fill(32,io.lsu_pkt_r.bits.word)) & lsu_ld_datafn_r(31,0))
|
||||
// this signal is used for gpr update
|
||||
io.lsu_result_corr_r := ((Fill(32,io.lsu_pkt_r.unsign & io.lsu_pkt_r.by)) & Cat(0.U(24.W),lsu_ld_datafn_corr_r(7,0))) |
|
||||
((Fill(32,io.lsu_pkt_r.unsign & io.lsu_pkt_r.half)) & Cat(0.U(16.W),lsu_ld_datafn_corr_r(15,0))) |
|
||||
((Fill(32,!io.lsu_pkt_r.unsign & io.lsu_pkt_r.by)) & Cat((Fill(24, lsu_ld_datafn_corr_r(7))) ,lsu_ld_datafn_corr_r(7,0))) |
|
||||
((Fill(32,!io.lsu_pkt_r.unsign & io.lsu_pkt_r.half)) & Cat((Fill(16,lsu_ld_datafn_corr_r(15))) ,lsu_ld_datafn_corr_r(15,0))) |
|
||||
((Fill(32,io.lsu_pkt_r.word)) & lsu_ld_datafn_corr_r(31,0))
|
||||
io.lsu_result_corr_r := ((Fill(32,io.lsu_pkt_r.bits.unsign & io.lsu_pkt_r.bits.by)) & Cat(0.U(24.W),lsu_ld_datafn_corr_r(7,0))) |
|
||||
((Fill(32,io.lsu_pkt_r.bits.unsign & io.lsu_pkt_r.bits.half)) & Cat(0.U(16.W),lsu_ld_datafn_corr_r(15,0))) |
|
||||
((Fill(32,!io.lsu_pkt_r.bits.unsign & io.lsu_pkt_r.bits.by)) & Cat((Fill(24, lsu_ld_datafn_corr_r(7))) ,lsu_ld_datafn_corr_r(7,0))) |
|
||||
((Fill(32,!io.lsu_pkt_r.bits.unsign & io.lsu_pkt_r.bits.half)) & Cat((Fill(16,lsu_ld_datafn_corr_r(15))) ,lsu_ld_datafn_corr_r(15,0))) |
|
||||
((Fill(32,io.lsu_pkt_r.bits.word)) & lsu_ld_datafn_corr_r(31,0))
|
||||
}
|
||||
|
||||
else {
|
||||
lsu_ld_datafn_m := Mux(io.addr_external_m.asBool, io.bus_read_data_m,io.lsu_ld_data_m)
|
||||
lsu_ld_datafn_corr_r := Mux(addr_external_r===1.U, bus_read_data_r,io.lsu_ld_data_corr_r)
|
||||
io.lsu_result_m := ((Fill(32,io.lsu_pkt_m.unsign & io.lsu_pkt_m.by)) & Cat(0.U(24.W),lsu_ld_datafn_m(7,0))) |
|
||||
((Fill(32,io.lsu_pkt_m.unsign & io.lsu_pkt_m.half)) & Cat(0.U(16.W),lsu_ld_datafn_m(15,0))) |
|
||||
((Fill(32,!io.lsu_pkt_m.unsign & io.lsu_pkt_m.by)) & Cat((Fill(24, lsu_ld_datafn_m(7))) ,lsu_ld_datafn_m(7,0))) |
|
||||
((Fill(32,!io.lsu_pkt_m.unsign & io.lsu_pkt_m.half)) & Cat((Fill(16,lsu_ld_datafn_m(15))) ,lsu_ld_datafn_m(15,0))) |
|
||||
((Fill(32,io.lsu_pkt_m.word)) & lsu_ld_datafn_m(31,0))
|
||||
io.lsu_result_corr_r := ((Fill(32,io.lsu_pkt_r.unsign & io.lsu_pkt_r.by)) & Cat(0.U(24.W),lsu_ld_datafn_corr_r(7,0))) |
|
||||
((Fill(32,io.lsu_pkt_r.unsign & io.lsu_pkt_r.half)) & Cat(0.U(16.W),lsu_ld_datafn_corr_r(15,0))) |
|
||||
((Fill(32,!io.lsu_pkt_r.unsign & io.lsu_pkt_r.by)) & Cat((Fill(24, lsu_ld_datafn_corr_r(7))) ,lsu_ld_datafn_corr_r(7,0))) |
|
||||
((Fill(32,!io.lsu_pkt_r.unsign & io.lsu_pkt_r.half)) & Cat((Fill(16,lsu_ld_datafn_corr_r(15))) ,lsu_ld_datafn_corr_r(15,0))) |
|
||||
((Fill(32,io.lsu_pkt_r.word)) & lsu_ld_datafn_corr_r(31,0))
|
||||
io.lsu_result_m := ((Fill(32,io.lsu_pkt_m.bits.unsign & io.lsu_pkt_m.bits.by)) & Cat(0.U(24.W),lsu_ld_datafn_m(7,0))) |
|
||||
((Fill(32,io.lsu_pkt_m.bits.unsign & io.lsu_pkt_m.bits.half)) & Cat(0.U(16.W),lsu_ld_datafn_m(15,0))) |
|
||||
((Fill(32,!io.lsu_pkt_m.bits.unsign & io.lsu_pkt_m.bits.by)) & Cat((Fill(24, lsu_ld_datafn_m(7))) ,lsu_ld_datafn_m(7,0))) |
|
||||
((Fill(32,!io.lsu_pkt_m.bits.unsign & io.lsu_pkt_m.bits.half)) & Cat((Fill(16,lsu_ld_datafn_m(15))) ,lsu_ld_datafn_m(15,0))) |
|
||||
((Fill(32,io.lsu_pkt_m.bits.word)) & lsu_ld_datafn_m(31,0))
|
||||
io.lsu_result_corr_r := ((Fill(32,io.lsu_pkt_r.bits.unsign & io.lsu_pkt_r.bits.by)) & Cat(0.U(24.W),lsu_ld_datafn_corr_r(7,0))) |
|
||||
((Fill(32,io.lsu_pkt_r.bits.unsign & io.lsu_pkt_r.bits.half)) & Cat(0.U(16.W),lsu_ld_datafn_corr_r(15,0))) |
|
||||
((Fill(32,!io.lsu_pkt_r.bits.unsign & io.lsu_pkt_r.bits.by)) & Cat((Fill(24, lsu_ld_datafn_corr_r(7))) ,lsu_ld_datafn_corr_r(7,0))) |
|
||||
((Fill(32,!io.lsu_pkt_r.bits.unsign & io.lsu_pkt_r.bits.half)) & Cat((Fill(16,lsu_ld_datafn_corr_r(15))) ,lsu_ld_datafn_corr_r(15,0))) |
|
||||
((Fill(32,io.lsu_pkt_r.bits.word)) & lsu_ld_datafn_corr_r(31,0))
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -12,8 +12,8 @@ class el2_lsu_stbuf extends Module with el2_lib with RequireAsyncReset {
|
|||
val lsu_c1_r_clk = Input(Clock())
|
||||
val lsu_stbuf_c1_clk = Input(Clock())
|
||||
val lsu_free_c2_clk = Input(Clock())
|
||||
val lsu_pkt_m = Input(new el2_lsu_pkt_t)
|
||||
val lsu_pkt_r = Input(new el2_lsu_pkt_t)
|
||||
val lsu_pkt_m = Flipped(Valid(new el2_lsu_pkt_t))
|
||||
val lsu_pkt_r = Flipped(Valid(new el2_lsu_pkt_t))
|
||||
val store_stbuf_reqvld_r = Input(Bool())
|
||||
val lsu_commit_r = Input(Bool())
|
||||
val dec_lsu_valid_raw_d = Input(Bool())
|
||||
|
|
@ -46,7 +46,6 @@ class el2_lsu_stbuf extends Module with el2_lib with RequireAsyncReset {
|
|||
val stbuf_fwddata_lo_m = Output(UInt(DCCM_DATA_WIDTH.W))
|
||||
val stbuf_fwdbyteen_hi_m = Output(UInt(DCCM_BYTE_WIDTH.W))
|
||||
val stbuf_fwdbyteen_lo_m = Output(UInt(DCCM_BYTE_WIDTH.W))
|
||||
// val testout = Output(Vec(LSU_STBUF_DEPTH, UInt(8.W)))
|
||||
})
|
||||
|
||||
io.stbuf_reqvld_any := 0.U
|
||||
|
|
@ -110,17 +109,17 @@ class el2_lsu_stbuf extends Module with el2_lib with RequireAsyncReset {
|
|||
|
||||
//////////////////////////////////////Code Start here///////////////////////////////
|
||||
val ldst_byteen_r = Mux1H(Seq(
|
||||
io.lsu_pkt_r.by.asBool -> "b00000001".U,
|
||||
io.lsu_pkt_r.half.asBool ->"b00000011".U,
|
||||
io.lsu_pkt_r.word.asBool -> "b00001111".U,
|
||||
io.lsu_pkt_r.dword.asBool -> "b11111111".U
|
||||
io.lsu_pkt_r.bits.by.asBool -> "b00000001".U,
|
||||
io.lsu_pkt_r.bits.half.asBool ->"b00000011".U,
|
||||
io.lsu_pkt_r.bits.word.asBool -> "b00001111".U,
|
||||
io.lsu_pkt_r.bits.dword.asBool -> "b11111111".U
|
||||
))
|
||||
val ldst_dual_d = io.lsu_addr_d (2) =/= io.end_addr_d(2)
|
||||
val dual_stbuf_write_r = ldst_dual_r & io.store_stbuf_reqvld_r
|
||||
|
||||
store_byteen_ext_r := ldst_byteen_r << io.lsu_addr_r(1,0)
|
||||
val store_byteen_hi_r = store_byteen_ext_r (7,4) & Fill(4, io.lsu_pkt_r.store)
|
||||
val store_byteen_lo_r = store_byteen_ext_r (3,0) & Fill(4, io.lsu_pkt_r.store)
|
||||
val store_byteen_hi_r = store_byteen_ext_r (7,4) & Fill(4, io.lsu_pkt_r.bits.store)
|
||||
val store_byteen_lo_r = store_byteen_ext_r (3,0) & Fill(4, io.lsu_pkt_r.bits.store)
|
||||
|
||||
val RdPtrPlus1 = RdPtr + "b01".U
|
||||
val WrPtrPlus1 = WrPtr + "b01".U
|
||||
|
|
@ -158,19 +157,14 @@ class el2_lsu_stbuf extends Module with el2_lib with RequireAsyncReset {
|
|||
Mux(!stbuf_byteen(i)(3) | store_byteen_hi_r(3), io.store_datafn_hi_r(31, 24), stbuf_data(i)(31, 24))).asUInt)
|
||||
|
||||
stbuf_datain := (0 until LSU_STBUF_DEPTH).map(i=>Cat(datain4(i), datain3(i), datain2(i), datain1(i)))
|
||||
// io.testout := datain3
|
||||
|
||||
// for (i<- 0 until LSU_STBUF_DEPTH) {
|
||||
|
||||
|
||||
stbuf_vld := (0 until LSU_STBUF_DEPTH).map(i=> withClock(io.lsu_free_c2_clk){ RegNext(Mux(stbuf_wr_en(i).asBool(),1.U ,stbuf_vld(i)) & !stbuf_reset(i), 0.U)}).reverse.reduce(Cat(_,_))
|
||||
// stbuf_addr := (0 until LSU_STBUF_DEPTH).map(i=> RegEnable(stbuf_addrin(i), 0.U, stbuf_wr_en(i).asBool())).reverse.reduce(Cat(_,_))
|
||||
stbuf_dma_kill := (0 until LSU_STBUF_DEPTH).map(i=> withClock(io.lsu_free_c2_clk){RegNext(Mux(stbuf_dma_kill_en(i).asBool,1.U ,stbuf_dma_kill(i)) & !stbuf_reset(i), 0.U)}).reverse.reduce(Cat(_,_))
|
||||
stbuf_byteen := (0 until LSU_STBUF_DEPTH).map(i=> withClock(io.lsu_stbuf_c1_clk){ RegNext(Mux(stbuf_wr_en(i).asBool(),stbuf_byteenin(i) , stbuf_byteen(i)) & Fill(stbuf_byteenin(i).getWidth , !stbuf_reset(i)), 0.U)})
|
||||
//stbuf_data := (0 until LSU_STBUF_DEPTH).map(i=> RegEnable(stbuf_datain(i), 0.U, stbuf_wr_en(i).asBool())).reverse.reduce(Cat(_,_))
|
||||
for (i<- 0 until LSU_STBUF_DEPTH) {
|
||||
// withClock(io.lsu_free_c2_clk){ stbuf_dma_kill(i) := RegEnable(1.U & !stbuf_reset(i), 0.U, stbuf_dma_kill_en(i).asBool)}
|
||||
|
||||
stbuf_addr(i) := rvdffe(stbuf_addrin(i),stbuf_wr_en(i).asBool(),clock,io.scan_mode)
|
||||
// withClock(io.lsu_stbuf_c1_clk){ stbuf_byteen(i) := RegNext( stbuf_byteenin(i) & Fill(stbuf_byteenin(i).getWidth, !stbuf_reset(i)), 0.U, stbuf_wr_en(i).asBool())}
|
||||
stbuf_data(i) := rvdffe(stbuf_datain(i),stbuf_wr_en(i).asBool(),clock,io.scan_mode)
|
||||
}
|
||||
withClock(io.lsu_c1_m_clk){ldst_dual_m := RegNext(ldst_dual_d,0.U)}
|
||||
|
|
@ -192,8 +186,8 @@ class el2_lsu_stbuf extends Module with el2_lib with RequireAsyncReset {
|
|||
withClock(io.lsu_stbuf_c1_clk){ RdPtr := RegEnable(NxtRdPtr, 0.U, RdPtrEn)}
|
||||
|
||||
val stbuf_numvld_any = VecInit.tabulate(LSU_STBUF_DEPTH)(i=>Cat(0.U(3.W), stbuf_vld(i))).reduce (_+_)
|
||||
val isdccmst_m = io.lsu_pkt_m.valid & io.lsu_pkt_m.store & io.addr_in_dccm_m & !io.lsu_pkt_m.dma
|
||||
val isdccmst_r = io.lsu_pkt_r.valid & io.lsu_pkt_r.store & io.addr_in_dccm_r & !io.lsu_pkt_r.dma
|
||||
val isdccmst_m = io.lsu_pkt_m.valid & io.lsu_pkt_m.bits.store & io.addr_in_dccm_m & !io.lsu_pkt_m.bits.dma
|
||||
val isdccmst_r = io.lsu_pkt_r.valid & io.lsu_pkt_r.bits.store & io.addr_in_dccm_r & !io.lsu_pkt_r.bits.dma
|
||||
|
||||
stbuf_specvld_m := Cat(0.U(1.W),isdccmst_m) << (isdccmst_m & ldst_dual_m)
|
||||
stbuf_specvld_r := Cat(0.U(1.W),isdccmst_r) << (isdccmst_r & ldst_dual_r)
|
||||
|
|
@ -211,7 +205,7 @@ class el2_lsu_stbuf extends Module with el2_lib with RequireAsyncReset {
|
|||
|
||||
val stbuf_match_hi = (0 until LSU_STBUF_DEPTH).map(i=> ((stbuf_addr(i)(LSU_SB_BITS-1,log2Ceil(DCCM_BYTE_WIDTH)) === cmpaddr_hi_m(13,0)) & stbuf_vld(i) & !stbuf_dma_kill(i) & io.addr_in_dccm_m).asUInt).reverse.reduce(Cat(_,_))
|
||||
val stbuf_match_lo = (0 until LSU_STBUF_DEPTH).map(i=> ((stbuf_addr(i)(LSU_SB_BITS-1,log2Ceil(DCCM_BYTE_WIDTH)) === cmpaddr_lo_m(13,0)) & stbuf_vld(i) & !stbuf_dma_kill(i) & io.addr_in_dccm_m).asUInt).reverse.reduce(Cat(_,_))
|
||||
stbuf_dma_kill_en := (0 until LSU_STBUF_DEPTH).map(i=> ((stbuf_match_hi(i) | stbuf_match_lo(i)) & io.lsu_pkt_m.valid & io.lsu_pkt_m.dma & io.lsu_pkt_m.store).asUInt).reverse.reduce(Cat(_,_))
|
||||
stbuf_dma_kill_en := (0 until LSU_STBUF_DEPTH).map(i=> ((stbuf_match_hi(i) | stbuf_match_lo(i)) & io.lsu_pkt_m.valid & io.lsu_pkt_m.bits.dma & io.lsu_pkt_m.bits.store).asUInt).reverse.reduce(Cat(_,_))
|
||||
|
||||
|
||||
val stbuf_fwdbyteenvec_hi = (0 until LSU_STBUF_DEPTH).map(i=>(0 until DCCM_BYTE_WIDTH).map(j=> stbuf_match_hi(i) & stbuf_byteen(i)(j) & stbuf_vld(i).asUInt()))
|
||||
|
|
@ -227,10 +221,10 @@ class el2_lsu_stbuf extends Module with el2_lib with RequireAsyncReset {
|
|||
val ldst_byteen_hi_r = ldst_byteen_ext_r(7,4)
|
||||
val ldst_byteen_lo_r = ldst_byteen_ext_r(3,0)
|
||||
|
||||
val ld_addr_rhit_lo_lo = (io.lsu_addr_m(31,2) === io.lsu_addr_r(31,2)) & io.lsu_pkt_r.valid & io.lsu_pkt_r.store & !io.lsu_pkt_r.dma
|
||||
val ld_addr_rhit_lo_hi = (io.end_addr_m(31,2) === io.lsu_addr_r(31,2)) & io.lsu_pkt_r.valid & io.lsu_pkt_r.store & !io.lsu_pkt_r.dma
|
||||
val ld_addr_rhit_hi_lo = (io.lsu_addr_m(31,2) === io.end_addr_r(31,2)) & io.lsu_pkt_r.valid & io.lsu_pkt_r.store & !io.lsu_pkt_r.dma & dual_stbuf_write_r
|
||||
val ld_addr_rhit_hi_hi = (io.end_addr_m(31,2) === io.end_addr_r(31,2)) & io.lsu_pkt_r.valid & io.lsu_pkt_r.store & !io.lsu_pkt_r.dma & dual_stbuf_write_r
|
||||
val ld_addr_rhit_lo_lo = (io.lsu_addr_m(31,2) === io.lsu_addr_r(31,2)) & io.lsu_pkt_r.valid & io.lsu_pkt_r.bits.store & !io.lsu_pkt_r.bits.dma
|
||||
val ld_addr_rhit_lo_hi = (io.end_addr_m(31,2) === io.lsu_addr_r(31,2)) & io.lsu_pkt_r.valid & io.lsu_pkt_r.bits.store & !io.lsu_pkt_r.bits.dma
|
||||
val ld_addr_rhit_hi_lo = (io.lsu_addr_m(31,2) === io.end_addr_r(31,2)) & io.lsu_pkt_r.valid & io.lsu_pkt_r.bits.store & !io.lsu_pkt_r.bits.dma & dual_stbuf_write_r
|
||||
val ld_addr_rhit_hi_hi = (io.end_addr_m(31,2) === io.end_addr_r(31,2)) & io.lsu_pkt_r.valid & io.lsu_pkt_r.bits.store & !io.lsu_pkt_r.bits.dma & dual_stbuf_write_r
|
||||
|
||||
ld_byte_rhit_lo_lo := (0 until DCCM_BYTE_WIDTH).map(i=> (ld_addr_rhit_lo_lo & ldst_byteen_lo_r(i)).asUInt).reverse.reduce(Cat(_,_))
|
||||
ld_byte_rhit_lo_hi := (0 until DCCM_BYTE_WIDTH).map(i=> (ld_addr_rhit_lo_hi & ldst_byteen_lo_r(i)).asUInt).reverse.reduce(Cat(_,_))
|
||||
|
|
|
|||
|
|
@ -6,17 +6,17 @@ import include._
|
|||
class el2_lsu_trigger extends Module with RequireAsyncReset with el2_lib {
|
||||
val io = IO(new Bundle{
|
||||
val trigger_pkt_any = Input(Vec (4,(new el2_trigger_pkt_t)))
|
||||
val lsu_pkt_m = Input(new el2_lsu_pkt_t)
|
||||
val lsu_pkt_m = Flipped(Valid(new el2_lsu_pkt_t))
|
||||
val lsu_addr_m = Input(UInt(32.W))
|
||||
val store_data_m = Input(UInt(32.W))
|
||||
val lsu_trigger_match_m = Output(UInt(4.W))
|
||||
|
||||
})
|
||||
|
||||
val store_data_trigger_m= Cat((Fill(16,io.lsu_pkt_m.word) & io.store_data_m(31,16)),(Fill(8,(io.lsu_pkt_m.half | io.lsu_pkt_m.word)) & io.store_data_m(15,8)), io.store_data_m(7,0))
|
||||
val store_data_trigger_m= Cat((Fill(16,io.lsu_pkt_m.bits.word) & io.store_data_m(31,16)),(Fill(8,(io.lsu_pkt_m.bits.half | io.lsu_pkt_m.bits.word)) & io.store_data_m(15,8)), io.store_data_m(7,0))
|
||||
val lsu_match_data = (0 until 4).map(i=>Mux1H(Seq(!io.trigger_pkt_any(i).select.asBool->io.lsu_addr_m, (io.trigger_pkt_any(i).select & io.trigger_pkt_any(i).store).asBool->store_data_trigger_m)))
|
||||
io.lsu_trigger_match_m := (0 until 4).map(i =>io.lsu_pkt_m.valid & !io.lsu_pkt_m.dma & ((io.trigger_pkt_any(i).store & io.lsu_pkt_m.store)|
|
||||
(io.trigger_pkt_any(i).load & io.lsu_pkt_m.load & !io.trigger_pkt_any(i).select) )&
|
||||
io.lsu_trigger_match_m := (0 until 4).map(i =>io.lsu_pkt_m.valid & !io.lsu_pkt_m.bits.dma & ((io.trigger_pkt_any(i).store & io.lsu_pkt_m.bits.store)|
|
||||
(io.trigger_pkt_any(i).load & io.lsu_pkt_m.bits.load & !io.trigger_pkt_any(i).select) )&
|
||||
rvmaskandmatch(io.trigger_pkt_any(i).tdata2, lsu_match_data(i), io.trigger_pkt_any(i).match_.asBool())).reverse.reduce(Cat(_,_))
|
||||
|
||||
}
|
||||
|
|
|
|||
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Reference in New Issue