bla
This commit is contained in:
waleed-lm
parent
8f8ec9569e
commit
39de042d82
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@ -2026,15 +2026,16 @@ circuit el2_dec_dec_ctl :
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node _T_1969 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33]
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node _T_1970 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52]
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node _T_1971 = eq(_T_1970, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
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node _T_1972 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:33]
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node _T_1973 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33]
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node _T_1974 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52]
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node _T_1975 = eq(_T_1974, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
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node _T_1976 = and(_T_1968, _T_1969) @[el2_dec_dec_ctl.scala 168:42]
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node _T_1977 = and(_T_1976, _T_1971) @[el2_dec_dec_ctl.scala 168:42]
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node _T_1978 = and(_T_1977, _T_1972) @[el2_dec_dec_ctl.scala 168:42]
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node _T_1979 = and(_T_1978, _T_1973) @[el2_dec_dec_ctl.scala 168:42]
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node _T_1980 = and(_T_1979, _T_1975) @[el2_dec_dec_ctl.scala 168:42]
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node _T_1981 = or(_T_1966, _T_1980) @[el2_dec_dec_ctl.scala 167:103]
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io.out.legal <= _T_1981 @[el2_dec_dec_ctl.scala 153:16]
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node _T_1972 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52]
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node _T_1973 = eq(_T_1972, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
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node _T_1974 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33]
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node _T_1975 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52]
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node _T_1976 = eq(_T_1975, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45]
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node _T_1977 = and(_T_1968, _T_1969) @[el2_dec_dec_ctl.scala 168:43]
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node _T_1978 = and(_T_1977, _T_1971) @[el2_dec_dec_ctl.scala 168:43]
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node _T_1979 = and(_T_1978, _T_1973) @[el2_dec_dec_ctl.scala 168:43]
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node _T_1980 = and(_T_1979, _T_1974) @[el2_dec_dec_ctl.scala 168:43]
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node _T_1981 = and(_T_1980, _T_1976) @[el2_dec_dec_ctl.scala 168:43]
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node _T_1982 = or(_T_1966, _T_1981) @[el2_dec_dec_ctl.scala 167:103]
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io.out.legal <= _T_1982 @[el2_dec_dec_ctl.scala 153:16]
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@ -646,11 +646,11 @@ module el2_dec_dec_ctl(
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wire _T_1964 = _T_1963 & io_ins[1]; // @[el2_dec_dec_ctl.scala 167:99]
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wire _T_1965 = _T_1964 & _T_1281; // @[el2_dec_dec_ctl.scala 167:99]
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wire _T_1966 = _T_1943 | _T_1965; // @[el2_dec_dec_ctl.scala 167:50]
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wire _T_1976 = _T_104 & io_ins[4]; // @[el2_dec_dec_ctl.scala 168:42]
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wire _T_1977 = _T_1976 & _T_100; // @[el2_dec_dec_ctl.scala 168:42]
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wire _T_1978 = _T_1977 & io_ins[2]; // @[el2_dec_dec_ctl.scala 168:42]
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wire _T_1979 = _T_1978 & io_ins[1]; // @[el2_dec_dec_ctl.scala 168:42]
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wire _T_1980 = _T_1979 & _T_1281; // @[el2_dec_dec_ctl.scala 168:42]
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wire _T_1977 = _T_104 & io_ins[4]; // @[el2_dec_dec_ctl.scala 168:43]
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wire _T_1978 = _T_1977 & _T_100; // @[el2_dec_dec_ctl.scala 168:43]
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wire _T_1979 = _T_1978 & _T_18; // @[el2_dec_dec_ctl.scala 168:43]
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wire _T_1980 = _T_1979 & io_ins[1]; // @[el2_dec_dec_ctl.scala 168:43]
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wire _T_1981 = _T_1980 & _T_1281; // @[el2_dec_dec_ctl.scala 168:43]
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assign io_out_alu = _T_7 | _T_11; // @[el2_dec_dec_ctl.scala 72:14]
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assign io_out_rs1 = _T_102 | _T_107; // @[el2_dec_dec_ctl.scala 73:14]
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assign io_out_rs2 = _T_115 | _T_122; // @[el2_dec_dec_ctl.scala 79:14]
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@ -700,5 +700,5 @@ module el2_dec_dec_ctl(
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assign io_out_fence = _T_9 & io_ins[3]; // @[el2_dec_dec_ctl.scala 137:16]
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assign io_out_fence_i = _T_997 & io_ins[3]; // @[el2_dec_dec_ctl.scala 138:18]
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assign io_out_pm_alu = _T_1021 | _T_11; // @[el2_dec_dec_ctl.scala 139:17]
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assign io_out_legal = _T_1966 | _T_1980; // @[el2_dec_dec_ctl.scala 153:16]
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assign io_out_legal = _T_1966 | _T_1981; // @[el2_dec_dec_ctl.scala 153:16]
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endmodule
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@ -169,6 +169,5 @@ class el2_dec_dec_ctl extends Module{
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}
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object dec extends App {
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chisel3.Driver.execute(args, () => new el2_dec_dec_ctl())
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println(Driver.emitVerilog(new el2_dec_dec_ctl()))
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println(chisel3.Driver.emitVerilog(new el2_dec_dec_ctl()))
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}
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@ -1,5 +1,158 @@
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package snapshot
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import chisel3._
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class el2_param {
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object pt{
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val BHT_ADDR_HI = "h9".U(4.W)
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val BHT_ADDR_LO = "h2".U(2.W)
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val BHT_ARRAY_DEPTH = "h100".U(11.W)
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val BHT_GHR_HASH_1 = "h0".U(1.W)
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val BHT_GHR_SIZE = "8h".U(4.W)
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val BHT_SIZE = "h200".U(12.W)
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val BTB_ADDR_HI = "h09".U(5.W)
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val BTB_ADDR_LO = "h2".U(2.W)
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val BTB_ARRAY_DEPTH = "h100".U(9.W)
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val BTB_BTAG_FOLD = "h0".U(1.W)
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val BTB_BTAG_SIZE = "h5".U(4.W)
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val BTB_FOLD2_INDEX_HASH = "h0".U(1.W)
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val BTB_INDEX1_HI = "h09".U(5.W)
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val BTB_INDEX1_LO = "h02".U(5.W)
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val BTB_INDEX2_HI = "h11".U(5.W)
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val BTB_INDEX2_LO = "h0A".U(5.W)
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val BTB_INDEX3_HI = "h19".U(5.W)
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val BTB_INDEX3_LO = "h12".U(5.W)
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val BTB_SIZE = "h200".U(10.W)
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val BUILD_AHB_LITE = "h0".U(1.W)
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val BUILD_AXI4 = "h1".U(1.W)
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val BUILD_AXI_NATIVE = "h1".U(1.W)
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val BUS_PRTY_DEFAULT = "h3".U(2.W)
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val DATA_ACCESS_ADDR0 = "h00000000".U(32.W)
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val DATA_ACCESS_ADDR1 = "hC0000000".U(32.W)
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val DATA_ACCESS_ADDR2 = "hA0000000".U(32.W)
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val DATA_ACCESS_ADDR3 = "h80000000".U(32.W)
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val DATA_ACCESS_ADDR4 = "h00000000".U(32.W)
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val DATA_ACCESS_ADDR5 = "h00000000".U(32.W)
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val DATA_ACCESS_ADDR6 = "h00000000".U(32.W)
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val DATA_ACCESS_ADDR7 = "h00000000".U(32.W)
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val DATA_ACCESS_ENABLE0 = "h1".U(1.W)
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val DATA_ACCESS_ENABLE1 = "h1".U(1.W)
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val DATA_ACCESS_ENABLE2 = "h1".U(1.W)
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val DATA_ACCESS_ENABLE3 = "h1".U(1.W)
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val DATA_ACCESS_ENABLE4 = "h0".U(1.W)
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val DATA_ACCESS_ENABLE5 = "h0".U(1.W)
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val DATA_ACCESS_ENABLE6 = "h0".U(1.W)
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val DATA_ACCESS_ENABLE7 = "h0".U(1.W)
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val DATA_ACCESS_MASK0 = "h7FFFFFFF".U(32.W)
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val DATA_ACCESS_MASK1 = "h3FFFFFFF".U(32.W)
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val DATA_ACCESS_MASK2 = "h1FFFFFFF".U(32.W)
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val DATA_ACCESS_MASK3 = "h0FFFFFFF".U(32.W)
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val DATA_ACCESS_MASK4 = "hFFFFFFFF".U(32.W)
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val DATA_ACCESS_MASK5 = "hFFFFFFFF".U(32.W)
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val DATA_ACCESS_MASK6 = "hFFFFFFFF".U(32.W)
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val DATA_ACCESS_MASK7 = "hFFFFFFFF".U(32.W)
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val DCCM_BANK_BITS = "h2".U(3.W)
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val DCCM_BITS = "h10".U(5.W)
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val DCCM_BYTE_WIDTH = "h4".U(3.W)
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val DCCM_DATA_WIDTH = "h20".U(6.W)
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val DCCM_ECC_WIDTH = "h7".U(3.W)
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val DCCM_ENABLE = "h1".U(1.W)
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val DCCM_FDATA_WIDTH = "h27".U(6.W)
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val DCCM_INDEX_BITS = "hC".U(4.W)
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val DCCM_NUM_BANKS = "h04".U(5.W)
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val DCCM_REGION = "hF".U(4.W)
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val DCCM_SADR = "hF0040000".U(32.W)
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val DCCM_SIZE = "h040".U(10.W)
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val DCCM_WIDTH_BITS = "h2".U(2.W)
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val DMA_BUF_DEPTH = "h5".U(3.W)
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val DMA_BUS_ID = "h1".U(1.W)
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val DMA_BUS_PRTY = "h2".U(2.W)
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val DMA_BUS_TAG = "h1".U(4.W)
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val FAST_INTERRUPT_REDIRECT= "h1".U(1.W)
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val ICACHE_2BANKS = "h1".U(1.W)
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val ICACHE_BANK_BITS = "h1".U(3.W)
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val ICACHE_BANK_HI = "h3".U(3.W)
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val ICACHE_BANK_LO = "h3".U(2.W)
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val ICACHE_BANK_WIDTH = "h8".U(4.W)
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val ICACHE_BANKS_WAY = "h2".U(3.W)
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val ICACHE_BEAT_ADDR_HI = "h5".U(4.W)
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val ICACHE_BEAT_BITS = "h3".U(4.W)
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val ICACHE_DATA_DEPTH = "h0200".U(14.W)
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val ICACHE_DATA_INDEX_LO = "h4".U(3.W)
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val ICACHE_DATA_WIDTH = "h40".U(7.W)
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val ICACHE_ECC = "h1".U(1.W)
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val ICACHE_ENABLE = "h1".U(1.W)
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val ICACHE_FDATA_WIDTH = "h47".U(7.W)
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val ICACHE_INDEX_HI = "h0C".U(5.W)
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val ICACHE_LN_SZ = "h40".U(7.W)
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val ICACHE_NUM_BEATS = "h8".U(4.W)
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val ICACHE_NUM_WAYS = "h2".U(3.W)
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val ICACHE_ONLY = "h0".U(1.W)
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val ICACHE_SCND_LAST = "h6".U(4.W)
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val ICACHE_SIZE = "h010".U(9.W)
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val ICACHE_STATUS_BITS = "h1".U(3.W)
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val ICACHE_TAG_DEPTH = "h0080".U(13.W)
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val ICACHE_TAG_INDEX_LO = "h6".U(3.W)
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val ICACHE_TAG_LO = "h0D".U(5.W)
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val ICACHE_WAYPACK = "h0".U(1.W)
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val ICCM_BANK_BITS = "h2".U(3.W)
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val ICCM_BANK_HI = "h03".U(5.W)
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val ICCM_BANK_INDEX_LO = "h04".U(5.W)
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val ICCM_BITS = "h10".U(5.W)
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val ICCM_ENABLE = "h1".U(1.W)
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val ICCM_ICACHE = "h1".U(1.W)
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val ICCM_INDEX_BITS = "hC".U(4.W)
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val ICCM_NUM_BANKS = "h04".U(5.W)
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val ICCM_ONLY = "h0".U(1.W)
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val ICCM_REGION = "hE".U(4.W)
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val ICCM_SADR = "hEE000000".U(32.W)
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val ICCM_SIZE = "h040".U(10.W)
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val IFU_BUS_ID = "h1".U(1.W)
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val IFU_BUS_PRTY = "h2".U(2.W)
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val IFU_BUS_TAG = "h3".U(4.W)
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val INST_ACCESS_ADDR0 = "h00000000".U(32.W)
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val INST_ACCESS_ADDR1 = "hC0000000".U(32.W)
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val INST_ACCESS_ADDR2 = "hA0000000".U(32.W)
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val INST_ACCESS_ADDR3 = "h80000000".U(32.W)
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val INST_ACCESS_ADDR4 = "h00000000".U(32.W)
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val INST_ACCESS_ADDR5 = "h00000000".U(32.W)
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val INST_ACCESS_ADDR6 = "h00000000".U(32.W)
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val INST_ACCESS_ADDR7 = "h00000000".U(32.W)
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val INST_ACCESS_ENABLE0 = "h1".U(1.W)
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val INST_ACCESS_ENABLE1 = "h1".U(1.W)
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val INST_ACCESS_ENABLE2 = "h1".U(1.W)
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val INST_ACCESS_ENABLE3 = "h1".U(1.W)
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val INST_ACCESS_ENABLE4 = "h0".U(1.W)
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val INST_ACCESS_ENABLE5 = "h0".U(1.W)
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val INST_ACCESS_ENABLE6 = "h0".U(1.W)
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val INST_ACCESS_ENABLE7 = "h0".U(1.W)
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val INST_ACCESS_MASK0 = "h7FFFFFFF".U(32.W)
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val INST_ACCESS_MASK1 = "h3FFFFFFF".U(32.W)
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val INST_ACCESS_MASK2 = "h1FFFFFFF".U(32.W)
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val INST_ACCESS_MASK3 = "h0FFFFFFF".U(32.W)
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val INST_ACCESS_MASK4 = "hFFFFFFFF".U(32.W)
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val INST_ACCESS_MASK5 = "hFFFFFFFF".U(32.W)
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val INST_ACCESS_MASK6 = "hFFFFFFFF".U(32.W)
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val INST_ACCESS_MASK7 = "hFFFFFFFF".U(32.W)
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val LOAD_TO_USE_PLUS1 = "h0".U(1.W)
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val LSU2DMA = "h0".U(1.W)
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val LSU_BUS_ID = "h1".U(1.W)
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val LSU_BUS_PRTY = "h2".U(2.W)
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val LSU_BUS_TAG = "h3".U(4.W)
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val LSU_NUM_NBLOAD = "h04".U(5.W)
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val LSU_NUM_NBLOAD_WIDTH = "h2".U(3.W)
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val LSU_SB_BITS = "h10".U(5.W)
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val LSU_STBUF_DEPTH = "h4".U(4.W)
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val NO_ICCM_NO_ICACHE = "h0".U(1.W)
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val PIC_2CYCLE = "h0".U(1.W)
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val PIC_BASE_ADDR = "hF00C0000".U(32.W)
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val PIC_BITS = "h0F".U(5.W)
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val PIC_INT_WORDS = "h1".U(4.W)
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val PIC_REGION = "hF".U(4.W)
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val PIC_SIZE = "h020".U(9.W)
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val PIC_TOTAL_INT = "h1F".U(8.W)
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val PIC_TOTAL_INT_PLUS1 = "h020".U(9.W)
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val RET_STACK_SIZE = "h8".U(4.W)
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val SB_BUS_ID = "h1".U(1.W)
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val SB_BUS_PRTY = "h2".U(2.W)
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val SB_BUS_TAG = "h1".U(4.W)
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val TIMER_LEGAL_EN = "h1".U(1.W)
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}
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@ -1 +1 @@
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||||
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|
|||
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||||
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|
|||
[0m[[0m[31merror[0m] [0m[0m/home/waleedbinehsan/Desktop/SweRV-Chislified-master/src/main/scala/dec/el2_dec_dec_ctl.scala:173:12: type mismatch;[0m
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||||
[0m[[0m[31merror[0m] [0m[0m found : Unit[0m
|
||||
[0m[[0m[31merror[0m] [0m[0m required: dec.el2_dec_dec_ctl => chisel3.iotesters.PeekPokeTester[dec.el2_dec_dec_ctl][0m
|
||||
[0m[[0m[31merror[0m] [0m[0m println(chisel3.Driver.emitVerilog(new el2_dec_dec_ctl()))[0m
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||||
[0m[[0m[31merror[0m] [0m[0m ^[0m
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[0m[[0m[31merror[0m] [0m[0mone error found[0m
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[0m[[0m[33mwarn[0m] [0m[0mthere was one deprecation warning (since 3.2.2)[0m
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[0m[[0m[33mwarn[0m] [0m[0mthere were two deprecation warnings in total; re-run with -deprecation for details[0m
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||||
[0m[[0m[33mwarn[0m] [0m[0mthere were 72 feature warnings; re-run with -feature for details[0m
|
||||
[0m[[0m[33mwarn[0m] [0m[0mfour warnings found[0m
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||||
[0m[[0m[0mdebug[0m] [0m[0mInvalidated products: Set(/home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/encoder_generator.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/rvrangecheck.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/RVCExpander$$anon$1.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/caller$$anon$2.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/dec/dec$.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/rvrangecheck$.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/exp$$anon$9.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/RVCDecoder.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/rvdff$.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/RVCExpander.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/rvbradder.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/reg1.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/reg1$$anon$3.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/tocopy.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/rvdff$$anon$1.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/tocopy$$anon$8.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/dec/el2_dec_dec_ctl.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/dec/el2_dec_pkt_t.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/top$$anon$4.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/caller.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/encoder_generator$$anon$6.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/ExpandedInstruction.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/rvrangecheck$$anon$7.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/rvdff.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/rvbradder$$anon$5.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/exp.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/top.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/encoder_generator$.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/dec/dec.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/dec/dec$delayedInit$body.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/dec/el2_dec_dec_ctl$$anon$1.class)[0m
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||||
[0m[[0m[0mdebug[0m] [0m[0mInvalidated products: Set()[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mExternal API changes: API Changes: Set()[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mModified binary dependencies: Set()[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mInitial directly invalidated classes: Set(dec.dec, dec.el2_dec_dec_ctl, dec.el2_dec_pkt_t)[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mSources indirectly invalidated by:[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m product: Set(/home/waleedbinehsan/Desktop/SweRV-Chislified-master/src/main/scala/lib/RVC.scala, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/src/main/scala/dec/el2_dec_dec_ctl.scala, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/src/main/scala/lib/GCD.scala)[0m
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||||
[0m[[0m[0mdebug[0m] [0m[0m product: Set()[0m
|
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[0m[[0m[0mdebug[0m] [0m[0m binary dep: Set()[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m external source: Set()[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mAll sources are invalidated.[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mAll initially invalidated classes: Set(dec.dec, dec.el2_dec_dec_ctl, dec.el2_dec_pkt_t)[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mAll initially invalidated sources:Set(/home/waleedbinehsan/Desktop/SweRV-Chislified-master/src/main/scala/dec/el2_dec_dec_ctl.scala)[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mInitial set of included nodes: dec.dec, dec.el2_dec_dec_ctl, dec.el2_dec_pkt_t[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mRecompiling all sources: number of invalidated sources > 50.0% of all sources[0m
|
||||
[0m[[0m[0minfo[0m] [0m[0mCompiling 3 Scala sources to /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes ...[0m
|
||||
[0m[[0m[0minfo[0m] [0m[0mCompiling 1 Scala source to /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes ...[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mGetting org.scala-sbt:compiler-bridge_2.12:1.3.5:compile for Scala 2.12.10[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0mGetting org.scala-sbt:compiler-bridge_2.12:1.3.5:compile for Scala 2.12.10[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m[zinc] Running cached compiler 3e6bed8c for Scala compiler version 2.12.10[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m[zinc] Running cached compiler 3bb278c6 for Scala compiler version 2.12.10[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m[zinc] The Scala compiler is invoked with:[0m
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||||
[0m[[0m[0mdebug[0m] [0m[0m -Xsource:2.11[0m
|
||||
[0m[[0m[0mdebug[0m] [0m[0m -Xplugin:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalamacros/paradise_2.12.10/2.1.0/paradise_2.12.10-2.1.0.jar[0m
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|||
[0m[[0m[0mdebug[0m] [0m[0m /home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-library.jar[0m
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[0m[[0m[0mdebug[0m] [0m[0mCompilation failed (CompilerInterface)[0m
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[0m[[0m[31merror[0m] [0m[0m(Compile / [31mcompileIncremental[0m) Compilation failed[0m
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[0m[[0m[0mdebug[0m] [0m[0mScala compilation took 9.899922123 s[0m
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[0m[[0m[0mdebug[0m] [0m[0mDone compiling.[0m
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[0m[[0m[0mdebug[0m] [0m[0mNew invalidations:[0m
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[0m[[0m[0mdebug[0m] [0m[0mInitial set of included nodes: [0m
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[0m[[0m[0mdebug[0m] [0m[0mPreviously invalidated, but (transitively) depend on new invalidations:[0m
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[0m[[0m[0mdebug[0m] [0m[0m Set()[0m
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[0m[[0m[0mdebug[0m] [0m[0mPackaging /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/chisel-module-template_2.12-3.3.0.jar ...[0m
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[0m[[0m[0mdebug[0m] [0m[0mInput file mappings:[0m
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[0m[[0m[0mdebug[0m] [0m[0m /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/snapshot/pt.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lsu/el2_lsu.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/exu/el2_exu.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/dbg/el2_dbg.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m lib/encoder_generator$$anon$6.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/encoder_generator$$anon$6.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m lib/ifu_compress$$anon$1.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/ifu_compress$$anon$1.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/rvrangecheck.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/reg1.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m lib/RVCDriver$.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/RVCDriver$.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m lib/rvrangecheck$.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/rvrangecheck$.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/exp.sc[0m
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@ -40,10 +60,6 @@
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[0m[[0m[0mdebug[0m] [0m[0m /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/rvbradder$$anon$5.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/rvdff$$anon$1.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m lib/RVCDriver.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/RVCDriver.class[0m
|
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[0m[[0m[0mdebug[0m] [0m[0m lib/RVCDriver$delayedInit$body.class[0m
|
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[0m[[0m[0mdebug[0m] [0m[0m /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/RVCDriver$delayedInit$body.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m lib/RVCDecoder.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/RVCDecoder.class[0m
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@ -52,8 +68,6 @@
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[0m[[0m[0mdebug[0m] [0m[0m /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/tocopy.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m lib/encoder_generator.class[0m
|
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[0m[[0m[0mdebug[0m] [0m[0m /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/encoder_generator.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m lib/ifu_compress.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/ifu_compress.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/encoder_generator$.class[0m
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@ -62,6 +76,18 @@
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[0m[[0m[0mdebug[0m] [0m[0m /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/ExpandedInstruction.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/dmi[0m
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[0m[[0m[0mdebug[0m] [0m[0m /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/dmi/rvjtag_tap.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m dmi/dmi_wrapper.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/dmi/dmi_wrapper.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m dmi/dmi_jtag_to_core_sync.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/dmi/dmi_jtag_to_core_sync.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m include/el2_bundle.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/include/el2_bundle.class[0m
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[0m[[0m[0mdebug[0m] [0m[0m dec[0m
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[0m[[0m[0mdebug[0m] [0m[0m /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/dec[0m
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[0m[[0m[0mdebug[0m] [0m[0m dec/el2_dec_dec_ctl$$anon$1.class[0m
|
||||
|
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|
|||
Loading…
Reference in New Issue