RegEnable added

el2_ifu_iccm_mem.fir

@@ -501,7 +501,7 @@ circuit el2_ifu_iccm_mem :
       _T_371 <= redundant_data1_in @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
     redundant_data[1] <= _T_371 @[el2_ifu_iccm_mem.scala 100:21]
-    node _T_372 = bits(io.iccm_rw_addr, 3, 1) @[el2_ifu_iccm_mem.scala 102:50]
+    node _T_372 = bits(io.iccm_rw_addr, 2, 0) @[el2_ifu_iccm_mem.scala 102:50]
     reg iccm_rd_addr_lo_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 102:34]
     iccm_rd_addr_lo_q <= _T_372 @[el2_ifu_iccm_mem.scala 102:34]
     node _T_373 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 103:48]

el2_ifu_iccm_mem.v

@@ -516,7 +516,7 @@ end // initial
     if (reset) begin
       iccm_rd_addr_lo_q <= 3'h0;
     end else begin
-      iccm_rd_addr_lo_q <= io_iccm_rw_addr[3:1];
+      iccm_rd_addr_lo_q <= io_iccm_rw_addr[2:0];
     end
     if (reset) begin
       iccm_rd_addr_hi_q <= 2'h0;

src/main/scala/ifu/el2_ifu_iccm_mem.scala

@@ -99,7 +99,7 @@ class el2_ifu_iccm_mem extends Module with el2_lib {
     io.iccm_wr_data(77,39), io.iccm_wr_data(38,0))
   redundant_data(1) := RegEnable(redundant_data1_in, 0.U, redundant_data1_en.asBool)
 
-  val iccm_rd_addr_lo_q = RegNext(io.iccm_rw_addr(ICCM_BANK_HI,1), 0.U)
+  val iccm_rd_addr_lo_q = RegNext(io.iccm_rw_addr(ICCM_BANK_HI-1,0), 0.U)
   val iccm_rd_addr_hi_q = RegNext(addr_bank_inc(ICCM_BANK_HI-1,1), 0.U)
 
   val iccm_rd_data_pre = Cat(Mux1H((0 until ICCM_NUM_BANKS).map(i=>(iccm_rd_addr_hi_q===i.U)->iccm_bank_dout_fn(i)(31,0))),