PIC,param,lib,mem.scala added

src/main/scala/dbg/dbg.scala

@@ -456,6 +456,6 @@ class dbg extends Module with lib with RequireAsyncReset {
   io.dbg_dma.dbg_ib.dbg_cmd_type      := io.dbg_dec.dbg_ib.dbg_cmd_type
 }
 
-object dbg_main extends App {
+//object dbg_main extends App {
-  println((new chisel3.stage.ChiselStage).emitVerilog(new dbg()))
+//  println((new chisel3.stage.ChiselStage).emitVerilog(new dbg()))
-}
+//}

src/main/scala/exu/exu.scala

@@ -233,6 +233,6 @@ class exu extends Module with lib with RequireAsyncReset{
   io.dec_exu.tlu_exu.exu_npc_r			 		 := Mux(i0_pred_correct_upper_r===1.U,  pred_correct_npc_r, i0_flush_path_upper_r)
 }
 
-object exu_main extends App {
+//object exu_main extends App {
-  println((new chisel3.stage.ChiselStage).emitVerilog(new exu()))
+//  println((new chisel3.stage.ChiselStage).emitVerilog(new exu()))
-}
+//}

src/main/scala/ifu/ifu.scala

@@ -118,6 +118,6 @@ class ifu extends Module with lib with RequireAsyncReset {
   io.iccm_dma_sb_error := mem_ctl.io.iccm_dma_sb_error
 }
 
-object ifu_main extends App {
+//object ifu_main extends App {
-  println((new chisel3.stage.ChiselStage).emitVerilog(new ifu()))
+//  println((new chisel3.stage.ChiselStage).emitVerilog(new ifu()))
-}
+//}

src/main/scala/lib/ahb_to_axi4.scala

@@ -79,7 +79,7 @@ class ahb_to_axi4 extends Module with lib with RequireAsyncReset {
   io.ahb_hreadyout := 0.U
   io.ahb_hresp := 0.U
 }
-object AHB_main extends App {
+//object AHB_main extends App {
-  println("Generate Verilog")
+//  println("Generate Verilog")
-  println((new chisel3.stage.ChiselStage).emitVerilog(new ahb_to_axi4()))
+ // println((new chisel3.stage.ChiselStage).emitVerilog(new ahb_to_axi4()))
-}
+//}

src/main/scala/lib/axi4_to_ahb.scala

@@ -437,7 +437,7 @@ class axi4_to_ahb extends Module with lib with RequireAsyncReset with Config {
   ahbm_data_clk := rvclkhdr(clock, ahbm_data_clken, io.scan_mode)
 }
 
-object AXImain extends App {
+//object AXImain extends App {
-  println("Generate Verilog")
+ // println("Generate Verilog")
-  println((new chisel3.stage.ChiselStage).emitVerilog(new axi4_to_ahb()))
+//  println((new chisel3.stage.ChiselStage).emitVerilog(new axi4_to_ahb()))
-}
+//}

src/main/scala/lib/beh_lib.scala

@@ -1,361 +0,0 @@
-package lib
-import chisel3._
-import chisel3.util._
-
-
-
-class rvdff(WIDTH:Int=1,SHORT:Int=0) extends Module{
- val io = IO(new Bundle{
-val din  = Input(UInt(WIDTH.W))
-val dout = Output(UInt(WIDTH.W))
-})
-
-val flop = RegNext(io.din,0.U)
-
-if(SHORT == 1)
-{io.dout := io.din}
-else
-{io.dout := flop}
-}
-
-class rvdffsc extends Module with lib {
-  val io = IO(new Bundle{
-    val din = Input(UInt(32.W))
-    val en = Input(Bool())
-    val clear = Input(Bool())
-    val out = Output(UInt())
-  })
-  io.out := RegEnable(io.din & Fill(io.din.getWidth, ~io.clear), 0.U, io.en)
-}
-
-class rvdffs extends Module with lib {
-  val io = IO(new Bundle{
-    val din = Input(UInt(32.W))
-    val en = Input(Bool())
-    val clear = Input(Bool())
-    val out = Output(UInt())
-  })
-  io.out := RegEnable(io.din, 0.U, io.en)
-}
-
-class rvsyncss(WIDTH:Int = 251,SHORT:Int = 0) extends Module with RequireAsyncReset{  //Done for verification and testing
-  val io = IO(new Bundle{
-    val din   = Input(UInt(WIDTH.W))
-    val dout  = Output(UInt(WIDTH.W))
-  })
-  val sync_ff1 = RegNext(io.din,0.U)    //RegNext(io.in,init)
-  val sync_ff2 = RegNext(sync_ff1,0.U)
-  if(SHORT == 1)
-  {	io.dout := io.din   }
-  else
-  {	io.dout := sync_ff2 }
-}
-
-
-
-class rvlsadder extends Module{  //Done for verification and testing
-  val io = IO(new Bundle{
-    val rs1     = Input(UInt(32.W))
-    val offset  = Input(UInt(12.W))
-    val dout    = Output(UInt(32.W))
-  })
-  val w1 =  Cat("b0".U,io.rs1(11,0)) + Cat("b0".U,io.offset(11,0))  //w1[12] =cout  offset[11]=sign
-
-  val dout_upper = ((Fill(20, ~(io.offset(11) ^ w1(12)))) & io.rs1(31,12)) |
-    ((Fill(20, ~io.offset(11) ^ w1(12))) & (io.rs1(31,12)+1.U)) |
-    ((Fill(20, io.offset(11) ^ ~w1(12))) & (io.rs1(31,12)-1.U))
-
-  io.dout := Cat(dout_upper,w1(11,0))
-}
-
-
-
-
-class rvbsadder extends Module{   //Done for verification and testing
-  val io = IO(new Bundle{
-    val pc     = Input(UInt(32.W)) // lsb is not using in code
-    val offset = Input(UInt(13.W)) // lsb is not using in code
-    val dout   = Output(UInt(31.W))
-  })
-  val w1 =  Cat("b0".U,io.pc(12,1)) + Cat("b0".U,io.offset(12,1))  //w1[12] =cout  offset[12]=sign
-
-  val dout_upper = ((Fill(19, ~(io.offset(12) ^ w1(12))))&  io.pc(31,13))       |
-    ((Fill(19, ~io.offset(12) ^  w1(12))) & (io.pc(31,13)+1.U)) |
-    ((Fill(19, io.offset(12) ^  ~w1(12))) & (io.pc(31,13)-1.U))
-  io.dout := Cat(dout_upper,w1(11,0))
-}
-
-
-
-
-class rvtwoscomp(WIDTH:Int=32) extends Module{   //Done for verification and testing
-  val io = IO(new Bundle{
-    val din   = Input(UInt(WIDTH.W))
-    val dout  = Output(UInt(WIDTH.W))
-  })
-
-
-  val temp = Wire(Vec(WIDTH-1,UInt(1.W)))
-  val i:Int = 1
-
-  for(i <- 1 to WIDTH-1){
-    val done  = io.din(i-1,0).orR
-    temp(i-1) := Mux(done ,~io.din(i),io.din(i))
-  }
-  io.dout := Cat(temp.asUInt,io.din(0))
-}
-
-
-class rvmaskandmatch(WIDTH:Int=32) extends Module{     //Done for verification and testing
-  val io = IO(new Bundle{
-    val mask       = Input(UInt(WIDTH.W))
-    val data       = Input(UInt(WIDTH.W))
-    val masken     = Input(UInt(1.W))
-    val match_out  = Output(UInt(1.W))
-  })
-
-  val matchvec = Wire(Vec(WIDTH,UInt(1.W)))
-  val masken_or_fullmask = io.masken.asBool & ~io.mask(WIDTH-1,0).andR
-
-  matchvec(0)  :=  masken_or_fullmask | (io.mask(0) === io.data(0)).asUInt
-
-  for(i <- 1 to WIDTH-1)
-  {matchvec(i) := Mux(io.mask(i-1,0).andR & masken_or_fullmask,"b1".U,(io.mask(i) === io.data(i)).asUInt)}
-  io.match_out := matchvec.asUInt
-}
-
-
-
-
-class rvrangecheck(CCM_SADR:Int=0, CCM_SIZE:Int=128) extends Module{
-  val io = IO(new Bundle{
-    val addr       =  Input(UInt(32.W))
-    val in_range   =  Output(UInt(1.W))
-    val in_region  =  Output(UInt(1.W))
-  })
-  val REGION_BITS = 4
-  val MASK_BITS   = 10 + log2Ceil(CCM_SIZE)
-
-  val start_addr  = Wire(UInt(32.W))
-  start_addr  := CCM_SIZE.U
-  val region  = start_addr(31,(32-REGION_BITS))
-
-  io.in_region  := (io.addr(31,(32-REGION_BITS)) === region(REGION_BITS-1,0)).asUInt
-  if(CCM_SIZE == 48)
-    io.in_range := (io.addr(31,MASK_BITS) === start_addr(31,MASK_BITS)).asUInt & ~(io.addr(MASK_BITS-1,MASK_BITS-2).andR.asUInt)
-  else
-    io.in_range := (io.addr(31,MASK_BITS) === start_addr(31,MASK_BITS)).asUInt
-}
-
-
-
-// DONE
-class rveven_paritygen(WIDTH:Int= 16) extends Module{    //Done for verification and testing
-  val io = IO(new Bundle{
-    val data_in        =  Input (UInt(WIDTH.W))
-    val parity_out     =  Output(UInt(1.W))
-  })
-  io.parity_out := io.data_in.xorR.asUInt
-} // DONE
-
-
-// DONE
-class rveven_paritycheck(WIDTH:Int= 16) extends Module{    //Done for verification and testing
-  val io = IO(new Bundle{
-    val data_in        =  Input (UInt(WIDTH.W))
-    val parity_in      =  Input (UInt(1.W))
-    val parity_err     =  Output(UInt(1.W))
-  })
-  io.parity_err := (io.data_in.xorR.asUInt) ^ io.parity_in
-} // DONE
-
-
-
-class rvecc_encode extends Module{   //Done for verification and testing
-  val io      =  IO(new Bundle{
-    val din     =  Input(UInt(32.W))
-    val ecc_out =  Output(UInt(7.W))
-  })
-  val mask0 = Array(0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0,1,1,0,1,1)
-  val mask1 = Array(1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,1,1,0,1)
-  val mask2 = Array(1,1,1,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,1,1,1,1,0,0,0,1,1,1,0)
-  val mask3 = Array(0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,1,1,1,1,1,1,1,0,0,0,0)
-  val mask4 = Array(0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0)
-  val mask5 = Array(1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0)
-  val w0 = Wire(Vec(18,UInt(1.W)))
-  val w1 = Wire(Vec(18,UInt(1.W)))
-  val w2 = Wire(Vec(18,UInt(1.W)))
-  val w3 = Wire(Vec(15,UInt(1.W)))
-  val w4 = Wire(Vec(15,UInt(1.W)))
-  val w5 = Wire(Vec(6, UInt(1.W)))
-  var j = 0;var k = 0;var m = 0;
-  var x = 0;var y = 0;var z = 0
-
-  for(i <- 0 to 31)
-  {
-    if(mask0(i)==1) {w0(j) := io.din(i); j = j +1 }
-    if(mask1(i)==1) {w1(k) := io.din(i); k = k +1 }
-    if(mask2(i)==1) {w2(m) := io.din(i); m = m +1 }
-    if(mask3(i)==1) {w3(x) := io.din(i); x = x +1 }
-    if(mask4(i)==1) {w4(y) := io.din(i); y = y +1 }
-    if(mask5(i)==1) {w5(z) := io.din(i); z = z +1 }
-  }
-  val w6 = Cat((w0.asUInt.xorR),(w1.asUInt.xorR),(w2.asUInt.xorR),(w3.asUInt.xorR),(w4.asUInt.xorR),(w5.asUInt.xorR))
-  io.ecc_out := Cat(io.din.xorR ^ w6.xorR, w6)
-}
-
-
-// Make generator and then make it a method
-class rvecc_decode extends Module{  //Done for verification and testing
-  val io      =  IO(new Bundle{
-    val en      =  Input(UInt(1.W))
-    val din     =  Input(UInt(32.W))
-    val ecc_in  =  Input(UInt(7.W))
-    val sed_ded =  Input(UInt(1.W))
-    val ecc_out =  Output(UInt(7.W))
-    val dout    =  Output(UInt(32.W))
-    val single_ecc_error = Output(UInt(1.W))
-    val double_ecc_error = Output(UInt(1.W))
-  })
-  val mask0 = Array(1,1,0,1,1,0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0)
-  val mask1 = Array(1,0,1,1,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1)
-  val mask2 = Array(0,1,1,1,0,0,0,1,1,1,1,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,1,1,1)
-  val mask3 = Array(0,0,0,0,1,1,1,1,1,1,1,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0)
-  val mask4 = Array(0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0)
-  val mask5 = Array(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1)
-
-  val w0 = Wire(Vec(18,UInt(1.W)))
-  val w1 = Wire(Vec(18,UInt(1.W)))
-  val w2 = Wire(Vec(18,UInt(1.W)))
-  val w3 = Wire(Vec(15,UInt(1.W)))
-  val w4 = Wire(Vec(15,UInt(1.W)))
-  val w5 = Wire(Vec(6,UInt(1.W)))
-
-  var j = 0;var k = 0;var m = 0;  var n =0;
-  var x = 0;var y = 0;
-
-  for(i <- 0 to 31)
-  {
-    if(mask0(i)==1) {w0(j) := io.din(i); j = j +1 }
-    if(mask1(i)==1) {w1(k) := io.din(i); k = k +1 }
-    if(mask2(i)==1) {w2(m) := io.din(i); m = m +1 }
-    if(mask3(i)==1) {w3(n) := io.din(i); n = n +1 }
-    if(mask4(i)==1) {w4(x) := io.din(i); x = x +1 }
-    if(mask5(i)==1) {w5(y) := io.din(i); y = y +1 }
-  }
-
-  val ecc_check = Cat((io.din.xorR ^ io.ecc_in.xorR) & ~io.sed_ded ,io.ecc_in(5)^(w5.asUInt.xorR),io.ecc_in(4)^(w4.asUInt.xorR),io.ecc_in(3)^(w3.asUInt.xorR),io.ecc_in(2)^(w2.asUInt.xorR),io.ecc_in(1)^(w1.asUInt.xorR),io.ecc_in(0)^(w0.asUInt.xorR))
-  io.ecc_out := ecc_check
-
-  io.single_ecc_error :=  io.en & (ecc_check!= 0.U) & ((io.din.xorR ^ io.ecc_in.xorR) & ~io.sed_ded)
-  io.double_ecc_error :=  io.en & (ecc_check!= 0.U) & ((io.din.xorR ^ io.ecc_in.xorR) & ~io.sed_ded)
-  val error_mask = Wire(Vec(39,UInt(1.W)))
-
-  for(i <- 1 until 40){
-    error_mask(i-1) := ecc_check(5,0) === i.asUInt
-  }
-  val din_plus_parity = Cat(io.ecc_in(6), io.din(31,26), io.ecc_in(5), io.din(25,11), io.ecc_in(4), io.din(10,4), io.ecc_in(3), io.din(3,1), io.ecc_in(2), io.din(0), io.ecc_in(1,0))
-  val dout_plus_parity = Mux(io.single_ecc_error.asBool, (error_mask.asUInt ^ din_plus_parity), din_plus_parity)
-
-  io.dout :=  Cat(dout_plus_parity(37,32),dout_plus_parity(30,16), dout_plus_parity(14,8), dout_plus_parity(6,4), dout_plus_parity(2))
-  io.ecc_out := Cat(dout_plus_parity(38) ^ (ecc_check(6,0) === "b1000000".U), dout_plus_parity(31), dout_plus_parity(15), dout_plus_parity(7), dout_plus_parity(3), dout_plus_parity(1,0))
-}
-
-
-
-
-
-
-class rvecc_encode_64 extends Module{    //Done for verification and testing
-  val io      =  IO(new Bundle{
-    val din     =  Input(UInt(64.W))
-    val ecc_out =  Output(UInt(7.W))
-  })
-  val mask0 = Array(1,1,0,1,1,0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0,1)
-  val mask1 = Array(1,0,1,1,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1,1)
-  val mask2 = Array(0,1,1,1,0,0,0,1,1,1,1,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,1,1,1,1)
-  val mask3 = Array(0,0,0,0,1,1,1,1,1,1,1,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0)
-  val mask4 = Array(0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0)
-  val mask5 = Array(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0)
-  val mask6 = Array(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1)
-
-  val w0 = Wire(Vec(35,UInt(1.W)))
-  val w1 = Wire(Vec(35,UInt(1.W)))
-  val w2 = Wire(Vec(35,UInt(1.W)))
-  val w3 = Wire(Vec(31,UInt(1.W)))
-  val w4 = Wire(Vec(31,UInt(1.W)))
-  val w5 = Wire(Vec(31,UInt(1.W)))
-  val w6 = Wire(Vec(7, UInt(1.W)))
-
-  var j = 0;var k = 0;var m = 0; var n =0;
-  var x = 0;var y = 0;var z = 0
-
-  for(i <- 0 to 63)
-  {
-    if(mask0(i)==1) {w0(j) := io.din(i); j = j +1 }
-    if(mask1(i)==1) {w1(k) := io.din(i); k = k +1 }
-    if(mask2(i)==1) {w2(m) := io.din(i); m = m +1 }
-    if(mask3(i)==1) {w3(n) := io.din(i); n = n +1 }
-    if(mask4(i)==1) {w4(x) := io.din(i); x = x +1 }
-    if(mask5(i)==1) {w5(y) := io.din(i); y = y +1 }
-    if(mask6(i)==1) {w6(z) := io.din(i); z = z +1 }
-  }
-  io.ecc_out := Cat((w0.asUInt.xorR),(w1.asUInt.xorR),(w2.asUInt.xorR),(w3.asUInt.xorR),(w4.asUInt.xorR),(w5.asUInt.xorR),(w6.asUInt.xorR))
-}
-
-
-
-
-
-class rvecc_decode_64 extends Module{     //Done for verification and testing
-  val io        =  IO(new Bundle{
-    val en        =  Input(UInt(1.W))
-    val din       =  Input(UInt(64.W))
-    val ecc_in    =  Input(UInt(7.W))
-    val ecc_error =  Output(UInt(1.W))
-  })
-  val mask0 = Array(1,1,0,1,1,0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0,1)
-  val mask1 = Array(1,0,1,1,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1,1)
-  val mask2 = Array(0,1,1,1,0,0,0,1,1,1,1,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,1,1,1,1)
-  val mask3 = Array(0,0,0,0,1,1,1,1,1,1,1,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0)
-  val mask4 = Array(0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0)
-  val mask5 = Array(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0)
-  val mask6 = Array(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1)
-
-  val w0 = Wire(Vec(35,UInt(1.W)))
-  val w1 = Wire(Vec(35,UInt(1.W)))
-  val w2 = Wire(Vec(35,UInt(1.W)))
-  val w3 = Wire(Vec(31,UInt(1.W)))
-  val w4 = Wire(Vec(31,UInt(1.W)))
-  val w5 = Wire(Vec(31,UInt(1.W)))
-  val w6 = Wire(Vec(7, UInt(1.W)))
-
-  var j = 0;var k = 0;var m = 0;  var n =0;
-  var x = 0;var y = 0;var z = 0
-
-  for(i <- 0 to 63)
-  {
-    if(mask0(i)==1) {w0(j) := io.din(i); j = j +1 }
-    if(mask1(i)==1) {w1(k) := io.din(i); k = k +1 }
-    if(mask2(i)==1) {w2(m) := io.din(i); m = m +1 }
-    if(mask3(i)==1) {w3(n) := io.din(i); n = n +1 }
-    if(mask4(i)==1) {w4(x) := io.din(i); x = x +1 }
-    if(mask5(i)==1) {w5(y) := io.din(i); y = y +1 }
-    if(mask6(i)==1) {w6(z) := io.din(i); z = z +1 }
-  }
-
-  val ecc_check = Cat((io.ecc_in(6) ^ w5.asUInt.xorR) ,io.ecc_in(5)^(w5.asUInt.xorR),io.ecc_in(4)^(w4.asUInt.xorR),io.ecc_in(3)^(w3.asUInt.xorR),io.ecc_in(2)^(w2.asUInt.xorR),io.ecc_in(1)^(w1.asUInt.xorR),io.ecc_in(0)^(w0.asUInt.xorR))
-  io.ecc_error := io.en & (ecc_check(6,0) != 0.U)
-
-
-  object rvsyncss {
-    def apply(din:UInt,clk:Clock) =withClock(clk){RegNext(withClock(clk){RegNext(din,0.U)},0.U)}
-  }
-}
-
-
-
-
-
-
-

src/main/scala/lib/lib.scala

@@ -1,178 +1,38 @@
 package lib
 import chisel3._
 import chisel3.util._
-import mem.quasar.{DCCM_ENABLE, ICACHE_ECC, ICACHE_WAYPACK, ICCM_ENABLE, bool2int}
+import include._
-trait param {
-  val BHT_ADDR_HI            = 9
-  val BHT_ADDR_LO            = 2
-  val BHT_ARRAY_DEPTH        = 256
-  val BHT_GHR_HASH_1         = false
-  val BHT_GHR_SIZE           = 8
-  val BHT_SIZE               = 512
-  val BTB_ADDR_HI            = 9
-  val BTB_ADDR_LO            = 2
-  val BTB_ARRAY_DEPTH        = 256
-  val BTB_BTAG_FOLD          = false
-  val BTB_BTAG_SIZE          = 5
-  val BTB_FOLD2_INDEX_HASH   = false
-  val BTB_INDEX1_HI          = 9
-  val BTB_INDEX1_LO          = 2
-  val BTB_INDEX2_HI          = 17
-  val BTB_INDEX2_LO          = 10
-  val BTB_INDEX3_HI          = 25
-  val BTB_INDEX3_LO          = 18
-  val BTB_SIZE               = 512
-  val BUILD_AHB_LITE         = false
-  val BUILD_AXI4             = true
-  val BUILD_AXI_NATIVE       = true
-  val BUS_PRTY_DEFAULT       = 3
-  val DATA_ACCESS_ADDR0      = 0x00000000 //.U(32.W)
-  val DATA_ACCESS_ADDR1      = 0xC0000000 //.U(32.W)
-  val DATA_ACCESS_ADDR2      = 0xA0000000 //.U(32.W)
-  val DATA_ACCESS_ADDR3      = 0x80000000 //.U(32.W)
-  val DATA_ACCESS_ADDR4      = 0x00000000 //.U(32.W)
-  val DATA_ACCESS_ADDR5      = 0x00000000 //.U(32.W)
-  val DATA_ACCESS_ADDR6      = 0x00000000 //.U(32.W)
-  val DATA_ACCESS_ADDR7      = 0x00000000 //.U(32.W)
-  val DATA_ACCESS_ENABLE0    = true //.U(1.W)
-  val DATA_ACCESS_ENABLE1    = true //.U(1.W)
-  val DATA_ACCESS_ENABLE2    = true //.U(1.W)
-  val DATA_ACCESS_ENABLE3    = true //.U(1.W)
-  val DATA_ACCESS_ENABLE4    = false //.U(1.W)
-  val DATA_ACCESS_ENABLE5    = false //.U(1.W)
-  val DATA_ACCESS_ENABLE6    = false //.U(1.W)
-  val DATA_ACCESS_ENABLE7    = false //.U(1.W)
-  val DATA_ACCESS_MASK0      = 0x7FFFFFFF //.U(32.W)
-  val DATA_ACCESS_MASK1      = 0x3FFFFFFF //.U(32.W)
-  val DATA_ACCESS_MASK2      = 0x1FFFFFFF //.U(32.W)
-  val DATA_ACCESS_MASK3      = 0x0FFFFFFF //.U(32.W)
-  val DATA_ACCESS_MASK4      = 0xFFFFFFFF //.U(32.W)
-  val DATA_ACCESS_MASK5      = 0xFFFFFFFF //.U(32.W)
-  val DATA_ACCESS_MASK6      = 0xFFFFFFFF //.U(32.W)
-  val DATA_ACCESS_MASK7      = 0xFFFFFFFF //.U(32.W)
-  val DCCM_BANK_BITS         = 2  //.U(3.W)
-  val DCCM_BITS              = 16 //.U(5.W)
-  val DCCM_BYTE_WIDTH        = 4  //.U(3.W)
-  val DCCM_DATA_WIDTH        = 32 //.U(6.W)
-  val DCCM_ECC_WIDTH         = 7  //.U(3.W)
-  val DCCM_ENABLE            = true  //.U(1.W)
-  val DCCM_FDATA_WIDTH       = 0x27 //.U(6.W)
-  val DCCM_INDEX_BITS        = 0xC  //.U(4.W)
-  val DCCM_NUM_BANKS         = 0x04 //.U(5.W)
-  val DCCM_REGION            = 15  //.U(4.W)
-  val DCCM_SADR              = 0xF0040000
-  val DCCM_SIZE              = 0x040
-  val DCCM_WIDTH_BITS        = 2 //.U(2.W)
-  val DMA_BUF_DEPTH          = 5 //.U(3.W)
-  val DMA_BUS_ID             = true //.U(1.W)
-  val DMA_BUS_PRTY           = 0x2 //.U(2.W)
-  val DMA_BUS_TAG            = 0x1 //.U(4.W)
-  val FAST_INTERRUPT_REDIRECT= 0x1 //.U(1.W)
-  val ICACHE_2BANKS          = 1
-  val ICACHE_BANK_BITS       = 1
-  val ICACHE_BANK_HI         = 3
-  val ICACHE_BANK_LO         = 3
-  val ICACHE_BANK_WIDTH      = 8
-  val ICACHE_BANKS_WAY       = 2
-  val ICACHE_BEAT_ADDR_HI    = 5
-  val ICACHE_BEAT_BITS       = 3
-  val ICACHE_DATA_DEPTH      = 512
-  val ICACHE_DATA_INDEX_LO   = 4
-  val ICACHE_DATA_WIDTH      = 64
-  val ICACHE_ECC             = true
-  val ICACHE_ENABLE          = true
-  val ICACHE_FDATA_WIDTH     = 71
-  val ICACHE_INDEX_HI        = 12
-  val ICACHE_LN_SZ           = 64
-  val ICACHE_NUM_BEATS       = 8
-  val ICACHE_NUM_WAYS        = 2
-  val ICACHE_ONLY            = false
-  val ICACHE_SCND_LAST       = 6
-  val ICACHE_SIZE            = 16
-  val ICACHE_STATUS_BITS     = 1
-  val ICACHE_TAG_DEPTH       = 128
-  val ICACHE_TAG_INDEX_LO    = 6
-  val ICACHE_TAG_LO          = 13
-  val ICACHE_WAYPACK         = false
-  val ICCM_BANK_BITS         = 2
-  val ICCM_BANK_HI           = 3  //.U(5.W)
-  val ICCM_BANK_INDEX_LO     = 4  //.U(5.W)
-  val ICCM_BITS              = 16  //.U(5.W)
-  val ICCM_ENABLE            = true   //.U(1.W)
-  val ICCM_ICACHE            = true   //.U(1.W)
-  val ICCM_INDEX_BITS        = 0xC   //.U(4.W)
-  val ICCM_NUM_BANKS         = 0x04  //.U(5.W)
-  val ICCM_ONLY              = false   //.U(1.W)
-  val ICCM_REGION            = 0xE   //.U(4.W)
-  val ICCM_SADR              = 0xEE000000 //.U(32.W)
-  val ICCM_SIZE              = 0x040 //.U(10.W)
-  val IFU_BUS_ID             = 0x1   //.U(1.W)
-  val IFU_BUS_PRTY           = 0x2   //.U(2.W)
-  val IFU_BUS_TAG            = 0x3   //.U(4.W)
-  val INST_ACCESS_ADDR0      = 0x00000000 //.U(32.W)
-  val INST_ACCESS_ADDR1      = 0xC0000000 //.U(32.W)
-  val INST_ACCESS_ADDR2      = 0xA0000000 //.U(32.W)
-  val INST_ACCESS_ADDR3      = 0x80000000 //.U(32.W)
-  val INST_ACCESS_ADDR4      = 0x00000000 //.U(32.W)
-  val INST_ACCESS_ADDR5      = 0x00000000 //.U(32.W)
-  val INST_ACCESS_ADDR6      = 0x00000000 //.U(32.W)
-  val INST_ACCESS_ADDR7      = 0x00000000 //.U(32.W)
-  val INST_ACCESS_ENABLE0    = 0x1 //.U(1.W)
-  val INST_ACCESS_ENABLE1    = 0x1 //.U(1.W)
-  val INST_ACCESS_ENABLE2    = 0x1 //.U(1.W)
-  val INST_ACCESS_ENABLE3    = 0x1 //.U(1.W)
-  val INST_ACCESS_ENABLE4    = 0x0 //.U(1.W)
-  val INST_ACCESS_ENABLE5    = 0x0 //.U(1.W)
-  val INST_ACCESS_ENABLE6    = 0x0 //.U(1.W)
-  val INST_ACCESS_ENABLE7    = 0x0 //.U(1.W)
-  val INST_ACCESS_MASK0      = 0x7FFFFFFF //.U(32.W)
-  val INST_ACCESS_MASK1      = 0x3FFFFFFF //.U(32.W)
-  val INST_ACCESS_MASK2      = 0x1FFFFFFF //.U(32.W)
-  val INST_ACCESS_MASK3      = 0x0FFFFFFF //.U(32.W)
-  val INST_ACCESS_MASK4      = 0xFFFFFFFF //.U(32.W)
-  val INST_ACCESS_MASK5      = 0xFFFFFFFF //.U(32.W)
-  val INST_ACCESS_MASK6      = 0xFFFFFFFF //.U(32.W)
-  val INST_ACCESS_MASK7      = 0xFFFFFFFF //.U(32.W)
-  val LOAD_TO_USE_PLUS1      = 0x0 //.U(1.W)
-  val LSU2DMA                = 0x0 //.U(1.W)
-  val LSU_BUS_ID             = 0x1 //.U(1.W)
-  val LSU_BUS_PRTY           = 0x2 //.U(2.W)
-  val LSU_BUS_TAG            = 0x3 //.U(4.W)
-  val LSU_NUM_NBLOAD         = 0x04 //.U(5.W)
-  val LSU_NUM_NBLOAD_WIDTH   = 0x2  //.U(3.W)
-  val LSU_SB_BITS            = 0x10 //.U(5.W)
-  val LSU_STBUF_DEPTH        = 0x4  //.U(4.W)
-  val NO_ICCM_NO_ICACHE      = false  //.U(1.W)
-  val PIC_2CYCLE             = 0x0  //.U(1.W)
-  val PIC_BASE_ADDR          = 0xF00C0000 //.U(32.W)
-  val PIC_BITS               = 0x0F  //.U(5.W)
-  val PIC_INT_WORDS          = 0x1   //.U(4.W)
-  val PIC_REGION             = 0xF   //.U(4.W)
-  val PIC_SIZE               = 0x020 //.U(9.W)
-  val PIC_TOTAL_INT          = 0x1F  //.U(8.W)
-  val PIC_TOTAL_INT_PLUS1    = 0x020 //.U(9.W)
-  val RET_STACK_SIZE         = 0x8   //.U(4.W)
-  val SB_BUS_ID              = 0x1   //.U(1.W)
-  val SB_BUS_PRTY            = 0x2   //.U(2.W)
-  val SB_BUS_TAG             = 0x1   //.U(4.W)
-  val TIMER_LEGAL_EN         = 0x1   //.U(1.W)
-}
-
 trait lib extends param{
+  implicit def int2boolean(b:Int) = if (b==1) true else false
+
+  implicit def uint2bool(b:UInt) = b.asBool()
+
+  implicit def aslong(b:Int) = 0xFFFFFFFFL & b
+
   def repl(b:Int, a:UInt) = VecInit.tabulate(b)(i => a).reduce(Cat(_,_))
 
+ // def bridge_gen(tag: Int, ahb_type: Boolean) = if(BUILD_AXI4) flip(tag, ahb_type) else ahb_bridge_gen(ahb_type)
+
+//  def flip(tag: Int , ahb_type: Boolean) = if(ahb_type) Flipped(new axi_channels(tag)) else new axi_channels(tag)
+
+//  def ahb_bridge_gen(ahb_type: Boolean) = if(ahb_type) new Bundle{
+//    val sig = Flipped(new ahb_channel())
+ //   val hsel = Input(Bool())
+ //   val hreadyin = Input(Bool())}
+//  else new ahb_channel()
+
   def MEM_CAL : (Int, Int, Int, Int)=
     (ICACHE_WAYPACK, ICACHE_ECC) match{
-      case(false,false) => (68, 22, 68, 22)
+      case(0,0) => (68, 22, 68, 22)
-      case(false,true)  => (71, 26, 71, 26)
+      case(0,1)  => (71, 26, 71, 26)
-      case(true,false)  => (68*ICACHE_NUM_WAYS, 22*ICACHE_NUM_WAYS, 68, 22)
+      case(1,0)  => (68*ICACHE_NUM_WAYS, 22*ICACHE_NUM_WAYS, 68, 22)
-      case(true,true)   => (71*ICACHE_NUM_WAYS, 26*ICACHE_NUM_WAYS, 71, 26)
+      case(1,1)   => (71*ICACHE_NUM_WAYS, 26*ICACHE_NUM_WAYS, 71, 26)
     }
+
   val DATA_MEM_LINE = MEM_CAL
   val Tag_Word = MEM_CAL._4
 
-  implicit def bool2int(b:Boolean) = if (b) 1 else 0
+
-  implicit def aslong(b:Int) = 0xFFFFFFFFL & b
   object rvsyncss {
     def apply(din:UInt,clk:Clock) =withClock(clk){RegNext(withClock(clk){RegNext(din,0.U)},0.U)}
   }

src/main/scala/lib/param.scala

@@ -0,0 +1,158 @@
+package lib
+import chisel3._
+import chisel3.util._
+trait param {
+  val BHT_ADDR_HI            = 	0x9
+  val BHT_ADDR_LO            = 	0x2
+  val BHT_ARRAY_DEPTH        = 	0x100
+  val BHT_GHR_HASH_1         = 	0x0
+  val BHT_GHR_SIZE           = 	0x8
+  val BHT_SIZE               = 	0x200
+  val BTB_ADDR_HI            = 	0x09
+  val BTB_ADDR_LO            = 	0x2
+  val BTB_ARRAY_DEPTH        = 	0x100
+  val BTB_BTAG_FOLD          = 	0x0
+  val BTB_BTAG_SIZE          = 	0x5
+  val BTB_FOLD2_INDEX_HASH   = 	0x0
+  val BTB_INDEX1_HI          = 	0x09
+  val BTB_INDEX1_LO          = 	0x02
+  val BTB_INDEX2_HI          = 	0x11
+  val BTB_INDEX2_LO          = 	0x0A
+  val BTB_INDEX3_HI          = 	0x19
+  val BTB_INDEX3_LO          = 	0x12
+  val BTB_SIZE               = 	0x200
+  val BUILD_AHB_LITE         = 	0x0
+  val BUILD_AXI4             = 	0x1
+  val BUILD_AXI_NATIVE       = 	0x1
+  val BUS_PRTY_DEFAULT       = 	0x3
+  val DATA_ACCESS_ADDR0      = 	0x00000000
+  val DATA_ACCESS_ADDR1      = 	0xC0000000
+  val DATA_ACCESS_ADDR2      = 	0xA0000000
+  val DATA_ACCESS_ADDR3      = 	0x80000000
+  val DATA_ACCESS_ADDR4      = 	0x00000000
+  val DATA_ACCESS_ADDR5      = 	0x00000000
+  val DATA_ACCESS_ADDR6      = 	0x00000000
+  val DATA_ACCESS_ADDR7      = 	0x00000000
+  val DATA_ACCESS_ENABLE0    = 	0x1
+  val DATA_ACCESS_ENABLE1    = 	0x1
+  val DATA_ACCESS_ENABLE2    = 	0x1
+  val DATA_ACCESS_ENABLE3    = 	0x1
+  val DATA_ACCESS_ENABLE4    = 	0x0
+  val DATA_ACCESS_ENABLE5    = 	0x0
+  val DATA_ACCESS_ENABLE6    = 	0x0
+  val DATA_ACCESS_ENABLE7    = 	0x0
+  val DATA_ACCESS_MASK0      = 	0x7FFFFFFF
+  val DATA_ACCESS_MASK1      = 	0x3FFFFFFF
+  val DATA_ACCESS_MASK2      = 	0x1FFFFFFF
+  val DATA_ACCESS_MASK3      = 	0x0FFFFFFF
+  val DATA_ACCESS_MASK4      = 	0xFFFFFFFF
+  val DATA_ACCESS_MASK5      = 	0xFFFFFFFF
+  val DATA_ACCESS_MASK6      = 	0xFFFFFFFF
+  val DATA_ACCESS_MASK7      = 	0xFFFFFFFF
+  val DCCM_BANK_BITS         = 	0x2
+  val DCCM_BITS              = 	0x10
+  val DCCM_BYTE_WIDTH        = 	0x4
+  val DCCM_DATA_WIDTH        = 	0x20
+  val DCCM_ECC_WIDTH         = 	0x7
+  val DCCM_ENABLE            = 	0x1
+  val DCCM_FDATA_WIDTH       = 	0x27
+  val DCCM_INDEX_BITS        = 	0xC
+  val DCCM_NUM_BANKS         = 	0x04
+  val DCCM_REGION            = 	0xF
+  val DCCM_SADR              = 	0xF0040000
+  val DCCM_SIZE              = 	0x040
+  val DCCM_WIDTH_BITS        = 	0x2
+  val DMA_BUF_DEPTH          = 	0x5
+  val DMA_BUS_ID             = 	0x1
+  val DMA_BUS_PRTY           = 	0x2
+  val DMA_BUS_TAG            = 	0x1
+  val FAST_INTERRUPT_REDIRECT = 0x1
+  val ICACHE_2BANKS          = 	0x1
+  val ICACHE_BANK_BITS       = 	0x1
+  val ICACHE_BANK_HI         = 	0x3
+  val ICACHE_BANK_LO         = 	0x3
+  val ICACHE_BANK_WIDTH      = 	0x8
+  val ICACHE_BANKS_WAY       = 	0x2
+  val ICACHE_BEAT_ADDR_HI    = 	0x5
+  val ICACHE_BEAT_BITS       = 	0x3
+  val ICACHE_DATA_DEPTH      = 	0x0200
+  val ICACHE_DATA_INDEX_LO   = 	0x4
+  val ICACHE_DATA_WIDTH      = 	0x40
+  val ICACHE_ECC             = 	0x1
+  val ICACHE_ENABLE          = 	0x1
+  val ICACHE_FDATA_WIDTH     = 	0x47
+  val ICACHE_INDEX_HI        = 	0x0C
+  val ICACHE_LN_SZ           = 	0x40
+  val ICACHE_NUM_BEATS       = 	0x8
+  val ICACHE_NUM_WAYS        = 	0x2
+  val ICACHE_ONLY            = 	0x0
+  val ICACHE_SCND_LAST       = 	0x6
+  val ICACHE_SIZE            = 	0x010
+  val ICACHE_STATUS_BITS     = 	0x1
+  val ICACHE_TAG_DEPTH       = 	0x0080
+  val ICACHE_TAG_INDEX_LO    = 	0x6
+  val ICACHE_TAG_LO          = 	0x0D
+  val ICACHE_WAYPACK         = 	0x0
+  val ICCM_BANK_BITS         = 	0x2
+  val ICCM_BANK_HI           = 	0x03
+  val ICCM_BANK_INDEX_LO     = 	0x04
+  val ICCM_BITS              = 	0x10
+  val ICCM_ENABLE            = 	0x1
+  val ICCM_ICACHE            = 	0x1
+  val ICCM_INDEX_BITS        = 	0xC
+  val ICCM_NUM_BANKS         = 	0x04
+  val ICCM_ONLY              = 	0x0
+  val ICCM_REGION            = 	0xE
+  val ICCM_SADR              = 	0xEE000000
+  val ICCM_SIZE              = 	0x040
+  val IFU_BUS_ID             = 	0x1
+  val IFU_BUS_PRTY           = 	0x2
+  val IFU_BUS_TAG            = 	0x3
+  val INST_ACCESS_ADDR0      = 	0x00000000
+  val INST_ACCESS_ADDR1      = 	0xC0000000
+  val INST_ACCESS_ADDR2      = 	0xA0000000
+  val INST_ACCESS_ADDR3      = 	0x80000000
+  val INST_ACCESS_ADDR4      = 	0x00000000
+  val INST_ACCESS_ADDR5      = 	0x00000000
+  val INST_ACCESS_ADDR6      = 	0x00000000
+  val INST_ACCESS_ADDR7      = 	0x00000000
+  val INST_ACCESS_ENABLE0    = 	0x1
+  val INST_ACCESS_ENABLE1    = 	0x1
+  val INST_ACCESS_ENABLE2    = 	0x1
+  val INST_ACCESS_ENABLE3    = 	0x1
+  val INST_ACCESS_ENABLE4    = 	0x0
+  val INST_ACCESS_ENABLE5    = 	0x0
+  val INST_ACCESS_ENABLE6    = 	0x0
+  val INST_ACCESS_ENABLE7    = 	0x0
+  val INST_ACCESS_MASK0      = 	0x7FFFFFFF
+  val INST_ACCESS_MASK1      = 	0x3FFFFFFF
+  val INST_ACCESS_MASK2      = 	0x1FFFFFFF
+  val INST_ACCESS_MASK3      = 	0x0FFFFFFF
+  val INST_ACCESS_MASK4      = 	0xFFFFFFFF
+  val INST_ACCESS_MASK5      = 	0xFFFFFFFF
+  val INST_ACCESS_MASK6      = 	0xFFFFFFFF
+  val INST_ACCESS_MASK7      = 	0xFFFFFFFF
+  val LOAD_TO_USE_PLUS1      = 	0x0
+  val LSU2DMA                = 	0x0
+  val LSU_BUS_ID             = 	0x1
+  val LSU_BUS_PRTY           = 	0x2
+  val LSU_BUS_TAG            = 	0x3
+  val LSU_NUM_NBLOAD         = 	0x04
+  val LSU_NUM_NBLOAD_WIDTH   = 	0x2
+  val LSU_SB_BITS            = 	0x10
+  val LSU_STBUF_DEPTH        = 	0x4
+  val NO_ICCM_NO_ICACHE      = 	0x0
+  val PIC_2CYCLE             = 	0x0
+  val PIC_BASE_ADDR          = 	0xF00C0000
+  val PIC_BITS               = 	0x0F
+  val PIC_INT_WORDS          = 	0x1
+  val PIC_REGION             = 	0xF
+  val PIC_SIZE               = 	0x020
+  val PIC_TOTAL_INT          = 	0x1F
+  val PIC_TOTAL_INT_PLUS1    = 	0x020
+  val RET_STACK_SIZE         = 	0x8
+  val SB_BUS_ID              = 	0x1
+  val SB_BUS_PRTY            = 	0x2
+  val SB_BUS_TAG             = 	0x1
+  val TIMER_LEGAL_EN         = 	0x1
+}

src/main/scala/lsu/lsu.scala

@@ -6,7 +6,7 @@ import chisel3.util._
 import include._
 import mem._
 
-class lsu extends Module with RequireAsyncReset with param with lib {
+class lsu extends Module with RequireAsyncReset with lib {
   val io = IO (new Bundle {
     val clk_override                      = Input(Bool())
     val lsu_dma = new lsu_dma
@@ -319,6 +319,6 @@ class lsu extends Module with RequireAsyncReset with param with lib {
   withClock(clkdomain.io.lsu_c2_r_clk){lsu_raw_fwd_lo_r := RegNext(lsu_raw_fwd_lo_m,0.U)}
 
 }
-object lsu_top extends App {
+//object lsu_top extends App {
-  println((new chisel3.stage.ChiselStage).emitVerilog(new lsu()))
+ // println((new chisel3.stage.ChiselStage).emitVerilog(new lsu()))
-}
+//}

src/main/scala/lsu/lsu_bus_buffer.scala

@@ -618,6 +618,6 @@ class  lsu_bus_buffer extends Module with RequireAsyncReset with lib {
   lsu_nonblock_load_valid_r := withClock(io.lsu_c2_r_clk){RegNext(io.dctl_busbuff.lsu_nonblock_load_valid_m, false.B)}
 }
 
-object bus_buffer extends App {
+//object bus_buffer extends App {
-  println((new chisel3.stage.ChiselStage).emitVerilog(new lsu_bus_buffer()))
+//  println((new chisel3.stage.ChiselStage).emitVerilog(new lsu_bus_buffer()))
-}
+//}

src/main/scala/mem.scala

@@ -28,37 +28,6 @@ class Mem_bundle extends Bundle with lib {
   val iccm = Flipped(new iccm_mem())
   val ic = Flipped (new ic_mem())
   val scan_mode = Input(Bool())
- // val iccm_rw_addr = Input(UInt((ICCM_BITS-1).W))
- // val iccm_buf_correct_ecc = Input(Bool())
- // val iccm_correction_state = Input(Bool())
-//  val iccm_wren = Input(Bool())
-//  val iccm_rden = Input(Bool())
-//  val iccm_wr_size = Input(UInt(3.W))
- // val iccm_wr_data = Input(UInt(78.W))
- // val ic_rw_addr = Input(UInt(31.W))
- // val ic_tag_valid = Input(UInt(ICACHE_NUM_WAYS.W))
- // val ic_wr_en = Input(UInt(ICACHE_NUM_WAYS.W))
- // val ic_rd_en = Input(Bool())
- // val ic_premux_data = Input(UInt(64.W))
-//  val ic_sel_premux_data = Input(Bool())
- // val ic_wr_data = Input(Vec(ICACHE_BANKS_WAY, UInt(71.W)))
- // val ic_debug_wr_data = Input(UInt(71.W))
- // val ic_debug_addr = Input(UInt((ICACHE_INDEX_HI-2).W))
- // val ic_debug_rd_en = Input(Bool())
- // val ic_debug_wr_en = Input(Bool())
-//  val ic_debug_tag_array = Input(Bool())
- // val ic_debug_way = Input(UInt(ICACHE_NUM_WAYS.W))
-//  val scan_mode = Input(Bool())
-//  val iccm_rd_data_ecc = Output(UInt(78.W))
-//  val ic_rd_data = Output(UInt(64.W))
- // val ictag_debug_rd_data = Output(UInt(26.W))
-//  val ic_eccerr = Output(UInt(ICACHE_BANKS_WAY.W))
-//  val ic_parerr = Output(UInt(ICACHE_BANKS_WAY.W))
-//  val ic_rd_hit = Output(UInt(ICACHE_NUM_WAYS.W))
- // val ic_tag_perr = Output(Bool())
- // val ic_debug_rd_data = Output(UInt(71.W))
- // val iccm_rd_data = Output(UInt(64.W))
-
 }
 object quasar extends lib {
   class mem extends BlackBox(Map("DCCM_BITS" -> DCCM_BITS,
@@ -67,16 +36,16 @@ object quasar extends lib {
     "ICACHE_NUM_WAYS" -> ICACHE_NUM_WAYS,
     "ICACHE_BANKS_WAY" -> ICACHE_BANKS_WAY,
     "ICACHE_INDEX_HI" -> ICACHE_INDEX_HI,
-    "DCCM_ENABLE" -> bool2int(DCCM_ENABLE),
+    "DCCM_ENABLE" -> DCCM_ENABLE,
-    "ICACHE_ENABLE" -> bool2int(ICCM_ENABLE),
+    "ICACHE_ENABLE" -> ICCM_ENABLE,
-    "ICCM_ENABLE" -> bool2int(ICCM_ENABLE),
+    "ICCM_ENABLE" -> ICCM_ENABLE,
     "ICACHE_TAG_INDEX_LO" -> ICACHE_TAG_INDEX_LO,
     "ICACHE_DATA_INDEX_LO" -> ICACHE_DATA_INDEX_LO,
     "ICACHE_TAG_LO" -> ICACHE_TAG_LO,
     "ICACHE_BANK_LO" -> ICACHE_BANK_LO,
     "ICACHE_BANK_HI" -> ICACHE_BANK_HI,
-    "ICACHE_WAYPACK" -> bool2int(ICACHE_WAYPACK),
+    "ICACHE_WAYPACK" -> ICACHE_WAYPACK,
-    "ICACHE_ECC" -> bool2int(ICACHE_ECC),
+    "ICACHE_ECC" -> ICACHE_ECC,
     "ICACHE_DATA_DEPTH" -> ICACHE_DATA_DEPTH,
     "ICACHE_BANK_BITS" -> ICACHE_BANK_BITS,
     "ICACHE_BEAT_ADDR_HI" -> ICACHE_BEAT_ADDR_HI,
@@ -99,8 +68,4 @@ class blackbox_mem extends Module with lib {
   val io = IO(new Mem_bundle)
   val it = Module(new quasar.mem)
   io <> it.io
-}
+}
-
-object mem extends App {
-  println((new chisel3.stage.ChiselStage).emitVerilog(new blackbox_mem))
-}

src/main/scala/pic_ctrl.scala

@@ -165,7 +165,7 @@ class pic_ctrl extends Module with RequireAsyncReset with lib {
 
 
 
-  if (PIC_2CYCLE == 1) {
+  if (PIC_2CYCLE) {
     val level_intpend_w_prior_en = Wire(Vec((NUM_LEVELS/2)+1, Vec(PIC_TOTAL_INT_PLUS1+3, UInt(INTPRIORITY_BITS.W))))  //PIC_TOTAL_INT_PLUS1+3 should be there
     val level_intpend_id = Wire(Vec((NUM_LEVELS/2)+1, Vec(PIC_TOTAL_INT_PLUS1+3, UInt(ID_BITS.W)))) //PIC_TOTAL_INT_PLUS1+3 should be there
     for(i<-0 until (NUM_LEVELS/2)+1; j<-0 until  PIC_TOTAL_INT_PLUS1+3){ //PIC_TOTAL_INT_PLUS1+3 should be there
@@ -406,7 +406,6 @@ class pic_ctrl extends Module with RequireAsyncReset with lib {
 
 }
 
-object pic_main extends App{
+//object pic_gen extends App {
-  println("Generating Verilog...")
+//  println((new chisel3.stage.ChiselStage).emitVerilog(new pic_ctrl()))
-  println((new chisel3.stage.ChiselStage).emitVerilog(new pic_ctrl()))
+//}
-}

src/main/scala/snapshot/el2_param.scala

@@ -1,158 +0,0 @@
-package snapshot
-import chisel3._
-
-object pt{
-  val BHT_ADDR_HI            = "h9".U(4.W)
-  val BHT_ADDR_LO            = "h2".U(2.W)
-  val BHT_ARRAY_DEPTH        = "h100".U(11.W)
-  val BHT_GHR_HASH_1         = "h0".U(1.W)
-  val BHT_GHR_SIZE           = "8h".U(4.W)
-  val BHT_SIZE               = "h200".U(12.W)
-  val BTB_ADDR_HI            = "h09".U(5.W)
-  val BTB_ADDR_LO            = "h2".U(2.W)
-  val BTB_ARRAY_DEPTH        = "h100".U(9.W)
-  val BTB_BTAG_FOLD          = "h0".U(1.W)
-  val BTB_BTAG_SIZE          = "h5".U(4.W)
-  val BTB_FOLD2_INDEX_HASH   = "h0".U(1.W)
-  val BTB_INDEX1_HI          = "h09".U(5.W)
-  val BTB_INDEX1_LO          = "h02".U(5.W)
-  val BTB_INDEX2_HI          = "h11".U(5.W)
-  val BTB_INDEX2_LO          = "h0A".U(5.W)
-  val BTB_INDEX3_HI          = "h19".U(5.W)
-  val BTB_INDEX3_LO          = "h12".U(5.W)
-  val BTB_SIZE               = "h200".U(10.W)
-  val BUILD_AHB_LITE         = "h0".U(1.W)
-  val BUILD_AXI4             = "h1".U(1.W)
-  val BUILD_AXI_NATIVE       = "h1".U(1.W)
-  val BUS_PRTY_DEFAULT       = "h3".U(2.W)
-  val DATA_ACCESS_ADDR0      = "h00000000".U(32.W)
-  val DATA_ACCESS_ADDR1      = "hC0000000".U(32.W)
-  val DATA_ACCESS_ADDR2      = "hA0000000".U(32.W)
-  val DATA_ACCESS_ADDR3      = "h80000000".U(32.W)
-  val DATA_ACCESS_ADDR4      = "h00000000".U(32.W)
-  val DATA_ACCESS_ADDR5      = "h00000000".U(32.W)
-  val DATA_ACCESS_ADDR6      = "h00000000".U(32.W)
-  val DATA_ACCESS_ADDR7      = "h00000000".U(32.W)
-  val DATA_ACCESS_ENABLE0    = "h1".U(1.W)
-  val DATA_ACCESS_ENABLE1    = "h1".U(1.W)
-  val DATA_ACCESS_ENABLE2    = "h1".U(1.W)
-  val DATA_ACCESS_ENABLE3    = "h1".U(1.W)
-  val DATA_ACCESS_ENABLE4    = "h0".U(1.W)
-  val DATA_ACCESS_ENABLE5    = "h0".U(1.W)
-  val DATA_ACCESS_ENABLE6    = "h0".U(1.W)
-  val DATA_ACCESS_ENABLE7    = "h0".U(1.W)
-  val DATA_ACCESS_MASK0      = "h7FFFFFFF".U(32.W)
-  val DATA_ACCESS_MASK1      = "h3FFFFFFF".U(32.W)
-  val DATA_ACCESS_MASK2      = "h1FFFFFFF".U(32.W)
-  val DATA_ACCESS_MASK3      = "h0FFFFFFF".U(32.W)
-  val DATA_ACCESS_MASK4      = "hFFFFFFFF".U(32.W)
-  val DATA_ACCESS_MASK5      = "hFFFFFFFF".U(32.W)
-  val DATA_ACCESS_MASK6      = "hFFFFFFFF".U(32.W)
-  val DATA_ACCESS_MASK7      = "hFFFFFFFF".U(32.W)
-  val DCCM_BANK_BITS         = "h2".U(3.W)
-  val DCCM_BITS              = "h10".U(5.W)
-  val DCCM_BYTE_WIDTH        = "h4".U(3.W)
-  val DCCM_DATA_WIDTH        = "h20".U(6.W)
-  val DCCM_ECC_WIDTH         = "h7".U(3.W)
-  val DCCM_ENABLE            = "h1".U(1.W)
-  val DCCM_FDATA_WIDTH       = "h27".U(6.W)
-  val DCCM_INDEX_BITS        = "hC".U(4.W)
-  val DCCM_NUM_BANKS         = "h04".U(5.W)
-  val DCCM_REGION            = "hF".U(4.W)
-  val DCCM_SADR              = "hF0040000".U(32.W)
-  val DCCM_SIZE              = "h040".U(10.W)
-  val DCCM_WIDTH_BITS        = "h2".U(2.W)
-  val DMA_BUF_DEPTH          = "h5".U(3.W)
-  val DMA_BUS_ID             = "h1".U(1.W)
-  val DMA_BUS_PRTY           = "h2".U(2.W)
-  val DMA_BUS_TAG            = "h1".U(4.W)
-  val FAST_INTERRUPT_REDIRECT= "h1".U(1.W)
-  val ICACHE_2BANKS          = "h1".U(1.W)
-  val ICACHE_BANK_BITS       = "h1".U(3.W)
-  val ICACHE_BANK_HI         = "h3".U(3.W)
-  val ICACHE_BANK_LO         = "h3".U(2.W)
-  val ICACHE_BANK_WIDTH      = "h8".U(4.W)
-  val ICACHE_BANKS_WAY       = "h2".U(3.W)
-  val ICACHE_BEAT_ADDR_HI    = "h5".U(4.W)
-  val ICACHE_BEAT_BITS       = "h3".U(4.W)
-  val ICACHE_DATA_DEPTH      = "h0200".U(14.W)
-  val ICACHE_DATA_INDEX_LO   = "h4".U(3.W)
-  val ICACHE_DATA_WIDTH      = "h40".U(7.W)
-  val ICACHE_ECC             = "h1".U(1.W)
-  val ICACHE_ENABLE          = "h1".U(1.W)
-  val ICACHE_FDATA_WIDTH     = "h47".U(7.W)
-  val ICACHE_INDEX_HI        = "h0C".U(5.W)
-  val ICACHE_LN_SZ           = "h40".U(7.W)
-  val ICACHE_NUM_BEATS       = "h8".U(4.W)
-  val ICACHE_NUM_WAYS        = "h2".U(3.W)
-  val ICACHE_ONLY            = "h0".U(1.W)
-  val ICACHE_SCND_LAST       = "h6".U(4.W)
-  val ICACHE_SIZE            = "h010".U(9.W)
-  val ICACHE_STATUS_BITS     = "h1".U(3.W)
-  val ICACHE_TAG_DEPTH       = "h0080".U(13.W)
-  val ICACHE_TAG_INDEX_LO    = "h6".U(3.W)
-  val ICACHE_TAG_LO          = "h0D".U(5.W)
-  val ICACHE_WAYPACK         = "h0".U(1.W)
-  val ICCM_BANK_BITS         = "h2".U(3.W)
-  val ICCM_BANK_HI           = "h03".U(5.W)
-  val ICCM_BANK_INDEX_LO     = "h04".U(5.W)
-  val ICCM_BITS              = "h10".U(5.W)
-  val ICCM_ENABLE            = "h1".U(1.W)
-  val ICCM_ICACHE            = "h1".U(1.W)
-  val ICCM_INDEX_BITS        = "hC".U(4.W)
-  val ICCM_NUM_BANKS         = "h04".U(5.W)
-  val ICCM_ONLY              = "h0".U(1.W)
-  val ICCM_REGION            = "hE".U(4.W)
-  val ICCM_SADR              = "hEE000000".U(32.W)
-  val ICCM_SIZE              = "h040".U(10.W)
-  val IFU_BUS_ID             = "h1".U(1.W)
-  val IFU_BUS_PRTY           = "h2".U(2.W)
-  val IFU_BUS_TAG            = "h3".U(4.W)
-  val INST_ACCESS_ADDR0      = "h00000000".U(32.W)
-  val INST_ACCESS_ADDR1      = "hC0000000".U(32.W)
-  val INST_ACCESS_ADDR2      = "hA0000000".U(32.W)
-  val INST_ACCESS_ADDR3      = "h80000000".U(32.W)
-  val INST_ACCESS_ADDR4      = "h00000000".U(32.W)
-  val INST_ACCESS_ADDR5      = "h00000000".U(32.W)
-  val INST_ACCESS_ADDR6      = "h00000000".U(32.W)
-  val INST_ACCESS_ADDR7      = "h00000000".U(32.W)
-  val INST_ACCESS_ENABLE0    = "h1".U(1.W)
-  val INST_ACCESS_ENABLE1    = "h1".U(1.W)
-  val INST_ACCESS_ENABLE2    = "h1".U(1.W)
-  val INST_ACCESS_ENABLE3    = "h1".U(1.W)
-  val INST_ACCESS_ENABLE4    = "h0".U(1.W)
-  val INST_ACCESS_ENABLE5    = "h0".U(1.W)
-  val INST_ACCESS_ENABLE6    = "h0".U(1.W)
-  val INST_ACCESS_ENABLE7    = "h0".U(1.W)
-  val INST_ACCESS_MASK0      = "h7FFFFFFF".U(32.W)
-  val INST_ACCESS_MASK1      = "h3FFFFFFF".U(32.W)
-  val INST_ACCESS_MASK2      = "h1FFFFFFF".U(32.W)
-  val INST_ACCESS_MASK3      = "h0FFFFFFF".U(32.W)
-  val INST_ACCESS_MASK4      = "hFFFFFFFF".U(32.W)
-  val INST_ACCESS_MASK5      = "hFFFFFFFF".U(32.W)
-  val INST_ACCESS_MASK6      = "hFFFFFFFF".U(32.W)
-  val INST_ACCESS_MASK7      = "hFFFFFFFF".U(32.W)
-  val LOAD_TO_USE_PLUS1      = "h0".U(1.W)
-  val LSU2DMA                = "h0".U(1.W)
-  val LSU_BUS_ID             = "h1".U(1.W)
-  val LSU_BUS_PRTY           = "h2".U(2.W)
-  val LSU_BUS_TAG            = "h3".U(4.W)
-  val LSU_NUM_NBLOAD         = "h04".U(5.W)
-  val LSU_NUM_NBLOAD_WIDTH   = "h2".U(3.W)
-  val LSU_SB_BITS            = "h10".U(5.W)
-  val LSU_STBUF_DEPTH        = "h4".U(4.W)
-  val NO_ICCM_NO_ICACHE      = "h0".U(1.W)
-  val PIC_2CYCLE             = "h0".U(1.W)
-  val PIC_BASE_ADDR          = "hF00C0000".U(32.W)
-  val PIC_BITS               = "h0F".U(5.W)
-  val PIC_INT_WORDS          = "h1".U(4.W)
-  val PIC_REGION             = "hF".U(4.W)
-  val PIC_SIZE               = "h020".U(9.W)
-  val PIC_TOTAL_INT          = "h1F".U(8.W)
-  val PIC_TOTAL_INT_PLUS1    = "h020".U(9.W)
-  val RET_STACK_SIZE         = "h8".U(4.W)
-  val SB_BUS_ID              = "h1".U(1.W)
-  val SB_BUS_PRTY            = "h2".U(2.W)
-  val SB_BUS_TAG             = "h1".U(4.W)
-  val TIMER_LEGAL_EN         = "h1".U(1.W)
-}