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Quasar updated

This commit is contained in:
​Laraib Khan 2021-02-09 12:12:03 +05:00
parent 11c09dc85b
commit 3b9f229475
117 changed files with 55609 additions and 41592 deletions
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5716
lsu.fir
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2126
lsu.v
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386
lsu_dccm_ctl.anno.json Normal file
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[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_wren",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_ld_single_ecc_error_r_ff",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_wen",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_stbuf_commit_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_reqvld_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_dccm_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_valid",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_load",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_store",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_addr_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_end_addr_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_word",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_dword"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_stbuf_commit_any",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_reqvld_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_ld_single_ecc_error_r_ff",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_dccm_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_wen",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_valid",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_load",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_store",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_addr_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_end_addr_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_word",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_dword"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_wr_data_lo",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_ld_single_ecc_error_r_ff",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_wen",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_sec_data_ecc_lo_r_ff",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_sec_data_lo_r_ff",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_sec_data_ecc_hi_r_ff",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_sec_data_hi_r_ff",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_wdata_ecc_lo",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_wdata_lo",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_ecc_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_data_any"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_ld_data_m",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_m",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_fwddata_hi_m",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_fwddata_lo_m",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_pic_m",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_fwdbyteen_hi_m",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_fwdbyteen_lo_m",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pic_picm_rd_data",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_dccm_m",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_rdata_hi_m",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_rdata_lo_m",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_rd_data_hi",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_rd_data_lo"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_ctl_dccm_dma_ecc_error",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_double_ecc_error_m"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pic_picm_wren",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_pic_wen",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_commit_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_pic_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_valid",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_store"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_wr_addr_hi",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_ld_single_ecc_error_r_ff",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_wen",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_end_addr_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_addr_any"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_picm_mask_data_m",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pic_picm_rd_data"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_data_ecc_lo_m",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_rd_data_lo"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_rdata_lo_m",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_rd_data_lo"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_store_datafn_lo_r",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_data_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_store_data_lo_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_stbuf_commit_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_dccm_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_reqvld_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_addr_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_ld_single_ecc_error_r_ff",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_dccm_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_wen",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_valid",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_load",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_store",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_store",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_end_addr_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_word",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_by",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_half",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_word",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_dword"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_ctl_dccm_dma_rdata",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_ldst_dual_m",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_fwddata_hi_m",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_fwddata_lo_m",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_pic_m",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_fwdbyteen_hi_m",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_fwdbyteen_lo_m",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pic_picm_rd_data",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_dccm_m",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_sec_data_hi_m",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_sec_data_lo_m"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pic_picm_rden",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_pic_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_valid",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_load"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_rdata_hi_m",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_rd_data_hi"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_ctl_dccm_dma_rtag",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_mem_tag_m"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_store_datafn_hi_r",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_data_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_store_data_hi_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_stbuf_commit_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_dccm_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_reqvld_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_addr_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_end_addr_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_ld_single_ecc_error_r_ff",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_dccm_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_wen",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_valid",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_load",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_store",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_store",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_end_addr_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_word",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_by",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_half",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_word",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_dword"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_data_ecc_hi_m",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_rd_data_hi"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_rden",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_dccm_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_valid",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_load",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_store",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_word",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_dword",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_store_data_r",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_store_data_hi_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_store_data_lo_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_store",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_word",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_by",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_half"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pic_picm_wraddr",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_pic_wen",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_ctl_dma_mem_addr",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_r"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_wr_data_hi",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_ld_single_ecc_error_r_ff",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_wen",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_sec_data_ecc_hi_r_ff",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_sec_data_hi_r_ff",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_sec_data_ecc_lo_r_ff",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_sec_data_lo_r_ff",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_wdata_ecc_hi",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_wdata_hi",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_ecc_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_data_any"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_rd_addr_lo",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_ctl_dccm_dma_rvalid",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_m_bits_dma",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_m_valid",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_m_bits_load"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pic_picm_mken",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_pic_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_valid",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_store"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_wr_addr_lo",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_ld_single_ecc_error_r_ff",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_wen",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_addr_any"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pic_picm_wr_data",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_pic_wen",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_ctl_dma_mem_wdata",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_store_datafn_lo_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_data_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_store_data_lo_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_stbuf_commit_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_dccm_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_reqvld_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_stbuf_addr_any",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_ld_single_ecc_error_r_ff",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_addr_in_dccm_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_dma_dccm_wen",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_valid",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_load",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_store",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_store",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_end_addr_d",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_word",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_by",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_half",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_word",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_d_bits_dword"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pic_picm_rdaddr",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_addr_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_dccm_rd_addr_hi",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_end_addr_d"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~lsu_dccm_ctl|lsu_dccm_ctl>io_ld_single_ecc_error_r",
"sources":[
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_double_ecc_error_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_pkt_r_bits_load",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_single_ecc_error_lo_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_raw_fwd_lo_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_single_ecc_error_hi_r",
"~lsu_dccm_ctl|lsu_dccm_ctl>io_lsu_raw_fwd_hi_r"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"lsu_dccm_ctl.gated_latch",
"resourceId":"/vsrc/gated_latch.sv"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"lsu_dccm_ctl"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

2262
lsu_dccm_ctl.fir Normal file
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File diff suppressed because it is too large Load Diff

1291
lsu_dccm_ctl.v Normal file
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File diff suppressed because it is too large Load Diff

974
pic_ctrl.anno.json Normal file
View File

@ -0,0 +1,974 @@
[
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>selected_int_priority"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_4_2"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_4_0"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_3_4"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_3_2"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_3_0"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_2_8"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_2_6"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_2_4"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_2_2"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_2_0"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_1_16"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_1_14"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_1_12"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_1_10"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_1_8"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_1_6"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_1_4"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_1_2"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_1_0"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_0_32"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_0_30"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_0_28"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_0_26"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_0_24"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_0_22"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_0_20"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_0_18"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_0_16"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_0_14"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_0_12"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_0_10"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_0_8"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_0_6"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_0_4"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_0_2"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_0_0"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_w_prior_en_0_0"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_w_prior_en_0_1"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_w_prior_en_0_2"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_w_prior_en_0_3"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_w_prior_en_0_4"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_w_prior_en_0_5"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_w_prior_en_0_6"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_w_prior_en_0_7"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_w_prior_en_0_8"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_w_prior_en_0_9"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_w_prior_en_0_10"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_w_prior_en_0_11"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_w_prior_en_0_12"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_w_prior_en_0_13"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_w_prior_en_0_14"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_w_prior_en_0_15"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_w_prior_en_0_16"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_w_prior_en_0_17"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_w_prior_en_0_18"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_w_prior_en_0_19"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_w_prior_en_0_20"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_w_prior_en_0_21"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_w_prior_en_0_22"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_w_prior_en_0_23"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_w_prior_en_0_24"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_w_prior_en_0_25"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_w_prior_en_0_26"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_w_prior_en_0_27"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_w_prior_en_0_28"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_w_prior_en_0_29"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_w_prior_en_0_30"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_w_prior_en_0_31"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_w_prior_en_0_32"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_w_prior_en_0_33"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_0_1"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_0_3"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_0_5"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_0_7"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_0_9"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_0_11"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_0_13"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_0_15"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_0_17"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_0_19"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_0_21"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_0_23"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_0_25"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_0_27"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_0_29"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_0_31"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_0_33"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_1_1"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_1_3"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_1_5"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_1_7"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_1_9"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_1_11"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_1_13"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_1_15"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_1_17"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_1_18"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_1_19"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_1_20"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_1_21"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_1_22"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_1_23"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_1_24"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_1_25"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_1_26"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_1_27"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_1_28"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_1_29"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_1_30"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_1_31"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_1_32"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_1_33"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_2_1"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_2_3"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_2_5"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_2_7"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_2_9"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_2_10"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_2_11"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_2_12"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_2_13"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_2_14"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_2_15"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_2_16"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_2_17"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_2_18"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_2_19"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_2_20"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_2_21"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_2_22"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_2_23"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_2_24"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_2_25"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_2_26"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_2_27"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_2_28"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_2_29"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_2_30"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_2_31"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_2_32"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_2_33"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_3_1"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_3_3"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_3_5"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_3_6"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_3_7"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_3_8"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_3_9"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_3_10"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_3_11"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_3_12"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_3_13"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_3_14"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_3_15"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_3_16"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_3_17"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_3_18"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_3_19"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_3_20"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_3_21"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_3_22"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_3_23"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_3_24"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_3_25"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_3_26"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_3_27"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_3_28"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_3_29"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_3_30"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_3_31"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_3_32"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_3_33"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_4_1"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_4_3"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_4_4"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_4_5"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_4_6"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_4_7"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_4_8"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_4_9"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_4_10"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_4_11"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_4_12"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_4_13"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_4_14"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_4_15"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_4_16"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_4_17"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_4_18"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_4_19"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_4_20"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_4_21"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_4_22"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_4_23"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_4_24"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_4_25"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_4_26"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_4_27"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_4_28"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_4_29"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_4_30"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_4_31"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_4_32"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_4_33"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_5_0"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_5_1"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_5_2"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_5_3"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_5_4"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_5_5"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_5_6"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_5_7"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_5_8"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_5_9"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_5_10"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_5_11"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_5_12"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_5_13"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_5_14"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_5_15"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_5_16"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_5_17"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_5_18"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_5_19"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_5_20"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_5_21"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_5_22"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_5_23"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_5_24"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_5_25"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_5_26"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_5_27"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_5_28"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_5_29"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_5_30"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_5_31"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_5_32"
},
{
"class":"firrtl.transforms.DontTouchAnnotation",
"target":"~pic_ctrl|pic_ctrl>level_intpend_id_5_33"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"pic_ctrl"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

4782
pic_ctrl.fir Normal file
View File

File diff suppressed because it is too large Load Diff

4532
pic_ctrl.v Normal file
View File

File diff suppressed because it is too large Load Diff

269
quasar.anno.json
View File

@ -1,32 +1,4 @@
[ [
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~quasar|quasar>io_iccm_wr_data",
"sources":[
"~quasar|quasar>io_iccm_rd_data_ecc",
"~quasar|quasar>io_ic_rd_hit",
"~quasar|quasar>io_ic_rd_data",
"~quasar|quasar>io_ifu_axi_r_bits_id",
"~quasar|quasar>io_ifu_axi_r_valid",
"~quasar|quasar>io_ifu_bus_clk_en",
"~quasar|quasar>io_mpc_reset_run_req",
"~quasar|quasar>io_dccm_rd_data_hi",
"~quasar|quasar>io_dccm_rd_data_lo",
"~quasar|quasar>io_rst_vec",
"~quasar|quasar>io_nmi_vec",
"~quasar|quasar>io_extintsrc_req"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~quasar|quasar>io_dccm_rd_addr_lo",
"sources":[
"~quasar|quasar>io_dccm_rd_data_hi",
"~quasar|quasar>io_dccm_rd_data_lo",
"~quasar|quasar>io_mpc_reset_run_req",
"~quasar|quasar>io_extintsrc_req"
]
},
{ {
"class":"firrtl.transforms.CombinationalPath", "class":"firrtl.transforms.CombinationalPath",
"sink":"~quasar|quasar>io_iccm_wren", "sink":"~quasar|quasar>io_iccm_wren",
@ -41,86 +13,7 @@
"~quasar|quasar>io_dccm_rd_data_hi", "~quasar|quasar>io_dccm_rd_data_hi",
"~quasar|quasar>io_dccm_rd_data_lo", "~quasar|quasar>io_dccm_rd_data_lo",
"~quasar|quasar>io_rst_vec", "~quasar|quasar>io_rst_vec",
"~quasar|quasar>io_nmi_vec", "~quasar|quasar>io_nmi_vec"
"~quasar|quasar>io_extintsrc_req"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~quasar|quasar>io_dccm_rd_addr_hi",
"sources":[
"~quasar|quasar>io_dccm_rd_data_hi",
"~quasar|quasar>io_dccm_rd_data_lo",
"~quasar|quasar>io_mpc_reset_run_req",
"~quasar|quasar>io_extintsrc_req"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~quasar|quasar>io_ic_rw_addr",
"sources":[
"~quasar|quasar>io_ic_rd_hit",
"~quasar|quasar>io_mpc_reset_run_req",
"~quasar|quasar>io_rst_vec",
"~quasar|quasar>io_nmi_vec",
"~quasar|quasar>io_dccm_rd_data_hi",
"~quasar|quasar>io_dccm_rd_data_lo",
"~quasar|quasar>io_extintsrc_req"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~quasar|quasar>io_dccm_wren",
"sources":[
"~quasar|quasar>io_dccm_rd_data_hi",
"~quasar|quasar>io_dccm_rd_data_lo",
"~quasar|quasar>io_mpc_reset_run_req",
"~quasar|quasar>io_extintsrc_req"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~quasar|quasar>io_dccm_wr_addr_lo",
"sources":[
"~quasar|quasar>io_dccm_rd_data_hi",
"~quasar|quasar>io_dccm_rd_data_lo",
"~quasar|quasar>io_mpc_reset_run_req",
"~quasar|quasar>io_extintsrc_req"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~quasar|quasar>io_iccm_wr_size",
"sources":[
"~quasar|quasar>io_iccm_rd_data_ecc",
"~quasar|quasar>io_ic_rd_hit",
"~quasar|quasar>io_ic_rd_data",
"~quasar|quasar>io_ifu_axi_r_bits_id",
"~quasar|quasar>io_ifu_axi_r_valid",
"~quasar|quasar>io_ifu_bus_clk_en",
"~quasar|quasar>io_mpc_reset_run_req",
"~quasar|quasar>io_dccm_rd_data_hi",
"~quasar|quasar>io_dccm_rd_data_lo",
"~quasar|quasar>io_rst_vec",
"~quasar|quasar>io_nmi_vec",
"~quasar|quasar>io_extintsrc_req"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~quasar|quasar>io_active_l2clk",
"sources":[
"~quasar|quasar>clock"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~quasar|quasar>io_dccm_rden",
"sources":[
"~quasar|quasar>io_dccm_rd_data_hi",
"~quasar|quasar>io_dccm_rd_data_lo",
"~quasar|quasar>io_mpc_reset_run_req",
"~quasar|quasar>io_extintsrc_req"
] ]
}, },
{ {
@ -136,24 +29,17 @@
"~quasar|quasar>io_mpc_reset_run_req", "~quasar|quasar>io_mpc_reset_run_req",
"~quasar|quasar>io_rst_vec", "~quasar|quasar>io_rst_vec",
"~quasar|quasar>io_nmi_vec", "~quasar|quasar>io_nmi_vec",
"~quasar|quasar>io_dccm_rd_data_hi",
"~quasar|quasar>io_dccm_rd_data_lo"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~quasar|quasar>io_dccm_wr_addr_lo",
"sources":[
"~quasar|quasar>io_dccm_rd_data_hi", "~quasar|quasar>io_dccm_rd_data_hi",
"~quasar|quasar>io_dccm_rd_data_lo", "~quasar|quasar>io_dccm_rd_data_lo",
"~quasar|quasar>io_extintsrc_req" "~quasar|quasar>io_mpc_reset_run_req"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~quasar|quasar>io_core_rst_l",
"sources":[
"~quasar|quasar>reset",
"~quasar|quasar>io_scan_mode"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~quasar|quasar>io_free_l2clk",
"sources":[
"~quasar|quasar>clock"
] ]
}, },
{ {
@ -162,8 +48,34 @@
"sources":[ "sources":[
"~quasar|quasar>io_dccm_rd_data_hi", "~quasar|quasar>io_dccm_rd_data_hi",
"~quasar|quasar>io_dccm_rd_data_lo", "~quasar|quasar>io_dccm_rd_data_lo",
"~quasar|quasar>io_mpc_reset_run_req", "~quasar|quasar>io_mpc_reset_run_req"
"~quasar|quasar>io_extintsrc_req" ]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~quasar|quasar>io_dccm_rd_addr_hi",
"sources":[
"~quasar|quasar>io_dccm_rd_data_hi",
"~quasar|quasar>io_dccm_rd_data_lo",
"~quasar|quasar>io_mpc_reset_run_req"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~quasar|quasar>io_dccm_rden",
"sources":[
"~quasar|quasar>io_dccm_rd_data_hi",
"~quasar|quasar>io_dccm_rd_data_lo",
"~quasar|quasar>io_mpc_reset_run_req"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~quasar|quasar>io_dccm_wren",
"sources":[
"~quasar|quasar>io_dccm_rd_data_hi",
"~quasar|quasar>io_dccm_rd_data_lo",
"~quasar|quasar>io_mpc_reset_run_req"
] ]
}, },
{ {
@ -177,25 +89,78 @@
"~quasar|quasar>io_ifu_bus_clk_en", "~quasar|quasar>io_ifu_bus_clk_en",
"~quasar|quasar>io_mpc_reset_run_req", "~quasar|quasar>io_mpc_reset_run_req",
"~quasar|quasar>io_dccm_rd_data_hi", "~quasar|quasar>io_dccm_rd_data_hi",
"~quasar|quasar>io_dccm_rd_data_lo", "~quasar|quasar>io_dccm_rd_data_lo"
"~quasar|quasar>io_extintsrc_req"
] ]
}, },
{ {
"class":"firrtl.transforms.CombinationalPath", "class":"firrtl.transforms.CombinationalPath",
"sink":"~quasar|quasar>io_ic_rd_en", "sink":"~quasar|quasar>io_dccm_rd_addr_lo",
"sources":[ "sources":[
"~quasar|quasar>io_dccm_rd_data_hi",
"~quasar|quasar>io_dccm_rd_data_lo",
"~quasar|quasar>io_mpc_reset_run_req"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~quasar|quasar>io_dccm_wr_data_lo",
"sources":[
"~quasar|quasar>io_dccm_rd_data_hi",
"~quasar|quasar>io_dccm_rd_data_lo",
"~quasar|quasar>io_mpc_reset_run_req"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~quasar|quasar>io_dccm_wr_data_hi",
"sources":[
"~quasar|quasar>io_dccm_rd_data_hi",
"~quasar|quasar>io_dccm_rd_data_lo",
"~quasar|quasar>io_mpc_reset_run_req"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~quasar|quasar>io_active_l2clk",
"sources":[
"~quasar|quasar>clock"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~quasar|quasar>io_ic_rw_addr",
"sources":[
"~quasar|quasar>io_ic_rd_hit",
"~quasar|quasar>io_mpc_reset_run_req",
"~quasar|quasar>io_rst_vec",
"~quasar|quasar>io_nmi_vec",
"~quasar|quasar>io_dccm_rd_data_hi",
"~quasar|quasar>io_dccm_rd_data_lo"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~quasar|quasar>io_iccm_wr_size",
"sources":[
"~quasar|quasar>io_iccm_rd_data_ecc",
"~quasar|quasar>io_ic_rd_hit", "~quasar|quasar>io_ic_rd_hit",
"~quasar|quasar>io_ic_rd_data", "~quasar|quasar>io_ic_rd_data",
"~quasar|quasar>io_ifu_axi_r_bits_id", "~quasar|quasar>io_ifu_axi_r_bits_id",
"~quasar|quasar>io_ifu_axi_r_valid", "~quasar|quasar>io_ifu_axi_r_valid",
"~quasar|quasar>io_ifu_bus_clk_en", "~quasar|quasar>io_ifu_bus_clk_en",
"~quasar|quasar>io_mpc_reset_run_req", "~quasar|quasar>io_mpc_reset_run_req",
"~quasar|quasar>io_rst_vec",
"~quasar|quasar>io_nmi_vec",
"~quasar|quasar>io_dccm_rd_data_hi", "~quasar|quasar>io_dccm_rd_data_hi",
"~quasar|quasar>io_dccm_rd_data_lo", "~quasar|quasar>io_dccm_rd_data_lo",
"~quasar|quasar>io_extintsrc_req" "~quasar|quasar>io_rst_vec",
"~quasar|quasar>io_nmi_vec"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~quasar|quasar>io_core_rst_l",
"sources":[
"~quasar|quasar>reset",
"~quasar|quasar>io_scan_mode"
] ]
}, },
{ {
@ -208,8 +173,7 @@
"~quasar|quasar>io_ifu_bus_clk_en", "~quasar|quasar>io_ifu_bus_clk_en",
"~quasar|quasar>io_mpc_reset_run_req", "~quasar|quasar>io_mpc_reset_run_req",
"~quasar|quasar>io_dccm_rd_data_hi", "~quasar|quasar>io_dccm_rd_data_hi",
"~quasar|quasar>io_dccm_rd_data_lo", "~quasar|quasar>io_dccm_rd_data_lo"
"~quasar|quasar>io_extintsrc_req"
] ]
}, },
{ {
@ -226,28 +190,47 @@
"~quasar|quasar>io_rst_vec", "~quasar|quasar>io_rst_vec",
"~quasar|quasar>io_nmi_vec", "~quasar|quasar>io_nmi_vec",
"~quasar|quasar>io_dccm_rd_data_hi", "~quasar|quasar>io_dccm_rd_data_hi",
"~quasar|quasar>io_dccm_rd_data_lo", "~quasar|quasar>io_dccm_rd_data_lo"
"~quasar|quasar>io_extintsrc_req"
] ]
}, },
{ {
"class":"firrtl.transforms.CombinationalPath", "class":"firrtl.transforms.CombinationalPath",
"sink":"~quasar|quasar>io_dccm_wr_data_hi", "sink":"~quasar|quasar>io_free_l2clk",
"sources":[ "sources":[
"~quasar|quasar>io_dccm_rd_data_hi", "~quasar|quasar>clock"
"~quasar|quasar>io_dccm_rd_data_lo",
"~quasar|quasar>io_mpc_reset_run_req",
"~quasar|quasar>io_extintsrc_req"
] ]
}, },
{ {
"class":"firrtl.transforms.CombinationalPath", "class":"firrtl.transforms.CombinationalPath",
"sink":"~quasar|quasar>io_dccm_wr_data_lo", "sink":"~quasar|quasar>io_iccm_wr_data",
"sources":[ "sources":[
"~quasar|quasar>io_iccm_rd_data_ecc",
"~quasar|quasar>io_ic_rd_hit",
"~quasar|quasar>io_ic_rd_data",
"~quasar|quasar>io_ifu_axi_r_bits_id",
"~quasar|quasar>io_ifu_axi_r_valid",
"~quasar|quasar>io_ifu_bus_clk_en",
"~quasar|quasar>io_mpc_reset_run_req",
"~quasar|quasar>io_dccm_rd_data_hi", "~quasar|quasar>io_dccm_rd_data_hi",
"~quasar|quasar>io_dccm_rd_data_lo", "~quasar|quasar>io_dccm_rd_data_lo",
"~quasar|quasar>io_rst_vec",
"~quasar|quasar>io_nmi_vec"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~quasar|quasar>io_ic_rd_en",
"sources":[
"~quasar|quasar>io_ic_rd_hit",
"~quasar|quasar>io_ic_rd_data",
"~quasar|quasar>io_ifu_axi_r_bits_id",
"~quasar|quasar>io_ifu_axi_r_valid",
"~quasar|quasar>io_ifu_bus_clk_en",
"~quasar|quasar>io_mpc_reset_run_req", "~quasar|quasar>io_mpc_reset_run_req",
"~quasar|quasar>io_extintsrc_req" "~quasar|quasar>io_rst_vec",
"~quasar|quasar>io_nmi_vec",
"~quasar|quasar>io_dccm_rd_data_hi",
"~quasar|quasar>io_dccm_rd_data_lo"
] ]
}, },
{ {

49134
quasar.fir
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File diff suppressed because it is too large Load Diff

24750
quasar.v
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File diff suppressed because it is too large Load Diff

15
src/main/scala/ifu/ifu.scala
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@ -76,7 +76,21 @@ class ifu extends Module with lib with RequireAsyncReset {
aln_ctl.io.ifu_bp_ret_f := bp_ctl.io.ifu_bp_ret_f aln_ctl.io.ifu_bp_ret_f := bp_ctl.io.ifu_bp_ret_f
aln_ctl.io.exu_flush_final := io.exu_flush_final aln_ctl.io.exu_flush_final := io.exu_flush_final
aln_ctl.io.dec_aln <> io.ifu_dec.dec_aln aln_ctl.io.dec_aln <> io.ifu_dec.dec_aln
// io.ifu_dec.dec_aln.aln_dec.ifu_i0_cinst := aln_ctl.io.ifu_i0_cinst
// io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf := aln_ctl.io.ifu_i0_icaf
// io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_type := aln_ctl.io.ifu_i0_icaf_type
// io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_second := aln_ctl.io.ifu_i0_icaf_second
// io.ifu_dec.dec_aln.aln_ib.ifu_i0_dbecc := aln_ctl.io.ifu_i0_dbecc
// io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_index := aln_ctl.io.ifu_i0_bp_index
io.ifu_i0_fa_index := aln_ctl.io.ifu_i0_fa_index io.ifu_i0_fa_index := aln_ctl.io.ifu_i0_fa_index
// io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_fghr := aln_ctl.io.ifu_i0_bp_fghr
// io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_btag := aln_ctl.io.ifu_i0_bp_btag
// io.ifu_dec.dec_aln.aln_ib.ifu_i0_valid := aln_ctl.io.ifu_i0_valid
// io.ifu_dec.dec_aln.aln_ib.ifu_i0_instr := aln_ctl.io.ifu_i0_instr
// io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc := aln_ctl.io.ifu_i0_pc
// io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc4 := aln_ctl.io.ifu_i0_pc4
// io.ifu_dec.dec_aln.ifu_pmu_instr_aligned := aln_ctl.io.ifu_pmu_instr_aligned
// aln_ctl.io.i0_brp <> io.ifu_dec.dec_aln.aln_ib.i0_brp
aln_ctl.io.dec_i0_decode_d := io.dec_i0_decode_d aln_ctl.io.dec_i0_decode_d := io.dec_i0_decode_d
aln_ctl.io.ifu_bp_fa_index_f := bp_ctl.io.ifu_bp_fa_index_f aln_ctl.io.ifu_bp_fa_index_f := bp_ctl.io.ifu_bp_fa_index_f
@ -86,6 +100,7 @@ class ifu extends Module with lib with RequireAsyncReset {
// BP wiring Inputs // BP wiring Inputs
bp_ctl.io.scan_mode := io.scan_mode bp_ctl.io.scan_mode := io.scan_mode
// bp_ctl.io.active_clk := io.active_clk
bp_ctl.io.ic_hit_f := mem_ctl.io.ic_hit_f bp_ctl.io.ic_hit_f := mem_ctl.io.ic_hit_f
bp_ctl.io.ifc_fetch_addr_f := ifc_ctl.io.ifc_fetch_addr_f bp_ctl.io.ifc_fetch_addr_f := ifc_ctl.io.ifc_fetch_addr_f
bp_ctl.io.ifc_fetch_req_f := ifc_ctl.io.ifc_fetch_req_f bp_ctl.io.ifc_fetch_req_f := ifc_ctl.io.ifc_fetch_req_f

4
src/main/scala/ifu/ifu_aln_ctl.scala
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@ -24,8 +24,8 @@ class ifu_aln_ctl extends Module with lib with RequireAsyncReset {
// val ifu_i0_pc4 = Output(Bool()) // val ifu_i0_pc4 = Output(Bool())
val ifu_bp_fa_index_f = Vec(2, Input(UInt(log2Ceil(BTB_SIZE).W))) val ifu_bp_fa_index_f = Vec(2, Input(UInt(log2Ceil(BTB_SIZE).W)))
// val i0_brp = Output(Valid(new br_pkt_t())) // val i0_brp = Output(Valid(new br_pkt_t()))
// val ifu_i0_bp_index = Output(UInt((BTB_ADDR_HI-BTB_ADDR_LO+1).W)) // val ifu_i0_bp_index = Output(UInt((BTB_ADDR_HI-BTB_ADDR_LO+1).W))
// val ifu_i0_bp_fghr = Output(UInt(BHT_GHR_SIZE.W)) // val ifu_i0_bp_fghr = Output(UInt(BHT_GHR_SIZE.W))
// val ifu_i0_bp_btag = Output(UInt(BTB_BTAG_SIZE.W)) // val ifu_i0_bp_btag = Output(UInt(BTB_BTAG_SIZE.W))
val ifu_i0_fa_index = Output(UInt(log2Ceil(BTB_SIZE).W)) val ifu_i0_fa_index = Output(UInt(log2Ceil(BTB_SIZE).W))
// val ifu_pmu_instr_aligned = Output(Bool()) // val ifu_pmu_instr_aligned = Output(Bool())

126
src/main/scala/ifu/ifu_bp_ctl.scala
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@ -132,7 +132,7 @@ class ifu_bp_ctl extends Module with lib with RequireAsyncReset {
// If there is a flush from the lower pipe wait until the flush gets deasserted from the (decode) side // If there is a flush from the lower pipe wait until the flush gets deasserted from the (decode) side
leak_one_f := (io.dec_bp.dec_tlu_flush_leak_one_wb & io.dec_tlu_flush_lower_wb) | (leak_one_f_d1 & !io.dec_tlu_flush_lower_wb) leak_one_f := (io.dec_bp.dec_tlu_flush_leak_one_wb & io.dec_tlu_flush_lower_wb) | (leak_one_f_d1 & !io.dec_tlu_flush_lower_wb)
if(!BTB_FULLYA) { if(!BTB_FULLYA) {
val fetch_rd_tag_f = if (BTB_BTAG_FOLD) btb_tag_hash_fold(io.ifc_fetch_addr_f) else btb_tag_hash(io.ifc_fetch_addr_f) val fetch_rd_tag_f = if (BTB_BTAG_FOLD) btb_tag_hash_fold(io.ifc_fetch_addr_f) else btb_tag_hash(io.ifc_fetch_addr_f)
val fetch_rd_tag_p1_f = if (BTB_BTAG_FOLD) btb_tag_hash_fold(Cat(fetch_addr_p1_f, 0.U)) else btb_tag_hash(Cat(fetch_addr_p1_f, 0.U)) val fetch_rd_tag_p1_f = if (BTB_BTAG_FOLD) btb_tag_hash_fold(Cat(fetch_addr_p1_f, 0.U)) else btb_tag_hash(Cat(fetch_addr_p1_f, 0.U))
// There is a misprediction and the exu is writing back // There is a misprediction and the exu is writing back
@ -248,11 +248,11 @@ if(!BTB_FULLYA) {
io.ifc_fetch_addr_f(0).asBool -> Cat(tag_match_way1_expanded_p1_f(0), tag_match_way1_expanded_f(1)))) io.ifc_fetch_addr_f(0).asBool -> Cat(tag_match_way1_expanded_p1_f(0), tag_match_way1_expanded_f(1))))
btb_lru_b0_f := rvdffe(btb_lru_b0_ns, (io.ifc_fetch_req_f|exu_mp_valid).asBool, clock, io.scan_mode) btb_lru_b0_f := rvdffe(btb_lru_b0_ns, (io.ifc_fetch_req_f|exu_mp_valid).asBool, clock, io.scan_mode)
} }
io.ifu_bp_way_f := way_raw io.ifu_bp_way_f := way_raw
// update the lru // update the lru
//io.test := btb_lru_b0_ns //io.test := btb_lru_b0_ns
// Checking if the end of line is near // Checking if the end of line is near
val eoc_near = io.ifc_fetch_addr_f(ICACHE_BEAT_ADDR_HI-1, 2).andR val eoc_near = io.ifc_fetch_addr_f(ICACHE_BEAT_ADDR_HI-1, 2).andR
// Mask according to eoc-near and make the hit-final // Mask according to eoc-near and make the hit-final
@ -419,7 +419,7 @@ if(!BTB_FULLYA) {
val btb_bank0_rd_data_way1_out = Wire(Vec(LRU_SIZE,UInt(BTB_DWIDTH.W))) val btb_bank0_rd_data_way1_out = Wire(Vec(LRU_SIZE,UInt(BTB_DWIDTH.W)))
// BTB // BTB
// Entry -> Tag[BTB-BTAG-SIZE], toffset[12], pc4, boffset, call, ret, valid // Entry -> Tag[BTB-BTAG-SIZE], toffset[12], pc4, boffset, call, ret, valid
if(!BTB_FULLYA) { if(!BTB_FULLYA) {
// Enable for write on each way // Enable for write on each way
val btb_wr_en_way0 = ((!exu_mp_way) & exu_mp_valid_write & (!dec_tlu_error_wb)) | ((!dec_tlu_way_wb) & dec_tlu_error_wb) val btb_wr_en_way0 = ((!exu_mp_way) & exu_mp_valid_write & (!dec_tlu_error_wb)) | ((!dec_tlu_way_wb) & dec_tlu_error_wb)
val btb_wr_en_way1 = (exu_mp_way & exu_mp_valid_write & (!dec_tlu_error_wb)) | (dec_tlu_way_wb & dec_tlu_error_wb) val btb_wr_en_way1 = (exu_mp_way & exu_mp_valid_write & (!dec_tlu_error_wb)) | (dec_tlu_way_wb & dec_tlu_error_wb)
@ -437,68 +437,68 @@ if(!BTB_FULLYA) {
// BTB read muxing // BTB read muxing
btb_bank0_rd_data_way0_p1_f := Mux1H((0 until LRU_SIZE).map(i => (btb_rd_addr_p1_f === i.U).asBool -> btb_bank0_rd_data_way0_out(i))) btb_bank0_rd_data_way0_p1_f := Mux1H((0 until LRU_SIZE).map(i => (btb_rd_addr_p1_f === i.U).asBool -> btb_bank0_rd_data_way0_out(i)))
btb_bank0_rd_data_way1_p1_f := Mux1H((0 until LRU_SIZE).map(i => (btb_rd_addr_p1_f === i.U).asBool -> btb_bank0_rd_data_way1_out(i))) btb_bank0_rd_data_way1_p1_f := Mux1H((0 until LRU_SIZE).map(i => (btb_rd_addr_p1_f === i.U).asBool -> btb_bank0_rd_data_way1_out(i)))
} }
// if(BTB_FULLYA){ // if(BTB_FULLYA){
// val fetch_mp_collision_f = WireInit(Bool(),init = false.B) // val fetch_mp_collision_f = WireInit(Bool(),init = false.B)
// val fetch_mp_collision_p1_f = WireInit(Bool() ,init = false.B) // val fetch_mp_collision_p1_f = WireInit(Bool() ,init = false.B)
// //
// // Fully Associative tag hash uses bits 31:3. Bits 2:1 are the offset bits used for the 4 tag comp banks // // Fully Associative tag hash uses bits 31:3. Bits 2:1 are the offset bits used for the 4 tag comp banks
// // Full tag used to speed up lookup. There is one 31:3 cmp per entry, and 4 2:1 cmps per entry. // // Full tag used to speed up lookup. There is one 31:3 cmp per entry, and 4 2:1 cmps per entry.
// val ifc_fetch_addr_p1_f = io.ifc_fetch_addr_f(FA_CMP_LOWER-1,1) + 1.U // val ifc_fetch_addr_p1_f = io.ifc_fetch_addr_f(FA_CMP_LOWER-1,1) + 1.U
// //
// //
// // val fetch_mp_collision_f = ((io.exu_bp.exu_mp_btag(BTB_BTAG_SIZE-1,0) === io.ifc_fetch_addr_f) & exu_mp_valid & io.ifc_fetch_req_f & ~io.exu_bp.exu_mp_pkt.bits.way) // // val fetch_mp_collision_f = ((io.exu_bp.exu_mp_btag(BTB_BTAG_SIZE-1,0) === io.ifc_fetch_addr_f) & exu_mp_valid & io.ifc_fetch_req_f & ~io.exu_bp.exu_mp_pkt.bits.way)
// // val fetch_mp_collision_p1_f = ( (io.exu_bp.exu_mp_btag(BTB_BTAG_SIZE-1,0) === Cat(io.ifc_fetch_addr_f(30,FA_CMP_LOWER), ifc_fetch_addr_p1_f(FA_CMP_LOWER-1,1))) & exu_mp_valid & io.ifc_fetch_req_f & ~io.exu_bp.exu_mp_pkt.bits.way) // // val fetch_mp_collision_p1_f = ( (io.exu_bp.exu_mp_btag(BTB_BTAG_SIZE-1,0) === Cat(io.ifc_fetch_addr_f(30,FA_CMP_LOWER), ifc_fetch_addr_p1_f(FA_CMP_LOWER-1,1))) & exu_mp_valid & io.ifc_fetch_req_f & ~io.exu_bp.exu_mp_pkt.bits.way)
// // val btb_upper_hit = Wire(Vec(BTB_SIZE,Bool())) // // val btb_upper_hit = Wire(Vec(BTB_SIZE,Bool()))
// val btb_offset_0 = WireInit(UInt(BTB_SIZE.W) ,init = 0.U) // val btb_offset_0 = WireInit(UInt(BTB_SIZE.W) ,init = 0.U)
// val btb_used = WireInit(UInt(BTB_SIZE.W) ,init = 0.U) // val btb_used = WireInit(UInt(BTB_SIZE.W) ,init = 0.U)
// val btb_offset_1 = WireInit(UInt(BTB_SIZE.W) ,init = 0.U) // val btb_offset_1 = WireInit(UInt(BTB_SIZE.W) ,init = 0.U)
// val wr0_en = WireInit(UInt(BTB_SIZE.W) ,init = 0.U) // val wr0_en = WireInit(UInt(BTB_SIZE.W) ,init = 0.U)
// val btbdata = Wire(Vec(BTB_SIZE,UInt(BTB_DWIDTH.W))) // val btbdata = Wire(Vec(BTB_SIZE,UInt(BTB_DWIDTH.W)))
// btbdata := btbdata.map(i=> 0.U) // btbdata := btbdata.map(i=> 0.U)
// val hit0 = WireInit(UInt(1.W) ,init = 0.U) // val hit0 = WireInit(UInt(1.W) ,init = 0.U)
// val hit1 = WireInit(UInt(1.W) ,init = 0.U) // val hit1 = WireInit(UInt(1.W) ,init = 0.U)
// //
// // btb_upper_hit := (0 until BTB_SIZE).map(i=> ((btbdata(i)(BTB_DWIDTH_TOP,FA_TAG_END_UPPER) === io.ifc_fetch_addr_f(30,FA_CMP_LOWER)) & btbdata(i)(0) & ~wr0_en(i))) // // btb_upper_hit := (0 until BTB_SIZE).map(i=> ((btbdata(i)(BTB_DWIDTH_TOP,FA_TAG_END_UPPER) === io.ifc_fetch_addr_f(30,FA_CMP_LOWER)) & btbdata(i)(0) & ~wr0_en(i)))
// // val btb_offset_0 = (0 until BTB_SIZE).map(i=> (btbdata(i)(FA_TAG_START_LOWER,FA_TAG_END_LOWER) === io.ifc_fetch_addr_f(FA_CMP_LOWER-1,1)) & btb_upper_hit(i)) // // val btb_offset_0 = (0 until BTB_SIZE).map(i=> (btbdata(i)(FA_TAG_START_LOWER,FA_TAG_END_LOWER) === io.ifc_fetch_addr_f(FA_CMP_LOWER-1,1)) & btb_upper_hit(i))
// // val btb_offset_1 = (0 until BTB_SIZE).map(i=> (btbdata(i)(FA_TAG_START_LOWER,FA_TAG_END_LOWER) === ifc_fetch_addr_p1_f(FA_CMP_LOWER-1,1)) & btb_upper_hit(i)) // // val btb_offset_1 = (0 until BTB_SIZE).map(i=> (btbdata(i)(FA_TAG_START_LOWER,FA_TAG_END_LOWER) === ifc_fetch_addr_p1_f(FA_CMP_LOWER-1,1)) & btb_upper_hit(i))
// //
// // hit unless we are also writing this entry at the same time // // hit unless we are also writing this entry at the same time
// val hit0_index = MuxCase(1.U, (0 until BTB_SIZE).map(i=> btb_offset_0(i) -> i.U)) // val hit0_index = MuxCase(1.U, (0 until BTB_SIZE).map(i=> btb_offset_0(i) -> i.U))
// val hit1_index = MuxCase(1.U, (0 until BTB_SIZE).map(i=> btb_offset_1(i) -> i.U)) // val hit1_index = MuxCase(1.U, (0 until BTB_SIZE).map(i=> btb_offset_1(i) -> i.U))
// // Mux out the 2 potential branches // // Mux out the 2 potential branches
// btb_vbank0_rd_data_f := (0 until BTB_SIZE ).map(i=> if(btb_offset_1(i) == 1) Mux(fetch_mp_collision_f,btb_wr_data,btbdata(i)) else 0.U ).reverse.reduce(Cat(_,_)) // btb_vbank0_rd_data_f := (0 until BTB_SIZE ).map(i=> if(btb_offset_1(i) == 1) Mux(fetch_mp_collision_f,btb_wr_data,btbdata(i)) else 0.U ).reverse.reduce(Cat(_,_))
// btb_vbank1_rd_data_f :=(0 until BTB_SIZE).map(i=> if(btb_offset_1(i) == 1) Mux(fetch_mp_collision_p1_f,btb_wr_data,btbdata(i)) else 0.U).reverse.reduce(Cat(_,_)) // btb_vbank1_rd_data_f :=(0 until BTB_SIZE).map(i=> if(btb_offset_1(i) == 1) Mux(fetch_mp_collision_p1_f,btb_wr_data,btbdata(i)) else 0.U).reverse.reduce(Cat(_,_))
// val btb_fa_wr_addr0 = MuxCase(1.U, (0 until BTB_SIZE).map(i=> !btb_used(i) -> i.U)) // val btb_fa_wr_addr0 = MuxCase(1.U, (0 until BTB_SIZE).map(i=> !btb_used(i) -> i.U))
// //
// vwayhit_f := Cat(hit1,hit0) & Cat(eoc_mask,1.U) // vwayhit_f := Cat(hit1,hit0) & Cat(eoc_mask,1.U)
// way_raw := vwayhit_f | Cat(fetch_mp_collision_p1_f, fetch_mp_collision_f) // way_raw := vwayhit_f | Cat(fetch_mp_collision_p1_f, fetch_mp_collision_f)
// wr0_en := (0 until BTB_SIZE).map(i=> ((btb_fa_wr_addr0(BTB_FA_INDEX,0) === i.asUInt()) & (exu_mp_valid_write & ~io.exu_bp.exu_mp_pkt.bits.way)) | // wr0_en := (0 until BTB_SIZE).map(i=> ((btb_fa_wr_addr0(BTB_FA_INDEX,0) === i.asUInt()) & (exu_mp_valid_write & ~io.exu_bp.exu_mp_pkt.bits.way)) |
// ((io.dec_fa_error_index === i.asUInt()) & dec_tlu_error_wb)).reverse.reduce(Cat(_,_)) // ((io.dec_fa_error_index === i.asUInt()) & dec_tlu_error_wb)).reverse.reduce(Cat(_,_))
// btbdata := (0 until BTB_SIZE).map(i=> rvdffe(btb_wr_data,wr0_en(i),clock,io.scan_mode)) // btbdata := (0 until BTB_SIZE).map(i=> rvdffe(btb_wr_data,wr0_en(i),clock,io.scan_mode))
// //
// io.ifu_bp_fa_index_f(1) := Mux(hit1,hit1_index,0.U) // io.ifu_bp_fa_index_f(1) := Mux(hit1,hit1_index,0.U)
// io.ifu_bp_fa_index_f(0) := Mux(hit0,hit0_index,0.U) // io.ifu_bp_fa_index_f(0) := Mux(hit0,hit0_index,0.U)
// //
// val btb_used_reset = btb_used.andR() // val btb_used_reset = btb_used.andR()
// val btb_used_ns = Mux1H(Seq( // val btb_used_ns = Mux1H(Seq(
// vwayhit_f(1).asBool -> (1.U(32.W) << hit1_index(BTB_FA_INDEX,0)), // vwayhit_f(1).asBool -> (1.U(32.W) << hit1_index(BTB_FA_INDEX,0)),
// vwayhit_f(0).asBool() -> (1.U(32.W) << hit0_index(BTB_FA_INDEX,0)), // vwayhit_f(0).asBool() -> (1.U(32.W) << hit0_index(BTB_FA_INDEX,0)),
// (exu_mp_valid_write & !io.exu_bp.exu_mp_pkt.bits.way & !dec_tlu_error_wb).asBool() -> (1.U(32.W) << btb_fa_wr_addr0(BTB_FA_INDEX,0)), // (exu_mp_valid_write & !io.exu_bp.exu_mp_pkt.bits.way & !dec_tlu_error_wb).asBool() -> (1.U(32.W) << btb_fa_wr_addr0(BTB_FA_INDEX,0)),
// btb_used_reset.asBool -> Fill(BTB_SIZE,0.U), // btb_used_reset.asBool -> Fill(BTB_SIZE,0.U),
// (!btb_used_reset & dec_tlu_error_wb ).asBool -> (btb_used & ~(1.U(32.W) << io.dec_fa_error_index(BTB_FA_INDEX,0))), // (!btb_used_reset & dec_tlu_error_wb ).asBool -> (btb_used & ~(1.U(32.W) << io.dec_fa_error_index(BTB_FA_INDEX,0))),
// !(btb_used_reset | dec_tlu_error_wb ).asBool() -> btb_used // !(btb_used_reset | dec_tlu_error_wb ).asBool() -> btb_used
// )) // ))
// val write_used = btb_used_reset | io.ifu_bp_hit_taken_f | exu_mp_valid_write | dec_tlu_error_wb // val write_used = btb_used_reset | io.ifu_bp_hit_taken_f | exu_mp_valid_write | dec_tlu_error_wb
// btb_used := rvdffe(btb_used_ns,write_used.asBool(),clock,io.scan_mode) // btb_used := rvdffe(btb_used_ns,write_used.asBool(),clock,io.scan_mode)
// } // }
val bht_bank_clken = Wire(Vec(2, Vec(BHT_ARRAY_DEPTH/NUM_BHT_LOOP, Bool()))) val bht_bank_clken = Wire(Vec(2, Vec(BHT_ARRAY_DEPTH/NUM_BHT_LOOP, Bool())))
val bht_bank_clk = Wire(Vec(2, Vec(BHT_ARRAY_DEPTH/NUM_BHT_LOOP, Clock()))) val bht_bank_clk = Wire(Vec(2, Vec(BHT_ARRAY_DEPTH/NUM_BHT_LOOP, Clock())))
if(RV_FPGA_OPTIMIZE) { if(RV_FPGA_OPTIMIZE) {
for(i<-0 until 2; k<- 0 until (BHT_ARRAY_DEPTH/NUM_BHT_LOOP)) bht_bank_clk(i)(k) := rvclkhdr(clock, bht_bank_clken(i)(k), io.scan_mode) for(i<-0 until 2; k<- 0 until (BHT_ARRAY_DEPTH/NUM_BHT_LOOP)) bht_bank_clk(i)(k) := rvclkhdr(clock, bht_bank_clken(i)(k), io.scan_mode)
// (0 until 2).map(i=>(0 until (BHT_ARRAY_DEPTH/NUM_BHT_LOOP)).map(k=>rvclkhdr(clock, bht_bank_clken(i)(k), io.scan_mode))) // (0 until 2).map(i=>(0 until (BHT_ARRAY_DEPTH/NUM_BHT_LOOP)).map(k=>rvclkhdr(clock, bht_bank_clken(i)(k), io.scan_mode)))
} }
for(i<-0 until 2; k<- 0 until (BHT_ARRAY_DEPTH/NUM_BHT_LOOP)){ for(i<-0 until 2; k<- 0 until (BHT_ARRAY_DEPTH/NUM_BHT_LOOP)){
@ -530,6 +530,6 @@ if(!BTB_FULLYA) {
bht_bank1_rd_data_f := Mux1H((0 until BHT_ARRAY_DEPTH).map(i=>(bht_rd_addr_f===i.U).asBool->bht_bank_rd_data_out(1)(i))) bht_bank1_rd_data_f := Mux1H((0 until BHT_ARRAY_DEPTH).map(i=>(bht_rd_addr_f===i.U).asBool->bht_bank_rd_data_out(1)(i)))
bht_bank0_rd_data_p1_f := Mux1H((0 until BHT_ARRAY_DEPTH).map(i=>(bht_rd_addr_p1_f===i.U).asBool->bht_bank_rd_data_out(0)(i))) bht_bank0_rd_data_p1_f := Mux1H((0 until BHT_ARRAY_DEPTH).map(i=>(bht_rd_addr_p1_f===i.U).asBool->bht_bank_rd_data_out(0)(i)))
} }
object bp_MAIN extends App { //object bp_MAIN extends App {
println((new chisel3.stage.ChiselStage).emitVerilog(new ifu_bp_ctl())) // println((new chisel3.stage.ChiselStage).emitVerilog(new ifu_bp_ctl()))
} //}

16
src/main/scala/lib/lib.scala
View File

@ -36,6 +36,12 @@ trait lib extends param{
object rvsyncss { object rvsyncss {
def apply(din:UInt,clk:Clock) =withClock(clk){RegNext(withClock(clk){RegNext(din,0.U)},0.U)} def apply(din:UInt,clk:Clock) =withClock(clk){RegNext(withClock(clk){RegNext(din,0.U)},0.U)}
} }
object rvsyncss_fpga {
def apply(din:UInt, gw_clk:Clock, rawclk:Clock, clken:Bool) = {
val din_ff1 = rvdff_fpga(din,gw_clk,clken, rawclk)
rvdff_fpga(din_ff1,gw_clk,clken, rawclk)
}
}
/////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////
def btb_tag_hash(pc : UInt) = def btb_tag_hash(pc : UInt) =
@ -106,11 +112,11 @@ trait lib extends param{
} }
/////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////
def configurable_gw(clk : Clock, rst:AsyncReset, extintsrc_req_sync : Bool, meigwctrl_polarity: Bool, meigwctrl_type: Bool, meigwclr: Bool) = { def configurable_gw(gw_clk : Clock, rawclk:Clock, clken:Bool, rst:AsyncReset, extintsrc_req_sync : Bool, meigwctrl_polarity: Bool, meigwctrl_type: Bool, meigwclr: Bool) = {
val din = WireInit(Bool(), 0.U) val gw_int_pending = WireInit(UInt(1.W),0.U)
val dout = withClockAndReset(clk, rst){RegNext(din, false.B)} val gw_int_pending_in = (extintsrc_req_sync ^ meigwctrl_polarity) | (gw_int_pending & !meigwclr)
din := (extintsrc_req_sync ^ meigwctrl_polarity) | (dout & !meigwclr) gw_int_pending := rvdff_fpga(gw_int_pending_in,gw_clk,clken,rawclk)
Mux(meigwctrl_type, (extintsrc_req_sync ^ meigwctrl_polarity) | dout, extintsrc_req_sync ^ meigwctrl_polarity) Mux(meigwctrl_type.asBool(), ((extintsrc_req_sync ^ meigwctrl_polarity) | gw_int_pending), (extintsrc_req_sync ^ meigwctrl_polarity))
} }
/////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////

319
src/main/scala/lib/param.scala
View File

@ -2,165 +2,12 @@ package lib
import chisel3._ import chisel3._
import chisel3.util._ import chisel3.util._
trait param { trait param {
val BHT_ADDR_HI = 0x9 val BHT_ADDR_HI = 0x09
val BHT_ADDR_LO = 0x2 val BHT_ADDR_LO = 0x02
val BHT_ARRAY_DEPTH = 0x100 val BHT_ARRAY_DEPTH = 0x0100
val BHT_GHR_HASH_1 = 0x0 val BHT_GHR_HASH_1 = 0x00
val BHT_GHR_SIZE = 0x8 val BHT_GHR_SIZE = 0x08
val BHT_SIZE = 0x200 val BHT_SIZE = 0x0200
val BTB_ADDR_HI = 0x09
val BTB_ADDR_LO = 0x2
val BTB_ARRAY_DEPTH = 0x100
val BTB_BTAG_FOLD = 0x0
val BTB_BTAG_SIZE = 0x5
val BTB_FOLD2_INDEX_HASH = 0x0
val BTB_INDEX1_HI = 0x09
val BTB_INDEX1_LO = 0x02
val BTB_INDEX2_HI = 0x11
val BTB_INDEX2_LO = 0x0A
val BTB_INDEX3_HI = 0x19
val BTB_INDEX3_LO = 0x12
val BTB_SIZE = 0x200
val BUILD_AHB_LITE = 0x0
val BUILD_AXI4 = 0x1
val BUILD_AXI_NATIVE = 0x1
val BUS_PRTY_DEFAULT = 0x3
val DATA_ACCESS_ADDR0 = 0x00000000
val DATA_ACCESS_ADDR1 = 0xC0000000
val DATA_ACCESS_ADDR2 = 0xA0000000
val DATA_ACCESS_ADDR3 = 0x80000000
val DATA_ACCESS_ADDR4 = 0x00000000
val DATA_ACCESS_ADDR5 = 0x00000000
val DATA_ACCESS_ADDR6 = 0x00000000
val DATA_ACCESS_ADDR7 = 0x00000000
val DATA_ACCESS_ENABLE0 = 0x1
val DATA_ACCESS_ENABLE1 = 0x1
val DATA_ACCESS_ENABLE2 = 0x1
val DATA_ACCESS_ENABLE3 = 0x1
val DATA_ACCESS_ENABLE4 = 0x0
val DATA_ACCESS_ENABLE5 = 0x0
val DATA_ACCESS_ENABLE6 = 0x0
val DATA_ACCESS_ENABLE7 = 0x0
val DATA_ACCESS_MASK0 = 0x7FFFFFFF
val DATA_ACCESS_MASK1 = 0x3FFFFFFF
val DATA_ACCESS_MASK2 = 0x1FFFFFFF
val DATA_ACCESS_MASK3 = 0x0FFFFFFF
val DATA_ACCESS_MASK4 = 0xFFFFFFFF
val DATA_ACCESS_MASK5 = 0xFFFFFFFF
val DATA_ACCESS_MASK6 = 0xFFFFFFFF
val DATA_ACCESS_MASK7 = 0xFFFFFFFF
val DCCM_BANK_BITS = 0x2
val DCCM_BITS = 0x10
val DCCM_BYTE_WIDTH = 0x4
val DCCM_DATA_WIDTH = 0x20
val DCCM_ECC_WIDTH = 0x7
val DCCM_ENABLE = 0x1
val DCCM_FDATA_WIDTH = 0x27
val DCCM_INDEX_BITS = 0xC
val DCCM_NUM_BANKS = 0x04
val DCCM_REGION = 0xF
val DCCM_SADR = 0xF0040000
val DCCM_SIZE = 0x040
val DCCM_WIDTH_BITS = 0x2
val DMA_BUF_DEPTH = 0x5
val DMA_BUS_ID = 0x1
val DMA_BUS_PRTY = 0x2
val DMA_BUS_TAG = 0x1
val FAST_INTERRUPT_REDIRECT = 0x1
val ICACHE_2BANKS = 0x1
val ICACHE_BANK_BITS = 0x1
val ICACHE_BANK_HI = 0x3
val ICACHE_BANK_LO = 0x3
val ICACHE_BANK_WIDTH = 0x8
val ICACHE_BANKS_WAY = 0x2
val ICACHE_BEAT_ADDR_HI = 0x5
val ICACHE_BEAT_BITS = 0x3
val ICACHE_DATA_DEPTH = 0x0200
val ICACHE_DATA_INDEX_LO = 0x4
val ICACHE_DATA_WIDTH = 0x40
val ICACHE_ECC = 0x1
val ICACHE_ENABLE = 0x1
val ICACHE_FDATA_WIDTH = 0x47
val ICACHE_INDEX_HI = 0x0C
val ICACHE_LN_SZ = 0x40
val ICACHE_NUM_BEATS = 0x8
val ICACHE_NUM_WAYS = 0x2
val ICACHE_ONLY = 0x0
val ICACHE_SCND_LAST = 0x6
val ICACHE_SIZE = 0x010
val ICACHE_STATUS_BITS = 0x1
val ICACHE_TAG_DEPTH = 0x0080
val ICACHE_TAG_INDEX_LO = 0x6
val ICACHE_TAG_LO = 0x0D
val ICACHE_WAYPACK = 0x0
val ICCM_BANK_BITS = 0x2
val ICCM_BANK_HI = 0x03
val ICCM_BANK_INDEX_LO = 0x04
val ICCM_BITS = 0x10
val ICCM_ENABLE = 0x1
val ICCM_ICACHE = 0x1
val ICCM_INDEX_BITS = 0xC
val ICCM_NUM_BANKS = 0x04
val ICCM_ONLY = 0x0
val ICCM_REGION = 0xE
val ICCM_SADR = 0xEE000000
val ICCM_SIZE = 0x040
val IFU_BUS_ID = 0x1
val IFU_BUS_PRTY = 0x2
val IFU_BUS_TAG = 0x3
val INST_ACCESS_ADDR0 = 0x00000000
val INST_ACCESS_ADDR1 = 0xC0000000
val INST_ACCESS_ADDR2 = 0xA0000000
val INST_ACCESS_ADDR3 = 0x80000000
val INST_ACCESS_ADDR4 = 0x00000000
val INST_ACCESS_ADDR5 = 0x00000000
val INST_ACCESS_ADDR6 = 0x00000000
val INST_ACCESS_ADDR7 = 0x00000000
val INST_ACCESS_ENABLE0 = 0x1
val INST_ACCESS_ENABLE1 = 0x1
val INST_ACCESS_ENABLE2 = 0x1
val INST_ACCESS_ENABLE3 = 0x1
val INST_ACCESS_ENABLE4 = 0x0
val INST_ACCESS_ENABLE5 = 0x0
val INST_ACCESS_ENABLE6 = 0x0
val INST_ACCESS_ENABLE7 = 0x0
val INST_ACCESS_MASK0 = 0x7FFFFFFF
val INST_ACCESS_MASK1 = 0x3FFFFFFF
val INST_ACCESS_MASK2 = 0x1FFFFFFF
val INST_ACCESS_MASK3 = 0x0FFFFFFF
val INST_ACCESS_MASK4 = 0xFFFFFFFF
val INST_ACCESS_MASK5 = 0xFFFFFFFF
val INST_ACCESS_MASK6 = 0xFFFFFFFF
val INST_ACCESS_MASK7 = 0xFFFFFFFF
val LOAD_TO_USE_PLUS1 = 0x0
val LSU2DMA = 0x0
val LSU_BUS_ID = 0x1
val LSU_BUS_PRTY = 0x2
val LSU_BUS_TAG = 0x3
val LSU_NUM_NBLOAD = 0x04
val LSU_NUM_NBLOAD_WIDTH = 0x2
val LSU_SB_BITS = 0x10
val LSU_STBUF_DEPTH = 0x4
val NO_ICCM_NO_ICACHE = 0x0
val PIC_2CYCLE = 0x0
val PIC_BASE_ADDR = 0xF00C0000
val PIC_BITS = 0x0F
val PIC_INT_WORDS = 0x1
val PIC_REGION = 0xF
val PIC_SIZE = 0x020
val PIC_TOTAL_INT = 0x1F
val PIC_TOTAL_INT_PLUS1 = 0x020
val RET_STACK_SIZE = 0x8
val SB_BUS_ID = 0x1
val SB_BUS_PRTY = 0x2
val SB_BUS_TAG = 0x1
val TIMER_LEGAL_EN = 0x1
val RV_FPGA_OPTIMIZE = 0x1
val DIV_NEW = 0x1
val DIV_BIT = 0x4
val BTB_ENABLE = 0x1
val BTB_TOFFSET_SIZE = 0x00C
val BTB_FULLYA = 0x00
val BITMANIP_ZBA = 0x00 val BITMANIP_ZBA = 0x00
val BITMANIP_ZBB = 0x01 val BITMANIP_ZBB = 0x01
val BITMANIP_ZBC = 0x00 val BITMANIP_ZBC = 0x00
@ -169,13 +16,165 @@ trait param {
val BITMANIP_ZBP = 0x00 val BITMANIP_ZBP = 0x00
val BITMANIP_ZBR = 0x00 val BITMANIP_ZBR = 0x00
val BITMANIP_ZBS = 0x01 val BITMANIP_ZBS = 0x01
val BTB_ADDR_HI = 0x009
val BTB_ADDR_LO = 0x02
val BTB_ARRAY_DEPTH = 0x0100
val BTB_BTAG_FOLD = 0x00
val BTB_BTAG_SIZE = 0x005
val BTB_ENABLE = 0x01
val BTB_FOLD2_INDEX_HASH = 0x00
val BTB_FULLYA = 0x00
val BTB_INDEX1_HI = 0x009
val BTB_INDEX1_LO = 0x002
val BTB_INDEX2_HI = 0x011
val BTB_INDEX2_LO = 0x00A
val BTB_INDEX3_HI = 0x019
val BTB_INDEX3_LO = 0x012
val BTB_SIZE = 0x0200
val BTB_TOFFSET_SIZE = 0x00C
val BUILD_AHB_LITE = 0x0
val BUILD_AXI4 = 0x01
val BUILD_AXI_NATIVE = 0x01
val BUS_PRTY_DEFAULT = 0x03
val DATA_ACCESS_ADDR0 = 0x000000000
val DATA_ACCESS_ADDR1 = 0x000000000
val DATA_ACCESS_ADDR2 = 0x000000000
val DATA_ACCESS_ADDR3 = 0x000000000
val DATA_ACCESS_ADDR4 = 0x000000000
val DATA_ACCESS_ADDR5 = 0x000000000
val DATA_ACCESS_ADDR6 = 0x000000000
val DATA_ACCESS_ADDR7 = 0x000000000
val DATA_ACCESS_ENABLE0 = 0x00
val DATA_ACCESS_ENABLE1 = 0x00
val DATA_ACCESS_ENABLE2 = 0x00
val DATA_ACCESS_ENABLE3 = 0x00
val DATA_ACCESS_ENABLE4 = 0x00
val DATA_ACCESS_ENABLE5 = 0x00
val DATA_ACCESS_ENABLE6 = 0x00
val DATA_ACCESS_ENABLE7 = 0x00
val DATA_ACCESS_MASK0 = 0x0FFFFFFFF
val DATA_ACCESS_MASK1 = 0x0FFFFFFFF
val DATA_ACCESS_MASK2 = 0x0FFFFFFFF
val DATA_ACCESS_MASK3 = 0x0FFFFFFFF
val DATA_ACCESS_MASK4 = 0x0FFFFFFFF
val DATA_ACCESS_MASK5 = 0x0FFFFFFFF
val DATA_ACCESS_MASK6 = 0x0FFFFFFFF
val DATA_ACCESS_MASK7 = 0x0FFFFFFFF
val DCCM_BANK_BITS = 0x02
val DCCM_BITS = 0x010
val DCCM_BYTE_WIDTH = 0x04
val DCCM_DATA_WIDTH = 0x020
val DCCM_ECC_WIDTH = 0x07
val DCCM_ENABLE = 0x01
val DCCM_FDATA_WIDTH = 0x027
val DCCM_INDEX_BITS = 0x0C
val DCCM_NUM_BANKS = 0x004
val DCCM_REGION = 0x0F
val DCCM_SADR = 0x0F0040000
val DCCM_SIZE = 0x0040
val DCCM_WIDTH_BITS = 0x02
val DIV_BIT = 0x04
val DIV_NEW = 0x01
val DMA_BUF_DEPTH = 0x05
val DMA_BUS_ID = 0x001
val DMA_BUS_PRTY = 0x02
val DMA_BUS_TAG = 0x01
val FAST_INTERRUPT_REDIRECT = 0x01
val ICACHE_2BANKS = 0x01
val ICACHE_BANK_BITS = 0x01
val ICACHE_BANK_HI = 0x03
val ICACHE_BANK_LO = 0x03
val ICACHE_BANK_WIDTH = 0x08
val ICACHE_BANKS_WAY = 0x02
val ICACHE_BEAT_ADDR_HI = 0x05
val ICACHE_BEAT_BITS = 0x03
val ICACHE_BYPASS_ENABLE = 0x01 val ICACHE_BYPASS_ENABLE = 0x01
val ICACHE_DATA_DEPTH = 0x00200
val ICACHE_DATA_INDEX_LO = 0x04
val ICACHE_DATA_WIDTH = 0x040
val ICACHE_ECC = 0x01
val ICACHE_ENABLE = 0x01
val ICACHE_FDATA_WIDTH = 0x047
val ICACHE_INDEX_HI = 0x00C
val ICACHE_LN_SZ = 0x040
val ICACHE_NUM_BEATS = 0x08
val ICACHE_NUM_BYPASS = 0x02 val ICACHE_NUM_BYPASS = 0x02
val ICACHE_NUM_BYPASS_WIDTH = 0x02 val ICACHE_NUM_BYPASS_WIDTH = 0x02
val ICACHE_NUM_WAYS = 0x02
val ICACHE_ONLY = 0x00
val ICACHE_SCND_LAST = 0x06
val ICACHE_SIZE = 0x0010
val ICACHE_STATUS_BITS = 0x01
val ICACHE_TAG_BYPASS_ENABLE = 0x01 val ICACHE_TAG_BYPASS_ENABLE = 0x01
val ICACHE_TAG_DEPTH = 0x00080
val ICACHE_TAG_INDEX_LO = 0x06
val ICACHE_TAG_LO = 0x00D
val ICACHE_TAG_NUM_BYPASS = 0x02 val ICACHE_TAG_NUM_BYPASS = 0x02
val ICACHE_TAG_NUM_BYPASS_WIDTH = 0x02 val ICACHE_TAG_NUM_BYPASS_WIDTH = 0x02
val ICACHE_WAYPACK = 0x01
val ICCM_BANK_BITS = 0x02
val ICCM_BANK_HI = 0x003
val ICCM_BANK_INDEX_LO = 0x004
val ICCM_BITS = 0x010
val ICCM_ENABLE = 0x01
val ICCM_ICACHE = 0x01
val ICCM_INDEX_BITS = 0x0C
val ICCM_NUM_BANKS = 0x004
val ICCM_ONLY = 0x00
val ICCM_REGION = 0x0E
val ICCM_SADR = 0x0EE000000
val ICCM_SIZE = 0x0040
val IFU_BUS_ID = 0x01
val IFU_BUS_PRTY = 0x02
val IFU_BUS_TAG = 0x03
val INST_ACCESS_ADDR0 = 0x000000000
val INST_ACCESS_ADDR1 = 0x000000000
val INST_ACCESS_ADDR2 = 0x000000000
val INST_ACCESS_ADDR3 = 0x000000000
val INST_ACCESS_ADDR4 = 0x000000000
val INST_ACCESS_ADDR5 = 0x000000000
val INST_ACCESS_ADDR6 = 0x000000000
val INST_ACCESS_ADDR7 = 0x000000000
val INST_ACCESS_ENABLE0 = 0x00
val INST_ACCESS_ENABLE1 = 0x00
val INST_ACCESS_ENABLE2 = 0x00
val INST_ACCESS_ENABLE3 = 0x00
val INST_ACCESS_ENABLE4 = 0x00
val INST_ACCESS_ENABLE5 = 0x00
val INST_ACCESS_ENABLE6 = 0x00
val INST_ACCESS_ENABLE7 = 0x00
val INST_ACCESS_MASK0 = 0x0FFFFFFFF
val INST_ACCESS_MASK1 = 0x0FFFFFFFF
val INST_ACCESS_MASK2 = 0x0FFFFFFFF
val INST_ACCESS_MASK3 = 0x0FFFFFFFF
val INST_ACCESS_MASK4 = 0x0FFFFFFFF
val INST_ACCESS_MASK5 = 0x0FFFFFFFF
val INST_ACCESS_MASK6 = 0x0FFFFFFFF
val INST_ACCESS_MASK7 = 0x0FFFFFFFF
val LOAD_TO_USE_PLUS1 = 0x00
val LSU2DMA = 0x00
val LSU_BUS_ID = 0x01
val LSU_BUS_PRTY = 0x02
val LSU_BUS_TAG = 0x03
val LSU_NUM_NBLOAD = 0x004
val LSU_NUM_NBLOAD_WIDTH = 0x02
val LSU_SB_BITS = 0x010
val LSU_STBUF_DEPTH = 0x04
val NO_ICCM_NO_ICACHE = 0x00
val PIC_2CYCLE = 0x00
val PIC_BASE_ADDR = 0x0F00C0000
val PIC_BITS = 0x00F
val PIC_INT_WORDS = 0x01
val PIC_REGION = 0x0F
val PIC_SIZE = 0x0020
val PIC_TOTAL_INT = 0x01F
val PIC_TOTAL_INT_PLUS1 = 0x0020
val RET_STACK_SIZE = 0x08
val SB_BUS_ID = 0x01
val SB_BUS_PRTY = 0x02
val SB_BUS_TAG = 0x01
val TIMER_LEGAL_EN = 0x01
val RV_FPGA_OPTIMIZE = 0x1
} }

69
src/main/scala/pic_ctrl.scala
View File

@ -3,15 +3,14 @@ import chisel3.util._
import include._ import include._
import lib._ import lib._
import chisel3.experimental.chiselName import chisel3.experimental.chiselName
import chisel3.stage.ChiselStage
@chiselName @chiselName
class pic_ctrl extends Module with RequireAsyncReset with lib { class pic_ctrl extends Module with RequireAsyncReset with lib {
val io = IO (new Bundle { val io = IO (new Bundle {
val scan_mode = Input(Bool()) val scan_mode = Input(Bool())
val free_clk = Input(Clock () ) val free_clk = Input(Clock () )
val io_clk_override = Input(Bool () )
val clk_override = Input(Bool () ) val clk_override = Input(Bool () )
val io_clk_override = Input(Bool () )
val extintsrc_req = Input(UInt (PIC_TOTAL_INT_PLUS1.W)) val extintsrc_req = Input(UInt (PIC_TOTAL_INT_PLUS1.W))
val lsu_pic = Flipped(new lsu_pic()) val lsu_pic = Flipped(new lsu_pic())
val dec_pic = Flipped(new dec_pic) val dec_pic = Flipped(new dec_pic)
@ -27,12 +26,12 @@ class pic_ctrl extends Module with RequireAsyncReset with lib {
def cmp_and_mux (a_id : UInt, a_priority : UInt, b_id : UInt, b_priority : UInt) = def cmp_and_mux (a_id : UInt, a_priority : UInt, b_id : UInt, b_priority : UInt) =
(Mux(a_priority<b_priority, b_id, a_id), Mux(a_priority<b_priority, b_priority, a_priority)) (Mux(a_priority<b_priority, b_id, a_id), Mux(a_priority<b_priority, b_priority, a_priority))
def configurable_gw (clk : Clock, extintsrc_req_sync : UInt, meigwctrl_polarity : UInt, meigwctrl_type : UInt, meigwclr : UInt) = { // def configurable_gw (clk : Clock, extintsrc_req_sync : UInt, meigwctrl_polarity : UInt, meigwctrl_type : UInt, meigwclr : UInt) = {
val gw_int_pending = WireInit(UInt(1.W),0.U) // val gw_int_pending = WireInit(UInt(1.W),0.U)
val gw_int_pending_in = (extintsrc_req_sync ^ meigwctrl_polarity) | (gw_int_pending & !meigwclr) // val gw_int_pending_in = (extintsrc_req_sync ^ meigwctrl_polarity) | (gw_int_pending & !meigwclr)
gw_int_pending := withClock(clk){RegNext(gw_int_pending_in,0.U)} // gw_int_pending := withClock(clk){RegNext(gw_int_pending_in,0.U)}
Mux(meigwctrl_type.asBool(), ((extintsrc_req_sync ^ meigwctrl_polarity) | gw_int_pending), (extintsrc_req_sync ^ meigwctrl_polarity)) // Mux(meigwctrl_type.asBool(), ((extintsrc_req_sync ^ meigwctrl_polarity) | gw_int_pending), (extintsrc_req_sync ^ meigwctrl_polarity))
} // }
// io.mexintpend := 0.U // io.mexintpend := 0.U
// io.pic_claimid := 0.U // io.pic_claimid := 0.U
@ -57,7 +56,7 @@ class pic_ctrl extends Module with RequireAsyncReset with lib {
case _ => 1024 case _ => 1024
} }
val INT_ENABLE_GRPS = (PIC_TOTAL_INT_PLUS1 - 1) / 4
val INT_GRPS = INTPEND_SIZE / 32 val INT_GRPS = INTPEND_SIZE / 32
val INTPRIORITY_BITS = 4 val INTPRIORITY_BITS = 4
val ID_BITS = 8 val ID_BITS = 8
@ -70,14 +69,14 @@ class pic_ctrl extends Module with RequireAsyncReset with lib {
val selected_int_priority = WireInit(0.U (INTPRIORITY_BITS.W)) val selected_int_priority = WireInit(0.U (INTPRIORITY_BITS.W))
val intpend_w_prior_en = Wire(Vec(PIC_TOTAL_INT_PLUS1,UInt(INTPRIORITY_BITS.W)))/////////////////// val intpend_w_prior_en = Wire(Vec(PIC_TOTAL_INT_PLUS1,UInt(INTPRIORITY_BITS.W)))///////////////////
val intpend_id = Wire(Vec(PIC_TOTAL_INT_PLUS1,UInt(ID_BITS.W))) val intpend_id = Wire(Vec(PIC_TOTAL_INT_PLUS1,UInt(ID_BITS.W)))
val levelx_intpend_w_prior_en = Wire(Vec((NUM_LEVELS - NUM_LEVELS/2)+1 ,Vec ((PIC_TOTAL_INT_PLUS1 / scala.math.pow(2,NUM_LEVELS/2)+2).toInt,UInt(INTPRIORITY_BITS.W)))) val levelx_intpend_w_prior_en = Wire(Vec((NUM_LEVELS - NUM_LEVELS/2)+1 ,Vec ((PIC_TOTAL_INT_PLUS1 / scala.math.pow(2,NUM_LEVELS/2).toInt)+2,UInt(INTPRIORITY_BITS.W))))
for(i<- 0 until (NUM_LEVELS - NUM_LEVELS/2)+1; j<- 0 until (PIC_TOTAL_INT_PLUS1 / scala.math.pow(2,NUM_LEVELS/2).toInt)+2) levelx_intpend_w_prior_en(i)(j) := 0.U for(i<- 0 until (NUM_LEVELS - NUM_LEVELS/2)+1; j<- 0 until (PIC_TOTAL_INT_PLUS1 / scala.math.pow(2,NUM_LEVELS/2).toInt)+2) levelx_intpend_w_prior_en(i)(j) := 0.U
val levelx_intpend_id = Wire(Vec((NUM_LEVELS - NUM_LEVELS/2)+1 ,Vec ((PIC_TOTAL_INT_PLUS1 / scala.math.pow(2,NUM_LEVELS/2).toInt)+2,UInt(ID_BITS.W)))) val levelx_intpend_id = Wire(Vec((NUM_LEVELS - NUM_LEVELS/2)+1 ,Vec ((PIC_TOTAL_INT_PLUS1 / scala.math.pow(2,NUM_LEVELS/2).toInt)+2,UInt(ID_BITS.W))))
for(i<- 0 until (NUM_LEVELS - NUM_LEVELS/2)+1; j<- 0 until (PIC_TOTAL_INT_PLUS1 / scala.math.pow(2,NUM_LEVELS/2).toInt)+2) levelx_intpend_id(i)(j) := 0.U for(i<- 0 until (NUM_LEVELS - NUM_LEVELS/2)+1; j<- 0 until (PIC_TOTAL_INT_PLUS1 / scala.math.pow(2,NUM_LEVELS/2).toInt)+2) levelx_intpend_id(i)(j) := 0.U
val l2_intpend_w_prior_en_ff = Wire(Vec((PIC_TOTAL_INT_PLUS1 / scala.math.pow(2,NUM_LEVELS/2)+1).toInt,UInt(INTPRIORITY_BITS.W))) val l2_intpend_w_prior_en_ff = Wire(Vec(PIC_TOTAL_INT_PLUS1 / scala.math.pow(2,NUM_LEVELS/2).toInt,UInt(INTPRIORITY_BITS.W)))
for(i<- 0 until (PIC_TOTAL_INT_PLUS1 / scala.math.pow(2,NUM_LEVELS/2)+1).toInt) l2_intpend_w_prior_en_ff(i) := 0.U for(i<- 0 until (PIC_TOTAL_INT_PLUS1 / scala.math.pow(2,NUM_LEVELS/2).toInt)) l2_intpend_w_prior_en_ff(i) := 0.U
val l2_intpend_id_ff = Wire(Vec((PIC_TOTAL_INT_PLUS1 / scala.math.pow(2,NUM_LEVELS/2)+1).toInt,UInt(ID_BITS.W))) val l2_intpend_id_ff = Wire(Vec(PIC_TOTAL_INT_PLUS1 / scala.math.pow(2,NUM_LEVELS/2).toInt,UInt(ID_BITS.W)))
for(i<- 0 until (PIC_TOTAL_INT_PLUS1 / scala.math.pow(2,NUM_LEVELS/2)+1).toInt) l2_intpend_id_ff(i) := 0.U for(i<- 0 until (PIC_TOTAL_INT_PLUS1 / scala.math.pow(2,NUM_LEVELS/2).toInt)) l2_intpend_id_ff(i) := 0.U
val config_reg = WireInit(0.U(1.W)) val config_reg = WireInit(0.U(1.W))
val intpriord = WireInit(0.U(1.W)) val intpriord = WireInit(0.U(1.W))
val prithresh_reg_write = WireInit(0.U(1.W)) val prithresh_reg_write = WireInit(0.U(1.W))
@ -106,6 +105,20 @@ class pic_ctrl extends Module with RequireAsyncReset with lib {
withClock(io.free_clk) {picm_mken_ff := RegNext(io.lsu_pic.picm_mken,0.U)} withClock(io.free_clk) {picm_mken_ff := RegNext(io.lsu_pic.picm_mken,0.U)}
withClock(pic_data_c1_clk) {picm_wr_data_ff := RegNext(io.lsu_pic.picm_wr_data,0.U)} withClock(pic_data_c1_clk) {picm_wr_data_ff := RegNext(io.lsu_pic.picm_wr_data,0.U)}
val intenable_clk_enable_grp = Wire(Vec(INT_ENABLE_GRPS+1,UInt(1.W)))
val intenable_clk_enable = WireInit(UInt(PIC_TOTAL_INT_PLUS1.W),0.U)
val gw_clk = Wire(Vec(INT_ENABLE_GRPS+1,Clock()))
for (p <- 0 to INT_ENABLE_GRPS) {
if (p==INT_ENABLE_GRPS) {
intenable_clk_enable_grp(p) := intenable_clk_enable(PIC_TOTAL_INT_PLUS1-1, p*4).orR | io.io_clk_override
gw_clk(p) := rvoclkhdr(clock,intenable_clk_enable_grp(p),io.scan_mode)
}else {
intenable_clk_enable_grp(p) := intenable_clk_enable(p*4+3 , p*4).orR | io.io_clk_override
gw_clk(p) := rvoclkhdr(clock,intenable_clk_enable_grp(p),io.scan_mode)
}
}
val temp_raddr_intenable_base_match = ~(picm_raddr_ff ^ INTENABLE_BASE_ADDR.asUInt) val temp_raddr_intenable_base_match = ~(picm_raddr_ff ^ INTENABLE_BASE_ADDR.asUInt)
val raddr_intenable_base_match = temp_raddr_intenable_base_match(31,NUM_LEVELS+2).andR//// (31,NUM_LEVELS+2) val raddr_intenable_base_match = temp_raddr_intenable_base_match(31,NUM_LEVELS+2).andR//// (31,NUM_LEVELS+2)
@ -130,14 +143,15 @@ class pic_ctrl extends Module with RequireAsyncReset with lib {
val gw_config_c1_clken = (waddr_config_gw_base_match & picm_wren_ff) | (raddr_config_gw_base_match & picm_rden_ff) | io.clk_override val gw_config_c1_clken = (waddr_config_gw_base_match & picm_wren_ff) | (raddr_config_gw_base_match & picm_rden_ff) | io.clk_override
// C1 - 1 clock pulse for data // C1 - 1 clock pulse for data
pic_raddr_c1_clk := rvclkhdr(clock,pic_raddr_c1_clken,io.scan_mode) pic_raddr_c1_clk := rvoclkhdr(clock,pic_raddr_c1_clken,io.scan_mode)
pic_data_c1_clk := rvclkhdr(clock,pic_data_c1_clken,io.scan_mode) pic_data_c1_clk := rvoclkhdr(clock,pic_data_c1_clken,io.scan_mode)
pic_pri_c1_clk := rvclkhdr(clock,pic_pri_c1_clken.asBool,io.scan_mode) pic_pri_c1_clk := rvoclkhdr(clock,pic_pri_c1_clken.asBool,io.scan_mode)
pic_int_c1_clk := rvclkhdr(clock,pic_int_c1_clken.asBool,io.scan_mode) pic_int_c1_clk := rvoclkhdr(clock,pic_int_c1_clken.asBool,io.scan_mode)
gw_config_c1_clk := rvclkhdr(clock,(gw_config_c1_clken | io.io_clk_override).asBool,io.scan_mode) gw_config_c1_clk := rvoclkhdr(clock,gw_config_c1_clken.asBool,io.scan_mode)
// ------ end clock gating section ------------------------ // ------ end clock gating section ------------------------
val extintsrc_req_sync = Cat(rvsyncss(io.extintsrc_req(PIC_TOTAL_INT_PLUS1-1,1),io.free_clk),io.extintsrc_req(0)) val extintsrc_req_sync = Wire(Vec(PIC_TOTAL_INT_PLUS1,UInt(1.W)))
(0 until PIC_TOTAL_INT_PLUS1).map (i => if(i>0){ extintsrc_req_sync(i) := rvsyncss_fpga(io.extintsrc_req(i),gw_clk(i/4),clock, intenable_clk_enable_grp(i/4))} else extintsrc_req_sync(i) := 0.U)
val intpriority_reg_we = (0 until PIC_TOTAL_INT_PLUS1).map (i => if(i>0){waddr_intpriority_base_match & (picm_waddr_ff(NUM_LEVELS+1,2) === i.asUInt) & picm_wren_ff} else 0.U) val intpriority_reg_we = (0 until PIC_TOTAL_INT_PLUS1).map (i => if(i>0){waddr_intpriority_base_match & (picm_waddr_ff(NUM_LEVELS+1,2) === i.asUInt) & picm_wren_ff} else 0.U)
val intpriority_reg_re = (0 until PIC_TOTAL_INT_PLUS1).map (i => if(i>0){raddr_intpriority_base_match & (picm_raddr_ff(NUM_LEVELS+1,2) === i.asUInt) & picm_rden_ff} else 0.U) val intpriority_reg_re = (0 until PIC_TOTAL_INT_PLUS1).map (i => if(i>0){raddr_intpriority_base_match & (picm_raddr_ff(NUM_LEVELS+1,2) === i.asUInt) & picm_rden_ff} else 0.U)
@ -153,8 +167,9 @@ class pic_ctrl extends Module with RequireAsyncReset with lib {
val gw_config_reg = Wire(Vec(PIC_TOTAL_INT_PLUS1,UInt(2.W))) val gw_config_reg = Wire(Vec(PIC_TOTAL_INT_PLUS1,UInt(2.W)))
(0 until PIC_TOTAL_INT_PLUS1).map (i => if(i>0){ gw_config_reg(i) := withClock(gw_config_c1_clk){RegEnable(picm_wr_data_ff(1,0),0.U,gw_config_reg_we(i).asBool)}} else gw_config_reg(i) := 0.U(2.W)) (0 until PIC_TOTAL_INT_PLUS1).map (i => if(i>0){ gw_config_reg(i) := withClock(gw_config_c1_clk){RegEnable(picm_wr_data_ff(1,0),0.U,gw_config_reg_we(i).asBool)}} else gw_config_reg(i) := 0.U(2.W))
intenable_clk_enable := (0 until PIC_TOTAL_INT_PLUS1).map (i => if(i>0){gw_config_reg(i)(1) | intenable_reg_we(i) | intenable_reg(i) | gw_clear_reg_we(i)} else 0.U).reverse.reduce(Cat(_,_))
val extintsrc_req_gw = (0 until PIC_TOTAL_INT_PLUS1).map(i=>if(i>0) val extintsrc_req_gw = (0 until PIC_TOTAL_INT_PLUS1).map(i=>if(i>0)
configurable_gw(io.free_clk, extintsrc_req_sync(i), gw_config_reg(i)(0), gw_config_reg(i)(1), gw_clear_reg_we(i).asBool()) configurable_gw(gw_clk(i/4), clock, intenable_clk_enable_grp(i/4),reset.asAsyncReset(), extintsrc_req_sync(i), gw_config_reg(i)(0), gw_config_reg(i)(1), gw_clear_reg_we(i).asBool())
else 0.U) else 0.U)
//val intpriord = WireInit(Bool(), false.B) //val intpriord = WireInit(Bool(), false.B)
@ -178,8 +193,8 @@ class pic_ctrl extends Module with RequireAsyncReset with lib {
level_intpend_w_prior_en(0) := (0 until PIC_TOTAL_INT_PLUS1).map(i=> intpend_w_prior_en(i)) ++ IndexedSeq(0.U(4.W), 0.U(4.W), 0.U(4.W)) level_intpend_w_prior_en(0) := (0 until PIC_TOTAL_INT_PLUS1).map(i=> intpend_w_prior_en(i)) ++ IndexedSeq(0.U(4.W), 0.U(4.W), 0.U(4.W))
level_intpend_id(0) := (0 until PIC_TOTAL_INT_PLUS1).map(i=> intpend_id(i)) ++ IndexedSeq(0.U(8.W), 0.U(8.W), 0.U(8.W)) level_intpend_id(0) := (0 until PIC_TOTAL_INT_PLUS1).map(i=> intpend_id(i)) ++ IndexedSeq(0.U(8.W), 0.U(8.W), 0.U(8.W))
levelx_intpend_w_prior_en(NUM_LEVELS - NUM_LEVELS/2) := (0 to (PIC_TOTAL_INT_PLUS1/scala.math.pow(2,(NUM_LEVELS/2))).toInt).map(i=> l2_intpend_w_prior_en_ff(i)) ++ IndexedSeq(0.U(INTPRIORITY_BITS.W)) levelx_intpend_w_prior_en(NUM_LEVELS/2) := (0 until (PIC_TOTAL_INT_PLUS1/scala.math.pow(2,(NUM_LEVELS/2))).toInt).map(i=> l2_intpend_w_prior_en_ff(i)) ++ IndexedSeq(0.U(INTPRIORITY_BITS.W))
levelx_intpend_id(NUM_LEVELS - NUM_LEVELS/2) := (0 to (PIC_TOTAL_INT_PLUS1/scala.math.pow(2,(NUM_LEVELS/2))).toInt).map(i=> l2_intpend_id_ff(i)) ++ IndexedSeq(1.U(ID_BITS.W)) levelx_intpend_id(NUM_LEVELS/2) := (0 until (PIC_TOTAL_INT_PLUS1/scala.math.pow(2,(NUM_LEVELS/2))).toInt).map(i=> l2_intpend_id_ff(i)) ++ IndexedSeq(1.U(ID_BITS.W))
/// Do the prioritization of the interrupts here //////////// /// Do the prioritization of the interrupts here ////////////
for (l <-0 until NUM_LEVELS/2 ; m <- 0 to ((PIC_TOTAL_INT_PLUS1)/scala.math.pow(2,(l+1)).toInt)) { for (l <-0 until NUM_LEVELS/2 ; m <- 0 to ((PIC_TOTAL_INT_PLUS1)/scala.math.pow(2,(l+1)).toInt)) {
@ -196,8 +211,7 @@ class pic_ctrl extends Module with RequireAsyncReset with lib {
(0 to PIC_TOTAL_INT_PLUS1 / scala.math.pow(2,NUM_LEVELS/2).toInt).map(i => l2_intpend_w_prior_en_ff(i) := withClock(io.free_clk){RegNext(level_intpend_w_prior_en(NUM_LEVELS/2)(i))}) (0 to PIC_TOTAL_INT_PLUS1 / scala.math.pow(2,NUM_LEVELS/2).toInt).map(i => l2_intpend_w_prior_en_ff(i) := withClock(io.free_clk){RegNext(level_intpend_w_prior_en(NUM_LEVELS/2)(i))})
(0 to PIC_TOTAL_INT_PLUS1 / scala.math.pow(2,NUM_LEVELS/2).toInt).map(i => l2_intpend_id_ff(i) := withClock(io.free_clk){RegNext(level_intpend_id(NUM_LEVELS/2)(i))}) (0 to PIC_TOTAL_INT_PLUS1 / scala.math.pow(2,NUM_LEVELS/2).toInt).map(i => l2_intpend_id_ff(i) := withClock(io.free_clk){RegNext(level_intpend_id(NUM_LEVELS/2)(i))})
for (j <- 0 until (NUM_LEVELS - NUM_LEVELS/2) ) { for (j <-NUM_LEVELS/2 until NUM_LEVELS ; k <- 0 to ((PIC_TOTAL_INT_PLUS1)/math.pow(2,(j+1)).toInt)) {
for(k <- 0 to ((PIC_TOTAL_INT_PLUS1)/scala.math.pow(2,(j+1+3)).toInt)) {
if ( k == (PIC_TOTAL_INT_PLUS1)/scala.math.pow(2,(j+1)).toInt) { if ( k == (PIC_TOTAL_INT_PLUS1)/scala.math.pow(2,(j+1)).toInt) {
levelx_intpend_w_prior_en(j + 1)(k + 1) := 0.U levelx_intpend_w_prior_en(j + 1)(k + 1) := 0.U
@ -208,7 +222,6 @@ class pic_ctrl extends Module with RequireAsyncReset with lib {
(levelx_intpend_w_prior_en(j+1)(k)) := out_priority1 (levelx_intpend_w_prior_en(j+1)(k)) := out_priority1
} }
}
claimid_in := levelx_intpend_id(NUM_LEVELS - NUM_LEVELS/2)(0) // This is the last level output claimid_in := levelx_intpend_id(NUM_LEVELS - NUM_LEVELS/2)(0) // This is the last level output
selected_int_priority := levelx_intpend_w_prior_en(NUM_LEVELS - NUM_LEVELS/2)(0) selected_int_priority := levelx_intpend_w_prior_en(NUM_LEVELS - NUM_LEVELS/2)(0)
} }
@ -408,5 +421,7 @@ class pic_ctrl extends Module with RequireAsyncReset with lib {
} }
} }
object pic extends App { object pic extends App {
println((new ChiselStage).emitVerilog(new pic_ctrl))} println((new chisel3.stage.ChiselStage).emitVerilog(new pic_ctrl()))
}

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