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Debug rvoclk corrected

This commit is contained in:
​Laraib Khan 2021-02-04 18:00:41 +05:00
parent df4b1058f1
commit 11c09dc85b
4 changed files with 688 additions and 803 deletions
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@ -51735,7 +51735,6 @@ module csr_tlu(
input [30:0] io_dec_tlu_i0_pc_r,
input io_dec_tlu_i0_valid_r,
input io_dec_csr_any_unq_d,
output io_dec_tlu_misc_clk_override,
output io_dec_tlu_picio_clk_override,
output io_dec_tlu_dec_clk_override,
output io_dec_tlu_lsu_clk_override,
@ -53309,7 +53308,6 @@ module csr_tlu(
assign io_dec_tlu_perfcnt1 = perf_csrs_io_dec_tlu_perfcnt1; // @[dec_tlu_ctl.scala 2437:29]
assign io_dec_tlu_perfcnt2 = perf_csrs_io_dec_tlu_perfcnt2; // @[dec_tlu_ctl.scala 2438:29]
assign io_dec_tlu_perfcnt3 = perf_csrs_io_dec_tlu_perfcnt3; // @[dec_tlu_ctl.scala 2439:29]
assign io_dec_tlu_misc_clk_override = mcgc[8]; // @[dec_tlu_ctl.scala 1757:39]
assign io_dec_tlu_picio_clk_override = mcgc[9]; // @[dec_tlu_ctl.scala 1756:39]
assign io_dec_tlu_dec_clk_override = mcgc[7]; // @[dec_tlu_ctl.scala 1758:39]
assign io_dec_tlu_lsu_clk_override = mcgc[4]; // @[dec_tlu_ctl.scala 1760:39]
@ -55146,7 +55144,6 @@ module dec_tlu_ctl(
output [31:0] io_dec_tlu_mtval_wb1,
output io_dec_tlu_pipelining_disable,
output io_dec_tlu_trace_disable,
output io_dec_tlu_misc_clk_override,
output io_dec_tlu_dec_clk_override,
output io_dec_tlu_lsu_clk_override,
output io_dec_tlu_pic_clk_override,
@ -55443,7 +55440,6 @@ module dec_tlu_ctl(
wire [30:0] csr_io_dec_tlu_i0_pc_r; // @[dec_tlu_ctl.scala 283:23]
wire csr_io_dec_tlu_i0_valid_r; // @[dec_tlu_ctl.scala 283:23]
wire csr_io_dec_csr_any_unq_d; // @[dec_tlu_ctl.scala 283:23]
wire csr_io_dec_tlu_misc_clk_override; // @[dec_tlu_ctl.scala 283:23]
wire csr_io_dec_tlu_picio_clk_override; // @[dec_tlu_ctl.scala 283:23]
wire csr_io_dec_tlu_dec_clk_override; // @[dec_tlu_ctl.scala 283:23]
wire csr_io_dec_tlu_lsu_clk_override; // @[dec_tlu_ctl.scala 283:23]
@ -56507,7 +56503,6 @@ module dec_tlu_ctl(
.io_dec_tlu_i0_pc_r(csr_io_dec_tlu_i0_pc_r),
.io_dec_tlu_i0_valid_r(csr_io_dec_tlu_i0_valid_r),
.io_dec_csr_any_unq_d(csr_io_dec_csr_any_unq_d),
.io_dec_tlu_misc_clk_override(csr_io_dec_tlu_misc_clk_override),
.io_dec_tlu_picio_clk_override(csr_io_dec_tlu_picio_clk_override),
.io_dec_tlu_dec_clk_override(csr_io_dec_tlu_dec_clk_override),
.io_dec_tlu_lsu_clk_override(csr_io_dec_tlu_lsu_clk_override),
@ -56858,7 +56853,6 @@ module dec_tlu_ctl(
assign io_dec_tlu_mtval_wb1 = csr_io_dec_tlu_mtval_wb1; // @[dec_tlu_ctl.scala 886:46]
assign io_dec_tlu_pipelining_disable = csr_io_dec_tlu_pipelining_disable; // @[dec_tlu_ctl.scala 902:46]
assign io_dec_tlu_trace_disable = csr_io_dec_tlu_trace_disable; // @[dec_tlu_ctl.scala 911:49]
assign io_dec_tlu_misc_clk_override = csr_io_dec_tlu_misc_clk_override; // @[dec_tlu_ctl.scala 892:46]
assign io_dec_tlu_dec_clk_override = csr_io_dec_tlu_dec_clk_override; // @[dec_tlu_ctl.scala 894:46]
assign io_dec_tlu_lsu_clk_override = csr_io_dec_tlu_lsu_clk_override; // @[dec_tlu_ctl.scala 896:46]
assign io_dec_tlu_pic_clk_override = csr_io_dec_tlu_pic_clk_override; // @[dec_tlu_ctl.scala 898:46]
@ -58536,7 +58530,6 @@ module dec(
input io_dbg_halt_req,
input io_dbg_resume_req,
output io_dec_tlu_dbg_halted,
output io_dec_tlu_debug_mode,
output io_dec_tlu_resume_ack,
output io_dec_tlu_mpc_halted_only,
output [31:0] io_dec_dbg_rddata,
@ -58592,7 +58585,6 @@ module dec(
output [4:0] io_trace_rv_trace_pkt_rv_i_ecause_ip,
output io_trace_rv_trace_pkt_rv_i_interrupt_ip,
output [31:0] io_trace_rv_trace_pkt_rv_i_tval_ip,
output io_dec_tlu_misc_clk_override,
output io_dec_tlu_lsu_clk_override,
output io_dec_tlu_pic_clk_override,
output io_dec_tlu_picio_clk_override,
@ -59174,7 +59166,6 @@ module dec(
wire [31:0] tlu_io_dec_tlu_mtval_wb1; // @[dec.scala 133:19]
wire tlu_io_dec_tlu_pipelining_disable; // @[dec.scala 133:19]
wire tlu_io_dec_tlu_trace_disable; // @[dec.scala 133:19]
wire tlu_io_dec_tlu_misc_clk_override; // @[dec.scala 133:19]
wire tlu_io_dec_tlu_dec_clk_override; // @[dec.scala 133:19]
wire tlu_io_dec_tlu_lsu_clk_override; // @[dec.scala 133:19]
wire tlu_io_dec_tlu_pic_clk_override; // @[dec.scala 133:19]
@ -59650,7 +59641,6 @@ module dec(
.io_dec_tlu_mtval_wb1(tlu_io_dec_tlu_mtval_wb1),
.io_dec_tlu_pipelining_disable(tlu_io_dec_tlu_pipelining_disable),
.io_dec_tlu_trace_disable(tlu_io_dec_tlu_trace_disable),
.io_dec_tlu_misc_clk_override(tlu_io_dec_tlu_misc_clk_override),
.io_dec_tlu_dec_clk_override(tlu_io_dec_tlu_dec_clk_override),
.io_dec_tlu_lsu_clk_override(tlu_io_dec_tlu_lsu_clk_override),
.io_dec_tlu_pic_clk_override(tlu_io_dec_tlu_pic_clk_override),
@ -59740,7 +59730,6 @@ module dec(
assign io_mpc_debug_run_ack = tlu_io_mpc_debug_run_ack; // @[dec.scala 286:29]
assign io_debug_brkpt_status = tlu_io_debug_brkpt_status; // @[dec.scala 287:29]
assign io_dec_tlu_dbg_halted = tlu_io_dec_tlu_dbg_halted; // @[dec.scala 276:28]
assign io_dec_tlu_debug_mode = tlu_io_dec_tlu_debug_mode; // @[dec.scala 277:28]
assign io_dec_tlu_resume_ack = tlu_io_dec_tlu_resume_ack; // @[dec.scala 278:28]
assign io_dec_tlu_mpc_halted_only = tlu_io_dec_tlu_mpc_halted_only; // @[dec.scala 279:51]
assign io_dec_dbg_rddata = decode_io_dec_i0_wdata_r; // @[dec.scala 322:21]
@ -59795,7 +59784,6 @@ module dec(
assign io_trace_rv_trace_pkt_rv_i_ecause_ip = tlu_io_dec_tlu_exc_cause_wb1; // @[dec.scala 316:40]
assign io_trace_rv_trace_pkt_rv_i_interrupt_ip = tlu_io_dec_tlu_int_valid_wb1; // @[dec.scala 317:43]
assign io_trace_rv_trace_pkt_rv_i_tval_ip = tlu_io_dec_tlu_mtval_wb1; // @[dec.scala 318:38]
assign io_dec_tlu_misc_clk_override = tlu_io_dec_tlu_misc_clk_override; // @[dec.scala 298:35]
assign io_dec_tlu_lsu_clk_override = tlu_io_dec_tlu_lsu_clk_override; // @[dec.scala 300:36]
assign io_dec_tlu_pic_clk_override = tlu_io_dec_tlu_pic_clk_override; // @[dec.scala 302:36]
assign io_dec_tlu_picio_clk_override = tlu_io_dec_tlu_picio_clk_override; // @[dec.scala 305:36]
@ -60141,7 +60129,6 @@ module dbg(
input io_core_dbg_cmd_fail,
output io_dbg_halt_req,
output io_dbg_resume_req,
input io_dec_tlu_debug_mode,
input io_dec_tlu_dbg_halted,
input io_dec_tlu_mpc_halted_only,
input io_dec_tlu_resume_ack,
@ -60180,7 +60167,6 @@ module dbg(
input io_dbg_dma_dma_dbg_ready,
input io_dbg_bus_clk_en,
input io_dbg_rst_l,
input io_clk_override,
input io_scan_mode
);
`ifdef RANDOMIZE_REG_INIT
@ -60257,23 +60243,6 @@ module dbg(
wire [3:0] sb_abmem_cmd_size;
wire dmcontrol_wren_Q;
wire [31:0] abstractcs_reg;
wire _T = io_dmi_reg_en | execute_command; // @[dbg.scala 114:39]
wire _T_1 = dbg_state != 4'h0; // @[dbg.scala 114:70]
wire _T_2 = _T | _T_1; // @[dbg.scala 114:57]
wire _T_3 = _T_2 | dbg_state_en; // @[dbg.scala 114:88]
wire _T_4 = _T_3 | io_dec_tlu_dbg_halted; // @[dbg.scala 114:103]
wire _T_5 = _T_4 | io_dec_tlu_mpc_halted_only; // @[dbg.scala 114:127]
wire _T_6 = _T_5 | io_dec_tlu_debug_mode; // @[dbg.scala 115:32]
wire _T_7 = _T_6 | io_dbg_halt_req; // @[dbg.scala 115:56]
wire _T_9 = _T | sb_state_en; // @[dbg.scala 116:57]
wire _T_10 = sb_state != 4'h0; // @[dbg.scala 116:83]
wire _T_11 = _T_9 | _T_10; // @[dbg.scala 116:71]
wire rvclkhdr_io_l1clk; // @[lib.scala 343:22]
wire rvclkhdr_io_clk; // @[lib.scala 343:22]
wire rvclkhdr_io_en; // @[lib.scala 343:22]
wire rvclkhdr_1_io_l1clk; // @[lib.scala 343:22]
wire rvclkhdr_1_io_clk; // @[lib.scala 343:22]
wire rvclkhdr_1_io_en; // @[lib.scala 343:22]
wire _T_14 = dmcontrol_reg[0] | io_scan_mode; // @[dbg.scala 121:74]
wire dbg_dm_rst_l = io_dbg_rst_l & _T_14; // @[dbg.scala 121:103]
wire _T_17 = ~dmcontrol_reg[1]; // @[dbg.scala 122:32]
@ -60344,13 +60313,13 @@ module dbg(
wire [31:0] _T_115 = _T_114 & io_dmi_reg_wdata; // @[dbg.scala 158:55]
wire [31:0] _T_119 = _T_110 & sb_bus_rdata[63:32]; // @[dbg.scala 158:104]
wire [31:0] sbdata1_din = _T_115 | _T_119; // @[dbg.scala 158:74]
wire rvclkhdr_2_io_l1clk; // @[lib.scala 409:23]
wire rvclkhdr_2_io_clk; // @[lib.scala 409:23]
wire rvclkhdr_2_io_en; // @[lib.scala 409:23]
wire rvclkhdr_io_l1clk; // @[lib.scala 409:23]
wire rvclkhdr_io_clk; // @[lib.scala 409:23]
wire rvclkhdr_io_en; // @[lib.scala 409:23]
reg [31:0] sbdata0_reg; // @[Reg.scala 27:20]
wire rvclkhdr_3_io_l1clk; // @[lib.scala 409:23]
wire rvclkhdr_3_io_clk; // @[lib.scala 409:23]
wire rvclkhdr_3_io_en; // @[lib.scala 409:23]
wire rvclkhdr_1_io_l1clk; // @[lib.scala 409:23]
wire rvclkhdr_1_io_clk; // @[lib.scala 409:23]
wire rvclkhdr_1_io_en; // @[lib.scala 409:23]
reg [31:0] sbdata1_reg; // @[Reg.scala 27:20]
wire sbaddress0_reg_wren0 = _T_96 & _T_28; // @[dbg.scala 163:64]
wire sbaddress0_reg_wren = sbaddress0_reg_wren0 | sbaddress0_reg_wren1; // @[dbg.scala 164:52]
@ -60361,9 +60330,9 @@ module dbg(
wire [31:0] _T_129 = sbaddress0_reg + _T_127; // @[dbg.scala 166:54]
wire [31:0] _T_130 = _T_126 & _T_129; // @[dbg.scala 166:36]
wire [31:0] sbaddress0_reg_din = _T_124 | _T_130; // @[dbg.scala 165:81]
wire rvclkhdr_4_io_l1clk; // @[lib.scala 409:23]
wire rvclkhdr_4_io_clk; // @[lib.scala 409:23]
wire rvclkhdr_4_io_en; // @[lib.scala 409:23]
wire rvclkhdr_2_io_l1clk; // @[lib.scala 409:23]
wire rvclkhdr_2_io_clk; // @[lib.scala 409:23]
wire rvclkhdr_2_io_en; // @[lib.scala 409:23]
reg [31:0] _T_131; // @[Reg.scala 27:20]
wire sbreadonaddr_access = sbaddress0_reg_wren0 & sbcs_reg[20]; // @[dbg.scala 170:94]
wire _T_136 = ~io_dmi_reg_wr_en; // @[dbg.scala 171:45]
@ -60489,13 +60458,13 @@ module dbg(
wire [15:0] temp_command_din_31_16 = {io_dmi_reg_wdata[31:24],1'h0,io_dmi_reg_wdata[22:19],command_postexec_din,command_transfer_din,io_dmi_reg_wdata[16]}; // @[Cat.scala 29:58]
wire [15:0] temp_command_din_15_0 = command_wren ? io_dmi_reg_wdata[15:0] : dbg_cmd_next_addr[15:0]; // @[dbg.scala 253:37]
reg _T_361; // @[dbg.scala 257:12]
wire rvclkhdr_5_io_l1clk; // @[lib.scala 409:23]
wire rvclkhdr_5_io_clk; // @[lib.scala 409:23]
wire rvclkhdr_5_io_en; // @[lib.scala 409:23]
wire rvclkhdr_3_io_l1clk; // @[lib.scala 409:23]
wire rvclkhdr_3_io_clk; // @[lib.scala 409:23]
wire rvclkhdr_3_io_en; // @[lib.scala 409:23]
reg [15:0] temp_command_reg_31_16; // @[Reg.scala 27:20]
wire rvclkhdr_6_io_l1clk; // @[lib.scala 409:23]
wire rvclkhdr_6_io_clk; // @[lib.scala 409:23]
wire rvclkhdr_6_io_en; // @[lib.scala 409:23]
wire rvclkhdr_4_io_l1clk; // @[lib.scala 409:23]
wire rvclkhdr_4_io_clk; // @[lib.scala 409:23]
wire rvclkhdr_4_io_en; // @[lib.scala 409:23]
reg [15:0] temp_command_reg_15_0; // @[Reg.scala 27:20]
wire _T_367 = _T_96 & _T_219; // @[dbg.scala 266:58]
wire _T_368 = dbg_state == 4'h2; // @[dbg.scala 266:102]
@ -60515,9 +60484,9 @@ module dbg(
wire [31:0] _T_385 = data0_reg_wren2 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
wire [31:0] _T_387 = _T_385 & sb_bus_rdata[31:0]; // @[dbg.scala 272:31]
wire [31:0] data0_din = _T_383 | _T_387; // @[dbg.scala 271:52]
wire rvclkhdr_7_io_l1clk; // @[lib.scala 409:23]
wire rvclkhdr_7_io_clk; // @[lib.scala 409:23]
wire rvclkhdr_7_io_en; // @[lib.scala 409:23]
wire rvclkhdr_5_io_l1clk; // @[lib.scala 409:23]
wire rvclkhdr_5_io_clk; // @[lib.scala 409:23]
wire rvclkhdr_5_io_en; // @[lib.scala 409:23]
reg [31:0] data0_reg; // @[Reg.scala 27:20]
wire _T_390 = _T_96 & _T_221; // @[dbg.scala 277:59]
wire _T_392 = _T_390 & _T_368; // @[dbg.scala 277:92]
@ -60531,9 +60500,9 @@ module dbg(
wire [31:0] _T_408 = data1_reg_wren1 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
wire [31:0] _T_410 = _T_408 & dbg_cmd_next_addr; // @[dbg.scala 281:92]
wire [31:0] data1_din = _T_406 | _T_410; // @[dbg.scala 281:64]
wire rvclkhdr_8_io_l1clk; // @[lib.scala 409:23]
wire rvclkhdr_8_io_clk; // @[lib.scala 409:23]
wire rvclkhdr_8_io_en; // @[lib.scala 409:23]
wire rvclkhdr_6_io_l1clk; // @[lib.scala 409:23]
wire rvclkhdr_6_io_clk; // @[lib.scala 409:23]
wire rvclkhdr_6_io_en; // @[lib.scala 409:23]
reg [31:0] _T_411; // @[Reg.scala 27:20]
reg sb_abmem_cmd_done; // @[Reg.scala 27:20]
reg sb_abmem_data_done; // @[Reg.scala 27:20]
@ -60699,9 +60668,9 @@ module dbg(
wire _T_595 = io_dbg_rst_l & _T_14; // @[dbg.scala 385:68]
wire _T_597 = _T_595 & reset; // @[dbg.scala 385:95]
reg [3:0] _T_598; // @[Reg.scala 27:20]
wire rvclkhdr_9_io_l1clk; // @[lib.scala 409:23]
wire rvclkhdr_9_io_clk; // @[lib.scala 409:23]
wire rvclkhdr_9_io_en; // @[lib.scala 409:23]
wire rvclkhdr_7_io_l1clk; // @[lib.scala 409:23]
wire rvclkhdr_7_io_clk; // @[lib.scala 409:23]
wire rvclkhdr_7_io_en; // @[lib.scala 409:23]
reg [31:0] _T_599; // @[Reg.scala 27:20]
wire _T_600 = abmem_addr_in_dccm_region | abmem_addr_in_iccm_region; // @[dbg.scala 392:58]
wire abmem_addr_core_local = _T_600 | abmem_addr_in_pic_region; // @[dbg.scala 392:86]
@ -60883,12 +60852,12 @@ module dbg(
wire [63:0] _T_871 = _T_805 & _T_870; // @[dbg.scala 558:40]
wire [63:0] _T_872 = _T_862 | _T_871; // @[dbg.scala 557:121]
wire [63:0] _T_877 = _T_812 & io_sb_axi_r_bits_data; // @[dbg.scala 559:40]
rvclkhdr rvclkhdr ( // @[lib.scala 343:22]
rvclkhdr rvclkhdr ( // @[lib.scala 409:23]
.io_l1clk(rvclkhdr_io_l1clk),
.io_clk(rvclkhdr_io_clk),
.io_en(rvclkhdr_io_en)
);
rvclkhdr rvclkhdr_1 ( // @[lib.scala 343:22]
rvclkhdr rvclkhdr_1 ( // @[lib.scala 409:23]
.io_l1clk(rvclkhdr_1_io_l1clk),
.io_clk(rvclkhdr_1_io_clk),
.io_en(rvclkhdr_1_io_en)
@ -60923,16 +60892,6 @@ module dbg(
.io_clk(rvclkhdr_7_io_clk),
.io_en(rvclkhdr_7_io_en)
);
rvclkhdr rvclkhdr_8 ( // @[lib.scala 409:23]
.io_l1clk(rvclkhdr_8_io_l1clk),
.io_clk(rvclkhdr_8_io_clk),
.io_en(rvclkhdr_8_io_en)
);
rvclkhdr rvclkhdr_9 ( // @[lib.scala 409:23]
.io_l1clk(rvclkhdr_9_io_l1clk),
.io_clk(rvclkhdr_9_io_clk),
.io_en(rvclkhdr_9_io_en)
);
assign io_dbg_cmd_size = command_reg[21:20]; // @[dbg.scala 405:21]
assign io_dbg_core_rst_l = _T_17 | io_scan_mode; // @[dbg.scala 122:28]
assign io_dbg_halt_req = _T_412 ? dmcontrol_reg[31] : _GEN_90; // @[dbg.scala 294:25 dbg.scala 306:23 dbg.scala 311:23 dbg.scala 321:29 dbg.scala 326:23 dbg.scala 331:23 dbg.scala 336:23 dbg.scala 345:29 dbg.scala 352:25 dbg.scala 359:29 dbg.scala 364:29 dbg.scala 369:23]
@ -61002,27 +60961,23 @@ module dbg(
assign sb_abmem_cmd_size = {{1'd0}, _T_737}; // @[dbg.scala 488:34]
assign dmcontrol_wren_Q = _T_163; // @[dbg.scala 183:21]
assign abstractcs_reg = {_T_313,_T_311}; // @[dbg.scala 238:20]
assign rvclkhdr_io_clk = clock; // @[lib.scala 344:17]
assign rvclkhdr_io_en = _T_7 | io_clk_override; // @[lib.scala 345:16]
assign rvclkhdr_1_io_clk = clock; // @[lib.scala 344:17]
assign rvclkhdr_1_io_en = _T_11 | io_clk_override; // @[lib.scala 345:16]
assign rvclkhdr_io_clk = clock; // @[lib.scala 411:18]
assign rvclkhdr_io_en = sbdata0_reg_wren0 | sbdata0_reg_wren1; // @[lib.scala 412:17]
assign rvclkhdr_1_io_clk = clock; // @[lib.scala 411:18]
assign rvclkhdr_1_io_en = sbdata1_reg_wren0 | sbdata0_reg_wren1; // @[lib.scala 412:17]
assign rvclkhdr_2_io_clk = clock; // @[lib.scala 411:18]
assign rvclkhdr_2_io_en = sbdata0_reg_wren0 | sbdata0_reg_wren1; // @[lib.scala 412:17]
assign rvclkhdr_2_io_en = sbaddress0_reg_wren0 | sbaddress0_reg_wren1; // @[lib.scala 412:17]
assign rvclkhdr_3_io_clk = clock; // @[lib.scala 411:18]
assign rvclkhdr_3_io_en = sbdata1_reg_wren0 | sbdata0_reg_wren1; // @[lib.scala 412:17]
assign rvclkhdr_3_io_en = command_wren; // @[lib.scala 412:17]
assign rvclkhdr_4_io_clk = clock; // @[lib.scala 411:18]
assign rvclkhdr_4_io_en = sbaddress0_reg_wren0 | sbaddress0_reg_wren1; // @[lib.scala 412:17]
assign rvclkhdr_4_io_en = command_wren | _T_344; // @[lib.scala 412:17]
assign rvclkhdr_5_io_clk = clock; // @[lib.scala 411:18]
assign rvclkhdr_5_io_en = command_wren; // @[lib.scala 412:17]
assign rvclkhdr_5_io_en = _T_376 | data0_reg_wren2; // @[lib.scala 412:17]
assign rvclkhdr_6_io_clk = clock; // @[lib.scala 411:18]
assign rvclkhdr_6_io_en = command_wren | _T_344; // @[lib.scala 412:17]
assign rvclkhdr_7_io_clk = clock; // @[lib.scala 411:18]
assign rvclkhdr_7_io_en = _T_376 | data0_reg_wren2; // @[lib.scala 412:17]
assign rvclkhdr_8_io_clk = clock; // @[lib.scala 411:18]
assign rvclkhdr_8_io_en = data1_reg_wren0 | data1_reg_wren1; // @[lib.scala 412:17]
assign rvclkhdr_6_io_en = data1_reg_wren0 | data1_reg_wren1; // @[lib.scala 412:17]
assign dbg_nxtstate = _T_412 ? _T_415 : _GEN_88; // @[dbg.scala 290:25 dbg.scala 304:23 dbg.scala 309:23 dbg.scala 314:20 dbg.scala 324:23 dbg.scala 329:23 dbg.scala 334:23 dbg.scala 343:29 dbg.scala 348:25 dbg.scala 355:29 dbg.scala 367:20]
assign rvclkhdr_9_io_clk = clock; // @[lib.scala 411:18]
assign rvclkhdr_9_io_en = io_dmi_reg_en; // @[lib.scala 412:17]
assign rvclkhdr_7_io_clk = clock; // @[lib.scala 411:18]
assign rvclkhdr_7_io_en = io_dmi_reg_en; // @[lib.scala 412:17]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
@ -61200,35 +61155,35 @@ end // initial
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
always @(posedge rvclkhdr_1_io_l1clk or posedge dbg_dm_rst_l) begin
always @(posedge clock or posedge dbg_dm_rst_l) begin
if (dbg_dm_rst_l) begin
temp_sbcs_22 <= 1'h0;
end else if (sbcs_sbbusyerror_wren) begin
temp_sbcs_22 <= sbcs_sbbusyerror_din;
end
end
always @(posedge rvclkhdr_1_io_l1clk or posedge dbg_dm_rst_l) begin
always @(posedge clock or posedge dbg_dm_rst_l) begin
if (dbg_dm_rst_l) begin
temp_sbcs_21 <= 1'h0;
end else if (sbcs_sbbusy_wren) begin
temp_sbcs_21 <= sbcs_sbbusy_din;
end
end
always @(posedge rvclkhdr_1_io_l1clk or posedge dbg_dm_rst_l) begin
always @(posedge clock or posedge dbg_dm_rst_l) begin
if (dbg_dm_rst_l) begin
temp_sbcs_20 <= 1'h0;
end else if (sbcs_wren) begin
temp_sbcs_20 <= io_dmi_reg_wdata[20];
end
end
always @(posedge rvclkhdr_1_io_l1clk or posedge dbg_dm_rst_l) begin
always @(posedge clock or posedge dbg_dm_rst_l) begin
if (dbg_dm_rst_l) begin
temp_sbcs_19_15 <= 5'h0;
end else if (sbcs_wren) begin
temp_sbcs_19_15 <= _T_43;
end
end
always @(posedge rvclkhdr_1_io_l1clk or posedge dbg_dm_rst_l) begin
always @(posedge clock or posedge dbg_dm_rst_l) begin
if (dbg_dm_rst_l) begin
temp_sbcs_14_12 <= 3'h0;
end else if (sbcs_sberror_wren) begin
@ -61284,49 +61239,49 @@ end // initial
_T_131 <= sbaddress0_reg_din;
end
end
always @(posedge rvclkhdr_io_l1clk or posedge dbg_dm_rst_l) begin
always @(posedge clock or posedge dbg_dm_rst_l) begin
if (dbg_dm_rst_l) begin
dm_temp <= 4'h0;
end else if (dmcontrol_wren) begin
dm_temp <= _T_154;
end
end
always @(posedge rvclkhdr_io_l1clk or posedge io_dbg_rst_l) begin
always @(posedge clock or posedge io_dbg_rst_l) begin
if (io_dbg_rst_l) begin
dm_temp_0 <= 1'h0;
end else if (dmcontrol_wren) begin
dm_temp_0 <= io_dmi_reg_wdata[0];
end
end
always @(posedge rvclkhdr_io_l1clk or posedge dbg_dm_rst_l) begin
always @(posedge clock or posedge dbg_dm_rst_l) begin
if (dbg_dm_rst_l) begin
_T_163 <= 1'h0;
end else begin
_T_163 <= _T_144 & io_dmi_reg_wr_en;
end
end
always @(posedge rvclkhdr_io_l1clk or posedge dbg_dm_rst_l) begin
always @(posedge clock or posedge dbg_dm_rst_l) begin
if (dbg_dm_rst_l) begin
_T_202 <= 1'h0;
end else if (dmstatus_resumeack_wren) begin
_T_202 <= _T_184;
end
end
always @(posedge rvclkhdr_io_l1clk or posedge dbg_dm_rst_l) begin
always @(posedge clock or posedge dbg_dm_rst_l) begin
if (dbg_dm_rst_l) begin
_T_205 <= 1'h0;
end else begin
_T_205 <= io_dec_tlu_dbg_halted & _T_203;
end
end
always @(posedge rvclkhdr_io_l1clk or posedge reset) begin
always @(posedge clock or posedge reset) begin
if (reset) begin
_T_206 <= 1'h0;
end else begin
_T_206 <= dmstatus_haveresetn_wren | _T_206;
end
end
always @(posedge rvclkhdr_io_l1clk or posedge dbg_dm_rst_l) begin
always @(posedge clock or posedge dbg_dm_rst_l) begin
if (dbg_dm_rst_l) begin
abs_temp_12 <= 1'h0;
end else if (abstractcs_busy_wren) begin
@ -61339,7 +61294,7 @@ end // initial
end
end
end
always @(posedge rvclkhdr_io_l1clk or posedge dbg_dm_rst_l) begin
always @(posedge clock or posedge dbg_dm_rst_l) begin
if (dbg_dm_rst_l) begin
abs_temp_10_8 <= 3'h0;
end else if (abstractcs_error_sel0) begin
@ -61360,14 +61315,14 @@ end // initial
abs_temp_10_8 <= abstractcs_reg[10:8];
end
end
always @(posedge rvclkhdr_io_l1clk or posedge dbg_dm_rst_l) begin
always @(posedge clock or posedge dbg_dm_rst_l) begin
if (dbg_dm_rst_l) begin
abstractauto_reg <= 2'h0;
end else if (abstractauto_reg_wren) begin
abstractauto_reg <= io_dmi_reg_wdata[1:0];
end
end
always @(posedge rvclkhdr_io_l1clk or posedge dbg_dm_rst_l) begin
always @(posedge clock or posedge dbg_dm_rst_l) begin
if (dbg_dm_rst_l) begin
_T_361 <= 1'h0;
end else begin
@ -61402,7 +61357,7 @@ end // initial
_T_411 <= data1_din;
end
end
always @(posedge rvclkhdr_io_l1clk or posedge dbg_dm_rst_l) begin
always @(posedge clock or posedge dbg_dm_rst_l) begin
if (dbg_dm_rst_l) begin
sb_abmem_cmd_done <= 1'h0;
end else if (sb_abmem_cmd_done_en) begin
@ -61423,7 +61378,7 @@ end // initial
end
end
end
always @(posedge rvclkhdr_io_l1clk or posedge dbg_dm_rst_l) begin
always @(posedge clock or posedge dbg_dm_rst_l) begin
if (dbg_dm_rst_l) begin
sb_abmem_data_done <= 1'h0;
end else if (sb_abmem_data_done_en) begin
@ -61444,7 +61399,7 @@ end // initial
end
end
end
always @(posedge rvclkhdr_io_l1clk or posedge _T_597) begin
always @(posedge clock or posedge _T_597) begin
if (_T_597) begin
_T_598 <= 4'h0;
end else if (dbg_state_en) begin
@ -61502,7 +61457,7 @@ end // initial
_T_599 <= dmi_reg_rdata_din;
end
end
always @(posedge rvclkhdr_1_io_l1clk or posedge dbg_dm_rst_l) begin
always @(posedge clock or posedge dbg_dm_rst_l) begin
if (dbg_dm_rst_l) begin
_T_734 <= 4'h0;
end else if (sb_state_en) begin
@ -82471,7 +82426,6 @@ module quasar(
wire dec_io_dbg_halt_req; // @[quasar.scala 77:19]
wire dec_io_dbg_resume_req; // @[quasar.scala 77:19]
wire dec_io_dec_tlu_dbg_halted; // @[quasar.scala 77:19]
wire dec_io_dec_tlu_debug_mode; // @[quasar.scala 77:19]
wire dec_io_dec_tlu_resume_ack; // @[quasar.scala 77:19]
wire dec_io_dec_tlu_mpc_halted_only; // @[quasar.scala 77:19]
wire [31:0] dec_io_dec_dbg_rddata; // @[quasar.scala 77:19]
@ -82527,7 +82481,6 @@ module quasar(
wire [4:0] dec_io_trace_rv_trace_pkt_rv_i_ecause_ip; // @[quasar.scala 77:19]
wire dec_io_trace_rv_trace_pkt_rv_i_interrupt_ip; // @[quasar.scala 77:19]
wire [31:0] dec_io_trace_rv_trace_pkt_rv_i_tval_ip; // @[quasar.scala 77:19]
wire dec_io_dec_tlu_misc_clk_override; // @[quasar.scala 77:19]
wire dec_io_dec_tlu_lsu_clk_override; // @[quasar.scala 77:19]
wire dec_io_dec_tlu_pic_clk_override; // @[quasar.scala 77:19]
wire dec_io_dec_tlu_picio_clk_override; // @[quasar.scala 77:19]
@ -82728,7 +82681,6 @@ module quasar(
wire dbg_io_core_dbg_cmd_fail; // @[quasar.scala 78:19]
wire dbg_io_dbg_halt_req; // @[quasar.scala 78:19]
wire dbg_io_dbg_resume_req; // @[quasar.scala 78:19]
wire dbg_io_dec_tlu_debug_mode; // @[quasar.scala 78:19]
wire dbg_io_dec_tlu_dbg_halted; // @[quasar.scala 78:19]
wire dbg_io_dec_tlu_mpc_halted_only; // @[quasar.scala 78:19]
wire dbg_io_dec_tlu_resume_ack; // @[quasar.scala 78:19]
@ -82767,7 +82719,6 @@ module quasar(
wire dbg_io_dbg_dma_dma_dbg_ready; // @[quasar.scala 78:19]
wire dbg_io_dbg_bus_clk_en; // @[quasar.scala 78:19]
wire dbg_io_dbg_rst_l; // @[quasar.scala 78:19]
wire dbg_io_clk_override; // @[quasar.scala 78:19]
wire dbg_io_scan_mode; // @[quasar.scala 78:19]
wire exu_clock; // @[quasar.scala 79:19]
wire exu_reset; // @[quasar.scala 79:19]
@ -83305,7 +83256,6 @@ module quasar(
.io_dbg_halt_req(dec_io_dbg_halt_req),
.io_dbg_resume_req(dec_io_dbg_resume_req),
.io_dec_tlu_dbg_halted(dec_io_dec_tlu_dbg_halted),
.io_dec_tlu_debug_mode(dec_io_dec_tlu_debug_mode),
.io_dec_tlu_resume_ack(dec_io_dec_tlu_resume_ack),
.io_dec_tlu_mpc_halted_only(dec_io_dec_tlu_mpc_halted_only),
.io_dec_dbg_rddata(dec_io_dec_dbg_rddata),
@ -83361,7 +83311,6 @@ module quasar(
.io_trace_rv_trace_pkt_rv_i_ecause_ip(dec_io_trace_rv_trace_pkt_rv_i_ecause_ip),
.io_trace_rv_trace_pkt_rv_i_interrupt_ip(dec_io_trace_rv_trace_pkt_rv_i_interrupt_ip),
.io_trace_rv_trace_pkt_rv_i_tval_ip(dec_io_trace_rv_trace_pkt_rv_i_tval_ip),
.io_dec_tlu_misc_clk_override(dec_io_dec_tlu_misc_clk_override),
.io_dec_tlu_lsu_clk_override(dec_io_dec_tlu_lsu_clk_override),
.io_dec_tlu_pic_clk_override(dec_io_dec_tlu_pic_clk_override),
.io_dec_tlu_picio_clk_override(dec_io_dec_tlu_picio_clk_override),
@ -83564,7 +83513,6 @@ module quasar(
.io_core_dbg_cmd_fail(dbg_io_core_dbg_cmd_fail),
.io_dbg_halt_req(dbg_io_dbg_halt_req),
.io_dbg_resume_req(dbg_io_dbg_resume_req),
.io_dec_tlu_debug_mode(dbg_io_dec_tlu_debug_mode),
.io_dec_tlu_dbg_halted(dbg_io_dec_tlu_dbg_halted),
.io_dec_tlu_mpc_halted_only(dbg_io_dec_tlu_mpc_halted_only),
.io_dec_tlu_resume_ack(dbg_io_dec_tlu_resume_ack),
@ -83603,7 +83551,6 @@ module quasar(
.io_dbg_dma_dma_dbg_ready(dbg_io_dbg_dma_dma_dbg_ready),
.io_dbg_bus_clk_en(dbg_io_dbg_bus_clk_en),
.io_dbg_rst_l(dbg_io_dbg_rst_l),
.io_clk_override(dbg_io_clk_override),
.io_scan_mode(dbg_io_scan_mode)
);
exu exu ( // @[quasar.scala 79:19]
@ -84333,7 +84280,6 @@ module quasar(
assign dbg_io_core_dbg_rddata = dma_ctrl_io_dma_dbg_cmd_done ? dma_ctrl_io_dma_dbg_rddata : dec_io_dec_dbg_rddata; // @[quasar.scala 195:26]
assign dbg_io_core_dbg_cmd_done = dma_ctrl_io_dma_dbg_cmd_done | dec_io_dec_dbg_cmd_done; // @[quasar.scala 196:28]
assign dbg_io_core_dbg_cmd_fail = dma_ctrl_io_dma_dbg_cmd_fail | dec_io_dec_dbg_cmd_fail; // @[quasar.scala 197:28]
assign dbg_io_dec_tlu_debug_mode = dec_io_dec_tlu_debug_mode; // @[quasar.scala 198:29]
assign dbg_io_dec_tlu_dbg_halted = dec_io_dec_tlu_dbg_halted; // @[quasar.scala 199:29]
assign dbg_io_dec_tlu_mpc_halted_only = dec_io_dec_tlu_mpc_halted_only; // @[quasar.scala 200:34]
assign dbg_io_dec_tlu_resume_ack = dec_io_dec_tlu_resume_ack; // @[quasar.scala 201:29]
@ -84352,7 +84298,6 @@ module quasar(
assign dbg_io_dbg_dma_dma_dbg_ready = dma_ctrl_io_dbg_dma_dma_dbg_ready; // @[quasar.scala 221:23]
assign dbg_io_dbg_bus_clk_en = io_dbg_bus_clk_en; // @[quasar.scala 206:25]
assign dbg_io_dbg_rst_l = io_dbg_rst_l; // @[quasar.scala 207:20]
assign dbg_io_clk_override = dec_io_dec_tlu_misc_clk_override; // @[quasar.scala 208:23]
assign dbg_io_scan_mode = io_scan_mode; // @[quasar.scala 209:20]
assign exu_clock = io_active_l2clk; // @[quasar.scala 170:13]
assign exu_reset = io_core_rst_l; // @[quasar.scala 169:13]

4
src/main/scala/dbg/dbg.scala
View File

@ -115,8 +115,8 @@ class dbg extends Module with lib with RequireAsyncReset {
io.dec_tlu_mpc_halted_only | io.dec_tlu_debug_mode | io.dbg_halt_req | io.clk_override
val sb_free_clken = io.dmi_reg_en | execute_command | sb_state_en | (sb_state =/= sb_state_t.sbidle) | io.clk_override;
val dbg_free_clk = rvclkhdr(clock, dbg_free_clken, io.scan_mode) // dbg_free_cgc
val sb_free_clk = rvclkhdr(clock, sb_free_clken, io.scan_mode) // sb_free_cgc
val dbg_free_clk = rvoclkhdr(clock, dbg_free_clken, io.scan_mode) // dbg_free_cgc
val sb_free_clk = rvoclkhdr(clock, sb_free_clken, io.scan_mode) // sb_free_cgc
val dbg_dm_rst_l = (io.dbg_rst_l.asBool() & (dmcontrol_reg(0) | io.scan_mode)).asAsyncReset()
io.dbg_core_rst_l := (!dmcontrol_reg(1)).asBool() | io.scan_mode

BIN
target/scala-2.12/classes/dbg/dbg.class
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