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EXU integrated

This commit is contained in:
waleed-lm 2020-11-10 18:21:45 +05:00
parent 1f7988a179
commit 3e23edf4e3
96 changed files with 8616 additions and 129 deletions
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113
axi4_to_ahb.anno.json Normal file
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[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_bvalid",
"sources":[
"~axi4_to_ahb|axi4_to_ahb>io_axi_bready",
"~axi4_to_ahb|axi4_to_ahb>io_axi_rready",
"~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~axi4_to_ahb|axi4_to_ahb>io_ahb_htrans",
"sources":[
"~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid",
"~axi4_to_ahb|axi4_to_ahb>io_axi_bready",
"~axi4_to_ahb|axi4_to_ahb>io_axi_rready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_wready",
"sources":[
"~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid",
"~axi4_to_ahb|axi4_to_ahb>io_axi_bready",
"~axi4_to_ahb|axi4_to_ahb>io_axi_rready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~axi4_to_ahb|axi4_to_ahb>io_ahb_hwrite",
"sources":[
"~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid",
"~axi4_to_ahb|axi4_to_ahb>io_axi_bready",
"~axi4_to_ahb|axi4_to_ahb>io_axi_rready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~axi4_to_ahb|axi4_to_ahb>io_ahb_haddr",
"sources":[
"~axi4_to_ahb|axi4_to_ahb>io_axi_araddr",
"~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid",
"~axi4_to_ahb|axi4_to_ahb>io_axi_bready",
"~axi4_to_ahb|axi4_to_ahb>io_axi_rready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~axi4_to_ahb|axi4_to_ahb>io_ahb_hsize",
"sources":[
"~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid",
"~axi4_to_ahb|axi4_to_ahb>io_axi_arsize",
"~axi4_to_ahb|axi4_to_ahb>io_axi_bready",
"~axi4_to_ahb|axi4_to_ahb>io_axi_rready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_awready",
"sources":[
"~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid",
"~axi4_to_ahb|axi4_to_ahb>io_axi_bready",
"~axi4_to_ahb|axi4_to_ahb>io_axi_rready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_arready",
"sources":[
"~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid",
"~axi4_to_ahb|axi4_to_ahb>io_axi_bready",
"~axi4_to_ahb|axi4_to_ahb>io_axi_rready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_rvalid",
"sources":[
"~axi4_to_ahb|axi4_to_ahb>io_axi_bready",
"~axi4_to_ahb|axi4_to_ahb>io_axi_rready",
"~axi4_to_ahb|axi4_to_ahb>io_axi_arvalid"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~axi4_to_ahb|axi4_to_ahb>io_ahb_hprot",
"sources":[
"~axi4_to_ahb|axi4_to_ahb>io_axi_arprot"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"axi4_to_ahb.TEC_RV_ICG",
"resourceId":"/vsrc/TEC_RV_ICG.v"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"axi4_to_ahb"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

1288
axi4_to_ahb.fir Normal file
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438
axi4_to_ahb.v Normal file
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module rvclkhdr(
output io_l1clk,
input io_clk,
input io_en,
input io_scan_mode
);
wire clkhdr_Q; // @[el2_lib.scala 474:26]
wire clkhdr_CK; // @[el2_lib.scala 474:26]
wire clkhdr_EN; // @[el2_lib.scala 474:26]
wire clkhdr_SE; // @[el2_lib.scala 474:26]
TEC_RV_ICG clkhdr ( // @[el2_lib.scala 474:26]
.Q(clkhdr_Q),
.CK(clkhdr_CK),
.EN(clkhdr_EN),
.SE(clkhdr_SE)
);
assign io_l1clk = clkhdr_Q; // @[el2_lib.scala 475:14]
assign clkhdr_CK = io_clk; // @[el2_lib.scala 476:18]
assign clkhdr_EN = io_en; // @[el2_lib.scala 477:18]
assign clkhdr_SE = io_scan_mode; // @[el2_lib.scala 478:18]
endmodule
module axi4_to_ahb(
input clock,
input reset,
input io_scan_mode,
input io_bus_clk_en,
input io_clk_override,
input io_axi_awvalid,
input io_axi_awid,
input [31:0] io_axi_awaddr,
input [2:0] io_axi_awsize,
input [2:0] io_axi_awprot,
input io_axi_wvalid,
input [63:0] io_axi_wdata,
input [7:0] io_axi_wstrb,
input io_axi_wlast,
input io_axi_bready,
input io_axi_arvalid,
input io_axi_arid,
input [31:0] io_axi_araddr,
input [2:0] io_axi_arsize,
input [2:0] io_axi_arprot,
input io_axi_rready,
input [63:0] io_ahb_hrdata,
input io_ahb_hready,
input io_ahb_hresp,
output io_axi_awready,
output io_axi_wready,
output io_axi_bvalid,
output [1:0] io_axi_bresp,
output io_axi_bid,
output io_axi_arready,
output io_axi_rvalid,
output io_axi_rid,
output [31:0] io_axi_rdata,
output [1:0] io_axi_rresp,
output io_axi_rlast,
output [31:0] io_ahb_haddr,
output [2:0] io_ahb_hburst,
output io_ahb_hmastlock,
output [3:0] io_ahb_hprot,
output [2:0] io_ahb_hsize,
output [1:0] io_ahb_htrans,
output io_ahb_hwrite,
output [63:0] io_ahb_hwdata
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [31:0] _RAND_1;
reg [31:0] _RAND_2;
reg [31:0] _RAND_3;
reg [31:0] _RAND_4;
reg [31:0] _RAND_5;
reg [63:0] _RAND_6;
reg [63:0] _RAND_7;
reg [63:0] _RAND_8;
reg [31:0] _RAND_9;
reg [31:0] _RAND_10;
`endif // RANDOMIZE_REG_INIT
wire rvclkhdr_io_l1clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_io_clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_io_en; // @[el2_lib.scala 483:22]
wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 483:22]
wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_1_io_clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_1_io_en; // @[el2_lib.scala 483:22]
wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 483:22]
wire rvclkhdr_2_io_l1clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_2_io_clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_2_io_en; // @[el2_lib.scala 483:22]
wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 483:22]
wire rvclkhdr_3_io_l1clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_3_io_clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_3_io_en; // @[el2_lib.scala 483:22]
wire rvclkhdr_3_io_scan_mode; // @[el2_lib.scala 483:22]
wire rvclkhdr_4_io_l1clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_4_io_clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_4_io_en; // @[el2_lib.scala 483:22]
wire rvclkhdr_4_io_scan_mode; // @[el2_lib.scala 483:22]
wire rvclkhdr_5_io_l1clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_5_io_clk; // @[el2_lib.scala 483:22]
wire rvclkhdr_5_io_en; // @[el2_lib.scala 483:22]
wire rvclkhdr_5_io_scan_mode; // @[el2_lib.scala 483:22]
reg [2:0] buf_nxtstate; // @[axi4_to_ahb.scala 63:29]
wire wrbuf_en = io_axi_awvalid & io_axi_awready; // @[axi4_to_ahb.scala 183:30]
wire bus_clk = rvclkhdr_io_l1clk; // @[axi4_to_ahb.scala 83:21 axi4_to_ahb.scala 216:11]
reg wrbuf_vld; // @[Reg.scala 27:20]
reg wrbuf_data_vld; // @[Reg.scala 27:20]
wire wr_cmd_vld = wrbuf_vld & wrbuf_data_vld; // @[axi4_to_ahb.scala 193:27]
wire master_valid = wr_cmd_vld | io_axi_arvalid; // @[axi4_to_ahb.scala 194:30]
wire [1:0] _T_28 = wr_cmd_vld ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 196:20]
wire [2:0] master_opc = {{1'd0}, _T_28}; // @[axi4_to_ahb.scala 196:14]
wire _T_149 = master_opc[2:1] == 2'h1; // @[axi4_to_ahb.scala 252:89]
wire _T_150 = master_valid & _T_149; // @[axi4_to_ahb.scala 252:70]
wire _T_151 = ~_T_150; // @[axi4_to_ahb.scala 252:55]
wire wrbuf_data_en = io_axi_wvalid & io_axi_wready; // @[axi4_to_ahb.scala 184:34]
wire _T_8 = ~wrbuf_en; // @[axi4_to_ahb.scala 186:33]
wire wrbuf_rst = _T_150 & _T_8; // @[axi4_to_ahb.scala 186:31]
wire _T_11 = wrbuf_vld & _T_151; // @[axi4_to_ahb.scala 188:33]
wire _T_15 = wrbuf_data_vld & _T_151; // @[axi4_to_ahb.scala 189:37]
reg [31:0] wrbuf_addr; // @[Reg.scala 27:20]
wire [31:0] master_addr = wr_cmd_vld ? wrbuf_addr : io_axi_araddr; // @[axi4_to_ahb.scala 197:21]
reg [2:0] wrbuf_size; // @[Reg.scala 27:20]
wire [2:0] master_size = wr_cmd_vld ? wrbuf_size : io_axi_arsize; // @[axi4_to_ahb.scala 198:21]
reg [7:0] wrbuf_byteen; // @[Reg.scala 27:20]
reg [63:0] wrbuf_data; // @[Reg.scala 27:20]
wire buf_clk = rvclkhdr_2_io_l1clk; // @[axi4_to_ahb.scala 151:21 axi4_to_ahb.scala 433:11]
reg [63:0] buf_data; // @[Reg.scala 27:20]
wire ahbm_data_clk = rvclkhdr_5_io_l1clk; // @[axi4_to_ahb.scala 155:27 axi4_to_ahb.scala 436:17]
reg [63:0] ahb_hrdata_q; // @[axi4_to_ahb.scala 425:12]
wire _T_60 = wrbuf_en | wrbuf_data_en; // @[axi4_to_ahb.scala 214:74]
wire _T_69 = buf_nxtstate == 3'h2; // @[axi4_to_ahb.scala 230:54]
wire buf_data_wr_en = master_valid & _T_69; // @[axi4_to_ahb.scala 230:38]
wire [2:0] _T_100 = wrbuf_byteen[7] ? 3'h7 : 3'h0; // @[Mux.scala 98:16]
wire [2:0] _T_101 = wrbuf_byteen[6] ? 3'h6 : _T_100; // @[Mux.scala 98:16]
wire [2:0] _T_102 = wrbuf_byteen[5] ? 3'h5 : _T_101; // @[Mux.scala 98:16]
wire [2:0] _T_103 = wrbuf_byteen[4] ? 3'h4 : _T_102; // @[Mux.scala 98:16]
wire [2:0] _T_104 = wrbuf_byteen[3] ? 3'h3 : _T_103; // @[Mux.scala 98:16]
wire [2:0] _T_105 = wrbuf_byteen[2] ? 3'h2 : _T_104; // @[Mux.scala 98:16]
wire [2:0] _T_106 = wrbuf_byteen[1] ? 3'h1 : _T_105; // @[Mux.scala 98:16]
wire [2:0] _T_107 = wrbuf_byteen[0] ? 3'h0 : _T_106; // @[Mux.scala 98:16]
wire [2:0] buf_cmd_byte_ptr = _T_149 ? _T_107 : master_addr[2:0]; // @[axi4_to_ahb.scala 233:30]
wire [1:0] _T_113 = master_valid ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire _T_117 = master_opc == 3'h0; // @[axi4_to_ahb.scala 240:61]
reg [31:0] buf_addr; // @[Reg.scala 27:20]
wire _T_540 = master_size[1:0] == 2'h0; // @[axi4_to_ahb.scala 331:24]
wire _T_541 = _T_117 | _T_540; // @[axi4_to_ahb.scala 330:51]
wire _T_543 = master_size[1:0] == 2'h1; // @[axi4_to_ahb.scala 331:57]
wire _T_544 = _T_541 | _T_543; // @[axi4_to_ahb.scala 331:36]
wire _T_546 = master_size[1:0] == 2'h2; // @[axi4_to_ahb.scala 331:91]
wire _T_547 = _T_544 | _T_546; // @[axi4_to_ahb.scala 331:70]
wire _T_549 = master_size[1:0] == 2'h3; // @[axi4_to_ahb.scala 332:25]
wire _T_551 = wrbuf_byteen == 8'h3; // @[axi4_to_ahb.scala 332:62]
wire _T_553 = wrbuf_byteen == 8'hc; // @[axi4_to_ahb.scala 332:97]
wire _T_554 = _T_551 | _T_553; // @[axi4_to_ahb.scala 332:74]
wire _T_556 = wrbuf_byteen == 8'h30; // @[axi4_to_ahb.scala 332:132]
wire _T_557 = _T_554 | _T_556; // @[axi4_to_ahb.scala 332:109]
wire _T_559 = wrbuf_byteen == 8'hc0; // @[axi4_to_ahb.scala 332:168]
wire _T_560 = _T_557 | _T_559; // @[axi4_to_ahb.scala 332:145]
wire _T_562 = wrbuf_byteen == 8'hf; // @[axi4_to_ahb.scala 333:28]
wire _T_563 = _T_560 | _T_562; // @[axi4_to_ahb.scala 332:181]
wire _T_565 = wrbuf_byteen == 8'hf0; // @[axi4_to_ahb.scala 333:63]
wire _T_566 = _T_563 | _T_565; // @[axi4_to_ahb.scala 333:40]
wire _T_568 = wrbuf_byteen == 8'hff; // @[axi4_to_ahb.scala 333:99]
wire _T_569 = _T_566 | _T_568; // @[axi4_to_ahb.scala 333:76]
wire _T_570 = _T_549 & _T_569; // @[axi4_to_ahb.scala 332:38]
wire buf_aligned_in = _T_547 | _T_570; // @[axi4_to_ahb.scala 331:104]
wire _T_452 = buf_aligned_in & _T_149; // @[axi4_to_ahb.scala 325:55]
wire [2:0] _T_489 = _T_452 ? 3'h0 : master_addr[2:0]; // @[axi4_to_ahb.scala 325:38]
wire [34:0] _T_490 = {master_addr,_T_489}; // @[Cat.scala 29:58]
wire _T_499 = buf_aligned_in & _T_549; // @[axi4_to_ahb.scala 329:38]
wire _T_502 = _T_499 & _T_149; // @[axi4_to_ahb.scala 329:72]
wire [1:0] _T_536 = _T_502 ? 2'h0 : master_size[1:0]; // @[axi4_to_ahb.scala 329:21]
wire [31:0] _T_575 = {master_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58]
wire [31:0] _T_578 = {buf_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58]
wire [1:0] _T_582 = buf_aligned_in ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire [2:0] buf_size_in = {{1'd0}, _T_536}; // @[axi4_to_ahb.scala 329:15]
wire [1:0] _T_584 = _T_582 & buf_size_in[1:0]; // @[axi4_to_ahb.scala 336:80]
wire [2:0] _T_585 = {1'h0,_T_584}; // @[Cat.scala 29:58]
wire _T_593 = ~io_axi_arprot[2]; // @[axi4_to_ahb.scala 340:33]
wire [1:0] _T_594 = {1'h1,_T_593}; // @[Cat.scala 29:58]
reg buf_write; // @[Reg.scala 27:20]
wire [31:0] buf_addr_in = _T_490[31:0]; // @[axi4_to_ahb.scala 325:15]
wire _T_652 = master_valid & io_bus_clk_en; // @[axi4_to_ahb.scala 379:61]
wire _T_664 = buf_data_wr_en & io_bus_clk_en; // @[axi4_to_ahb.scala 391:66]
wire _T_688 = master_valid | io_clk_override; // @[axi4_to_ahb.scala 428:58]
wire _T_691 = io_ahb_hready & io_ahb_htrans[1]; // @[axi4_to_ahb.scala 429:54]
wire _T_692 = _T_691 | io_clk_override; // @[axi4_to_ahb.scala 429:74]
rvclkhdr rvclkhdr ( // @[el2_lib.scala 483:22]
.io_l1clk(rvclkhdr_io_l1clk),
.io_clk(rvclkhdr_io_clk),
.io_en(rvclkhdr_io_en),
.io_scan_mode(rvclkhdr_io_scan_mode)
);
rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 483:22]
.io_l1clk(rvclkhdr_1_io_l1clk),
.io_clk(rvclkhdr_1_io_clk),
.io_en(rvclkhdr_1_io_en),
.io_scan_mode(rvclkhdr_1_io_scan_mode)
);
rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 483:22]
.io_l1clk(rvclkhdr_2_io_l1clk),
.io_clk(rvclkhdr_2_io_clk),
.io_en(rvclkhdr_2_io_en),
.io_scan_mode(rvclkhdr_2_io_scan_mode)
);
rvclkhdr rvclkhdr_3 ( // @[el2_lib.scala 483:22]
.io_l1clk(rvclkhdr_3_io_l1clk),
.io_clk(rvclkhdr_3_io_clk),
.io_en(rvclkhdr_3_io_en),
.io_scan_mode(rvclkhdr_3_io_scan_mode)
);
rvclkhdr rvclkhdr_4 ( // @[el2_lib.scala 483:22]
.io_l1clk(rvclkhdr_4_io_l1clk),
.io_clk(rvclkhdr_4_io_clk),
.io_en(rvclkhdr_4_io_en),
.io_scan_mode(rvclkhdr_4_io_scan_mode)
);
rvclkhdr rvclkhdr_5 ( // @[el2_lib.scala 483:22]
.io_l1clk(rvclkhdr_5_io_l1clk),
.io_clk(rvclkhdr_5_io_clk),
.io_en(rvclkhdr_5_io_en),
.io_scan_mode(rvclkhdr_5_io_scan_mode)
);
assign io_axi_awready = ~_T_11; // @[axi4_to_ahb.scala 188:18]
assign io_axi_wready = ~_T_15; // @[axi4_to_ahb.scala 189:17]
assign io_axi_bvalid = 1'h0; // @[axi4_to_ahb.scala 203:17]
assign io_axi_bresp = 2'h0; // @[axi4_to_ahb.scala 204:16]
assign io_axi_bid = 1'h0; // @[axi4_to_ahb.scala 205:14]
assign io_axi_arready = ~wr_cmd_vld; // @[axi4_to_ahb.scala 190:18]
assign io_axi_rvalid = 1'h0; // @[axi4_to_ahb.scala 207:17]
assign io_axi_rid = 1'h0; // @[axi4_to_ahb.scala 209:14]
assign io_axi_rdata = ahb_hrdata_q[31:0]; // @[axi4_to_ahb.scala 210:16]
assign io_axi_rresp = 2'h0; // @[axi4_to_ahb.scala 208:16]
assign io_axi_rlast = 1'h1; // @[axi4_to_ahb.scala 191:16]
assign io_ahb_haddr = master_valid ? _T_575 : _T_578; // @[axi4_to_ahb.scala 335:16]
assign io_ahb_hburst = 3'h0; // @[axi4_to_ahb.scala 338:17]
assign io_ahb_hmastlock = 1'h0; // @[axi4_to_ahb.scala 339:20]
assign io_ahb_hprot = {{2'd0}, _T_594}; // @[axi4_to_ahb.scala 340:16]
assign io_ahb_hsize = master_valid ? _T_585 : 3'h0; // @[axi4_to_ahb.scala 336:16]
assign io_ahb_htrans = _T_113 & 2'h2; // @[axi4_to_ahb.scala 220:17 axi4_to_ahb.scala 236:21 axi4_to_ahb.scala 248:21 axi4_to_ahb.scala 263:21 axi4_to_ahb.scala 273:21 axi4_to_ahb.scala 293:21 axi4_to_ahb.scala 307:21]
assign io_ahb_hwrite = master_valid ? _T_149 : buf_write; // @[axi4_to_ahb.scala 341:17]
assign io_ahb_hwdata = buf_data; // @[axi4_to_ahb.scala 342:17]
assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 484:17]
assign rvclkhdr_io_en = io_bus_clk_en; // @[el2_lib.scala 485:16]
assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 484:17]
assign rvclkhdr_1_io_en = io_bus_clk_en & _T_60; // @[el2_lib.scala 485:16]
assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 484:17]
assign rvclkhdr_2_io_en = io_bus_clk_en & _T_688; // @[el2_lib.scala 485:16]
assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
assign rvclkhdr_3_io_clk = clock; // @[el2_lib.scala 484:17]
assign rvclkhdr_3_io_en = io_bus_clk_en; // @[el2_lib.scala 485:16]
assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
assign rvclkhdr_4_io_clk = clock; // @[el2_lib.scala 484:17]
assign rvclkhdr_4_io_en = io_bus_clk_en & _T_692; // @[el2_lib.scala 485:16]
assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
assign rvclkhdr_5_io_clk = clock; // @[el2_lib.scala 484:17]
assign rvclkhdr_5_io_en = io_bus_clk_en & io_clk_override; // @[el2_lib.scala 485:16]
assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
buf_nxtstate = _RAND_0[2:0];
_RAND_1 = {1{`RANDOM}};
wrbuf_vld = _RAND_1[0:0];
_RAND_2 = {1{`RANDOM}};
wrbuf_data_vld = _RAND_2[0:0];
_RAND_3 = {1{`RANDOM}};
wrbuf_addr = _RAND_3[31:0];
_RAND_4 = {1{`RANDOM}};
wrbuf_size = _RAND_4[2:0];
_RAND_5 = {1{`RANDOM}};
wrbuf_byteen = _RAND_5[7:0];
_RAND_6 = {2{`RANDOM}};
wrbuf_data = _RAND_6[63:0];
_RAND_7 = {2{`RANDOM}};
buf_data = _RAND_7[63:0];
_RAND_8 = {2{`RANDOM}};
ahb_hrdata_q = _RAND_8[63:0];
_RAND_9 = {1{`RANDOM}};
buf_addr = _RAND_9[31:0];
_RAND_10 = {1{`RANDOM}};
buf_write = _RAND_10[0:0];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
buf_nxtstate = 3'h0;
end
if (reset) begin
wrbuf_vld = 1'h0;
end
if (reset) begin
wrbuf_data_vld = 1'h0;
end
if (reset) begin
wrbuf_addr = 32'h0;
end
if (reset) begin
wrbuf_size = 3'h0;
end
if (reset) begin
wrbuf_byteen = 8'h0;
end
if (reset) begin
wrbuf_data = 64'h0;
end
if (reset) begin
buf_data = 64'h0;
end
if (reset) begin
ahb_hrdata_q = 64'h0;
end
if (reset) begin
buf_addr = 32'h0;
end
if (reset) begin
buf_write = 1'h0;
end
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
always @(posedge clock or posedge reset) begin
if (reset) begin
buf_nxtstate <= 3'h0;
end else if (_T_149) begin
buf_nxtstate <= 3'h2;
end else begin
buf_nxtstate <= 3'h1;
end
end
always @(posedge bus_clk or posedge reset) begin
if (reset) begin
wrbuf_vld <= 1'h0;
end else if (wrbuf_en) begin
wrbuf_vld <= wrbuf_rst;
end
end
always @(posedge bus_clk or posedge reset) begin
if (reset) begin
wrbuf_data_vld <= 1'h0;
end else if (wrbuf_data_en) begin
wrbuf_data_vld <= wrbuf_rst;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
wrbuf_addr <= 32'h0;
end else if (wrbuf_en) begin
wrbuf_addr <= io_axi_awaddr;
end
end
always @(posedge bus_clk or posedge reset) begin
if (reset) begin
wrbuf_size <= 3'h0;
end else if (wrbuf_en) begin
wrbuf_size <= io_axi_awsize;
end
end
always @(posedge bus_clk or posedge reset) begin
if (reset) begin
wrbuf_byteen <= 8'h0;
end else if (wrbuf_data_en) begin
wrbuf_byteen <= io_axi_wstrb;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
wrbuf_data <= 64'h0;
end else if (wrbuf_data_en) begin
wrbuf_data <= io_axi_wdata;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
buf_data <= 64'h0;
end else if (_T_664) begin
buf_data <= wrbuf_data;
end
end
always @(posedge ahbm_data_clk or posedge reset) begin
if (reset) begin
ahb_hrdata_q <= 64'h0;
end else begin
ahb_hrdata_q <= io_ahb_hrdata;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
buf_addr <= 32'h0;
end else if (_T_652) begin
buf_addr <= buf_addr_in;
end
end
always @(posedge buf_clk or posedge reset) begin
if (reset) begin
buf_write <= 1'h0;
end else if (master_valid) begin
buf_write <= _T_149;
end
end
endmodule

18
dmi_wrapper.anno.json Normal file
View File

@ -0,0 +1,18 @@
[
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"dmi_wrapper"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

349
dmi_wrapper.fir Normal file
View File

@ -0,0 +1,349 @@
;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
circuit dmi_wrapper :
module rvjtag_tap :
input clock : Clock
input reset : AsyncReset
output io : {flip trst : AsyncReset, flip tck : Clock, flip tms : UInt<1>, flip tdi : UInt<1>, dmi_reset : UInt<1>, dmi_hard_reset : UInt<1>, flip rd_status : UInt<2>, flip dmi_stat : UInt<2>, flip idle : UInt<3>, flip version : UInt<4>, flip jtag_id : UInt<31>, flip rd_data : UInt<32>, tdo : UInt<1>, tdoEnable : UInt<1>, wr_en : UInt<1>, rd_en : UInt<1>, wr_data : UInt<32>, wr_addr : UInt<0>}
wire nsr : UInt<41>
nsr <= UInt<41>("h00")
reg sr : UInt, io.tck with : (reset => (io.trst, UInt<1>("h00"))) @[rvjtag_tap.scala 32:55]
sr <= nsr @[rvjtag_tap.scala 32:55]
wire dr : UInt<41>
dr <= UInt<41>("h00")
wire nstate : UInt<4>
nstate <= UInt<4>("h00")
reg state : UInt, io.tck with : (reset => (io.trst, UInt<4>("h00"))) @[rvjtag_tap.scala 39:57]
state <= nstate @[rvjtag_tap.scala 39:57]
wire ir : UInt<5>
ir <= UInt<5>("h00")
wire jtag_reset : UInt<1>
jtag_reset <= UInt<1>("h00")
wire shift_dr : UInt<1>
shift_dr <= UInt<1>("h00")
wire pause_dr : UInt<1>
pause_dr <= UInt<1>("h00")
wire update_dr : UInt<1>
update_dr <= UInt<1>("h00")
wire capture_dr : UInt<1>
capture_dr <= UInt<1>("h00")
wire shift_ir : UInt<1>
shift_ir <= UInt<1>("h00")
wire pause_ir : UInt<1>
pause_ir <= UInt<1>("h00")
wire update_ir : UInt<1>
update_ir <= UInt<1>("h00")
wire capture_ir : UInt<1>
capture_ir <= UInt<1>("h00")
wire dr_en : UInt<2>
dr_en <= UInt<1>("h00")
wire devid_sel : UInt<1>
devid_sel <= UInt<1>("h00")
node _T = eq(UInt<4>("h00"), state) @[Conditional.scala 37:30]
when _T : @[Conditional.scala 40:58]
node _T_1 = mux(io.tms, UInt<4>("h00"), UInt<4>("h01")) @[rvjtag_tap.scala 55:46]
nstate <= _T_1 @[rvjtag_tap.scala 55:40]
jtag_reset <= UInt<1>("h01") @[rvjtag_tap.scala 56:18]
skip @[Conditional.scala 40:58]
else : @[Conditional.scala 39:67]
node _T_2 = eq(UInt<4>("h01"), state) @[Conditional.scala 37:30]
when _T_2 : @[Conditional.scala 39:67]
node _T_3 = mux(io.tms, UInt<4>("h02"), UInt<4>("h01")) @[rvjtag_tap.scala 57:47]
nstate <= _T_3 @[rvjtag_tap.scala 57:41]
skip @[Conditional.scala 39:67]
else : @[Conditional.scala 39:67]
node _T_4 = eq(UInt<4>("h02"), state) @[Conditional.scala 37:30]
when _T_4 : @[Conditional.scala 39:67]
node _T_5 = mux(io.tms, UInt<4>("h09"), UInt<4>("h03")) @[rvjtag_tap.scala 58:47]
nstate <= _T_5 @[rvjtag_tap.scala 58:41]
skip @[Conditional.scala 39:67]
else : @[Conditional.scala 39:67]
node _T_6 = eq(UInt<4>("h03"), state) @[Conditional.scala 37:30]
when _T_6 : @[Conditional.scala 39:67]
node _T_7 = mux(io.tms, UInt<4>("h05"), UInt<4>("h04")) @[rvjtag_tap.scala 59:47]
nstate <= _T_7 @[rvjtag_tap.scala 59:41]
capture_dr <= UInt<1>("h01") @[rvjtag_tap.scala 60:18]
skip @[Conditional.scala 39:67]
else : @[Conditional.scala 39:67]
node _T_8 = eq(UInt<4>("h04"), state) @[Conditional.scala 37:30]
when _T_8 : @[Conditional.scala 39:67]
node _T_9 = mux(io.tms, UInt<4>("h05"), UInt<4>("h04")) @[rvjtag_tap.scala 61:47]
nstate <= _T_9 @[rvjtag_tap.scala 61:41]
shift_dr <= UInt<1>("h01") @[rvjtag_tap.scala 62:16]
skip @[Conditional.scala 39:67]
else : @[Conditional.scala 39:67]
node _T_10 = eq(UInt<4>("h05"), state) @[Conditional.scala 37:30]
when _T_10 : @[Conditional.scala 39:67]
node _T_11 = mux(io.tms, UInt<4>("h08"), UInt<4>("h06")) @[rvjtag_tap.scala 63:47]
nstate <= _T_11 @[rvjtag_tap.scala 63:41]
skip @[Conditional.scala 39:67]
else : @[Conditional.scala 39:67]
node _T_12 = eq(UInt<4>("h06"), state) @[Conditional.scala 37:30]
when _T_12 : @[Conditional.scala 39:67]
node _T_13 = mux(io.tms, UInt<4>("h07"), UInt<4>("h06")) @[rvjtag_tap.scala 64:47]
nstate <= _T_13 @[rvjtag_tap.scala 64:41]
pause_dr <= UInt<1>("h01") @[rvjtag_tap.scala 65:16]
skip @[Conditional.scala 39:67]
else : @[Conditional.scala 39:67]
node _T_14 = eq(UInt<4>("h07"), state) @[Conditional.scala 37:30]
when _T_14 : @[Conditional.scala 39:67]
node _T_15 = mux(io.tms, UInt<4>("h08"), UInt<4>("h04")) @[rvjtag_tap.scala 66:47]
nstate <= _T_15 @[rvjtag_tap.scala 66:41]
skip @[Conditional.scala 39:67]
else : @[Conditional.scala 39:67]
node _T_16 = eq(UInt<4>("h08"), state) @[Conditional.scala 37:30]
when _T_16 : @[Conditional.scala 39:67]
node _T_17 = mux(io.tms, UInt<4>("h02"), UInt<4>("h01")) @[rvjtag_tap.scala 67:47]
nstate <= _T_17 @[rvjtag_tap.scala 67:41]
update_dr <= UInt<1>("h01") @[rvjtag_tap.scala 68:17]
skip @[Conditional.scala 39:67]
else : @[Conditional.scala 39:67]
node _T_18 = eq(UInt<4>("h09"), state) @[Conditional.scala 37:30]
when _T_18 : @[Conditional.scala 39:67]
node _T_19 = mux(io.tms, UInt<4>("h00"), UInt<4>("h0a")) @[rvjtag_tap.scala 69:47]
nstate <= _T_19 @[rvjtag_tap.scala 69:41]
skip @[Conditional.scala 39:67]
else : @[Conditional.scala 39:67]
node _T_20 = eq(UInt<4>("h0a"), state) @[Conditional.scala 37:30]
when _T_20 : @[Conditional.scala 39:67]
node _T_21 = mux(io.tms, UInt<4>("h0c"), UInt<4>("h0b")) @[rvjtag_tap.scala 70:47]
nstate <= _T_21 @[rvjtag_tap.scala 70:41]
capture_ir <= UInt<1>("h01") @[rvjtag_tap.scala 71:18]
skip @[Conditional.scala 39:67]
else : @[Conditional.scala 39:67]
node _T_22 = eq(UInt<4>("h0b"), state) @[Conditional.scala 37:30]
when _T_22 : @[Conditional.scala 39:67]
node _T_23 = mux(io.tms, UInt<4>("h0c"), UInt<4>("h0b")) @[rvjtag_tap.scala 72:47]
nstate <= _T_23 @[rvjtag_tap.scala 72:41]
shift_ir <= UInt<1>("h01") @[rvjtag_tap.scala 73:16]
skip @[Conditional.scala 39:67]
else : @[Conditional.scala 39:67]
node _T_24 = eq(UInt<4>("h0c"), state) @[Conditional.scala 37:30]
when _T_24 : @[Conditional.scala 39:67]
node _T_25 = mux(io.tms, UInt<4>("h0f"), UInt<4>("h0d")) @[rvjtag_tap.scala 74:47]
nstate <= _T_25 @[rvjtag_tap.scala 74:41]
skip @[Conditional.scala 39:67]
else : @[Conditional.scala 39:67]
node _T_26 = eq(UInt<4>("h0d"), state) @[Conditional.scala 37:30]
when _T_26 : @[Conditional.scala 39:67]
node _T_27 = mux(io.tms, UInt<4>("h0e"), UInt<4>("h0d")) @[rvjtag_tap.scala 75:47]
nstate <= _T_27 @[rvjtag_tap.scala 75:41]
pause_ir <= UInt<1>("h01") @[rvjtag_tap.scala 76:16]
skip @[Conditional.scala 39:67]
else : @[Conditional.scala 39:67]
node _T_28 = eq(UInt<4>("h0e"), state) @[Conditional.scala 37:30]
when _T_28 : @[Conditional.scala 39:67]
node _T_29 = mux(io.tms, UInt<4>("h0f"), UInt<4>("h0b")) @[rvjtag_tap.scala 77:47]
nstate <= _T_29 @[rvjtag_tap.scala 77:41]
skip @[Conditional.scala 39:67]
else : @[Conditional.scala 39:67]
node _T_30 = eq(UInt<4>("h0f"), state) @[Conditional.scala 37:30]
when _T_30 : @[Conditional.scala 39:67]
node _T_31 = mux(io.tms, UInt<4>("h02"), UInt<4>("h01")) @[rvjtag_tap.scala 78:47]
nstate <= _T_31 @[rvjtag_tap.scala 78:41]
update_ir <= UInt<1>("h01") @[rvjtag_tap.scala 79:17]
skip @[Conditional.scala 39:67]
node _T_32 = or(shift_dr, shift_ir) @[rvjtag_tap.scala 81:28]
io.tdoEnable <= _T_32 @[rvjtag_tap.scala 81:16]
node _T_33 = bits(sr, 4, 0) @[rvjtag_tap.scala 85:93]
node _T_34 = eq(_T_33, UInt<1>("h00")) @[rvjtag_tap.scala 85:98]
node _T_35 = bits(_T_34, 0, 0) @[rvjtag_tap.scala 85:106]
node _T_36 = bits(sr, 4, 0) @[rvjtag_tap.scala 85:123]
node _T_37 = mux(_T_35, UInt<5>("h01f"), _T_36) @[rvjtag_tap.scala 85:89]
node _T_38 = mux(update_ir, _T_37, UInt<1>("h00")) @[rvjtag_tap.scala 85:75]
node _T_39 = mux(jtag_reset, UInt<1>("h01"), _T_38) @[rvjtag_tap.scala 85:56]
reg _T_40 : UInt, io.tck with : (reset => (io.trst, UInt<1>("h01"))) @[rvjtag_tap.scala 85:52]
_T_40 <= _T_39 @[rvjtag_tap.scala 85:52]
ir <= _T_40 @[rvjtag_tap.scala 85:6]
node _T_41 = eq(ir, UInt<5>("h01")) @[rvjtag_tap.scala 86:18]
devid_sel <= _T_41 @[rvjtag_tap.scala 86:13]
node _T_42 = eq(ir, UInt<5>("h011")) @[rvjtag_tap.scala 87:22]
node _T_43 = eq(ir, UInt<5>("h010")) @[rvjtag_tap.scala 87:32]
node _T_44 = cat(_T_42, _T_43) @[Cat.scala 29:58]
dr_en <= _T_44 @[rvjtag_tap.scala 87:13]
node _T_45 = eq(shift_dr, UInt<1>("h01")) @[rvjtag_tap.scala 92:16]
when _T_45 : @[rvjtag_tap.scala 92:23]
node _T_46 = bits(dr_en, 1, 1) @[rvjtag_tap.scala 93:15]
node _T_47 = eq(_T_46, UInt<1>("h01")) @[rvjtag_tap.scala 93:18]
when _T_47 : @[rvjtag_tap.scala 93:28]
node _T_48 = bits(sr, 40, 1) @[rvjtag_tap.scala 93:49]
node _T_49 = cat(io.tdi, _T_48) @[Cat.scala 29:58]
nsr <= _T_49 @[rvjtag_tap.scala 93:33]
skip @[rvjtag_tap.scala 93:28]
else : @[rvjtag_tap.scala 94:54]
node _T_50 = bits(dr_en, 0, 0) @[rvjtag_tap.scala 94:22]
node _T_51 = eq(_T_50, UInt<1>("h01")) @[rvjtag_tap.scala 94:25]
node _T_52 = eq(devid_sel, UInt<1>("h01")) @[rvjtag_tap.scala 94:44]
node _T_53 = or(_T_51, _T_52) @[rvjtag_tap.scala 94:32]
when _T_53 : @[rvjtag_tap.scala 94:54]
node _T_54 = mux(UInt<1>("h00"), UInt<9>("h01ff"), UInt<9>("h00")) @[Bitwise.scala 72:12]
node _T_55 = bits(sr, 31, 1) @[rvjtag_tap.scala 94:106]
node _T_56 = cat(_T_54, io.tdi) @[Cat.scala 29:58]
node _T_57 = cat(_T_56, _T_55) @[Cat.scala 29:58]
nsr <= _T_57 @[rvjtag_tap.scala 94:59]
skip @[rvjtag_tap.scala 94:54]
else : @[rvjtag_tap.scala 95:17]
node _T_58 = mux(UInt<1>("h00"), UInt<40>("h0ffffffffff"), UInt<40>("h00")) @[Bitwise.scala 72:12]
node _T_59 = cat(_T_58, io.tdi) @[Cat.scala 29:58]
nsr <= _T_59 @[rvjtag_tap.scala 95:22]
skip @[rvjtag_tap.scala 95:17]
skip @[rvjtag_tap.scala 92:23]
else : @[rvjtag_tap.scala 97:33]
node _T_60 = eq(capture_dr, UInt<1>("h01")) @[rvjtag_tap.scala 97:26]
when _T_60 : @[rvjtag_tap.scala 97:33]
node _T_61 = bits(dr_en, 0, 0) @[rvjtag_tap.scala 98:17]
when _T_61 : @[rvjtag_tap.scala 98:21]
node _T_62 = mux(UInt<1>("h00"), UInt<26>("h03ffffff"), UInt<26>("h00")) @[Bitwise.scala 72:12]
node _T_63 = cat(UInt<6>("h07"), io.version) @[Cat.scala 29:58]
node _T_64 = cat(_T_62, io.idle) @[Cat.scala 29:58]
node _T_65 = cat(_T_64, io.dmi_stat) @[Cat.scala 29:58]
node _T_66 = cat(_T_65, _T_63) @[Cat.scala 29:58]
nsr <= _T_66 @[rvjtag_tap.scala 98:26]
skip @[rvjtag_tap.scala 98:21]
else : @[rvjtag_tap.scala 99:28]
node _T_67 = bits(dr_en, 1, 1) @[rvjtag_tap.scala 99:24]
when _T_67 : @[rvjtag_tap.scala 99:28]
node _T_68 = mux(UInt<1>("h00"), UInt<7>("h07f"), UInt<7>("h00")) @[Bitwise.scala 72:12]
node _T_69 = cat(_T_68, io.rd_data) @[Cat.scala 29:58]
node _T_70 = cat(_T_69, io.rd_status) @[Cat.scala 29:58]
nsr <= _T_70 @[rvjtag_tap.scala 99:33]
skip @[rvjtag_tap.scala 99:28]
else : @[rvjtag_tap.scala 100:29]
when devid_sel : @[rvjtag_tap.scala 100:29]
node _T_71 = mux(UInt<1>("h00"), UInt<9>("h01ff"), UInt<9>("h00")) @[Bitwise.scala 72:12]
node _T_72 = cat(_T_71, io.jtag_id) @[Cat.scala 29:58]
node _T_73 = cat(_T_72, UInt<1>("h01")) @[Cat.scala 29:58]
nsr <= _T_73 @[rvjtag_tap.scala 100:34]
skip @[rvjtag_tap.scala 100:29]
skip @[rvjtag_tap.scala 97:33]
else : @[rvjtag_tap.scala 102:30]
node _T_74 = eq(shift_ir, UInt<1>("h01")) @[rvjtag_tap.scala 102:23]
when _T_74 : @[rvjtag_tap.scala 102:30]
node _T_75 = mux(UInt<1>("h00"), UInt<36>("h0fffffffff"), UInt<36>("h00")) @[Bitwise.scala 72:12]
node _T_76 = bits(sr, 4, 1) @[rvjtag_tap.scala 102:78]
node _T_77 = cat(_T_75, io.tdi) @[Cat.scala 29:58]
node _T_78 = cat(_T_77, _T_76) @[Cat.scala 29:58]
nsr <= _T_78 @[rvjtag_tap.scala 102:35]
skip @[rvjtag_tap.scala 102:30]
else : @[rvjtag_tap.scala 103:32]
node _T_79 = eq(capture_ir, UInt<1>("h01")) @[rvjtag_tap.scala 103:25]
when _T_79 : @[rvjtag_tap.scala 103:32]
node _T_80 = mux(UInt<1>("h00"), UInt<40>("h0ffffffffff"), UInt<40>("h00")) @[Bitwise.scala 72:12]
node _T_81 = cat(_T_80, UInt<1>("h01")) @[Cat.scala 29:58]
nsr <= _T_81 @[rvjtag_tap.scala 103:37]
skip @[rvjtag_tap.scala 103:32]
node _T_82 = bits(sr, 0, 0) @[rvjtag_tap.scala 106:40]
reg _T_83 : UInt<1>, io.tck with : (reset => (reset, UInt<1>("h00"))) @[rvjtag_tap.scala 106:37]
_T_83 <= _T_82 @[rvjtag_tap.scala 106:37]
io.tdo <= _T_83 @[rvjtag_tap.scala 106:28]
node _T_84 = bits(dr_en, 0, 0) @[rvjtag_tap.scala 108:89]
node _T_85 = bits(_T_84, 0, 0) @[rvjtag_tap.scala 108:99]
node _T_86 = and(update_dr, _T_85) @[rvjtag_tap.scala 108:82]
node _T_87 = bits(sr, 17, 17) @[rvjtag_tap.scala 108:104]
node _T_88 = mux(_T_86, _T_87, UInt<1>("h00")) @[rvjtag_tap.scala 108:71]
reg _T_89 : UInt, io.tck with : (reset => (io.trst, UInt<1>("h00"))) @[rvjtag_tap.scala 108:67]
_T_89 <= _T_88 @[rvjtag_tap.scala 108:67]
io.dmi_hard_reset <= _T_89 @[rvjtag_tap.scala 108:57]
node _T_90 = bits(dr_en, 0, 0) @[rvjtag_tap.scala 109:84]
node _T_91 = bits(_T_90, 0, 0) @[rvjtag_tap.scala 109:94]
node _T_92 = and(update_dr, _T_91) @[rvjtag_tap.scala 109:77]
node _T_93 = bits(sr, 16, 16) @[rvjtag_tap.scala 109:99]
node _T_94 = mux(_T_92, _T_93, UInt<1>("h00")) @[rvjtag_tap.scala 109:66]
reg _T_95 : UInt, io.tck with : (reset => (io.trst, UInt<1>("h00"))) @[rvjtag_tap.scala 109:62]
_T_95 <= _T_94 @[rvjtag_tap.scala 109:62]
io.dmi_reset <= _T_95 @[rvjtag_tap.scala 109:52]
node _T_96 = bits(dr_en, 1, 1) @[rvjtag_tap.scala 111:74]
node _T_97 = bits(_T_96, 0, 0) @[rvjtag_tap.scala 111:84]
node _T_98 = and(update_dr, _T_97) @[rvjtag_tap.scala 111:67]
node _T_99 = bits(dr, 40, 2) @[rvjtag_tap.scala 111:96]
node _T_100 = cat(_T_99, UInt<2>("h00")) @[Cat.scala 29:58]
node _T_101 = mux(_T_98, sr, _T_100) @[rvjtag_tap.scala 111:56]
reg _T_102 : UInt, io.tck with : (reset => (io.trst, UInt<1>("h00"))) @[rvjtag_tap.scala 111:52]
_T_102 <= _T_101 @[rvjtag_tap.scala 111:52]
dr <= _T_102 @[rvjtag_tap.scala 111:42]
node _T_103 = bits(dr, 0, 0) @[rvjtag_tap.scala 113:19]
io.rd_en <= _T_103 @[rvjtag_tap.scala 113:14]
node _T_104 = bits(dr, 1, 1) @[rvjtag_tap.scala 114:19]
io.wr_en <= _T_104 @[rvjtag_tap.scala 114:14]
node _T_105 = bits(dr, 33, 2) @[rvjtag_tap.scala 115:19]
io.wr_data <= _T_105 @[rvjtag_tap.scala 115:14]
node _T_106 = bits(dr, 40, 34) @[rvjtag_tap.scala 116:19]
io.wr_addr <= _T_106 @[rvjtag_tap.scala 116:14]
module dmi_jtag_to_core_sync :
input clock : Clock
input reset : AsyncReset
output io : {flip rd_en : UInt<1>, flip wr_en : UInt<1>, reg_en : UInt<1>, reg_wr_en : UInt<1>}
wire c_rd_en : UInt<1>
c_rd_en <= UInt<1>("h00")
wire c_wr_en : UInt<1>
c_wr_en <= UInt<1>("h00")
wire rden : UInt<3>
rden <= UInt<3>("h00")
wire wren : UInt<3>
wren <= UInt<3>("h00")
node _T = bits(rden, 1, 0) @[dmi_jtag_to_core_sync.scala 26:27]
node _T_1 = cat(_T, io.rd_en) @[Cat.scala 29:58]
reg _T_2 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[dmi_jtag_to_core_sync.scala 26:18]
_T_2 <= _T_1 @[dmi_jtag_to_core_sync.scala 26:18]
rden <= _T_2 @[dmi_jtag_to_core_sync.scala 26:8]
node _T_3 = bits(wren, 1, 0) @[dmi_jtag_to_core_sync.scala 27:27]
node _T_4 = cat(_T_3, io.wr_en) @[Cat.scala 29:58]
reg _T_5 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[dmi_jtag_to_core_sync.scala 27:18]
_T_5 <= _T_4 @[dmi_jtag_to_core_sync.scala 27:18]
wren <= _T_5 @[dmi_jtag_to_core_sync.scala 27:8]
node _T_6 = bits(rden, 1, 1) @[dmi_jtag_to_core_sync.scala 28:18]
node _T_7 = bits(rden, 2, 2) @[dmi_jtag_to_core_sync.scala 28:29]
node _T_8 = eq(_T_7, UInt<1>("h00")) @[dmi_jtag_to_core_sync.scala 28:24]
node _T_9 = and(_T_6, _T_8) @[dmi_jtag_to_core_sync.scala 28:22]
c_rd_en <= _T_9 @[dmi_jtag_to_core_sync.scala 28:11]
node _T_10 = bits(wren, 1, 1) @[dmi_jtag_to_core_sync.scala 29:18]
node _T_11 = bits(wren, 2, 2) @[dmi_jtag_to_core_sync.scala 29:29]
node _T_12 = eq(_T_11, UInt<1>("h00")) @[dmi_jtag_to_core_sync.scala 29:24]
node _T_13 = and(_T_10, _T_12) @[dmi_jtag_to_core_sync.scala 29:22]
c_wr_en <= _T_13 @[dmi_jtag_to_core_sync.scala 29:11]
node _T_14 = or(c_wr_en, c_rd_en) @[dmi_jtag_to_core_sync.scala 31:28]
io.reg_en <= _T_14 @[dmi_jtag_to_core_sync.scala 31:17]
io.reg_wr_en <= c_wr_en @[dmi_jtag_to_core_sync.scala 32:17]
module dmi_wrapper :
input clock : Clock
input reset : AsyncReset
output io : {flip trst_n : AsyncReset, flip tck : Clock, flip tms : UInt<1>, flip tdi : UInt<1>, tdo : UInt<1>, tdoEnable : UInt<1>, flip jtag_id : UInt<32>, flip rd_data : UInt<32>, reg_wr_data : UInt<32>, reg_wr_addr : UInt<7>, reg_en : UInt<1>, reg_wr_en : UInt<1>, dmi_hard_reset : UInt<1>}
wire rd_en : UInt<1>
rd_en <= UInt<1>("h00")
wire wr_en : UInt<1>
wr_en <= UInt<1>("h00")
wire dmireset : UInt<1>
dmireset <= UInt<1>("h00")
inst i_jtag_tap of rvjtag_tap @[dmi_wrapper.scala 35:27]
i_jtag_tap.clock <= clock
i_jtag_tap.reset <= reset
i_jtag_tap.io.trst <= io.trst_n @[dmi_wrapper.scala 36:27]
i_jtag_tap.io.tck <= io.tck @[dmi_wrapper.scala 37:27]
i_jtag_tap.io.tms <= io.tms @[dmi_wrapper.scala 38:27]
i_jtag_tap.io.tdi <= io.tdi @[dmi_wrapper.scala 39:27]
io.tdo <= i_jtag_tap.io.tdo @[dmi_wrapper.scala 40:27]
io.tdoEnable <= i_jtag_tap.io.tdoEnable @[dmi_wrapper.scala 41:27]
io.reg_wr_data <= i_jtag_tap.io.wr_data @[dmi_wrapper.scala 42:27]
io.reg_wr_addr <= i_jtag_tap.io.wr_addr @[dmi_wrapper.scala 43:27]
rd_en <= i_jtag_tap.io.rd_en @[dmi_wrapper.scala 44:27]
wr_en <= i_jtag_tap.io.wr_en @[dmi_wrapper.scala 45:27]
i_jtag_tap.io.rd_data <= io.rd_data @[dmi_wrapper.scala 46:27]
i_jtag_tap.io.rd_status <= UInt<2>("h00") @[dmi_wrapper.scala 47:27]
i_jtag_tap.io.idle <= UInt<3>("h00") @[dmi_wrapper.scala 48:27]
i_jtag_tap.io.dmi_stat <= UInt<2>("h00") @[dmi_wrapper.scala 49:27]
i_jtag_tap.io.version <= UInt<4>("h01") @[dmi_wrapper.scala 50:27]
i_jtag_tap.io.jtag_id <= io.jtag_id @[dmi_wrapper.scala 51:27]
io.dmi_hard_reset <= i_jtag_tap.io.dmi_hard_reset @[dmi_wrapper.scala 52:27]
dmireset <= i_jtag_tap.io.dmi_reset @[dmi_wrapper.scala 53:26]
inst i_dmi_jtag_to_core_sync of dmi_jtag_to_core_sync @[dmi_wrapper.scala 56:39]
i_dmi_jtag_to_core_sync.clock <= clock
i_dmi_jtag_to_core_sync.reset <= reset
i_dmi_jtag_to_core_sync.io.wr_en <= wr_en @[dmi_wrapper.scala 57:36]
i_dmi_jtag_to_core_sync.io.rd_en <= rd_en @[dmi_wrapper.scala 58:36]
io.reg_en <= i_dmi_jtag_to_core_sync.io.reg_en @[dmi_wrapper.scala 59:16]
io.reg_wr_en <= i_dmi_jtag_to_core_sync.io.reg_wr_en @[dmi_wrapper.scala 60:16]

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dmi_wrapper.v Normal file
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@ -0,0 +1,525 @@
module rvjtag_tap(
input reset,
input io_trst,
input io_tck,
input io_tms,
input io_tdi,
output io_dmi_hard_reset,
input [30:0] io_jtag_id,
input [31:0] io_rd_data,
output io_tdo,
output io_tdoEnable,
output io_wr_en,
output io_rd_en,
output [31:0] io_wr_data
);
`ifdef RANDOMIZE_REG_INIT
reg [63:0] _RAND_0;
reg [31:0] _RAND_1;
reg [31:0] _RAND_2;
reg [31:0] _RAND_3;
reg [31:0] _RAND_4;
reg [63:0] _RAND_5;
`endif // RANDOMIZE_REG_INIT
reg [40:0] sr; // @[rvjtag_tap.scala 32:55]
reg [3:0] state; // @[rvjtag_tap.scala 39:57]
wire jtag_reset = 4'h0 == state; // @[Conditional.scala 37:30]
wire _T_2 = 4'h1 == state; // @[Conditional.scala 37:30]
wire _T_4 = 4'h2 == state; // @[Conditional.scala 37:30]
wire _T_6 = 4'h3 == state; // @[Conditional.scala 37:30]
wire _T_8 = 4'h4 == state; // @[Conditional.scala 37:30]
wire _T_10 = 4'h5 == state; // @[Conditional.scala 37:30]
wire _T_12 = 4'h6 == state; // @[Conditional.scala 37:30]
wire _T_14 = 4'h7 == state; // @[Conditional.scala 37:30]
wire _T_16 = 4'h8 == state; // @[Conditional.scala 37:30]
wire _T_18 = 4'h9 == state; // @[Conditional.scala 37:30]
wire _T_20 = 4'ha == state; // @[Conditional.scala 37:30]
wire _T_22 = 4'hb == state; // @[Conditional.scala 37:30]
wire _T_24 = 4'hc == state; // @[Conditional.scala 37:30]
wire _T_26 = 4'hd == state; // @[Conditional.scala 37:30]
wire _T_28 = 4'he == state; // @[Conditional.scala 37:30]
wire _T_30 = 4'hf == state; // @[Conditional.scala 37:30]
wire _GEN_3 = _T_28 ? 1'h0 : _T_30; // @[Conditional.scala 39:67]
wire _GEN_6 = _T_26 ? 1'h0 : _GEN_3; // @[Conditional.scala 39:67]
wire _GEN_9 = _T_24 ? 1'h0 : _GEN_6; // @[Conditional.scala 39:67]
wire _GEN_13 = _T_22 ? 1'h0 : _GEN_9; // @[Conditional.scala 39:67]
wire _GEN_16 = _T_20 ? 1'h0 : _T_22; // @[Conditional.scala 39:67]
wire _GEN_18 = _T_20 ? 1'h0 : _GEN_13; // @[Conditional.scala 39:67]
wire _GEN_20 = _T_18 ? 1'h0 : _T_20; // @[Conditional.scala 39:67]
wire _GEN_21 = _T_18 ? 1'h0 : _GEN_16; // @[Conditional.scala 39:67]
wire _GEN_23 = _T_18 ? 1'h0 : _GEN_18; // @[Conditional.scala 39:67]
wire _GEN_26 = _T_16 ? 1'h0 : _GEN_20; // @[Conditional.scala 39:67]
wire _GEN_27 = _T_16 ? 1'h0 : _GEN_21; // @[Conditional.scala 39:67]
wire _GEN_29 = _T_16 ? 1'h0 : _GEN_23; // @[Conditional.scala 39:67]
wire _GEN_31 = _T_14 ? 1'h0 : _T_16; // @[Conditional.scala 39:67]
wire _GEN_32 = _T_14 ? 1'h0 : _GEN_26; // @[Conditional.scala 39:67]
wire _GEN_33 = _T_14 ? 1'h0 : _GEN_27; // @[Conditional.scala 39:67]
wire _GEN_35 = _T_14 ? 1'h0 : _GEN_29; // @[Conditional.scala 39:67]
wire _GEN_38 = _T_12 ? 1'h0 : _GEN_31; // @[Conditional.scala 39:67]
wire _GEN_39 = _T_12 ? 1'h0 : _GEN_32; // @[Conditional.scala 39:67]
wire _GEN_40 = _T_12 ? 1'h0 : _GEN_33; // @[Conditional.scala 39:67]
wire _GEN_42 = _T_12 ? 1'h0 : _GEN_35; // @[Conditional.scala 39:67]
wire _GEN_45 = _T_10 ? 1'h0 : _GEN_38; // @[Conditional.scala 39:67]
wire _GEN_46 = _T_10 ? 1'h0 : _GEN_39; // @[Conditional.scala 39:67]
wire _GEN_47 = _T_10 ? 1'h0 : _GEN_40; // @[Conditional.scala 39:67]
wire _GEN_49 = _T_10 ? 1'h0 : _GEN_42; // @[Conditional.scala 39:67]
wire _GEN_53 = _T_8 ? 1'h0 : _GEN_45; // @[Conditional.scala 39:67]
wire _GEN_54 = _T_8 ? 1'h0 : _GEN_46; // @[Conditional.scala 39:67]
wire _GEN_55 = _T_8 ? 1'h0 : _GEN_47; // @[Conditional.scala 39:67]
wire _GEN_57 = _T_8 ? 1'h0 : _GEN_49; // @[Conditional.scala 39:67]
wire _GEN_60 = _T_6 ? 1'h0 : _T_8; // @[Conditional.scala 39:67]
wire _GEN_62 = _T_6 ? 1'h0 : _GEN_53; // @[Conditional.scala 39:67]
wire _GEN_63 = _T_6 ? 1'h0 : _GEN_54; // @[Conditional.scala 39:67]
wire _GEN_64 = _T_6 ? 1'h0 : _GEN_55; // @[Conditional.scala 39:67]
wire _GEN_66 = _T_6 ? 1'h0 : _GEN_57; // @[Conditional.scala 39:67]
wire _GEN_68 = _T_4 ? 1'h0 : _T_6; // @[Conditional.scala 39:67]
wire _GEN_69 = _T_4 ? 1'h0 : _GEN_60; // @[Conditional.scala 39:67]
wire _GEN_71 = _T_4 ? 1'h0 : _GEN_62; // @[Conditional.scala 39:67]
wire _GEN_72 = _T_4 ? 1'h0 : _GEN_63; // @[Conditional.scala 39:67]
wire _GEN_73 = _T_4 ? 1'h0 : _GEN_64; // @[Conditional.scala 39:67]
wire _GEN_75 = _T_4 ? 1'h0 : _GEN_66; // @[Conditional.scala 39:67]
wire _GEN_77 = _T_2 ? 1'h0 : _GEN_68; // @[Conditional.scala 39:67]
wire _GEN_78 = _T_2 ? 1'h0 : _GEN_69; // @[Conditional.scala 39:67]
wire _GEN_80 = _T_2 ? 1'h0 : _GEN_71; // @[Conditional.scala 39:67]
wire _GEN_81 = _T_2 ? 1'h0 : _GEN_72; // @[Conditional.scala 39:67]
wire _GEN_82 = _T_2 ? 1'h0 : _GEN_73; // @[Conditional.scala 39:67]
wire _GEN_84 = _T_2 ? 1'h0 : _GEN_75; // @[Conditional.scala 39:67]
wire capture_dr = jtag_reset ? 1'h0 : _GEN_77; // @[Conditional.scala 40:58]
wire shift_dr = jtag_reset ? 1'h0 : _GEN_78; // @[Conditional.scala 40:58]
wire update_dr = jtag_reset ? 1'h0 : _GEN_80; // @[Conditional.scala 40:58]
wire capture_ir = jtag_reset ? 1'h0 : _GEN_81; // @[Conditional.scala 40:58]
wire shift_ir = jtag_reset ? 1'h0 : _GEN_82; // @[Conditional.scala 40:58]
wire update_ir = jtag_reset ? 1'h0 : _GEN_84; // @[Conditional.scala 40:58]
wire _T_34 = sr[4:0] == 5'h0; // @[rvjtag_tap.scala 85:98]
reg [4:0] ir; // @[rvjtag_tap.scala 85:52]
wire devid_sel = ir == 5'h1; // @[rvjtag_tap.scala 86:18]
wire _T_42 = ir == 5'h11; // @[rvjtag_tap.scala 87:22]
wire _T_43 = ir == 5'h10; // @[rvjtag_tap.scala 87:32]
wire [1:0] dr_en = {_T_42,_T_43}; // @[Cat.scala 29:58]
wire [40:0] _T_49 = {io_tdi,sr[40:1]}; // @[Cat.scala 29:58]
wire _T_53 = dr_en[0] | devid_sel; // @[rvjtag_tap.scala 94:32]
wire [40:0] _T_57 = {9'h0,io_tdi,sr[31:1]}; // @[Cat.scala 29:58]
wire [40:0] _T_59 = {40'h0,io_tdi}; // @[Cat.scala 29:58]
wire [40:0] _T_70 = {7'h0,io_rd_data,2'h0}; // @[Cat.scala 29:58]
wire [40:0] _T_73 = {9'h0,io_jtag_id,1'h1}; // @[Cat.scala 29:58]
wire [40:0] _T_78 = {36'h0,io_tdi,sr[4:1]}; // @[Cat.scala 29:58]
reg _T_83; // @[rvjtag_tap.scala 106:37]
wire _T_86 = update_dr & dr_en[0]; // @[rvjtag_tap.scala 108:82]
reg _T_89; // @[rvjtag_tap.scala 108:67]
wire _T_98 = update_dr & dr_en[1]; // @[rvjtag_tap.scala 111:67]
reg [40:0] dr; // @[rvjtag_tap.scala 111:52]
wire [40:0] _T_100 = {dr[40:2],2'h0}; // @[Cat.scala 29:58]
assign io_dmi_hard_reset = _T_89; // @[rvjtag_tap.scala 108:57]
assign io_tdo = _T_83; // @[rvjtag_tap.scala 106:28]
assign io_tdoEnable = shift_dr | shift_ir; // @[rvjtag_tap.scala 81:16]
assign io_wr_en = dr[1]; // @[rvjtag_tap.scala 114:14]
assign io_rd_en = dr[0]; // @[rvjtag_tap.scala 113:14]
assign io_wr_data = dr[33:2]; // @[rvjtag_tap.scala 115:14]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {2{`RANDOM}};
sr = _RAND_0[40:0];
_RAND_1 = {1{`RANDOM}};
state = _RAND_1[3:0];
_RAND_2 = {1{`RANDOM}};
ir = _RAND_2[4:0];
_RAND_3 = {1{`RANDOM}};
_T_83 = _RAND_3[0:0];
_RAND_4 = {1{`RANDOM}};
_T_89 = _RAND_4[0:0];
_RAND_5 = {2{`RANDOM}};
dr = _RAND_5[40:0];
`endif // RANDOMIZE_REG_INIT
if (io_trst) begin
sr = 41'h0;
end
if (io_trst) begin
state = 4'h0;
end
if (io_trst) begin
ir = 5'h1;
end
if (reset) begin
_T_83 = 1'h0;
end
if (io_trst) begin
_T_89 = 1'h0;
end
if (io_trst) begin
dr = 41'h0;
end
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
always @(posedge io_tck or posedge io_trst) begin
if (io_trst) begin
sr <= 41'h0;
end else if (shift_dr) begin
if (dr_en[1]) begin
sr <= _T_49;
end else if (_T_53) begin
sr <= _T_57;
end else begin
sr <= _T_59;
end
end else if (capture_dr) begin
if (dr_en[0]) begin
sr <= 41'h71;
end else if (dr_en[1]) begin
sr <= _T_70;
end else if (devid_sel) begin
sr <= _T_73;
end else begin
sr <= 41'h0;
end
end else if (shift_ir) begin
sr <= _T_78;
end else if (capture_ir) begin
sr <= 41'h1;
end else begin
sr <= 41'h0;
end
end
always @(posedge io_tck or posedge io_trst) begin
if (io_trst) begin
state <= 4'h0;
end else if (jtag_reset) begin
if (io_tms) begin
state <= 4'h0;
end else begin
state <= 4'h1;
end
end else if (_T_2) begin
if (io_tms) begin
state <= 4'h2;
end else begin
state <= 4'h1;
end
end else if (_T_4) begin
if (io_tms) begin
state <= 4'h9;
end else begin
state <= 4'h3;
end
end else if (_T_6) begin
if (io_tms) begin
state <= 4'h5;
end else begin
state <= 4'h4;
end
end else if (_T_8) begin
if (io_tms) begin
state <= 4'h5;
end else begin
state <= 4'h4;
end
end else if (_T_10) begin
if (io_tms) begin
state <= 4'h8;
end else begin
state <= 4'h6;
end
end else if (_T_12) begin
if (io_tms) begin
state <= 4'h7;
end else begin
state <= 4'h6;
end
end else if (_T_14) begin
if (io_tms) begin
state <= 4'h8;
end else begin
state <= 4'h4;
end
end else if (_T_16) begin
if (io_tms) begin
state <= 4'h2;
end else begin
state <= 4'h1;
end
end else if (_T_18) begin
if (io_tms) begin
state <= 4'h0;
end else begin
state <= 4'ha;
end
end else if (_T_20) begin
if (io_tms) begin
state <= 4'hc;
end else begin
state <= 4'hb;
end
end else if (_T_22) begin
if (io_tms) begin
state <= 4'hc;
end else begin
state <= 4'hb;
end
end else if (_T_24) begin
if (io_tms) begin
state <= 4'hf;
end else begin
state <= 4'hd;
end
end else if (_T_26) begin
if (io_tms) begin
state <= 4'he;
end else begin
state <= 4'hd;
end
end else if (_T_28) begin
if (io_tms) begin
state <= 4'hf;
end else begin
state <= 4'hb;
end
end else if (_T_30) begin
if (io_tms) begin
state <= 4'h2;
end else begin
state <= 4'h1;
end
end else begin
state <= 4'h0;
end
end
always @(posedge io_tck or posedge io_trst) begin
if (io_trst) begin
ir <= 5'h1;
end else if (jtag_reset) begin
ir <= 5'h1;
end else if (update_ir) begin
if (_T_34) begin
ir <= 5'h1f;
end else begin
ir <= sr[4:0];
end
end else begin
ir <= 5'h0;
end
end
always @(posedge io_tck or posedge reset) begin
if (reset) begin
_T_83 <= 1'h0;
end else begin
_T_83 <= sr[0];
end
end
always @(posedge io_tck or posedge io_trst) begin
if (io_trst) begin
_T_89 <= 1'h0;
end else begin
_T_89 <= _T_86 & sr[17];
end
end
always @(posedge io_tck or posedge io_trst) begin
if (io_trst) begin
dr <= 41'h0;
end else if (_T_98) begin
dr <= sr;
end else begin
dr <= _T_100;
end
end
endmodule
module dmi_jtag_to_core_sync(
input clock,
input reset,
input io_rd_en,
input io_wr_en,
output io_reg_en,
output io_reg_wr_en
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [31:0] _RAND_1;
`endif // RANDOMIZE_REG_INIT
reg [2:0] rden; // @[dmi_jtag_to_core_sync.scala 26:18]
reg [2:0] wren; // @[dmi_jtag_to_core_sync.scala 27:18]
wire _T_8 = ~rden[2]; // @[dmi_jtag_to_core_sync.scala 28:24]
wire c_rd_en = rden[1] & _T_8; // @[dmi_jtag_to_core_sync.scala 28:22]
wire _T_12 = ~wren[2]; // @[dmi_jtag_to_core_sync.scala 29:24]
wire c_wr_en = wren[1] & _T_12; // @[dmi_jtag_to_core_sync.scala 29:22]
assign io_reg_en = c_wr_en | c_rd_en; // @[dmi_jtag_to_core_sync.scala 31:17]
assign io_reg_wr_en = wren[1] & _T_12; // @[dmi_jtag_to_core_sync.scala 32:17]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
rden = _RAND_0[2:0];
_RAND_1 = {1{`RANDOM}};
wren = _RAND_1[2:0];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
rden = 3'h0;
end
if (reset) begin
wren = 3'h0;
end
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
always @(posedge clock or posedge reset) begin
if (reset) begin
rden <= 3'h0;
end else begin
rden <= {rden[1:0],io_rd_en};
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
wren <= 3'h0;
end else begin
wren <= {wren[1:0],io_wr_en};
end
end
endmodule
module dmi_wrapper(
input clock,
input reset,
input io_trst_n,
input io_tck,
input io_tms,
input io_tdi,
output io_tdo,
output io_tdoEnable,
input [31:0] io_jtag_id,
input [31:0] io_rd_data,
output [31:0] io_reg_wr_data,
output [6:0] io_reg_wr_addr,
output io_reg_en,
output io_reg_wr_en,
output io_dmi_hard_reset
);
wire i_jtag_tap_reset; // @[dmi_wrapper.scala 35:27]
wire i_jtag_tap_io_trst; // @[dmi_wrapper.scala 35:27]
wire i_jtag_tap_io_tck; // @[dmi_wrapper.scala 35:27]
wire i_jtag_tap_io_tms; // @[dmi_wrapper.scala 35:27]
wire i_jtag_tap_io_tdi; // @[dmi_wrapper.scala 35:27]
wire i_jtag_tap_io_dmi_hard_reset; // @[dmi_wrapper.scala 35:27]
wire [30:0] i_jtag_tap_io_jtag_id; // @[dmi_wrapper.scala 35:27]
wire [31:0] i_jtag_tap_io_rd_data; // @[dmi_wrapper.scala 35:27]
wire i_jtag_tap_io_tdo; // @[dmi_wrapper.scala 35:27]
wire i_jtag_tap_io_tdoEnable; // @[dmi_wrapper.scala 35:27]
wire i_jtag_tap_io_wr_en; // @[dmi_wrapper.scala 35:27]
wire i_jtag_tap_io_rd_en; // @[dmi_wrapper.scala 35:27]
wire [31:0] i_jtag_tap_io_wr_data; // @[dmi_wrapper.scala 35:27]
wire i_dmi_jtag_to_core_sync_clock; // @[dmi_wrapper.scala 56:39]
wire i_dmi_jtag_to_core_sync_reset; // @[dmi_wrapper.scala 56:39]
wire i_dmi_jtag_to_core_sync_io_rd_en; // @[dmi_wrapper.scala 56:39]
wire i_dmi_jtag_to_core_sync_io_wr_en; // @[dmi_wrapper.scala 56:39]
wire i_dmi_jtag_to_core_sync_io_reg_en; // @[dmi_wrapper.scala 56:39]
wire i_dmi_jtag_to_core_sync_io_reg_wr_en; // @[dmi_wrapper.scala 56:39]
rvjtag_tap i_jtag_tap ( // @[dmi_wrapper.scala 35:27]
.reset(i_jtag_tap_reset),
.io_trst(i_jtag_tap_io_trst),
.io_tck(i_jtag_tap_io_tck),
.io_tms(i_jtag_tap_io_tms),
.io_tdi(i_jtag_tap_io_tdi),
.io_dmi_hard_reset(i_jtag_tap_io_dmi_hard_reset),
.io_jtag_id(i_jtag_tap_io_jtag_id),
.io_rd_data(i_jtag_tap_io_rd_data),
.io_tdo(i_jtag_tap_io_tdo),
.io_tdoEnable(i_jtag_tap_io_tdoEnable),
.io_wr_en(i_jtag_tap_io_wr_en),
.io_rd_en(i_jtag_tap_io_rd_en),
.io_wr_data(i_jtag_tap_io_wr_data)
);
dmi_jtag_to_core_sync i_dmi_jtag_to_core_sync ( // @[dmi_wrapper.scala 56:39]
.clock(i_dmi_jtag_to_core_sync_clock),
.reset(i_dmi_jtag_to_core_sync_reset),
.io_rd_en(i_dmi_jtag_to_core_sync_io_rd_en),
.io_wr_en(i_dmi_jtag_to_core_sync_io_wr_en),
.io_reg_en(i_dmi_jtag_to_core_sync_io_reg_en),
.io_reg_wr_en(i_dmi_jtag_to_core_sync_io_reg_wr_en)
);
assign io_tdo = i_jtag_tap_io_tdo; // @[dmi_wrapper.scala 40:27]
assign io_tdoEnable = i_jtag_tap_io_tdoEnable; // @[dmi_wrapper.scala 41:27]
assign io_reg_wr_data = i_jtag_tap_io_wr_data; // @[dmi_wrapper.scala 42:27]
assign io_reg_wr_addr = 7'h0; // @[dmi_wrapper.scala 43:27]
assign io_reg_en = i_dmi_jtag_to_core_sync_io_reg_en; // @[dmi_wrapper.scala 59:16]
assign io_reg_wr_en = i_dmi_jtag_to_core_sync_io_reg_wr_en; // @[dmi_wrapper.scala 60:16]
assign io_dmi_hard_reset = i_jtag_tap_io_dmi_hard_reset; // @[dmi_wrapper.scala 52:27]
assign i_jtag_tap_reset = reset;
assign i_jtag_tap_io_trst = io_trst_n; // @[dmi_wrapper.scala 36:27]
assign i_jtag_tap_io_tck = io_tck; // @[dmi_wrapper.scala 37:27]
assign i_jtag_tap_io_tms = io_tms; // @[dmi_wrapper.scala 38:27]
assign i_jtag_tap_io_tdi = io_tdi; // @[dmi_wrapper.scala 39:27]
assign i_jtag_tap_io_jtag_id = io_jtag_id[30:0]; // @[dmi_wrapper.scala 51:27]
assign i_jtag_tap_io_rd_data = io_rd_data; // @[dmi_wrapper.scala 46:27]
assign i_dmi_jtag_to_core_sync_clock = clock;
assign i_dmi_jtag_to_core_sync_reset = reset;
assign i_dmi_jtag_to_core_sync_io_rd_en = i_jtag_tap_io_rd_en; // @[dmi_wrapper.scala 58:36]
assign i_dmi_jtag_to_core_sync_io_wr_en = i_jtag_tap_io_wr_en; // @[dmi_wrapper.scala 57:36]
endmodule

115
el2_dma_ctrl.anno.json Normal file
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@ -0,0 +1,115 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dma_ctrl|el2_dma_ctrl>io_dma_dccm_stall_any",
"sources":[
"~el2_dma_ctrl|el2_dma_ctrl>io_dec_tlu_dma_qos_prty",
"~el2_dma_ctrl|el2_dma_ctrl>io_dma_mem_write"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dma_ctrl|el2_dma_ctrl>io_dma_pmu_any_write",
"sources":[
"~el2_dma_ctrl|el2_dma_ctrl>io_dma_mem_write",
"~el2_dma_ctrl|el2_dma_ctrl>io_dma_dccm_req",
"~el2_dma_ctrl|el2_dma_ctrl>io_dma_iccm_req",
"~el2_dma_ctrl|el2_dma_ctrl>io_dccm_ready",
"~el2_dma_ctrl|el2_dma_ctrl>io_iccm_ready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dma_ctrl|el2_dma_ctrl>io_dma_pmu_dccm_write",
"sources":[
"~el2_dma_ctrl|el2_dma_ctrl>io_dma_dccm_req",
"~el2_dma_ctrl|el2_dma_ctrl>io_dma_mem_write",
"~el2_dma_ctrl|el2_dma_ctrl>io_dccm_ready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dma_ctrl|el2_dma_ctrl>io_dma_iccm_stall_any",
"sources":[
"~el2_dma_ctrl|el2_dma_ctrl>io_dec_tlu_dma_qos_prty",
"~el2_dma_ctrl|el2_dma_ctrl>io_dma_mem_write"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dma_ctrl|el2_dma_ctrl>io_dma_dccm_req",
"sources":[
"~el2_dma_ctrl|el2_dma_ctrl>io_dccm_ready",
"~el2_dma_ctrl|el2_dma_ctrl>io_dma_mem_write"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dma_ctrl|el2_dma_ctrl>io_dma_mem_addr",
"sources":[
"~el2_dma_ctrl|el2_dma_ctrl>io_dma_mem_write"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dma_ctrl|el2_dma_ctrl>io_dma_pmu_any_read",
"sources":[
"~el2_dma_ctrl|el2_dma_ctrl>io_dma_dccm_req",
"~el2_dma_ctrl|el2_dma_ctrl>io_dma_iccm_req",
"~el2_dma_ctrl|el2_dma_ctrl>io_dma_mem_write",
"~el2_dma_ctrl|el2_dma_ctrl>io_dccm_ready",
"~el2_dma_ctrl|el2_dma_ctrl>io_iccm_ready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dma_ctrl|el2_dma_ctrl>io_dma_pmu_dccm_read",
"sources":[
"~el2_dma_ctrl|el2_dma_ctrl>io_dma_dccm_req",
"~el2_dma_ctrl|el2_dma_ctrl>io_dma_mem_write",
"~el2_dma_ctrl|el2_dma_ctrl>io_dccm_ready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dma_ctrl|el2_dma_ctrl>io_dma_mem_sz",
"sources":[
"~el2_dma_ctrl|el2_dma_ctrl>io_dma_mem_write"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dma_ctrl|el2_dma_ctrl>io_dma_iccm_req",
"sources":[
"~el2_dma_ctrl|el2_dma_ctrl>io_iccm_ready",
"~el2_dma_ctrl|el2_dma_ctrl>io_dma_mem_write"
]
},
{
"class":"logger.LogLevelAnnotation",
"globalLogLevel":{
}
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"el2_dma_ctrl.TEC_RV_ICG",
"resourceId":"/vsrc/TEC_RV_ICG.v"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"el2_dma_ctrl"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

2267
el2_dma_ctrl.fir Normal file
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2046
el2_dma_ctrl.v Normal file
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34
src/main/scala/dmi/dmi_jtag_to_core_sync.scala
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@ -1,5 +1,37 @@
package dmi package dmi
import chisel3._
import scala.collection._
import chisel3.util._
import include._
import lib._
class dmi_jtag_to_core_sync { class dmi_jtag_to_core_sync extends Module with el2_lib with RequireAsyncReset {
val io = IO(new Bundle{
// JTAG signals
val rd_en = Input(UInt(1.W))// 1 bit Read Enable from JTAG
val wr_en = Input(UInt(1.W))// 1 bit Write enable from JTAG
// Processor Signals
// val rst_n = Input(Bool()) // Core reset
// val clk = Input(Bool()) // Core clock
val reg_en = Output(UInt(1.W)) // 1 bit Write interface bit to Processor
val reg_wr_en = Output(UInt(1.W)) // 1 bit Write enable to Processor
})
val c_rd_en =WireInit(0.U(1.W))
val c_wr_en =WireInit(0.U(1.W))
val rden =WireInit(0.U(3.W))
val wren =WireInit(0.U(3.W))
// synchronizers
rden := RegNext(Cat(rden(1,0),io.rd_en),0.U)
wren := RegNext(Cat(wren(1,0),io.wr_en),0.U)
c_rd_en := rden(1) & !rden(2)
c_wr_en := wren(1) & !wren(2)
// Outputs
io.reg_en := c_wr_en | c_rd_en
io.reg_wr_en := c_wr_en
}
object dmijtag_main extends App{
println("Generate Verilog")
println((new chisel3.stage.ChiselStage).emitVerilog(new dmi_jtag_to_core_sync()))
} }

62
src/main/scala/dmi/dmi_wrapper.scala
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@ -1,5 +1,65 @@
package dmi package dmi
import chisel3._
import scala.collection._
import chisel3.util._
import include._
import lib._
class dmi_wrapper { class dmi_wrapper extends Module with el2_lib with RequireAsyncReset {
val io = IO(new Bundle{
// JTAG signals
val trst_n = Input(AsyncReset())
val tck = Input(Clock()) // JTAG clock
val tms =Input(UInt(1.W)) // Test mode select
val tdi =Input(UInt(1.W)) // Test Data Input
val tdo =Output(UInt(1.W)) // Test Data Output
val tdoEnable =Output(UInt(1.W)) // Test Data Output enable
// Processor Signals
// val core_rst_n =Input(UInt(1.W)) // Core reset
// val core_clk =Input(UInt(1.W)) // Core clock
val jtag_id = Input(UInt(32.W)) // JTAG ID
val rd_data = Input(UInt(32.W)) // 32 bit Read data from Processor
val reg_wr_data = Output(UInt(32.W)) // 32 bit Write data to Processor
val reg_wr_addr = Output(UInt(7.W)) // 7 bit reg address to Processor
val reg_en = Output(UInt(1.W)) // 1 bit Read enable to Processor
val reg_wr_en = Output(UInt(1.W)) // 1 bit Write enable to Processor
val dmi_hard_reset = Output(UInt(1.W))
})
//Wire Declaration
val rd_en = WireInit(0.U(1.W))
val wr_en = WireInit(0.U(1.W))
val dmireset = WireInit(0.U(1.W))
//jtag_tap instantiation
val i_jtag_tap = Module(new rvjtag_tap())
i_jtag_tap.io.trst := io.trst_n // dedicated JTAG TRST (active low) pad signal or asynchronous active low power on reset
i_jtag_tap.io.tck := io.tck // dedicated JTAG TCK pad signal
i_jtag_tap.io.tms := io.tms // dedicated JTAG TMS pad signal
i_jtag_tap.io.tdi := io.tdi // dedicated JTAG TDI pad signal
io.tdo := i_jtag_tap.io.tdo // dedicated JTAG TDO pad signal
io.tdoEnable := i_jtag_tap.io.tdoEnable // enable for TDO pad
io.reg_wr_data := i_jtag_tap.io.wr_data // 32 bit Write data
io.reg_wr_addr := i_jtag_tap.io.wr_addr // 7 bit Write address
rd_en := i_jtag_tap.io.rd_en // 1 bit read enable
wr_en := i_jtag_tap.io.wr_en // 1 bit Write enable
i_jtag_tap.io.rd_data := io.rd_data // 32 bit Read data
i_jtag_tap.io.rd_status := 0.U(2.W)
i_jtag_tap.io.idle := 0.U(3.W) // no need to wait to sample data
i_jtag_tap.io.dmi_stat := 0.U(2.W) // no need to wait or error possible
i_jtag_tap.io.version := 1.U(4.W) // debug spec 0.13 compliant
i_jtag_tap.io.jtag_id := io.jtag_id
io.dmi_hard_reset := i_jtag_tap.io.dmi_hard_reset
dmireset := i_jtag_tap.io.dmi_reset
// dmi_jtag_to_core_sync instantiation
val i_dmi_jtag_to_core_sync = Module(new dmi_jtag_to_core_sync())
i_dmi_jtag_to_core_sync.io.wr_en := wr_en // 1 bit Write enable
i_dmi_jtag_to_core_sync.io.rd_en := rd_en // 1 bit Read enable
io.reg_en :=i_dmi_jtag_to_core_sync.io.reg_en // 1 bit Write interface bit
io.reg_wr_en := i_dmi_jtag_to_core_sync.io.reg_wr_en // 1 bit Write enable
}
object dmiwrapper_main extends App{
println("Generate Verilog")
println((new chisel3.stage.ChiselStage).emitVerilog(new dmi_wrapper()))
} }

119
src/main/scala/dmi/rvjtag_tap.scala
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@ -1,5 +1,122 @@
package dmi package dmi
import chisel3._
import chisel3.util._
import include._
import lib._
class rvjtag_tap { class rvjtag_tap extends Module with el2_lib with RequireAsyncReset {
val io = IO(new Bundle{
val trst = Input(AsyncReset())
val tck = Input(Clock())
val tms = Input(Bool())
val tdi = Input(Bool())
val dmi_reset = Output(Bool())
val dmi_hard_reset = Output(Bool())
val rd_status = Input(UInt(2.W))
val dmi_stat = Input(UInt(2.W))
val idle = Input(UInt(3.W))
val version = Input(UInt(4.W))
val jtag_id = Input(UInt(31.W))
val rd_data = Input(UInt(32.W))
val tdo = Output(Bool())
val tdoEnable = Output(Bool())
val wr_en = Output(Bool())
val rd_en = Output(Bool())
val wr_data = Output(UInt(32.W))
val wr_addr = Output(UInt(AWIDTH.W))
})
val AWIDTH = 7
val USER_DR_LENGTH = AWIDTH + 34
val nsr = WireInit(0.U(USER_DR_LENGTH.W))
val sr = withClockAndReset (io.tck,io.trst) {RegNext(nsr,0.U)}
val dr = WireInit(0.U(USER_DR_LENGTH.W))
///////////////////////////////////////////////////////
// Tap controller
///////////////////////////////////////////////////////
val test_logic_reset_state :: run_test_idle_state :: select_dr_scan_state :: capture_dr_state :: shift_dr_state :: exit1_dr_state :: pause_dr_state :: exit2_dr_state :: update_dr_state :: select_ir_scan_state :: capture_ir_state :: shift_ir_state :: exit1_ir_state :: pause_ir_state :: exit2_ir_state :: update_ir_state :: Nil = Enum(16)
val nstate = WireInit(test_logic_reset_state)
val state = withClockAndReset(io.tck,io.trst) {RegNext(nstate,test_logic_reset_state)}
val ir = WireInit(0.U(5.W))
val jtag_reset = WireInit(Bool(),false.B)
val shift_dr = WireInit(UInt(1.W),init = 0.U)
val pause_dr = WireInit(UInt(1.W),init = 0.U)
val update_dr = WireInit(Bool(),false.B)
val capture_dr = WireInit(UInt(1.W),init = 0.U)
val shift_ir = WireInit(UInt(1.W),init = 0.U)
val pause_ir = WireInit(UInt(1.W),init = 0.U)
val update_ir = WireInit(Bool(),false.B)
val capture_ir = WireInit(UInt(1.W),init = 0.U)
val dr_en = WireInit(UInt(2.W),init = 0.U)
val devid_sel = WireInit(Bool(),false.B)
val abits = AWIDTH.U(6.W)
switch (state) {
is(test_logic_reset_state) {nstate := Mux(io.tms, test_logic_reset_state, run_test_idle_state)
jtag_reset := 1.U }
is(run_test_idle_state) {nstate := Mux(io.tms,select_dr_scan_state,run_test_idle_state) }
is(select_dr_scan_state) {nstate := Mux(io.tms,select_ir_scan_state,capture_dr_state) }
is(capture_dr_state) {nstate := Mux(io.tms,exit1_dr_state,shift_dr_state)
capture_dr := 1.U }
is(shift_dr_state) {nstate := Mux(io.tms,exit1_dr_state,shift_dr_state)
shift_dr := 1.U }
is(exit1_dr_state) {nstate := Mux(io.tms,update_dr_state,pause_dr_state) }
is(pause_dr_state) {nstate := Mux(io.tms,exit2_dr_state,pause_dr_state)
pause_dr := 1.U }
is(exit2_dr_state) {nstate := Mux(io.tms,update_dr_state,shift_dr_state) }
is(update_dr_state) {nstate := Mux(io.tms,select_dr_scan_state,run_test_idle_state)
update_dr := 1.U }
is(select_ir_scan_state) {nstate := Mux(io.tms,test_logic_reset_state,capture_ir_state) }
is(capture_ir_state) {nstate := Mux(io.tms,exit1_ir_state,shift_ir_state)
capture_ir := 1.U }
is(shift_ir_state) {nstate := Mux(io.tms,exit1_ir_state,shift_ir_state)
shift_ir := 1.U }
is(exit1_ir_state) {nstate := Mux(io.tms,update_ir_state,pause_ir_state) }
is(pause_ir_state) {nstate := Mux(io.tms,exit2_ir_state,pause_ir_state)
pause_ir := 1.U }
is(exit2_ir_state) {nstate := Mux(io.tms,update_ir_state,shift_ir_state) }
is(update_ir_state) {nstate := Mux(io.tms,select_dr_scan_state,run_test_idle_state)
update_ir := 1.U }
}
io.tdoEnable := shift_dr | shift_ir
///////////////////////////////////////////////////////
// IR register
//////////////////////////////////////////////////////
ir := withClockAndReset(io.tck,io.trst) {RegNext(Mux(jtag_reset,1.U,Mux(update_ir,Mux((sr(4,0)===0.U).asBool,"h1f".U,sr(4,0)),0.U)),1.U)}
devid_sel := ir==="b00001".U(5.W)
dr_en := Cat(ir===17.U,ir===16.U)
///////////////////////////////////////////////////////
// Shift register
///////////////////////////////////////////////////////
when(shift_dr===1.U){
when(dr_en(1)===true.B){nsr :=Cat(io.tdi, sr(USER_DR_LENGTH-1,1))}
.elsewhen(dr_en(0)===1.U || devid_sel===true.B){nsr := Cat(Fill(USER_DR_LENGTH-32,0.U) , io.tdi, sr(31,1))}
.otherwise{nsr := Cat(Fill(USER_DR_LENGTH-1,0.U),io.tdi)} // bypass
}
.elsewhen(capture_dr ===1.U){
when(dr_en(0)){nsr := Cat(Fill(USER_DR_LENGTH-15,0.U) ,io.idle, io.dmi_stat,abits,io.version)}
.elsewhen(dr_en(1)){nsr := Cat(Fill(AWIDTH,0.U),io.rd_data,io.rd_status)}
.elsewhen(devid_sel){nsr := Cat(Fill(USER_DR_LENGTH-32,0.U),io.jtag_id,1.U)}
}
.elsewhen(shift_ir===1.U){nsr := Cat(Fill(USER_DR_LENGTH-5,0.U),io.tdi,sr(4,1))}
.elsewhen(capture_ir===1.U){nsr := Cat(Fill(USER_DR_LENGTH-1,0.U),1.U)}
// TDO retiming
withClock(io.tck) {io.tdo:=RegNext(sr(0),0.U)}
// DMI CS register
withClockAndReset (io.tck,io.trst) {io.dmi_hard_reset := RegNext(Mux(update_dr & dr_en(0).asBool(),sr(17),0.U),0.U)}
withClockAndReset (io.tck,io.trst) {io.dmi_reset := RegNext(Mux(update_dr & dr_en(0).asBool(),sr(16),0.U),0.U)}
// DR register
withClockAndReset (io.tck,io.trst) {dr := RegNext(Mux(update_dr & dr_en(1).asBool(),sr,Cat(dr(USER_DR_LENGTH-1,2),0.U(2.W))),0.U)}
io.rd_en := dr(0)
io.wr_en := dr(1)
io.wr_data := dr(33,2)
io.wr_addr := dr(40,34)
} }
object tapmain extends App{
println("Generate Verilog")
println((new chisel3.stage.ChiselStage).emitVerilog(new rvjtag_tap()))
}

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src/main/scala/el2_dma_ctrl.scala Normal file
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package dma
import chisel3._
import chisel3.util._
import scala.collection._
import lib._
class el2_dma_ctrl extends Module with el2_lib with RequireAsyncReset {
val io = IO(new Bundle {
val free_clk = Input(Clock())
val rst_l = Input(Bool())
val dma_bus_clk_en = Input(Bool()) // slave bus clock enable
val clk_override = Input(Bool())
val scan_mode = Input(Bool())
// Debug signals
val dbg_cmd_addr = Input(UInt(32.W))
val dbg_cmd_wrdata = Input(UInt(32.W))
val dbg_cmd_valid = Input(Bool())
val dbg_cmd_write = Input(Bool()) // 1: write command, 0: read_command
val dbg_cmd_type = Input(UInt(2.W)) // 0:gpr 1:csr 2: memory
val dbg_cmd_size = Input(UInt(2.W)) // size of the abstract mem access debug command
val dbg_dma_bubble = Input(Bool()) // Debug needs a bubble to send a valid
val dma_dbg_ready = Output(Bool()) // DMA is ready to accept debug request
val dma_dbg_cmd_done = Output(Bool())
val dma_dbg_cmd_fail = Output(Bool())
val dma_dbg_rddata = Output(UInt(32.W))
// Core side signals
val dma_dccm_req = Output(Bool()) // DMA dccm request (only one of dccm/iccm will be set)
val dma_iccm_req = Output(Bool()) // DMA iccm request
val dma_mem_tag = Output(UInt(3.W)) // DMA Buffer entry number
val dma_mem_addr = Output(UInt(32.W))// DMA request address
val dma_mem_sz = Output(UInt(3.W)) // DMA request size
val dma_mem_write = Output(Bool()) // DMA write to dccm/iccm
val dma_mem_wdata = Output(UInt(64.W))// DMA write data
val dccm_dma_rvalid = Input(Bool()) // dccm data valid for DMA read
val dccm_dma_ecc_error = Input(Bool()) // ECC error on DMA read
val dccm_dma_rtag = Input(UInt(3.W)) // Tag of the DMA req
val dccm_dma_rdata = Input(UInt(64.W)) // dccm data for DMA read
val iccm_dma_rvalid = Input(Bool()) // iccm data valid for DMA read
val iccm_dma_ecc_error = Input(Bool()) // ECC error on DMA read
val iccm_dma_rtag = Input(UInt(3.W)) // Tag of the DMA req
val iccm_dma_rdata = Input(UInt(64.W)) // iccm data for DMA read
val dma_dccm_stall_any = Output(Bool()) // stall dccm pipe (bubble) so that DMA can proceed
val dma_iccm_stall_any = Output(Bool()) // stall iccm pipe (bubble) so that DMA can proceed
val dccm_ready = Input(Bool()) // dccm ready to accept DMA request
val iccm_ready = Input(Bool()) // iccm ready to accept DMA request
val dec_tlu_dma_qos_prty = Input(UInt(3.W)) // DMA QoS priority coming from MFDC [18:15]
// PMU signals
val dma_pmu_dccm_read = Output(Bool())
val dma_pmu_dccm_write = Output(Bool())
val dma_pmu_any_read = Output(Bool())
val dma_pmu_any_write = Output(Bool())
// AXI Write Channels
val dma_axi_awvalid = Input(Bool())
val dma_axi_awready = Output(Bool())
val dma_axi_awid = Input(UInt(DMA_BUS_TAG.W))
val dma_axi_awaddr = Input(UInt(32.W))
val dma_axi_awsize = Input(UInt(3.W))
val dma_axi_wvalid = Input(Bool())
val dma_axi_wready = Output(Bool())
val dma_axi_wdata = Input(UInt(64.W))
val dma_axi_wstrb = Input(UInt(8.W))
val dma_axi_bvalid = Output(Bool())
val dma_axi_bready = Input(Bool())
val dma_axi_bresp = Output(UInt(2.W))
val dma_axi_bid = Output(UInt(DMA_BUS_TAG.W))
// AXI Read Channels
val dma_axi_arvalid = Input(Bool())
val dma_axi_arready = Output(Bool())
val dma_axi_arid = Input(UInt(DMA_BUS_TAG.W))
val dma_axi_araddr = Input(UInt(32.W))
val dma_axi_arsize = Input(UInt(3.W))
val dma_axi_rvalid = Output(Bool())
val dma_axi_rready = Input(Bool())
val dma_axi_rid = Output(UInt(DMA_BUS_TAG.W))
val dma_axi_rdata = Output(UInt(64.W))
val dma_axi_rresp = Output(UInt(2.W))
val dma_axi_rlast = Output(Bool())
})
val DEPTH_PTR = log2Ceil(DMA_BUF_DEPTH)
val fifo_error = Wire(Vec(DMA_BUF_DEPTH, UInt(2.W)))
val fifo_error_bus = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
val fifo_done = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
val fifo_addr = Wire(Vec(DMA_BUF_DEPTH, UInt(32.W)))
val fifo_sz = Wire(Vec(DMA_BUF_DEPTH,UInt(3.W)))
val fifo_byteen = Wire(Vec(DMA_BUF_DEPTH,UInt(8.W)))
val fifo_data = Wire(Vec(DMA_BUF_DEPTH,UInt(64.W)))
val fifo_tag = Wire(Vec(DMA_BUF_DEPTH,UInt(DMA_BUS_TAG.W)))
val fifo_mid = Wire(Vec(DMA_BUF_DEPTH,UInt((DMA_BUS_ID:Int).W)))
val fifo_prty = Wire(Vec(DMA_BUF_DEPTH,UInt(DMA_BUS_PRTY.W)))
val fifo_error_en = WireInit(UInt(DMA_BUF_DEPTH.W),0.U)
val fifo_error_in = Wire(Vec(DMA_BUF_DEPTH, UInt(2.W)))
val fifo_data_in = Wire(Vec(DMA_BUF_DEPTH,UInt(64.W)))
val RspPtr = WireInit(UInt((log2Ceil(DMA_BUF_DEPTH)).W), 0.U)
val WrPtr = WireInit(UInt((log2Ceil(DMA_BUF_DEPTH)).W), 0.U)
val RdPtr = WireInit(UInt((log2Ceil(DMA_BUF_DEPTH)).W), 0.U)
val NxtRspPtr = WireInit(UInt((log2Ceil(DMA_BUF_DEPTH)).W), 0.U)
val NxtWrPtr = WireInit(UInt((log2Ceil(DMA_BUF_DEPTH)).W), 0.U)
val NxtRdPtr = WireInit(UInt((log2Ceil(DMA_BUF_DEPTH)).W), 0.U)
val dma_dbg_cmd_error = WireInit(UInt(1.W),0.U)
val dma_dbg_cmd_done_q = WireInit(UInt(1.W), 0.U)
val fifo_empty = WireInit(UInt(1.W), 0.U)
val dma_address_error = WireInit(UInt(1.W), 0.U)
val dma_alignment_error = WireInit(UInt(1.W), 0.U)
val num_fifo_vld = WireInit(UInt(4.W),0.U)
val dma_mem_req = WireInit(UInt(1.W), 0.U)
val dma_mem_addr_int = WireInit(UInt(32.W), 0.U)
val dma_mem_sz_int = WireInit(UInt(3.W), 0.U)
val dma_mem_byteen = WireInit(UInt(8.W), 0.U)
val dma_nack_count = WireInit(UInt(3.W), 0.U)
val dma_nack_count_csr = WireInit(UInt(3.W), 0.U)
val bus_rsp_valid = WireInit(UInt(1.W), 0.U)
val bus_rsp_sent = WireInit(UInt(1.W), 0.U)
val bus_cmd_valid = WireInit(UInt(1.W), 0.U)
val bus_cmd_sent = WireInit(UInt(1.W), 0.U)
val bus_cmd_write = WireInit(UInt(1.W), 0.U)
val bus_cmd_posted_write = WireInit(UInt(1.W), 0.U)
val bus_cmd_byteen = WireInit(UInt(8.W), 0.U)
val bus_cmd_sz = WireInit(UInt(3.W), 0.U)
val bus_cmd_addr = WireInit(UInt(32.W), 0.U)
val bus_cmd_wdata = WireInit(UInt(64.W), 0.U)
val bus_cmd_tag = WireInit(UInt(DMA_BUS_TAG.W), 0.U)
val bus_cmd_mid = WireInit(UInt((DMA_BUS_ID:Int).W), 0.U)
val bus_cmd_prty = WireInit(UInt(DMA_BUS_PRTY.W), 0.U)
val bus_posted_write_done = WireInit(UInt(1.W), 0.U)
val fifo_full_spec_bus = WireInit(UInt(1.W), 0.U)
val dbg_dma_bubble_bus = WireInit(UInt(1.W), 0.U)
val axi_mstr_priority = WireInit(UInt(1.W), 0.U)
val axi_mstr_sel = WireInit(UInt(1.W), 0.U)
val axi_rsp_sent = WireInit(UInt(1.W), 0.U)
val fifo_cmd_en = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
val fifo_data_en = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
val fifo_pend_en = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
val fifo_error_bus_en = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
val fifo_done_en = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
val fifo_done_bus_en = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
val fifo_reset = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
val fifo_valid = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
val fifo_rpend = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
val fifo_done_bus = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
val fifo_write = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
val fifo_posted_write = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
val fifo_dbg = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
val wrbuf_vld = WireInit(UInt(1.W), 0.U)
val wrbuf_data_vld = WireInit(UInt(1.W), 0.U)
val rdbuf_vld = WireInit(UInt(1.W), 0.U)
val dma_free_clk = Wire(Clock())
val dma_bus_clk = Wire(Clock())
val dma_buffer_c1_clk = Wire(Clock())
val fifo_byteen_in = WireInit(UInt(8.W), 0.U)
//------------------------LOGIC STARTS HERE---------------------------------
// DCCM Address check
val (dma_mem_addr_in_dccm,dma_mem_addr_in_dccm_region_nc) = rvrangecheck_ch(dma_mem_addr_int(31,0),DCCM_SADR.U,DCCM_SIZE)
// PIC memory address check
val (dma_mem_addr_in_pic,dma_mem_addr_in_pic_region_nc) = rvrangecheck_ch(dma_mem_addr_int(31,0),PIC_BASE_ADDR.U,PIC_SIZE)
// ICCM Address check
val (dma_mem_addr_in_iccm,dma_mem_addr_in_iccm_region_nc) = if(ICCM_ENABLE) rvrangecheck_ch(dma_mem_addr_int(31,0),ICCM_SADR.U,ICCM_SIZE) else (0.U,0.U)
// FIFO inputs
val fifo_addr_in = Mux(io.dbg_cmd_valid.asBool, io.dbg_cmd_addr(31,0), bus_cmd_addr(31,0))
fifo_byteen_in := Mux(io.dbg_cmd_valid.asBool, "h0f".U << (4.U * io.dbg_cmd_addr(2)), bus_cmd_byteen(7,0))
val fifo_sz_in = Mux(io.dbg_cmd_valid.asBool, Cat(0.U, io.dbg_cmd_size(1,0)), bus_cmd_sz(2,0))
val fifo_write_in = Mux(io.dbg_cmd_valid.asBool, io.dbg_cmd_write, bus_cmd_write)
val fifo_posted_write_in = !io.dbg_cmd_valid & bus_cmd_posted_write
val fifo_dbg_in = io.dbg_cmd_valid
fifo_cmd_en := (0 until DMA_BUF_DEPTH).map(i => (((bus_cmd_sent.asBool & io.dma_bus_clk_en) | (io.dbg_cmd_valid & io.dbg_cmd_type(1).asBool)) & (i.U === WrPtr)).asUInt).reverse.reduce(Cat(_,_))
fifo_data_en := (0 until DMA_BUF_DEPTH).map(i => (((bus_cmd_sent & fifo_write_in & io.dma_bus_clk_en) | (io.dbg_cmd_valid & io.dbg_cmd_type(1) & io.dbg_cmd_write)) & (i.U === WrPtr)) | ((dma_address_error | dma_alignment_error) & (i.U === RdPtr)) | (io.dccm_dma_rvalid & (i.U === io.dccm_dma_rtag)) | (io.iccm_dma_rvalid & (i.U === io.iccm_dma_rtag))).reverse.reduce(Cat(_,_))
fifo_pend_en := (0 until DMA_BUF_DEPTH).map(i => ((io.dma_dccm_req | io.dma_iccm_req) & !io.dma_mem_write & (i.U === RdPtr)).asUInt).reverse.reduce(Cat(_,_))
fifo_error_en := (0 until DMA_BUF_DEPTH).map(i => (((dma_address_error.asBool | dma_alignment_error.asBool | dma_dbg_cmd_error) & (i.U === RdPtr)) | ((io.dccm_dma_rvalid & io.dccm_dma_ecc_error) & (i.U === io.dccm_dma_rtag)) | ((io.iccm_dma_rvalid & io.iccm_dma_ecc_error) & (i.U === io.iccm_dma_rtag))).asUInt).reverse.reduce(Cat(_,_))
fifo_error_bus_en := (0 until DMA_BUF_DEPTH).map(i => ((((fifo_error_in(i)(1,0).orR) & fifo_error_en(i)) | (fifo_error(i).orR)) & io.dma_bus_clk_en).asUInt).reverse.reduce(Cat(_,_))
fifo_done_en := (0 until DMA_BUF_DEPTH).map(i => (((fifo_error(i).orR | fifo_error_en(i) | ((io.dma_dccm_req | io.dma_iccm_req) & io.dma_mem_write)) & (i.U === RdPtr)) | (io.dccm_dma_rvalid & (i.U === io.dccm_dma_rtag)) | (io.iccm_dma_rvalid & (i.U === io.iccm_dma_rtag))).asUInt).reverse.reduce(Cat(_,_))
fifo_done_bus_en := (0 until DMA_BUF_DEPTH).map(i => ((fifo_done_en(i) | fifo_done(i)) & io.dma_bus_clk_en).asUInt).reverse.reduce(Cat(_,_))
fifo_reset := (0 until DMA_BUF_DEPTH).map(i => ((((bus_rsp_sent | bus_posted_write_done) & io.dma_bus_clk_en) | io.dma_dbg_cmd_done) & (i.U === RspPtr))).reverse.reduce(Cat(_,_))
(0 until DMA_BUF_DEPTH).map(i => fifo_error_in(i) := (Mux(io.dccm_dma_rvalid & (i.U === io.dccm_dma_rtag), Cat(0.U, io.dccm_dma_ecc_error), Mux(io.iccm_dma_rvalid & (i.U === io.iccm_dma_rtag), (Cat(0.U, io.iccm_dma_ecc_error)), (Cat((dma_address_error | dma_alignment_error | dma_dbg_cmd_error), dma_alignment_error))))))
(0 until DMA_BUF_DEPTH).map(i => fifo_data_in(i) := (Mux(fifo_error_en(i) & (fifo_error_in(i).orR), Cat(Fill(32, 0.U), fifo_addr(i)), Mux(io.dccm_dma_rvalid & (i.U === io.dccm_dma_rtag), io.dccm_dma_rdata, Mux(io.iccm_dma_rvalid & (i.U === io.iccm_dma_rtag), io.iccm_dma_rdata, Mux(io.dbg_cmd_valid, Fill(2, io.dbg_cmd_wrdata), bus_cmd_wdata(63,0)))))))
fifo_valid := (0 until DMA_BUF_DEPTH).map(i => withClock(dma_free_clk) {RegNext(Mux(fifo_cmd_en(i), 1.U, fifo_valid(i)) & !fifo_reset(i), 0.U)}).reverse.reduce(Cat(_,_))
(0 until DMA_BUF_DEPTH).map(i => fifo_error(i) := withClock(dma_free_clk) {RegNext(Mux(fifo_error_en(i).asBool(),fifo_error_in(i) , fifo_error(i)) & Fill(fifo_error_in(i).getWidth , !fifo_reset(i)), 0.U)})
fifo_error_bus := (0 until DMA_BUF_DEPTH).map(i => withClock(dma_free_clk) {RegNext(Mux(fifo_error_bus_en(i), 1.U, fifo_error_bus(i)) & !fifo_reset(i), 0.U)}).reverse.reduce(Cat(_,_))
fifo_rpend := (0 until DMA_BUF_DEPTH).map(i => withClock(dma_free_clk) {RegNext(Mux(fifo_pend_en(i), 1.U, fifo_rpend(i)) & !fifo_reset(i), 0.U)}).reverse.reduce(Cat(_,_))
fifo_done := (0 until DMA_BUF_DEPTH).map(i => withClock(dma_free_clk) {RegNext(Mux(fifo_done_en(i), 1.U, fifo_done(i)) & !fifo_reset(i), 0.U)}).reverse.reduce(Cat(_,_))
fifo_done_bus := (0 until DMA_BUF_DEPTH).map(i => withClock(dma_free_clk) {RegNext(Mux(fifo_done_bus_en(i), 1.U, fifo_done_bus(i)) & !fifo_reset(i), 0.U)}).reverse.reduce(Cat(_,_))
(0 until DMA_BUF_DEPTH).map(i => fifo_addr(i) := rvdffe(fifo_addr_in, fifo_cmd_en(i), clock, io.scan_mode))
(0 until DMA_BUF_DEPTH).map(i => fifo_sz(i) := withClock(dma_buffer_c1_clk) {RegEnable(fifo_sz_in(2,0), 0.U, fifo_cmd_en(i))})
(0 until DMA_BUF_DEPTH).map(i => fifo_byteen(i) := withClock(dma_buffer_c1_clk) {RegEnable(fifo_byteen_in(7,0), 0.U, fifo_cmd_en(i).asBool())})
fifo_write := (0 until DMA_BUF_DEPTH).map(i => (withClock(dma_buffer_c1_clk) {RegEnable(fifo_write_in, 0.U, fifo_cmd_en(i))})).reverse.reduce(Cat(_,_))
fifo_posted_write := (0 until DMA_BUF_DEPTH).map(i => (withClock(dma_buffer_c1_clk) {RegEnable(fifo_posted_write_in, 0.U, fifo_cmd_en(i))})).reverse.reduce(Cat(_,_))
fifo_dbg := (0 until DMA_BUF_DEPTH).map(i => withClock(dma_buffer_c1_clk) {RegEnable(fifo_dbg_in, 0.U, fifo_cmd_en(i))}).reverse.reduce(Cat(_,_))
(0 until DMA_BUF_DEPTH).map(i => fifo_data(i) := rvdffe(fifo_data_in(i), fifo_data_en(i), clock, io.scan_mode))
(0 until DMA_BUF_DEPTH).map(i => fifo_tag(i) := withClock(dma_buffer_c1_clk) {RegEnable(bus_cmd_tag, 0.U, fifo_cmd_en(i))})
(0 until DMA_BUF_DEPTH).map(i => fifo_mid(i) := withClock(dma_buffer_c1_clk) {RegEnable(bus_cmd_mid, 0.U, fifo_cmd_en(i))})
(0 until DMA_BUF_DEPTH).map(i => fifo_prty(i) := withClock(dma_buffer_c1_clk) {RegEnable(bus_cmd_prty, 0.U, fifo_cmd_en(i))})
// Pointer logic
NxtWrPtr := Mux((WrPtr === (DMA_BUF_DEPTH - 1).U).asBool, 0.U, WrPtr + 1.U)
NxtRdPtr := Mux((RdPtr === (DMA_BUF_DEPTH - 1).U).asBool, 0.U, RdPtr + 1.U)
NxtRspPtr := Mux((RspPtr === (DMA_BUF_DEPTH - 1).U).asBool, 0.U, RspPtr + 1.U)
val WrPtrEn = fifo_cmd_en.orR
val RdPtrEn = (io.dma_dccm_req | io.dma_iccm_req | (dma_address_error.asBool | dma_alignment_error.asBool | dma_dbg_cmd_error))
val RspPtrEn = (io.dma_dbg_cmd_done | (bus_rsp_sent | bus_posted_write_done) & io.dma_bus_clk_en)
WrPtr := withClock(dma_free_clk) {
RegEnable(NxtWrPtr, 0.U, WrPtrEn)
}
RdPtr := withClock(dma_free_clk) {
RegEnable(NxtRdPtr, 0.U, RdPtrEn.asBool)
}
RspPtr := withClock(dma_free_clk) {
RegEnable(NxtRspPtr, 0.U, RspPtrEn.asBool)
}
// Miscellaneous signal
val fifo_full = fifo_full_spec_bus;
val num_fifo_vld_tmp = WireInit(UInt(4.W),0.U)
val num_fifo_vld_tmp2 = WireInit(UInt(4.W),0.U)
num_fifo_vld_tmp := (Cat(Fill(3, 0.U), bus_cmd_sent)) - (Cat(Fill(3, 0.U), bus_rsp_sent))
num_fifo_vld_tmp2 := (0 until DMA_BUF_DEPTH).map(i => Cat(Fill(3,0.U), fifo_valid(i))).reduce(_+_)
num_fifo_vld := num_fifo_vld_tmp + num_fifo_vld_tmp2
val fifo_full_spec = (num_fifo_vld_tmp2 >= DMA_BUF_DEPTH.asUInt())
val dma_fifo_ready = ~(fifo_full | dbg_dma_bubble_bus)
// Error logic
dma_address_error := fifo_valid(RdPtr) & !fifo_done(RdPtr) & !fifo_dbg(RdPtr) & (~(dma_mem_addr_in_dccm | dma_mem_addr_in_iccm)).asUInt // request not for ICCM or DCCM
dma_alignment_error := fifo_valid(RdPtr) & !fifo_done(RdPtr) & !dma_address_error &
(((dma_mem_sz_int(2,0) === 1.U) & dma_mem_addr_int(0)) | // HW size but unaligned
((dma_mem_sz_int(2,0) === 2.U) & (dma_mem_addr_int(1, 0).orR)) | // W size but unaligned
((dma_mem_sz_int(2,0) === 3.U) & (dma_mem_addr_int(2, 0).orR)) | // DW size but unaligned
(dma_mem_addr_in_iccm & ~((dma_mem_sz_int(1, 0) === 2.U) | (dma_mem_sz_int(1, 0) === 3.U)).asUInt ) | // ICCM access not word size
(dma_mem_addr_in_dccm & io.dma_mem_write & ~((dma_mem_sz_int(1, 0) === 2.U) | (dma_mem_sz_int(1, 0) === 3.U)).asUInt) | // DCCM write not word size
(io.dma_mem_write & (dma_mem_sz_int(2, 0) === 2.U) & (Mux1H(Seq((dma_mem_addr_int(2,0) === 0.U) -> (dma_mem_byteen(3,0)),
(dma_mem_addr_int(2,0) === 1.U) -> (dma_mem_byteen(4,1)),
(dma_mem_addr_int(2,0) === 2.U) -> (dma_mem_byteen(5,2)),
(dma_mem_addr_int(2,0) === 3.U) -> (dma_mem_byteen(6,3)))) =/= 15.U)) | // Write byte enables not aligned for word store
(io.dma_mem_write & (dma_mem_sz_int(2, 0) === 3.U) & !((dma_mem_byteen(7,0) === "h0f".U) | (dma_mem_byteen(7,0) === "hf0".U) | (dma_mem_byteen(7,0) === "hff".U)))) // Write byte enables not aligned for dword store
//Dbg outputs
io.dma_dbg_ready := fifo_empty & dbg_dma_bubble_bus
io.dma_dbg_cmd_done := (fifo_valid(RspPtr) & fifo_dbg(RspPtr) & fifo_done(RspPtr))
io.dma_dbg_rddata := Mux(fifo_addr(RspPtr)(2), fifo_data(RspPtr)(63, 32), fifo_data(RspPtr)(31,0))
io.dma_dbg_cmd_fail := fifo_error(RspPtr).orR
dma_dbg_cmd_error := fifo_valid(RdPtr) & !fifo_done(RdPtr) & fifo_dbg(RdPtr) & ((~(dma_mem_addr_in_dccm | dma_mem_addr_in_iccm | dma_mem_addr_in_pic)).asBool() | (dma_mem_sz_int(1, 0) =/= 2.U)) // Only word accesses allowed
// Block the decode if fifo full
io.dma_dccm_stall_any := dma_mem_req & (dma_mem_addr_in_dccm | dma_mem_addr_in_pic) & (dma_nack_count >= dma_nack_count_csr)
io.dma_iccm_stall_any := dma_mem_req & dma_mem_addr_in_iccm & (dma_nack_count >= dma_nack_count_csr);
// Used to indicate ready to debug
fifo_empty := ~(fifo_valid.orR)
// Nack counter, stall the lsu pipe if 7 nacks
dma_nack_count_csr := io.dec_tlu_dma_qos_prty
val dma_nack_count_d = Mux(dma_nack_count >= dma_nack_count_csr, (Fill(3, !(io.dma_dccm_req | io.dma_iccm_req)) & dma_nack_count(2,0)), Mux((dma_mem_req.asBool & !(io.dma_dccm_req | io.dma_iccm_req)), dma_nack_count(2,0) + 1.U, 0.U))
dma_nack_count := withClock(dma_free_clk) {
RegEnable(dma_nack_count_d(2,0), 0.U, dma_mem_req.asBool)
}
// Core outputs
dma_mem_req := fifo_valid(RdPtr) & !fifo_rpend(RdPtr) & !fifo_done(RdPtr) & !(dma_address_error | dma_alignment_error | dma_dbg_cmd_error)
io.dma_dccm_req := dma_mem_req & (dma_mem_addr_in_dccm | dma_mem_addr_in_pic) & io.dccm_ready;
io.dma_iccm_req := dma_mem_req & dma_mem_addr_in_iccm & io.iccm_ready;
io.dma_mem_tag := RdPtr
dma_mem_addr_int := fifo_addr(RdPtr)
dma_mem_sz_int := fifo_sz(RdPtr)
io.dma_mem_addr := Mux(io.dma_mem_write & (dma_mem_byteen(7,0) === "hf0".U), Cat(dma_mem_addr_int(31, 3), 1.U, dma_mem_addr_int(1, 0)), dma_mem_addr_int(31,0))
io.dma_mem_sz := Mux(io.dma_mem_write & ((dma_mem_byteen(7,0) === "h0f".U) | (dma_mem_byteen(7,0) === "hf0".U)), 2.U, dma_mem_sz_int(2,0))
dma_mem_byteen := fifo_byteen(RdPtr)
io.dma_mem_write := fifo_write(RdPtr)
io.dma_mem_wdata := fifo_data(RdPtr)
// PMU outputs
io.dma_pmu_dccm_read := io.dma_dccm_req & !io.dma_mem_write;
io.dma_pmu_dccm_write := io.dma_dccm_req & io.dma_mem_write;
io.dma_pmu_any_read := (io.dma_dccm_req | io.dma_iccm_req) & !io.dma_mem_write;
io.dma_pmu_any_write := (io.dma_dccm_req | io.dma_iccm_req) & io.dma_mem_write;
// Inputs
fifo_full_spec_bus := withClock(dma_bus_clk) {
RegNext(fifo_full_spec, 0.U)
}
dbg_dma_bubble_bus := withClock(dma_bus_clk) {
RegNext(io.dbg_dma_bubble, 0.U)
}
dma_dbg_cmd_done_q := withClock(io.free_clk) {
RegNext(io.dma_dbg_cmd_done, 0.U)
}
// Clock Gating logic
val dma_buffer_c1_clken = (bus_cmd_valid & io.dma_bus_clk_en) | io.dbg_cmd_valid | io.clk_override
val dma_free_clken = (bus_cmd_valid | bus_rsp_valid | io.dbg_cmd_valid | io.dma_dbg_cmd_done | dma_dbg_cmd_done_q | (fifo_valid.orR) | io.clk_override)
val dma_buffer_c1cgc = Module(new rvclkhdr)
dma_buffer_c1cgc.io.en := dma_buffer_c1_clken
dma_buffer_c1cgc.io.scan_mode := io.scan_mode
dma_buffer_c1cgc.io.clk := clock
dma_buffer_c1_clk := dma_buffer_c1cgc.io.l1clk
val dma_free_cgc = Module(new rvclkhdr)
dma_free_cgc.io.en := dma_free_clken
dma_free_cgc.io.scan_mode := io.scan_mode
dma_free_cgc.io.clk := clock
dma_free_clk := dma_free_cgc.io.l1clk
val dma_bus_cgc = Module(new rvclkhdr)
dma_bus_cgc.io.en := io.dma_bus_clk_en
dma_bus_cgc.io.scan_mode := io.scan_mode
dma_bus_cgc.io.clk := clock
dma_bus_clk := dma_bus_cgc.io.l1clk
// Write channel buffer
val wrbuf_en = io.dma_axi_awvalid & io.dma_axi_awready
val wrbuf_data_en = io.dma_axi_wvalid & io.dma_axi_wready
val wrbuf_cmd_sent = bus_cmd_sent & bus_cmd_write
val wrbuf_rst = wrbuf_cmd_sent.asBool & !wrbuf_en
val wrbuf_data_rst = wrbuf_cmd_sent.asBool & !wrbuf_data_en
wrbuf_vld := withClock(dma_bus_clk) {RegNext(Mux(wrbuf_en, 1.U, wrbuf_vld) & !wrbuf_rst, 0.U)}
wrbuf_data_vld := withClock(dma_bus_clk) {RegNext(Mux(wrbuf_data_en, 1.U, wrbuf_data_vld) & !wrbuf_data_rst, 0.U)}
val wrbuf_tag = withClock(dma_bus_clk) {
RegEnable(io.dma_axi_awid, 0.U, wrbuf_en)
}
val wrbuf_sz = withClock(dma_bus_clk) {
RegEnable(io.dma_axi_awsize, 0.U, wrbuf_en)
}
val wrbuf_addr = rvdffe(io.dma_axi_awaddr, wrbuf_en & io.dma_bus_clk_en, clock, io.scan_mode)
val wrbuf_data = rvdffe(io.dma_axi_wdata, wrbuf_data_en & io.dma_bus_clk_en, clock, io.scan_mode)
val wrbuf_byteen = withClock(dma_bus_clk) {
RegEnable(io.dma_axi_wstrb, 0.U, wrbuf_data_en)
}
// Read channel buffer
val rdbuf_en = io.dma_axi_arvalid & io.dma_axi_arready
val rdbuf_cmd_sent = bus_cmd_sent & !bus_cmd_write
val rdbuf_rst = rdbuf_cmd_sent.asBool & !rdbuf_en
rdbuf_vld := withClock(dma_bus_clk) {RegNext(Mux(rdbuf_en, 1.U, rdbuf_vld) & !rdbuf_rst, 0.U)}
val rdbuf_tag = withClock(dma_bus_clk) {
RegEnable(io.dma_axi_arid, 0.U, rdbuf_en)
}
val rdbuf_sz = withClock(dma_bus_clk) {
RegEnable(io.dma_axi_arsize, 0.U, rdbuf_en)
}
val rdbuf_addr = rvdffe(io.dma_axi_araddr, rdbuf_en & io.dma_bus_clk_en, clock, io.scan_mode)
io.dma_axi_awready := ~(wrbuf_vld & !wrbuf_cmd_sent)
io.dma_axi_wready := ~(wrbuf_data_vld & !wrbuf_cmd_sent)
io.dma_axi_arready := ~(rdbuf_vld & !rdbuf_cmd_sent)
//Generate a single request from read/write channel
bus_cmd_valid := (wrbuf_vld & wrbuf_data_vld) | rdbuf_vld
bus_cmd_sent := bus_cmd_valid & dma_fifo_ready.asUInt
bus_cmd_write := axi_mstr_sel
bus_cmd_posted_write := 0.U;
bus_cmd_addr := Mux(axi_mstr_sel.asBool, wrbuf_addr, rdbuf_addr)
bus_cmd_sz := Mux(axi_mstr_sel.asBool, wrbuf_sz, rdbuf_sz)
bus_cmd_wdata := wrbuf_data
bus_cmd_byteen := wrbuf_byteen
bus_cmd_tag := Mux(axi_mstr_sel.asBool, wrbuf_tag, rdbuf_tag)
bus_cmd_mid := 0.U
bus_cmd_prty := 0.U
// Sel=1 -> write has higher priority
axi_mstr_sel := Mux((wrbuf_vld & wrbuf_data_vld & rdbuf_vld) === 1.U, axi_mstr_priority, wrbuf_vld & wrbuf_data_vld)
val axi_mstr_prty_in = ~axi_mstr_priority
val axi_mstr_prty_en = bus_cmd_sent
axi_mstr_priority := withClock(dma_bus_clk) {
RegEnable(axi_mstr_prty_in, 0.U, axi_mstr_prty_en.asBool)
}
val axi_rsp_valid = fifo_valid(RspPtr) & !fifo_dbg(RspPtr) & fifo_done_bus(RspPtr)
val axi_rsp_rdata = fifo_data(RspPtr)
val axi_rsp_write = fifo_write(RspPtr)
val axi_rsp_error = Mux(fifo_error(RspPtr)(0), 2.U, Mux(fifo_error(RspPtr)(1), 3.U, 0.U));
val axi_rsp_tag = fifo_tag(RspPtr)
// AXI response channel signals
io.dma_axi_bvalid := axi_rsp_valid & axi_rsp_write
io.dma_axi_bresp := axi_rsp_error(1,0)
io.dma_axi_bid := axi_rsp_tag
io.dma_axi_rvalid := axi_rsp_valid & !axi_rsp_write
io.dma_axi_rresp := axi_rsp_error
io.dma_axi_rdata := axi_rsp_rdata(63,0)
io.dma_axi_rlast := 1.U
io.dma_axi_rid := axi_rsp_tag
bus_posted_write_done := 0.U
bus_rsp_valid := (io.dma_axi_bvalid | io.dma_axi_rvalid)
bus_rsp_sent := ((io.dma_axi_bvalid & io.dma_axi_bready) | (io.dma_axi_rvalid & io.dma_axi_rready))
}
object dma extends App{
chisel3.Driver.emitVerilog(new el2_dma_ctrl)
}

123
src/main/scala/lib/GCD.scala
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@ -1,123 +0,0 @@
package lib
import chisel3._
import chisel3.util._
/*
///////////////////////////////////////////////////////////////
class rvdff(val Width:Int = 1, val short:Int = 0) extends Module with RequireAsyncReset {
val io = IO(new Bundle {
val in = Input(UInt(Width.W))
val out = Output(UInt())
})
val inter = if(short==0) RegNext(io.in, init =0.U) else io.in
io.out := inter
}
/////////////////////////////////////////////////////////////
class caller extends Module {
val io = IO(new Bundle {
val in = Input(UInt(32.W))
val out = Output(UInt())
})
val u0 = Module(new rvdff(32))
io <> u0.io
}
///////////////////////////////////////////////////////////////
class reg1 extends Module with RequireAsyncReset{
val io = IO(new Bundle{
val in = Input(Bool())
val out = Output(Bool())
})
io.out := RegNext(io.in, init = 0.U)
}
class top extends Module with RequireAsyncReset{
val io = IO(new Bundle{
val in = Input(Bool())
val out = Output(Bool())
})
val negReset = (~reset.asBool).asAsyncReset
val r0 = Module(new reg1)
r0.io<>io
r0.reset := negReset
}
///////////////////////////////////////////////////////////////
class rvbradder() extends Module {
val io = IO(new Bundle {
val pc = Input(UInt(31.W))
val offset = Input(UInt(12.W))
val dout = Output(UInt())
})
val inter = io.pc(11,0) +& io.offset
val cout = inter(inter.getWidth-1)
val pc_inc = io.pc(io.pc.getWidth-1, 12) + 1.U
val pc_dec = io.pc(io.pc.getWidth-1, 12) - 1.U
val sign = io.offset(io.offset.getWidth -1)
io.dout:= Cat(Fill(19,(sign ^(~cout))) & io.pc(io.pc.getWidth-1,12) |
(Fill(19,(~sign & cout)) & pc_inc) |
(Fill(19,(sign & ~cout)) & pc_dec) , inter(inter.getWidth-2,0))
}
///////////////////////////////////////////////////////////////
class encoder_generator(val width:Int=4) extends Module {
val io = IO (new Bundle {
val in = Input (UInt(width.W))
val out = Output (UInt(log2Ceil(width).W))
})
var z:Array[UInt] = new Array[UInt](width)
for(i<- 0 until width){
z(i) = i.U
}
io.out := Mux1H(io.in , z)
}
///////////////////////////////////////////////////////////////
class rvrangecheck(val CCM_SADR:Int = 0, val CCM_SIZE:Int = 128) extends Module {
val io = IO(new Bundle {
val addr = Input(UInt(32.W))
val in_range = Output(Bool())
val in_region = Output(Bool())
//val test = Output(UInt())
})
val start_addr = (CCM_SADR.U)(32.W)
val region = start_addr(31,28)
val MASK_BITS = 10+log2Ceil(CCM_SIZE)
io.in_region := io.addr(31,28) === region
val inter = if(CCM_SIZE == 48) io.addr(31, MASK_BITS) === start_addr(31, MASK_BITS) & ~(io.addr(MASK_BITS-1,MASK_BITS-2).andR)
else (io.addr(31,MASK_BITS)===start_addr(31,MASK_BITS))
io.in_range := inter
}
////////////////////////////////////////////////////////////////
class tocopy extends Module{
val io = IO(new Bundle {
val in1 = Input(UInt(1.W))
val in2 = Input(UInt(1.W))
val out = Output(UInt())
})
io.out := io.in1 +& io.in2
}
class exp extends Module{
val io = IO(new Bundle{
val in1 = Input(UInt(1.W))
val in2 = Input(UInt(1.W))
val out = Output(UInt())
})
val mod_array= new Array[tocopy](2)
mod_array(0) = Module(new tocopy)
mod_array(0).io.in1:=io.in1
mod_array(0).io.in2:=io.in2
mod_array(1) = Module(new tocopy)
mod_array(1).io.in1:=io.in1
mod_array(1).io.in2:=io.in2
io.out:= mod_array(0).io.out +& mod_array(1).io.out
}
////////////////////////////////////////////////////////////////
//println((new chisel3.stage.ChiselStage).emitVerilog(new exp))*/

240
src/main/scala/lib/ahb_to_axi4.scala Normal file
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@ -0,0 +1,240 @@
//package lib
//import chisel3._
//import chisel3.util._
////import chisel3.experimental.chiselName
//
////@chiselName
//class ahb_to_axi4 extends Module with el2_lib with RequireAsyncReset {
// val io = IO(new Bundle {
// val scan_mode = Input(Bool())
// val bus_clk_en = Input(Bool())
// val clk_override = Input(Bool())
// val axi_awready = Input(Bool())
// val axi_wready = Input(Bool())
// val axi_bvalid = Input(Bool())
// val axi_bresp = Input(UInt(2.W))
// val axi_bid = Input(UInt(TAG.W))
// val axi_arready = Input(Bool())
// val axi_rvalid = Input(Bool())
// val axi_rid = Input(UInt(TAG.W))
// val axi_rdata = Input(UInt(64.W))
// val axi_rresp = Input(UInt(2.W))
// val ahb_haddr = Input(UInt(32.W)) // ahb bus address
// val ahb_hburst = Input(UInt(3.W)) // tied to 0
// val ahb_hmastlock = Input(Bool()) // tied to 0
// val ahb_hprot = Input(UInt(4.W)) // tied to 4'b0011
// val ahb_hsize = Input(UInt(3.W)) // size of bus transaction (possible values 0 =1 =2 =3)
// val ahb_htrans = Input(UInt(2.W)) // Transaction type (possible values 0 =2 only right now)
// val ahb_hwrite = Input(Bool()) // ahb bus write
// val ahb_hwdata = Input(UInt(64.W)) // ahb bus write data
// val ahb_hsel = Input(Bool()) // this slave was selected
// val ahb_hreadyin = Input(Bool()) // previous hready was accepted or not
// // outputs
// val axi_awvalid = Output(Bool())
// val axi_awid = Output(UInt(TAG.W))
// val axi_awaddr = Output(UInt(32.W))
// val axi_awsize = Output(UInt(3.W))
// val axi_awprot = Output(UInt(3.W))
// val axi_awlen = Output(UInt(8.W))
// val axi_awburst = Output(UInt(2.W))
// val axi_wvalid = Output(Bool())
// val axi_wdata = Output(UInt(64.W))
// val axi_wstrb = Output(UInt(8.W))
// val axi_wlast = Output(Bool())
// val axi_bready = Output(Bool())
// val axi_arvalid = Output(Bool())
// val axi_arid = Output(UInt(TAG.W))
// val axi_araddr = Output(UInt(32.W))
// val axi_arsize = Output(UInt(3.W))
// val axi_arprot = Output(UInt(3.W))
// val axi_arlen = Output(UInt(8.W))
// val axi_arburst = Output(UInt(2.W))
// val axi_rready = Output(Bool())
// val ahb_hrdata = Output(UInt(64.W)) // ahb bus read data
// val ahb_hreadyout = Output(Bool()) // slave ready to accept transaction
// val ahb_hresp = Output(Bool()) // slave response (high indicates erro)
// })
// val idle:: wr :: rd :: pend :: Nil = Enum(4)
// val TAG= 1
// val master_wstrb = WireInit(0.U(8.W))
// val buf_state_en = WireInit(false.B)
//
// // Buffer signals (one entry buffer)
// val buf_read_error_in = WireInit(false.B)
// val buf_read_error = WireInit(false.B)
// val buf_rdata = WireInit(0.U(64.W))
// val ahb_hready = WireInit(Bool(), false.B)
// val ahb_hready_q = WireInit(Bool(), false.B)
// val ahb_htrans_in = WireInit(0.U(2.W))
// val ahb_htrans_q = WireInit(0.U(2.W))
// val ahb_hsize_q = WireInit(0.U(3.W))
// val ahb_hwrite_q = WireInit(Bool(), false.B)
// val ahb_haddr_q = WireInit(0.U(32.W))
// val ahb_hwdata_q = WireInit(0.U(64.W))
// val ahb_hresp_q = WireInit(Bool(), false.B)
//
// //Miscellaneous signals
// val ahb_addr_in_iccm = WireInit(Bool(), false.B)
// val ahb_addr_in_iccm_region_nc = WireInit(Bool(), false.B)
//
// // signals needed for the read data coming back from the core and to block any further commands as AHB is a blocking bus
// val buf_rdata_en = WireInit(Bool(), false.B)
// val ahb_bus_addr_clk_en = WireInit(Bool(), false.B)
// val buf_rdata_clk_en = WireInit(Bool(), false.B)
// val ahb_clk = Wire(Clock())
// val ahb_addr_clk = Wire(Clock())
// val buf_rdata_clk = Wire(Clock())
//
// // Command buffer is the holding station where we convert to AXI and send to core
// val cmdbuf_wr_en = WireInit(Bool(), false.B)
// val cmdbuf_rst = WireInit(Bool(), false.B)
// val cmdbuf_full = WireInit(Bool(), false.B)
// val cmdbuf_vld = WireInit(Bool(), false.B)
// val cmdbuf_write = WireInit(Bool(), false.B)
// val cmdbuf_size = WireInit(0.U(2.W))
// val cmdbuf_wstrb = WireInit(0.U(8.W))
// val cmdbuf_addr = WireInit(0.U(32.W))
// val cmdbuf_wdata = WireInit(0.U(64.W))
// val bus_clk = Wire(Clock())
//
// // Address check dccm
// val (ahb_addr_in_dccm, ahb_addr_in_dccm_region_nc) = rvrangecheck_ch(ahb_haddr_q.asUInt,DCCM_SADR.asUInt(),DCCM_SIZE)
//
// // Address check iccm
// if (ICCM_ENABLE == 1) {
// ahb_addr_in_iccm := rvrangecheck_ch(ahb_haddr_q.asUInt, ICCM_SADR.asUInt(), ICCM_SIZE)._1
// ahb_addr_in_iccm_region_nc := rvrangecheck_ch(ahb_haddr_q.asUInt, ICCM_SADR.asUInt(), ICCM_SIZE)._2
// }
// else {
// ahb_addr_in_iccm := 0.U
// ahb_addr_in_iccm_region_nc := 0.U
//
//
// // PIC memory address check
// val (ahb_addr_in_pic, ahb_addr_in_pic_region_nc) = rvrangecheck_ch(ahb_haddr_q.asUInt,PIC_BASE_ADDR.asUInt(),PIC_SIZE)
//
// // FSM to control the bus states and when to block the hready and load the command buffer
// val buf_state = WireInit(idle)
// val buf_nxtstate = WireInit(idle)
// buf_nxtstate := idle
// buf_state_en := false.B
// buf_rdata_en := false.B // signal to load the buffer when the core sends read data back
// buf_read_error_in := false.B // signal indicating that an error came back with the read from the core
// cmdbuf_wr_en := false.B // all clear from the gasket to load the buffer with the command for reads, command/dat for writes
// switch(buf_state){
//
// is(idle) {
// buf_nxtstate := Mux(io.ahb_hwrite, wr, rd)
// buf_state_en := ahb_hready & io.ahb_htrans(1) & io.ahb_hsel // only transition on a valid hrtans
// }
// is(wr) { // Write command recieved last cycle
// buf_nxtstate := Mux((io.ahb_hresp | (io.ahb_htrans(1, 0) === "b0".U) | !io.ahb_hsel).asBool, idle, Mux(io.ahb_hwrite, wr, rd))
// buf_state_en := (!cmdbuf_full | io.ahb_hresp)
// cmdbuf_wr_en := !cmdbuf_full & !(io.ahb_hresp | ((io.ahb_htrans(1, 0) === "b01".U) & io.ahb_hsel)) // Dont send command to the buffer in case of an error or when the master is not ready with the data now.
//
// is(rd) { // Read command recieved last cycle.
// buf_nxtstate := Mux(io.ahb_hresp, idle, pend) // If error go to idle, else wait for read data
// buf_state_en := (!cmdbuf_full | io.ahb_hresp) // only when command can go, or if its an error
// cmdbuf_wr_en := !io.ahb_hresp & !cmdbuf_full // send command only when no error
//
// is(pend) { // Read Command has been sent. Waiting on Data.
// buf_nxtstate := idle // go back for next command and present data next cycle
// buf_state_en := io.axi_rvalid & !cmdbuf_write // read data is back
// buf_rdata_en := buf_state_en // buffer the read data coming back from core
// buf_read_error_in := buf_state_en & io.axi_rresp(1,0).orR // buffer error flag if return has Error ( ECC )
//
//
// buf_state := withClock(ahb_clk){RegEnable(buf_nxtstate,0.U,buf_state_en.asBool())}
//
// master_wstrb := (Fill(8,ahb_hsize_q(2,0) === 0.U) & (1.U << ahb_haddr_q(2,0)).asUInt()) |
// (Fill(8,ahb_hsize_q(2,0) === 1.U) & (3.U << ahb_haddr_q(2,0)).asUInt()) |
// (Fill(8,ahb_hsize_q(2,0) === 2.U) & (15.U << ahb_haddr_q(2,0)).asUInt()) |
// (Fill(8,ahb_hsize_q(2,0) === 3.U) & 255.U)
//
// // AHB signals
// io.ahb_hreadyout := Mux(io.ahb_hresp,(ahb_hresp_q & !ahb_hready_q), ((!cmdbuf_full | (buf_state === idle)) & !(buf_state === rd | buf_state === pend) & !buf_read_error))
// ahb_hready := io.ahb_hreadyout & io.ahb_hreadyin
// ahb_htrans_in := Fill(2,io.ahb_hsel) & io.ahb_htrans(1,0)
// io.ahb_hrdata := buf_rdata(63,0)
// io.ahb_hresp := ((ahb_htrans_q(1,0) =/= 0.U) & (buf_state =/= idle) &
// ((!(ahb_addr_in_dccm | ahb_addr_in_iccm)) | // request not for ICCM or DCCM
// ((ahb_addr_in_iccm | (ahb_addr_in_dccm & ahb_hwrite_q)) & !((ahb_hsize_q(1,0) === 2.U) | (ahb_hsize_q(1,0) === 3.U))) | // ICCM Rd/Wr OR DCCM Wr not the right size
// ((ahb_hsize_q(2,0) === 1.U) & ahb_haddr_q(0)) | // HW size but unaligned
// ((ahb_hsize_q(2,0) === 2.U) & (ahb_haddr_q(1,0)).orR) | // W size but unaligned
// ((ahb_hsize_q(2,0) === 3.U) & (ahb_haddr_q(2,0)).orR))) | // DW size but unaligned
// buf_read_error | // Read ECC error
// (ahb_hresp_q & !ahb_hready_q)
//
// // Buffer signals - needed for the read data and ECC error response
// buf_rdata := withClock(buf_rdata_clk){RegNext(io.axi_rdata,0.U)}
// buf_read_error := withClock(ahb_clk){RegNext(buf_read_error_in,0.U)}
//
// // All the Master signals are captured before presenting it to the command buffer. We check for Hresp before sending it to the cmd buffer.
// ahb_hresp_q := withClock(ahb_clk){RegNext(io.ahb_hresp,0.U)}
// ahb_hready_q := withClock(ahb_clk){RegNext(ahb_hready,0.U)}
// ahb_htrans_q := withClock(ahb_clk){RegNext(ahb_htrans_in,0.U)}
// ahb_hsize_q := withClock(ahb_addr_clk){RegNext(io.ahb_hsize,0.U)}
// ahb_hwrite_q := withClock(ahb_addr_clk){RegNext(io.ahb_hwrite,0.U)}
// ahb_haddr_q := withClock(ahb_addr_clk){RegNext(io.ahb_haddr,0.U)}
//
// // Clock header logic
// ahb_bus_addr_clk_en := io.bus_clk_en & (ahb_hready & io.ahb_htrans(1))
// buf_rdata_clk_en := io.bus_clk_en & buf_rdata_en;
//
// ahb_clk := rvclkhdr(clock, io.bus_clk_en, io.scan_mode)
// ahb_addr_clk := rvclkhdr(clock, ahb_bus_addr_clk_en, io.scan_mode)
// buf_rdata_clk := rvclkhdr(clock, buf_rdata_clk_en, io.scan_mode)
//
// cmdbuf_rst := (((io.axi_awvalid & io.axi_awready) | (io.axi_arvalid & io.axi_arready)) & !cmdbuf_wr_en) | (io.ahb_hresp & !cmdbuf_write)
// cmdbuf_full := (cmdbuf_vld & !((io.axi_awvalid & io.axi_awready) | (io.axi_arvalid & io.axi_arready)))
//
// //rvdffsc
// cmdbuf_vld := withClock(bus_clk) {
// RegEnable("b1".U & Fill("b1".U.getWidth, cmdbuf_rst), 0.U, cmdbuf_wr_en.asBool())
//
// //dffs
// cmdbuf_write := withClock(bus_clk) {
// RegEnable(ahb_hwrite_q, 0.U, cmdbuf_wr_en.asBool())
//
// cmdbuf_size := withClock(bus_clk) {
// RegEnable(ahb_hsize_q, 0.U, cmdbuf_wr_en.asBool())
//
// cmdbuf_wstrb := withClock(bus_clk) {
// RegEnable(master_wstrb, 0.U, cmdbuf_wr_en.asBool())
//
// //rvdffe
// cmdbuf_addr := RegEnable(ahb_haddr_q, 0.U, cmdbuf_wr_en.asBool())
// cmdbuf_wdata := RegEnable(io.ahb_hwdata, 0.U, cmdbuf_wr_en.asBool())
//
// // AXI Write Command Channel
// io.axi_awvalid := cmdbuf_vld & cmdbuf_write
// io.axi_awid := Fill(TAG, 0.U)
// io.axi_awaddr := cmdbuf_addr
// io.axi_awsize := Cat("b0".U, cmdbuf_size(1, 0))
// io.axi_awprot := Fill(3, 0.U)
// io.axi_awlen := Fill(8, 0.U)
// io.axi_awburst := "b01".U
// // AXI Write Data Channel - This is tied to the command channel as we only write the command buffer once we have the data.
// io.axi_wvalid := cmdbuf_vld & cmdbuf_write
// io.axi_wdata := cmdbuf_wdata
// io.axi_wstrb := cmdbuf_wstrb
// io.axi_wlast := "b1".U
// // AXI Write Response - Always ready. AHB does not require a write response.
// io.axi_bready := "b1".U
// // AXI Read Channels
// io.axi_arvalid := cmdbuf_vld & !cmdbuf_write
// io.axi_arid := Fill(TAG, 0.U)
// io.axi_araddr := cmdbuf_addr
// io.axi_arsize := Cat("b0".U, cmdbuf_size(1, 0))
// io.axi_arprot := Fill(3, 0.U)
// io.axi_arlen := Fill(8, 0.U)
// io.axi_arburst := "b01".U
// // AXI Read Response Channel - Always ready as AHB reads are blocking and the the buffer is available for the read coming back always.
// io.axi_rready := true.B
//
//
// bus_clk := rvclkhdr(clock, io.bus_clk_en, io.scan_mode)
//}
//object AHB_main extends App {
// println("Generate Verilog")
// println((new chisel3.stage.ChiselStage).emitVerilog(new ahb_to_axi4()))

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src/main/scala/lib/axi4_to_ahb.scala Normal file
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package lib
import chisel3._
import chisel3.util._
trait Config {
val TAG = 1
}
class axi4_to_ahb_IO extends Bundle with Config {
val scan_mode = Input(Bool())
val bus_clk_en = Input(Bool())
val clk_override = Input(Bool())
val axi_awvalid = Input(Bool())
val axi_awid = Input(UInt(TAG.W)) // [TAG-1:0]
val axi_awaddr = Input(UInt(32.W)) // [31:0]
val axi_awsize = Input(UInt(3.W)) // [2:0]
val axi_awprot = Input(UInt(3.W)) // [2:0]
val axi_wvalid = Input(Bool())
val axi_wdata = Input(UInt(64.W)) // [63:0]
val axi_wstrb = Input(UInt(8.W)) // [7:0]
val axi_wlast = Input(Bool())
val axi_bready = Input(Bool())
val axi_arvalid = Input(Bool())
val axi_arid = Input(UInt(TAG.W)) // [TAG-1:0]
val axi_araddr = Input(UInt(32.W)) // [31:0]
val axi_arsize = Input(UInt(3.W)) // [2:0]
val axi_arprot = Input(UInt(3.W)) // [2:0]
val axi_rready = Input(Bool())
val ahb_hrdata = Input(UInt(64.W)) // [63:0] // ahb bus read data
val ahb_hready = Input(Bool()) // slave ready to accept transaction
val ahb_hresp = Input(Bool()) // slave response (high indicates erro)
//----------------------------outputs---------------------------
val axi_awready = Output(Bool())
val axi_wready = Output(Bool())
val axi_bvalid = Output(Bool())
val axi_bresp = Output(UInt(2.W)) // [1:0]]
val axi_bid = Output(UInt(TAG.W)) // [TAG-1:0]
// AXI Read Channels
val axi_arready = Output(Bool())
val axi_rvalid = Output(Bool())
val axi_rid = Output(UInt(TAG.W)) // [TAG-1:0]
val axi_rdata = Output(UInt(32.W)) // [63:0]
val axi_rresp = Output(UInt(2.W)) // 1:0]
val axi_rlast = Output(Bool())
// AHB-Lite signals
val ahb_haddr = Output(UInt(32.W)) // [31:0] // ahb bus address
val ahb_hburst = Output(UInt(3.W)) // [2:0] // tied to 0
val ahb_hmastlock = Output(Bool()) // tied to 0
val ahb_hprot = Output(UInt(4.W)) // [3:0] // tied to 4'b0011
val ahb_hsize = Output(UInt(3.W)) // [2:0] // size of bus transaction (possible values 0,1,2,3)
val ahb_htrans = Output(UInt(2.W))
val ahb_hwrite = Output(Bool()) // ahb bus write
val ahb_hwdata = Output(UInt(64.W)) // [63:0] // ahb bus write data
}
class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config {
val io = IO(new axi4_to_ahb_IO)
val idle :: cmd_rd :: cmd_wr :: data_rd :: data_wr :: done :: stream_rd :: stream_err_rd :: nil = Enum(8)
val state = RegInit(idle) // typedef enum
val buf_state = RegInit(idle)
val buf_nxtstate = RegInit(idle)
//logic signals
val slave_valid = WireInit(Bool(), init = false.B)
val slave_ready = WireInit(Bool(), init = false.B)
val slave_tag = WireInit(0.U(TAG.W)) // [TAG-1:0]
val slave_rdata = WireInit(0.U(64.W)) // [63:0]
val slave_opc = WireInit(0.U(4.W)) // [3:0]
val wrbuf_en = WireInit(Bool(), init = false.B)
val wrbuf_data_en = WireInit(Bool(), init = false.B)
val wrbuf_cmd_sent = WireInit(Bool(), init = false.B)
val wrbuf_rst = WireInit(Bool(), init = false.B)
val wrbuf_vld = WireInit(Bool(), init = false.B)
val wrbuf_data_vld = WireInit(Bool(), init = false.B)
val wrbuf_tag = WireInit(0.U(TAG.W)) // [TAG-1:0]
val wrbuf_size = WireInit(0.U(3.W)) // [2:0]
val wrbuf_addr = WireInit(0.U(32.W)) // [31:0]
val wrbuf_data = WireInit(0.U(64.W)) // [63:0]
val wrbuf_byteen = WireInit(0.U(8.W)) // [7:0]
val bus_write_clk_en = WireInit(Bool(), init = false.B)
val bus_clk = Wire(Clock())
val bus_write_clk = Wire(Clock())
val master_valid = WireInit(Bool(), init = false.B)
val master_ready = WireInit(0.U(1.W))
val master_tag = WireInit(0.U(TAG.W)) // [TAG-1:0]
val master_addr = WireInit(0.U(32.W)) // [31:0]
val master_wdata = WireInit(0.U(64.W)) // [63:0]
val master_size = WireInit(0.U(3.W)) // [2:0]
val master_opc = WireInit(0.U(3.W)) // [2:0]
val master_byteen = WireInit(0.U(8.W)) // [7:0]
// Buffer signals (one entry buffer)
val buf_addr = WireInit(0.U(32.W)) // [31:0]
val buf_size = WireInit(0.U(2.W)) // [1:0]
val buf_write = WireInit(Bool(), init = false.B)
val buf_byteen = WireInit(0.U(8.W)) // [7:0]
val buf_aligned = WireInit(Bool(), init = false.B)
val buf_data = WireInit(0.U(64.W)) // [63:0]
val buf_tag = WireInit(0.U(TAG.W)) // [TAG-1:0]
//Miscellaneous signals
val buf_rst = WireInit(Bool(), init = false.B)
val buf_tag_in = WireInit(0.U(TAG.W)) // [TAG-1:0]
val buf_addr_in = WireInit(0.U(32.W)) // [31:0]
val buf_byteen_in = WireInit(0.U(8.W)) // [7:0]
val buf_data_in = WireInit(0.U(64.W)) // [63:0]
val buf_write_in = WireInit(Bool(), init = false.B)
val buf_aligned_in = WireInit(Bool(), init = false.B)
val buf_size_in = WireInit(0.U(3.W)) // [2:0]
val buf_state_en = WireInit(Bool(), init = false.B)
val buf_wr_en = WireInit(Bool(), init = false.B)
val buf_data_wr_en = WireInit(Bool(), init = false.B)
val slvbuf_error_en = WireInit(Bool(), init = false.B)
val wr_cmd_vld = WireInit(Bool(), init = false.B)
val cmd_done_rst = WireInit(Bool(), init = false.B)
val cmd_done = WireInit(Bool(), init = false.B)
val cmd_doneQ = WireInit(Bool(), init = false.B)
val trxn_done = WireInit(Bool(), init = false.B)
val buf_cmd_byte_ptr = WireInit(0.U(3.W)) // [2:0]
val buf_cmd_byte_ptrQ = WireInit(0.U(3.W)) // [2:0]
val buf_cmd_nxtbyte_ptr = WireInit(0.U(3.W)) // [2:0]
val buf_cmd_byte_ptr_en = WireInit(Bool(), init = false.B)
val found = WireInit(Bool(), init = false.B)
val slave_valid_pre = WireInit(Bool(), init = false.B)
val ahb_hready_q = WireInit(Bool(), init = false.B)
val ahb_hresp_q = WireInit(Bool(), init = false.B)
val ahb_htrans_q = WireInit(0.U(2.W)) // [1:0]
val ahb_hwrite_q = WireInit(Bool(), init = false.B)
val ahb_hrdata_q = WireInit(0.U(64.W)) // [63:0]
val slvbuf_write = WireInit(Bool(), init = false.B)
val slvbuf_error = WireInit(Bool(), init = false.B)
val slvbuf_tag = WireInit(0.U(TAG.W)) // [TAG-1:0]
val slvbuf_error_in = WireInit(Bool(), init = false.B)
val slvbuf_wr_en = WireInit(Bool(), init = false.B)
val bypass_en = WireInit(Bool(), init = false.B)
val rd_bypass_idle = WireInit(Bool(), init = false.B)
val last_addr_en = WireInit(Bool(), init = false.B)
val last_bus_addr = WireInit(0.U(32.W)) // [31:0]
// Clocks
val buf_clken = WireInit(Bool(), init = false.B)
val slvbuf_clken = WireInit(Bool(), init = false.B)
val ahbm_addr_clken = WireInit(Bool(), init = false.B)
val ahbm_data_clken = WireInit(Bool(), init = false.B)
val buf_clk = Wire(Clock())
//val slvbuf_clk = Wire(Clock())
val ahbm_clk = Wire(Clock())
val ahbm_addr_clk = Wire(Clock())
val ahbm_data_clk = Wire(Clock())
def get_write_size(byteen: UInt) = {
val byteen = WireInit(0.U(8.W))
val size = ("b11".U & (Fill(2, (byteen(7, 0) === "hff".U))) |
("b10".U & (Fill(2, (byteen(7, 0) === "hf0".U) | (byteen(7, 0) === "h0f".U)))) |
("b01".U & (Fill(2, (byteen(7, 0) === "hc0".U) | (byteen(7, 0) === "h30".U) | (byteen(7, 0) === "h0c".U) | (byteen(7, 0) === "h03".U)))))
size
}
def get_write_addr(byteen_e: UInt) = {
val byteen_e = WireInit(0.U(8.W))
val addr = ("h0".U & (Fill(3, (byteen_e(7, 0) === "hff".U) | (byteen_e(7, 0) === "h0f".U) | (byteen_e(7, 0) === "h03".U))) |
("h2".U & (Fill(3, (byteen_e(7, 0) === "h0c".U)))) |
("h4".U & (Fill(3, ((byteen_e(7, 0) === "hf0".U) | (byteen_e(7, 0) === "h03".U)))) |
("h6".U & (Fill(3, (byteen_e(7, 0) === "hc0".U))))))
addr
}
def get_nxtbyte_ptr(current_byte_ptr: UInt, byteen: UInt, get_next: Bool): UInt = {
val start_ptr = Mux(get_next, current_byte_ptr + 1.U, current_byte_ptr)
val temp = (0 until 8).map(j => (byteen(j) & (j.asUInt() >= start_ptr)) -> j.U)
MuxCase(0.U, temp)
}
// Write buffer
wrbuf_en := io.axi_awvalid & io.axi_awready & master_ready
wrbuf_data_en := io.axi_wvalid & io.axi_wready & master_ready
wrbuf_cmd_sent := master_valid & master_ready & (master_opc(2, 1) === "b01".U)
wrbuf_rst := wrbuf_cmd_sent & !wrbuf_en
io.axi_awready := !(wrbuf_vld & !wrbuf_cmd_sent) & master_ready
io.axi_wready := !(wrbuf_data_vld & !wrbuf_cmd_sent) & master_ready
io.axi_arready := !(wrbuf_vld & wrbuf_data_vld) & master_ready
io.axi_rlast := true.B
wr_cmd_vld := wrbuf_vld & wrbuf_data_vld
master_valid := wr_cmd_vld | io.axi_arvalid
master_tag := Mux(wr_cmd_vld.asBool(), wrbuf_tag(TAG - 1, 0), io.axi_arid(TAG - 1, 0))
master_opc := Mux(wr_cmd_vld.asBool(), "b011".U, "b0".U)
master_addr := Mux(wr_cmd_vld.asBool(), wrbuf_addr(31, 0), io.axi_araddr(31, 0))
master_size := Mux(wr_cmd_vld.asBool(), wrbuf_size(2, 0), io.axi_arsize(2, 0))
master_byteen := wrbuf_byteen(7, 0)
master_wdata := wrbuf_data(63, 0)
// AXI response channel signals
io.axi_bvalid := slave_valid & slave_ready & slave_opc(3)
io.axi_bresp := Mux(slave_opc(0), "b10".U, Mux(slave_opc(1), "b11".U, "b0".U))
io.axi_bid := slave_tag(TAG - 1, 0)
io.axi_rvalid := slave_valid & slave_ready & (slave_opc(3, 2) === "b0".U)
io.axi_rresp := Mux(slave_opc(0), "b10".U, Mux(slave_opc(1), "b11".U, "b0".U))
io.axi_rid := slave_tag(TAG - 1, 0)
io.axi_rdata := slave_rdata(63, 0)
slave_ready := io.axi_bready & io.axi_rready
// Clock header logic
bus_write_clk_en := io.bus_clk_en & ((io.axi_awvalid & io.axi_awready) | (io.axi_wvalid & io.axi_wready))
bus_clk := rvclkhdr(clock, io.bus_clk_en, io.scan_mode)
bus_write_clk := rvclkhdr(clock, bus_write_clk_en.asBool(), io.scan_mode)
//State machine
io.ahb_htrans := 0.U
master_ready := 0.U
buf_state_en := 0.U
switch(buf_state) {
is(idle) {
master_ready := 1.U
buf_write_in := (master_opc(2, 1) === "b01".U)
buf_nxtstate := Mux(buf_write_in.asBool(), cmd_wr, cmd_rd)
buf_state_en := master_valid & master_ready
buf_wr_en := buf_state_en
buf_data_wr_en := buf_state_en & (buf_nxtstate === cmd_wr)
buf_cmd_byte_ptr_en := buf_state_en
// ---------------------FROM FUNCTION CHECK LATER
buf_cmd_byte_ptr := Mux(buf_write_in.asBool(), (get_nxtbyte_ptr("b0".U, buf_byteen_in(7, 0), false.B)).asInstanceOf[UInt], master_addr(2, 0))
bypass_en := buf_state_en
rd_bypass_idle := bypass_en & (buf_nxtstate === cmd_rd)
io.ahb_htrans := (Fill(2, bypass_en)) & "b10".U
}
is(cmd_rd) {
buf_nxtstate := Mux((master_valid & (master_opc(2, 0) === "b000".U)).asBool(), stream_rd, data_rd)
buf_state_en := ahb_hready_q & (ahb_htrans_q(1, 0) =/= "b0".U) & !ahb_hwrite_q
cmd_done := buf_state_en & !master_valid
slvbuf_wr_en := buf_state_en
master_ready := (ahb_hready_q & (ahb_htrans_q(1, 0) =/= "b0".U) & !ahb_hwrite_q) & (buf_nxtstate === stream_rd) ////////////TBD////////
buf_wr_en := master_ready
bypass_en := master_ready & master_valid
buf_cmd_byte_ptr := Mux(bypass_en.asBool(), master_addr(2, 0), buf_addr(2, 0))
io.ahb_htrans := "b10".U & (Fill(2, (!buf_state_en | bypass_en)))
}
is(stream_rd) {
master_ready := (ahb_hready_q & !ahb_hresp_q) & !(master_valid & master_opc(2, 1) === "b01".U)
buf_wr_en := (master_valid & master_ready & (master_opc(2, 0) === "b000".U)) // update the fifo if we are streaming the read commands
buf_nxtstate := Mux(ahb_hresp_q.asBool(), stream_err_rd, Mux(buf_wr_en.asBool(), stream_rd, data_rd)) // assuming that the master accpets the slave response right away.
buf_state_en := (ahb_hready_q | ahb_hresp_q)
buf_data_wr_en := buf_state_en
slvbuf_error_in := ahb_hresp_q
slvbuf_error_en := buf_state_en
slave_valid_pre := buf_state_en & !ahb_hresp_q // send a response right away if we are not going through an error response.
cmd_done := buf_state_en & !master_valid // last one of the stream should not send a htrans
bypass_en := master_ready & master_valid & (buf_nxtstate === stream_rd) & buf_state_en
buf_cmd_byte_ptr := Mux(bypass_en.asBool(), master_addr(2, 0), buf_addr(2, 0))
io.ahb_htrans := "b10".U & Fill(2, (!((buf_nxtstate =/= stream_rd) & buf_state_en)))
slvbuf_wr_en := buf_wr_en // shifting the contents from the buf to slv_buf for streaming cases
}
is(stream_err_rd) {
buf_nxtstate := data_rd
buf_state_en := ahb_hready_q & (ahb_htrans_q(1, 0) =/= "b0".U) & !ahb_hwrite_q
slave_valid_pre := buf_state_en
slvbuf_wr_en := buf_state_en // Overwrite slvbuf with buffer
buf_cmd_byte_ptr := buf_addr(2, 0)
io.ahb_htrans := "b10".U(2.W) & Fill(2, !buf_state_en)
}
is(data_rd) {
buf_nxtstate := done
buf_state_en := (ahb_hready_q | ahb_hresp_q)
buf_data_wr_en := buf_state_en
slvbuf_error_in := ahb_hresp_q
slvbuf_error_en := buf_state_en
slvbuf_wr_en := buf_state_en
}
is(cmd_wr) {
buf_nxtstate := data_wr
trxn_done := ahb_hready_q & ahb_hwrite_q & (ahb_htrans_q(1, 0) =/= "b0".U)
buf_state_en := trxn_done
buf_cmd_byte_ptr_en := buf_state_en
slvbuf_wr_en := buf_state_en
buf_cmd_byte_ptr := Mux(trxn_done.asBool(), (get_nxtbyte_ptr(buf_cmd_byte_ptrQ(2, 0), buf_byteen(7, 0), true.B)).asInstanceOf[UInt], buf_cmd_byte_ptrQ)
cmd_done := trxn_done & (buf_aligned | (buf_cmd_byte_ptrQ === "b111".U) | (buf_byteen((get_nxtbyte_ptr(buf_cmd_byte_ptrQ(2, 0), buf_byteen(7, 0), true.B))) === "b0".U))
io.ahb_htrans := Fill(2, !(cmd_done | cmd_doneQ)) & "b10".U
}
is(data_wr) {
buf_state_en := (cmd_doneQ & ahb_hready_q) | ahb_hresp_q
master_ready := ((cmd_doneQ & ahb_hready_q) | ahb_hresp_q) & !ahb_hresp_q & slave_ready //////////TBD///////// // Ready to accept new command if current command done and no error
buf_nxtstate := Mux((ahb_hresp_q | !slave_ready).asBool(), done, Mux((master_valid & master_ready).asBool(), Mux((master_opc(2, 1) === "b01".U), cmd_wr, cmd_rd), idle))
slvbuf_error_in := ahb_hresp_q
slvbuf_error_en := buf_state_en
buf_write_in := (master_opc(2, 1) === "b01".U)
buf_wr_en := buf_state_en & ((buf_nxtstate === cmd_wr) | (buf_nxtstate === cmd_rd))
buf_data_wr_en := buf_wr_en
cmd_done := (ahb_hresp_q | (ahb_hready_q & (ahb_htrans_q(1, 0) =/= "b0".U) & ((buf_cmd_byte_ptrQ === "b111".U) | (buf_byteen((get_nxtbyte_ptr(buf_cmd_byte_ptrQ(2, 0), buf_byteen(7, 0), true.B))) === "b0".U))))
bypass_en := buf_state_en & buf_write_in & (buf_nxtstate === cmd_wr) // Only bypass for writes for the time being
io.ahb_htrans := Fill(2, (!(cmd_done | cmd_doneQ) | bypass_en)) & "b10".U
slave_valid_pre := buf_state_en & (buf_nxtstate =/= done)
trxn_done := ahb_hready_q & ahb_hwrite_q & (ahb_htrans_q(1, 0) =/= "b0".U)
buf_cmd_byte_ptr_en := trxn_done | bypass_en
//val tmp_func = get_nxtbyte_ptr(Fill(3,0.U),buf_byteen_in(7,0),false.B)
//val tmp_func2 = get_nxtbyte_ptr(buf_cmd_byte_ptrQ(2,0),buf_byteen(7,0),true.B)
buf_cmd_byte_ptr := Mux(bypass_en, get_nxtbyte_ptr(Fill(3, 0.U), buf_byteen_in(7, 0), false.B), Mux(trxn_done, get_nxtbyte_ptr(buf_cmd_byte_ptrQ(2, 0), buf_byteen(7, 0), true.B), buf_cmd_byte_ptrQ))
}
is(done) {
buf_nxtstate := idle
buf_state_en := slave_ready
slvbuf_error_en := true.B
slave_valid_pre := true.B
}
}
buf_rst := false.B
cmd_done_rst := slave_valid_pre
buf_addr_in := Cat(master_addr, Mux((buf_aligned_in & (master_opc(2, 1) === "b01".U)).asBool(), get_write_addr(master_byteen(7, 0)), master_addr(2, 0)))
buf_tag_in := master_tag(TAG - 1, 0)
buf_byteen_in := wrbuf_byteen(7,0)
buf_data_in := Mux((buf_state === data_rd), ahb_hrdata_q(63, 0), master_wdata(63, 0))
buf_size_in := Mux((buf_aligned_in & (master_size(1, 0) === "b11".U) & (master_opc(2, 1) === "b01".U)).asBool(), get_write_size(master_byteen(7, 0)), master_size(1, 0))
buf_aligned_in := (master_opc(2, 0) === "b0".U) | // reads are always aligned since they are either DW or sideeffects
(master_size(1, 0) === "b0".U) | (master_size(1, 0) === "b01".U) | (master_size(1, 0) === "b10".U) | // Always aligned for Byte/HW/Word since they can be only for non-idempotent. IFU/SB are always aligned
((master_size(1, 0) === "b11".U) & ((master_byteen(7, 0) === "h3".U) | (master_byteen(7, 0) === "hc".U) | (master_byteen(7, 0) === "h30".U) | (master_byteen(7, 0) === "hc0".U) |
(master_byteen(7, 0) === "hf".U) | (master_byteen(7, 0) === "hf0".U) | (master_byteen(7, 0) === "hff".U)))
// Generate the ahb signals
io.ahb_haddr := Mux(bypass_en.asBool(), Cat(master_addr(31, 3), buf_cmd_byte_ptr(2, 0)), Cat(buf_addr(31, 3), buf_cmd_byte_ptr(2, 0)))
io.ahb_hsize := Mux(bypass_en.asBool(), Cat("b0".U, (Fill(2, buf_aligned_in) & buf_size_in(1, 0))), (Cat("b0".U, (Fill(2, buf_aligned) & buf_size(1, 0)))))
io.ahb_hburst := "b0".U
io.ahb_hmastlock := "b0".U
io.ahb_hprot := Cat("b001".U, ~io.axi_arprot(2))
io.ahb_hwrite := Mux(bypass_en.asBool(), (master_opc(2, 1) === "b01".U), buf_write)
io.ahb_hwdata := buf_data(63, 0)
slave_valid := slave_valid_pre
slave_opc := Cat(Mux(slvbuf_write.asBool(), "b11".U, "b00".U), Fill(2, slvbuf_error) & "b10".U)
slave_rdata := Mux(slvbuf_error.asBool(), Fill(2, last_bus_addr(31, 0)), Mux((buf_state === done), buf_data(63, 0), ahb_hrdata_q(63, 0)))
slave_tag := slvbuf_tag(TAG - 1, 0)
last_addr_en := (io.ahb_htrans(1, 0) =/= "b0".U) & io.ahb_hready & io.ahb_hwrite
//rvdffsc
wrbuf_vld := withClock(bus_clk) {RegEnable("b1".U & Fill("b1".U.getWidth, wrbuf_rst), 0.U, wrbuf_en.asBool())}
wrbuf_data_vld := withClock(bus_clk) {RegEnable("b1".U & Fill("b1".U.getWidth, wrbuf_rst), 0.U, wrbuf_data_en.asBool())}
//rvdffs
wrbuf_tag := withClock(bus_clk) {RegEnable(io.axi_awid(TAG - 1, 0), 0.U, wrbuf_en.asBool())}
wrbuf_size := withClock(bus_clk) {RegEnable(io.axi_awsize(2, 0), 0.U, wrbuf_en.asBool())}
//rvdffe
wrbuf_addr := RegEnable(io.axi_awaddr, 0.U, wrbuf_en.asBool())
wrbuf_data := RegEnable(io.axi_wdata, 0.U, wrbuf_data_en.asBool())
//rvdffs
wrbuf_byteen := withClock(bus_clk) {
RegEnable(io.axi_wstrb(7, 0), 0.U, wrbuf_data_en.asBool())
}
last_bus_addr := withClock(ahbm_clk) {
RegEnable(io.ahb_haddr(31, 0), 0.U, last_addr_en.asBool())
}
//sc
buf_state := withClock(ahbm_clk) {
RegEnable(buf_nxtstate & Fill(buf_nxtstate.getWidth, buf_rst), 0.U, buf_state_en.asBool())
}
//s
buf_write := withClock(buf_clk) {
RegEnable(buf_write_in, 0.U, buf_wr_en.asBool())
}
buf_tag := withClock(buf_clk) {
RegEnable(buf_tag_in(TAG - 1, 0), 0.U, buf_wr_en.asBool())
}
//e
buf_addr := RegEnable(buf_addr_in(31, 0), 0.U, (buf_wr_en & io.bus_clk_en).asBool)
//s
buf_size := withClock(buf_clk) {
RegEnable(buf_size(1, 0), 0.U, buf_wr_en.asBool())
}
buf_aligned := withClock(buf_clk) {
RegEnable(buf_aligned_in, 0.U, buf_wr_en.asBool())
}
buf_byteen := withClock(buf_clk) {
RegEnable(buf_byteen(7, 0), 0.U, buf_wr_en.asBool())
}
//e
buf_data := RegEnable(buf_data_in(63, 0), 0.U, (buf_data_wr_en & io.bus_clk_en).asBool())
//s
slvbuf_write := withClock(buf_clk) {
RegEnable(buf_write, 0.U, slvbuf_wr_en.asBool())
}
slvbuf_tag := withClock(buf_clk) {
RegEnable(buf_tag(TAG - 1, 0), 0.U, slvbuf_wr_en.asBool())
}
slvbuf_error := withClock(ahbm_clk) {
RegEnable(slvbuf_error_in, 0.U, slvbuf_error_en.asBool())
}
//sc
cmd_doneQ := withClock(ahbm_clk) {
RegEnable("b1".U & Fill("b1".U.getWidth, cmd_done_rst), 0.U, cmd_done.asBool())
}
//rvdffs
buf_cmd_byte_ptrQ := withClock(ahbm_clk) {
RegEnable(buf_cmd_byte_ptr(2, 0), 0.U, buf_cmd_byte_ptr_en.asBool())
}
//rvdff
ahb_hready_q := withClock(ahbm_clk) {
RegNext(io.ahb_hready, 0.U)
}
ahb_htrans_q := withClock(ahbm_clk) {
RegNext(io.ahb_htrans(1, 0), 0.U)
}
ahb_hwrite_q := withClock(ahbm_addr_clk) {
RegNext(io.ahb_hwrite, 0.U)
}
ahb_hresp_q := withClock(ahbm_clk) {
RegNext(io.ahb_hresp, 0.U)
}
ahb_hrdata_q := withClock(ahbm_data_clk) {
RegNext(io.ahb_hrdata(63, 0), 0.U)
}
buf_clken := io.bus_clk_en & (buf_wr_en | slvbuf_wr_en | io.clk_override)
ahbm_addr_clken := io.bus_clk_en & ((io.ahb_hready & io.ahb_htrans(1)) | io.clk_override)
ahbm_data_clken := io.bus_clk_en & ((buf_state =/= idle) | io.clk_override)
//Clkhdr
buf_clk := rvclkhdr(clock, buf_clken, io.scan_mode)
ahbm_clk := rvclkhdr(clock, io.bus_clk_en, io.scan_mode)
ahbm_addr_clk := rvclkhdr(clock, ahbm_addr_clken, io.scan_mode)
ahbm_data_clk := rvclkhdr(clock, ahbm_data_clken, io.scan_mode)
}
object AXImain extends App {
println("Generate Verilog")
println((new chisel3.stage.ChiselStage).emitVerilog(new axi4_to_ahb()))
}

2
src/main/scala/lib/el2_lib.scala
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@ -170,6 +170,8 @@ trait el2_lib extends param{
val DATA_MEM_LINE = MEM_CAL val DATA_MEM_LINE = MEM_CAL
val Tag_Word = MEM_CAL._4 val Tag_Word = MEM_CAL._4
implicit def bool2int(b:Boolean) = if (b) 1 else 0
object rvsyncss { object rvsyncss {
def apply(din:UInt,clk:Clock) =withClock(clk){RegNext(withClock(clk){RegNext(din,0.U)},0.U)} def apply(din:UInt,clk:Clock) =withClock(clk){RegNext(withClock(clk){RegNext(din,0.U)},0.U)}
} }

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src/main/scala/lsu/el2_lsu.scala
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@ -421,9 +421,9 @@ class el2_lsu extends Module with RequireAsyncReset with param with el2_lib {
bus_intf.io.end_addr_d := lsu_lsc_ctl.io.end_addr_d bus_intf.io.end_addr_d := lsu_lsc_ctl.io.end_addr_d
bus_intf.io.end_addr_m := lsu_lsc_ctl.io.end_addr_m bus_intf.io.end_addr_m := lsu_lsc_ctl.io.end_addr_m
bus_intf.io.end_addr_r := lsu_lsc_ctl.io.end_addr_r bus_intf.io.end_addr_r := lsu_lsc_ctl.io.end_addr_r
bus_intf.io.store_data_r := dccm_ctl.io.store_data_r bus_intf.io.store_data_r := dccm_ctl.io.store_data_r
bus_intf.io.lsu_pkt_m <> lsu_lsc_ctl.io.lsu_pkt_m bus_intf.io.lsu_pkt_m <> lsu_lsc_ctl.io.lsu_pkt_m
bus_intf.io.lsu_pkt_r <> lsu_lsc_ctl.io.lsu_pkt_r bus_intf.io.lsu_pkt_r <> lsu_lsc_ctl.io.lsu_pkt_r
bus_intf.io.dec_tlu_force_halt := io.dec_tlu_force_halt bus_intf.io.dec_tlu_force_halt := io.dec_tlu_force_halt
bus_intf.io.lsu_commit_r := lsu_lsc_ctl.io.lsu_commit_r bus_intf.io.lsu_commit_r := lsu_lsc_ctl.io.lsu_commit_r
bus_intf.io.is_sideeffects_m := lsu_lsc_ctl.io.is_sideeffects_m bus_intf.io.is_sideeffects_m := lsu_lsc_ctl.io.is_sideeffects_m

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