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Alingner Done

This commit is contained in:
waleed-lm 2020-10-14 19:32:17 +05:00
parent 4e846f6ab3
commit 432a2fdc44
4 changed files with 22 additions and 24 deletions
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30
el2_ifu_aln_ctl.fir
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@ -2360,17 +2360,17 @@ circuit el2_ifu_aln_ctl :
node _T_166 = and(_T_164, _T_165) @[el2_ifu_aln_ctl.scala 184:35] node _T_166 = and(_T_164, _T_165) @[el2_ifu_aln_ctl.scala 184:35]
node _T_167 = bits(_T_166, 0, 0) @[el2_ifu_aln_ctl.scala 184:52] node _T_167 = bits(_T_166, 0, 0) @[el2_ifu_aln_ctl.scala 184:52]
node _T_168 = or(q0off, f0_shift_2B) @[el2_ifu_aln_ctl.scala 184:76] node _T_168 = or(q0off, f0_shift_2B) @[el2_ifu_aln_ctl.scala 184:76]
node _T_169 = bits(qwen, 0, 0) @[el2_ifu_aln_ctl.scala 185:11] node _T_169 = bits(qwen, 0, 0) @[el2_ifu_aln_ctl.scala 185:31]
node _T_170 = eq(_T_169, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 185:6] node _T_170 = eq(_T_169, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 185:26]
node _T_171 = eq(rdptr, UInt<2>("h02")) @[el2_ifu_aln_ctl.scala 185:23] node _T_171 = eq(rdptr, UInt<2>("h02")) @[el2_ifu_aln_ctl.scala 185:43]
node _T_172 = and(_T_170, _T_171) @[el2_ifu_aln_ctl.scala 185:15] node _T_172 = and(_T_170, _T_171) @[el2_ifu_aln_ctl.scala 185:35]
node _T_173 = bits(_T_172, 0, 0) @[el2_ifu_aln_ctl.scala 185:32] node _T_173 = bits(_T_172, 0, 0) @[el2_ifu_aln_ctl.scala 185:52]
node _T_174 = or(q0off, f1_shift_2B) @[el2_ifu_aln_ctl.scala 185:56] node _T_174 = or(q0off, f1_shift_2B) @[el2_ifu_aln_ctl.scala 185:76]
node _T_175 = bits(qwen, 0, 0) @[el2_ifu_aln_ctl.scala 186:11] node _T_175 = bits(qwen, 0, 0) @[el2_ifu_aln_ctl.scala 186:31]
node _T_176 = eq(_T_175, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 186:6] node _T_176 = eq(_T_175, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 186:26]
node _T_177 = eq(rdptr, UInt<1>("h01")) @[el2_ifu_aln_ctl.scala 186:23] node _T_177 = eq(rdptr, UInt<1>("h01")) @[el2_ifu_aln_ctl.scala 186:43]
node _T_178 = and(_T_176, _T_177) @[el2_ifu_aln_ctl.scala 186:15] node _T_178 = and(_T_176, _T_177) @[el2_ifu_aln_ctl.scala 186:35]
node _T_179 = bits(_T_178, 0, 0) @[el2_ifu_aln_ctl.scala 186:32] node _T_179 = bits(_T_178, 0, 0) @[el2_ifu_aln_ctl.scala 186:52]
node _T_180 = mux(_T_167, _T_168, UInt<1>("h00")) @[Mux.scala 27:72] node _T_180 = mux(_T_167, _T_168, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_181 = mux(_T_173, _T_174, UInt<1>("h00")) @[Mux.scala 27:72] node _T_181 = mux(_T_173, _T_174, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_182 = mux(_T_179, q0off, UInt<1>("h00")) @[Mux.scala 27:72] node _T_182 = mux(_T_179, q0off, UInt<1>("h00")) @[Mux.scala 27:72]
@ -3138,10 +3138,10 @@ circuit el2_ifu_aln_ctl :
node _T_788 = bits(shift_2B, 0, 0) @[el2_ifu_aln_ctl.scala 415:37] node _T_788 = bits(shift_2B, 0, 0) @[el2_ifu_aln_ctl.scala 415:37]
node _T_789 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 415:52] node _T_789 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 415:52]
node _T_790 = bits(shift_4B, 0, 0) @[el2_ifu_aln_ctl.scala 415:66] node _T_790 = bits(shift_4B, 0, 0) @[el2_ifu_aln_ctl.scala 415:66]
node _T_791 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 415:83] node _T_791 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 415:82]
node _T_792 = eq(_T_791, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 415:77] node _T_792 = bits(f0val, 1, 1) @[el2_ifu_aln_ctl.scala 415:94]
node _T_793 = bits(f0val, 0, 0) @[el2_ifu_aln_ctl.scala 415:94] node _T_793 = eq(_T_792, UInt<1>("h00")) @[el2_ifu_aln_ctl.scala 415:88]
node _T_794 = and(_T_792, _T_793) @[el2_ifu_aln_ctl.scala 415:87] node _T_794 = and(_T_791, _T_793) @[el2_ifu_aln_ctl.scala 415:86]
node _T_795 = mux(_T_788, _T_789, UInt<1>("h00")) @[Mux.scala 27:72] node _T_795 = mux(_T_788, _T_789, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_796 = mux(_T_790, _T_794, UInt<1>("h00")) @[Mux.scala 27:72] node _T_796 = mux(_T_790, _T_794, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_797 = or(_T_795, _T_796) @[Mux.scala 27:72] node _T_797 = or(_T_795, _T_796) @[Mux.scala 27:72]

10
el2_ifu_aln_ctl.v
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@ -764,9 +764,7 @@ module el2_ifu_aln_ctl(
wire _T_118 = ~qwen[2]; // @[el2_ifu_aln_ctl.scala 176:26] wire _T_118 = ~qwen[2]; // @[el2_ifu_aln_ctl.scala 176:26]
wire _T_120 = _T_118 & _T_188; // @[el2_ifu_aln_ctl.scala 176:35] wire _T_120 = _T_118 & _T_188; // @[el2_ifu_aln_ctl.scala 176:35]
wire _T_795 = shift_2B & f0val[0]; // @[Mux.scala 27:72] wire _T_795 = shift_2B & f0val[0]; // @[Mux.scala 27:72]
wire _T_792 = ~f0val[0]; // @[el2_ifu_aln_ctl.scala 415:77] wire _T_796 = shift_4B & _T_802; // @[Mux.scala 27:72]
wire _T_794 = _T_792 & f0val[0]; // @[el2_ifu_aln_ctl.scala 415:87]
wire _T_796 = shift_4B & _T_794; // @[Mux.scala 27:72]
wire f0_shift_2B = _T_795 | _T_796; // @[Mux.scala 27:72] wire f0_shift_2B = _T_795 | _T_796; // @[Mux.scala 27:72]
wire _T_122 = q2off | f0_shift_2B; // @[el2_ifu_aln_ctl.scala 176:74] wire _T_122 = q2off | f0_shift_2B; // @[el2_ifu_aln_ctl.scala 176:74]
wire _T_126 = _T_118 & _T_187; // @[el2_ifu_aln_ctl.scala 177:15] wire _T_126 = _T_118 & _T_187; // @[el2_ifu_aln_ctl.scala 177:15]
@ -789,9 +787,9 @@ module el2_ifu_aln_ctl(
wire _T_164 = ~qwen[0]; // @[el2_ifu_aln_ctl.scala 184:26] wire _T_164 = ~qwen[0]; // @[el2_ifu_aln_ctl.scala 184:26]
wire _T_166 = _T_164 & _T_186; // @[el2_ifu_aln_ctl.scala 184:35] wire _T_166 = _T_164 & _T_186; // @[el2_ifu_aln_ctl.scala 184:35]
wire _T_168 = q0off | f0_shift_2B; // @[el2_ifu_aln_ctl.scala 184:76] wire _T_168 = q0off | f0_shift_2B; // @[el2_ifu_aln_ctl.scala 184:76]
wire _T_172 = _T_164 & _T_188; // @[el2_ifu_aln_ctl.scala 185:15] wire _T_172 = _T_164 & _T_188; // @[el2_ifu_aln_ctl.scala 185:35]
wire _T_174 = q0off | f1_shift_2B; // @[el2_ifu_aln_ctl.scala 185:56] wire _T_174 = q0off | f1_shift_2B; // @[el2_ifu_aln_ctl.scala 185:76]
wire _T_178 = _T_164 & _T_187; // @[el2_ifu_aln_ctl.scala 186:15] wire _T_178 = _T_164 & _T_187; // @[el2_ifu_aln_ctl.scala 186:35]
wire _T_180 = _T_166 & _T_168; // @[Mux.scala 27:72] wire _T_180 = _T_166 & _T_168; // @[Mux.scala 27:72]
wire _T_181 = _T_172 & _T_174; // @[Mux.scala 27:72] wire _T_181 = _T_172 & _T_174; // @[Mux.scala 27:72]
wire _T_182 = _T_178 & q0off; // @[Mux.scala 27:72] wire _T_182 = _T_178 & q0off; // @[Mux.scala 27:72]

2
src/main/scala/ifu/el2_ifu_aln_ctl.scala
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@ -412,7 +412,7 @@ class el2_ifu_aln_ctl extends Module with el2_lib with RequireAsyncReset {
shift_2B := i0_shift & first2B shift_2B := i0_shift & first2B
shift_4B := i0_shift & first4B shift_4B := i0_shift & first4B
f0_shift_2B := Mux1H(Seq(shift_2B.asBool -> f0val(0), shift_4B.asBool -> (!f0val(0) & f0val(0)))) f0_shift_2B := Mux1H(Seq(shift_2B.asBool -> f0val(0), shift_4B.asBool -> (f0val(0) & !f0val(1))))
f1_shift_2B := f0val(0) & !f0val(1) & shift_4B f1_shift_2B := f0val(0) & !f0val(1) & shift_4B
} }

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target/scala-2.12/classes/ifu/el2_ifu_aln_ctl.class
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