colin
/
quasar
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

slv_error corrected

This commit is contained in:
​Laraib Khan 2021-01-14 10:12:56 +05:00
parent 9479360020
commit 43402819b0
10 changed files with 608 additions and 611 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

878
axi4_to_ahb.fir
View File

File diff suppressed because it is too large Load Diff

300
axi4_to_ahb.v
View File

@ -124,19 +124,19 @@ module axi4_to_ahb(
wire _T_99 = 3'h1 == buf_state; // @[Conditional.scala 37:30]
reg ahb_hready_q; // @[Reg.scala 27:20]
reg [1:0] ahb_htrans_q; // @[Reg.scala 27:20]
wire _T_106 = ahb_htrans_q != 2'h0; // @[axi4_to_ahb.scala 178:58]
wire _T_107 = ahb_hready_q & _T_106; // @[axi4_to_ahb.scala 178:36]
wire _T_106 = ahb_htrans_q != 2'h0; // @[axi4_to_ahb.scala 177:58]
wire _T_107 = ahb_hready_q & _T_106; // @[axi4_to_ahb.scala 177:36]
reg ahb_hwrite_q; // @[Reg.scala 27:20]
wire _T_108 = ~ahb_hwrite_q; // @[axi4_to_ahb.scala 178:72]
wire _T_109 = _T_107 & _T_108; // @[axi4_to_ahb.scala 178:70]
wire _T_108 = ~ahb_hwrite_q; // @[axi4_to_ahb.scala 177:72]
wire _T_109 = _T_107 & _T_108; // @[axi4_to_ahb.scala 177:70]
wire _T_134 = 3'h6 == buf_state; // @[Conditional.scala 37:30]
reg ahb_hresp_q; // @[Reg.scala 27:20]
wire _T_154 = ahb_hready_q | ahb_hresp_q; // @[axi4_to_ahb.scala 192:37]
wire _T_154 = ahb_hready_q | ahb_hresp_q; // @[axi4_to_ahb.scala 191:37]
wire _T_173 = 3'h7 == buf_state; // @[Conditional.scala 37:30]
wire _T_184 = 3'h3 == buf_state; // @[Conditional.scala 37:30]
wire _T_186 = 3'h2 == buf_state; // @[Conditional.scala 37:30]
wire _T_187 = ahb_hready_q & ahb_hwrite_q; // @[axi4_to_ahb.scala 224:33]
wire _T_190 = _T_187 & _T_106; // @[axi4_to_ahb.scala 224:48]
wire _T_187 = ahb_hready_q & ahb_hwrite_q; // @[axi4_to_ahb.scala 223:33]
wire _T_190 = _T_187 & _T_106; // @[axi4_to_ahb.scala 223:48]
wire _T_279 = 3'h4 == buf_state; // @[Conditional.scala 37:30]
wire _GEN_16 = _T_279 & _T_190; // @[Conditional.scala 39:67]
wire _GEN_20 = _T_186 ? _T_190 : _GEN_16; // @[Conditional.scala 39:67]
@ -146,8 +146,8 @@ module axi4_to_ahb(
wire _GEN_96 = _T_99 ? 1'h0 : _GEN_80; // @[Conditional.scala 39:67]
wire trxn_done = _T_47 ? 1'h0 : _GEN_96; // @[Conditional.scala 40:58]
reg cmd_doneQ; // @[Reg.scala 27:20]
wire _T_280 = cmd_doneQ & ahb_hready_q; // @[axi4_to_ahb.scala 234:34]
wire _T_281 = _T_280 | ahb_hresp_q; // @[axi4_to_ahb.scala 234:50]
wire _T_280 = cmd_doneQ & ahb_hready_q; // @[axi4_to_ahb.scala 233:34]
wire _T_281 = _T_280 | ahb_hresp_q; // @[axi4_to_ahb.scala 233:50]
wire _T_438 = 3'h5 == buf_state; // @[Conditional.scala 37:30]
wire slave_ready = io_axi_b_ready & io_axi_r_ready; // @[axi4_to_ahb.scala 158:33]
wire _GEN_2 = _T_438 & slave_ready; // @[Conditional.scala 39:67]
@ -170,18 +170,18 @@ module axi4_to_ahb(
wire _GEN_98 = _T_99 ? 1'h0 : _GEN_82; // @[Conditional.scala 39:67]
wire buf_write_in = _T_47 ? _T_49 : _GEN_98; // @[Conditional.scala 40:58]
wire [2:0] _T_51 = buf_write_in ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 164:26]
wire _T_101 = master_opc == 3'h0; // @[axi4_to_ahb.scala 177:61]
wire _T_102 = master_valid & _T_101; // @[axi4_to_ahb.scala 177:41]
wire [2:0] _T_104 = _T_102 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 177:26]
wire _T_122 = _T_104 == 3'h6; // @[axi4_to_ahb.scala 181:174]
wire _T_123 = _T_109 & _T_122; // @[axi4_to_ahb.scala 181:88]
wire _T_135 = ~ahb_hresp_q; // @[axi4_to_ahb.scala 189:39]
wire _T_136 = ahb_hready_q & _T_135; // @[axi4_to_ahb.scala 189:37]
wire _T_139 = master_valid & _T_49; // @[axi4_to_ahb.scala 189:70]
wire _T_140 = ~_T_139; // @[axi4_to_ahb.scala 189:55]
wire _T_141 = _T_136 & _T_140; // @[axi4_to_ahb.scala 189:53]
wire _T_283 = buf_state_en & _T_135; // @[axi4_to_ahb.scala 235:36]
wire _T_284 = _T_283 & slave_ready; // @[axi4_to_ahb.scala 235:51]
wire _T_101 = master_opc == 3'h0; // @[axi4_to_ahb.scala 176:61]
wire _T_102 = master_valid & _T_101; // @[axi4_to_ahb.scala 176:41]
wire [2:0] _T_104 = _T_102 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 176:26]
wire _T_122 = _T_104 == 3'h6; // @[axi4_to_ahb.scala 180:174]
wire _T_123 = _T_109 & _T_122; // @[axi4_to_ahb.scala 180:88]
wire _T_135 = ~ahb_hresp_q; // @[axi4_to_ahb.scala 188:39]
wire _T_136 = ahb_hready_q & _T_135; // @[axi4_to_ahb.scala 188:37]
wire _T_139 = master_valid & _T_49; // @[axi4_to_ahb.scala 188:70]
wire _T_140 = ~_T_139; // @[axi4_to_ahb.scala 188:55]
wire _T_141 = _T_136 & _T_140; // @[axi4_to_ahb.scala 188:53]
wire _T_283 = buf_state_en & _T_135; // @[axi4_to_ahb.scala 234:36]
wire _T_284 = _T_283 & slave_ready; // @[axi4_to_ahb.scala 234:51]
wire _GEN_5 = _T_279 & _T_284; // @[Conditional.scala 39:67]
wire _GEN_27 = _T_186 ? 1'h0 : _GEN_5; // @[Conditional.scala 39:67]
wire _GEN_46 = _T_184 ? 1'h0 : _GEN_27; // @[Conditional.scala 39:67]
@ -189,15 +189,15 @@ module axi4_to_ahb(
wire _GEN_67 = _T_134 ? _T_141 : _GEN_63; // @[Conditional.scala 39:67]
wire _GEN_87 = _T_99 ? _T_123 : _GEN_67; // @[Conditional.scala 39:67]
wire master_ready = _T_47 | _GEN_87; // @[Conditional.scala 40:58]
wire _T_147 = master_valid & master_ready; // @[axi4_to_ahb.scala 191:82]
wire _T_150 = _T_147 & _T_101; // @[axi4_to_ahb.scala 191:97]
wire [2:0] _T_152 = _T_150 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 191:67]
wire [2:0] _T_153 = ahb_hresp_q ? 3'h7 : _T_152; // @[axi4_to_ahb.scala 191:26]
wire _T_285 = ~slave_ready; // @[axi4_to_ahb.scala 236:42]
wire _T_286 = ahb_hresp_q | _T_285; // @[axi4_to_ahb.scala 236:40]
wire [2:0] _T_291 = _T_49 ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 236:101]
wire [2:0] _T_292 = master_valid ? _T_291 : 3'h0; // @[axi4_to_ahb.scala 236:66]
wire [2:0] _T_293 = _T_286 ? 3'h5 : _T_292; // @[axi4_to_ahb.scala 236:26]
wire _T_147 = master_valid & master_ready; // @[axi4_to_ahb.scala 190:82]
wire _T_150 = _T_147 & _T_101; // @[axi4_to_ahb.scala 190:97]
wire [2:0] _T_152 = _T_150 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 190:67]
wire [2:0] _T_153 = ahb_hresp_q ? 3'h7 : _T_152; // @[axi4_to_ahb.scala 190:26]
wire _T_285 = ~slave_ready; // @[axi4_to_ahb.scala 235:42]
wire _T_286 = ahb_hresp_q | _T_285; // @[axi4_to_ahb.scala 235:40]
wire [2:0] _T_291 = _T_49 ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 235:101]
wire [2:0] _T_292 = master_valid ? _T_291 : 3'h0; // @[axi4_to_ahb.scala 235:66]
wire [2:0] _T_293 = _T_286 ? 3'h5 : _T_292; // @[axi4_to_ahb.scala 235:26]
wire [2:0] _GEN_6 = _T_279 ? _T_293 : 3'h0; // @[Conditional.scala 39:67]
wire [2:0] _GEN_19 = _T_186 ? 3'h4 : _GEN_6; // @[Conditional.scala 39:67]
wire [2:0] _GEN_35 = _T_184 ? 3'h5 : _GEN_19; // @[Conditional.scala 39:67]
@ -216,8 +216,8 @@ module axi4_to_ahb(
wire [2:0] master_size = wr_cmd_vld ? wrbuf_size : io_axi_ar_bits_size; // @[axi4_to_ahb.scala 145:21]
reg [7:0] wrbuf_byteen; // @[Reg.scala 27:20]
reg [63:0] wrbuf_data; // @[Reg.scala 27:20]
wire _T_356 = buf_nxtstate != 3'h5; // @[axi4_to_ahb.scala 246:55]
wire _T_357 = buf_state_en & _T_356; // @[axi4_to_ahb.scala 246:39]
wire _T_356 = buf_nxtstate != 3'h5; // @[axi4_to_ahb.scala 245:55]
wire _T_357 = buf_state_en & _T_356; // @[axi4_to_ahb.scala 245:39]
wire _GEN_15 = _T_279 ? _T_357 : _T_438; // @[Conditional.scala 39:67]
wire _GEN_34 = _T_186 ? 1'h0 : _GEN_15; // @[Conditional.scala 39:67]
wire _GEN_50 = _T_184 ? 1'h0 : _GEN_34; // @[Conditional.scala 39:67]
@ -227,20 +227,20 @@ module axi4_to_ahb(
wire slave_valid_pre = _T_47 ? 1'h0 : _GEN_95; // @[Conditional.scala 40:58]
wire _T_28 = slave_valid_pre & slave_ready; // @[axi4_to_ahb.scala 150:33]
reg slvbuf_write; // @[Reg.scala 27:20]
wire [1:0] _T_595 = slvbuf_write ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 280:23]
wire [1:0] _T_595 = slvbuf_write ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 279:23]
reg slvbuf_error; // @[Reg.scala 27:20]
wire [1:0] _T_597 = slvbuf_error ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire [1:0] _T_598 = _T_597 & 2'h2; // @[axi4_to_ahb.scala 280:88]
wire [1:0] _T_598 = _T_597 & 2'h2; // @[axi4_to_ahb.scala 279:88]
wire [3:0] slave_opc = {_T_595,_T_598}; // @[Cat.scala 29:58]
wire [1:0] _T_33 = slave_opc[1] ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 151:55]
reg slvbuf_tag; // @[Reg.scala 27:20]
wire _T_38 = slave_opc[3:2] == 2'h0; // @[axi4_to_ahb.scala 154:66]
reg [31:0] last_bus_addr; // @[Reg.scala 27:20]
wire [63:0] _T_602 = {last_bus_addr,last_bus_addr}; // @[Cat.scala 29:58]
wire _T_603 = buf_state == 3'h5; // @[axi4_to_ahb.scala 281:91]
wire _T_603 = buf_state == 3'h5; // @[axi4_to_ahb.scala 280:91]
reg [63:0] buf_data; // @[Reg.scala 27:20]
reg [63:0] ahb_hrdata_q; // @[Reg.scala 27:20]
wire [63:0] _T_606 = _T_603 ? buf_data : ahb_hrdata_q; // @[axi4_to_ahb.scala 281:79]
wire [63:0] _T_606 = _T_603 ? buf_data : ahb_hrdata_q; // @[axi4_to_ahb.scala 280:79]
wire _T_53 = buf_nxtstate == 3'h2; // @[axi4_to_ahb.scala 167:54]
wire _T_54 = buf_state_en & _T_53; // @[axi4_to_ahb.scala 167:38]
wire [2:0] _T_85 = wrbuf_byteen[6] ? 3'h6 : 3'h7; // @[Mux.scala 98:16]
@ -250,14 +250,14 @@ module axi4_to_ahb(
wire [2:0] _T_89 = wrbuf_byteen[2] ? 3'h2 : _T_88; // @[Mux.scala 98:16]
wire [2:0] _T_90 = wrbuf_byteen[1] ? 3'h1 : _T_89; // @[Mux.scala 98:16]
wire [2:0] _T_91 = wrbuf_byteen[0] ? 3'h0 : _T_90; // @[Mux.scala 98:16]
wire [2:0] _T_93 = buf_write_in ? _T_91 : master_addr[2:0]; // @[axi4_to_ahb.scala 170:30]
wire _T_94 = buf_nxtstate == 3'h1; // @[axi4_to_ahb.scala 172:51]
wire _T_124 = master_ready & master_valid; // @[axi4_to_ahb.scala 183:33]
wire _T_160 = buf_nxtstate == 3'h6; // @[axi4_to_ahb.scala 198:64]
wire _T_161 = _T_124 & _T_160; // @[axi4_to_ahb.scala 198:48]
wire _T_162 = _T_161 & buf_state_en; // @[axi4_to_ahb.scala 198:79]
wire _T_347 = buf_state_en & buf_write_in; // @[axi4_to_ahb.scala 244:33]
wire _T_349 = _T_347 & _T_53; // @[axi4_to_ahb.scala 244:48]
wire [2:0] _T_93 = buf_write_in ? _T_91 : master_addr[2:0]; // @[axi4_to_ahb.scala 169:30]
wire _T_94 = buf_nxtstate == 3'h1; // @[axi4_to_ahb.scala 171:51]
wire _T_124 = master_ready & master_valid; // @[axi4_to_ahb.scala 182:33]
wire _T_160 = buf_nxtstate == 3'h6; // @[axi4_to_ahb.scala 197:64]
wire _T_161 = _T_124 & _T_160; // @[axi4_to_ahb.scala 197:48]
wire _T_162 = _T_161 & buf_state_en; // @[axi4_to_ahb.scala 197:79]
wire _T_347 = buf_state_en & buf_write_in; // @[axi4_to_ahb.scala 243:33]
wire _T_349 = _T_347 & _T_53; // @[axi4_to_ahb.scala 243:48]
wire _GEN_13 = _T_279 & _T_349; // @[Conditional.scala 39:67]
wire _GEN_33 = _T_186 ? 1'h0 : _GEN_13; // @[Conditional.scala 39:67]
wire _GEN_49 = _T_184 ? 1'h0 : _GEN_33; // @[Conditional.scala 39:67]
@ -266,22 +266,22 @@ module axi4_to_ahb(
wire _GEN_89 = _T_99 ? _T_124 : _GEN_76; // @[Conditional.scala 39:67]
wire bypass_en = _T_47 ? buf_state_en : _GEN_89; // @[Conditional.scala 40:58]
wire [1:0] _T_97 = bypass_en ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire [1:0] _T_98 = _T_97 & 2'h2; // @[axi4_to_ahb.scala 173:49]
wire _T_110 = ~master_valid; // @[axi4_to_ahb.scala 179:34]
wire _T_111 = buf_state_en & _T_110; // @[axi4_to_ahb.scala 179:32]
wire [1:0] _T_98 = _T_97 & 2'h2; // @[axi4_to_ahb.scala 172:49]
wire _T_110 = ~master_valid; // @[axi4_to_ahb.scala 178:34]
wire _T_111 = buf_state_en & _T_110; // @[axi4_to_ahb.scala 178:32]
reg [31:0] buf_addr; // @[Reg.scala 27:20]
wire [2:0] _T_128 = bypass_en ? master_addr[2:0] : buf_addr[2:0]; // @[axi4_to_ahb.scala 184:30]
wire _T_129 = ~buf_state_en; // @[axi4_to_ahb.scala 185:48]
wire _T_130 = _T_129 | bypass_en; // @[axi4_to_ahb.scala 185:62]
wire [2:0] _T_128 = bypass_en ? master_addr[2:0] : buf_addr[2:0]; // @[axi4_to_ahb.scala 183:30]
wire _T_129 = ~buf_state_en; // @[axi4_to_ahb.scala 184:48]
wire _T_130 = _T_129 | bypass_en; // @[axi4_to_ahb.scala 184:62]
wire [1:0] _T_132 = _T_130 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire [1:0] _T_133 = 2'h2 & _T_132; // @[axi4_to_ahb.scala 185:36]
wire _T_167 = buf_nxtstate != 3'h6; // @[axi4_to_ahb.scala 200:63]
wire _T_168 = _T_167 & buf_state_en; // @[axi4_to_ahb.scala 200:78]
wire _T_169 = ~_T_168; // @[axi4_to_ahb.scala 200:47]
wire [1:0] _T_133 = 2'h2 & _T_132; // @[axi4_to_ahb.scala 184:36]
wire _T_167 = buf_nxtstate != 3'h6; // @[axi4_to_ahb.scala 199:63]
wire _T_168 = _T_167 & buf_state_en; // @[axi4_to_ahb.scala 199:78]
wire _T_169 = ~_T_168; // @[axi4_to_ahb.scala 199:47]
wire [1:0] _T_171 = _T_169 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire [1:0] _T_172 = 2'h2 & _T_171; // @[axi4_to_ahb.scala 200:36]
wire [1:0] _T_172 = 2'h2 & _T_171; // @[axi4_to_ahb.scala 199:36]
wire [1:0] _T_182 = _T_129 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire [1:0] _T_183 = 2'h2 & _T_182; // @[axi4_to_ahb.scala 210:41]
wire [1:0] _T_183 = 2'h2 & _T_182; // @[axi4_to_ahb.scala 209:41]
reg [2:0] buf_cmd_byte_ptrQ; // @[Reg.scala 27:20]
reg [7:0] buf_byteen; // @[Reg.scala 27:20]
wire [2:0] _T_195 = buf_cmd_byte_ptrQ + 3'h1; // @[axi4_to_ahb.scala 136:52]
@ -306,17 +306,17 @@ module axi4_to_ahb(
wire [2:0] _T_226 = _T_205 ? 3'h2 : _T_225; // @[Mux.scala 98:16]
wire [2:0] _T_227 = _T_202 ? 3'h1 : _T_226; // @[Mux.scala 98:16]
wire [2:0] _T_228 = _T_199 ? 3'h0 : _T_227; // @[Mux.scala 98:16]
wire [2:0] _T_229 = trxn_done ? _T_228 : buf_cmd_byte_ptrQ; // @[axi4_to_ahb.scala 228:30]
wire _T_230 = buf_cmd_byte_ptrQ == 3'h7; // @[axi4_to_ahb.scala 229:65]
wire [2:0] _T_229 = trxn_done ? _T_228 : buf_cmd_byte_ptrQ; // @[axi4_to_ahb.scala 227:30]
wire _T_230 = buf_cmd_byte_ptrQ == 3'h7; // @[axi4_to_ahb.scala 228:65]
reg buf_aligned; // @[Reg.scala 27:20]
wire _T_231 = buf_aligned | _T_230; // @[axi4_to_ahb.scala 229:44]
wire [7:0] _T_269 = buf_byteen >> _T_228; // @[axi4_to_ahb.scala 229:92]
wire _T_271 = ~_T_269[0]; // @[axi4_to_ahb.scala 229:163]
wire _T_272 = _T_231 | _T_271; // @[axi4_to_ahb.scala 229:79]
wire _T_273 = trxn_done & _T_272; // @[axi4_to_ahb.scala 229:29]
wire _T_344 = _T_230 | _T_271; // @[axi4_to_ahb.scala 243:38]
wire _T_345 = _T_107 & _T_344; // @[axi4_to_ahb.scala 242:79]
wire _T_346 = ahb_hresp_q | _T_345; // @[axi4_to_ahb.scala 242:32]
wire _T_231 = buf_aligned | _T_230; // @[axi4_to_ahb.scala 228:44]
wire [7:0] _T_269 = buf_byteen >> _T_228; // @[axi4_to_ahb.scala 228:92]
wire _T_271 = ~_T_269[0]; // @[axi4_to_ahb.scala 228:163]
wire _T_272 = _T_231 | _T_271; // @[axi4_to_ahb.scala 228:79]
wire _T_273 = trxn_done & _T_272; // @[axi4_to_ahb.scala 228:29]
wire _T_344 = _T_230 | _T_271; // @[axi4_to_ahb.scala 242:38]
wire _T_345 = _T_107 & _T_344; // @[axi4_to_ahb.scala 241:79]
wire _T_346 = ahb_hresp_q | _T_345; // @[axi4_to_ahb.scala 241:32]
wire _GEN_12 = _T_279 & _T_346; // @[Conditional.scala 39:67]
wire _GEN_25 = _T_186 ? _T_273 : _GEN_12; // @[Conditional.scala 39:67]
wire _GEN_44 = _T_184 ? 1'h0 : _GEN_25; // @[Conditional.scala 39:67]
@ -324,17 +324,17 @@ module axi4_to_ahb(
wire _GEN_75 = _T_134 ? _T_111 : _GEN_62; // @[Conditional.scala 39:67]
wire _GEN_85 = _T_99 ? _T_111 : _GEN_75; // @[Conditional.scala 39:67]
wire cmd_done = _T_47 ? 1'h0 : _GEN_85; // @[Conditional.scala 40:58]
wire _T_274 = cmd_done | cmd_doneQ; // @[axi4_to_ahb.scala 230:47]
wire _T_275 = ~_T_274; // @[axi4_to_ahb.scala 230:36]
wire _T_274 = cmd_done | cmd_doneQ; // @[axi4_to_ahb.scala 229:47]
wire _T_275 = ~_T_274; // @[axi4_to_ahb.scala 229:36]
wire [1:0] _T_277 = _T_275 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire [1:0] _T_278 = _T_277 & 2'h2; // @[axi4_to_ahb.scala 230:61]
wire _T_298 = _T_53 | _T_94; // @[axi4_to_ahb.scala 240:62]
wire _T_299 = buf_state_en & _T_298; // @[axi4_to_ahb.scala 240:33]
wire _T_352 = _T_275 | bypass_en; // @[axi4_to_ahb.scala 245:61]
wire [1:0] _T_278 = _T_277 & 2'h2; // @[axi4_to_ahb.scala 229:61]
wire _T_298 = _T_53 | _T_94; // @[axi4_to_ahb.scala 239:62]
wire _T_299 = buf_state_en & _T_298; // @[axi4_to_ahb.scala 239:33]
wire _T_352 = _T_275 | bypass_en; // @[axi4_to_ahb.scala 244:61]
wire [1:0] _T_354 = _T_352 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire [1:0] _T_355 = _T_354 & 2'h2; // @[axi4_to_ahb.scala 245:75]
wire _T_362 = trxn_done | bypass_en; // @[axi4_to_ahb.scala 248:40]
wire [2:0] _T_437 = bypass_en ? _T_91 : _T_229; // @[axi4_to_ahb.scala 249:30]
wire [1:0] _T_355 = _T_354 & 2'h2; // @[axi4_to_ahb.scala 244:75]
wire _T_362 = trxn_done | bypass_en; // @[axi4_to_ahb.scala 247:40]
wire [2:0] _T_437 = bypass_en ? _T_91 : _T_229; // @[axi4_to_ahb.scala 248:30]
wire _GEN_7 = _T_279 & ahb_hresp_q; // @[Conditional.scala 39:67]
wire _GEN_8 = _T_279 ? buf_state_en : _T_438; // @[Conditional.scala 39:67]
wire _GEN_10 = _T_279 & _T_299; // @[Conditional.scala 39:67]
@ -383,29 +383,29 @@ module axi4_to_ahb(
wire [2:0] buf_cmd_byte_ptr = _T_47 ? _T_93 : _GEN_90; // @[Conditional.scala 40:58]
wire slvbuf_wr_en = _T_47 ? 1'h0 : _GEN_86; // @[Conditional.scala 40:58]
wire slvbuf_error_en = _T_47 ? 1'h0 : _GEN_94; // @[Conditional.scala 40:58]
wire _T_533 = master_size[1:0] == 2'h0; // @[axi4_to_ahb.scala 266:24]
wire _T_534 = _T_101 | _T_533; // @[axi4_to_ahb.scala 265:48]
wire _T_536 = master_size[1:0] == 2'h1; // @[axi4_to_ahb.scala 266:54]
wire _T_537 = _T_534 | _T_536; // @[axi4_to_ahb.scala 266:33]
wire _T_539 = master_size[1:0] == 2'h2; // @[axi4_to_ahb.scala 266:93]
wire _T_540 = _T_537 | _T_539; // @[axi4_to_ahb.scala 266:72]
wire _T_542 = master_size[1:0] == 2'h3; // @[axi4_to_ahb.scala 267:25]
wire _T_544 = wrbuf_byteen == 8'h3; // @[axi4_to_ahb.scala 267:62]
wire _T_546 = wrbuf_byteen == 8'hc; // @[axi4_to_ahb.scala 267:97]
wire _T_547 = _T_544 | _T_546; // @[axi4_to_ahb.scala 267:74]
wire _T_549 = wrbuf_byteen == 8'h30; // @[axi4_to_ahb.scala 267:132]
wire _T_550 = _T_547 | _T_549; // @[axi4_to_ahb.scala 267:109]
wire _T_552 = wrbuf_byteen == 8'hc0; // @[axi4_to_ahb.scala 267:168]
wire _T_553 = _T_550 | _T_552; // @[axi4_to_ahb.scala 267:145]
wire _T_555 = wrbuf_byteen == 8'hf; // @[axi4_to_ahb.scala 268:28]
wire _T_556 = _T_553 | _T_555; // @[axi4_to_ahb.scala 267:181]
wire _T_558 = wrbuf_byteen == 8'hf0; // @[axi4_to_ahb.scala 268:63]
wire _T_559 = _T_556 | _T_558; // @[axi4_to_ahb.scala 268:40]
wire _T_561 = wrbuf_byteen == 8'hff; // @[axi4_to_ahb.scala 268:99]
wire _T_562 = _T_559 | _T_561; // @[axi4_to_ahb.scala 268:76]
wire _T_563 = _T_542 & _T_562; // @[axi4_to_ahb.scala 267:38]
wire buf_aligned_in = _T_540 | _T_563; // @[axi4_to_ahb.scala 266:106]
wire _T_442 = buf_aligned_in & _T_49; // @[axi4_to_ahb.scala 260:62]
wire _T_533 = master_size[1:0] == 2'h0; // @[axi4_to_ahb.scala 265:24]
wire _T_534 = _T_101 | _T_533; // @[axi4_to_ahb.scala 264:48]
wire _T_536 = master_size[1:0] == 2'h1; // @[axi4_to_ahb.scala 265:54]
wire _T_537 = _T_534 | _T_536; // @[axi4_to_ahb.scala 265:33]
wire _T_539 = master_size[1:0] == 2'h2; // @[axi4_to_ahb.scala 265:93]
wire _T_540 = _T_537 | _T_539; // @[axi4_to_ahb.scala 265:72]
wire _T_542 = master_size[1:0] == 2'h3; // @[axi4_to_ahb.scala 266:25]
wire _T_544 = wrbuf_byteen == 8'h3; // @[axi4_to_ahb.scala 266:62]
wire _T_546 = wrbuf_byteen == 8'hc; // @[axi4_to_ahb.scala 266:97]
wire _T_547 = _T_544 | _T_546; // @[axi4_to_ahb.scala 266:74]
wire _T_549 = wrbuf_byteen == 8'h30; // @[axi4_to_ahb.scala 266:132]
wire _T_550 = _T_547 | _T_549; // @[axi4_to_ahb.scala 266:109]
wire _T_552 = wrbuf_byteen == 8'hc0; // @[axi4_to_ahb.scala 266:168]
wire _T_553 = _T_550 | _T_552; // @[axi4_to_ahb.scala 266:145]
wire _T_555 = wrbuf_byteen == 8'hf; // @[axi4_to_ahb.scala 267:28]
wire _T_556 = _T_553 | _T_555; // @[axi4_to_ahb.scala 266:181]
wire _T_558 = wrbuf_byteen == 8'hf0; // @[axi4_to_ahb.scala 267:63]
wire _T_559 = _T_556 | _T_558; // @[axi4_to_ahb.scala 267:40]
wire _T_561 = wrbuf_byteen == 8'hff; // @[axi4_to_ahb.scala 267:99]
wire _T_562 = _T_559 | _T_561; // @[axi4_to_ahb.scala 267:76]
wire _T_563 = _T_542 & _T_562; // @[axi4_to_ahb.scala 266:38]
wire buf_aligned_in = _T_540 | _T_563; // @[axi4_to_ahb.scala 265:106]
wire _T_442 = buf_aligned_in & _T_49; // @[axi4_to_ahb.scala 259:62]
wire [2:0] _T_459 = _T_546 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
wire [2:0] _T_460 = 3'h2 & _T_459; // @[axi4_to_ahb.scala 128:15]
wire _T_466 = _T_558 | _T_544; // @[axi4_to_ahb.scala 129:56]
@ -415,11 +415,11 @@ module axi4_to_ahb(
wire [2:0] _T_474 = _T_552 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
wire [2:0] _T_475 = 3'h6 & _T_474; // @[axi4_to_ahb.scala 130:15]
wire [2:0] _T_476 = _T_470 | _T_475; // @[axi4_to_ahb.scala 129:96]
wire [2:0] _T_483 = _T_442 ? _T_476 : master_addr[2:0]; // @[axi4_to_ahb.scala 260:45]
wire [2:0] _T_483 = _T_442 ? _T_476 : master_addr[2:0]; // @[axi4_to_ahb.scala 259:45]
wire [31:0] buf_addr_in = {master_addr[31:3],_T_483}; // @[Cat.scala 29:58]
wire _T_487 = buf_state == 3'h3; // @[axi4_to_ahb.scala 263:33]
wire _T_493 = buf_aligned_in & _T_542; // @[axi4_to_ahb.scala 264:38]
wire _T_496 = _T_493 & _T_49; // @[axi4_to_ahb.scala 264:72]
wire _T_487 = buf_state == 3'h3; // @[axi4_to_ahb.scala 262:33]
wire _T_493 = buf_aligned_in & _T_542; // @[axi4_to_ahb.scala 263:38]
wire _T_496 = _T_493 & _T_49; // @[axi4_to_ahb.scala 263:72]
wire [1:0] _T_502 = _T_561 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire _T_508 = _T_558 | _T_555; // @[axi4_to_ahb.scala 121:55]
wire [1:0] _T_510 = _T_508 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
@ -431,65 +431,65 @@ module axi4_to_ahb(
wire [1:0] _T_525 = _T_523 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire [1:0] _T_526 = 2'h1 & _T_525; // @[axi4_to_ahb.scala 122:21]
wire [1:0] _T_527 = _T_512 | _T_526; // @[axi4_to_ahb.scala 121:93]
wire [1:0] _T_529 = _T_496 ? _T_527 : master_size[1:0]; // @[axi4_to_ahb.scala 264:21]
wire [28:0] _T_568 = bypass_en ? master_addr[31:3] : buf_addr[31:3]; // @[axi4_to_ahb.scala 270:30]
wire _T_569 = io_ahb_out_htrans == 2'h2; // @[axi4_to_ahb.scala 270:115]
wire [1:0] _T_529 = _T_496 ? _T_527 : master_size[1:0]; // @[axi4_to_ahb.scala 263:21]
wire [28:0] _T_568 = bypass_en ? master_addr[31:3] : buf_addr[31:3]; // @[axi4_to_ahb.scala 269:30]
wire _T_569 = io_ahb_out_htrans == 2'h2; // @[axi4_to_ahb.scala 269:115]
wire [2:0] _T_571 = _T_569 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
wire [2:0] _T_572 = _T_571 & buf_cmd_byte_ptr; // @[axi4_to_ahb.scala 270:124]
wire [2:0] _T_572 = _T_571 & buf_cmd_byte_ptr; // @[axi4_to_ahb.scala 269:124]
wire [1:0] _T_576 = buf_aligned_in ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire [2:0] buf_size_in = {{1'd0}, _T_529}; // @[axi4_to_ahb.scala 264:15]
wire [1:0] _T_578 = _T_576 & buf_size_in[1:0]; // @[axi4_to_ahb.scala 271:81]
wire [2:0] buf_size_in = {{1'd0}, _T_529}; // @[axi4_to_ahb.scala 263:15]
wire [1:0] _T_578 = _T_576 & buf_size_in[1:0]; // @[axi4_to_ahb.scala 270:81]
wire [2:0] _T_579 = {1'h0,_T_578}; // @[Cat.scala 29:58]
wire [1:0] _T_581 = buf_aligned ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
reg [1:0] buf_size; // @[Reg.scala 27:20]
wire [1:0] _T_583 = _T_581 & buf_size; // @[axi4_to_ahb.scala 271:138]
wire [1:0] _T_583 = _T_581 & buf_size; // @[axi4_to_ahb.scala 270:138]
wire [2:0] _T_584 = {1'h0,_T_583}; // @[Cat.scala 29:58]
wire _T_587 = ~io_axi_ar_bits_prot[2]; // @[axi4_to_ahb.scala 275:37]
wire _T_587 = ~io_axi_ar_bits_prot[2]; // @[axi4_to_ahb.scala 274:37]
wire [1:0] _T_588 = {1'h1,_T_587}; // @[Cat.scala 29:58]
reg buf_write; // @[Reg.scala 27:20]
wire _T_610 = io_ahb_out_htrans != 2'h0; // @[axi4_to_ahb.scala 284:44]
wire _T_611 = _T_610 & io_ahb_in_hready; // @[axi4_to_ahb.scala 284:56]
wire last_addr_en = _T_611 & io_ahb_out_hwrite; // @[axi4_to_ahb.scala 284:75]
wire _T_613 = io_axi_aw_valid & io_axi_aw_ready; // @[axi4_to_ahb.scala 286:31]
wire wrbuf_en = _T_613 & master_ready; // @[axi4_to_ahb.scala 286:49]
wire _T_615 = io_axi_w_valid & io_axi_w_ready; // @[axi4_to_ahb.scala 287:35]
wire wrbuf_data_en = _T_615 & master_ready; // @[axi4_to_ahb.scala 287:52]
wire wrbuf_cmd_sent = _T_147 & _T_49; // @[axi4_to_ahb.scala 288:49]
wire _T_621 = ~wrbuf_en; // @[axi4_to_ahb.scala 289:34]
wire _T_622 = wrbuf_cmd_sent & _T_621; // @[axi4_to_ahb.scala 289:32]
wire wrbuf_rst = _T_622 | dec_tlu_force_halt_bus; // @[axi4_to_ahb.scala 289:45]
wire _T_624 = ~wrbuf_cmd_sent; // @[axi4_to_ahb.scala 291:36]
wire _T_625 = wrbuf_vld & _T_624; // @[axi4_to_ahb.scala 291:34]
wire _T_626 = ~_T_625; // @[axi4_to_ahb.scala 291:22]
wire _T_629 = wrbuf_data_vld & _T_624; // @[axi4_to_ahb.scala 292:38]
wire _T_630 = ~_T_629; // @[axi4_to_ahb.scala 292:21]
wire _T_633 = ~wr_cmd_vld; // @[axi4_to_ahb.scala 293:22]
wire _T_610 = io_ahb_out_htrans != 2'h0; // @[axi4_to_ahb.scala 283:44]
wire _T_611 = _T_610 & io_ahb_in_hready; // @[axi4_to_ahb.scala 283:56]
wire last_addr_en = _T_611 & io_ahb_out_hwrite; // @[axi4_to_ahb.scala 283:75]
wire _T_613 = io_axi_aw_valid & io_axi_aw_ready; // @[axi4_to_ahb.scala 285:31]
wire wrbuf_en = _T_613 & master_ready; // @[axi4_to_ahb.scala 285:49]
wire _T_615 = io_axi_w_valid & io_axi_w_ready; // @[axi4_to_ahb.scala 286:35]
wire wrbuf_data_en = _T_615 & master_ready; // @[axi4_to_ahb.scala 286:52]
wire wrbuf_cmd_sent = _T_147 & _T_49; // @[axi4_to_ahb.scala 287:49]
wire _T_621 = ~wrbuf_en; // @[axi4_to_ahb.scala 288:34]
wire _T_622 = wrbuf_cmd_sent & _T_621; // @[axi4_to_ahb.scala 288:32]
wire wrbuf_rst = _T_622 | dec_tlu_force_halt_bus; // @[axi4_to_ahb.scala 288:45]
wire _T_624 = ~wrbuf_cmd_sent; // @[axi4_to_ahb.scala 290:36]
wire _T_625 = wrbuf_vld & _T_624; // @[axi4_to_ahb.scala 290:34]
wire _T_626 = ~_T_625; // @[axi4_to_ahb.scala 290:22]
wire _T_629 = wrbuf_data_vld & _T_624; // @[axi4_to_ahb.scala 291:38]
wire _T_630 = ~_T_629; // @[axi4_to_ahb.scala 291:21]
wire _T_633 = ~wr_cmd_vld; // @[axi4_to_ahb.scala 292:22]
wire _T_637 = ~wrbuf_rst; // @[lib.scala 391:75]
wire _T_639 = wrbuf_en | wrbuf_rst; // @[lib.scala 391:95]
wire _T_640 = _T_639 & io_bus_clk_en; // @[lib.scala 391:102]
wire _T_647 = wrbuf_data_en | wrbuf_rst; // @[lib.scala 391:95]
wire _T_648 = _T_647 & io_bus_clk_en; // @[lib.scala 391:102]
wire _T_653 = io_bus_clk_en & wrbuf_en; // @[lib.scala 383:57]
wire _T_660 = wrbuf_en & io_bus_clk_en; // @[axi4_to_ahb.scala 300:61]
wire _T_663 = wrbuf_data_en & io_bus_clk_en; // @[axi4_to_ahb.scala 301:65]
wire _T_660 = wrbuf_en & io_bus_clk_en; // @[axi4_to_ahb.scala 299:61]
wire _T_663 = wrbuf_data_en & io_bus_clk_en; // @[axi4_to_ahb.scala 300:65]
wire _T_667 = io_bus_clk_en & wrbuf_data_en; // @[lib.scala 383:57]
wire _T_671 = io_bus_clk_en & last_addr_en; // @[lib.scala 383:57]
wire _T_728 = buf_wr_en | slvbuf_wr_en; // @[axi4_to_ahb.scala 321:43]
wire _T_729 = _T_728 | io_clk_override; // @[axi4_to_ahb.scala 321:58]
wire buf_clken = io_bus_clk_en & _T_729; // @[axi4_to_ahb.scala 321:30]
wire _T_728 = buf_wr_en | slvbuf_wr_en; // @[axi4_to_ahb.scala 320:51]
wire _T_729 = _T_728 | io_clk_override; // @[axi4_to_ahb.scala 320:66]
wire buf_clken = io_bus_clk_en & _T_729; // @[axi4_to_ahb.scala 320:38]
wire _T_674 = buf_clken & buf_wr_en; // @[lib.scala 383:57]
reg buf_tag; // @[Reg.scala 27:20]
wire _T_681 = buf_wr_en & io_bus_clk_en; // @[axi4_to_ahb.scala 306:53]
wire _T_696 = buf_data_wr_en & io_bus_clk_en; // @[axi4_to_ahb.scala 310:58]
wire _T_681 = buf_wr_en & io_bus_clk_en; // @[axi4_to_ahb.scala 305:62]
wire _T_696 = buf_data_wr_en & io_bus_clk_en; // @[axi4_to_ahb.scala 309:67]
wire _T_700 = buf_clken & slvbuf_wr_en; // @[lib.scala 383:57]
wire _T_707 = buf_clken & slvbuf_error_en; // @[lib.scala 383:57]
wire _T_707 = io_bus_clk_en & slvbuf_error_en; // @[lib.scala 383:57]
wire _T_711 = ~slave_valid_pre; // @[lib.scala 391:75]
wire _T_713 = cmd_done | slave_valid_pre; // @[lib.scala 391:95]
wire _T_714 = _T_713 & io_bus_clk_en; // @[lib.scala 391:102]
wire _T_719 = io_bus_clk_en & buf_cmd_byte_ptr_en; // @[lib.scala 383:57]
wire _T_731 = buf_state != 3'h0; // @[axi4_to_ahb.scala 322:50]
wire _T_732 = _T_731 | io_clk_override; // @[axi4_to_ahb.scala 322:60]
wire ahbm_data_clken = io_bus_clk_en & _T_732; // @[axi4_to_ahb.scala 322:36]
wire _T_731 = buf_state != 3'h0; // @[axi4_to_ahb.scala 321:52]
wire _T_732 = _T_731 | io_clk_override; // @[axi4_to_ahb.scala 321:62]
wire ahbm_data_clken = io_bus_clk_en & _T_732; // @[axi4_to_ahb.scala 321:38]
rvclkhdr rvclkhdr ( // @[lib.scala 399:23]
.io_clk(rvclkhdr_io_clk),
.io_en(rvclkhdr_io_en)
@ -506,25 +506,25 @@ module axi4_to_ahb(
.io_clk(rvclkhdr_3_io_clk),
.io_en(rvclkhdr_3_io_en)
);
assign io_axi_aw_ready = _T_626 & master_ready; // @[axi4_to_ahb.scala 291:19]
assign io_axi_w_ready = _T_630 & master_ready; // @[axi4_to_ahb.scala 292:18]
assign io_axi_aw_ready = _T_626 & master_ready; // @[axi4_to_ahb.scala 290:19]
assign io_axi_w_ready = _T_630 & master_ready; // @[axi4_to_ahb.scala 291:18]
assign io_axi_b_valid = _T_28 & slave_opc[3]; // @[axi4_to_ahb.scala 150:18]
assign io_axi_b_bits_resp = slave_opc[0] ? 2'h2 : _T_33; // @[axi4_to_ahb.scala 151:22]
assign io_axi_b_bits_id = slvbuf_tag; // @[axi4_to_ahb.scala 152:20]
assign io_axi_ar_ready = _T_633 & master_ready; // @[axi4_to_ahb.scala 293:19]
assign io_axi_ar_ready = _T_633 & master_ready; // @[axi4_to_ahb.scala 292:19]
assign io_axi_r_valid = _T_28 & _T_38; // @[axi4_to_ahb.scala 154:18]
assign io_axi_r_bits_id = slvbuf_tag; // @[axi4_to_ahb.scala 156:20]
assign io_axi_r_bits_data = slvbuf_error ? _T_602 : _T_606; // @[axi4_to_ahb.scala 157:22]
assign io_axi_r_bits_resp = slave_opc[0] ? 2'h2 : _T_33; // @[axi4_to_ahb.scala 155:22]
assign io_axi_r_bits_last = 1'h1; // @[axi4_to_ahb.scala 294:22]
assign io_ahb_out_haddr = {_T_568,_T_572}; // @[axi4_to_ahb.scala 270:20]
assign io_ahb_out_hburst = 3'h0; // @[axi4_to_ahb.scala 273:21]
assign io_ahb_out_hmastlock = 1'h0; // @[axi4_to_ahb.scala 274:24]
assign io_ahb_out_hprot = {{2'd0}, _T_588}; // @[axi4_to_ahb.scala 275:20]
assign io_ahb_out_hsize = bypass_en ? _T_579 : _T_584; // @[axi4_to_ahb.scala 271:20]
assign io_ahb_out_htrans = _T_47 ? _T_98 : _GEN_91; // @[axi4_to_ahb.scala 29:21 axi4_to_ahb.scala 173:25 axi4_to_ahb.scala 185:25 axi4_to_ahb.scala 200:25 axi4_to_ahb.scala 210:25 axi4_to_ahb.scala 230:25 axi4_to_ahb.scala 245:25]
assign io_ahb_out_hwrite = bypass_en ? _T_49 : buf_write; // @[axi4_to_ahb.scala 276:21]
assign io_ahb_out_hwdata = buf_data; // @[axi4_to_ahb.scala 277:21]
assign io_axi_r_bits_last = 1'h1; // @[axi4_to_ahb.scala 293:22]
assign io_ahb_out_haddr = {_T_568,_T_572}; // @[axi4_to_ahb.scala 269:20]
assign io_ahb_out_hburst = 3'h0; // @[axi4_to_ahb.scala 272:21]
assign io_ahb_out_hmastlock = 1'h0; // @[axi4_to_ahb.scala 273:24]
assign io_ahb_out_hprot = {{2'd0}, _T_588}; // @[axi4_to_ahb.scala 274:20]
assign io_ahb_out_hsize = bypass_en ? _T_579 : _T_584; // @[axi4_to_ahb.scala 270:20]
assign io_ahb_out_htrans = _T_47 ? _T_98 : _GEN_91; // @[axi4_to_ahb.scala 29:21 axi4_to_ahb.scala 172:25 axi4_to_ahb.scala 184:25 axi4_to_ahb.scala 199:25 axi4_to_ahb.scala 209:25 axi4_to_ahb.scala 229:25 axi4_to_ahb.scala 244:25]
assign io_ahb_out_hwrite = bypass_en ? _T_49 : buf_write; // @[axi4_to_ahb.scala 275:21]
assign io_ahb_out_hwdata = buf_data; // @[axi4_to_ahb.scala 276:21]
assign rvclkhdr_io_clk = clock; // @[lib.scala 401:18]
assign rvclkhdr_io_en = wrbuf_en & io_bus_clk_en; // @[lib.scala 402:17]
assign rvclkhdr_1_io_clk = clock; // @[lib.scala 401:18]

1
src/main/scala/lib/ahb_to_axi4.scala
View File

@ -111,7 +111,6 @@ class ahb_to_axi4(TAG : Int) extends Module with lib with RequireAsyncReset {
((ahb_hsize_q(2,0) === 3.U) & (ahb_haddr_q(2,0)).orR))) | // DW size but unaligned
buf_read_error | // Read ECC error
(ahb_hresp_q & !ahb_hready_q)
// Buffer signals - needed for the read data and ECC error response
buf_rdata := rvdff_fpga(io.axi.r.bits.data,buf_rdata_clk,buf_rdata_clk_en,clock)
buf_read_error := rvdff_fpga(buf_read_error_in,bus_clk,io.bus_clk_en,clock)

6
src/main/scala/lib/axi4_to_ahb.scala
View File

@ -166,7 +166,6 @@ class axi4_to_ahb(val TAG : Int = 3) extends Module with lib with RequireAsyncRe
buf_wr_en := buf_state_en
buf_data_wr_en := buf_state_en & (buf_nxtstate === cmd_wr)
buf_cmd_byte_ptr_en := buf_state_en
// ---------------------FROM FUNCTION CHECK LATER
buf_cmd_byte_ptr := Mux(buf_write_in.asBool(), (get_nxtbyte_ptr(0.U(3.W), buf_byteen_in(7, 0), false.B)), master_addr(2, 0))
bypass_en := buf_state_en
rd_bypass_idle := bypass_en & (buf_nxtstate === cmd_rd)
@ -304,13 +303,13 @@ class axi4_to_ahb(val TAG : Int = 3) extends Module with lib with RequireAsyncRe
buf_write := rvdffs_fpga(buf_write_in, buf_wr_en.asBool(), buf_clk, buf_clken, clock)
buf_tag := rvdffs_fpga(buf_tag_in(TAG - 1, 0), buf_wr_en.asBool(), buf_clk, buf_clken, clock)
buf_addr := rvdffe(buf_addr_in(31, 0), (buf_wr_en & io.bus_clk_en).asBool, clock, io.scan_mode)
buf_size := rvdffs_fpga(buf_size_in(1, 0), buf_wr_en.asBool(), buf_clk, buf_clken, clock)
buf_size := rvdffs_fpga(buf_size_in(1,0), buf_wr_en.asBool(), buf_clk, buf_clken, clock)
buf_aligned := rvdffs_fpga(buf_aligned_in, buf_wr_en.asBool(), buf_clk, buf_clken, clock)
buf_byteen := rvdffs_fpga(buf_byteen_in(7, 0), buf_wr_en.asBool(), buf_clk, buf_clken, clock)
buf_data := rvdffe(buf_data_in(63, 0), (buf_data_wr_en & io.bus_clk_en).asBool(), clock, io.scan_mode)
slvbuf_write := rvdffs_fpga(buf_write, slvbuf_wr_en.asBool(), buf_clk, buf_clken, clock)
slvbuf_tag := rvdffs_fpga(buf_tag(TAG - 1, 0), slvbuf_wr_en.asBool(), buf_clk, buf_clken, clock)
slvbuf_error := rvdffs_fpga(slvbuf_error_in, slvbuf_error_en.asBool(), buf_clk, buf_clken, clock)
slvbuf_error := rvdffs_fpga(slvbuf_error_in, slvbuf_error_en.asBool(), bus_clk, io.bus_clk_en, clock)
cmd_doneQ := rvdffsc_fpga(1.U, cmd_done.asBool(), cmd_done_rst, bus_clk, io.bus_clk_en, clock)
buf_cmd_byte_ptrQ := rvdffs_fpga(buf_cmd_byte_ptr(2, 0), buf_cmd_byte_ptr_en.asBool(), bus_clk, io.bus_clk_en, clock)
ahb_hready_q := rvdff_fpga(io.ahb.in.hready, bus_clk, io.bus_clk_en, clock)
@ -320,7 +319,6 @@ class axi4_to_ahb(val TAG : Int = 3) extends Module with lib with RequireAsyncRe
ahb_hrdata_q := rvdff_fpga(io.ahb.in.hrdata(63, 0), ahbm_data_clk, ahbm_data_clken, clock)
buf_clken := io.bus_clk_en & (buf_wr_en | slvbuf_wr_en | io.clk_override)
ahbm_data_clken := io.bus_clk_en & ((buf_state =/= idle) | io.clk_override)
if (RV_FPGA_OPTIMIZE) {
bus_clk := 0.B.asClock()
buf_clk := 0.B.asClock()

BIN
target/scala-2.12/classes/lib/ahb_to_axi4$.class
View File

Binary file not shown.

BIN
target/scala-2.12/classes/lib/ahb_to_axi4$delayedInit$body.class
View File

Binary file not shown.

BIN
target/scala-2.12/classes/lib/ahb_to_axi4.class
View File

Binary file not shown.

BIN
target/scala-2.12/classes/lib/axi4_to_ahb$.class
View File

Binary file not shown.

BIN
target/scala-2.12/classes/lib/axi4_to_ahb$delayedInit$body.class
View File

Binary file not shown.

BIN
target/scala-2.12/classes/lib/axi4_to_ahb.class
View File

Binary file not shown.