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rvdffsc corrected

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​Laraib Khan 2021-01-14 12:36:40 +05:00
parent 43402819b0
commit 43cddfd8b7
4 changed files with 1329 additions and 1327 deletions
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1820
axi4_to_ahb.fir
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836
axi4_to_ahb.v
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2
src/main/scala/lib/lib.scala
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@ -388,7 +388,7 @@ trait lib extends param{
def apply(din: UInt, en:Bool,clear: UInt, clk: Clock, clken: Bool,rawclk:Clock):UInt = { def apply(din: UInt, en:Bool,clear: UInt, clk: Clock, clken: Bool,rawclk:Clock):UInt = {
val dout =Wire(UInt()) val dout =Wire(UInt())
if (RV_FPGA_OPTIMIZE) if (RV_FPGA_OPTIMIZE)
dout := withClock (rawclk) {RegEnable ((din & Fill(clear.getWidth,!clear)) , 0.U, ((en|clear)& clken))} dout := withClock (rawclk) {RegEnable ((din & Fill(din.getWidth,!clear)), 0.U, ((en|clear)& clken))}
else dout := withClock(clk) {RegNext (Mux(en,din,dout) & !clear, 0.U)} else dout := withClock(clk) {RegNext (Mux(en,din,dout) & !clear, 0.U)}
dout dout
} }

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target/scala-2.12/classes/lib/lib$rvdffsc_fpga$.class
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