rvdffsc corrected

2021-01-14 12:36:40 +05:00 · 2021-01-14 12:36:40 +05:00 · 43cddfd8b7
parent 43402819b0
commit 43cddfd8b7
4 changed files with 1329 additions and 1327 deletions
--- a/axi4_to_ahb.fir
+++ b/axi4_to_ahb.fir
--- a/axi4_to_ahb.v
+++ b/axi4_to_ahb.v
--- a/src/main/scala/lib/lib.scala
+++ b/src/main/scala/lib/lib.scala
@ -388,7 +388,7 @@ trait lib extends param{
    def apply(din: UInt, en:Bool,clear: UInt, clk: Clock, clken: Bool,rawclk:Clock):UInt = {
      val dout =Wire(UInt())
      if (RV_FPGA_OPTIMIZE)
-        dout := withClock (rawclk) {RegEnable ((din & Fill(clear.getWidth,!clear)) , 0.U, ((en|clear)& clken))}
+        dout := withClock (rawclk) {RegEnable ((din & Fill(din.getWidth,!clear)), 0.U, ((en|clear)& clken))}
      else dout := withClock(clk) {RegNext (Mux(en,din,dout) & !clear, 0.U)}
      dout
    }
--- a/target/scala-2.12/classes/lib/lib$rvdffsc_fpga$.class
+++ b/target/scala-2.12/classes/lib/lib$rvdffsc_fpga$.class