Delete wb_mem_wrapper.v
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// SPDX-License-Identifier: Apache-2.0
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// Copyright 2019 Western Digital Corporation or its affiliates.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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//********************************************************************************
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// $Id$
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//
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// Function: Wrapper for on-chip memory instantiations
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// Comments:
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//
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//********************************************************************************
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`default_nettype none
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module wb_mem_wrapper
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  #(parameter MEM_SIZE = 0,
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    parameter mem_clear = 0,
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    parameter INIT_FILE = "")
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  (
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   input wire 			     i_clk,
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   input wire 			     i_rst,
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   input wire [$clog2(MEM_SIZE)-1:2] i_wb_adr,
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   input wire [31:0] 		     i_wb_dat,
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   input wire [3:0] 		     i_wb_sel,
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   input wire 			     i_wb_we ,
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   input wire 			     i_wb_cyc,
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   input wire 			     i_wb_stb,
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   output reg 			     o_wb_ack,
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   output wire [31:0] 		     o_wb_rdt);
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   wire [31:0] 	 mem_addr;
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   wire [63:0] 	 mem_wdata;
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   wire [63:0] 	 mem_rdata;
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   wire [7:0] 	 mem_we;
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   assign mem_we[3:0] = (i_wb_cyc & i_wb_stb & i_wb_we & !i_wb_adr[2]) ? i_wb_sel : 4'd0;
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   assign mem_we[7:4] = (i_wb_cyc & i_wb_stb & i_wb_we &  i_wb_adr[2]) ? i_wb_sel : 4'd0;
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   assign mem_wdata = {i_wb_dat, i_wb_dat};
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   assign o_wb_rdt = i_wb_adr[2] ? mem_rdata[63:32] : mem_rdata[31:0];
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   always @(posedge i_clk) begin
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      o_wb_ack <= i_wb_cyc & i_wb_stb & !o_wb_ack;
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      if (i_rst)
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	o_wb_ack <= 1'b0;
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   end
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   dpram64
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     #(.SIZE (MEM_SIZE),
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       .mem_clear (mem_clear),
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       .memfile (INIT_FILE))
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   ram
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     (.clk   (i_clk),
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      .we    (mem_we),
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      .din   (mem_wdata),
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      .waddr ({i_wb_adr[$clog2(MEM_SIZE)-1:3],3'b000}),
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      .raddr ({i_wb_adr[$clog2(MEM_SIZE)-1:3],3'b000}),
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      .dout  (mem_rdata));
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endmodule
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