Daily update

EL2_IC_TAG.anno.json

@@ -0,0 +1,26 @@
+[
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~EL2_IC_TAG|EL2_IC_TAG>io_test",
+    "sources":[
+      "~EL2_IC_TAG|EL2_IC_TAG>io_ic_wr_en",
+      "~EL2_IC_TAG|EL2_IC_TAG>io_ic_rw_addr"
+    ]
+  },
+  {
+    "class":"firrtl.EmitCircuitAnnotation",
+    "emitter":"firrtl.VerilogEmitter"
+  },
+  {
+    "class":"firrtl.options.TargetDirAnnotation",
+    "directory":"."
+  },
+  {
+    "class":"firrtl.options.OutputAnnotationFileAnnotation",
+    "file":"EL2_IC_TAG"
+  },
+  {
+    "class":"firrtl.transforms.BlackBoxTargetDirAnno",
+    "targetDir":"."
+  }
+]

EL2_IC_TAG.fir

@@ -0,0 +1,21 @@
+;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
+circuit EL2_IC_TAG : 
+  module EL2_IC_TAG : 
+    input clock : Clock
+    input reset : UInt<1>
+    output io : {flip clk : UInt<1>, flip rst_l : UInt<1>, flip clk_override : UInt<1>, flip dec_tlu_core_ecc_disable : UInt<1>, flip ic_rw_addr : UInt<29>, flip ic_wr_en : UInt<2>, flip ic_tag_valid : UInt<2>, flip ic_rd_en : UInt<1>, flip ic_debug_addr : UInt<9>, flip ic_debug_rd_en : UInt<1>, flip ic_debug_wr_en : UInt<1>, flip ic_debug_tag_array : UInt<1>, flip ic_debug_way : UInt<2>, ictag_debug_rd_data : UInt<26>, flip ic_debug_wr_data : UInt<71>, ic_rd_hit : UInt<2>, ic_tag_perr : UInt<1>, flip scan_mode : UInt<1>, test : UInt}
+    
+    node _T = bits(io.ic_rw_addr, 5, 4) @[el2_ifu_ic_mem.scala 68:69]
+    wire _T_1 : UInt<1>[1] @[el2_lib.scala 39:24]
+    _T_1[0] <= UInt<1>("h01") @[el2_lib.scala 39:24]
+    node _T_2 = eq(_T, _T_1[0]) @[el2_ifu_ic_mem.scala 68:92]
+    wire _T_3 : UInt<1>[2] @[el2_lib.scala 39:24]
+    _T_3[0] <= _T_2 @[el2_lib.scala 39:24]
+    _T_3[1] <= _T_2 @[el2_lib.scala 39:24]
+    node _T_4 = cat(_T_3[0], _T_3[1]) @[Cat.scala 29:58]
+    node ic_tag_wren = and(io.ic_wr_en, _T_4) @[el2_ifu_ic_mem.scala 68:32]
+    io.test <= ic_tag_wren @[el2_ifu_ic_mem.scala 72:10]
+    io.ic_tag_perr <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 73:18]
+    io.ic_rd_hit <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 74:16]
+    io.ictag_debug_rd_data <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 75:26]
+    

EL2_IC_TAG.v

@@ -0,0 +1,30 @@
+module EL2_IC_TAG(
+  input         clock,
+  input         reset,
+  input         io_clk,
+  input         io_rst_l,
+  input         io_clk_override,
+  input         io_dec_tlu_core_ecc_disable,
+  input  [28:0] io_ic_rw_addr,
+  input  [1:0]  io_ic_wr_en,
+  input  [1:0]  io_ic_tag_valid,
+  input         io_ic_rd_en,
+  input  [8:0]  io_ic_debug_addr,
+  input         io_ic_debug_rd_en,
+  input         io_ic_debug_wr_en,
+  input         io_ic_debug_tag_array,
+  input  [1:0]  io_ic_debug_way,
+  output [25:0] io_ictag_debug_rd_data,
+  input  [70:0] io_ic_debug_wr_data,
+  output [1:0]  io_ic_rd_hit,
+  output        io_ic_tag_perr,
+  input         io_scan_mode,
+  output [1:0]  io_test
+);
+  wire  _T_2 = io_ic_rw_addr[5:4] == 2'h1; // @[el2_ifu_ic_mem.scala 68:92]
+  wire [1:0] _T_4 = {_T_2,_T_2}; // @[Cat.scala 29:58]
+  assign io_ictag_debug_rd_data = 26'h0; // @[el2_ifu_ic_mem.scala 75:26]
+  assign io_ic_rd_hit = 2'h0; // @[el2_ifu_ic_mem.scala 74:16]
+  assign io_ic_tag_perr = 1'h0; // @[el2_ifu_ic_mem.scala 73:18]
+  assign io_test = io_ic_wr_en & _T_4; // @[el2_ifu_ic_mem.scala 72:10]
+endmodule

el2_ifu_bp_ctl.fir

@@ -5,8 +5,8 @@ circuit el2_ifu_bp_ctl :
     input reset : UInt<1>
     output io : {flip in : UInt<32>, flip in2 : UInt<32>, out : UInt}
     
-    node _T = bits(io.in, 9, 2) @[el2_lib.scala 32:16]
+    node _T = bits(io.in, 9, 2) @[el2_lib.scala 35:30]
-    node _T_1 = bits(io.in2, 7, 0) @[el2_lib.scala 32:40]
+    node _T_1 = bits(io.in2, 7, 0) @[el2_lib.scala 35:53]
-    node _T_2 = xor(_T, _T_1) @[el2_lib.scala 32:35]
+    node _T_2 = xor(_T, _T_1) @[el2_lib.scala 35:48]
     io.out <= _T_2 @[el2_ifu_bp_ctl.scala 13:10]
     

el2_ifu_ic_mem.anno.json

@@ -0,0 +1,18 @@
+[
+  {
+    "class":"firrtl.EmitCircuitAnnotation",
+    "emitter":"firrtl.VerilogEmitter"
+  },
+  {
+    "class":"firrtl.options.TargetDirAnnotation",
+    "directory":"."
+  },
+  {
+    "class":"firrtl.options.OutputAnnotationFileAnnotation",
+    "file":"el2_ifu_ic_mem"
+  },
+  {
+    "class":"firrtl.transforms.BlackBoxTargetDirAnno",
+    "targetDir":"."
+  }
+]

el2_ifu_ic_mem.fir

@@ -0,0 +1,15 @@
+;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
+circuit el2_ifu_ic_mem : 
+  module el2_ifu_ic_mem : 
+    input clock : Clock
+    input reset : UInt<1>
+    output io : {flip clk : UInt<1>, flip rst_l : UInt<1>, flip clk_override : UInt<1>, flip dec_tlu_core_ecc_disable : UInt<1>, flip ic_rw_addr : UInt<31>, flip ic_wr_en : UInt<2>, flip ic_rd_en : UInt<1>, flip ic_debug_addr : UInt<9>, flip ic_debug_rd_en : UInt<1>, flip ic_debug_wr_en : UInt<1>, flip ic_debug_tag_array : UInt<1>, flip ic_debug_way : UInt<2>, flip ic_premux_data : UInt<64>, flip ic_sel_premux_data : UInt<1>, flip ic_wr_data : UInt<71>[2], ic_rd_data : UInt<64>, ic_debug_rd_data : UInt<71>, ictag_debug_rd_data : UInt<26>, flip ic_debug_wr_data : UInt<71>, ic_eccerr : UInt<2>, ic_parerr : UInt<2>, flip ic_tag_valid : UInt<2>, ic_rd_hit : UInt<2>, ic_tag_perr : UInt<1>, flip scan_mode : UInt<1>}
+    
+    io.ic_tag_perr <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 34:18]
+    io.ic_rd_hit <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 35:16]
+    io.ic_parerr <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 36:16]
+    io.ic_eccerr <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 37:16]
+    io.ictag_debug_rd_data <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 38:26]
+    io.ic_debug_rd_data <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 39:23]
+    io.ic_rd_data <= UInt<1>("h00") @[el2_ifu_ic_mem.scala 40:17]
+    

el2_ifu_ic_mem.v

@@ -0,0 +1,38 @@
+module el2_ifu_ic_mem(
+  input         clock,
+  input         reset,
+  input         io_clk,
+  input         io_rst_l,
+  input         io_clk_override,
+  input         io_dec_tlu_core_ecc_disable,
+  input  [30:0] io_ic_rw_addr,
+  input  [1:0]  io_ic_wr_en,
+  input         io_ic_rd_en,
+  input  [8:0]  io_ic_debug_addr,
+  input         io_ic_debug_rd_en,
+  input         io_ic_debug_wr_en,
+  input         io_ic_debug_tag_array,
+  input  [1:0]  io_ic_debug_way,
+  input  [63:0] io_ic_premux_data,
+  input         io_ic_sel_premux_data,
+  input  [70:0] io_ic_wr_data_0,
+  input  [70:0] io_ic_wr_data_1,
+  output [63:0] io_ic_rd_data,
+  output [70:0] io_ic_debug_rd_data,
+  output [25:0] io_ictag_debug_rd_data,
+  input  [70:0] io_ic_debug_wr_data,
+  output [1:0]  io_ic_eccerr,
+  output [1:0]  io_ic_parerr,
+  input  [1:0]  io_ic_tag_valid,
+  output [1:0]  io_ic_rd_hit,
+  output        io_ic_tag_perr,
+  input         io_scan_mode
+);
+  assign io_ic_rd_data = 64'h0; // @[el2_ifu_ic_mem.scala 40:17]
+  assign io_ic_debug_rd_data = 71'h0; // @[el2_ifu_ic_mem.scala 39:23]
+  assign io_ictag_debug_rd_data = 26'h0; // @[el2_ifu_ic_mem.scala 38:26]
+  assign io_ic_eccerr = 2'h0; // @[el2_ifu_ic_mem.scala 37:16]
+  assign io_ic_parerr = 2'h0; // @[el2_ifu_ic_mem.scala 36:16]
+  assign io_ic_rd_hit = 2'h0; // @[el2_ifu_ic_mem.scala 35:16]
+  assign io_ic_tag_perr = 1'h0; // @[el2_ifu_ic_mem.scala 34:18]
+endmodule

project/target/config-classes/$f7cc14b2623d339d7fbd.cache

@@ -0,0 +1 @@
+sbt.internal.DslEntry

project/target/scala-2.12/sbt-1.0/update/update_cache_2.12/inputs

@@ -1 +1 @@
-884984604
+338581136

project/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/input_dsp

@@ -1 +1 @@
--1413115869
+23355001

project/target/streams/_global/dependencyPositions/_global/streams/update_cache_2.12/output_dsp

@@ -1 +1 @@
-{"{\"organization\":\"org.scala-lang\",\"name\":\"scala-library\",\"revision\":\"2.12.10\",\"configurations\":\"provided\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","startLine"],"path":"(sbt.Classpaths.jvmBaseSettings) Defaults.scala","startLine":2531},"type":"LinePosition"}}
+{"{\"organization\":\"org.scala-lang\",\"name\":\"scala-library\",\"revision\":\"2.12.10\",\"configurations\":\"provided\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","startLine"],"path":"(sbt.Classpaths.jvmBaseSettings) Defaults.scala","startLine":2531},"type":"LinePosition"},"{\"organization\":\"org.jetbrains\",\"name\":\"sbt-structure-extractor\",\"revision\":\"2018.2.1+4-88400d3f\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{\"e:sbtVersion\":\"1.0\",\"e:scalaVersion\":\"2.12\"},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/tmp/idea.sbt","range":{"$fields":["start","end"],"start":4,"end":10}},"type":"RangePosition"},"{\"organization\":\"org.jetbrains\",\"name\":\"sbt-idea-shell\",\"revision\":\"2018.3\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{\"e:sbtVersion\":\"1.0\",\"e:scalaVersion\":\"2.12\"},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/tmp/idea.sbt","range":{"$fields":["start","end"],"start":4,"end":10}},"type":"RangePosition"},"{\"organization\":\"org.jetbrains\",\"name\":\"sbt-idea-compiler-indices\",\"revision\":\"0.1.3\",\"isChanging\":false,\"isTransitive\":true,\"isForce\":false,\"explicitArtifacts\":[],\"inclusions\":[],\"exclusions\":[],\"extraAttributes\":{\"e:sbtVersion\":\"1.0\",\"e:scalaVersion\":\"2.12\"},\"crossVersion\":{\"type\":\"Disabled\"}}":{"value":{"$fields":["path","range"],"path":"/tmp/idea.sbt","range":{"$fields":["start","end"],"start":4,"end":10}},"type":"RangePosition"}}

project/target/streams/_global/update/_global/streams/out

@@ -1,3 +1,3 @@
-[debug] "not up to date. inChanged = true, force = false
+[debug] "not up to date. inChanged = true, force = false
-[debug] Updating ProjectRef(uri("file:/home/waleedbinehsan/Desktop/SweRV-Chislified-master/project/"), "swerv-chislified-master-build")...
+[debug] Updating ProjectRef(uri("file:/home/waleedbinehsan/Desktop/SweRV-Chislified-master/project/"), "swerv-chislified-master-build")...
-[debug] Done updating ProjectRef(uri("file:/home/waleedbinehsan/Desktop/SweRV-Chislified-master/project/"), "swerv-chislified-master-build")
+[debug] Done updating ProjectRef(uri("file:/home/waleedbinehsan/Desktop/SweRV-Chislified-master/project/"), "swerv-chislified-master-build")

project/target/streams/compile/compileIncremental/_global/streams/out

@@ -1 +1 @@
-[debug] Full compilation, no sources in previous analysis.
+[debug] Full compilation, no sources in previous analysis.

project/target/streams/compile/copyResources/_global/streams/out

@@ -1,2 +1,2 @@
-[debug] Copy resource mappings: 
+[debug] Copy resource mappings: 
-[debug] 	
+[debug] 	

project/target/streams/runtime/dependencyClasspath/_global/streams/export

@@ -1 +1 @@
-/home/waleedbinehsan/Desktop/SweRV-Chislified-master/project/target/scala-2.12/sbt-1.0/classes:/home/waleedbinehsan/.sbt/1.0/plugins/target/scala-2.12/sbt-1.0/classes
+/home/waleedbinehsan/Desktop/SweRV-Chislified-master/project/target/scala-2.12/sbt-1.0/classes:/home/waleedbinehsan/.sbt/1.0/plugins/target/scala-2.12/sbt-1.0/classes:/home/waleedbinehsan/idea-IE-201.7846.105/plugins/Scala/repo/org.jetbrains/sbt-structure-extractor/scala_2.12/sbt_1.0/2018.2.1+4-88400d3f/jars/sbt-structure-extractor.jar:/home/waleedbinehsan/idea-IE-201.7846.105/plugins/Scala/repo/org.jetbrains/sbt-idea-shell/scala_2.12/sbt_1.0/2018.3/jars/sbt-idea-shell.jar:/home/waleedbinehsan/idea-IE-201.7846.105/plugins/Scala/repo/org.jetbrains/sbt-idea-compiler-indices/scala_2.12/sbt_1.0/0.1.3/jars/sbt-idea-compiler-indices.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/sugakandrey/scala-compiler-indices-protocol_2.12/0.1.1/scala-compiler-indices-protocol_2.12-0.1.1.jar:/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-library.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/io/spray/spray-json_2.12/1.3.4/spray-json_2.12-1.3.4.jar

project/target/streams/runtime/externalDependencyClasspath/_global/streams/export

@@ -1 +1 @@
-
+/home/waleedbinehsan/idea-IE-201.7846.105/plugins/Scala/repo/org.jetbrains/sbt-structure-extractor/scala_2.12/sbt_1.0/2018.2.1+4-88400d3f/jars/sbt-structure-extractor.jar:/home/waleedbinehsan/idea-IE-201.7846.105/plugins/Scala/repo/org.jetbrains/sbt-idea-shell/scala_2.12/sbt_1.0/2018.3/jars/sbt-idea-shell.jar:/home/waleedbinehsan/idea-IE-201.7846.105/plugins/Scala/repo/org.jetbrains/sbt-idea-compiler-indices/scala_2.12/sbt_1.0/0.1.3/jars/sbt-idea-compiler-indices.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/sugakandrey/scala-compiler-indices-protocol_2.12/0.1.1/scala-compiler-indices-protocol_2.12-0.1.1.jar:/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-library.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/io/spray/spray-json_2.12/1.3.4/spray-json_2.12-1.3.4.jar

project/target/streams/runtime/fullClasspath/_global/streams/export

@@ -1 +1 @@
-/home/waleedbinehsan/Desktop/SweRV-Chislified-master/project/target/scala-2.12/sbt-1.0/classes:/home/waleedbinehsan/.sbt/1.0/plugins/target/scala-2.12/sbt-1.0/classes
+/home/waleedbinehsan/Desktop/SweRV-Chislified-master/project/target/scala-2.12/sbt-1.0/classes:/home/waleedbinehsan/.sbt/1.0/plugins/target/scala-2.12/sbt-1.0/classes:/home/waleedbinehsan/idea-IE-201.7846.105/plugins/Scala/repo/org.jetbrains/sbt-structure-extractor/scala_2.12/sbt_1.0/2018.2.1+4-88400d3f/jars/sbt-structure-extractor.jar:/home/waleedbinehsan/idea-IE-201.7846.105/plugins/Scala/repo/org.jetbrains/sbt-idea-shell/scala_2.12/sbt_1.0/2018.3/jars/sbt-idea-shell.jar:/home/waleedbinehsan/idea-IE-201.7846.105/plugins/Scala/repo/org.jetbrains/sbt-idea-compiler-indices/scala_2.12/sbt_1.0/0.1.3/jars/sbt-idea-compiler-indices.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/sugakandrey/scala-compiler-indices-protocol_2.12/0.1.1/scala-compiler-indices-protocol_2.12-0.1.1.jar:/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-library.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/io/spray/spray-json_2.12/1.3.4/spray-json_2.12-1.3.4.jar

project/target/streams/runtime/managedClasspath/_global/streams/export

@@ -1 +1 @@
-
+/home/waleedbinehsan/idea-IE-201.7846.105/plugins/Scala/repo/org.jetbrains/sbt-structure-extractor/scala_2.12/sbt_1.0/2018.2.1+4-88400d3f/jars/sbt-structure-extractor.jar:/home/waleedbinehsan/idea-IE-201.7846.105/plugins/Scala/repo/org.jetbrains/sbt-idea-shell/scala_2.12/sbt_1.0/2018.3/jars/sbt-idea-shell.jar:/home/waleedbinehsan/idea-IE-201.7846.105/plugins/Scala/repo/org.jetbrains/sbt-idea-compiler-indices/scala_2.12/sbt_1.0/0.1.3/jars/sbt-idea-compiler-indices.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/io/github/sugakandrey/scala-compiler-indices-protocol_2.12/0.1.1/scala-compiler-indices-protocol_2.12-0.1.1.jar:/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-library.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/io/spray/spray-json_2.12/1.3.4/spray-json_2.12-1.3.4.jar

src/main/scala/ifu/el2_ifu_bp_ctl.scala

@@ -13,6 +13,7 @@ class el2_ifu_bp_ctl extends Module with el2_lib {
   io.out := el2_btb_ghr_hash(io.in,io.in2)
 }
 
-object ifu extends App {
+//object ifu_ic extends App {
-  println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu_bp_ctl()))
+//  println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu_bp_ctl()))
-}
+//}
+

src/main/scala/ifu/el2_ifu_ic_mem.scala

@@ -0,0 +1,86 @@
+package ifu
+import lib._
+import chisel3._
+import chisel3.util._
+
+class el2_ifu_ic_mem extends Module with param{
+  val io = IO(new Bundle{
+    val clk = Input(Bool())
+    val rst_l = Input(Bool())
+    val clk_override = Input(Bool())
+    val dec_tlu_core_ecc_disable = Input(Bool())
+    val ic_rw_addr = Input(UInt(31.W))
+    val ic_wr_en = Input(UInt(ICACHE_NUM_WAYS.W))
+    val ic_rd_en = Input(Bool())
+    val ic_debug_addr = Input(UInt((ICACHE_INDEX_HI-3).W))
+    val ic_debug_rd_en = Input(Bool())
+    val ic_debug_wr_en = Input(Bool())
+    val ic_debug_tag_array = Input(Bool())
+    val ic_debug_way = Input(UInt(ICACHE_NUM_WAYS.W))
+    val ic_premux_data = Input(UInt(64.W))
+    val ic_sel_premux_data = Input(Bool())
+    val ic_wr_data = Vec(ICACHE_BANK_WAY, Input(UInt(71.W)))
+    val ic_rd_data = Output(UInt(64.W))
+    val ic_debug_rd_data = Output(UInt(71.W))
+    val ictag_debug_rd_data = Output(UInt(26.W))
+    val ic_debug_wr_data = Input(UInt(71.W))
+    val ic_eccerr = Output(UInt(ICACHE_BANK_WAY.W))
+    val ic_parerr = Output(UInt(ICACHE_BANK_WAY.W))
+    val ic_tag_valid = Input(UInt(ICACHE_NUM_WAYS.W))
+    val ic_rd_hit = Output(UInt(ICACHE_NUM_WAYS.W))
+    val ic_tag_perr = Output(Bool())
+    val scan_mode = Input(Bool())
+  })
+  io.ic_tag_perr := 0.U
+  io.ic_rd_hit := 0.U
+  io.ic_parerr := 0.U
+  io.ic_eccerr := 0.U
+  io.ictag_debug_rd_data := 0.U
+  io.ic_debug_rd_data := 0.U
+  io.ic_rd_data := 0.U
+  //val icache_tag = Module(new kncpa)
+}
+class EL2_IC_TAG extends Module with el2_lib with param {
+  val io = IO(new Bundle{
+    val clk = Input(Bool())
+    val rst_l = Input(Bool())
+    val clk_override = Input(Bool())
+    val dec_tlu_core_ecc_disable = Input(Bool())
+    val ic_rw_addr = Input(UInt(29.W))
+    val ic_wr_en = Input(UInt(ICACHE_NUM_WAYS.W))
+    val ic_tag_valid = Input(UInt(ICACHE_NUM_WAYS.W))
+    val ic_rd_en = Input(Bool())
+    val ic_debug_addr = Input(UInt((ICACHE_INDEX_HI-3).W))
+    val ic_debug_rd_en = Input(Bool())
+    val ic_debug_wr_en = Input(Bool())
+    val ic_debug_tag_array = Input(Bool())
+    val ic_debug_way = Input(UInt(ICACHE_NUM_WAYS.W))
+    val ictag_debug_rd_data = Output(UInt(26.W))
+    val ic_debug_wr_data = Input(UInt(71.W))
+    val ic_rd_hit = Output(UInt(ICACHE_NUM_WAYS.W))
+    val ic_tag_perr = Output(Bool())
+    val scan_mode = Input(Bool())
+
+    val test = Output(UInt())
+  })
+
+
+  val ic_tag_wren = io.ic_wr_en & repl(ICACHE_NUM_WAYS, io.ic_rw_addr(ICACHE_BEAT_ADDR_HI,4)===
+    repl(ICACHE_NUM_WAYS-1, 1.U))
+  val ic_debug_rd_way_en = repl(ICACHE_NUM_WAYS, io.ic_debug_rd_en & io.ic_debug_tag_array) & io.ic_debug_way
+  val ic_debug_wr_way_en = repl(ICACHE_NUM_WAYS, io.ic_debug_wr_en & io.ic_debug_tag_array) & io.ic_debug_way
+  val ic_tag_clken = repl(ICACHE_NUM_WAYS,io.ic_rd_en | io.clk_override) | io.ic_wr_en | ic_debug_wr_way_en |
+    ic_debug_rd_way_en
+  val ic_rd_en_ff = RegNext(io.ic_rd_en, init=0.U)
+  val ic_rw_addr_ff = RegNext(io.ic_rw_addr(31,ICACHE_TAG_LO))
+  val PAD_BITS = 21 - (32 - ICACHE_TAG_LO)
+  val ic_tag_wren_q = ic_tag_wren | ic_debug_wr_way_en
+
+  io.test:= ic_tag_wren
+  io.ic_tag_perr := 0.U
+  io.ic_rd_hit := 0.U
+  io.ictag_debug_rd_data := 0.U
+}
+object ifu_ic extends App {
+  println((new chisel3.stage.ChiselStage).emitVerilog(new EL2_IC_TAG()))
+}

src/main/scala/lib/beh_lib.scala

@@ -0,0 +1,337 @@
+package lib
+import chisel3._
+import chisel3.util._
+
+
+
+class rvdff(WIDTH:Int=1,SHORT:Int=0) extends Module{
+ val io = IO(new Bundle{
+val din  = Input(UInt(WIDTH.W))
+val dout = Output(UInt(WIDTH.W))
+})
+
+val flop = RegNext(io.din,0.U)
+
+if(SHORT == 1)
+{io.dout := io.din}
+else
+{io.dout := flop}
+}
+
+
+class rvsyncss(WIDTH:Int = 251,SHORT:Int = 0) extends Module with RequireAsyncReset{  //Done for verification and testing
+  val io = IO(new Bundle{
+    val din   = Input(UInt(WIDTH.W))
+    val dout  = Output(UInt(WIDTH.W))
+  })
+  val sync_ff1 = RegNext(io.din,0.U)    //RegNext(io.in,init)
+  val sync_ff2 = RegNext(sync_ff1,0.U)
+  if(SHORT == 1)
+  {	io.dout := io.din   }
+  else
+  {	io.dout := sync_ff2 }
+}
+
+
+
+class rvlsadder extends Module{  //Done for verification and testing
+  val io = IO(new Bundle{
+    val rs1     = Input(UInt(32.W))
+    val offset  = Input(UInt(12.W))
+    val dout    = Output(UInt(32.W))
+  })
+  val w1 =  Cat("b0".U,io.rs1(11,0)) + Cat("b0".U,io.offset(11,0))  //w1[12] =cout  offset[11]=sign
+
+  val dout_upper = ((Fill(20, ~(io.offset(11) ^ w1(12)))) & io.rs1(31,12)) |
+    ((Fill(20, ~io.offset(11) ^ w1(12))) & (io.rs1(31,12)+1.U)) |
+    ((Fill(20, io.offset(11) ^ ~w1(12))) & (io.rs1(31,12)-1.U))
+
+  io.dout := Cat(dout_upper,w1(11,0))
+}
+
+
+
+
+class rvbsadder extends Module{   //Done for verification and testing
+  val io = IO(new Bundle{
+    val pc     = Input(UInt(32.W)) // lsb is not using in code
+    val offset = Input(UInt(13.W)) // lsb is not using in code
+    val dout   = Output(UInt(31.W))
+  })
+  val w1 =  Cat("b0".U,io.pc(12,1)) + Cat("b0".U,io.offset(12,1))  //w1[12] =cout  offset[12]=sign
+
+  val dout_upper = ((Fill(19, ~(io.offset(12) ^ w1(12))))&  io.pc(31,13))       |
+    ((Fill(19, ~io.offset(12) ^  w1(12))) & (io.pc(31,13)+1.U)) |
+    ((Fill(19, io.offset(12) ^  ~w1(12))) & (io.pc(31,13)-1.U))
+  io.dout := Cat(dout_upper,w1(11,0))
+}
+
+
+
+
+class rvtwoscomp(WIDTH:Int=32) extends Module{   //Done for verification and testing
+  val io = IO(new Bundle{
+    val din   = Input(UInt(WIDTH.W))
+    val dout  = Output(UInt(WIDTH.W))
+  })
+
+
+  val temp = Wire(Vec(WIDTH-1,UInt(1.W)))
+  val i:Int = 1
+
+  for(i <- 1 to WIDTH-1){
+    val done  = io.din(i-1,0).orR
+    temp(i-1) := Mux(done ,~io.din(i),io.din(i))
+  }
+  io.dout := Cat(temp.asUInt,io.din(0))
+}
+
+
+class rvmaskandmatch(WIDTH:Int=32) extends Module{     //Done for verification and testing
+  val io = IO(new Bundle{
+    val mask       = Input(UInt(WIDTH.W))
+    val data       = Input(UInt(WIDTH.W))
+    val masken     = Input(UInt(1.W))
+    val match_out  = Output(UInt(1.W))
+  })
+
+  val matchvec = Wire(Vec(WIDTH,UInt(1.W)))
+  val masken_or_fullmask = io.masken.asBool & ~io.mask(WIDTH-1,0).andR
+
+  matchvec(0)  :=  masken_or_fullmask | (io.mask(0) === io.data(0)).asUInt
+
+  for(i <- 1 to WIDTH-1)
+  {matchvec(i) := Mux(io.mask(i-1,0).andR & masken_or_fullmask,"b1".U,(io.mask(i) === io.data(i)).asUInt)}
+  io.match_out := matchvec.asUInt
+}
+
+
+
+
+class rvrangecheck(CCM_SADR:Int=0, CCM_SIZE:Int=128) extends Module{
+  val io = IO(new Bundle{
+    val addr       =  Input(UInt(32.W))
+    val in_range   =  Output(UInt(1.W))
+    val in_region  =  Output(UInt(1.W))
+  })
+  val REGION_BITS = 4
+  val MASK_BITS   = 10 + log2Ceil(CCM_SIZE)
+
+  val start_addr  = Wire(UInt(32.W))
+  start_addr  := CCM_SIZE.U
+  val region  = start_addr(31,(32-REGION_BITS))
+
+  io.in_region  := (io.addr(31,(32-REGION_BITS)) === region(REGION_BITS-1,0)).asUInt
+  if(CCM_SIZE == 48)
+    io.in_range := (io.addr(31,MASK_BITS) === start_addr(31,MASK_BITS)).asUInt & ~(io.addr(MASK_BITS-1,MASK_BITS-2).andR.asUInt)
+  else
+    io.in_range := (io.addr(31,MASK_BITS) === start_addr(31,MASK_BITS)).asUInt
+}
+
+
+
+
+class rveven_paritygen(WIDTH:Int= 16) extends Module{    //Done for verification and testing
+  val io = IO(new Bundle{
+    val data_in        =  Input (UInt(WIDTH.W))
+    val parity_out     =  Output(UInt(1.W))
+  })
+  io.parity_out := io.data_in.xorR.asUInt
+}
+
+
+
+class rveven_paritycheck(WIDTH:Int= 16) extends Module{    //Done for verification and testing
+  val io = IO(new Bundle{
+    val data_in        =  Input (UInt(WIDTH.W))
+    val parity_in      =  Input (UInt(1.W))
+    val parity_err     =  Output(UInt(1.W))
+  })
+  io.parity_err := (io.data_in.xorR.asUInt) ^ io.parity_in
+}
+
+
+
+class rvecc_encode extends Module{   //Done for verification and testing
+  val io      =  IO(new Bundle{
+    val din     =  Input(UInt(32.W))
+    val ecc_out =  Output(UInt(7.W))
+  })
+  val mask0 = Array(0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0,1,1,0,1,1)
+  val mask1 = Array(1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,1,1,0,1)
+  val mask2 = Array(1,1,1,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,1,1,1,1,0,0,0,1,1,1,0)
+  val mask3 = Array(0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,1,1,1,1,1,1,1,0,0,0,0)
+  val mask4 = Array(0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0)
+  val mask5 = Array(1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0)
+  val w0 = Wire(Vec(18,UInt(1.W)))
+  val w1 = Wire(Vec(18,UInt(1.W)))
+  val w2 = Wire(Vec(18,UInt(1.W)))
+  val w3 = Wire(Vec(15,UInt(1.W)))
+  val w4 = Wire(Vec(15,UInt(1.W)))
+  val w5 = Wire(Vec(6, UInt(1.W)))
+  var j = 0;var k = 0;var m = 0;
+  var x = 0;var y = 0;var z = 0
+
+  for(i <- 0 to 31)
+  {
+    if(mask0(i)==1) {w0(j) := io.din(i); j = j +1 }
+    if(mask1(i)==1) {w1(k) := io.din(i); k = k +1 }
+    if(mask2(i)==1) {w2(m) := io.din(i); m = m +1 }
+    if(mask3(i)==1) {w3(x) := io.din(i); x = x +1 }
+    if(mask4(i)==1) {w4(y) := io.din(i); y = y +1 }
+    if(mask5(i)==1) {w5(z) := io.din(i); z = z +1 }
+  }
+  val w6 = Cat((w0.asUInt.xorR),(w1.asUInt.xorR),(w2.asUInt.xorR),(w3.asUInt.xorR),(w4.asUInt.xorR),(w5.asUInt.xorR))
+  io.ecc_out := Cat(io.din.xorR ^ w6.xorR, w6)
+}
+
+
+
+class rvecc_decode extends Module{  //Done for verification and testing
+  val io      =  IO(new Bundle{
+    val en      =  Input(UInt(1.W))
+    val din     =  Input(UInt(32.W))
+    val ecc_in  =  Input(UInt(7.W))
+    val sed_ded =  Input(UInt(1.W))
+    val ecc_out =  Output(UInt(7.W))
+    val dout    =  Output(UInt(32.W))
+    val single_ecc_error = Output(UInt(1.W))
+    val double_ecc_error = Output(UInt(1.W))
+  })
+  val mask0 = Array(1,1,0,1,1,0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0)
+  val mask1 = Array(1,0,1,1,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1)
+  val mask2 = Array(0,1,1,1,0,0,0,1,1,1,1,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,1,1,1)
+  val mask3 = Array(0,0,0,0,1,1,1,1,1,1,1,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0)
+  val mask4 = Array(0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0)
+  val mask5 = Array(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1)
+
+  val w0 = Wire(Vec(18,UInt(1.W)))
+  val w1 = Wire(Vec(18,UInt(1.W)))
+  val w2 = Wire(Vec(18,UInt(1.W)))
+  val w3 = Wire(Vec(15,UInt(1.W)))
+  val w4 = Wire(Vec(15,UInt(1.W)))
+  val w5 = Wire(Vec(6,UInt(1.W)))
+
+  var j = 0;var k = 0;var m = 0;  var n =0;
+  var x = 0;var y = 0;
+
+  for(i <- 0 to 31)
+  {
+    if(mask0(i)==1) {w0(j) := io.din(i); j = j +1 }
+    if(mask1(i)==1) {w1(k) := io.din(i); k = k +1 }
+    if(mask2(i)==1) {w2(m) := io.din(i); m = m +1 }
+    if(mask3(i)==1) {w3(n) := io.din(i); n = n +1 }
+    if(mask4(i)==1) {w4(x) := io.din(i); x = x +1 }
+    if(mask5(i)==1) {w5(y) := io.din(i); y = y +1 }
+  }
+
+  val ecc_check = Cat((io.din.xorR ^ io.ecc_in.xorR) & ~io.sed_ded ,io.ecc_in(5)^(w5.asUInt.xorR),io.ecc_in(4)^(w4.asUInt.xorR),io.ecc_in(3)^(w3.asUInt.xorR),io.ecc_in(2)^(w2.asUInt.xorR),io.ecc_in(1)^(w1.asUInt.xorR),io.ecc_in(0)^(w0.asUInt.xorR))
+  io.ecc_out := ecc_check
+
+  io.single_ecc_error :=  io.en & (ecc_check!= 0.U) & ((io.din.xorR ^ io.ecc_in.xorR) & ~io.sed_ded)
+  io.double_ecc_error :=  io.en & (ecc_check!= 0.U) & ((io.din.xorR ^ io.ecc_in.xorR) & ~io.sed_ded)
+  val error_mask = Wire(Vec(39,UInt(1.W)))
+
+  for(i <- 1 until 40){
+    error_mask(i-1) := ecc_check(5,0) === i.asUInt
+  }
+  val din_plus_parity = Cat(io.ecc_in(6), io.din(31,26), io.ecc_in(5), io.din(25,11), io.ecc_in(4), io.din(10,4), io.ecc_in(3), io.din(3,1), io.ecc_in(2), io.din(0), io.ecc_in(1,0))
+  val dout_plus_parity = Mux(io.single_ecc_error.asBool, (error_mask.asUInt ^ din_plus_parity), din_plus_parity)
+
+  io.dout :=  Cat(dout_plus_parity(37,32),dout_plus_parity(30,16), dout_plus_parity(14,8), dout_plus_parity(6,4), dout_plus_parity(2))
+  io.ecc_out := Cat(dout_plus_parity(38) ^ (ecc_check(6,0) === "b1000000".U), dout_plus_parity(31), dout_plus_parity(15), dout_plus_parity(7), dout_plus_parity(3), dout_plus_parity(1,0))
+}
+
+
+
+
+
+
+class rvecc_encode_64 extends Module{    //Done for verification and testing
+  val io      =  IO(new Bundle{
+    val din     =  Input(UInt(64.W))
+    val ecc_out =  Output(UInt(7.W))
+  })
+  val mask0 = Array(1,1,0,1,1,0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0,1)
+  val mask1 = Array(1,0,1,1,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1,1)
+  val mask2 = Array(0,1,1,1,0,0,0,1,1,1,1,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,1,1,1,1)
+  val mask3 = Array(0,0,0,0,1,1,1,1,1,1,1,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0)
+  val mask4 = Array(0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0)
+  val mask5 = Array(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0)
+  val mask6 = Array(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1)
+
+  val w0 = Wire(Vec(35,UInt(1.W)))
+  val w1 = Wire(Vec(35,UInt(1.W)))
+  val w2 = Wire(Vec(35,UInt(1.W)))
+  val w3 = Wire(Vec(31,UInt(1.W)))
+  val w4 = Wire(Vec(31,UInt(1.W)))
+  val w5 = Wire(Vec(31,UInt(1.W)))
+  val w6 = Wire(Vec(7, UInt(1.W)))
+
+  var j = 0;var k = 0;var m = 0; var n =0;
+  var x = 0;var y = 0;var z = 0
+
+  for(i <- 0 to 63)
+  {
+    if(mask0(i)==1) {w0(j) := io.din(i); j = j +1 }
+    if(mask1(i)==1) {w1(k) := io.din(i); k = k +1 }
+    if(mask2(i)==1) {w2(m) := io.din(i); m = m +1 }
+    if(mask3(i)==1) {w3(n) := io.din(i); n = n +1 }
+    if(mask4(i)==1) {w4(x) := io.din(i); x = x +1 }
+    if(mask5(i)==1) {w5(y) := io.din(i); y = y +1 }
+    if(mask6(i)==1) {w6(z) := io.din(i); z = z +1 }
+  }
+  io.ecc_out := Cat((w0.asUInt.xorR),(w1.asUInt.xorR),(w2.asUInt.xorR),(w3.asUInt.xorR),(w4.asUInt.xorR),(w5.asUInt.xorR),(w6.asUInt.xorR))
+}
+
+
+
+
+
+class rvecc_decode_64 extends Module{     //Done for verification and testing
+  val io        =  IO(new Bundle{
+    val en        =  Input(UInt(1.W))
+    val din       =  Input(UInt(64.W))
+    val ecc_in    =  Input(UInt(7.W))
+    val ecc_error =  Output(UInt(1.W))
+  })
+  val mask0 = Array(1,1,0,1,1,0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0,1)
+  val mask1 = Array(1,0,1,1,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1,1)
+  val mask2 = Array(0,1,1,1,0,0,0,1,1,1,1,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,1,1,1,1)
+  val mask3 = Array(0,0,0,0,1,1,1,1,1,1,1,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0)
+  val mask4 = Array(0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0)
+  val mask5 = Array(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0)
+  val mask6 = Array(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1)
+
+  val w0 = Wire(Vec(35,UInt(1.W)))
+  val w1 = Wire(Vec(35,UInt(1.W)))
+  val w2 = Wire(Vec(35,UInt(1.W)))
+  val w3 = Wire(Vec(31,UInt(1.W)))
+  val w4 = Wire(Vec(31,UInt(1.W)))
+  val w5 = Wire(Vec(31,UInt(1.W)))
+  val w6 = Wire(Vec(7, UInt(1.W)))
+
+  var j = 0;var k = 0;var m = 0;  var n =0;
+  var x = 0;var y = 0;var z = 0
+
+  for(i <- 0 to 63)
+  {
+    if(mask0(i)==1) {w0(j) := io.din(i); j = j +1 }
+    if(mask1(i)==1) {w1(k) := io.din(i); k = k +1 }
+    if(mask2(i)==1) {w2(m) := io.din(i); m = m +1 }
+    if(mask3(i)==1) {w3(n) := io.din(i); n = n +1 }
+    if(mask4(i)==1) {w4(x) := io.din(i); x = x +1 }
+    if(mask5(i)==1) {w5(y) := io.din(i); y = y +1 }
+    if(mask6(i)==1) {w6(z) := io.din(i); z = z +1 }
+  }
+
+  val ecc_check = Cat((io.ecc_in(6) ^ w5.asUInt.xorR) ,io.ecc_in(5)^(w5.asUInt.xorR),io.ecc_in(4)^(w4.asUInt.xorR),io.ecc_in(3)^(w3.asUInt.xorR),io.ecc_in(2)^(w2.asUInt.xorR),io.ecc_in(1)^(w1.asUInt.xorR),io.ecc_in(0)^(w0.asUInt.xorR))
+  io.ecc_error := io.en & (ecc_check(6,0) != 0.U)
+}
+
+
+
+
+
+
+

src/main/scala/lib/el2_lib.scala

@@ -12,8 +12,13 @@ trait param {
   val BTB_INDEX2_LO    = 10
   val BTB_INDEX3_HI    = 25
   val BTB_INDEX3_LO    = 18
-  val BHT_GHR_HASH_1   = false
+  val BHT_GHR_HASH_1   = true
   val BHT_GHR_SIZE     = 8
+  val ICACHE_NUM_WAYS = 2
+  val ICACHE_INDEX_HI = 12
+  val ICACHE_BANK_WAY = 2
+  val ICACHE_BEAT_ADDR_HI = 5
+  val ICACHE_TAG_LO = 13
 }
 
 trait el2_lib extends param{
@@ -28,6 +33,9 @@ trait el2_lib extends param{
     else pc(BTB_INDEX1_HI,BTB_INDEX1_LO) ^ pc(BTB_INDEX2_HI,BTB_INDEX2_LO) ^ pc(BTB_INDEX3_HI,BTB_INDEX3_LO)
 
   def el2_btb_ghr_hash(hashin : UInt, ghr :UInt) =
-    if(BHT_GHR_HASH_1) Cat(ghr(BHT_GHR_SIZE-1,BTB_INDEX1_HI), hashin(BTB_INDEX1_HI,2) ^ ghr(BTB_INDEX1_HI-2,0))
+    if(BHT_GHR_HASH_1) Cat(ghr(BHT_GHR_SIZE-1,BTB_INDEX1_HI-1), hashin(BTB_INDEX1_HI,2) ^ ghr(BTB_INDEX1_HI-2,0))
     else hashin(BHT_GHR_SIZE+1,2) ^ ghr(BHT_GHR_SIZE-1,0)
+
+  def repl(b:Int, a:UInt) : UInt =
+    VecInit.tabulate(b)(i => a).reduce(Cat(_,_))
 }

target/streams/_global/_global/checkBuildSources/_global/streams/out

@@ -1 +1 @@
-[debug] Checking for meta build source updates
+[debug] Checking for meta build source updates

target/streams/compile/_global/_global/compileSourceFileInputs/previous

@@ -1 +1 @@
-["sbt.Task[scala.collection.immutable.Map[java.lang.String, scala.collection.Seq[scala.Tuple2[java.nio.file.Path, sbt.nio.FileStamp]]]]",{"2.12.10":{"hashes":[["/home/waleedbinehsan/Desktop/SweRV-Chislified-master/src/main/scala/ifu/el2_ifu.scala","90ccc65ac7488b8494521c865b772c52b8366feb"],["/home/waleedbinehsan/Desktop/SweRV-Chislified-master/src/main/scala/snapshot/el2_param.scala","9d4cedee7eee5415275809ba6f02d693324110fd"],["/home/waleedbinehsan/Desktop/SweRV-Chislified-master/src/main/scala/lsu/el2_lsu.scala","1ef8375e06a926acc2800ce9f66b230a1a778a47"],["/home/waleedbinehsan/Desktop/SweRV-Chislified-master/src/main/scala/exu/el2_exu.scala","3f9225ed252ed66244ffaadc30181214d49eae29"],["/home/waleedbinehsan/Desktop/SweRV-Chislified-master/src/main/scala/dbg/el2_dbg.scala","a9288ad33e4be923745906ebdbedfc6940f5938b"],["/home/waleedbinehsan/Desktop/SweRV-Chislified-master/src/main/scala/lib/RVC.scala","bf772bd5f03f6938a3504872c23458ba6e032de2"],["/home/waleedbinehsan/Desktop/SweRV-Chislified-master/src/main/scala/lib/GCD.scala","21b7b4ecacf689e7624e3b296d935d5e5a464bc3"],["/home/waleedbinehsan/Desktop/SweRV-Chislified-master/src/main/scala/dmi/rvjtag_tap.scala","725d115902c1948b83040e3ae82f26ae3d44ee4b"],["/home/waleedbinehsan/Desktop/SweRV-Chislified-master/src/main/scala/dmi/dmi_jtag_to_core_sync.scala","973d8d71d39c2efb8a9869b538f76cb3f12fbd98"],["/home/waleedbinehsan/Desktop/SweRV-Chislified-master/src/main/scala/dmi/dmi_wrapper.scala","e57d82ef2ee034749d59900097403d64f5d99c7f"],["/home/waleedbinehsan/Desktop/SweRV-Chislified-master/src/main/scala/include/el2_bundle.scala","7305502ad88955c24e9f36a285410245bbd70b91"],["/home/waleedbinehsan/Desktop/SweRV-Chislified-master/src/main/scala/dec/el2_dec_dec_ctl.scala","84211b988157662baf5d608862039be53d036cb8"]],"lastModifiedTimes":[]}}]
+["sbt.Task[scala.collection.immutable.Map[java.lang.String, scala.collection.Seq[scala.Tuple2[java.nio.file.Path, sbt.nio.FileStamp]]]]",{"2.12.10":{"hashes":[["/home/waleedbinehsan/Desktop/SweRV-Chislified-master/src/main/scala/ifu/el2_ifu_bp_ctl.scala","e7075fe90fd5f9d5626d55fdd950bb57843575ca"],["/home/waleedbinehsan/Desktop/SweRV-Chislified-master/src/main/scala/ifu/el2_ifu_ic_mem.scala","f8ee55252a08ba8028c3363b17fa465c828d80d6"],["/home/waleedbinehsan/Desktop/SweRV-Chislified-master/src/main/scala/ifu/el2_ifu.scala","90ccc65ac7488b8494521c865b772c52b8366feb"],["/home/waleedbinehsan/Desktop/SweRV-Chislified-master/src/main/scala/snapshot/el2_param.scala","9d4cedee7eee5415275809ba6f02d693324110fd"],["/home/waleedbinehsan/Desktop/SweRV-Chislified-master/src/main/scala/lsu/el2_lsu.scala","1ef8375e06a926acc2800ce9f66b230a1a778a47"],["/home/waleedbinehsan/Desktop/SweRV-Chislified-master/src/main/scala/exu/el2_exu.scala","3f9225ed252ed66244ffaadc30181214d49eae29"],["/home/waleedbinehsan/Desktop/SweRV-Chislified-master/src/main/scala/dbg/el2_dbg.scala","a9288ad33e4be923745906ebdbedfc6940f5938b"],["/home/waleedbinehsan/Desktop/SweRV-Chislified-master/src/main/scala/lib/RVC.scala","bf772bd5f03f6938a3504872c23458ba6e032de2"],["/home/waleedbinehsan/Desktop/SweRV-Chislified-master/src/main/scala/lib/GCD.scala","21b7b4ecacf689e7624e3b296d935d5e5a464bc3"],["/home/waleedbinehsan/Desktop/SweRV-Chislified-master/src/main/scala/lib/el2_lib.scala","8a558dff7becf15e5c7702933975b775f156b689"],["/home/waleedbinehsan/Desktop/SweRV-Chislified-master/src/main/scala/dmi/rvjtag_tap.scala","725d115902c1948b83040e3ae82f26ae3d44ee4b"],["/home/waleedbinehsan/Desktop/SweRV-Chislified-master/src/main/scala/dmi/dmi_jtag_to_core_sync.scala","973d8d71d39c2efb8a9869b538f76cb3f12fbd98"],["/home/waleedbinehsan/Desktop/SweRV-Chislified-master/src/main/scala/dmi/dmi_wrapper.scala","e57d82ef2ee034749d59900097403d64f5d99c7f"],["/home/waleedbinehsan/Desktop/SweRV-Chislified-master/src/main/scala/include/el2_bundle.scala","7305502ad88955c24e9f36a285410245bbd70b91"],["/home/waleedbinehsan/Desktop/SweRV-Chislified-master/src/main/scala/dec/el2_dec_dec_ctl.scala","30ca3d905e7f594432b65a1f1064fa2f9999e3bc"]],"lastModifiedTimes":[]}}]

target/streams/compile/_global/_global/discoveredMainClasses/data

@@ -1 +1 @@
-["dec.dec"]
+["ifu.ifu_ic"]

target/streams/compile/compile/_global/streams/out

@@ -1,5 +1,2 @@
-[warn] there was one deprecation warning (since 3.2.2)
+[warn] there were 266 feature warnings; re-run with -feature for details
-[warn] there was one deprecation warning (since 3.2.4)
+[warn] one warning found
-[warn] there were two deprecation warnings in total; re-run with -deprecation for details
-[warn] there were 72 feature warnings; re-run with -feature for details
-[warn] four warnings found

target/streams/compile/compileIncremental/_global/streams/out

@@ -1,24 +1,24 @@
 [debug] 
 [debug] Initial source changes: 
 [debug] 	removed:Set()
-[debug] 	added: Set()
+[debug] 	added: Set(/home/waleedbinehsan/Desktop/SweRV-Chislified-master/src/main/scala/ifu/el2_ifu_ic_mem.scala, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/src/main/scala/ifu/el2_ifu_bp_ctl.scala, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/src/main/scala/lib/el2_lib.scala)
 [debug] 	modified: Set(/home/waleedbinehsan/Desktop/SweRV-Chislified-master/src/main/scala/dec/el2_dec_dec_ctl.scala)
-[debug] Invalidated products: Set()
+[debug] Invalidated products: Set(/home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/encoder_generator.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/rvrangecheck.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/RVCExpander$$anon$1.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/dbg/el2_dbg.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/caller$$anon$2.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/dec/dec$.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/rvrangecheck$.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/exp$$anon$9.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/RVCDecoder.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/rvdff$.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/RVCExpander.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/rvbradder.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/reg1.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/dmi/dmi_jtag_to_core_sync.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/reg1$$anon$3.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/tocopy.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/dmi/dmi_wrapper.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/rvdff$$anon$1.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/snapshot/pt.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/tocopy$$anon$8.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/dec/el2_dec_dec_ctl.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/dec/el2_dec_pkt_t.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/top$$anon$4.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/caller.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/encoder_generator$$anon$6.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/ExpandedInstruction.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/rvrangecheck$$anon$7.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/rvdff.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/rvbradder$$anon$5.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/exp.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/top.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/encoder_generator$.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/snapshot/pt$.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/dec/dec.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/dec/dec$delayedInit$body.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/exu/el2_exu.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/dmi/rvjtag_tap.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lsu/el2_lsu.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/dec/el2_dec_dec_ctl$$anon$1.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/ifu/el2_ifu.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/include/el2_bundle.class)
 [debug] External API changes: API Changes: Set()
 [debug] Modified binary dependencies: Set()
 [debug] Initial directly invalidated classes: Set(dec.dec, dec.el2_dec_dec_ctl, dec.el2_dec_pkt_t)
 [debug] 
 [debug] Sources indirectly invalidated by:
-[debug] 	product: Set()
+[debug] 	product: Set(/home/waleedbinehsan/Desktop/SweRV-Chislified-master/src/main/scala/include/el2_bundle.scala, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/src/main/scala/dmi/rvjtag_tap.scala, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/src/main/scala/lib/RVC.scala, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/src/main/scala/exu/el2_exu.scala, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/src/main/scala/dbg/el2_dbg.scala, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/src/main/scala/dmi/dmi_jtag_to_core_sync.scala, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/src/main/scala/dmi/dmi_wrapper.scala, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/src/main/scala/dec/el2_dec_dec_ctl.scala, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/src/main/scala/lsu/el2_lsu.scala, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/src/main/scala/ifu/el2_ifu.scala, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/src/main/scala/lib/GCD.scala, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/src/main/scala/snapshot/el2_param.scala)
 [debug] 	binary dep: Set()
 [debug] 	external source: Set()
-[debug] All initially invalidated classes: Set(dec.dec, dec.el2_dec_dec_ctl, dec.el2_dec_pkt_t)
+[debug] All sources are invalidated.
-[debug] All initially invalidated sources:Set(/home/waleedbinehsan/Desktop/SweRV-Chislified-master/src/main/scala/dec/el2_dec_dec_ctl.scala)
 [debug] Initial set of included nodes: dec.dec, dec.el2_dec_dec_ctl, dec.el2_dec_pkt_t
-[info] Compiling 1 Scala source to /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes ...
+[debug] Recompiling all sources: number of invalidated sources > 50.0% of all sources
+[info] Compiling 15 Scala sources to /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes ...
 [debug] Getting org.scala-sbt:compiler-bridge_2.12:1.3.5:compile for Scala 2.12.10
 [debug] Getting org.scala-sbt:compiler-bridge_2.12:1.3.5:compile for Scala 2.12.10
-[debug] [zinc] Running cached compiler 3bb278c6 for Scala compiler version 2.12.10
+[debug] [zinc] Running cached compiler 69ba6af for Scala compiler version 2.12.10
 [debug] [zinc] The Scala compiler is invoked with:
 [debug] 	-Xsource:2.11
 [debug] 	-Xplugin:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalamacros/paradise_2.12.10/2.1.0/paradise_2.12.10-2.1.0.jar
@@ -26,11 +26,5 @@
 [debug] 	/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-library.jar
 [debug] 	-classpath
 [debug] 	/home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar:/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar
-[debug] Scala compilation took 9.899922123 s
+[debug] Scala compilation took 8.031658869 s
 [debug] Done compiling.
-[debug] New invalidations:
-[debug] 	Set()
-[debug] Initial set of included nodes: 
-[debug] Previously invalidated, but (transitively) depend on new invalidations:
-[debug] 	Set()
-[debug] No classes were invalidated.

target/streams/compile/packageBin/_global/streams/inputs

@@ -1 +1 @@
-1668409227
+2112381394

target/streams/compile/packageBin/_global/streams/out

@@ -2,8 +2,28 @@
 [debug] Input file mappings:
 [debug] 	ifu
 [debug] 	  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/ifu
+[debug] 	ifu/ifu_ic.class
+[debug] 	  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/ifu/ifu_ic.class
 [debug] 	ifu/el2_ifu.class
 [debug] 	  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/ifu/el2_ifu.class
+[debug] 	ifu/el2_ifu_ic_mem.class
+[debug] 	  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/ifu/el2_ifu_ic_mem.class
+[debug] 	ifu/ifu_ic$.class
+[debug] 	  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/ifu/ifu_ic$.class
+[debug] 	ifu/ifu$.class
+[debug] 	  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/ifu/ifu$.class
+[debug] 	ifu/el2_ifu_bp_ctl$$anon$1.class
+[debug] 	  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/ifu/el2_ifu_bp_ctl$$anon$1.class
+[debug] 	ifu/el2_ifu_bp_ctl.class
+[debug] 	  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/ifu/el2_ifu_bp_ctl.class
+[debug] 	ifu/ifu.class
+[debug] 	  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/ifu/ifu.class
+[debug] 	ifu/ifu_ic$delayedInit$body.class
+[debug] 	  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/ifu/ifu_ic$delayedInit$body.class
+[debug] 	ifu/el2_ifu_ic_mem$$anon$1.class
+[debug] 	  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/ifu/el2_ifu_ic_mem$$anon$1.class
+[debug] 	ifu/ifu$delayedInit$body.class
+[debug] 	  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/ifu/ifu$delayedInit$body.class
 [debug] 	snapshot
 [debug] 	  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/snapshot
 [debug] 	snapshot/pt$.class
@@ -34,6 +54,8 @@
 [debug] 	  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/rvrangecheck$.class
 [debug] 	lib/exp.sc
 [debug] 	  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/exp.sc
+[debug] 	lib/el2_lib.class
+[debug] 	  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/el2_lib.class
 [debug] 	lib/exp.class
 [debug] 	  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/exp.class
 [debug] 	lib/top.class
@@ -72,6 +94,8 @@
 [debug] 	  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/encoder_generator$.class
 [debug] 	lib/caller.class
 [debug] 	  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/caller.class
+[debug] 	lib/param.class
+[debug] 	  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/param.class
 [debug] 	lib/rvdff.class
 [debug] 	  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/rvdff.class
 [debug] 	lib/ExpandedInstruction.class
@@ -96,10 +120,4 @@
 [debug] 	  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/dec/el2_dec_pkt_t.class
 [debug] 	dec/el2_dec_dec_ctl.class
 [debug] 	  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/dec/el2_dec_dec_ctl.class
-[debug] 	dec/dec$.class
-[debug] 	  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/dec/dec$.class
-[debug] 	dec/dec.class
-[debug] 	  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/dec/dec.class
-[debug] 	dec/dec$delayedInit$body.class
-[debug] 	  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/dec/dec$delayedInit$body.class
 [debug] Done packaging.