Quasar top done

src/main/scala/dbg/dbg.scala

@@ -450,6 +450,3 @@ class dbg extends Module with lib with RequireAsyncReset {
   io.dbg_dma.dbg_ib.dbg_cmd_write     := io.dbg_dec.dbg_ib.dbg_cmd_write
   io.dbg_dma.dbg_ib.dbg_cmd_type      := io.dbg_dec.dbg_ib.dbg_cmd_type
 }
-object dgb extends App {
-  println((new chisel3.stage.ChiselStage).emitVerilog(new dbg()))
-}

src/main/scala/lib/lib.scala

@@ -4,11 +4,16 @@ import chisel3.util._
 import include._
 trait lib extends param{
   implicit def int2boolean(b:Int) = if (b==1) true else false
+
   implicit def uint2bool(b:UInt) = b.asBool()
+
   implicit def aslong(b:Int) = 0xFFFFFFFFL & b
+
   def repl(b:Int, a:UInt) = VecInit.tabulate(b)(i => a).reduce(Cat(_,_))
 
-  def bridge_gen(tag: Int, ahb_type: Boolean) = if(BUILD_AXI4) new axi_channels(tag) else ahb_bridge_gen(ahb_type)
+  def bridge_gen(tag: Int, ahb_type: Boolean) = if(BUILD_AXI4) flip(tag, ahb_type) else ahb_bridge_gen(ahb_type)
+
+  def flip(tag: Int , ahb_type: Boolean) = if(ahb_type) Flipped(new axi_channels(tag)) else new axi_channels(tag)
 
   def ahb_bridge_gen(ahb_type: Boolean) = if(ahb_type) new Bundle{
     val ahb= Flipped(new ahb_channel())
@@ -23,6 +28,7 @@ trait lib extends param{
       case(1,0)  => (68*ICACHE_NUM_WAYS, 22*ICACHE_NUM_WAYS, 68, 22)
       case(1,1)   => (71*ICACHE_NUM_WAYS, 26*ICACHE_NUM_WAYS, 71, 26)
     }
+
   val DATA_MEM_LINE = MEM_CAL
   val Tag_Word = MEM_CAL._4
 

src/main/scala/quasar_wrapper.scala

@@ -16,7 +16,7 @@ class quasar_wrapper extends Module with lib with RequireAsyncReset {
     val lsu_brg = bridge_gen(LSU_BUS_TAG, false)
     val ifu_brg = bridge_gen(IFU_BUS_TAG, false)
     val sb_brg = bridge_gen(SB_BUS_TAG, false)
-    val dma_brg = Flipped(bridge_gen(DMA_BUS_TAG, true))
+    val dma_brg = bridge_gen(DMA_BUS_TAG, true)
 
     val lsu_bus_clk_en = Input(Bool())
     val ifu_bus_clk_en = Input(Bool())
@@ -96,10 +96,10 @@ class quasar_wrapper extends Module with lib with RequireAsyncReset {
 
 
   if(BUILD_AXI4) {
-    swerv.io.ahb.in <> 0.U.asTypeOf(swerv.io.ahb.in)
+    swerv.io.ahb <> 0.U.asTypeOf(swerv.io.ahb)
-    swerv.io.lsu_ahb.in <> 0.U.asTypeOf(swerv.io.lsu_ahb.in)
+    swerv.io.lsu_ahb <> 0.U.asTypeOf(swerv.io.lsu_ahb)
-    swerv.io.sb_ahb.in <> 0.U.asTypeOf(swerv.io.sb_ahb.in)
+    swerv.io.sb_ahb <> 0.U.asTypeOf(swerv.io.sb_ahb)
-    swerv.io.dma.ahb.out <> 0.U.asTypeOf(swerv.io.dma.ahb.out)
+    swerv.io.dma.ahb <> 0.U.asTypeOf(swerv.io.dma.ahb)
     swerv.io.dma.hsel := 0.U
     swerv.io.dma.hreadyin := 0.U
     swerv.io.lsu_axi <> io.lsu_brg