bus buffer with buf_nextstate in resp updated

src/main/scala/lib/lib.scala

@@ -374,14 +374,14 @@ trait lib extends param{
   object rvdff_fpga {
   def apply(din: UInt, clk: Clock, clken: Bool,rawclk:Clock):UInt = {
     if (RV_FPGA_OPTIMIZE)
-    withClock(rawclk) {RegEnable (din, 0.U, clken)}
+    withClock(clk) {RegEnable (din, 0.U, clken)}
     else RegNext (din, 0.U)
   }
 }
   object rvdffs_fpga {
     def apply(din: UInt, en:Bool,clk: Clock, clken: Bool,rawclk:Clock):UInt = {
       if (RV_FPGA_OPTIMIZE)
-        withClock (rawclk) {RegEnable (din, 0.U, (clken & en))}
+        withClock (clk) {RegEnable (din, 0.U, (clken & en))}
       else RegEnable (din, 0.U,en)
     }
   }

src/main/scala/lsu/lsu_bus_buffer.scala

@@ -353,6 +353,7 @@ class lsu_bus_buffer extends Module with RequireAsyncReset with lib {
   obuf_cmd_done := rvdff_fpga (obuf_cmd_done_in,io.lsu_busm_clk,io.lsu_busm_clken,clock)
   obuf_data_done := rvdff_fpga (obuf_data_done_in,io.lsu_busm_clk,io.lsu_busm_clken,clock)
   obuf_rdrsp_tag := rvdff_fpga (obuf_rdrsp_tag_in,io.lsu_busm_clk,io.lsu_busm_clken,clock)
+
   obuf_tag0 := rvdffs_fpga (obuf_tag0_in,obuf_wr_en,io.lsu_bus_obuf_c1_clk,io.lsu_bus_obuf_c1_clken,clock)
   val obuf_tag1 = rvdffs_fpga (obuf_tag1_in,obuf_wr_en,io.lsu_bus_obuf_c1_clk,io.lsu_bus_obuf_c1_clken,clock)
   val obuf_merge = rvdffs_fpga (obuf_merge_in,obuf_wr_en,io.lsu_bus_obuf_c1_clk,io.lsu_bus_obuf_c1_clken,clock)