bus buffer with buf_nextstate in resp updated

This commit is contained in:
​Laraib Khan 2020-12-28 12:49:43 +05:00
parent 0cd4180d83
commit 57f1b66c15
9 changed files with 4301 additions and 4300 deletions

File diff suppressed because it is too large Load Diff

File diff suppressed because it is too large Load Diff

View File

@ -374,14 +374,14 @@ trait lib extends param{
object rvdff_fpga { object rvdff_fpga {
def apply(din: UInt, clk: Clock, clken: Bool,rawclk:Clock):UInt = { def apply(din: UInt, clk: Clock, clken: Bool,rawclk:Clock):UInt = {
if (RV_FPGA_OPTIMIZE) if (RV_FPGA_OPTIMIZE)
withClock(rawclk) {RegEnable (din, 0.U, clken)} withClock(clk) {RegEnable (din, 0.U, clken)}
else RegNext (din, 0.U) else RegNext (din, 0.U)
} }
} }
object rvdffs_fpga { object rvdffs_fpga {
def apply(din: UInt, en:Bool,clk: Clock, clken: Bool,rawclk:Clock):UInt = { def apply(din: UInt, en:Bool,clk: Clock, clken: Bool,rawclk:Clock):UInt = {
if (RV_FPGA_OPTIMIZE) if (RV_FPGA_OPTIMIZE)
withClock (rawclk) {RegEnable (din, 0.U, (clken & en))} withClock (clk) {RegEnable (din, 0.U, (clken & en))}
else RegEnable (din, 0.U,en) else RegEnable (din, 0.U,en)
} }
} }

View File

@ -353,6 +353,7 @@ class lsu_bus_buffer extends Module with RequireAsyncReset with lib {
obuf_cmd_done := rvdff_fpga (obuf_cmd_done_in,io.lsu_busm_clk,io.lsu_busm_clken,clock) obuf_cmd_done := rvdff_fpga (obuf_cmd_done_in,io.lsu_busm_clk,io.lsu_busm_clken,clock)
obuf_data_done := rvdff_fpga (obuf_data_done_in,io.lsu_busm_clk,io.lsu_busm_clken,clock) obuf_data_done := rvdff_fpga (obuf_data_done_in,io.lsu_busm_clk,io.lsu_busm_clken,clock)
obuf_rdrsp_tag := rvdff_fpga (obuf_rdrsp_tag_in,io.lsu_busm_clk,io.lsu_busm_clken,clock) obuf_rdrsp_tag := rvdff_fpga (obuf_rdrsp_tag_in,io.lsu_busm_clk,io.lsu_busm_clken,clock)
obuf_tag0 := rvdffs_fpga (obuf_tag0_in,obuf_wr_en,io.lsu_bus_obuf_c1_clk,io.lsu_bus_obuf_c1_clken,clock) obuf_tag0 := rvdffs_fpga (obuf_tag0_in,obuf_wr_en,io.lsu_bus_obuf_c1_clk,io.lsu_bus_obuf_c1_clken,clock)
val obuf_tag1 = rvdffs_fpga (obuf_tag1_in,obuf_wr_en,io.lsu_bus_obuf_c1_clk,io.lsu_bus_obuf_c1_clken,clock) val obuf_tag1 = rvdffs_fpga (obuf_tag1_in,obuf_wr_en,io.lsu_bus_obuf_c1_clk,io.lsu_bus_obuf_c1_clken,clock)
val obuf_merge = rvdffs_fpga (obuf_merge_in,obuf_wr_en,io.lsu_bus_obuf_c1_clk,io.lsu_bus_obuf_c1_clken,clock) val obuf_merge = rvdffs_fpga (obuf_merge_in,obuf_wr_en,io.lsu_bus_obuf_c1_clk,io.lsu_bus_obuf_c1_clken,clock)
@ -479,7 +480,7 @@ class lsu_bus_buffer extends Module with RequireAsyncReset with lib {
buf_state_bus_en(i) := buf_resp_state_bus_en(i) buf_state_bus_en(i) := buf_resp_state_bus_en(i)
buf_state_en(i) := (buf_state_bus_en(i) & io.lsu_bus_clk_en) | io.dec_tlu_force_halt buf_state_en(i) := (buf_state_bus_en(i) & io.lsu_bus_clk_en) | io.dec_tlu_force_halt
buf_data_en(i) := buf_state_bus_en(i) & bus_rsp_read & io.lsu_bus_clk_en buf_data_en(i) := buf_state_bus_en(i) & bus_rsp_read & io.lsu_bus_clk_en
buf_error_en(i) := buf_state_bus_en(i) & io.lsu_bus_clk_en & ((bus_rsp_read_error & (bus_rsp_read_tag === (i.asUInt(LSU_BUS_TAG.W)))) | buf_error_en(i) := buf_state_bus_en(i) & io.lsu_bus_clk_en & ((bus_rsp_read_error & (bus_rsp_read_tag === (i.asUInt(LSU_BUS_TAG.W)))) |
(bus_rsp_read_error & buf_ldfwd(i) & (bus_rsp_read_tag === buf_ldfwdtag(i))) | (bus_rsp_read_error & buf_ldfwd(i) & (bus_rsp_read_tag === buf_ldfwdtag(i))) |
(bus_rsp_write_error & (bus_rsp_write_tag === i.asUInt(LSU_BUS_TAG.W)))) (bus_rsp_write_error & (bus_rsp_write_tag === i.asUInt(LSU_BUS_TAG.W))))
buf_data_in(i) := Mux((buf_state_en(i) & !buf_error_en(i)), Mux(buf_addr(i)(2), bus_rsp_rdata(63, 32), bus_rsp_rdata(31, 0)), bus_rsp_rdata(31, 0)) buf_data_in(i) := Mux((buf_state_en(i) & !buf_error_en(i)), Mux(buf_addr(i)(2), bus_rsp_rdata(63, 32), bus_rsp_rdata(31, 0)), bus_rsp_rdata(31, 0))