lib updated

project/target/config-classes/$1e1278e7407262c7fcf4.cache

@@ -1 +0,0 @@
-sbt.internal.DslEntry

project/target/streams/compile/compileIncremental/_global/streams/out

@@ -1 +1 @@
-[debug] Full compilation, no sources in previous analysis.
+[debug] Full compilation, no sources in previous analysis.

project/target/streams/compile/copyResources/_global/streams/out

@@ -1,2 +1,2 @@
-[debug] Copy resource mappings: 
+[debug] Copy resource mappings: 
-[debug] 	
+[debug] 	

quasar_wrapper.fir

@@ -95890,7 +95890,7 @@ circuit quasar_wrapper :
     node _T_748 = and(ld_fwddata_buf_hi_initial, ibuf_data) @[lsu_bus_buffer.scala 174:32]
     node _T_749 = or(_T_747, _T_748) @[lsu_bus_buffer.scala 173:103]
     io.ld_fwddata_buf_hi <= _T_749 @[lsu_bus_buffer.scala 170:24]
-    node bus_coalescing_disable = or(io.tlu_busbuff.dec_tlu_wb_coalescing_disable, UInt<1>("h00")) @[lsu_bus_buffer.scala 176:77]
+    node bus_coalescing_disable = or(io.tlu_busbuff.dec_tlu_wb_coalescing_disable, UInt<1>("h01")) @[lsu_bus_buffer.scala 176:77]
     node _T_750 = mux(io.lsu_pkt_r.bits.by, UInt<4>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_751 = mux(io.lsu_pkt_r.bits.half, UInt<4>("h03"), UInt<1>("h00")) @[Mux.scala 27:72]
     node _T_752 = mux(io.lsu_pkt_r.bits.word, UInt<4>("h0f"), UInt<1>("h00")) @[Mux.scala 27:72]
@@ -114375,7 +114375,7 @@ circuit quasar_wrapper :
     io.dccm.wr_addr_lo <= lsu.io.dccm.wr_addr_lo @[quasar.scala 238:11]
     io.dccm.rden <= lsu.io.dccm.rden @[quasar.scala 238:11]
     io.dccm.wren <= lsu.io.dccm.wren @[quasar.scala 238:11]
-    when UInt<1>("h00") : @[quasar.scala 241:26]
+    when UInt<1>("h01") : @[quasar.scala 241:26]
       inst axi4_to_ahb of axi4_to_ahb @[quasar.scala 242:32]
       axi4_to_ahb.clock <= clock
       axi4_to_ahb.reset <= reset

src/main/scala/lib/param.scala

@@ -21,7 +21,7 @@ trait param {
   val BTB_INDEX3_HI          = 	0x19
   val BTB_INDEX3_LO          = 	0x12
   val BTB_SIZE               = 	0x200
-  val BUILD_AHB_LITE         = 	0x0
+  val BUILD_AHB_LITE         = 	0x1
   val BUILD_AXI4             = 	0x0
   val BUILD_AXI_NATIVE       = 	0x1
   val BUS_PRTY_DEFAULT       = 	0x3

target/streams/_global/_global/checkBuildSources/_global/streams/out

@@ -1 +1 @@
-[debug] Checking for meta build source updates
+[debug] Checking for meta build source updates

target/streams/compile/_global/_global/compileSourceFileInputs/previous

@@ -1 +1 @@
-["sbt.Task[scala.collection.immutable.Map[java.lang.String, scala.collection.Seq[scala.Tuple2[java.nio.file.Path, sbt.nio.FileStamp]]]]",{"2.12.10":{"hashes":[["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/mem.scala","e9418660ac1519eea2058bbd87d585d5d47343f0"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/quasar.scala","503f063a2675efdbfb57a502a4fa60dea15b9331"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/dma_ctrl.scala","f24faa32ddf3bf63a73061d9d24e5c00058f3d2b"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/quasar_wrapper.scala","f3dd5c2431ee23c1b5b158754bdad765cc909ba9"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/pic_ctrl.scala","6e8e5a15a1d60123a4f55018ef9caede35deeeb1"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu_ifc_ctl.scala","a2fdfc7178e808f4bbb358784e7aa677d7fde3b6"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu_aln_ctl.scala","a66e9f0672f75f5a3288a7362ed7976e9d4048d0"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu_bp_ctl.scala","474eec82140152f20417b6c1e4404d409f7f4a9b"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu_mem_ctl.scala","aa8a428318dab2b44f123bfe674710f400b73ff9"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu_compress_ctl.scala","3e2056149b7e8a89ba0809ff0082c71e3601820a"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu.scala","343974417ab69591d12c7d15a8bee798ad82be20"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/snapshot/el2_param.scala","9d4cedee7eee5415275809ba6f02d693324110fd"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_bus_intf.scala","a5028b217bfd6cc6fad3c8388d151e7f8fbcbe77"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_trigger.scala","9923de9bfd2f504ae2bb2b15c42a32ceaa2d5846"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu.scala","0f9289fbd8cba0253e85afd8439b7fad7f368274"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_ecc.scala","d9c545afed0cc63a9ab0b880ec36abca3e7fb61a"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_stbuf.scala","d9284179851f33d9cd92a94f31bd327c1fdef9ac"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_dccm_ctl.scala","5168463f9c0e776c36750656998fc360fd269ab2"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_lsc_ctl.scala","191bf9cc863939ecf0cab24cdceca1b9b64223d4"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_bus_buffer.scala","415669c1df1dfb3db6b4d92e4010e4ccf4870d7e"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_addrcheck.scala","3c84af93ccb882d99b74852439d20c3b189dd518"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_clkdomain.scala","8d8d0e8ed37d5810d2b47b5762ccdb75afc7fce3"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/exu/exu.scala","013b036929ed7c9f917ba73eba950f188939743c"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/exu/exu_mul_ctl.scala","fd528764c26575f995645a109d8b55799591874c"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/exu/exu_div_ctl.scala","dc91c0c780fed1ff374122dea516b6252fca923f"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/exu/exu_alu_ctl.scala","d343e32edc9108a662b206313eaf1da425813eec"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/dbg/dbg.scala","ef5be7fa3e120fc7104f10ab2b519cca0905a566"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/lib/param.scala","6c672ea7f0e7f4522288b3fe7f476dad6908ff30"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/lib/axi4_to_ahb.scala","532968a2606c8c841ea8464c48293c06a0e069df"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/lib/lib.scala","ee1c243afb72958e00597a078bfb318805b9e8bc"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/lib/ahb_to_axi4.scala","99a4c8d332a0802d19c3c31f621b978afaf986ff"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/dmi/dmi_wrapper.scala","619171c0b49373f3aaf18f92aa659d8c05acbdfa"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/include/bundle.scala","03281ac6989dfaf67a9693a253a4aca96e04e5a1"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_trigger.scala","cb83a19d8b65a41e5dc8a61e2b4198c362c2d912"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_decode_ctl.scala","6980af1cdf70a73b9d9dc1b6bdd14d50395cc8e0"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec.scala","7c91d79f3efef190e30f1ad2346f5113c7a5598a"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_ib_ctl.scala","76e2bf13097343ace8beed76c0d1bf730db133ed"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_dec_ctl.scala","e1f606df5c404d0d829d3a680836da2d31e9197e"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_tlu_ctl.scala","95624005291940cd8a95dba6bc01a44a0fd312f7"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_gpr_ctl.scala","ef85566d41d8ca0d3781ab005c86097221e11c28"]],"lastModifiedTimes":[]}}]
+["sbt.Task[scala.collection.immutable.Map[java.lang.String, scala.collection.Seq[scala.Tuple2[java.nio.file.Path, sbt.nio.FileStamp]]]]",{"2.12.10":{"hashes":[["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/mem.scala","e9418660ac1519eea2058bbd87d585d5d47343f0"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/quasar.scala","cda24ad15d9de2a10ff5535fa4e6b0acd1245a96"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/dma_ctrl.scala","317c73a6f39d63e30b592e7261455062c6f31a0c"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/quasar_wrapper.scala","7de89776d7736202c5586c747a3886f28722a7fe"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/pic_ctrl.scala","23d46aa6c2bb3ccea125006655c103c982f1b9b1"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu_ifc_ctl.scala","58feaf508d092ed1910a9d0dfcf34bdd11f3049b"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu_aln_ctl.scala","c37fe97894075254205a512d25d660b5f15788c0"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu_bp_ctl.scala","474eec82140152f20417b6c1e4404d409f7f4a9b"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu_mem_ctl.scala","9f207697371dc1f28e50e429fe84ae24b9de4fc3"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu_compress_ctl.scala","3e2056149b7e8a89ba0809ff0082c71e3601820a"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu.scala","02c1c840ed0f45ee3b585b8da45554e11766615a"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_bus_intf.scala","f8aa1a99581dafdffe531465f6637f37d9905113"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_trigger.scala","9923de9bfd2f504ae2bb2b15c42a32ceaa2d5846"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu.scala","ab406bf532cd75335375aefb2489072385ebbc7e"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_ecc.scala","d9c545afed0cc63a9ab0b880ec36abca3e7fb61a"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_stbuf.scala","d9284179851f33d9cd92a94f31bd327c1fdef9ac"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_dccm_ctl.scala","5168463f9c0e776c36750656998fc360fd269ab2"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_lsc_ctl.scala","191bf9cc863939ecf0cab24cdceca1b9b64223d4"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_bus_buffer.scala","2f0d8e280d886bc80485e4b0341eeeb04812a552"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_addrcheck.scala","3c84af93ccb882d99b74852439d20c3b189dd518"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/lsu/lsu_clkdomain.scala","d7ca34e7d329d7eef0e2506c7a07d6911f2226bf"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/exu/exu.scala","013b036929ed7c9f917ba73eba950f188939743c"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/exu/exu_mul_ctl.scala","fd528764c26575f995645a109d8b55799591874c"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/exu/exu_div_ctl.scala","dc91c0c780fed1ff374122dea516b6252fca923f"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/exu/exu_alu_ctl.scala","369f3ac01e07eb8a2ec97049e878647a148eefef"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/dbg/dbg.scala","5ddd0ef60348a8c846f9be03f5672f1e699e4571"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/lib/param.scala","6a84cc0a74174fc9ed220355d4e478a8ba85cfcc"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/lib/axi4_to_ahb.scala","7d317f9c4391b9208baad34bef685a94deebda2e"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/lib/lib.scala","86cba6b253cea7c85f14f6816c06ee783c672dd7"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/lib/ahb_to_axi4.scala","0eb6908965b8cb41358107eae90c06a3202bb11c"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/dmi/dmi_wrapper.scala","619171c0b49373f3aaf18f92aa659d8c05acbdfa"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/include/bundle.scala","fe3fb275277cd7a9157cb234c209e23c52fe038a"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_trigger.scala","cb83a19d8b65a41e5dc8a61e2b4198c362c2d912"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_decode_ctl.scala","cb54784303a8451eea6df9648ea012ad0f2b317e"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec.scala","7c91d79f3efef190e30f1ad2346f5113c7a5598a"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_ib_ctl.scala","76e2bf13097343ace8beed76c0d1bf730db133ed"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_dec_ctl.scala","e1f606df5c404d0d829d3a680836da2d31e9197e"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_tlu_ctl.scala","cff6c4a3eecc6b3ec77c870747b620142bd9244c"],["/home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_gpr_ctl.scala","ef85566d41d8ca0d3781ab005c86097221e11c28"]],"lastModifiedTimes":[]}}]

target/streams/compile/compile/_global/streams/out

@@ -1,18 +1,6 @@
-[warn] /home/waleedbinehsan/Desktop/Quasar/src/main/scala/ifu/ifu_mem_ctl.scala:502:3: a pure expression does nothing in statement position; multiline expressions may require enclosing parentheses
+[warn] /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lib/lib.scala:25:5: match may not be exhaustive.
-[warn]   bus_ifu_bus_clk_en
-[warn]   ^
-[warn] /home/waleedbinehsan/Desktop/Quasar/src/main/scala/lib/lib.scala:8:5: match may not be exhaustive.
 [warn] It would fail on the following inputs: (0, _), (1, _), (??, _), (_, 0), (_, 1), (_, ??), (_, _)
 [warn]     (ICACHE_WAYPACK, ICACHE_ECC) match{
 [warn]     ^
-[warn] /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_tlu_ctl.scala:1751:16: comparing values of types Int and Boolean using `==' will always yield false
+[warn] there were 3745 feature warnings; re-run with -feature for details
-[warn]  if(BUILD_AXI4 == true){
+[warn] two warnings found
-[warn]                ^
-[warn] /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_tlu_ctl.scala:2122:17: comparing values of types Int and Boolean using `==' will always yield false
-[warn]  if (ICACHE_ECC == true) {
-[warn]                 ^
-[warn] /home/waleedbinehsan/Desktop/Quasar/src/main/scala/dec/dec_tlu_ctl.scala:2155:17: comparing values of types Int and Boolean using `==' will always yield false
-[warn]  if (ICACHE_ECC == true)  io.dec_tlu_ic_diag_pkt.icache_wrdata := Cat(dicad1(6,0), dicad0h(31,0), dicad0(31,0))
-[warn]                 ^
-[warn] there were 3738 feature warnings; re-run with -feature for details
-[warn] 6 warnings found

target/streams/compile/packageBin/_global/streams/inputs

@@ -1 +1 @@
--1947755211
+793527455

target/streams/compile/packageBin/_global/streams/out

@@ -32,14 +32,10 @@
 [debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/ifu/ifu_bp_ctl.class
 [debug] 	QUASAR_Wrp$.class
 [debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/QUASAR_Wrp$.class
-[debug] 	snapshot
-[debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/snapshot
-[debug] 	snapshot/pt$.class
-[debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/snapshot/pt$.class
-[debug] 	snapshot/pt.class
-[debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/snapshot/pt.class
 [debug] 	quasar_wrapper.class
 [debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/quasar_wrapper.class
+[debug] 	quasar_bundle$$anon$1.class
+[debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/quasar_bundle$$anon$1.class
 [debug] 	vsrc
 [debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/vsrc
 [debug] 	vsrc/ifu_iccm_mem.sv
@@ -160,30 +156,34 @@
 [debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lib/lib$rvclkhdr.class
 [debug] 	lib/lib$rvecc_encode.class
 [debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lib/lib$rvecc_encode.class
+[debug] 	lib/lib$gated_latch$$anon$4.class
+[debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lib/lib$gated_latch$$anon$4.class
 [debug] 	lib/Config.class
 [debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lib/Config.class
 [debug] 	lib/axi4_to_ahb_IO.class
 [debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lib/axi4_to_ahb_IO.class
-[debug] 	lib/lib$gated_latch$$anon$3.class
-[debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lib/lib$gated_latch$$anon$3.class
 [debug] 	lib/lib.class
 [debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lib/lib.class
+[debug] 	lib/lib$$anon$1.class
+[debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lib/lib$$anon$1.class
 [debug] 	lib/lib$rvecc_encode_64.class
 [debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lib/lib$rvecc_encode_64.class
 [debug] 	lib/ahb_to_axi4.class
 [debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lib/ahb_to_axi4.class
-[debug] 	lib/lib$rvecc_encode_64$$anon$2.class
+[debug] 	lib/lib$rvecc_encode_64$$anon$3.class
-[debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lib/lib$rvecc_encode_64$$anon$2.class
+[debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lib/lib$rvecc_encode_64$$anon$3.class
 [debug] 	lib/ahb_to_axi4$$anon$1.class
 [debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lib/ahb_to_axi4$$anon$1.class
 [debug] 	lib/lib$rvsyncss$.class
 [debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lib/lib$rvsyncss$.class
 [debug] 	lib/lib$gated_latch.class
 [debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lib/lib$gated_latch.class
-[debug] 	lib/lib$rvclkhdr$$anon$4.class
+[debug] 	lib/ahb_to_axi4$$anon$1$$anon$2.class
-[debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lib/lib$rvclkhdr$$anon$4.class
+[debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lib/ahb_to_axi4$$anon$1$$anon$2.class
-[debug] 	lib/lib$rvecc_encode$$anon$1.class
+[debug] 	lib/lib$rvclkhdr$$anon$5.class
-[debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lib/lib$rvecc_encode$$anon$1.class
+[debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lib/lib$rvclkhdr$$anon$5.class
+[debug] 	lib/lib$rvecc_encode$$anon$2.class
+[debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lib/lib$rvecc_encode$$anon$2.class
 [debug] 	lib/axi4_to_ahb.class
 [debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/lib/axi4_to_ahb.class
 [debug] 	lib/param.class
@@ -242,6 +242,8 @@
 [debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/lsu_error_pkt_t.class
 [debug] 	include/read_addr.class
 [debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/read_addr.class
+[debug] 	include/ahb_out_dma.class
+[debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/ahb_out_dma.class
 [debug] 	include/dest_pkt_t.class
 [debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/dest_pkt_t.class
 [debug] 	include/dbg_ib.class
@@ -254,12 +256,10 @@
 [debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/inst_pkt_t$.class
 [debug] 	include/tlu_dma.class
 [debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/tlu_dma.class
-[debug] 	include/write_addr$.class
-[debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/write_addr$.class
-[debug] 	include/write_resp$.class
-[debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/write_resp$.class
 [debug] 	include/axi_channels.class
 [debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/axi_channels.class
+[debug] 	include/ahb_out.class
+[debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/ahb_out.class
 [debug] 	include/ic_mem.class
 [debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/ic_mem.class
 [debug] 	include/write_addr.class
@@ -296,6 +296,8 @@
 [debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/dec_ifc.class
 [debug] 	include/ifu_dec.class
 [debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/ifu_dec.class
+[debug] 	include/ahb_channel.class
+[debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/ahb_channel.class
 [debug] 	include/lsu_pic.class
 [debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/lsu_pic.class
 [debug] 	include/dctl_busbuff.class
@@ -316,14 +318,14 @@
 [debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/dec_pkt_t.class
 [debug] 	include/aln_ib.class
 [debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/aln_ib.class
-[debug] 	include/read_data$.class
-[debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/read_data$.class
 [debug] 	include/cache_debug_pkt_t.class
 [debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/cache_debug_pkt_t.class
 [debug] 	include/load_cam_pkt_t.class
 [debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/load_cam_pkt_t.class
 [debug] 	include/dec_mem_ctrl.class
 [debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/dec_mem_ctrl.class
+[debug] 	include/ahb_in.class
+[debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/ahb_in.class
 [debug] 	include/axi_channels$.class
 [debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/axi_channels$.class
 [debug] 	include/ic_tag_ext_in_pkt_t.class
@@ -370,8 +372,6 @@
 [debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/alu_pkt_t.class
 [debug] 	include/rets_pkt_t.class
 [debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/rets_pkt_t.class
-[debug] 	include/read_addr$.class
-[debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/include/read_addr$.class
 [debug] 	dec
 [debug] 	  /home/waleedbinehsan/Desktop/Quasar/target/scala-2.12/classes/dec
 [debug] 	dec/dec_trigger$$anon$1.class