Quasar top done

src/main/scala/lib/param.scala

@@ -22,7 +22,7 @@ trait param {
   val BTB_INDEX3_LO          = 	0x12
   val BTB_SIZE               = 	0x200
   val BUILD_AHB_LITE         = 	0x0
-  val BUILD_AXI4             = 	0x1
+  val BUILD_AXI4             = 	0x0
   val BUILD_AXI_NATIVE       = 	0x1
   val BUS_PRTY_DEFAULT       = 	0x3
   val DATA_ACCESS_ADDR0      = 	0x00000000

src/main/scala/quasar_wrapper.scala

@@ -62,105 +62,105 @@ class quasar_wrapper extends Module with lib with RequireAsyncReset {
   })
   val mem = Module(new quasar.mem())
   val dmi_wrapper = Module(new dmi_wrapper())
-  val swerv = Module(new quasar())
-  swerv.io.scan_mode := io.scan_mode
+  val core = Module(new quasar())
+  core.io.scan_mode := io.scan_mode
   dmi_wrapper.io.trst_n := io.jtag_trst_n
   dmi_wrapper.io.tck := io.jtag_tck
   dmi_wrapper.io.tms := io.jtag_tms
   dmi_wrapper.io.tdi := io.jtag_tdi
   dmi_wrapper.io.core_clk := clock
   dmi_wrapper.io.jtag_id := io.jtag_id
-  dmi_wrapper.io.rd_data := swerv.io.dmi_reg_rdata
+  dmi_wrapper.io.rd_data := core.io.dmi_reg_rdata
 
 
   dmi_wrapper.io.core_rst_n := io.dbg_rst_l
-  swerv.io.dmi_reg_wdata := dmi_wrapper.io.reg_wr_data
-  swerv.io.dmi_reg_addr := dmi_wrapper.io.reg_wr_addr
-  swerv.io.dmi_reg_en := dmi_wrapper.io.reg_en
-  swerv.io.dmi_reg_wr_en := dmi_wrapper.io.reg_wr_en
-  swerv.io.dmi_hard_reset := dmi_wrapper.io.dmi_hard_reset
+  core.io.dmi_reg_wdata := dmi_wrapper.io.reg_wr_data
+  core.io.dmi_reg_addr := dmi_wrapper.io.reg_wr_addr
+  core.io.dmi_reg_en := dmi_wrapper.io.reg_en
+  core.io.dmi_reg_wr_en := dmi_wrapper.io.reg_wr_en
+  core.io.dmi_hard_reset := dmi_wrapper.io.dmi_hard_reset
   io.jtag_tdo := dmi_wrapper.io.tdo
 
   // Memory signals
-  mem.io.dccm_clk_override := swerv.io.dccm_clk_override
-  mem.io.icm_clk_override := swerv.io.icm_clk_override
-  mem.io.dec_tlu_core_ecc_disable := swerv.io.dec_tlu_core_ecc_disable
-  mem.io.dccm <> swerv.io.dccm
+  mem.io.dccm_clk_override := core.io.dccm_clk_override
+  mem.io.icm_clk_override := core.io.icm_clk_override
+  mem.io.dec_tlu_core_ecc_disable := core.io.dec_tlu_core_ecc_disable
+  mem.io.dccm <> core.io.dccm
   mem.io.rst_l := reset
   mem.io.clk := clock
   mem.io.scan_mode := io.scan_mode
   // Memory outputs
-  swerv.io.dbg_rst_l := io.dbg_rst_l
-  swerv.io.ic <> mem.io.ic
-  swerv.io.iccm <> mem.io.iccm
+  core.io.dbg_rst_l := io.dbg_rst_l
+  core.io.ic <> mem.io.ic
+  core.io.iccm <> mem.io.iccm
 
 
   if(BUILD_AXI4) {
-    swerv.io.ahb <> 0.U.asTypeOf(swerv.io.ahb)
-    swerv.io.lsu_ahb <> 0.U.asTypeOf(swerv.io.lsu_ahb)
-    swerv.io.sb_ahb <> 0.U.asTypeOf(swerv.io.sb_ahb)
-    swerv.io.dma.ahb <> 0.U.asTypeOf(swerv.io.dma.ahb)
-    swerv.io.dma.hsel := 0.U
-    swerv.io.dma.hreadyin := 0.U
-    swerv.io.lsu_axi <> io.lsu_brg
-    swerv.io.ifu_axi <> io.ifu_brg
-    swerv.io.sb_axi <> io.sb_brg
-    swerv.io.dma_axi <> io.dma_brg
+    core.io.ahb <> 0.U.asTypeOf(core.io.ahb)
+    core.io.lsu_ahb <> 0.U.asTypeOf(core.io.lsu_ahb)
+    core.io.sb_ahb <> 0.U.asTypeOf(core.io.sb_ahb)
+    core.io.dma.ahb <> 0.U.asTypeOf(core.io.dma.ahb)
+    core.io.dma.hsel := 0.U
+    core.io.dma.hreadyin := 0.U
+    core.io.lsu_axi <> io.lsu_brg
+    core.io.ifu_axi <> io.ifu_brg
+    core.io.sb_axi <> io.sb_brg
+    core.io.dma_axi <> io.dma_brg
   }
   else {
-    swerv.io.ahb <> io.ifu_brg
-    swerv.io.lsu_ahb <> io.lsu_brg
-    swerv.io.sb_ahb <> io.sb_brg
-    swerv.io.dma <> io.dma_brg
+    core.io.ahb <> io.ifu_brg
+    core.io.lsu_ahb <> io.lsu_brg
+    core.io.sb_ahb <> io.sb_brg
+    core.io.dma <> io.dma_brg
 
-    swerv.io.lsu_axi <> 0.U.asTypeOf(swerv.io.lsu_axi)
-    swerv.io.ifu_axi <> 0.U.asTypeOf(swerv.io.ifu_axi)
-    swerv.io.sb_axi <> 0.U.asTypeOf(swerv.io.sb_axi)
-    swerv.io.dma_axi <> 0.U.asTypeOf(swerv.io.lsu_axi)
+    core.io.lsu_axi <> 0.U.asTypeOf(core.io.lsu_axi)
+    core.io.ifu_axi <> 0.U.asTypeOf(core.io.ifu_axi)
+    core.io.sb_axi <> 0.U.asTypeOf(core.io.sb_axi)
+    core.io.dma_axi <> 0.U.asTypeOf(core.io.lsu_axi)
   }
-  // SweRV Inputs
-  swerv.io.dbg_rst_l := io.dbg_rst_l
-  swerv.io.rst_vec := io.rst_vec
-  swerv.io.nmi_int := io.nmi_int
-  swerv.io.nmi_vec := io.nmi_vec
+  // core Inputs
+  core.io.dbg_rst_l := io.dbg_rst_l
+  core.io.rst_vec := io.rst_vec
+  core.io.nmi_int := io.nmi_int
+  core.io.nmi_vec := io.nmi_vec
 
   // external halt/run interface
-  swerv.io.i_cpu_halt_req := io.i_cpu_halt_req
-  swerv.io.i_cpu_run_req := io.i_cpu_run_req
-  swerv.io.core_id := io.core_id
+  core.io.i_cpu_halt_req := io.i_cpu_halt_req
+  core.io.i_cpu_run_req := io.i_cpu_run_req
+  core.io.core_id := io.core_id
 
   // external MPC halt/run interface
-  swerv.io.mpc_debug_halt_req := io.mpc_debug_halt_req
-  swerv.io.mpc_debug_run_req := io.mpc_debug_run_req
-  swerv.io.mpc_reset_run_req := io.mpc_reset_run_req
+  core.io.mpc_debug_halt_req := io.mpc_debug_halt_req
+  core.io.mpc_debug_run_req := io.mpc_debug_run_req
+  core.io.mpc_reset_run_req := io.mpc_reset_run_req
 
-  swerv.io.lsu_bus_clk_en := io.lsu_bus_clk_en
-  swerv.io.ifu_bus_clk_en := io.ifu_bus_clk_en
-  swerv.io.dbg_bus_clk_en := io.dbg_bus_clk_en
-  swerv.io.dma_bus_clk_en := io.dma_bus_clk_en
+  core.io.lsu_bus_clk_en := io.lsu_bus_clk_en
+  core.io.ifu_bus_clk_en := io.ifu_bus_clk_en
+  core.io.dbg_bus_clk_en := io.dbg_bus_clk_en
+  core.io.dma_bus_clk_en := io.dma_bus_clk_en
 
-  swerv.io.timer_int := io.timer_int
-  swerv.io.soft_int := io.soft_int
-  swerv.io.extintsrc_req := io.extintsrc_req
+  core.io.timer_int := io.timer_int
+  core.io.soft_int := io.soft_int
+  core.io.extintsrc_req := io.extintsrc_req
 
   // Outputs
-  val core_rst_l = swerv.io.core_rst_l
-  io.rv_trace_pkt := swerv.io.rv_trace_pkt
+  val core_rst_l = core.io.core_rst_l
+  io.rv_trace_pkt := core.io.rv_trace_pkt
 
   // external halt/run interface
-  io.o_cpu_halt_ack := swerv.io.o_cpu_halt_ack
-  io.o_cpu_halt_status := swerv.io.o_cpu_halt_status
-  io.o_cpu_run_ack := swerv.io.o_cpu_run_ack
-  io.o_debug_mode_status := swerv.io.o_debug_mode_status
+  io.o_cpu_halt_ack := core.io.o_cpu_halt_ack
+  io.o_cpu_halt_status := core.io.o_cpu_halt_status
+  io.o_cpu_run_ack := core.io.o_cpu_run_ack
+  io.o_debug_mode_status := core.io.o_debug_mode_status
 
-  io.mpc_debug_halt_ack := swerv.io.mpc_debug_halt_ack
-  io.mpc_debug_run_ack := swerv.io.mpc_debug_run_ack
-  io.debug_brkpt_status := swerv.io.debug_brkpt_status
+  io.mpc_debug_halt_ack := core.io.mpc_debug_halt_ack
+  io.mpc_debug_run_ack := core.io.mpc_debug_run_ack
+  io.debug_brkpt_status := core.io.debug_brkpt_status
 
-  io.dec_tlu_perfcnt0 := swerv.io.dec_tlu_perfcnt0
-  io.dec_tlu_perfcnt1 := swerv.io.dec_tlu_perfcnt1
-  io.dec_tlu_perfcnt2 := swerv.io.dec_tlu_perfcnt2
-  io.dec_tlu_perfcnt3 := swerv.io.dec_tlu_perfcnt3
+  io.dec_tlu_perfcnt0 := core.io.dec_tlu_perfcnt0
+  io.dec_tlu_perfcnt1 := core.io.dec_tlu_perfcnt1
+  io.dec_tlu_perfcnt2 := core.io.dec_tlu_perfcnt2
+  io.dec_tlu_perfcnt3 := core.io.dec_tlu_perfcnt3
 
 }
 object QUASAR_Wrp extends App {