IFC updated
This commit is contained in:
Laraib Khan
parent
ce64b77952
commit
5ac08982de
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@ -0,0 +1,122 @@
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[
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~ifu_ifc_ctl|ifu_ifc_ctl>io_ifc_dma_access_ok",
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"sources":[
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"~ifu_ifc_ctl|ifu_ifc_ctl>io_exu_flush_final",
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"~ifu_ifc_ctl|ifu_ifc_ctl>io_ifc_iccm_access_bf",
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"~ifu_ifc_ctl|ifu_ifc_ctl>io_ifc_fetch_req_bf",
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"~ifu_ifc_ctl|ifu_ifc_ctl>io_ifu_fb_consume2",
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"~ifu_ifc_ctl|ifu_ifc_ctl>io_ifu_fb_consume1",
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"~ifu_ifc_ctl|ifu_ifc_ctl>io_dec_ifc_dec_tlu_flush_noredir_wb",
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"~ifu_ifc_ctl|ifu_ifc_ctl>io_ifc_fetch_addr_bf",
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"~ifu_ifc_ctl|ifu_ifc_ctl>io_ic_write_stall",
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"~ifu_ifc_ctl|ifu_ifc_ctl>io_ifc_fetch_req_bf_raw",
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"~ifu_ifc_ctl|ifu_ifc_ctl>io_ic_dma_active",
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"~ifu_ifc_ctl|ifu_ifc_ctl>io_ifu_bp_btb_target_f",
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"~ifu_ifc_ctl|ifu_ifc_ctl>io_exu_flush_path_final",
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"~ifu_ifc_ctl|ifu_ifc_ctl>io_ifc_fetch_addr_f",
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"~ifu_ifc_ctl|ifu_ifc_ctl>io_ic_hit_f",
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"~ifu_ifc_ctl|ifu_ifc_ctl>io_ifu_bp_hit_taken_f",
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"~ifu_ifc_ctl|ifu_ifc_ctl>io_ifc_fetch_req_f"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~ifu_ifc_ctl|ifu_ifc_ctl>io_dec_ifc_ifu_pmu_fetch_stall",
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"sources":[
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"~ifu_ifc_ctl|ifu_ifc_ctl>io_ifc_fetch_req_bf_raw",
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"~ifu_ifc_ctl|ifu_ifc_ctl>io_ic_dma_active",
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"~ifu_ifc_ctl|ifu_ifc_ctl>io_exu_flush_final",
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"~ifu_ifc_ctl|ifu_ifc_ctl>io_ifu_fb_consume2",
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"~ifu_ifc_ctl|ifu_ifc_ctl>io_ifu_fb_consume1"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~ifu_ifc_ctl|ifu_ifc_ctl>io_ifc_fetch_req_bf",
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"sources":[
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"~ifu_ifc_ctl|ifu_ifc_ctl>io_dec_ifc_dec_tlu_flush_noredir_wb",
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"~ifu_ifc_ctl|ifu_ifc_ctl>io_ic_write_stall",
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"~ifu_ifc_ctl|ifu_ifc_ctl>io_ifc_fetch_req_bf_raw",
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"~ifu_ifc_ctl|ifu_ifc_ctl>io_ic_dma_active",
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"~ifu_ifc_ctl|ifu_ifc_ctl>io_ifu_fb_consume2",
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"~ifu_ifc_ctl|ifu_ifc_ctl>io_ifu_fb_consume1",
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"~ifu_ifc_ctl|ifu_ifc_ctl>io_exu_flush_final",
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"~ifu_ifc_ctl|ifu_ifc_ctl>io_ifc_fetch_req_f",
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"~ifu_ifc_ctl|ifu_ifc_ctl>io_ic_hit_f"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~ifu_ifc_ctl|ifu_ifc_ctl>io_ifc_fetch_addr_bf",
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"sources":[
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"~ifu_ifc_ctl|ifu_ifc_ctl>io_ifu_bp_btb_target_f",
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"~ifu_ifc_ctl|ifu_ifc_ctl>io_exu_flush_path_final",
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"~ifu_ifc_ctl|ifu_ifc_ctl>io_ifc_fetch_addr_f",
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"~ifu_ifc_ctl|ifu_ifc_ctl>io_ic_hit_f",
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"~ifu_ifc_ctl|ifu_ifc_ctl>io_exu_flush_final",
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"~ifu_ifc_ctl|ifu_ifc_ctl>io_ifu_bp_hit_taken_f",
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"~ifu_ifc_ctl|ifu_ifc_ctl>io_ifc_fetch_req_f"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~ifu_ifc_ctl|ifu_ifc_ctl>io_ifc_iccm_access_bf",
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"sources":[
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"~ifu_ifc_ctl|ifu_ifc_ctl>io_ifc_fetch_addr_bf",
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"~ifu_ifc_ctl|ifu_ifc_ctl>io_ifu_bp_btb_target_f",
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"~ifu_ifc_ctl|ifu_ifc_ctl>io_exu_flush_path_final",
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"~ifu_ifc_ctl|ifu_ifc_ctl>io_ifc_fetch_addr_f",
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"~ifu_ifc_ctl|ifu_ifc_ctl>io_ic_hit_f",
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"~ifu_ifc_ctl|ifu_ifc_ctl>io_exu_flush_final",
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"~ifu_ifc_ctl|ifu_ifc_ctl>io_ifu_bp_hit_taken_f",
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"~ifu_ifc_ctl|ifu_ifc_ctl>io_ifc_fetch_req_f"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~ifu_ifc_ctl|ifu_ifc_ctl>io_ifc_fetch_uncacheable_bf",
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"sources":[
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"~ifu_ifc_ctl|ifu_ifc_ctl>io_dec_ifc_dec_tlu_mrac_ff",
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"~ifu_ifc_ctl|ifu_ifc_ctl>io_ifc_fetch_addr_bf",
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"~ifu_ifc_ctl|ifu_ifc_ctl>io_ifu_bp_btb_target_f",
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"~ifu_ifc_ctl|ifu_ifc_ctl>io_exu_flush_path_final",
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"~ifu_ifc_ctl|ifu_ifc_ctl>io_ifc_fetch_addr_f",
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"~ifu_ifc_ctl|ifu_ifc_ctl>io_ic_hit_f",
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"~ifu_ifc_ctl|ifu_ifc_ctl>io_exu_flush_final",
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"~ifu_ifc_ctl|ifu_ifc_ctl>io_ifu_bp_hit_taken_f",
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"~ifu_ifc_ctl|ifu_ifc_ctl>io_ifc_fetch_req_f"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~ifu_ifc_ctl|ifu_ifc_ctl>io_ifc_region_acc_fault_bf",
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"sources":[
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"~ifu_ifc_ctl|ifu_ifc_ctl>io_ifc_fetch_addr_bf",
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"~ifu_ifc_ctl|ifu_ifc_ctl>io_ifu_bp_btb_target_f",
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"~ifu_ifc_ctl|ifu_ifc_ctl>io_exu_flush_path_final",
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"~ifu_ifc_ctl|ifu_ifc_ctl>io_ifc_fetch_addr_f",
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"~ifu_ifc_ctl|ifu_ifc_ctl>io_ic_hit_f",
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"~ifu_ifc_ctl|ifu_ifc_ctl>io_exu_flush_final",
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"~ifu_ifc_ctl|ifu_ifc_ctl>io_ifu_bp_hit_taken_f",
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"~ifu_ifc_ctl|ifu_ifc_ctl>io_ifc_fetch_req_f"
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]
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},
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{
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"class":"firrtl.EmitCircuitAnnotation",
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"emitter":"firrtl.VerilogEmitter"
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},
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{
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"class":"firrtl.options.TargetDirAnnotation",
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"directory":"."
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},
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{
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"class":"firrtl.options.OutputAnnotationFileAnnotation",
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"file":"ifu_ifc_ctl"
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},
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{
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"class":"firrtl.transforms.BlackBoxTargetDirAnno",
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"targetDir":"."
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}
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]
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@ -0,0 +1,311 @@
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;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
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circuit ifu_ifc_ctl :
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module ifu_ifc_ctl :
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input clock : Clock
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input reset : AsyncReset
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output io : {flip exu_flush_final : UInt<1>, flip exu_flush_path_final : UInt<31>, flip free_l2clk : Clock, flip scan_mode : UInt<1>, flip ic_hit_f : UInt<1>, flip ifu_ic_mb_empty : UInt<1>, flip ifu_fb_consume1 : UInt<1>, flip ifu_fb_consume2 : UInt<1>, flip ifu_bp_hit_taken_f : UInt<1>, flip ifu_bp_btb_target_f : UInt<31>, flip ic_dma_active : UInt<1>, flip ic_write_stall : UInt<1>, dec_ifc : {flip dec_tlu_flush_noredir_wb : UInt<1>, flip dec_tlu_mrac_ff : UInt<32>, ifu_pmu_fetch_stall : UInt<1>}, dma_ifc : {flip dma_iccm_stall_any : UInt<1>}, ifc_fetch_addr_f : UInt<31>, ifc_fetch_addr_bf : UInt<31>, ifc_fetch_req_f : UInt<1>, ifc_fetch_uncacheable_bf : UInt<1>, ifc_fetch_req_bf : UInt<1>, ifc_fetch_req_bf_raw : UInt<1>, ifc_iccm_access_bf : UInt<1>, ifc_region_acc_fault_bf : UInt<1>, ifc_dma_access_ok : UInt<1>}
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wire fetch_addr_bf : UInt<31>
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fetch_addr_bf <= UInt<1>("h00")
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wire fetch_addr_next_0 : UInt<1>
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fetch_addr_next_0 <= UInt<1>("h00")
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wire fetch_addr_next : UInt<31>
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fetch_addr_next <= UInt<1>("h00")
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wire fb_write_ns : UInt<4>
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fb_write_ns <= UInt<1>("h00")
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wire fb_write_f : UInt<4>
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fb_write_f <= UInt<1>("h00")
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wire fb_full_f_ns : UInt<1>
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fb_full_f_ns <= UInt<1>("h00")
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wire fb_right : UInt<1>
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fb_right <= UInt<1>("h00")
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wire fb_right2 : UInt<1>
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fb_right2 <= UInt<1>("h00")
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wire fb_left : UInt<1>
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fb_left <= UInt<1>("h00")
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wire wfm : UInt<1>
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wfm <= UInt<1>("h00")
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wire idle : UInt<1>
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idle <= UInt<1>("h00")
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wire miss_f : UInt<1>
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miss_f <= UInt<1>("h00")
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wire miss_a : UInt<1>
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miss_a <= UInt<1>("h00")
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wire flush_fb : UInt<1>
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flush_fb <= UInt<1>("h00")
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wire mb_empty_mod : UInt<1>
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mb_empty_mod <= UInt<1>("h00")
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wire goto_idle : UInt<1>
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goto_idle <= UInt<1>("h00")
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wire leave_idle : UInt<1>
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leave_idle <= UInt<1>("h00")
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wire fetch_bf_en : UInt<1>
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fetch_bf_en <= UInt<1>("h00")
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wire line_wrap : UInt<1>
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line_wrap <= UInt<1>("h00")
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wire state : UInt<2>
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state <= UInt<1>("h00")
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wire dma_iccm_stall_any_f : UInt<1>
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dma_iccm_stall_any_f <= UInt<1>("h00")
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node dma_stall = or(io.ic_dma_active, dma_iccm_stall_any_f) @[ifu_ifc_ctl.scala 62:36]
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wire _T : UInt<1>
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_T <= UInt<1>("h00")
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node _T_1 = xor(io.dma_ifc.dma_iccm_stall_any, _T) @[lib.scala 458:21]
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node _T_2 = orr(_T_1) @[lib.scala 458:29]
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reg _T_3 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
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when _T_2 : @[Reg.scala 28:19]
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_T_3 <= io.dma_ifc.dma_iccm_stall_any @[Reg.scala 28:23]
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skip @[Reg.scala 28:19]
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_T <= _T_3 @[lib.scala 461:16]
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dma_iccm_stall_any_f <= _T @[ifu_ifc_ctl.scala 64:24]
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wire _T_4 : UInt
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_T_4 <= UInt<1>("h00")
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node _T_5 = xor(miss_f, _T_4) @[lib.scala 436:21]
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node _T_6 = orr(_T_5) @[lib.scala 436:29]
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reg _T_7 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
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when _T_6 : @[Reg.scala 28:19]
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_T_7 <= miss_f @[Reg.scala 28:23]
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skip @[Reg.scala 28:19]
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_T_4 <= _T_7 @[lib.scala 439:16]
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miss_a <= _T_4 @[ifu_ifc_ctl.scala 65:10]
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node _T_8 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_ifc_ctl.scala 67:30]
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node _T_9 = eq(io.ifc_fetch_req_f, UInt<1>("h00")) @[ifu_ifc_ctl.scala 67:53]
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node _T_10 = eq(io.ic_hit_f, UInt<1>("h00")) @[ifu_ifc_ctl.scala 67:75]
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node _T_11 = or(_T_9, _T_10) @[ifu_ifc_ctl.scala 67:73]
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node _T_12 = and(_T_8, _T_11) @[ifu_ifc_ctl.scala 67:50]
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node _T_13 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_ifc_ctl.scala 68:29]
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node _T_14 = and(_T_13, io.ifc_fetch_req_f) @[ifu_ifc_ctl.scala 68:49]
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node _T_15 = and(_T_14, io.ifu_bp_hit_taken_f) @[ifu_ifc_ctl.scala 68:70]
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node _T_16 = and(_T_15, io.ic_hit_f) @[ifu_ifc_ctl.scala 68:94]
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node _T_17 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_ifc_ctl.scala 69:30]
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node _T_18 = and(_T_17, io.ifc_fetch_req_f) @[ifu_ifc_ctl.scala 69:50]
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node _T_19 = eq(io.ifu_bp_hit_taken_f, UInt<1>("h00")) @[ifu_ifc_ctl.scala 69:73]
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node _T_20 = and(_T_18, _T_19) @[ifu_ifc_ctl.scala 69:71]
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node _T_21 = and(_T_20, io.ic_hit_f) @[ifu_ifc_ctl.scala 69:96]
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node _T_22 = bits(io.exu_flush_final, 0, 0) @[ifu_ifc_ctl.scala 71:57]
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node _T_23 = bits(_T_12, 0, 0) @[ifu_ifc_ctl.scala 72:23]
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node _T_24 = bits(_T_16, 0, 0) @[ifu_ifc_ctl.scala 73:22]
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node _T_25 = bits(_T_21, 0, 0) @[ifu_ifc_ctl.scala 74:23]
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node _T_26 = mux(_T_22, io.exu_flush_path_final, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_27 = mux(_T_23, io.ifc_fetch_addr_f, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_28 = mux(_T_24, io.ifu_bp_btb_target_f, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_29 = mux(_T_25, fetch_addr_next, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_30 = or(_T_26, _T_27) @[Mux.scala 27:72]
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node _T_31 = or(_T_30, _T_28) @[Mux.scala 27:72]
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node _T_32 = or(_T_31, _T_29) @[Mux.scala 27:72]
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wire _T_33 : UInt<31> @[Mux.scala 27:72]
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_T_33 <= _T_32 @[Mux.scala 27:72]
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io.ifc_fetch_addr_bf <= _T_33 @[ifu_ifc_ctl.scala 71:25]
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node _T_34 = bits(io.ifc_fetch_addr_f, 30, 1) @[ifu_ifc_ctl.scala 84:42]
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node _T_35 = add(_T_34, UInt<1>("h01")) @[ifu_ifc_ctl.scala 84:48]
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node address_upper = tail(_T_35, 1) @[ifu_ifc_ctl.scala 84:48]
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node _T_36 = bits(address_upper, 4, 4) @[ifu_ifc_ctl.scala 85:39]
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node _T_37 = bits(io.ifc_fetch_addr_f, 5, 5) @[ifu_ifc_ctl.scala 85:84]
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node _T_38 = xor(_T_36, _T_37) @[ifu_ifc_ctl.scala 85:63]
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node _T_39 = eq(_T_38, UInt<1>("h00")) @[ifu_ifc_ctl.scala 85:24]
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node _T_40 = bits(io.ifc_fetch_addr_f, 0, 0) @[ifu_ifc_ctl.scala 85:130]
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node _T_41 = and(_T_39, _T_40) @[ifu_ifc_ctl.scala 85:109]
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fetch_addr_next_0 <= _T_41 @[ifu_ifc_ctl.scala 85:21]
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node _T_42 = cat(address_upper, fetch_addr_next_0) @[Cat.scala 29:58]
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fetch_addr_next <= _T_42 @[ifu_ifc_ctl.scala 88:19]
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node _T_43 = not(idle) @[ifu_ifc_ctl.scala 90:30]
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io.ifc_fetch_req_bf_raw <= _T_43 @[ifu_ifc_ctl.scala 90:27]
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node _T_44 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[ifu_ifc_ctl.scala 92:91]
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node _T_45 = eq(_T_44, UInt<1>("h00")) @[ifu_ifc_ctl.scala 92:70]
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node _T_46 = and(fb_full_f_ns, _T_45) @[ifu_ifc_ctl.scala 92:68]
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node _T_47 = eq(_T_46, UInt<1>("h00")) @[ifu_ifc_ctl.scala 92:53]
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node _T_48 = and(io.ifc_fetch_req_bf_raw, _T_47) @[ifu_ifc_ctl.scala 92:51]
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node _T_49 = eq(dma_stall, UInt<1>("h00")) @[ifu_ifc_ctl.scala 93:5]
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node _T_50 = and(_T_48, _T_49) @[ifu_ifc_ctl.scala 92:114]
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node _T_51 = eq(io.ic_write_stall, UInt<1>("h00")) @[ifu_ifc_ctl.scala 93:18]
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node _T_52 = and(_T_50, _T_51) @[ifu_ifc_ctl.scala 93:16]
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node _T_53 = eq(io.dec_ifc.dec_tlu_flush_noredir_wb, UInt<1>("h00")) @[ifu_ifc_ctl.scala 93:39]
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node _T_54 = and(_T_52, _T_53) @[ifu_ifc_ctl.scala 93:37]
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io.ifc_fetch_req_bf <= _T_54 @[ifu_ifc_ctl.scala 92:23]
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node _T_55 = or(io.exu_flush_final, io.ifc_fetch_req_f) @[ifu_ifc_ctl.scala 95:37]
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fetch_bf_en <= _T_55 @[ifu_ifc_ctl.scala 95:15]
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node _T_56 = eq(io.ic_hit_f, UInt<1>("h00")) @[ifu_ifc_ctl.scala 97:34]
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node _T_57 = and(io.ifc_fetch_req_f, _T_56) @[ifu_ifc_ctl.scala 97:32]
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node _T_58 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_ifc_ctl.scala 97:49]
|
||||
node _T_59 = and(_T_57, _T_58) @[ifu_ifc_ctl.scala 97:47]
|
||||
miss_f <= _T_59 @[ifu_ifc_ctl.scala 97:10]
|
||||
node _T_60 = or(io.ifu_ic_mb_empty, io.exu_flush_final) @[ifu_ifc_ctl.scala 99:39]
|
||||
node _T_61 = eq(dma_stall, UInt<1>("h00")) @[ifu_ifc_ctl.scala 99:63]
|
||||
node _T_62 = and(_T_60, _T_61) @[ifu_ifc_ctl.scala 99:61]
|
||||
node _T_63 = eq(miss_f, UInt<1>("h00")) @[ifu_ifc_ctl.scala 99:76]
|
||||
node _T_64 = and(_T_62, _T_63) @[ifu_ifc_ctl.scala 99:74]
|
||||
node _T_65 = eq(miss_a, UInt<1>("h00")) @[ifu_ifc_ctl.scala 99:86]
|
||||
node _T_66 = and(_T_64, _T_65) @[ifu_ifc_ctl.scala 99:84]
|
||||
mb_empty_mod <= _T_66 @[ifu_ifc_ctl.scala 99:16]
|
||||
node _T_67 = and(io.exu_flush_final, io.dec_ifc.dec_tlu_flush_noredir_wb) @[ifu_ifc_ctl.scala 101:35]
|
||||
goto_idle <= _T_67 @[ifu_ifc_ctl.scala 101:13]
|
||||
node _T_68 = eq(io.dec_ifc.dec_tlu_flush_noredir_wb, UInt<1>("h00")) @[ifu_ifc_ctl.scala 103:38]
|
||||
node _T_69 = and(io.exu_flush_final, _T_68) @[ifu_ifc_ctl.scala 103:36]
|
||||
node _T_70 = and(_T_69, idle) @[ifu_ifc_ctl.scala 103:75]
|
||||
leave_idle <= _T_70 @[ifu_ifc_ctl.scala 103:14]
|
||||
node _T_71 = bits(state, 1, 1) @[ifu_ifc_ctl.scala 105:29]
|
||||
node _T_72 = eq(_T_71, UInt<1>("h00")) @[ifu_ifc_ctl.scala 105:23]
|
||||
node _T_73 = bits(state, 0, 0) @[ifu_ifc_ctl.scala 105:40]
|
||||
node _T_74 = and(_T_72, _T_73) @[ifu_ifc_ctl.scala 105:33]
|
||||
node _T_75 = and(_T_74, miss_f) @[ifu_ifc_ctl.scala 105:44]
|
||||
node _T_76 = eq(goto_idle, UInt<1>("h00")) @[ifu_ifc_ctl.scala 105:55]
|
||||
node _T_77 = and(_T_75, _T_76) @[ifu_ifc_ctl.scala 105:53]
|
||||
node _T_78 = bits(state, 1, 1) @[ifu_ifc_ctl.scala 106:11]
|
||||
node _T_79 = eq(mb_empty_mod, UInt<1>("h00")) @[ifu_ifc_ctl.scala 106:17]
|
||||
node _T_80 = and(_T_78, _T_79) @[ifu_ifc_ctl.scala 106:15]
|
||||
node _T_81 = eq(goto_idle, UInt<1>("h00")) @[ifu_ifc_ctl.scala 106:33]
|
||||
node _T_82 = and(_T_80, _T_81) @[ifu_ifc_ctl.scala 106:31]
|
||||
node next_state_1 = or(_T_77, _T_82) @[ifu_ifc_ctl.scala 105:67]
|
||||
node _T_83 = eq(goto_idle, UInt<1>("h00")) @[ifu_ifc_ctl.scala 108:23]
|
||||
node _T_84 = and(_T_83, leave_idle) @[ifu_ifc_ctl.scala 108:34]
|
||||
node _T_85 = bits(state, 0, 0) @[ifu_ifc_ctl.scala 108:56]
|
||||
node _T_86 = eq(goto_idle, UInt<1>("h00")) @[ifu_ifc_ctl.scala 108:62]
|
||||
node _T_87 = and(_T_85, _T_86) @[ifu_ifc_ctl.scala 108:60]
|
||||
node next_state_0 = or(_T_84, _T_87) @[ifu_ifc_ctl.scala 108:48]
|
||||
node _T_88 = cat(next_state_1, next_state_0) @[Cat.scala 29:58]
|
||||
wire _T_89 : UInt
|
||||
_T_89 <= UInt<1>("h00")
|
||||
node _T_90 = xor(_T_88, _T_89) @[lib.scala 436:21]
|
||||
node _T_91 = orr(_T_90) @[lib.scala 436:29]
|
||||
reg _T_92 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when _T_91 : @[Reg.scala 28:19]
|
||||
_T_92 <= _T_88 @[Reg.scala 28:23]
|
||||
skip @[Reg.scala 28:19]
|
||||
_T_89 <= _T_92 @[lib.scala 439:16]
|
||||
state <= _T_89 @[ifu_ifc_ctl.scala 110:9]
|
||||
flush_fb <= io.exu_flush_final @[ifu_ifc_ctl.scala 112:12]
|
||||
node _T_93 = eq(io.ifu_fb_consume2, UInt<1>("h00")) @[ifu_ifc_ctl.scala 115:38]
|
||||
node _T_94 = and(io.ifu_fb_consume1, _T_93) @[ifu_ifc_ctl.scala 115:36]
|
||||
node _T_95 = eq(io.ifc_fetch_req_f, UInt<1>("h00")) @[ifu_ifc_ctl.scala 115:61]
|
||||
node _T_96 = or(_T_95, miss_f) @[ifu_ifc_ctl.scala 115:81]
|
||||
node _T_97 = and(_T_94, _T_96) @[ifu_ifc_ctl.scala 115:58]
|
||||
node _T_98 = and(io.ifu_fb_consume2, io.ifc_fetch_req_f) @[ifu_ifc_ctl.scala 116:25]
|
||||
node _T_99 = or(_T_97, _T_98) @[ifu_ifc_ctl.scala 115:92]
|
||||
fb_right <= _T_99 @[ifu_ifc_ctl.scala 115:12]
|
||||
node _T_100 = not(io.ifc_fetch_req_f) @[ifu_ifc_ctl.scala 118:39]
|
||||
node _T_101 = or(_T_100, miss_f) @[ifu_ifc_ctl.scala 118:59]
|
||||
node _T_102 = and(io.ifu_fb_consume2, _T_101) @[ifu_ifc_ctl.scala 118:36]
|
||||
fb_right2 <= _T_102 @[ifu_ifc_ctl.scala 118:13]
|
||||
node _T_103 = or(io.ifu_fb_consume1, io.ifu_fb_consume2) @[ifu_ifc_ctl.scala 119:56]
|
||||
node _T_104 = eq(_T_103, UInt<1>("h00")) @[ifu_ifc_ctl.scala 119:35]
|
||||
node _T_105 = and(io.ifc_fetch_req_f, _T_104) @[ifu_ifc_ctl.scala 119:33]
|
||||
node _T_106 = eq(miss_f, UInt<1>("h00")) @[ifu_ifc_ctl.scala 119:80]
|
||||
node _T_107 = and(_T_105, _T_106) @[ifu_ifc_ctl.scala 119:78]
|
||||
fb_left <= _T_107 @[ifu_ifc_ctl.scala 119:11]
|
||||
node _T_108 = bits(flush_fb, 0, 0) @[ifu_ifc_ctl.scala 122:37]
|
||||
node _T_109 = eq(flush_fb, UInt<1>("h00")) @[ifu_ifc_ctl.scala 123:6]
|
||||
node _T_110 = and(_T_109, fb_right) @[ifu_ifc_ctl.scala 123:16]
|
||||
node _T_111 = bits(_T_110, 0, 0) @[ifu_ifc_ctl.scala 123:28]
|
||||
node _T_112 = bits(fb_write_f, 3, 1) @[ifu_ifc_ctl.scala 123:62]
|
||||
node _T_113 = cat(UInt<1>("h00"), _T_112) @[Cat.scala 29:58]
|
||||
node _T_114 = eq(flush_fb, UInt<1>("h00")) @[ifu_ifc_ctl.scala 124:6]
|
||||
node _T_115 = and(_T_114, fb_right2) @[ifu_ifc_ctl.scala 124:16]
|
||||
node _T_116 = bits(_T_115, 0, 0) @[ifu_ifc_ctl.scala 124:29]
|
||||
node _T_117 = bits(fb_write_f, 3, 2) @[ifu_ifc_ctl.scala 124:63]
|
||||
node _T_118 = cat(UInt<2>("h00"), _T_117) @[Cat.scala 29:58]
|
||||
node _T_119 = eq(flush_fb, UInt<1>("h00")) @[ifu_ifc_ctl.scala 125:6]
|
||||
node _T_120 = and(_T_119, fb_left) @[ifu_ifc_ctl.scala 125:16]
|
||||
node _T_121 = bits(_T_120, 0, 0) @[ifu_ifc_ctl.scala 125:27]
|
||||
node _T_122 = bits(fb_write_f, 2, 0) @[ifu_ifc_ctl.scala 125:51]
|
||||
node _T_123 = cat(_T_122, UInt<1>("h00")) @[Cat.scala 29:58]
|
||||
node _T_124 = eq(flush_fb, UInt<1>("h00")) @[ifu_ifc_ctl.scala 126:6]
|
||||
node _T_125 = eq(fb_right, UInt<1>("h00")) @[ifu_ifc_ctl.scala 126:18]
|
||||
node _T_126 = and(_T_124, _T_125) @[ifu_ifc_ctl.scala 126:16]
|
||||
node _T_127 = eq(fb_right2, UInt<1>("h00")) @[ifu_ifc_ctl.scala 126:30]
|
||||
node _T_128 = and(_T_126, _T_127) @[ifu_ifc_ctl.scala 126:28]
|
||||
node _T_129 = eq(fb_left, UInt<1>("h00")) @[ifu_ifc_ctl.scala 126:43]
|
||||
node _T_130 = and(_T_128, _T_129) @[ifu_ifc_ctl.scala 126:41]
|
||||
node _T_131 = bits(_T_130, 0, 0) @[ifu_ifc_ctl.scala 126:53]
|
||||
node _T_132 = bits(fb_write_f, 3, 0) @[ifu_ifc_ctl.scala 126:73]
|
||||
node _T_133 = mux(_T_108, UInt<4>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_134 = mux(_T_111, _T_113, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_135 = mux(_T_116, _T_118, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_136 = mux(_T_121, _T_123, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_137 = mux(_T_131, _T_132, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_138 = or(_T_133, _T_134) @[Mux.scala 27:72]
|
||||
node _T_139 = or(_T_138, _T_135) @[Mux.scala 27:72]
|
||||
node _T_140 = or(_T_139, _T_136) @[Mux.scala 27:72]
|
||||
node _T_141 = or(_T_140, _T_137) @[Mux.scala 27:72]
|
||||
wire _T_142 : UInt<4> @[Mux.scala 27:72]
|
||||
_T_142 <= _T_141 @[Mux.scala 27:72]
|
||||
fb_write_ns <= _T_142 @[ifu_ifc_ctl.scala 122:15]
|
||||
node _T_143 = eq(state, UInt<2>("h00")) @[ifu_ifc_ctl.scala 129:17]
|
||||
idle <= _T_143 @[ifu_ifc_ctl.scala 129:8]
|
||||
node _T_144 = eq(state, UInt<2>("h03")) @[ifu_ifc_ctl.scala 130:16]
|
||||
wfm <= _T_144 @[ifu_ifc_ctl.scala 130:7]
|
||||
node _T_145 = bits(fb_write_ns, 3, 3) @[ifu_ifc_ctl.scala 132:30]
|
||||
fb_full_f_ns <= _T_145 @[ifu_ifc_ctl.scala 132:16]
|
||||
wire fb_full_f : UInt
|
||||
fb_full_f <= UInt<1>("h00")
|
||||
node _T_146 = xor(fb_full_f_ns, fb_full_f) @[lib.scala 436:21]
|
||||
node _T_147 = orr(_T_146) @[lib.scala 436:29]
|
||||
reg _T_148 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when _T_147 : @[Reg.scala 28:19]
|
||||
_T_148 <= fb_full_f_ns @[Reg.scala 28:23]
|
||||
skip @[Reg.scala 28:19]
|
||||
fb_full_f <= _T_148 @[lib.scala 439:16]
|
||||
wire _T_149 : UInt
|
||||
_T_149 <= UInt<1>("h00")
|
||||
node _T_150 = xor(fb_write_ns, _T_149) @[lib.scala 436:21]
|
||||
node _T_151 = orr(_T_150) @[lib.scala 436:29]
|
||||
reg _T_152 : UInt, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when _T_151 : @[Reg.scala 28:19]
|
||||
_T_152 <= fb_write_ns @[Reg.scala 28:23]
|
||||
skip @[Reg.scala 28:19]
|
||||
_T_149 <= _T_152 @[lib.scala 439:16]
|
||||
fb_write_f <= _T_149 @[ifu_ifc_ctl.scala 134:16]
|
||||
node _T_153 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[ifu_ifc_ctl.scala 137:40]
|
||||
node _T_154 = or(_T_153, io.exu_flush_final) @[ifu_ifc_ctl.scala 137:61]
|
||||
node _T_155 = eq(_T_154, UInt<1>("h00")) @[ifu_ifc_ctl.scala 137:19]
|
||||
node _T_156 = and(fb_full_f, _T_155) @[ifu_ifc_ctl.scala 137:17]
|
||||
node _T_157 = or(_T_156, dma_stall) @[ifu_ifc_ctl.scala 137:84]
|
||||
node _T_158 = and(io.ifc_fetch_req_bf_raw, _T_157) @[ifu_ifc_ctl.scala 136:68]
|
||||
node _T_159 = or(wfm, _T_158) @[ifu_ifc_ctl.scala 136:41]
|
||||
io.dec_ifc.ifu_pmu_fetch_stall <= _T_159 @[ifu_ifc_ctl.scala 136:34]
|
||||
node _T_160 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58]
|
||||
node _T_161 = bits(_T_160, 31, 28) @[lib.scala 84:25]
|
||||
node iccm_acc_in_region_bf = eq(_T_161, UInt<4>("h0e")) @[lib.scala 84:47]
|
||||
node _T_162 = bits(_T_160, 31, 16) @[lib.scala 87:14]
|
||||
node iccm_acc_in_range_bf = eq(_T_162, UInt<16>("h0ee00")) @[lib.scala 87:29]
|
||||
io.ifc_iccm_access_bf <= iccm_acc_in_range_bf @[ifu_ifc_ctl.scala 142:25]
|
||||
node _T_163 = eq(io.ifc_iccm_access_bf, UInt<1>("h00")) @[ifu_ifc_ctl.scala 143:30]
|
||||
node _T_164 = or(io.ifu_fb_consume2, io.ifu_fb_consume1) @[ifu_ifc_ctl.scala 144:39]
|
||||
node _T_165 = eq(_T_164, UInt<1>("h00")) @[ifu_ifc_ctl.scala 144:18]
|
||||
node _T_166 = and(fb_full_f, _T_165) @[ifu_ifc_ctl.scala 144:16]
|
||||
node _T_167 = or(_T_163, _T_166) @[ifu_ifc_ctl.scala 143:53]
|
||||
node _T_168 = eq(io.ifc_fetch_req_bf, UInt<1>("h00")) @[ifu_ifc_ctl.scala 145:13]
|
||||
node _T_169 = and(wfm, _T_168) @[ifu_ifc_ctl.scala 145:11]
|
||||
node _T_170 = or(_T_167, _T_169) @[ifu_ifc_ctl.scala 144:62]
|
||||
node _T_171 = or(_T_170, idle) @[ifu_ifc_ctl.scala 145:35]
|
||||
node _T_172 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_ifc_ctl.scala 145:46]
|
||||
node _T_173 = and(_T_171, _T_172) @[ifu_ifc_ctl.scala 145:44]
|
||||
node _T_174 = or(_T_173, dma_iccm_stall_any_f) @[ifu_ifc_ctl.scala 145:67]
|
||||
io.ifc_dma_access_ok <= _T_174 @[ifu_ifc_ctl.scala 143:24]
|
||||
node _T_175 = eq(iccm_acc_in_range_bf, UInt<1>("h00")) @[ifu_ifc_ctl.scala 147:33]
|
||||
node _T_176 = and(_T_175, iccm_acc_in_region_bf) @[ifu_ifc_ctl.scala 147:55]
|
||||
io.ifc_region_acc_fault_bf <= _T_176 @[ifu_ifc_ctl.scala 147:30]
|
||||
node _T_177 = bits(io.ifc_fetch_addr_bf, 30, 27) @[ifu_ifc_ctl.scala 148:86]
|
||||
node _T_178 = cat(_T_177, UInt<1>("h00")) @[Cat.scala 29:58]
|
||||
node _T_179 = dshr(io.dec_ifc.dec_tlu_mrac_ff, _T_178) @[ifu_ifc_ctl.scala 148:61]
|
||||
node _T_180 = bits(_T_179, 0, 0) @[ifu_ifc_ctl.scala 148:61]
|
||||
node _T_181 = not(_T_180) @[ifu_ifc_ctl.scala 148:34]
|
||||
io.ifc_fetch_uncacheable_bf <= _T_181 @[ifu_ifc_ctl.scala 148:31]
|
||||
wire _T_182 : UInt<1>
|
||||
_T_182 <= UInt<1>("h00")
|
||||
node _T_183 = xor(io.ifc_fetch_req_bf, _T_182) @[lib.scala 458:21]
|
||||
node _T_184 = orr(_T_183) @[lib.scala 458:29]
|
||||
reg _T_185 : UInt<1>, io.free_l2clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when _T_184 : @[Reg.scala 28:19]
|
||||
_T_185 <= io.ifc_fetch_req_bf @[Reg.scala 28:23]
|
||||
skip @[Reg.scala 28:19]
|
||||
_T_182 <= _T_185 @[lib.scala 461:16]
|
||||
io.ifc_fetch_req_f <= _T_182 @[ifu_ifc_ctl.scala 150:22]
|
||||
node _T_186 = or(io.exu_flush_final, io.ifc_fetch_req_f) @[ifu_ifc_ctl.scala 152:76]
|
||||
wire _T_187 : UInt<31> @[lib.scala 593:38]
|
||||
_T_187 <= UInt<1>("h00") @[lib.scala 593:38]
|
||||
reg _T_188 : UInt, clock with : (reset => (reset, _T_187)) @[Reg.scala 27:20]
|
||||
when _T_186 : @[Reg.scala 28:19]
|
||||
_T_188 <= io.ifc_fetch_addr_bf @[Reg.scala 28:23]
|
||||
skip @[Reg.scala 28:19]
|
||||
io.ifc_fetch_addr_f <= _T_188 @[ifu_ifc_ctl.scala 152:23]
|
||||
|
||||
|
|
@ -0,0 +1,306 @@
|
|||
module ifu_ifc_ctl(
|
||||
input clock,
|
||||
input reset,
|
||||
input io_exu_flush_final,
|
||||
input [30:0] io_exu_flush_path_final,
|
||||
input io_free_l2clk,
|
||||
input io_scan_mode,
|
||||
input io_ic_hit_f,
|
||||
input io_ifu_ic_mb_empty,
|
||||
input io_ifu_fb_consume1,
|
||||
input io_ifu_fb_consume2,
|
||||
input io_ifu_bp_hit_taken_f,
|
||||
input [30:0] io_ifu_bp_btb_target_f,
|
||||
input io_ic_dma_active,
|
||||
input io_ic_write_stall,
|
||||
input io_dec_ifc_dec_tlu_flush_noredir_wb,
|
||||
input [31:0] io_dec_ifc_dec_tlu_mrac_ff,
|
||||
output io_dec_ifc_ifu_pmu_fetch_stall,
|
||||
input io_dma_ifc_dma_iccm_stall_any,
|
||||
output [30:0] io_ifc_fetch_addr_f,
|
||||
output [30:0] io_ifc_fetch_addr_bf,
|
||||
output io_ifc_fetch_req_f,
|
||||
output io_ifc_fetch_uncacheable_bf,
|
||||
output io_ifc_fetch_req_bf,
|
||||
output io_ifc_fetch_req_bf_raw,
|
||||
output io_ifc_iccm_access_bf,
|
||||
output io_ifc_region_acc_fault_bf,
|
||||
output io_ifc_dma_access_ok
|
||||
);
|
||||
`ifdef RANDOMIZE_REG_INIT
|
||||
reg [31:0] _RAND_0;
|
||||
reg [31:0] _RAND_1;
|
||||
reg [31:0] _RAND_2;
|
||||
reg [31:0] _RAND_3;
|
||||
reg [31:0] _RAND_4;
|
||||
reg [31:0] _RAND_5;
|
||||
reg [31:0] _RAND_6;
|
||||
`endif // RANDOMIZE_REG_INIT
|
||||
reg dma_iccm_stall_any_f; // @[Reg.scala 27:20]
|
||||
wire dma_stall = io_ic_dma_active | dma_iccm_stall_any_f; // @[ifu_ifc_ctl.scala 62:36]
|
||||
wire _T_1 = io_dma_ifc_dma_iccm_stall_any ^ dma_iccm_stall_any_f; // @[lib.scala 458:21]
|
||||
wire _T_2 = |_T_1; // @[lib.scala 458:29]
|
||||
wire _T_56 = ~io_ic_hit_f; // @[ifu_ifc_ctl.scala 97:34]
|
||||
wire _T_57 = io_ifc_fetch_req_f & _T_56; // @[ifu_ifc_ctl.scala 97:32]
|
||||
wire _T_58 = ~io_exu_flush_final; // @[ifu_ifc_ctl.scala 97:49]
|
||||
wire miss_f = _T_57 & _T_58; // @[ifu_ifc_ctl.scala 97:47]
|
||||
reg miss_a; // @[Reg.scala 27:20]
|
||||
wire _T_5 = miss_f ^ miss_a; // @[lib.scala 436:21]
|
||||
wire _T_6 = |_T_5; // @[lib.scala 436:29]
|
||||
wire _T_9 = ~io_ifc_fetch_req_f; // @[ifu_ifc_ctl.scala 67:53]
|
||||
wire _T_11 = _T_9 | _T_56; // @[ifu_ifc_ctl.scala 67:73]
|
||||
wire _T_12 = _T_58 & _T_11; // @[ifu_ifc_ctl.scala 67:50]
|
||||
wire _T_14 = _T_58 & io_ifc_fetch_req_f; // @[ifu_ifc_ctl.scala 68:49]
|
||||
wire _T_15 = _T_14 & io_ifu_bp_hit_taken_f; // @[ifu_ifc_ctl.scala 68:70]
|
||||
wire _T_16 = _T_15 & io_ic_hit_f; // @[ifu_ifc_ctl.scala 68:94]
|
||||
wire _T_19 = ~io_ifu_bp_hit_taken_f; // @[ifu_ifc_ctl.scala 69:73]
|
||||
wire _T_20 = _T_14 & _T_19; // @[ifu_ifc_ctl.scala 69:71]
|
||||
wire _T_21 = _T_20 & io_ic_hit_f; // @[ifu_ifc_ctl.scala 69:96]
|
||||
wire [30:0] _T_26 = io_exu_flush_final ? io_exu_flush_path_final : 31'h0; // @[Mux.scala 27:72]
|
||||
wire [30:0] _T_27 = _T_12 ? io_ifc_fetch_addr_f : 31'h0; // @[Mux.scala 27:72]
|
||||
wire [30:0] _T_28 = _T_16 ? io_ifu_bp_btb_target_f : 31'h0; // @[Mux.scala 27:72]
|
||||
wire [29:0] address_upper = io_ifc_fetch_addr_f[30:1] + 30'h1; // @[ifu_ifc_ctl.scala 84:48]
|
||||
wire _T_38 = address_upper[4] ^ io_ifc_fetch_addr_f[5]; // @[ifu_ifc_ctl.scala 85:63]
|
||||
wire _T_39 = ~_T_38; // @[ifu_ifc_ctl.scala 85:24]
|
||||
wire fetch_addr_next_0 = _T_39 & io_ifc_fetch_addr_f[0]; // @[ifu_ifc_ctl.scala 85:109]
|
||||
wire [30:0] fetch_addr_next = {address_upper,fetch_addr_next_0}; // @[Cat.scala 29:58]
|
||||
wire [30:0] _T_29 = _T_21 ? fetch_addr_next : 31'h0; // @[Mux.scala 27:72]
|
||||
wire [30:0] _T_30 = _T_26 | _T_27; // @[Mux.scala 27:72]
|
||||
wire [30:0] _T_31 = _T_30 | _T_28; // @[Mux.scala 27:72]
|
||||
reg [1:0] state; // @[Reg.scala 27:20]
|
||||
wire idle = state == 2'h0; // @[ifu_ifc_ctl.scala 129:17]
|
||||
wire _T_44 = io_ifu_fb_consume2 | io_ifu_fb_consume1; // @[ifu_ifc_ctl.scala 92:91]
|
||||
wire _T_45 = ~_T_44; // @[ifu_ifc_ctl.scala 92:70]
|
||||
wire [3:0] _T_133 = io_exu_flush_final ? 4'h1 : 4'h0; // @[Mux.scala 27:72]
|
||||
wire _T_93 = ~io_ifu_fb_consume2; // @[ifu_ifc_ctl.scala 115:38]
|
||||
wire _T_94 = io_ifu_fb_consume1 & _T_93; // @[ifu_ifc_ctl.scala 115:36]
|
||||
wire _T_96 = _T_9 | miss_f; // @[ifu_ifc_ctl.scala 115:81]
|
||||
wire _T_97 = _T_94 & _T_96; // @[ifu_ifc_ctl.scala 115:58]
|
||||
wire _T_98 = io_ifu_fb_consume2 & io_ifc_fetch_req_f; // @[ifu_ifc_ctl.scala 116:25]
|
||||
wire fb_right = _T_97 | _T_98; // @[ifu_ifc_ctl.scala 115:92]
|
||||
wire _T_110 = _T_58 & fb_right; // @[ifu_ifc_ctl.scala 123:16]
|
||||
reg [3:0] fb_write_f; // @[Reg.scala 27:20]
|
||||
wire [3:0] _T_113 = {1'h0,fb_write_f[3:1]}; // @[Cat.scala 29:58]
|
||||
wire [3:0] _T_134 = _T_110 ? _T_113 : 4'h0; // @[Mux.scala 27:72]
|
||||
wire [3:0] _T_138 = _T_133 | _T_134; // @[Mux.scala 27:72]
|
||||
wire fb_right2 = io_ifu_fb_consume2 & _T_96; // @[ifu_ifc_ctl.scala 118:36]
|
||||
wire _T_115 = _T_58 & fb_right2; // @[ifu_ifc_ctl.scala 124:16]
|
||||
wire [3:0] _T_118 = {2'h0,fb_write_f[3:2]}; // @[Cat.scala 29:58]
|
||||
wire [3:0] _T_135 = _T_115 ? _T_118 : 4'h0; // @[Mux.scala 27:72]
|
||||
wire [3:0] _T_139 = _T_138 | _T_135; // @[Mux.scala 27:72]
|
||||
wire _T_103 = io_ifu_fb_consume1 | io_ifu_fb_consume2; // @[ifu_ifc_ctl.scala 119:56]
|
||||
wire _T_104 = ~_T_103; // @[ifu_ifc_ctl.scala 119:35]
|
||||
wire _T_105 = io_ifc_fetch_req_f & _T_104; // @[ifu_ifc_ctl.scala 119:33]
|
||||
wire _T_106 = ~miss_f; // @[ifu_ifc_ctl.scala 119:80]
|
||||
wire fb_left = _T_105 & _T_106; // @[ifu_ifc_ctl.scala 119:78]
|
||||
wire _T_120 = _T_58 & fb_left; // @[ifu_ifc_ctl.scala 125:16]
|
||||
wire [3:0] _T_123 = {fb_write_f[2:0],1'h0}; // @[Cat.scala 29:58]
|
||||
wire [3:0] _T_136 = _T_120 ? _T_123 : 4'h0; // @[Mux.scala 27:72]
|
||||
wire [3:0] _T_140 = _T_139 | _T_136; // @[Mux.scala 27:72]
|
||||
wire _T_125 = ~fb_right; // @[ifu_ifc_ctl.scala 126:18]
|
||||
wire _T_126 = _T_58 & _T_125; // @[ifu_ifc_ctl.scala 126:16]
|
||||
wire _T_127 = ~fb_right2; // @[ifu_ifc_ctl.scala 126:30]
|
||||
wire _T_128 = _T_126 & _T_127; // @[ifu_ifc_ctl.scala 126:28]
|
||||
wire _T_129 = ~fb_left; // @[ifu_ifc_ctl.scala 126:43]
|
||||
wire _T_130 = _T_128 & _T_129; // @[ifu_ifc_ctl.scala 126:41]
|
||||
wire [3:0] _T_137 = _T_130 ? fb_write_f : 4'h0; // @[Mux.scala 27:72]
|
||||
wire [3:0] fb_write_ns = _T_140 | _T_137; // @[Mux.scala 27:72]
|
||||
wire fb_full_f_ns = fb_write_ns[3]; // @[ifu_ifc_ctl.scala 132:30]
|
||||
wire _T_46 = fb_full_f_ns & _T_45; // @[ifu_ifc_ctl.scala 92:68]
|
||||
wire _T_47 = ~_T_46; // @[ifu_ifc_ctl.scala 92:53]
|
||||
wire _T_48 = io_ifc_fetch_req_bf_raw & _T_47; // @[ifu_ifc_ctl.scala 92:51]
|
||||
wire _T_49 = ~dma_stall; // @[ifu_ifc_ctl.scala 93:5]
|
||||
wire _T_50 = _T_48 & _T_49; // @[ifu_ifc_ctl.scala 92:114]
|
||||
wire _T_51 = ~io_ic_write_stall; // @[ifu_ifc_ctl.scala 93:18]
|
||||
wire _T_52 = _T_50 & _T_51; // @[ifu_ifc_ctl.scala 93:16]
|
||||
wire _T_53 = ~io_dec_ifc_dec_tlu_flush_noredir_wb; // @[ifu_ifc_ctl.scala 93:39]
|
||||
wire fetch_bf_en = io_exu_flush_final | io_ifc_fetch_req_f; // @[ifu_ifc_ctl.scala 95:37]
|
||||
wire _T_60 = io_ifu_ic_mb_empty | io_exu_flush_final; // @[ifu_ifc_ctl.scala 99:39]
|
||||
wire _T_62 = _T_60 & _T_49; // @[ifu_ifc_ctl.scala 99:61]
|
||||
wire _T_64 = _T_62 & _T_106; // @[ifu_ifc_ctl.scala 99:74]
|
||||
wire _T_65 = ~miss_a; // @[ifu_ifc_ctl.scala 99:86]
|
||||
wire mb_empty_mod = _T_64 & _T_65; // @[ifu_ifc_ctl.scala 99:84]
|
||||
wire goto_idle = io_exu_flush_final & io_dec_ifc_dec_tlu_flush_noredir_wb; // @[ifu_ifc_ctl.scala 101:35]
|
||||
wire _T_69 = io_exu_flush_final & _T_53; // @[ifu_ifc_ctl.scala 103:36]
|
||||
wire leave_idle = _T_69 & idle; // @[ifu_ifc_ctl.scala 103:75]
|
||||
wire _T_72 = ~state[1]; // @[ifu_ifc_ctl.scala 105:23]
|
||||
wire _T_74 = _T_72 & state[0]; // @[ifu_ifc_ctl.scala 105:33]
|
||||
wire _T_75 = _T_74 & miss_f; // @[ifu_ifc_ctl.scala 105:44]
|
||||
wire _T_76 = ~goto_idle; // @[ifu_ifc_ctl.scala 105:55]
|
||||
wire _T_77 = _T_75 & _T_76; // @[ifu_ifc_ctl.scala 105:53]
|
||||
wire _T_79 = ~mb_empty_mod; // @[ifu_ifc_ctl.scala 106:17]
|
||||
wire _T_80 = state[1] & _T_79; // @[ifu_ifc_ctl.scala 106:15]
|
||||
wire _T_82 = _T_80 & _T_76; // @[ifu_ifc_ctl.scala 106:31]
|
||||
wire next_state_1 = _T_77 | _T_82; // @[ifu_ifc_ctl.scala 105:67]
|
||||
wire _T_84 = _T_76 & leave_idle; // @[ifu_ifc_ctl.scala 108:34]
|
||||
wire _T_87 = state[0] & _T_76; // @[ifu_ifc_ctl.scala 108:60]
|
||||
wire next_state_0 = _T_84 | _T_87; // @[ifu_ifc_ctl.scala 108:48]
|
||||
wire [1:0] _T_88 = {next_state_1,next_state_0}; // @[Cat.scala 29:58]
|
||||
wire [1:0] _T_90 = _T_88 ^ state; // @[lib.scala 436:21]
|
||||
wire _T_91 = |_T_90; // @[lib.scala 436:29]
|
||||
wire wfm = state == 2'h3; // @[ifu_ifc_ctl.scala 130:16]
|
||||
reg fb_full_f; // @[Reg.scala 27:20]
|
||||
wire _T_146 = fb_full_f_ns ^ fb_full_f; // @[lib.scala 436:21]
|
||||
wire _T_147 = |_T_146; // @[lib.scala 436:29]
|
||||
wire [3:0] _T_150 = fb_write_ns ^ fb_write_f; // @[lib.scala 436:21]
|
||||
wire _T_151 = |_T_150; // @[lib.scala 436:29]
|
||||
wire _T_154 = _T_44 | io_exu_flush_final; // @[ifu_ifc_ctl.scala 137:61]
|
||||
wire _T_155 = ~_T_154; // @[ifu_ifc_ctl.scala 137:19]
|
||||
wire _T_156 = fb_full_f & _T_155; // @[ifu_ifc_ctl.scala 137:17]
|
||||
wire _T_157 = _T_156 | dma_stall; // @[ifu_ifc_ctl.scala 137:84]
|
||||
wire _T_158 = io_ifc_fetch_req_bf_raw & _T_157; // @[ifu_ifc_ctl.scala 136:68]
|
||||
wire [31:0] _T_160 = {io_ifc_fetch_addr_bf,1'h0}; // @[Cat.scala 29:58]
|
||||
wire iccm_acc_in_region_bf = _T_160[31:28] == 4'he; // @[lib.scala 84:47]
|
||||
wire iccm_acc_in_range_bf = _T_160[31:16] == 16'hee00; // @[lib.scala 87:29]
|
||||
wire _T_163 = ~io_ifc_iccm_access_bf; // @[ifu_ifc_ctl.scala 143:30]
|
||||
wire _T_166 = fb_full_f & _T_45; // @[ifu_ifc_ctl.scala 144:16]
|
||||
wire _T_167 = _T_163 | _T_166; // @[ifu_ifc_ctl.scala 143:53]
|
||||
wire _T_168 = ~io_ifc_fetch_req_bf; // @[ifu_ifc_ctl.scala 145:13]
|
||||
wire _T_169 = wfm & _T_168; // @[ifu_ifc_ctl.scala 145:11]
|
||||
wire _T_170 = _T_167 | _T_169; // @[ifu_ifc_ctl.scala 144:62]
|
||||
wire _T_171 = _T_170 | idle; // @[ifu_ifc_ctl.scala 145:35]
|
||||
wire _T_173 = _T_171 & _T_58; // @[ifu_ifc_ctl.scala 145:44]
|
||||
wire _T_175 = ~iccm_acc_in_range_bf; // @[ifu_ifc_ctl.scala 147:33]
|
||||
wire [4:0] _T_178 = {io_ifc_fetch_addr_bf[30:27],1'h0}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_179 = io_dec_ifc_dec_tlu_mrac_ff >> _T_178; // @[ifu_ifc_ctl.scala 148:61]
|
||||
reg _T_185; // @[Reg.scala 27:20]
|
||||
wire _T_183 = io_ifc_fetch_req_bf ^ _T_185; // @[lib.scala 458:21]
|
||||
wire _T_184 = |_T_183; // @[lib.scala 458:29]
|
||||
reg [30:0] _T_188; // @[Reg.scala 27:20]
|
||||
assign io_dec_ifc_ifu_pmu_fetch_stall = wfm | _T_158; // @[ifu_ifc_ctl.scala 136:34]
|
||||
assign io_ifc_fetch_addr_f = _T_188; // @[ifu_ifc_ctl.scala 152:23]
|
||||
assign io_ifc_fetch_addr_bf = _T_31 | _T_29; // @[ifu_ifc_ctl.scala 71:25]
|
||||
assign io_ifc_fetch_req_f = _T_185; // @[ifu_ifc_ctl.scala 150:22]
|
||||
assign io_ifc_fetch_uncacheable_bf = ~_T_179[0]; // @[ifu_ifc_ctl.scala 148:31]
|
||||
assign io_ifc_fetch_req_bf = _T_52 & _T_53; // @[ifu_ifc_ctl.scala 92:23]
|
||||
assign io_ifc_fetch_req_bf_raw = ~idle; // @[ifu_ifc_ctl.scala 90:27]
|
||||
assign io_ifc_iccm_access_bf = _T_160[31:16] == 16'hee00; // @[ifu_ifc_ctl.scala 142:25]
|
||||
assign io_ifc_region_acc_fault_bf = _T_175 & iccm_acc_in_region_bf; // @[ifu_ifc_ctl.scala 147:30]
|
||||
assign io_ifc_dma_access_ok = _T_173 | dma_iccm_stall_any_f; // @[ifu_ifc_ctl.scala 143:24]
|
||||
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
||||
`define RANDOMIZE
|
||||
`endif
|
||||
`ifdef RANDOMIZE_INVALID_ASSIGN
|
||||
`define RANDOMIZE
|
||||
`endif
|
||||
`ifdef RANDOMIZE_REG_INIT
|
||||
`define RANDOMIZE
|
||||
`endif
|
||||
`ifdef RANDOMIZE_MEM_INIT
|
||||
`define RANDOMIZE
|
||||
`endif
|
||||
`ifndef RANDOM
|
||||
`define RANDOM $random
|
||||
`endif
|
||||
`ifdef RANDOMIZE_MEM_INIT
|
||||
integer initvar;
|
||||
`endif
|
||||
`ifndef SYNTHESIS
|
||||
`ifdef FIRRTL_BEFORE_INITIAL
|
||||
`FIRRTL_BEFORE_INITIAL
|
||||
`endif
|
||||
initial begin
|
||||
`ifdef RANDOMIZE
|
||||
`ifdef INIT_RANDOM
|
||||
`INIT_RANDOM
|
||||
`endif
|
||||
`ifndef VERILATOR
|
||||
`ifdef RANDOMIZE_DELAY
|
||||
#`RANDOMIZE_DELAY begin end
|
||||
`else
|
||||
#0.002 begin end
|
||||
`endif
|
||||
`endif
|
||||
`ifdef RANDOMIZE_REG_INIT
|
||||
_RAND_0 = {1{`RANDOM}};
|
||||
dma_iccm_stall_any_f = _RAND_0[0:0];
|
||||
_RAND_1 = {1{`RANDOM}};
|
||||
miss_a = _RAND_1[0:0];
|
||||
_RAND_2 = {1{`RANDOM}};
|
||||
state = _RAND_2[1:0];
|
||||
_RAND_3 = {1{`RANDOM}};
|
||||
fb_write_f = _RAND_3[3:0];
|
||||
_RAND_4 = {1{`RANDOM}};
|
||||
fb_full_f = _RAND_4[0:0];
|
||||
_RAND_5 = {1{`RANDOM}};
|
||||
_T_185 = _RAND_5[0:0];
|
||||
_RAND_6 = {1{`RANDOM}};
|
||||
_T_188 = _RAND_6[30:0];
|
||||
`endif // RANDOMIZE_REG_INIT
|
||||
if (reset) begin
|
||||
dma_iccm_stall_any_f = 1'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
miss_a = 1'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
state = 2'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
fb_write_f = 4'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
fb_full_f = 1'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
_T_185 = 1'h0;
|
||||
end
|
||||
if (reset) begin
|
||||
_T_188 = 31'h0;
|
||||
end
|
||||
`endif // RANDOMIZE
|
||||
end // initial
|
||||
`ifdef FIRRTL_AFTER_INITIAL
|
||||
`FIRRTL_AFTER_INITIAL
|
||||
`endif
|
||||
`endif // SYNTHESIS
|
||||
always @(posedge io_free_l2clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
dma_iccm_stall_any_f <= 1'h0;
|
||||
end else if (_T_2) begin
|
||||
dma_iccm_stall_any_f <= io_dma_ifc_dma_iccm_stall_any;
|
||||
end
|
||||
end
|
||||
always @(posedge io_free_l2clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
miss_a <= 1'h0;
|
||||
end else if (_T_6) begin
|
||||
miss_a <= miss_f;
|
||||
end
|
||||
end
|
||||
always @(posedge io_free_l2clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
state <= 2'h0;
|
||||
end else if (_T_91) begin
|
||||
state <= _T_88;
|
||||
end
|
||||
end
|
||||
always @(posedge io_free_l2clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
fb_write_f <= 4'h0;
|
||||
end else if (_T_151) begin
|
||||
fb_write_f <= fb_write_ns;
|
||||
end
|
||||
end
|
||||
always @(posedge io_free_l2clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
fb_full_f <= 1'h0;
|
||||
end else if (_T_147) begin
|
||||
fb_full_f <= fb_full_f_ns;
|
||||
end
|
||||
end
|
||||
always @(posedge io_free_l2clk or posedge reset) begin
|
||||
if (reset) begin
|
||||
_T_185 <= 1'h0;
|
||||
end else if (_T_184) begin
|
||||
_T_185 <= io_ifc_fetch_req_bf;
|
||||
end
|
||||
end
|
||||
always @(posedge clock or posedge reset) begin
|
||||
if (reset) begin
|
||||
_T_188 <= 31'h0;
|
||||
end else if (fetch_bf_en) begin
|
||||
_T_188 <= io_ifc_fetch_addr_bf;
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
|
@ -1,121 +1,121 @@
|
|||
package ifu
|
||||
import chisel3._
|
||||
import chisel3.internal.naming.chiselName
|
||||
import chisel3.util._
|
||||
import exu._
|
||||
import lib._
|
||||
import include._
|
||||
|
||||
@chiselName
|
||||
class ifu extends Module with lib with RequireAsyncReset {
|
||||
val io = IO(new Bundle{
|
||||
val exu_flush_final = Input(Bool())
|
||||
val exu_flush_path_final = Input(UInt(31.W))
|
||||
val free_clk = Input(Clock())
|
||||
val active_clk = Input(Clock())
|
||||
val ifu_dec = new ifu_dec() // IFU and DEC interconnects
|
||||
val exu_ifu = new exu_ifu() // IFU and EXU interconnects
|
||||
val iccm = new iccm_mem() // ICCM memory signals
|
||||
val ic = new ic_mem() // I$ memory signals
|
||||
val ifu = new axi_channels(IFU_BUS_TAG) // AXI Write Channel
|
||||
val ifu_bus_clk_en = Input(Bool())
|
||||
val ifu_dma = new ifu_dma() // DMA signals
|
||||
// ICCM DMA signals
|
||||
val iccm_dma_ecc_error = Output(Bool())
|
||||
val iccm_dma_rvalid = Output(Bool())
|
||||
val iccm_dma_rdata = Output(UInt(64.W))
|
||||
val iccm_dma_rtag = Output(UInt(3.W))
|
||||
val iccm_ready = Output(Bool())
|
||||
// Performance counter
|
||||
val iccm_dma_sb_error = Output(Bool())
|
||||
val dec_tlu_flush_lower_wb = Input(Bool())
|
||||
val scan_mode = Input(Bool())
|
||||
})
|
||||
val mem_ctl = Module(new ifu_mem_ctl)
|
||||
val bp_ctl = Module(new ifu_bp_ctl)
|
||||
val aln_ctl = Module(new ifu_aln_ctl)
|
||||
val ifc_ctl = Module(new ifu_ifc_ctl)
|
||||
|
||||
// IFC wiring Inputs
|
||||
ifc_ctl.io.active_clk := io.active_clk
|
||||
ifc_ctl.io.free_clk := io.free_clk
|
||||
ifc_ctl.io.scan_mode := io.scan_mode
|
||||
ifc_ctl.io.ic_hit_f := mem_ctl.io.ic_hit_f
|
||||
ifc_ctl.io.ifu_fb_consume1 := aln_ctl.io.ifu_fb_consume1
|
||||
ifc_ctl.io.ifu_fb_consume2 := aln_ctl.io.ifu_fb_consume2
|
||||
ifc_ctl.io.dec_ifc <> io.ifu_dec.dec_ifc
|
||||
ifc_ctl.io.exu_flush_final := io.exu_flush_final
|
||||
ifc_ctl.io.ifu_bp_hit_taken_f := bp_ctl.io.ifu_bp_hit_taken_f
|
||||
ifc_ctl.io.ifu_bp_btb_target_f := bp_ctl.io.ifu_bp_btb_target_f
|
||||
ifc_ctl.io.ic_dma_active := mem_ctl.io.ic_dma_active
|
||||
ifc_ctl.io.ic_write_stall := mem_ctl.io.ic_write_stall
|
||||
ifc_ctl.io.dma_ifc <> io.ifu_dma.dma_ifc
|
||||
ifc_ctl.io.ifu_ic_mb_empty := mem_ctl.io.ifu_ic_mb_empty
|
||||
ifc_ctl.io.exu_flush_path_final := io.exu_flush_path_final
|
||||
|
||||
// ALN wiring Inputs
|
||||
aln_ctl.io.scan_mode := io.scan_mode
|
||||
aln_ctl.io.active_clk := io.active_clk
|
||||
aln_ctl.io.ifu_async_error_start := mem_ctl.io.ifu_async_error_start
|
||||
aln_ctl.io.iccm_rd_ecc_double_err := mem_ctl.io.iccm_rd_ecc_double_err
|
||||
aln_ctl.io.ic_access_fault_f := mem_ctl.io.ic_access_fault_f
|
||||
aln_ctl.io.ic_access_fault_type_f := mem_ctl.io.ic_access_fault_type_f
|
||||
aln_ctl.io.ifu_bp_fghr_f := bp_ctl.io.ifu_bp_fghr_f
|
||||
aln_ctl.io.ifu_bp_btb_target_f := bp_ctl.io.ifu_bp_btb_target_f
|
||||
aln_ctl.io.ifu_bp_poffset_f := bp_ctl.io.ifu_bp_poffset_f
|
||||
aln_ctl.io.ifu_bp_hist0_f := bp_ctl.io.ifu_bp_hist0_f
|
||||
aln_ctl.io.ifu_bp_hist1_f := bp_ctl.io.ifu_bp_hist1_f
|
||||
aln_ctl.io.ifu_bp_pc4_f := bp_ctl.io.ifu_bp_pc4_f
|
||||
aln_ctl.io.ifu_bp_way_f := bp_ctl.io.ifu_bp_way_f
|
||||
aln_ctl.io.ifu_bp_valid_f := bp_ctl.io.ifu_bp_valid_f
|
||||
aln_ctl.io.ifu_bp_ret_f := bp_ctl.io.ifu_bp_ret_f
|
||||
aln_ctl.io.exu_flush_final := io.exu_flush_final
|
||||
aln_ctl.io.dec_aln <> io.ifu_dec.dec_aln
|
||||
aln_ctl.io.ifu_fetch_data_f := mem_ctl.io.ic_data_f
|
||||
aln_ctl.io.ifu_fetch_val := mem_ctl.io.ifu_fetch_val
|
||||
aln_ctl.io.ifu_fetch_pc := ifc_ctl.io.ifc_fetch_addr_f
|
||||
|
||||
// BP wiring Inputs
|
||||
bp_ctl.io.scan_mode := io.scan_mode
|
||||
bp_ctl.io.active_clk := io.active_clk
|
||||
bp_ctl.io.ic_hit_f := mem_ctl.io.ic_hit_f
|
||||
bp_ctl.io.ifc_fetch_addr_f := ifc_ctl.io.ifc_fetch_addr_f
|
||||
bp_ctl.io.ifc_fetch_req_f := ifc_ctl.io.ifc_fetch_req_f
|
||||
bp_ctl.io.dec_bp <> io.ifu_dec.dec_bp
|
||||
bp_ctl.io.exu_bp <> io.exu_ifu.exu_bp
|
||||
bp_ctl.io.exu_flush_final := io.exu_flush_final
|
||||
bp_ctl.io.dec_tlu_flush_lower_wb := io.dec_tlu_flush_lower_wb
|
||||
|
||||
// mem-ctl Inputs
|
||||
mem_ctl.io.free_clk := io.free_clk
|
||||
mem_ctl.io.active_clk := io.active_clk
|
||||
mem_ctl.io.exu_flush_final := io.exu_flush_final
|
||||
mem_ctl.io.dec_mem_ctrl <> io.ifu_dec.dec_mem_ctrl
|
||||
mem_ctl.io.ifc_fetch_addr_bf := ifc_ctl.io.ifc_fetch_addr_bf
|
||||
mem_ctl.io.ifc_fetch_uncacheable_bf := ifc_ctl.io.ifc_fetch_uncacheable_bf
|
||||
mem_ctl.io.ifc_fetch_req_bf := ifc_ctl.io.ifc_fetch_req_bf
|
||||
mem_ctl.io.ifc_fetch_req_bf_raw := ifc_ctl.io.ifc_fetch_req_bf_raw
|
||||
mem_ctl.io.ifc_iccm_access_bf := ifc_ctl.io.ifc_iccm_access_bf
|
||||
mem_ctl.io.ifc_region_acc_fault_bf := ifc_ctl.io.ifc_region_acc_fault_bf
|
||||
mem_ctl.io.ifc_dma_access_ok := ifc_ctl.io.ifc_dma_access_ok
|
||||
mem_ctl.io.ifu_bp_hit_taken_f := bp_ctl.io.ifu_bp_hit_taken_f
|
||||
mem_ctl.io.ifu_bp_inst_mask_f := bp_ctl.io.ifu_bp_inst_mask_f
|
||||
mem_ctl.io.ifu_axi <> io.ifu
|
||||
mem_ctl.io.ifu_bus_clk_en := io.ifu_bus_clk_en
|
||||
mem_ctl.io.dma_mem_ctl <> io.ifu_dma.dma_mem_ctl
|
||||
mem_ctl.io.ic <> io.ic
|
||||
mem_ctl.io.iccm <> io.iccm
|
||||
mem_ctl.io.ifu_fetch_val := mem_ctl.io.ic_fetch_val_f
|
||||
mem_ctl.io.dec_tlu_flush_lower_wb := io.dec_tlu_flush_lower_wb
|
||||
mem_ctl.io.scan_mode := io.scan_mode
|
||||
|
||||
// DMA to the ICCM
|
||||
io.iccm_dma_ecc_error := mem_ctl.io.iccm_dma_ecc_error
|
||||
io.iccm_dma_rvalid := mem_ctl.io.iccm_dma_rvalid
|
||||
io.iccm_dma_rdata := mem_ctl.io.iccm_dma_rdata
|
||||
io.iccm_dma_rtag := mem_ctl.io.iccm_dma_rtag
|
||||
io.iccm_ready := mem_ctl.io.iccm_ready
|
||||
io.iccm_dma_sb_error := mem_ctl.io.iccm_dma_sb_error
|
||||
}
|
||||
|
||||
|
||||
//package ifu
|
||||
//import chisel3._
|
||||
//import chisel3.internal.naming.chiselName
|
||||
//import chisel3.util._
|
||||
//import exu._
|
||||
//import lib._
|
||||
//import include._
|
||||
//
|
||||
//@chiselName
|
||||
//class ifu extends Module with lib with RequireAsyncReset {
|
||||
// val io = IO(new Bundle{
|
||||
// val exu_flush_final = Input(Bool())
|
||||
// val exu_flush_path_final = Input(UInt(31.W))
|
||||
// val free_clk = Input(Clock())
|
||||
// val active_clk = Input(Clock())
|
||||
// val ifu_dec = new ifu_dec() // IFU and DEC interconnects
|
||||
// val exu_ifu = new exu_ifu() // IFU and EXU interconnects
|
||||
// val iccm = new iccm_mem() // ICCM memory signals
|
||||
// val ic = new ic_mem() // I$ memory signals
|
||||
// val ifu = new axi_channels(IFU_BUS_TAG) // AXI Write Channel
|
||||
// val ifu_bus_clk_en = Input(Bool())
|
||||
// val ifu_dma = new ifu_dma() // DMA signals
|
||||
// // ICCM DMA signals
|
||||
// val iccm_dma_ecc_error = Output(Bool())
|
||||
// val iccm_dma_rvalid = Output(Bool())
|
||||
// val iccm_dma_rdata = Output(UInt(64.W))
|
||||
// val iccm_dma_rtag = Output(UInt(3.W))
|
||||
// val iccm_ready = Output(Bool())
|
||||
// // Performance counter
|
||||
// val iccm_dma_sb_error = Output(Bool())
|
||||
// val dec_tlu_flush_lower_wb = Input(Bool())
|
||||
// val scan_mode = Input(Bool())
|
||||
// })
|
||||
// val mem_ctl = Module(new ifu_mem_ctl)
|
||||
// val bp_ctl = Module(new ifu_bp_ctl)
|
||||
// val aln_ctl = Module(new ifu_aln_ctl)
|
||||
// val ifc_ctl = Module(new ifu_ifc_ctl)
|
||||
//
|
||||
// // IFC wiring Inputs
|
||||
// ifc_ctl.io.active_clk := io.active_clk
|
||||
// ifc_ctl.io.free_clk := io.free_clk
|
||||
// ifc_ctl.io.scan_mode := io.scan_mode
|
||||
// ifc_ctl.io.ic_hit_f := mem_ctl.io.ic_hit_f
|
||||
// ifc_ctl.io.ifu_fb_consume1 := aln_ctl.io.ifu_fb_consume1
|
||||
// ifc_ctl.io.ifu_fb_consume2 := aln_ctl.io.ifu_fb_consume2
|
||||
// ifc_ctl.io.dec_ifc <> io.ifu_dec.dec_ifc
|
||||
// ifc_ctl.io.exu_flush_final := io.exu_flush_final
|
||||
// ifc_ctl.io.ifu_bp_hit_taken_f := bp_ctl.io.ifu_bp_hit_taken_f
|
||||
// ifc_ctl.io.ifu_bp_btb_target_f := bp_ctl.io.ifu_bp_btb_target_f
|
||||
// ifc_ctl.io.ic_dma_active := mem_ctl.io.ic_dma_active
|
||||
// ifc_ctl.io.ic_write_stall := mem_ctl.io.ic_write_stall
|
||||
// ifc_ctl.io.dma_ifc <> io.ifu_dma.dma_ifc
|
||||
// ifc_ctl.io.ifu_ic_mb_empty := mem_ctl.io.ifu_ic_mb_empty
|
||||
// ifc_ctl.io.exu_flush_path_final := io.exu_flush_path_final
|
||||
//
|
||||
// // ALN wiring Inputs
|
||||
// aln_ctl.io.scan_mode := io.scan_mode
|
||||
// aln_ctl.io.active_clk := io.active_clk
|
||||
// aln_ctl.io.ifu_async_error_start := mem_ctl.io.ifu_async_error_start
|
||||
// aln_ctl.io.iccm_rd_ecc_double_err := mem_ctl.io.iccm_rd_ecc_double_err
|
||||
// aln_ctl.io.ic_access_fault_f := mem_ctl.io.ic_access_fault_f
|
||||
// aln_ctl.io.ic_access_fault_type_f := mem_ctl.io.ic_access_fault_type_f
|
||||
// aln_ctl.io.ifu_bp_fghr_f := bp_ctl.io.ifu_bp_fghr_f
|
||||
// aln_ctl.io.ifu_bp_btb_target_f := bp_ctl.io.ifu_bp_btb_target_f
|
||||
// aln_ctl.io.ifu_bp_poffset_f := bp_ctl.io.ifu_bp_poffset_f
|
||||
// aln_ctl.io.ifu_bp_hist0_f := bp_ctl.io.ifu_bp_hist0_f
|
||||
// aln_ctl.io.ifu_bp_hist1_f := bp_ctl.io.ifu_bp_hist1_f
|
||||
// aln_ctl.io.ifu_bp_pc4_f := bp_ctl.io.ifu_bp_pc4_f
|
||||
// aln_ctl.io.ifu_bp_way_f := bp_ctl.io.ifu_bp_way_f
|
||||
// aln_ctl.io.ifu_bp_valid_f := bp_ctl.io.ifu_bp_valid_f
|
||||
// aln_ctl.io.ifu_bp_ret_f := bp_ctl.io.ifu_bp_ret_f
|
||||
// aln_ctl.io.exu_flush_final := io.exu_flush_final
|
||||
// aln_ctl.io.dec_aln <> io.ifu_dec.dec_aln
|
||||
// aln_ctl.io.ifu_fetch_data_f := mem_ctl.io.ic_data_f
|
||||
// aln_ctl.io.ifu_fetch_val := mem_ctl.io.ifu_fetch_val
|
||||
// aln_ctl.io.ifu_fetch_pc := ifc_ctl.io.ifc_fetch_addr_f
|
||||
//
|
||||
// // BP wiring Inputs
|
||||
// bp_ctl.io.scan_mode := io.scan_mode
|
||||
// bp_ctl.io.active_clk := io.active_clk
|
||||
// bp_ctl.io.ic_hit_f := mem_ctl.io.ic_hit_f
|
||||
// bp_ctl.io.ifc_fetch_addr_f := ifc_ctl.io.ifc_fetch_addr_f
|
||||
// bp_ctl.io.ifc_fetch_req_f := ifc_ctl.io.ifc_fetch_req_f
|
||||
// bp_ctl.io.dec_bp <> io.ifu_dec.dec_bp
|
||||
// bp_ctl.io.exu_bp <> io.exu_ifu.exu_bp
|
||||
// bp_ctl.io.exu_flush_final := io.exu_flush_final
|
||||
// bp_ctl.io.dec_tlu_flush_lower_wb := io.dec_tlu_flush_lower_wb
|
||||
//
|
||||
// // mem-ctl Inputs
|
||||
// mem_ctl.io.free_clk := io.free_clk
|
||||
// mem_ctl.io.active_clk := io.active_clk
|
||||
// mem_ctl.io.exu_flush_final := io.exu_flush_final
|
||||
// mem_ctl.io.dec_mem_ctrl <> io.ifu_dec.dec_mem_ctrl
|
||||
// mem_ctl.io.ifc_fetch_addr_bf := ifc_ctl.io.ifc_fetch_addr_bf
|
||||
// mem_ctl.io.ifc_fetch_uncacheable_bf := ifc_ctl.io.ifc_fetch_uncacheable_bf
|
||||
// mem_ctl.io.ifc_fetch_req_bf := ifc_ctl.io.ifc_fetch_req_bf
|
||||
// mem_ctl.io.ifc_fetch_req_bf_raw := ifc_ctl.io.ifc_fetch_req_bf_raw
|
||||
// mem_ctl.io.ifc_iccm_access_bf := ifc_ctl.io.ifc_iccm_access_bf
|
||||
// mem_ctl.io.ifc_region_acc_fault_bf := ifc_ctl.io.ifc_region_acc_fault_bf
|
||||
// mem_ctl.io.ifc_dma_access_ok := ifc_ctl.io.ifc_dma_access_ok
|
||||
// mem_ctl.io.ifu_bp_hit_taken_f := bp_ctl.io.ifu_bp_hit_taken_f
|
||||
// mem_ctl.io.ifu_bp_inst_mask_f := bp_ctl.io.ifu_bp_inst_mask_f
|
||||
// mem_ctl.io.ifu_axi <> io.ifu
|
||||
// mem_ctl.io.ifu_bus_clk_en := io.ifu_bus_clk_en
|
||||
// mem_ctl.io.dma_mem_ctl <> io.ifu_dma.dma_mem_ctl
|
||||
// mem_ctl.io.ic <> io.ic
|
||||
// mem_ctl.io.iccm <> io.iccm
|
||||
// mem_ctl.io.ifu_fetch_val := mem_ctl.io.ic_fetch_val_f
|
||||
// mem_ctl.io.dec_tlu_flush_lower_wb := io.dec_tlu_flush_lower_wb
|
||||
// mem_ctl.io.scan_mode := io.scan_mode
|
||||
//
|
||||
// // DMA to the ICCM
|
||||
// io.iccm_dma_ecc_error := mem_ctl.io.iccm_dma_ecc_error
|
||||
// io.iccm_dma_rvalid := mem_ctl.io.iccm_dma_rvalid
|
||||
// io.iccm_dma_rdata := mem_ctl.io.iccm_dma_rdata
|
||||
// io.iccm_dma_rtag := mem_ctl.io.iccm_dma_rtag
|
||||
// io.iccm_ready := mem_ctl.io.iccm_ready
|
||||
// io.iccm_dma_sb_error := mem_ctl.io.iccm_dma_sb_error
|
||||
//}
|
||||
//
|
||||
//
|
||||
|
|
|
|||
|
|
@ -9,8 +9,8 @@ class ifu_ifc_ctl extends Module with lib with RequireAsyncReset {
|
|||
val io = IO(new Bundle{
|
||||
val exu_flush_final = Input(Bool()) // Miss Prediction for EXU
|
||||
val exu_flush_path_final = Input(UInt(31.W)) // Replay PC
|
||||
val free_clk = Input(Clock())
|
||||
val active_clk = Input(Clock())
|
||||
val free_l2clk = Input(Clock())
|
||||
// val active_clk = Input(Clock())
|
||||
val scan_mode = Input(Bool())
|
||||
val ic_hit_f = Input(Bool())
|
||||
val ifu_ic_mb_empty = Input(Bool()) // Miss buffer of mem-ctl empty
|
||||
|
|
@ -60,21 +60,27 @@ class ifu_ifc_ctl extends Module with lib with RequireAsyncReset {
|
|||
val idle_E :: fetch_E :: stall_E :: wfm_E :: Nil = Enum(4)
|
||||
|
||||
val dma_stall = io.ic_dma_active | dma_iccm_stall_any_f
|
||||
dma_iccm_stall_any_f := withClock(io.free_clk) {RegNext(io.dma_ifc.dma_iccm_stall_any, init=0.U)}
|
||||
|
||||
miss_a := withClock(io.free_clk) {RegNext(miss_f, init=0.U)}
|
||||
|
||||
val sel_last_addr_bf = !io.exu_flush_final & (!io.ifc_fetch_req_f | !io.ic_hit_f)
|
||||
val sel_btb_addr_bf = !io.exu_flush_final & io.ifc_fetch_req_f & io.ifu_bp_hit_taken_f & io.ic_hit_f
|
||||
val sel_next_addr_bf = !io.exu_flush_final & io.ifc_fetch_req_f & !io.ifu_bp_hit_taken_f & io.ic_hit_f
|
||||
|
||||
// TODO: Make an assertion for the 1H-Mux under here
|
||||
// Next PC calculation
|
||||
io.ifc_fetch_addr_bf := Mux1H(Seq(io.exu_flush_final.asBool -> io.exu_flush_path_final, // Replay PC
|
||||
sel_last_addr_bf.asBool -> io.ifc_fetch_addr_f, // Hold the current PC
|
||||
sel_btb_addr_bf.asBool -> io.ifu_bp_btb_target_f, // Take the predicted PC
|
||||
sel_next_addr_bf.asBool -> fetch_addr_next)) // PC+4
|
||||
|
||||
dma_iccm_stall_any_f := rvdffie(io.dma_ifc.dma_iccm_stall_any,io.free_l2clk,reset.asAsyncReset(),io.scan_mode)
|
||||
miss_a := rvdffie(miss_f,io.free_l2clk,reset.asAsyncReset(),io.scan_mode)
|
||||
if(BTB_ENABLE) {
|
||||
val sel_last_addr_bf = !io.exu_flush_final & (!io.ifc_fetch_req_f | !io.ic_hit_f)
|
||||
val sel_btb_addr_bf = !io.exu_flush_final & io.ifc_fetch_req_f & io.ifu_bp_hit_taken_f & io.ic_hit_f
|
||||
val sel_next_addr_bf = !io.exu_flush_final & io.ifc_fetch_req_f & !io.ifu_bp_hit_taken_f & io.ic_hit_f
|
||||
// Next PC calculation
|
||||
io.ifc_fetch_addr_bf := Mux1H(Seq(io.exu_flush_final.asBool -> io.exu_flush_path_final, // Replay PC
|
||||
sel_last_addr_bf.asBool -> io.ifc_fetch_addr_f, // Hold the current PC
|
||||
sel_btb_addr_bf.asBool -> io.ifu_bp_btb_target_f, // Take the predicted PC
|
||||
sel_next_addr_bf.asBool -> fetch_addr_next)) // PC+4
|
||||
}
|
||||
else{
|
||||
val sel_last_addr_bf = !io.exu_flush_final & (!io.ifc_fetch_req_f | !io.ic_hit_f)
|
||||
val sel_next_addr_bf = !io.exu_flush_final & io.ifc_fetch_req_f & io.ic_hit_f
|
||||
// Next PC calculation
|
||||
io.ifc_fetch_addr_bf := Mux1H(Seq(io.exu_flush_final.asBool -> io.exu_flush_path_final, // Replay PC
|
||||
sel_last_addr_bf.asBool -> io.ifc_fetch_addr_f, // Hold the current PC
|
||||
sel_next_addr_bf.asBool -> fetch_addr_next)) // PC+4
|
||||
}
|
||||
val address_upper = io.ifc_fetch_addr_f(30,1)+1.U
|
||||
fetch_addr_next_0 := !(address_upper(ICACHE_TAG_INDEX_LO-2) ^ io.ifc_fetch_addr_f(ICACHE_TAG_INDEX_LO-1)) & io.ifc_fetch_addr_f(0)
|
||||
|
||||
|
|
@ -101,7 +107,7 @@ class ifu_ifc_ctl extends Module with lib with RequireAsyncReset {
|
|||
|
||||
val next_state_0 = (!goto_idle & leave_idle) | (state(0) & !goto_idle)
|
||||
|
||||
state := withClock(io.active_clk) {RegNext(Cat(next_state_1, next_state_0), init = 0.U)}
|
||||
state := rvdffie(Cat(next_state_1, next_state_0),io.free_l2clk,reset.asAsyncReset(),io.scan_mode)
|
||||
|
||||
flush_fb := io.exu_flush_final
|
||||
|
||||
|
|
@ -124,12 +130,11 @@ class ifu_ifc_ctl extends Module with lib with RequireAsyncReset {
|
|||
wfm := state === 3.U(2.W)
|
||||
|
||||
fb_full_f_ns := fb_write_ns(3)
|
||||
val fb_full_f = withClock(io.active_clk) {RegNext(fb_full_f_ns, init = 0.U)}
|
||||
fb_write_f := withClock(io.active_clk) {RegNext(fb_write_ns, 0.U)}
|
||||
val fb_full_f = rvdffie(fb_full_f_ns,io.free_l2clk,reset.asAsyncReset(),io.scan_mode)
|
||||
fb_write_f := rvdffie(fb_write_ns,io.free_l2clk,reset.asAsyncReset(),io.scan_mode)
|
||||
|
||||
io.dec_ifc.ifu_pmu_fetch_stall := wfm | (io.ifc_fetch_req_bf_raw &
|
||||
((fb_full_f & !(io.ifu_fb_consume2 | io.ifu_fb_consume1 | io.exu_flush_final)) | dma_stall))
|
||||
|
||||
// Checking the next PC range and its region to access the ICCM or I$
|
||||
val (iccm_acc_in_region_bf, iccm_acc_in_range_bf) = if(ICCM_ENABLE)
|
||||
rvrangecheck(ICCM_SADR, ICCM_SIZE, Cat(io.ifc_fetch_addr_bf,0.U))
|
||||
|
|
@ -142,7 +147,10 @@ class ifu_ifc_ctl extends Module with lib with RequireAsyncReset {
|
|||
io.ifc_region_acc_fault_bf := !iccm_acc_in_range_bf & iccm_acc_in_region_bf
|
||||
io.ifc_fetch_uncacheable_bf := ~io.dec_ifc.dec_tlu_mrac_ff(Cat(io.ifc_fetch_addr_bf(30,27), 0.U))
|
||||
|
||||
io.ifc_fetch_req_f := withClock(io.active_clk){RegNext(io.ifc_fetch_req_bf, init=0.U)}
|
||||
io.ifc_fetch_req_f := rvdffie(io.ifc_fetch_req_bf,io.free_l2clk,reset.asAsyncReset(),io.scan_mode)
|
||||
|
||||
io.ifc_fetch_addr_f := rvdffe(io.ifc_fetch_addr_bf, io.exu_flush_final|io.ifc_fetch_req_f, clock, io.scan_mode)
|
||||
io.ifc_fetch_addr_f := rvdffpcie(io.ifc_fetch_addr_bf, io.exu_flush_final|io.ifc_fetch_req_f,reset.asAsyncReset(), clock, io.scan_mode)
|
||||
}
|
||||
object ifc extends App {
|
||||
println((new chisel3.stage.ChiselStage).emitVerilog(new ifu_ifc_ctl()))
|
||||
}
|
||||
|
|
@ -113,8 +113,8 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset {
|
|||
Mux(((bus_ifu_wr_en_ff & last_beat) & !uncacheable_miss_ff).asBool, idle_C,
|
||||
Mux((ic_byp_hit_f & !io.exu_flush_final & !(bus_ifu_wr_en_ff & last_beat) & !ifu_bp_hit_taken_q_f & !uncacheable_miss_ff).asBool, stream_C,
|
||||
Mux((bus_ifu_wr_en_ff & !io.exu_flush_final & !(bus_ifu_wr_en_ff & last_beat) & !ifu_bp_hit_taken_q_f & !uncacheable_miss_ff).asBool, stream_C,
|
||||
Mux((!ic_byp_hit_f & !io.exu_flush_final & (bus_ifu_wr_en_ff & last_beat) & !uncacheable_miss_ff).asBool, idle_C,
|
||||
Mux(((io.exu_flush_final | ifu_bp_hit_taken_q_f) & !(bus_ifu_wr_en_ff & last_beat)).asBool, hit_u_miss_C, idle_C))))))))
|
||||
Mux((!ic_byp_hit_f & !io.exu_flush_final & (bus_ifu_wr_en_ff & last_beat) & !uncacheable_miss_ff).asBool, idle_C,
|
||||
Mux(((io.exu_flush_final | ifu_bp_hit_taken_q_f) & !(bus_ifu_wr_en_ff & last_beat)).asBool, hit_u_miss_C, idle_C))))))))
|
||||
miss_state_en := io.dec_mem_ctrl.dec_tlu_force_halt | io.exu_flush_final | ic_byp_hit_f | ifu_bp_hit_taken_q_f | (bus_ifu_wr_en_ff & last_beat) | (bus_ifu_wr_en_ff & !uncacheable_miss_ff)
|
||||
}
|
||||
is (crit_wrd_rdy_C){ // Critical word hit but not complete, its going to be available in next cycle
|
||||
|
|
@ -159,7 +159,7 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset {
|
|||
miss_pending := miss_state =/= idle_C
|
||||
val crit_wd_byp_ok_ff = (miss_state === crit_byp_ok_C) | ((miss_state === crit_wrd_rdy_C) & !flush_final_f)
|
||||
val sel_hold_imb = (miss_pending & !(bus_ifu_wr_en_ff & last_beat) & !((miss_state === crit_wrd_rdy_C) & io.exu_flush_final) &
|
||||
!((miss_state === crit_wrd_rdy_C) & crit_byp_hit_f) ) | ic_act_miss_f |
|
||||
!((miss_state === crit_wrd_rdy_C) & crit_byp_hit_f) ) | ic_act_miss_f |
|
||||
(miss_pending & (miss_nxtstate === crit_wrd_rdy_C))
|
||||
|
||||
val sel_hold_imb_scnd = ((miss_state === scnd_miss_C) | ic_miss_under_miss_f) & !flush_final_f
|
||||
|
|
@ -200,12 +200,12 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset {
|
|||
val way_status_mb_ff = WireInit(UInt(ICACHE_STATUS_BITS.W), 0.U)
|
||||
val way_status_rep_new = WireInit(UInt(ICACHE_STATUS_BITS.W), 0.U)
|
||||
val way_status_mb_in = Mux((scnd_miss_req & !scnd_miss_index_match).asBool, way_status_mb_scnd_ff,
|
||||
Mux((scnd_miss_req & scnd_miss_index_match).asBool, way_status_rep_new,
|
||||
Mux(miss_pending.asBool, way_status_mb_ff, way_status)))
|
||||
Mux((scnd_miss_req & scnd_miss_index_match).asBool, way_status_rep_new,
|
||||
Mux(miss_pending.asBool, way_status_mb_ff, way_status)))
|
||||
val replace_way_mb_any = Wire(Vec(ICACHE_NUM_WAYS, UInt(1.W)))
|
||||
val tagv_mb_ff = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U)
|
||||
val tagv_mb_in = Mux(scnd_miss_req.asBool, tagv_mb_scnd_ff | (Fill(ICACHE_NUM_WAYS, scnd_miss_index_match) & replace_way_mb_any.reverse.reduce(Cat(_,_))),
|
||||
Mux(miss_pending.asBool, tagv_mb_ff, io.ic.tag_valid & Fill(ICACHE_NUM_WAYS, !reset_all_tags)))
|
||||
Mux(miss_pending.asBool, tagv_mb_ff, io.ic.tag_valid & Fill(ICACHE_NUM_WAYS, !reset_all_tags)))
|
||||
val scnd_miss_req_q = WireInit(Bool(), false.B)
|
||||
val reset_ic_ff = WireInit(Bool(), false.B)
|
||||
val reset_ic_in = miss_pending & !scnd_miss_req_q & (reset_all_tags | reset_ic_ff)
|
||||
|
|
@ -237,7 +237,7 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset {
|
|||
val reset_tag_valid_for_miss = WireInit(Bool(), false.B)
|
||||
val sel_mb_addr = (miss_pending & write_ic_16_bytes & !uncacheable_miss_ff) | reset_tag_valid_for_miss
|
||||
val ifu_ic_rw_int_addr = Mux1H(Seq(sel_mb_addr -> Cat(imb_ff(30,ICACHE_BEAT_ADDR_HI) , ic_wr_addr_bits_hi_3 , imb_ff(1,0)),
|
||||
!sel_mb_addr -> io.ifc_fetch_addr_bf))
|
||||
!sel_mb_addr -> io.ifc_fetch_addr_bf))
|
||||
val bus_ifu_wr_en_ff_q = WireInit(Bool(), false.B)
|
||||
val sel_mb_status_addr = (miss_pending & write_ic_16_bytes & !uncacheable_miss_ff & last_beat & bus_ifu_wr_en_ff_q) | reset_tag_valid_for_miss
|
||||
val ifu_status_wr_addr = Mux(sel_mb_status_addr, Cat(imb_ff(30, ICACHE_BEAT_ADDR_HI),ic_wr_addr_bits_hi_3, imb_ff(1,0)), ifu_fetch_addr_int_f)
|
||||
|
|
@ -286,9 +286,9 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset {
|
|||
val final_data_out1 = VecInit(io.ic.rd_data, ic_byp_data_only_new, io.ic.rd_data, ic_byp_data_only_new)
|
||||
val final_data_out2 = VecInit(1.U, io.iccm.rd_data, 1.U, 1.U)
|
||||
val ic_final_data = if(ICCM_ICACHE) Fill(64, sel_byp_data | sel_iccm_data | sel_ic_data) & io.ic.rd_data else
|
||||
if (ICCM_ONLY) (Fill(64, sel_byp_data) & ic_byp_data_only_new) | (Fill(64, sel_iccm_data) & io.iccm.rd_data) else
|
||||
if (ICCM_ONLY) (Fill(64, sel_byp_data) & ic_byp_data_only_new) | (Fill(64, sel_iccm_data) & io.iccm.rd_data) else
|
||||
if (ICACHE_ONLY) Fill(64, sel_byp_data | sel_ic_data) & io.ic.rd_data else
|
||||
if (NO_ICCM_NO_ICACHE) Fill(64, sel_byp_data) & ic_byp_data_only_new else 0.U
|
||||
if (NO_ICCM_NO_ICACHE) Fill(64, sel_byp_data) & ic_byp_data_only_new else 0.U
|
||||
val ic_premux_data_temp = if(ICCM_ICACHE) (Fill(64,sel_iccm_data) & io.iccm.rd_data) | (Fill(64, sel_byp_data) & ic_byp_data_only_new)
|
||||
else if(ICACHE_ONLY) Fill(64, sel_byp_data) & ic_byp_data_only_new else 0.U
|
||||
val ic_sel_premux_data_temp = if(ICCM_ICACHE) sel_iccm_data | sel_byp_data else if(ICACHE_ONLY) sel_byp_data else 0.U
|
||||
|
|
@ -313,8 +313,8 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset {
|
|||
val ic_miss_buff_data = Wire(Vec(2*ICACHE_NUM_BEATS, UInt(32.W)))
|
||||
for(i<- 0 until ICACHE_NUM_BEATS){
|
||||
val wr_data_c1_clk = write_fill_data.map(rvclkhdr(clock, _ , io.scan_mode))
|
||||
ic_miss_buff_data(2*i) := withClock(wr_data_c1_clk(i)){RegNext(ic_miss_buff_data_in(31,0), 0.U)}
|
||||
ic_miss_buff_data(2*i+1) := withClock(wr_data_c1_clk(i)){RegNext(ic_miss_buff_data_in(63,32), 0.U)}}
|
||||
ic_miss_buff_data(2*i) := withClock(wr_data_c1_clk(i)){RegNext(ic_miss_buff_data_in(31,0), 0.U)}
|
||||
ic_miss_buff_data(2*i+1) := withClock(wr_data_c1_clk(i)){RegNext(ic_miss_buff_data_in(63,32), 0.U)}}
|
||||
val ic_miss_buff_data_valid = WireInit(UInt(ICACHE_NUM_BEATS.W), 0.U)
|
||||
val ic_miss_buff_data_valid_in = (0 until ICACHE_NUM_BEATS).map(i=>write_fill_data(i)|(ic_miss_buff_data_valid(i)&(!ic_act_miss_f)))
|
||||
ic_miss_buff_data_valid := withClock(io.free_clk){RegNext(ic_miss_buff_data_valid_in.map(i=>i.asUInt()).reverse.reduce(Cat(_,_)), 0.U)}
|
||||
|
|
@ -329,16 +329,16 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset {
|
|||
val bypass_index_5_3_inc = bypass_index(bypass_index.getWidth-1,2) + 1.U
|
||||
val bypass_valid_value_check = Mux1H((0 until ICACHE_NUM_BEATS).map(i=>(bypass_index(bypass_index.getWidth-1,2)===i.U).asBool->ic_miss_buff_data_valid_in(i)))
|
||||
val bypass_data_ready_in = (bypass_valid_value_check & !bypass_index(1) & !bypass_index(0)) |
|
||||
(bypass_valid_value_check & !bypass_index(1) & bypass_index(0)) |
|
||||
(bypass_valid_value_check & bypass_index(1) & !bypass_index(0)) |
|
||||
(bypass_valid_value_check & bypass_index(1) & bypass_index(0) & Mux1H((0 until ICACHE_NUM_BEATS).map(i=>(bypass_index_5_3_inc===i.U).asBool->ic_miss_buff_data_valid_in(i)))) |
|
||||
(bypass_valid_value_check & bypass_index(ICACHE_BEAT_ADDR_HI-1,2)===Fill(ICACHE_BEAT_ADDR_HI,1.U))
|
||||
(bypass_valid_value_check & !bypass_index(1) & bypass_index(0)) |
|
||||
(bypass_valid_value_check & bypass_index(1) & !bypass_index(0)) |
|
||||
(bypass_valid_value_check & bypass_index(1) & bypass_index(0) & Mux1H((0 until ICACHE_NUM_BEATS).map(i=>(bypass_index_5_3_inc===i.U).asBool->ic_miss_buff_data_valid_in(i)))) |
|
||||
(bypass_valid_value_check & bypass_index(ICACHE_BEAT_ADDR_HI-1,2)===Fill(ICACHE_BEAT_ADDR_HI,1.U))
|
||||
|
||||
|
||||
val ic_crit_wd_rdy_new_ff = WireInit(Bool(), 0.U)
|
||||
val ic_crit_wd_rdy_new_in = (bypass_data_ready_in & crit_wd_byp_ok_ff & uncacheable_miss_ff & !io.exu_flush_final & !ifu_bp_hit_taken_q_f) |
|
||||
( crit_wd_byp_ok_ff & !uncacheable_miss_ff & !io.exu_flush_final & !ifu_bp_hit_taken_q_f) |
|
||||
(ic_crit_wd_rdy_new_ff & crit_wd_byp_ok_ff & !fetch_req_icache_f & !io.exu_flush_final)
|
||||
( crit_wd_byp_ok_ff & !uncacheable_miss_ff & !io.exu_flush_final & !ifu_bp_hit_taken_q_f) |
|
||||
(ic_crit_wd_rdy_new_ff & crit_wd_byp_ok_ff & !fetch_req_icache_f & !io.exu_flush_final)
|
||||
ic_crit_wd_rdy_new_ff := withClock(io.free_clk){RegNext(ic_crit_wd_rdy_new_in, 0.U)}
|
||||
val byp_fetch_index = ifu_fetch_addr_int_f(ICACHE_BEAT_ADDR_HI-1,0)
|
||||
val byp_fetch_index_0 = Cat(ifu_fetch_addr_int_f(ICACHE_BEAT_ADDR_HI-1,2), 0.U)
|
||||
|
|
@ -348,12 +348,12 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset {
|
|||
val byp_fetch_index_inc_1 = Cat(byp_fetch_index_inc, 1.U)
|
||||
val ic_miss_buff_data_error_bypass = Mux1H((0 until ICACHE_NUM_BEATS).map(i=>(bypass_index(ICACHE_BEAT_ADDR_HI-1,2)===i.U).asBool->ic_miss_buff_data_error(i)))
|
||||
val ic_miss_buff_data_error_bypass_inc = Mux1H((0 until ICACHE_NUM_BEATS).map(i=>(byp_fetch_index_inc===i.U).asBool->ic_miss_buff_data_error(i)))
|
||||
ifu_byp_data_err_new := (!ifu_fetch_addr_int_f(1) & !ifu_fetch_addr_int_f(0) & ic_miss_buff_data_error(byp_fetch_index(ICACHE_BEAT_ADDR_HI-1,2))) |
|
||||
(!ifu_fetch_addr_int_f(1) & ifu_fetch_addr_int_f(0) & ic_miss_buff_data_error(byp_fetch_index(ICACHE_BEAT_ADDR_HI-1,2))) |
|
||||
(!ifu_fetch_addr_int_f(1) & ifu_fetch_addr_int_f(0) & ic_miss_buff_data_error(byp_fetch_index(ICACHE_BEAT_ADDR_HI-1,2))) |
|
||||
( ifu_fetch_addr_int_f(1) & !ifu_fetch_addr_int_f(0) & ic_miss_buff_data_error(byp_fetch_index(ICACHE_BEAT_ADDR_HI-1,2))) |
|
||||
(ifu_fetch_addr_int_f(1) & ifu_fetch_addr_int_f(0) & (ic_miss_buff_data_error(byp_fetch_index(ICACHE_BEAT_ADDR_HI-1,2)) |
|
||||
ic_miss_buff_data_error(byp_fetch_index_inc(ICACHE_BEAT_ADDR_HI-3,0))))
|
||||
ifu_byp_data_err_new := (!ifu_fetch_addr_int_f(1) & !ifu_fetch_addr_int_f(0) & ic_miss_buff_data_error(byp_fetch_index(ICACHE_BEAT_ADDR_HI-1,2))) |
|
||||
(!ifu_fetch_addr_int_f(1) & ifu_fetch_addr_int_f(0) & ic_miss_buff_data_error(byp_fetch_index(ICACHE_BEAT_ADDR_HI-1,2))) |
|
||||
(!ifu_fetch_addr_int_f(1) & ifu_fetch_addr_int_f(0) & ic_miss_buff_data_error(byp_fetch_index(ICACHE_BEAT_ADDR_HI-1,2))) |
|
||||
( ifu_fetch_addr_int_f(1) & !ifu_fetch_addr_int_f(0) & ic_miss_buff_data_error(byp_fetch_index(ICACHE_BEAT_ADDR_HI-1,2))) |
|
||||
(ifu_fetch_addr_int_f(1) & ifu_fetch_addr_int_f(0) & (ic_miss_buff_data_error(byp_fetch_index(ICACHE_BEAT_ADDR_HI-1,2)) |
|
||||
ic_miss_buff_data_error(byp_fetch_index_inc(ICACHE_BEAT_ADDR_HI-3,0))))
|
||||
val ic_byp_data_only_pre_new = Mux(!ifu_fetch_addr_int_f(1).asBool,
|
||||
Cat(Mux1H((0 until 2*ICACHE_NUM_BEATS).map(i=>(byp_fetch_index_inc_0===i.U).asBool->ic_miss_buff_data(i)(15,0))), Mux1H((0 until 2*ICACHE_NUM_BEATS).map(i=>(byp_fetch_index_1===i.U).asBool->ic_miss_buff_data(i)(31,0))), Mux1H((0 until 2*ICACHE_NUM_BEATS).map(i=>(byp_fetch_index_0===i.U).asBool->ic_miss_buff_data(i)(31,0)))),
|
||||
Cat(Mux1H((0 until 2*ICACHE_NUM_BEATS).map(i=>(byp_fetch_index_inc_1===i.U).asBool->ic_miss_buff_data(i)(15,0))), Mux1H((0 until 2*ICACHE_NUM_BEATS).map(i=>(byp_fetch_index_inc_0===i.U).asBool->ic_miss_buff_data(i)(31,0))), Mux1H((0 until 2*ICACHE_NUM_BEATS).map(i=>(byp_fetch_index_1===i.U).asBool->ic_miss_buff_data(i)(31,0)))))
|
||||
|
|
@ -458,8 +458,8 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset {
|
|||
}
|
||||
err_stop_state := withClock(io.free_clk){RegEnable(err_stop_nxtstate, 0.U, err_stop_state_en)}
|
||||
bus_ifu_bus_clk_en := io.ifu_bus_clk_en
|
||||
val busclk = rvclkhdr(clock, bus_ifu_bus_clk_en, io.scan_mode)
|
||||
val busclk_force = rvclkhdr(clock, bus_ifu_bus_clk_en | io.dec_mem_ctrl.dec_tlu_force_halt , io.scan_mode)
|
||||
val busclk = rvclkhdr(clock, bus_ifu_bus_clk_en, io.scan_mode)
|
||||
val busclk_force = rvclkhdr(clock, bus_ifu_bus_clk_en | io.dec_mem_ctrl.dec_tlu_force_halt , io.scan_mode)
|
||||
val bus_ifu_bus_clk_en_ff = withClock(io.free_clk){RegNext(bus_ifu_bus_clk_en, 0.U)}
|
||||
scnd_miss_req_q := withClock(io.free_clk){RegNext(scnd_miss_req_in, 0.U)}
|
||||
val scnd_miss_req_ff2 = withClock(io.free_clk){RegNext(scnd_miss_req, 0.U)}
|
||||
|
|
@ -535,8 +535,8 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset {
|
|||
last_data_recieved_ff := withClock(io.free_clk){RegNext(last_data_recieved_in, 0.U)}
|
||||
// Request Address Count
|
||||
val bus_new_rd_addr_count = Mux(!miss_pending, imb_ff(ICACHE_BEAT_ADDR_HI-1, 2),
|
||||
Mux(scnd_miss_req_q, imb_scnd_ff(ICACHE_BEAT_ADDR_HI-1, 2),
|
||||
Mux(bus_cmd_sent, bus_rd_addr_count + 1.U, bus_rd_addr_count)))
|
||||
Mux(scnd_miss_req_q, imb_scnd_ff(ICACHE_BEAT_ADDR_HI-1, 2),
|
||||
Mux(bus_cmd_sent, bus_rd_addr_count + 1.U, bus_rd_addr_count)))
|
||||
bus_rd_addr_count := withClock(busclk_reset){RegNext(bus_new_rd_addr_count, 0.U)}
|
||||
// Command beat Count
|
||||
val bus_inc_cmd_beat_cnt = ifu_bus_cmd_valid & ifu_bus_cmd_ready & miss_pending & !io.dec_mem_ctrl.dec_tlu_force_halt
|
||||
|
|
@ -630,115 +630,110 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset {
|
|||
((miss_state===miss_wait_C) & !miss_state_en) |
|
||||
((miss_state===crit_wrd_rdy_C) & !miss_state_en) |
|
||||
((miss_state===crit_byp_ok_C) & miss_state_en & (miss_nxtstate===miss_wait_C)) )) |
|
||||
(io.ifc_fetch_req_bf & io.exu_flush_final & !io.ifc_fetch_uncacheable_bf & !io.ifc_iccm_access_bf)
|
||||
(io.ifc_fetch_req_bf & io.exu_flush_final & !io.ifc_fetch_uncacheable_bf & !io.ifc_iccm_access_bf)
|
||||
val bus_ic_wr_en = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U)
|
||||
io.ic.wr_en := bus_ic_wr_en & Fill(ICACHE_NUM_WAYS, write_ic_16_bytes)
|
||||
io.ic_write_stall := write_ic_16_bytes & !((((miss_state===crit_byp_ok_C) | ((miss_state===stream_C) & !(io.exu_flush_final | ifu_bp_hit_taken_q_f | stream_eol_f ))) & !(bus_ifu_wr_en_ff & last_beat & !uncacheable_miss_ff)))
|
||||
reset_all_tags := withClock(io.active_clk){RegNext(io.dec_mem_ctrl.dec_tlu_fence_i_wb, false.B)}
|
||||
// I$ status and P-LRU
|
||||
val ic_valid = !ifu_wr_cumulative_err_data & !(reset_ic_in | reset_ic_ff) & !reset_tag_valid_for_miss
|
||||
val ifu_status_wr_addr_w_debug = Mux((io.ic.debug_rd_en | io.ic.debug_wr_en) & io.ic.debug_tag_array, io.ic.debug_addr(ICACHE_INDEX_HI - 3, ICACHE_TAG_INDEX_LO - 3),
|
||||
ifu_status_wr_addr(ICACHE_INDEX_HI - 1, ICACHE_TAG_INDEX_LO - 1))
|
||||
val ifu_status_wr_addr_ff = withClock(io.free_clk) {
|
||||
RegNext(ifu_status_wr_addr_w_debug, 0.U)
|
||||
}
|
||||
val way_status_wr_en = WireInit(Bool(), false.B)
|
||||
val way_status_wr_en_w_debug = way_status_wr_en | (io.ic.debug_wr_en & io.ic.debug_tag_array)
|
||||
val way_status_wr_en_ff = withClock(io.free_clk) {
|
||||
RegNext(way_status_wr_en_w_debug, false.B)
|
||||
}
|
||||
val way_status_new = WireInit(UInt(ICACHE_STATUS_BITS.W), 0.U)
|
||||
val way_status_new_w_debug = Mux(io.ic.debug_wr_en & io.ic.debug_tag_array,
|
||||
if (ICACHE_STATUS_BITS == 1) io.ic.debug_wr_data(4) else io.ic.debug_wr_data(6, 4), way_status_new)
|
||||
val way_status_new_ff = withClock(io.free_clk) {
|
||||
RegNext(way_status_new_w_debug, 0.U)
|
||||
}
|
||||
val way_status_clken = (0 until ICACHE_TAG_DEPTH / 8).map(i => ifu_status_wr_addr_ff(ICACHE_INDEX_HI - ICACHE_TAG_INDEX_LO, 3) === i.U)
|
||||
val way_status_clk = way_status_clken.map(rvclkhdr(clock, _, io.scan_mode))
|
||||
val way_status_out = Wire(Vec(ICACHE_TAG_DEPTH, UInt(ICACHE_STATUS_BITS.W)))
|
||||
for (i <- 0 until ICACHE_TAG_DEPTH / 8; j <- 0 until 8)
|
||||
way_status_out((8 * i) + j) := withClock(way_status_clk(i)){RegEnable(way_status_new_ff, 0.U, (ifu_status_wr_addr_ff(2,0)===j.U) & way_status_wr_en_ff)}
|
||||
// I$ status and P-LRU
|
||||
val ic_valid = !ifu_wr_cumulative_err_data & !(reset_ic_in | reset_ic_ff) & !reset_tag_valid_for_miss
|
||||
val ifu_status_wr_addr_w_debug = Mux((io.ic.debug_rd_en | io.ic.debug_wr_en) & io.ic.debug_tag_array, io.ic.debug_addr(ICACHE_INDEX_HI - 3, ICACHE_TAG_INDEX_LO - 3),
|
||||
ifu_status_wr_addr(ICACHE_INDEX_HI - 1, ICACHE_TAG_INDEX_LO - 1))
|
||||
val ifu_status_wr_addr_ff = withClock(io.free_clk) {
|
||||
RegNext(ifu_status_wr_addr_w_debug, 0.U)
|
||||
}
|
||||
val way_status_wr_en = WireInit(Bool(), false.B)
|
||||
val way_status_wr_en_w_debug = way_status_wr_en | (io.ic.debug_wr_en & io.ic.debug_tag_array)
|
||||
val way_status_wr_en_ff = withClock(io.free_clk) {
|
||||
RegNext(way_status_wr_en_w_debug, false.B)
|
||||
}
|
||||
val way_status_new = WireInit(UInt(ICACHE_STATUS_BITS.W), 0.U)
|
||||
val way_status_new_w_debug = Mux(io.ic.debug_wr_en & io.ic.debug_tag_array,
|
||||
if (ICACHE_STATUS_BITS == 1) io.ic.debug_wr_data(4) else io.ic.debug_wr_data(6, 4), way_status_new)
|
||||
val way_status_new_ff = withClock(io.free_clk) {
|
||||
RegNext(way_status_new_w_debug, 0.U)
|
||||
}
|
||||
val way_status_clken = (0 until ICACHE_TAG_DEPTH / 8).map(i => ifu_status_wr_addr_ff(ICACHE_INDEX_HI - ICACHE_TAG_INDEX_LO, 3) === i.U)
|
||||
val way_status_clk = way_status_clken.map(rvclkhdr(clock, _, io.scan_mode))
|
||||
val way_status_out = Wire(Vec(ICACHE_TAG_DEPTH, UInt(ICACHE_STATUS_BITS.W)))
|
||||
for (i <- 0 until ICACHE_TAG_DEPTH / 8; j <- 0 until 8)
|
||||
way_status_out((8 * i) + j) := withClock(way_status_clk(i)){RegEnable(way_status_new_ff, 0.U, (ifu_status_wr_addr_ff(2,0)===j.U) & way_status_wr_en_ff)}
|
||||
val test_way_status_out = (0 until ICACHE_TAG_DEPTH).map(i=>way_status_out(i).asUInt).reverse.reduce(Cat(_,_))
|
||||
// io.test_way_status_out := test_way_status_out
|
||||
// io.test_way_status_out := test_way_status_out
|
||||
val test_way_status_clken = (0 until ICACHE_TAG_DEPTH/8).map(i=>way_status_clken(i).asUInt()).reverse.reduce(Cat(_,_))
|
||||
//io.test_way_status_clken := test_way_status_clken
|
||||
way_status := Mux1H((0 until ICACHE_TAG_DEPTH).map(i=>(ifu_ic_rw_int_addr_ff === i.U) -> way_status_out(i)))
|
||||
val ifu_ic_rw_int_addr_w_debug = Mux((io.ic.debug_rd_en | io.ic.debug_wr_en) & io.ic.debug_tag_array,
|
||||
io.ic.debug_addr(ICACHE_INDEX_HI - 3, ICACHE_TAG_INDEX_LO - 3), ifu_ic_rw_int_addr(ICACHE_INDEX_HI - 1, ICACHE_TAG_INDEX_LO - 1))
|
||||
ifu_ic_rw_int_addr_ff := withClock(io.free_clk) {
|
||||
RegNext(ifu_ic_rw_int_addr_w_debug, 0.U)
|
||||
}
|
||||
val ifu_tag_wren = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U)
|
||||
val ic_debug_tag_wr_en = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U)
|
||||
val ifu_tag_wren_w_debug = ifu_tag_wren | ic_debug_tag_wr_en
|
||||
val ifu_tag_wren_ff = withClock(io.free_clk) {
|
||||
RegNext(ifu_tag_wren_w_debug, 0.U)
|
||||
}
|
||||
val ic_valid_w_debug = Mux(io.ic.debug_wr_en & io.ic.debug_tag_array, io.ic.debug_wr_data(0), ic_valid)
|
||||
val ic_valid_ff = withClock(io.free_clk) {
|
||||
RegNext(ic_valid_w_debug, false.B)
|
||||
}
|
||||
val tag_valid_clken = (0 until (ICACHE_TAG_DEPTH / 32)).map(i => (0 until ICACHE_NUM_WAYS).map(j =>
|
||||
if (ICACHE_TAG_DEPTH == 32) ifu_tag_wren_ff(j) | perr_err_inv_way(j) | reset_all_tags
|
||||
else ((ifu_ic_rw_int_addr_ff(ICACHE_INDEX_HI - ICACHE_TAG_INDEX_LO, 5) === i.U) & ifu_tag_wren_ff(j)) |
|
||||
((perr_ic_index_ff(ICACHE_INDEX_HI - ICACHE_TAG_INDEX_LO, 5) === i.U) & perr_err_inv_way(j)) |
|
||||
reset_all_tags).reverse.reduce(Cat(_, _)))
|
||||
val tag_valid_clk = (0 until ICACHE_TAG_DEPTH / 32).map(i => (0 until ICACHE_NUM_WAYS).map(j => rvclkhdr(clock, tag_valid_clken(i)(j), io.scan_mode)))
|
||||
val ic_tag_valid_out = Wire(Vec(ICACHE_NUM_WAYS, Vec(ICACHE_TAG_DEPTH, Bool())))
|
||||
// io.valids := Cat((0 until ICACHE_TAG_DEPTH).map(i=>ic_tag_valid_out(1)(i).asUInt()).reverse.reduce(Cat(_,_)),
|
||||
// (0 until ICACHE_TAG_DEPTH).map(i=>ic_tag_valid_out(0)(i).asUInt()).reverse.reduce(Cat(_,_)))
|
||||
val ifu_ic_rw_int_addr_w_debug = Mux((io.ic.debug_rd_en | io.ic.debug_wr_en) & io.ic.debug_tag_array,
|
||||
io.ic.debug_addr(ICACHE_INDEX_HI - 3, ICACHE_TAG_INDEX_LO - 3), ifu_ic_rw_int_addr(ICACHE_INDEX_HI - 1, ICACHE_TAG_INDEX_LO - 1))
|
||||
ifu_ic_rw_int_addr_ff := withClock(io.free_clk) {
|
||||
RegNext(ifu_ic_rw_int_addr_w_debug, 0.U)
|
||||
}
|
||||
val ifu_tag_wren = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U)
|
||||
val ic_debug_tag_wr_en = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U)
|
||||
val ifu_tag_wren_w_debug = ifu_tag_wren | ic_debug_tag_wr_en
|
||||
val ifu_tag_wren_ff = withClock(io.free_clk) {
|
||||
RegNext(ifu_tag_wren_w_debug, 0.U)
|
||||
}
|
||||
val ic_valid_w_debug = Mux(io.ic.debug_wr_en & io.ic.debug_tag_array, io.ic.debug_wr_data(0), ic_valid)
|
||||
val ic_valid_ff = withClock(io.free_clk) {
|
||||
RegNext(ic_valid_w_debug, false.B)
|
||||
}
|
||||
val tag_valid_clken = (0 until (ICACHE_TAG_DEPTH / 32)).map(i => (0 until ICACHE_NUM_WAYS).map(j =>
|
||||
if (ICACHE_TAG_DEPTH == 32) ifu_tag_wren_ff(j) | perr_err_inv_way(j) | reset_all_tags
|
||||
else ((ifu_ic_rw_int_addr_ff(ICACHE_INDEX_HI - ICACHE_TAG_INDEX_LO, 5) === i.U) & ifu_tag_wren_ff(j)) |
|
||||
((perr_ic_index_ff(ICACHE_INDEX_HI - ICACHE_TAG_INDEX_LO, 5) === i.U) & perr_err_inv_way(j)) |
|
||||
reset_all_tags).reverse.reduce(Cat(_, _)))
|
||||
val tag_valid_clk = (0 until ICACHE_TAG_DEPTH / 32).map(i => (0 until ICACHE_NUM_WAYS).map(j => rvclkhdr(clock, tag_valid_clken(i)(j), io.scan_mode)))
|
||||
val ic_tag_valid_out = Wire(Vec(ICACHE_NUM_WAYS, Vec(ICACHE_TAG_DEPTH, Bool())))
|
||||
// io.valids := Cat((0 until ICACHE_TAG_DEPTH).map(i=>ic_tag_valid_out(1)(i).asUInt()).reverse.reduce(Cat(_,_)),
|
||||
// (0 until ICACHE_TAG_DEPTH).map(i=>ic_tag_valid_out(0)(i).asUInt()).reverse.reduce(Cat(_,_)))
|
||||
|
||||
for (i <- 0 until (ICACHE_TAG_DEPTH / 32); j <- 0 until ICACHE_NUM_WAYS; k <- 0 until 32)
|
||||
ic_tag_valid_out(j)((32 * i) + k) := withClock(tag_valid_clk(i)(j)){RegEnable(ic_valid_ff & !reset_all_tags.asBool & !perr_sel_invalidate, false.B,
|
||||
((((ifu_ic_rw_int_addr_ff === (k + (32 * i)).U) & ifu_tag_wren_ff(j)) | ((perr_ic_index_ff === (k + (32 * i)).U) & perr_err_inv_way(j)) | reset_all_tags)).asBool)}
|
||||
for (i <- 0 until (ICACHE_TAG_DEPTH / 32); j <- 0 until ICACHE_NUM_WAYS; k <- 0 until 32)
|
||||
ic_tag_valid_out(j)((32 * i) + k) := withClock(tag_valid_clk(i)(j)){RegEnable(ic_valid_ff & !reset_all_tags.asBool & !perr_sel_invalidate, false.B,
|
||||
((((ifu_ic_rw_int_addr_ff === (k + (32 * i)).U) & ifu_tag_wren_ff(j)) | ((perr_ic_index_ff === (k + (32 * i)).U) & perr_err_inv_way(j)) | reset_all_tags)).asBool)}
|
||||
|
||||
val ic_tag_valid_unq = (0 until ICACHE_NUM_WAYS).map(k => (0 until ICACHE_TAG_DEPTH).map(j =>
|
||||
Mux(ifu_ic_rw_int_addr_ff === j.U, ic_tag_valid_out(k)(j), false.B).asUInt).reduce(_|_)).reverse.reduce(Cat(_,_))
|
||||
val ic_tag_valid_unq = if(ICACHE_ENABLE)(0 until ICACHE_NUM_WAYS).map(k => (0 until ICACHE_TAG_DEPTH).map(j =>
|
||||
Mux(ifu_ic_rw_int_addr_ff === j.U, ic_tag_valid_out(k)(j), false.B).asUInt).reduce(_|_)).reverse.reduce(Cat(_,_))
|
||||
else 0.U(ICACHE_NUM_WAYS.W)
|
||||
// Making sudo LRU
|
||||
val way_status_hit_new = WireInit(UInt(ICACHE_STATUS_BITS.W), 0.U)
|
||||
if (ICACHE_NUM_WAYS == 4) {
|
||||
replace_way_mb_any(3) := (way_status_mb_ff(2) & way_status_mb_ff(0) & tagv_mb_ff(3, 0).andR) |
|
||||
(!tagv_mb_ff(3) & tagv_mb_ff(2) & tagv_mb_ff(1) & tagv_mb_ff(0))
|
||||
replace_way_mb_any(2) := (!way_status_mb_ff(2) & way_status_mb_ff(0) & tagv_mb_ff(3, 0).andR) |
|
||||
(!tagv_mb_ff(2) & tagv_mb_ff(1) & tagv_mb_ff(0))
|
||||
replace_way_mb_any(1) := (way_status_mb_ff(1) & !way_status_mb_ff(0) & tagv_mb_ff(3, 0).andR) |
|
||||
(!tagv_mb_ff(1) & tagv_mb_ff(0))
|
||||
replace_way_mb_any(0) := (!way_status_mb_ff(1) & !way_status_mb_ff(0) & tagv_mb_ff(3, 0).andR) | !tagv_mb_ff(0)
|
||||
|
||||
// Making sudo LRU
|
||||
val way_status_hit_new = WireInit(UInt(ICACHE_STATUS_BITS.W), 0.U)
|
||||
if (ICACHE_NUM_WAYS == 4) {
|
||||
replace_way_mb_any(3) := (way_status_mb_ff(2) & way_status_mb_ff(0) & tagv_mb_ff(3, 0).andR) |
|
||||
(!tagv_mb_ff(3) & tagv_mb_ff(2) & tagv_mb_ff(1) & tagv_mb_ff(0))
|
||||
replace_way_mb_any(2) := (!way_status_mb_ff(2) & way_status_mb_ff(0) & tagv_mb_ff(3, 0).andR) |
|
||||
(!tagv_mb_ff(2) & tagv_mb_ff(1) & tagv_mb_ff(0))
|
||||
replace_way_mb_any(1) := (way_status_mb_ff(1) & !way_status_mb_ff(0) & tagv_mb_ff(3, 0).andR) |
|
||||
(!tagv_mb_ff(1) & tagv_mb_ff(0))
|
||||
replace_way_mb_any(0) := (!way_status_mb_ff(1) & !way_status_mb_ff(0) & tagv_mb_ff(3, 0).andR) | !tagv_mb_ff(0)
|
||||
way_status_hit_new := Mux1H(Seq(io.ic.rd_hit(0) -> Cat(way_status(2), 3.U),
|
||||
io.ic.rd_hit(1) -> Cat(way_status(2), 1.U(2.W)),
|
||||
io.ic.rd_hit(2) -> Cat(1.U, way_status(1), 0.U),
|
||||
io.ic.rd_hit(3) -> Cat(0.U, way_status(1), 0.U)))
|
||||
|
||||
way_status_hit_new := Mux1H(Seq(io.ic.rd_hit(0) -> Cat(way_status(2), 3.U),
|
||||
io.ic.rd_hit(1) -> Cat(way_status(2), 1.U(2.W)),
|
||||
io.ic.rd_hit(2) -> Cat(1.U, way_status(1), 0.U),
|
||||
io.ic.rd_hit(3) -> Cat(0.U, way_status(1), 0.U)))
|
||||
|
||||
way_status_rep_new := Mux1H(Seq(io.ic.rd_hit(0) -> Cat(way_status_mb_ff(2), 3.U),
|
||||
io.ic.rd_hit(1) -> Cat(way_status_mb_ff(2), 1.U(2.W)),
|
||||
io.ic.rd_hit(2) -> Cat(1.U, way_status_mb_ff(1), 0.U),
|
||||
io.ic.rd_hit(3) -> Cat(0.U, way_status_mb_ff(1), 0.U)))
|
||||
}
|
||||
else {
|
||||
replace_way_mb_any(0) := (!way_status_mb_ff & tagv_mb_ff(0) & tagv_mb_ff(1)) | !tagv_mb_ff(0)
|
||||
replace_way_mb_any(1) := (way_status_mb_ff & tagv_mb_ff(0) & tagv_mb_ff(1)) | !tagv_mb_ff(1) & tagv_mb_ff(0)
|
||||
way_status_hit_new := io.ic.rd_hit(0)
|
||||
way_status_rep_new := replace_way_mb_any(0)
|
||||
}
|
||||
way_status_new := Mux((bus_ifu_wr_en_ff_q & last_beat).asBool, way_status_rep_new, way_status_hit_new)
|
||||
way_status_wr_en := (bus_ifu_wr_en_ff_q & last_beat) | ic_act_hit_f
|
||||
val bus_wren = (0 until ICACHE_NUM_WAYS).map(i => bus_ifu_wr_en_ff_q & replace_way_mb_any(i) & miss_pending)
|
||||
|
||||
val bus_wren_last = (0 until ICACHE_NUM_WAYS).map(i => bus_ifu_wr_en_ff_wo_err & replace_way_mb_any(i) & miss_pending & bus_last_data_beat)
|
||||
val wren_reset_miss = (0 until ICACHE_NUM_WAYS).map(i => replace_way_mb_any(i) & reset_tag_valid_for_miss)
|
||||
ifu_tag_wren := (0 until ICACHE_NUM_WAYS).map(i => bus_wren_last(i) | wren_reset_miss(i)).reverse.reduce(Cat(_, _))
|
||||
way_status_rep_new := Mux1H(Seq(replace_way_mb_any(0).asBool -> Cat(way_status_mb_ff(2), 3.U),
|
||||
replace_way_mb_any(1).asBool -> Cat(way_status_mb_ff(2), 1.U(2.W)),
|
||||
replace_way_mb_any(2).asBool -> Cat(1.U, way_status_mb_ff(1), 0.U),
|
||||
replace_way_mb_any(3).asBool -> Cat(0.U, way_status_mb_ff(1), 0.U)))
|
||||
}
|
||||
else {
|
||||
replace_way_mb_any(0) := (!way_status_mb_ff & tagv_mb_ff(0) & tagv_mb_ff(1)) | !tagv_mb_ff(0)
|
||||
replace_way_mb_any(1) := (way_status_mb_ff & tagv_mb_ff(0) & tagv_mb_ff(1)) | !tagv_mb_ff(1) & tagv_mb_ff(0)
|
||||
way_status_hit_new := io.ic.rd_hit(0)
|
||||
way_status_rep_new := replace_way_mb_any(0)
|
||||
}
|
||||
way_status_new := Mux((bus_ifu_wr_en_ff_q & last_beat).asBool, way_status_rep_new, way_status_hit_new)
|
||||
way_status_wr_en := (bus_ifu_wr_en_ff_q & last_beat) | ic_act_hit_f
|
||||
val bus_wren = if(ICACHE_ENABLE)(0 until ICACHE_NUM_WAYS).map(i => bus_ifu_wr_en_ff_q & replace_way_mb_any(i) & miss_pending)
|
||||
else (0 until ICACHE_NUM_WAYS).map(i => 0.U)
|
||||
val bus_wren_last = (0 until ICACHE_NUM_WAYS).map(i => bus_ifu_wr_en_ff_wo_err & replace_way_mb_any(i) & miss_pending & bus_last_data_beat)
|
||||
val wren_reset_miss = (0 until ICACHE_NUM_WAYS).map(i => replace_way_mb_any(i) & reset_tag_valid_for_miss)
|
||||
ifu_tag_wren := (0 until ICACHE_NUM_WAYS).map(i => bus_wren_last(i) | wren_reset_miss(i)).reverse.reduce(Cat(_, _))
|
||||
|
||||
bus_ic_wr_en := bus_wren.reverse.reduce(Cat(_,_))
|
||||
if(!ICACHE_ENABLE){
|
||||
for(i<- 0 until ICACHE_NUM_WAYS){
|
||||
|
||||
bus_wren(i) := 0.U
|
||||
}
|
||||
ic_tag_valid_unq := 0.U
|
||||
way_status := 0.U
|
||||
replace_way_mb_any := 0.U
|
||||
replace_way_mb_any := (0 until ICACHE_NUM_WAYS).map(i =>0.U)
|
||||
way_status_hit_new := 0.U
|
||||
way_status_rep_new := 0.U
|
||||
way_status_new := 0.U
|
||||
|
|
@ -770,16 +765,17 @@ class ifu_mem_ctl extends Module with lib with RequireAsyncReset {
|
|||
io.dec_mem_ctrl.ifu_ic_debug_rd_data_valid := withClock(io.free_clk){RegNext(ic_debug_rd_en_ff, 0.U)}
|
||||
// Memory protection each access enable with its Mask
|
||||
val ifc_region_acc_okay = !(Cat(INST_ACCESS_ENABLE0.U,INST_ACCESS_ENABLE1.U,INST_ACCESS_ENABLE2.U,INST_ACCESS_ENABLE3.U,INST_ACCESS_ENABLE4.U,INST_ACCESS_ENABLE5.U,INST_ACCESS_ENABLE6.U,INST_ACCESS_ENABLE7.U).orR()) |
|
||||
(INST_ACCESS_ENABLE0.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK0).U) === (aslong(INST_ACCESS_ADDR0).U | aslong(INST_ACCESS_MASK0).U))) |
|
||||
(INST_ACCESS_ENABLE1.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK1).U) === (aslong(INST_ACCESS_ADDR1).U | aslong(INST_ACCESS_MASK1).U))) |
|
||||
(INST_ACCESS_ENABLE2.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK2).U) === (aslong(INST_ACCESS_ADDR2).U | aslong(INST_ACCESS_MASK2).U))) |
|
||||
(INST_ACCESS_ENABLE3.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK3).U) === (aslong(INST_ACCESS_ADDR3).U | aslong(INST_ACCESS_MASK3).U))) |
|
||||
(INST_ACCESS_ENABLE4.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK4).U) === (aslong(INST_ACCESS_ADDR4).U | aslong(INST_ACCESS_MASK4).U))) |
|
||||
(INST_ACCESS_ENABLE5.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK5).U) === (aslong(INST_ACCESS_ADDR5).U | aslong(INST_ACCESS_MASK5).U))) |
|
||||
(INST_ACCESS_ENABLE6.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK6).U) === (aslong(INST_ACCESS_ADDR6).U | aslong(INST_ACCESS_MASK6).U))) |
|
||||
(INST_ACCESS_ENABLE7.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK7).U) === (aslong(INST_ACCESS_ADDR7).U | aslong(INST_ACCESS_MASK7).U)))
|
||||
(INST_ACCESS_ENABLE0.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK0).U) === (aslong(INST_ACCESS_ADDR0).U | aslong(INST_ACCESS_MASK0).U))) |
|
||||
(INST_ACCESS_ENABLE1.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK1).U) === (aslong(INST_ACCESS_ADDR1).U | aslong(INST_ACCESS_MASK1).U))) |
|
||||
(INST_ACCESS_ENABLE2.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK2).U) === (aslong(INST_ACCESS_ADDR2).U | aslong(INST_ACCESS_MASK2).U))) |
|
||||
(INST_ACCESS_ENABLE3.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK3).U) === (aslong(INST_ACCESS_ADDR3).U | aslong(INST_ACCESS_MASK3).U))) |
|
||||
(INST_ACCESS_ENABLE4.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK4).U) === (aslong(INST_ACCESS_ADDR4).U | aslong(INST_ACCESS_MASK4).U))) |
|
||||
(INST_ACCESS_ENABLE5.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK5).U) === (aslong(INST_ACCESS_ADDR5).U | aslong(INST_ACCESS_MASK5).U))) |
|
||||
(INST_ACCESS_ENABLE6.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK6).U) === (aslong(INST_ACCESS_ADDR6).U | aslong(INST_ACCESS_MASK6).U))) |
|
||||
(INST_ACCESS_ENABLE7.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK7).U) === (aslong(INST_ACCESS_ADDR7).U | aslong(INST_ACCESS_MASK7).U)))
|
||||
val ifc_region_acc_fault_memory_bf = !io.ifc_iccm_access_bf & !ifc_region_acc_okay & io.ifc_fetch_req_bf
|
||||
ifc_region_acc_fault_final_bf := io.ifc_region_acc_fault_bf | ifc_region_acc_fault_memory_bf
|
||||
ifc_region_acc_fault_memory_f := withClock(io.free_clk){RegNext(ifc_region_acc_fault_memory_bf, false.B)}
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -319,7 +319,7 @@ class axi4_to_ahb(val TAG : Int = 3) extends Module with lib with RequireAsyncRe
|
|||
ahb_hrdata_q := rvdff_fpga(io.ahb.in.hrdata(63, 0), ahbm_data_clk, ahbm_data_clken, clock)
|
||||
buf_clken := io.bus_clk_en & (buf_wr_en | slvbuf_wr_en | io.clk_override)
|
||||
ahbm_data_clken := io.bus_clk_en & ((buf_state =/= idle) | io.clk_override)
|
||||
if (RV_FPGA_OPTIMIZE) {
|
||||
if (RV_FPGA_OPTIMIZE) {
|
||||
bus_clk := 0.B.asClock()
|
||||
buf_clk := 0.B.asClock()
|
||||
ahbm_data_clk := 0.B.asClock()
|
||||
|
|
|
|||
|
|
@ -371,21 +371,21 @@ trait lib extends param{
|
|||
(in_range,in_region)
|
||||
}
|
||||
object rvdff_fpga {
|
||||
def apply(din: UInt, clk: Clock, clken: Bool,rawclk:Clock):UInt = {
|
||||
def apply(din: UInt, clk: Clock, clken: Bool,rawclk:Clock) = {
|
||||
if (RV_FPGA_OPTIMIZE)
|
||||
withClock(rawclk) {RegEnable (din, 0.U, clken)}
|
||||
else withClock(clk) {RegNext (din, 0.U)}
|
||||
}
|
||||
}
|
||||
object rvdffs_fpga {
|
||||
def apply(din: UInt, en:Bool,clk: Clock, clken: Bool,rawclk:Clock):UInt = {
|
||||
def apply(din: UInt, en:Bool,clk: Clock, clken: Bool,rawclk:Clock) = {
|
||||
if (RV_FPGA_OPTIMIZE)
|
||||
withClock (rawclk) {RegEnable (din, 0.U, (clken & en))}
|
||||
else withClock(clk) {RegEnable (din, 0.U,en)}
|
||||
}
|
||||
}
|
||||
object rvdffsc_fpga {
|
||||
def apply(din: UInt, en:Bool,clear: UInt, clk: Clock, clken: Bool,rawclk:Clock):UInt = {
|
||||
def apply(din: UInt, en:Bool,clear: UInt, clk: Clock, clken: Bool,rawclk:Clock) = {
|
||||
val dout =Wire(UInt())
|
||||
if (RV_FPGA_OPTIMIZE)
|
||||
dout := withClock (rawclk) {RegEnable ((din & Fill(din.getWidth,!clear)), 0.U, ((en|clear)& clken))}
|
||||
|
|
@ -429,6 +429,175 @@ trait lib extends param{
|
|||
}
|
||||
}
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////////
|
||||
object rvdffie {
|
||||
def apply(din: UInt, clk: Clock, rst_l: AsyncReset, scan_mode: Bool)= {
|
||||
val dout = WireInit(UInt(), 0.U)
|
||||
val en = (din ^ dout).orR
|
||||
if (RV_FPGA_OPTIMIZE) {
|
||||
withClock(clk) {
|
||||
dout := RegEnable(din, 0.U, en)
|
||||
}
|
||||
dout
|
||||
} else {
|
||||
|
||||
val obj = Module(new rvclkhdr())
|
||||
val l1clk = obj.io.l1clk
|
||||
obj.io.clk := clk
|
||||
obj.io.en := en
|
||||
obj.io.scan_mode := scan_mode
|
||||
withClock(l1clk) {
|
||||
dout := RegNext(din, 0.U)
|
||||
}
|
||||
dout
|
||||
}
|
||||
|
||||
}
|
||||
def apply(din: Bool, clk: Clock, rst_l: AsyncReset, scan_mode: Bool)= {
|
||||
val dout = WireInit(Bool(), 0.B)
|
||||
val en = (din ^ dout).orR
|
||||
if (RV_FPGA_OPTIMIZE) {
|
||||
withClock(clk) {
|
||||
dout := RegEnable(din, 0.B, en)
|
||||
}
|
||||
dout
|
||||
} else {
|
||||
|
||||
val obj = Module(new rvclkhdr())
|
||||
val l1clk = obj.io.l1clk
|
||||
obj.io.clk := clk
|
||||
obj.io.en := en
|
||||
obj.io.scan_mode := scan_mode
|
||||
withClock(l1clk) {
|
||||
dout := RegNext(din, 0.B)
|
||||
}
|
||||
dout
|
||||
}
|
||||
}
|
||||
|
||||
def apply(din: Bundle, clk: Clock, rst_l: AsyncReset, scan_mode: Bool) = {
|
||||
val dout = WireInit(din)
|
||||
val port = din.getElements
|
||||
val port2 = dout.getElements
|
||||
val en = (port zip port2).map { case (in, out) => (in.asUInt ^ out.asUInt).orR }.reduce(_ | _)
|
||||
if (RV_FPGA_OPTIMIZE) {
|
||||
withClock(clk) {
|
||||
dout := RegEnable(din, 0.U.asTypeOf(din.cloneType), en)
|
||||
}
|
||||
dout
|
||||
} else {
|
||||
val obj = Module(new rvclkhdr())
|
||||
val l1clk = obj.io.l1clk
|
||||
obj.io.clk := clk
|
||||
obj.io.en := en
|
||||
obj.io.scan_mode := scan_mode
|
||||
withClock(l1clk) {
|
||||
dout := RegNext(din, 0.U.asTypeOf(din.cloneType))
|
||||
}
|
||||
dout
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
def apply(din: Vec[UInt], clk: Clock, rst_l: AsyncReset, scan_mode: Bool) = {
|
||||
val dout = WireInit(din)
|
||||
val port = din.getElements
|
||||
val port2 = dout.getElements
|
||||
val en = (port zip port2).map { case (in, out) => (in.asUInt ^ out.asUInt).orR }.reduce(_ | _)
|
||||
if (RV_FPGA_OPTIMIZE) {
|
||||
withClock(clk) {
|
||||
dout := RegEnable(din, 0.U.asTypeOf(din), en)
|
||||
}
|
||||
dout
|
||||
} else {
|
||||
val obj = Module(new rvclkhdr())
|
||||
val l1clk = obj.io.l1clk
|
||||
obj.io.clk := clk
|
||||
obj.io.en := en
|
||||
obj.io.scan_mode := scan_mode
|
||||
withClock(l1clk) {
|
||||
dout := RegNext(din, 0.U.asTypeOf(din.cloneType))
|
||||
}
|
||||
dout
|
||||
}
|
||||
}
|
||||
}
|
||||
/////////////////////////////////////////////////////////////////////////////////////////////
|
||||
object rvdffiee {
|
||||
def apply(din: UInt, clk: Clock, rst_l: AsyncReset, en: Bool, scan_mode: Bool) = {
|
||||
val final_en = Wire(Bool())
|
||||
val dout = WireInit(UInt(), 0.U)
|
||||
if (RV_FPGA_OPTIMIZE) {
|
||||
withClock(clk) {
|
||||
dout := RegEnable(din, 0.U.asTypeOf(din), en)
|
||||
}
|
||||
dout
|
||||
} else {
|
||||
final_en := (din ^ dout).orR & en
|
||||
dout := rvdffe(din, final_en, clk, scan_mode)
|
||||
dout
|
||||
}
|
||||
}
|
||||
|
||||
def apply(din: Bundle, clk: Clock, rst_l: AsyncReset, en: Bool, scan_mode: Bool) = {
|
||||
val dout = WireInit(din)
|
||||
val port = din.getElements
|
||||
val port2 = dout.getElements
|
||||
if (RV_FPGA_OPTIMIZE) {
|
||||
withClock(clk) {
|
||||
dout := RegEnable(din, 0.U.asTypeOf(din), en)
|
||||
}
|
||||
dout
|
||||
} else {
|
||||
val final_en = Wire(Bool())
|
||||
|
||||
final_en := (port zip port2).map { case (in, out) => in.asUInt ^ out.asUInt }.reduce(_ | _) & en
|
||||
// final_en := (din ^ rvdffe(din,final_en,clk,scan_mode)).orR & en
|
||||
dout := rvdffe(din, final_en, clk, scan_mode)
|
||||
dout
|
||||
}
|
||||
}
|
||||
}
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
def rvdfflie_UInt(din: UInt, clk: Clock, rst_l: AsyncReset, en : Bool, scan_mode: Bool, WIDTH: Int=16, LEFT: Int=8) = {
|
||||
val EXTRA = WIDTH-LEFT
|
||||
val LMSB = WIDTH-1
|
||||
val LLSB = LMSB-LEFT+1
|
||||
val XMSB = LLSB-1
|
||||
val XLSB = LLSB-EXTRA
|
||||
Cat(rvdffiee(din(LMSB,LLSB),clk,rst_l,en,scan_mode),rvdffe(din(XMSB,XLSB),en,clk,scan_mode))
|
||||
|
||||
}
|
||||
object rvdfflie {
|
||||
def apply(din: Bundle, clk: Clock, rst_l: AsyncReset, en : Bool, scan_mode: Bool, elements: Int) = {
|
||||
if(RV_FPGA_OPTIMIZE){
|
||||
withClock(clk){
|
||||
RegEnable(din,0.U.asTypeOf(din),en)
|
||||
}
|
||||
}
|
||||
else{
|
||||
val vec = MixedVecInit((0 until din.getElements.length).map(i=>
|
||||
if(i<=elements) rvdffe(din.getElements(i).asUInt(),en,clk,scan_mode)
|
||||
else rvdffiee(din.getElements(i).asUInt(),clk,rst_l,en,scan_mode)))
|
||||
|
||||
vec.asTypeOf(din)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
object rvdffpcie {
|
||||
def apply(din: UInt, en: Bool, rst_l: AsyncReset, clk: Clock, scan_mode: Bool, WIDTH: Int = 31) = {
|
||||
if (RV_FPGA_OPTIMIZE) {
|
||||
withClock(clk) {
|
||||
RegEnable(din, 0.U.asTypeOf(din), en)
|
||||
}
|
||||
}
|
||||
else {
|
||||
rvdfflie_UInt(din, clk, rst_l, en, scan_mode, WIDTH, 19)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/////////////////////////////////////////////////////////
|
||||
def rvtwoscomp(din:UInt) = { //Done for verification and testing
|
||||
|
|
|
|||
|
|
@ -158,5 +158,6 @@ trait param {
|
|||
val RV_FPGA_OPTIMIZE = 0x1
|
||||
val DIV_NEW = 0x1
|
||||
val DIV_BIT = 0x4
|
||||
val BTB_ENABLE = 0x1
|
||||
|
||||
}
|
||||
|
|
|
|||
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Reference in New Issue