IFC
This commit is contained in:
waleed-lm
parent
e0e32412bc
commit
5c2e282a63
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@ -1,4 +1,65 @@
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[
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifu_bp_pc4_f",
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"sources":[
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"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_addr_f",
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"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_req_f",
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"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_flush_leak_one_wb",
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"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_flush_lower_wb"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifu_bp_way_f",
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"sources":[
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"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_addr_f",
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"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_req_f",
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"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_exu_mp_index",
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"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_flush_leak_one_wb",
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"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_flush_lower_wb",
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"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_exu_mp_btag",
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"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_exu_mp_pkt_misp"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifu_bp_hist0_f",
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"sources":[
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"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_addr_f"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifu_bp_hist1_f",
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"sources":[
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"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_addr_f",
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"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_req_f",
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"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_flush_leak_one_wb",
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"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_flush_lower_wb"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifu_bp_ret_f",
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"sources":[
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"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_addr_f",
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"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_req_f",
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"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_flush_leak_one_wb",
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"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_flush_lower_wb"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifu_bp_valid_f",
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"sources":[
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"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_bpred_disable",
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"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_addr_f",
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"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_ifc_fetch_req_f",
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"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_flush_leak_one_wb",
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"~el2_ifu_bp_ctl|el2_ifu_bp_ctl>io_dec_tlu_flush_lower_wb"
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]
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},
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{
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"class":"firrtl.EmitCircuitAnnotation",
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"emitter":"firrtl.VerilogEmitter"
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@ -203,15 +203,15 @@ circuit el2_ifu_bp_ctl :
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btb_bank0e_rd_data_p1_f <= _T_121 @[Mux.scala 27:72]
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node _T_122 = bits(io.ifc_fetch_addr_f, 1, 1) @[el2_ifu_bp_ctl.scala 177:60]
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node _T_123 = not(_T_122) @[el2_ifu_bp_ctl.scala 177:40]
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node _T_124 = bits(io.ifc_fetch_addr_f, 1, 1) @[el2_ifu_bp_ctl.scala 178:24]
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node _T_124 = bits(io.ifc_fetch_addr_f, 1, 1) @[el2_ifu_bp_ctl.scala 178:60]
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node _T_125 = mux(_T_123, btb_bank0e_rd_data_f, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_126 = mux(_T_124, btb_bank0o_rd_data_f, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_127 = or(_T_125, _T_126) @[Mux.scala 27:72]
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wire btb_vbank0_rd_data_f : UInt<22> @[Mux.scala 27:72]
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btb_vbank0_rd_data_f <= _T_127 @[Mux.scala 27:72]
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node _T_128 = bits(io.ifc_fetch_addr_f, 0, 0) @[el2_ifu_bp_ctl.scala 180:60]
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node _T_128 = bits(io.ifc_fetch_addr_f, 1, 1) @[el2_ifu_bp_ctl.scala 180:60]
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node _T_129 = not(_T_128) @[el2_ifu_bp_ctl.scala 180:40]
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node _T_130 = bits(io.ifc_fetch_addr_f, 0, 0) @[el2_ifu_bp_ctl.scala 181:24]
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node _T_130 = bits(io.ifc_fetch_addr_f, 1, 1) @[el2_ifu_bp_ctl.scala 181:60]
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node _T_131 = mux(_T_129, btb_bank0o_rd_data_f, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_132 = mux(_T_130, btb_bank0e_rd_data_p1_f, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_133 = or(_T_131, _T_132) @[Mux.scala 27:72]
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@ -237,9 +237,9 @@ circuit el2_ifu_bp_ctl :
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wire _T_147 : UInt<2> @[Mux.scala 27:72]
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_T_147 <= _T_146 @[Mux.scala 27:72]
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node _T_148 = cat(eoc_mask, UInt<1>("h01")) @[Cat.scala 29:58]
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node vwayhit_f = and(_T_147, _T_148) @[el2_ifu_bp_ctl.scala 190:71]
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node _T_149 = bits(vwayhit_f, 0, 0) @[el2_ifu_bp_ctl.scala 191:38]
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node _T_150 = bits(vwayhit_f, 1, 1) @[el2_ifu_bp_ctl.scala 191:53]
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node bht_valid_f = and(_T_147, _T_148) @[el2_ifu_bp_ctl.scala 190:71]
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node _T_149 = bits(bht_valid_f, 0, 0) @[el2_ifu_bp_ctl.scala 191:38]
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node _T_150 = bits(bht_valid_f, 1, 1) @[el2_ifu_bp_ctl.scala 191:53]
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node _T_151 = or(_T_149, _T_150) @[el2_ifu_bp_ctl.scala 191:42]
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node _T_152 = and(_T_151, io.ifc_fetch_req_f) @[el2_ifu_bp_ctl.scala 191:58]
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node _T_153 = not(leak_one_f) @[el2_ifu_bp_ctl.scala 191:81]
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@ -256,7 +256,7 @@ circuit el2_ifu_bp_ctl :
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node _T_160 = bits(io.exu_mp_pkt.way, 0, 0) @[el2_ifu_bp_ctl.scala 200:45]
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node _T_161 = not(_T_160) @[el2_ifu_bp_ctl.scala 200:33]
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node _T_162 = bits(tag_match_way0_f, 0, 0) @[el2_ifu_bp_ctl.scala 201:22]
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node _T_163 = bits(tag_match_way0_p1_f, 0, 0) @[el2_ifu_bp_ctl.scala 201:65]
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node _T_163 = bits(tag_match_way0_p1_f, 0, 0) @[el2_ifu_bp_ctl.scala 202:25]
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node _T_164 = mux(_T_161, mp_wrlru_b0, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_165 = mux(_T_162, fetch_wrlru_b0, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_166 = mux(_T_163, fetch_wrlru_p1_b0, UInt<1>("h00")) @[Mux.scala 27:72]
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@ -264,26 +264,276 @@ circuit el2_ifu_bp_ctl :
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node _T_168 = or(_T_167, _T_166) @[Mux.scala 27:72]
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wire _T_169 : UInt<256> @[Mux.scala 27:72]
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_T_169 <= _T_168 @[Mux.scala 27:72]
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node _T_170 = and(btb_lru_b0_hold, btb_lru_b0_f) @[el2_ifu_bp_ctl.scala 201:111]
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node btb_lru_b0_ns = or(_T_169, _T_170) @[el2_ifu_bp_ctl.scala 201:93]
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node _T_171 = bits(fetch_mp_collision_f, 0, 0) @[el2_ifu_bp_ctl.scala 203:37]
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node _T_172 = and(fetch_wrindex_dec, btb_lru_b0_f) @[el2_ifu_bp_ctl.scala 203:78]
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node _T_173 = orr(_T_172) @[el2_ifu_bp_ctl.scala 203:94]
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node btb_lru_rd_f = mux(_T_171, exu_mp_way_f, _T_173) @[el2_ifu_bp_ctl.scala 203:25]
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node _T_174 = bits(fetch_mp_collision_p1_f, 0, 0) @[el2_ifu_bp_ctl.scala 204:43]
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node _T_175 = and(fetch_wrindex_p1_dec, btb_lru_b0_f) @[el2_ifu_bp_ctl.scala 204:87]
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node _T_176 = orr(_T_175) @[el2_ifu_bp_ctl.scala 204:103]
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node btb_lru_rd_p1_f = mux(_T_174, exu_mp_way_f, _T_176) @[el2_ifu_bp_ctl.scala 204:28]
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node _T_177 = bits(io.ifc_fetch_addr_f, 1, 1) @[el2_ifu_bp_ctl.scala 206:53]
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node _T_178 = bits(_T_177, 0, 0) @[el2_ifu_bp_ctl.scala 206:57]
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node _T_179 = not(_T_178) @[el2_ifu_bp_ctl.scala 206:33]
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node _T_180 = cat(btb_lru_rd_f, btb_lru_rd_f) @[Cat.scala 29:58]
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node _T_181 = bits(io.ifc_fetch_addr_f, 1, 1) @[el2_ifu_bp_ctl.scala 207:24]
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node _T_182 = bits(_T_181, 0, 0) @[el2_ifu_bp_ctl.scala 207:28]
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node _T_183 = cat(btb_lru_rd_p1_f, btb_lru_rd_f) @[Cat.scala 29:58]
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node _T_184 = mux(_T_179, _T_180, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_185 = mux(_T_182, _T_183, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_186 = or(_T_184, _T_185) @[Mux.scala 27:72]
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node _T_170 = and(btb_lru_b0_hold, btb_lru_b0_f) @[el2_ifu_bp_ctl.scala 202:71]
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node btb_lru_b0_ns = or(_T_169, _T_170) @[el2_ifu_bp_ctl.scala 202:53]
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node _T_171 = bits(fetch_mp_collision_f, 0, 0) @[el2_ifu_bp_ctl.scala 204:37]
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node _T_172 = and(fetch_wrindex_dec, btb_lru_b0_f) @[el2_ifu_bp_ctl.scala 204:78]
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node _T_173 = orr(_T_172) @[el2_ifu_bp_ctl.scala 204:94]
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node btb_lru_rd_f = mux(_T_171, exu_mp_way_f, _T_173) @[el2_ifu_bp_ctl.scala 204:25]
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node _T_174 = bits(fetch_mp_collision_p1_f, 0, 0) @[el2_ifu_bp_ctl.scala 205:43]
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node _T_175 = and(fetch_wrindex_p1_dec, btb_lru_b0_f) @[el2_ifu_bp_ctl.scala 205:87]
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node _T_176 = orr(_T_175) @[el2_ifu_bp_ctl.scala 205:103]
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node btb_lru_rd_p1_f = mux(_T_174, exu_mp_way_f, _T_176) @[el2_ifu_bp_ctl.scala 205:28]
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node _T_177 = bits(io.ifc_fetch_addr_f, 1, 1) @[el2_ifu_bp_ctl.scala 207:53]
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node _T_178 = eq(_T_177, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 207:33]
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node _T_179 = cat(btb_lru_rd_f, btb_lru_rd_f) @[Cat.scala 29:58]
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node _T_180 = bits(io.ifc_fetch_addr_f, 1, 1) @[el2_ifu_bp_ctl.scala 208:24]
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node _T_181 = bits(_T_180, 0, 0) @[el2_ifu_bp_ctl.scala 208:28]
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node _T_182 = cat(btb_lru_rd_p1_f, btb_lru_rd_f) @[Cat.scala 29:58]
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node _T_183 = mux(_T_178, _T_179, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_184 = mux(_T_181, _T_182, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_185 = or(_T_183, _T_184) @[Mux.scala 27:72]
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wire btb_vlru_rd_f : UInt @[Mux.scala 27:72]
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btb_vlru_rd_f <= _T_186 @[Mux.scala 27:72]
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btb_vlru_rd_f <= _T_185 @[Mux.scala 27:72]
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node _T_186 = bits(io.ifc_fetch_addr_f, 1, 1) @[el2_ifu_bp_ctl.scala 210:66]
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node _T_187 = bits(_T_186, 0, 0) @[el2_ifu_bp_ctl.scala 210:70]
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node _T_188 = not(_T_187) @[el2_ifu_bp_ctl.scala 210:46]
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node _T_189 = bits(io.ifc_fetch_addr_f, 1, 1) @[el2_ifu_bp_ctl.scala 211:24]
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node _T_190 = bits(_T_189, 0, 0) @[el2_ifu_bp_ctl.scala 211:28]
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node _T_191 = bits(tag_match_way1_expanded_p1_f, 0, 0) @[el2_ifu_bp_ctl.scala 211:68]
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node _T_192 = bits(tag_match_way1_expanded_f, 1, 1) @[el2_ifu_bp_ctl.scala 211:97]
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node _T_193 = cat(_T_191, _T_192) @[Cat.scala 29:58]
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node _T_194 = mux(_T_188, tag_match_way1_expanded_f, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_195 = mux(_T_190, _T_193, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_196 = or(_T_194, _T_195) @[Mux.scala 27:72]
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wire tag_match_vway1_expanded_f : UInt<2> @[Mux.scala 27:72]
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tag_match_vway1_expanded_f <= _T_196 @[Mux.scala 27:72]
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node _T_197 = not(bht_valid_f) @[el2_ifu_bp_ctl.scala 213:47]
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node _T_198 = and(_T_197, btb_vlru_rd_f) @[el2_ifu_bp_ctl.scala 213:58]
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node way_raw = or(tag_match_vway1_expanded_f, _T_198) @[el2_ifu_bp_ctl.scala 213:44]
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node _T_199 = or(io.ifc_fetch_req_f, exu_mp_valid) @[el2_ifu_bp_ctl.scala 215:75]
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node _T_200 = bits(_T_199, 0, 0) @[el2_ifu_bp_ctl.scala 215:90]
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reg _T_201 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
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when _T_200 : @[Reg.scala 28:19]
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_T_201 <= btb_lru_b0_ns @[Reg.scala 28:23]
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skip @[Reg.scala 28:19]
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btb_lru_b0_f <= _T_201 @[el2_ifu_bp_ctl.scala 215:16]
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node _T_202 = bits(io.ifc_fetch_addr_f, 5, 3) @[el2_ifu_bp_ctl.scala 217:37]
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node eoc_near = andr(_T_202) @[el2_ifu_bp_ctl.scala 217:62]
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node _T_203 = eq(eoc_near, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 218:15]
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node _T_204 = bits(io.ifc_fetch_addr_f, 2, 1) @[el2_ifu_bp_ctl.scala 218:47]
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node _T_205 = orr(_T_204) @[el2_ifu_bp_ctl.scala 218:56]
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node _T_206 = eq(_T_205, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 218:27]
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node _T_207 = or(_T_203, _T_206) @[el2_ifu_bp_ctl.scala 218:25]
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eoc_mask <= _T_207 @[el2_ifu_bp_ctl.scala 218:12]
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wire btb_sel_data_f : UInt<17>
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btb_sel_data_f <= UInt<1>("h00")
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wire hist1_raw : UInt<2>
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hist1_raw <= UInt<1>("h00")
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node btb_rd_tgt_f = bits(btb_sel_data_f, 16, 5) @[el2_ifu_bp_ctl.scala 221:36]
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node btb_rd_pc4_f = bits(btb_sel_data_f, 4, 4) @[el2_ifu_bp_ctl.scala 222:36]
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node btb_rd_call_f = bits(btb_sel_data_f, 2, 2) @[el2_ifu_bp_ctl.scala 223:37]
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node btb_rd_ret_f = bits(btb_sel_data_f, 1, 1) @[el2_ifu_bp_ctl.scala 224:36]
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node _T_208 = bits(btb_sel_f, 1, 1) @[el2_ifu_bp_ctl.scala 226:40]
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node _T_209 = bits(_T_208, 0, 0) @[el2_ifu_bp_ctl.scala 226:44]
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node _T_210 = bits(btb_vbank1_rd_data_f, 16, 1) @[el2_ifu_bp_ctl.scala 226:76]
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node _T_211 = cat(_T_210, UInt<1>("h00")) @[Cat.scala 29:58]
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node _T_212 = bits(btb_sel_f, 0, 0) @[el2_ifu_bp_ctl.scala 227:14]
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node _T_213 = bits(_T_212, 0, 0) @[el2_ifu_bp_ctl.scala 227:18]
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node _T_214 = bits(btb_vbank1_rd_data_f, 16, 1) @[el2_ifu_bp_ctl.scala 227:50]
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node _T_215 = cat(_T_214, UInt<1>("h00")) @[Cat.scala 29:58]
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node _T_216 = mux(_T_209, _T_211, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_217 = mux(_T_213, _T_215, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_218 = or(_T_216, _T_217) @[Mux.scala 27:72]
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wire _T_219 : UInt<17> @[Mux.scala 27:72]
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_T_219 <= _T_218 @[Mux.scala 27:72]
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btb_sel_data_f <= _T_219 @[el2_ifu_bp_ctl.scala 226:18]
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node _T_220 = and(bht_valid_f, hist1_raw) @[el2_ifu_bp_ctl.scala 229:39]
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node _T_221 = orr(_T_220) @[el2_ifu_bp_ctl.scala 229:52]
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node _T_222 = and(_T_221, io.ifc_fetch_req_f) @[el2_ifu_bp_ctl.scala 229:56]
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node _T_223 = not(leak_one_f_d1) @[el2_ifu_bp_ctl.scala 229:79]
|
||||
node _T_224 = and(_T_222, _T_223) @[el2_ifu_bp_ctl.scala 229:77]
|
||||
node _T_225 = not(io.dec_tlu_bpred_disable) @[el2_ifu_bp_ctl.scala 229:96]
|
||||
node ifu_bp_hit_taken_f = and(_T_224, _T_225) @[el2_ifu_bp_ctl.scala 229:94]
|
||||
node _T_226 = bits(btb_vbank1_rd_data_f, 2, 2) @[el2_ifu_bp_ctl.scala 231:52]
|
||||
node _T_227 = bits(btb_vbank1_rd_data_f, 1, 1) @[el2_ifu_bp_ctl.scala 231:81]
|
||||
node _T_228 = or(_T_226, _T_227) @[el2_ifu_bp_ctl.scala 231:59]
|
||||
node _T_229 = bits(btb_vbank0_rd_data_f, 2, 2) @[el2_ifu_bp_ctl.scala 232:25]
|
||||
node _T_230 = bits(btb_vbank0_rd_data_f, 1, 1) @[el2_ifu_bp_ctl.scala 232:54]
|
||||
node _T_231 = or(_T_229, _T_230) @[el2_ifu_bp_ctl.scala 232:32]
|
||||
node bht_force_taken_f = cat(_T_228, _T_231) @[Cat.scala 29:58]
|
||||
wire bht_bank1_rd_data_f : UInt<2>
|
||||
bht_bank1_rd_data_f <= UInt<1>("h00")
|
||||
wire bht_bank0_rd_data_f : UInt<2>
|
||||
bht_bank0_rd_data_f <= UInt<1>("h00")
|
||||
wire bht_bank0_rd_data_p1_f : UInt<2>
|
||||
bht_bank0_rd_data_p1_f <= UInt<1>("h00")
|
||||
node _T_232 = bits(io.ifc_fetch_addr_f, 1, 1) @[el2_ifu_bp_ctl.scala 240:60]
|
||||
node _T_233 = bits(_T_232, 0, 0) @[el2_ifu_bp_ctl.scala 240:64]
|
||||
node _T_234 = eq(_T_233, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 240:40]
|
||||
node _T_235 = bits(io.ifc_fetch_addr_f, 1, 1) @[el2_ifu_bp_ctl.scala 241:60]
|
||||
node _T_236 = bits(_T_235, 0, 0) @[el2_ifu_bp_ctl.scala 241:64]
|
||||
node _T_237 = mux(_T_234, bht_bank0_rd_data_f, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_238 = mux(_T_236, bht_bank1_rd_data_f, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_239 = or(_T_237, _T_238) @[Mux.scala 27:72]
|
||||
wire bht_vbank0_rd_data_f : UInt<2> @[Mux.scala 27:72]
|
||||
bht_vbank0_rd_data_f <= _T_239 @[Mux.scala 27:72]
|
||||
node _T_240 = bits(io.ifc_fetch_addr_f, 1, 1) @[el2_ifu_bp_ctl.scala 243:60]
|
||||
node _T_241 = bits(_T_240, 0, 0) @[el2_ifu_bp_ctl.scala 243:64]
|
||||
node _T_242 = eq(_T_241, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 243:40]
|
||||
node _T_243 = bits(io.ifc_fetch_addr_f, 1, 1) @[el2_ifu_bp_ctl.scala 244:60]
|
||||
node _T_244 = bits(_T_243, 0, 0) @[el2_ifu_bp_ctl.scala 244:64]
|
||||
node _T_245 = mux(_T_242, bht_bank1_rd_data_f, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_246 = mux(_T_244, bht_bank0_rd_data_p1_f, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_247 = or(_T_245, _T_246) @[Mux.scala 27:72]
|
||||
wire bht_vbank1_rd_data_f : UInt<2> @[Mux.scala 27:72]
|
||||
bht_vbank1_rd_data_f <= _T_247 @[Mux.scala 27:72]
|
||||
node _T_248 = bits(bht_force_taken_f, 1, 1) @[el2_ifu_bp_ctl.scala 245:38]
|
||||
node _T_249 = bits(bht_vbank1_rd_data_f, 1, 1) @[el2_ifu_bp_ctl.scala 245:64]
|
||||
node _T_250 = or(_T_248, _T_249) @[el2_ifu_bp_ctl.scala 245:42]
|
||||
node _T_251 = bits(bht_valid_f, 1, 1) @[el2_ifu_bp_ctl.scala 245:82]
|
||||
node _T_252 = and(_T_250, _T_251) @[el2_ifu_bp_ctl.scala 245:69]
|
||||
node _T_253 = bits(bht_force_taken_f, 0, 0) @[el2_ifu_bp_ctl.scala 246:41]
|
||||
node _T_254 = bits(bht_vbank0_rd_data_f, 1, 1) @[el2_ifu_bp_ctl.scala 246:67]
|
||||
node _T_255 = or(_T_253, _T_254) @[el2_ifu_bp_ctl.scala 246:45]
|
||||
node _T_256 = bits(bht_valid_f, 0, 0) @[el2_ifu_bp_ctl.scala 246:85]
|
||||
node _T_257 = and(_T_255, _T_256) @[el2_ifu_bp_ctl.scala 246:72]
|
||||
node _T_258 = cat(_T_252, _T_257) @[Cat.scala 29:58]
|
||||
bht_dir_f <= _T_258 @[el2_ifu_bp_ctl.scala 245:13]
|
||||
node _T_259 = bits(btb_sel_f, 1, 1) @[el2_ifu_bp_ctl.scala 248:59]
|
||||
node _T_260 = and(ifu_bp_hit_taken_f, _T_259) @[el2_ifu_bp_ctl.scala 248:48]
|
||||
node _T_261 = not(ifu_bp_hit_taken_f) @[el2_ifu_bp_ctl.scala 248:66]
|
||||
node ifu_bp_inst_mask_f = or(_T_260, _T_261) @[el2_ifu_bp_ctl.scala 248:64]
|
||||
node _T_262 = bits(bht_vbank1_rd_data_f, 1, 1) @[el2_ifu_bp_ctl.scala 251:60]
|
||||
node _T_263 = bits(bht_vbank0_rd_data_f, 1, 1) @[el2_ifu_bp_ctl.scala 251:85]
|
||||
node _T_264 = cat(_T_262, _T_263) @[Cat.scala 29:58]
|
||||
node _T_265 = or(bht_force_taken_f, _T_264) @[el2_ifu_bp_ctl.scala 251:34]
|
||||
hist1_raw <= _T_265 @[el2_ifu_bp_ctl.scala 251:13]
|
||||
node _T_266 = bits(bht_vbank1_rd_data_f, 0, 0) @[el2_ifu_bp_ctl.scala 253:43]
|
||||
node _T_267 = bits(bht_vbank0_rd_data_f, 0, 0) @[el2_ifu_bp_ctl.scala 253:68]
|
||||
node hist0_raw = cat(_T_266, _T_267) @[Cat.scala 29:58]
|
||||
node _T_268 = bits(bht_valid_f, 1, 1) @[el2_ifu_bp_ctl.scala 255:30]
|
||||
node _T_269 = bits(btb_vbank1_rd_data_f, 4, 4) @[el2_ifu_bp_ctl.scala 255:56]
|
||||
node _T_270 = and(_T_268, _T_269) @[el2_ifu_bp_ctl.scala 255:34]
|
||||
node _T_271 = bits(bht_valid_f, 0, 0) @[el2_ifu_bp_ctl.scala 256:14]
|
||||
node _T_272 = bits(btb_vbank0_rd_data_f, 4, 4) @[el2_ifu_bp_ctl.scala 256:40]
|
||||
node _T_273 = and(_T_271, _T_272) @[el2_ifu_bp_ctl.scala 256:18]
|
||||
node pc4_raw = cat(_T_270, _T_273) @[Cat.scala 29:58]
|
||||
node _T_274 = bits(bht_valid_f, 1, 1) @[el2_ifu_bp_ctl.scala 258:31]
|
||||
node _T_275 = bits(btb_vbank1_rd_data_f, 2, 2) @[el2_ifu_bp_ctl.scala 258:58]
|
||||
node _T_276 = not(_T_275) @[el2_ifu_bp_ctl.scala 258:37]
|
||||
node _T_277 = and(_T_274, _T_276) @[el2_ifu_bp_ctl.scala 258:35]
|
||||
node _T_278 = bits(btb_vbank1_rd_data_f, 1, 1) @[el2_ifu_bp_ctl.scala 258:87]
|
||||
node _T_279 = and(_T_277, _T_278) @[el2_ifu_bp_ctl.scala 258:65]
|
||||
node _T_280 = bits(bht_valid_f, 0, 0) @[el2_ifu_bp_ctl.scala 259:32]
|
||||
node _T_281 = bits(btb_vbank0_rd_data_f, 2, 2) @[el2_ifu_bp_ctl.scala 259:59]
|
||||
node _T_282 = not(_T_281) @[el2_ifu_bp_ctl.scala 259:38]
|
||||
node _T_283 = and(_T_280, _T_282) @[el2_ifu_bp_ctl.scala 259:36]
|
||||
node _T_284 = bits(btb_vbank0_rd_data_f, 1, 1) @[el2_ifu_bp_ctl.scala 259:88]
|
||||
node _T_285 = and(_T_283, _T_284) @[el2_ifu_bp_ctl.scala 259:66]
|
||||
node pret_raw = cat(_T_279, _T_285) @[Cat.scala 29:58]
|
||||
node _T_286 = bits(bht_valid_f, 1, 1) @[el2_ifu_bp_ctl.scala 262:31]
|
||||
node _T_287 = bits(bht_valid_f, 0, 0) @[el2_ifu_bp_ctl.scala 262:49]
|
||||
node num_valids = add(_T_286, _T_287) @[el2_ifu_bp_ctl.scala 262:35]
|
||||
node _T_288 = and(btb_sel_f, bht_dir_f) @[el2_ifu_bp_ctl.scala 264:28]
|
||||
node final_h = andr(_T_288) @[el2_ifu_bp_ctl.scala 264:41]
|
||||
wire fghr : UInt<8>
|
||||
fghr <= UInt<1>("h00")
|
||||
node _T_289 = eq(num_valids, UInt<2>("h02")) @[el2_ifu_bp_ctl.scala 267:41]
|
||||
node _T_290 = bits(_T_289, 0, 0) @[el2_ifu_bp_ctl.scala 267:49]
|
||||
node _T_291 = bits(fghr, 5, 0) @[el2_ifu_bp_ctl.scala 267:65]
|
||||
node _T_292 = cat(_T_291, UInt<1>("h00")) @[Cat.scala 29:58]
|
||||
node _T_293 = cat(_T_292, final_h) @[Cat.scala 29:58]
|
||||
node _T_294 = eq(num_valids, UInt<1>("h01")) @[el2_ifu_bp_ctl.scala 268:16]
|
||||
node _T_295 = bits(_T_294, 0, 0) @[el2_ifu_bp_ctl.scala 268:24]
|
||||
node _T_296 = bits(fghr, 6, 0) @[el2_ifu_bp_ctl.scala 268:40]
|
||||
node _T_297 = cat(_T_296, final_h) @[Cat.scala 29:58]
|
||||
node _T_298 = eq(num_valids, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 269:16]
|
||||
node _T_299 = bits(_T_298, 0, 0) @[el2_ifu_bp_ctl.scala 269:24]
|
||||
node _T_300 = bits(fghr, 7, 0) @[el2_ifu_bp_ctl.scala 269:40]
|
||||
node _T_301 = mux(_T_290, _T_293, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_302 = mux(_T_295, _T_297, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_303 = mux(_T_299, _T_300, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_304 = or(_T_301, _T_302) @[Mux.scala 27:72]
|
||||
node _T_305 = or(_T_304, _T_303) @[Mux.scala 27:72]
|
||||
wire merged_ghr : UInt<8> @[Mux.scala 27:72]
|
||||
merged_ghr <= _T_305 @[Mux.scala 27:72]
|
||||
node _T_306 = bits(exu_flush_final_d1, 0, 0) @[el2_ifu_bp_ctl.scala 273:46]
|
||||
node _T_307 = not(exu_flush_final_d1) @[el2_ifu_bp_ctl.scala 274:6]
|
||||
node _T_308 = and(_T_307, io.ifc_fetch_req_f) @[el2_ifu_bp_ctl.scala 274:26]
|
||||
node _T_309 = and(_T_308, io.ic_hit_f) @[el2_ifu_bp_ctl.scala 274:47]
|
||||
node _T_310 = not(leak_one_f_d1) @[el2_ifu_bp_ctl.scala 274:63]
|
||||
node _T_311 = and(_T_309, _T_310) @[el2_ifu_bp_ctl.scala 274:61]
|
||||
node _T_312 = bits(_T_311, 0, 0) @[el2_ifu_bp_ctl.scala 274:79]
|
||||
node _T_313 = not(exu_flush_final_d1) @[el2_ifu_bp_ctl.scala 275:6]
|
||||
node _T_314 = and(io.ifc_fetch_req_f, io.ic_hit_f) @[el2_ifu_bp_ctl.scala 275:49]
|
||||
node _T_315 = not(leak_one_f_d1) @[el2_ifu_bp_ctl.scala 275:65]
|
||||
node _T_316 = and(_T_314, _T_315) @[el2_ifu_bp_ctl.scala 275:63]
|
||||
node _T_317 = not(_T_316) @[el2_ifu_bp_ctl.scala 275:28]
|
||||
node _T_318 = and(_T_313, _T_317) @[el2_ifu_bp_ctl.scala 275:26]
|
||||
node _T_319 = bits(_T_318, 0, 0) @[el2_ifu_bp_ctl.scala 275:82]
|
||||
node _T_320 = mux(_T_306, io.exu_mp_fghr, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_321 = mux(_T_312, merged_ghr, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_322 = mux(_T_319, fghr, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_323 = or(_T_320, _T_321) @[Mux.scala 27:72]
|
||||
node _T_324 = or(_T_323, _T_322) @[Mux.scala 27:72]
|
||||
wire fghr_ns : UInt<8> @[Mux.scala 27:72]
|
||||
fghr_ns <= _T_324 @[Mux.scala 27:72]
|
||||
reg _T_325 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_bp_ctl.scala 277:18]
|
||||
_T_325 <= fghr_ns @[el2_ifu_bp_ctl.scala 277:18]
|
||||
fghr <= _T_325 @[el2_ifu_bp_ctl.scala 277:8]
|
||||
io.ifu_bp_fghr_f <= fghr @[el2_ifu_bp_ctl.scala 278:20]
|
||||
io.ifu_bp_way_f <= way_raw @[el2_ifu_bp_ctl.scala 280:19]
|
||||
io.ifu_bp_hist1_f <= hist1_raw @[el2_ifu_bp_ctl.scala 281:21]
|
||||
io.ifu_bp_hist0_f <= hist0_raw @[el2_ifu_bp_ctl.scala 282:21]
|
||||
io.ifu_bp_pc4_f <= pc4_raw @[el2_ifu_bp_ctl.scala 283:19]
|
||||
node _T_326 = bits(io.dec_tlu_bpred_disable, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_327 = mux(_T_326, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_328 = not(_T_327) @[el2_ifu_bp_ctl.scala 285:36]
|
||||
node _T_329 = and(bht_valid_f, _T_328) @[el2_ifu_bp_ctl.scala 285:34]
|
||||
io.ifu_bp_valid_f <= _T_329 @[el2_ifu_bp_ctl.scala 285:21]
|
||||
io.ifu_bp_ret_f <= pret_raw @[el2_ifu_bp_ctl.scala 286:19]
|
||||
node _T_330 = bits(bht_dir_f, 0, 0) @[el2_ifu_bp_ctl.scala 288:30]
|
||||
node _T_331 = bits(fetch_start_f, 0, 0) @[el2_ifu_bp_ctl.scala 288:50]
|
||||
node _T_332 = eq(_T_331, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 288:36]
|
||||
node _T_333 = and(_T_330, _T_332) @[el2_ifu_bp_ctl.scala 288:34]
|
||||
node _T_334 = bits(bht_dir_f, 0, 0) @[el2_ifu_bp_ctl.scala 288:68]
|
||||
node _T_335 = eq(_T_334, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 288:58]
|
||||
node _T_336 = bits(fetch_start_f, 0, 0) @[el2_ifu_bp_ctl.scala 288:87]
|
||||
node _T_337 = and(_T_335, _T_336) @[el2_ifu_bp_ctl.scala 288:72]
|
||||
node _T_338 = or(_T_333, _T_337) @[el2_ifu_bp_ctl.scala 288:55]
|
||||
node _T_339 = bits(bht_dir_f, 0, 0) @[el2_ifu_bp_ctl.scala 289:15]
|
||||
node _T_340 = bits(fetch_start_f, 0, 0) @[el2_ifu_bp_ctl.scala 289:34]
|
||||
node _T_341 = and(_T_339, _T_340) @[el2_ifu_bp_ctl.scala 289:19]
|
||||
node _T_342 = bits(bht_dir_f, 0, 0) @[el2_ifu_bp_ctl.scala 289:52]
|
||||
node _T_343 = eq(_T_342, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 289:42]
|
||||
node _T_344 = bits(fetch_start_f, 0, 0) @[el2_ifu_bp_ctl.scala 289:72]
|
||||
node _T_345 = eq(_T_344, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 289:58]
|
||||
node _T_346 = and(_T_343, _T_345) @[el2_ifu_bp_ctl.scala 289:56]
|
||||
node _T_347 = or(_T_341, _T_346) @[el2_ifu_bp_ctl.scala 289:39]
|
||||
node bloc_f = cat(_T_338, _T_347) @[Cat.scala 29:58]
|
||||
node _T_348 = bits(bht_dir_f, 0, 0) @[el2_ifu_bp_ctl.scala 291:31]
|
||||
node _T_349 = eq(_T_348, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 291:21]
|
||||
node _T_350 = bits(io.ifc_fetch_addr_f, 0, 0) @[el2_ifu_bp_ctl.scala 291:56]
|
||||
node _T_351 = and(_T_349, _T_350) @[el2_ifu_bp_ctl.scala 291:35]
|
||||
node _T_352 = eq(btb_rd_pc4_f, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 291:62]
|
||||
node use_fa_plus = and(_T_351, _T_352) @[el2_ifu_bp_ctl.scala 291:60]
|
||||
node _T_353 = bits(fetch_start_f, 0, 0) @[el2_ifu_bp_ctl.scala 293:40]
|
||||
node _T_354 = bits(btb_sel_f, 0, 0) @[el2_ifu_bp_ctl.scala 293:55]
|
||||
node _T_355 = and(_T_353, _T_354) @[el2_ifu_bp_ctl.scala 293:44]
|
||||
node btb_fg_crossing_f = and(_T_355, btb_rd_pc4_f) @[el2_ifu_bp_ctl.scala 293:59]
|
||||
node _T_356 = bits(bloc_f, 1, 1) @[el2_ifu_bp_ctl.scala 294:40]
|
||||
node bp_total_branch_offset_f = xor(_T_356, btb_rd_pc4_f) @[el2_ifu_bp_ctl.scala 294:43]
|
||||
node _T_357 = not(ifu_bp_hit_taken_f) @[el2_ifu_bp_ctl.scala 296:89]
|
||||
node _T_358 = and(io.ifc_fetch_req_f, _T_357) @[el2_ifu_bp_ctl.scala 296:87]
|
||||
node _T_359 = and(_T_358, io.ic_hit_f) @[el2_ifu_bp_ctl.scala 296:109]
|
||||
node _T_360 = bits(_T_359, 0, 0) @[el2_ifu_bp_ctl.scala 296:124]
|
||||
reg ifc_fetch_adder_prior : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when _T_360 : @[Reg.scala 28:19]
|
||||
ifc_fetch_adder_prior <= io.ifc_fetch_addr_f @[Reg.scala 28:23]
|
||||
skip @[Reg.scala 28:19]
|
||||
node _T_361 = bits(use_fa_plus, 0, 0) @[el2_ifu_bp_ctl.scala 299:45]
|
||||
node _T_362 = bits(btb_fg_crossing_f, 0, 0) @[el2_ifu_bp_ctl.scala 300:23]
|
||||
node _T_363 = eq(btb_fg_crossing_f, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 301:6]
|
||||
node _T_364 = eq(use_fa_plus, UInt<1>("h00")) @[el2_ifu_bp_ctl.scala 301:27]
|
||||
node _T_365 = and(_T_363, _T_364) @[el2_ifu_bp_ctl.scala 301:25]
|
||||
node _T_366 = bits(_T_365, 0, 0) @[el2_ifu_bp_ctl.scala 301:41]
|
||||
node _T_367 = bits(io.ifc_fetch_addr_f, 31, 2) @[el2_ifu_bp_ctl.scala 301:68]
|
||||
node _T_368 = mux(_T_361, fetch_addr_p1_f, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_369 = mux(_T_362, ifc_fetch_adder_prior, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_370 = mux(_T_366, _T_367, UInt<1>("h00")) @[Mux.scala 27:72]
|
||||
node _T_371 = or(_T_368, _T_369) @[Mux.scala 27:72]
|
||||
node _T_372 = or(_T_371, _T_370) @[Mux.scala 27:72]
|
||||
wire adder_pc_in_f : UInt @[Mux.scala 27:72]
|
||||
adder_pc_in_f <= _T_372 @[Mux.scala 27:72]
|
||||
|
||||
|
|
|
|||
160
el2_ifu_bp_ctl.v
160
el2_ifu_bp_ctl.v
|
|
@ -49,15 +49,161 @@ module el2_ifu_bp_ctl(
|
|||
output [1:0] io_ifu_bp_valid_f,
|
||||
output [11:0] io_ifu_bp_poffset_f
|
||||
);
|
||||
`ifdef RANDOMIZE_REG_INIT
|
||||
reg [31:0] _RAND_0;
|
||||
reg [31:0] _RAND_1;
|
||||
reg [31:0] _RAND_2;
|
||||
reg [255:0] _RAND_3;
|
||||
reg [31:0] _RAND_4;
|
||||
`endif // RANDOMIZE_REG_INIT
|
||||
wire _T_26 = io_dec_tlu_flush_leak_one_wb & io_dec_tlu_flush_lower_wb; // @[el2_ifu_bp_ctl.scala 133:47]
|
||||
reg leak_one_f_d1; // @[el2_ifu_bp_ctl.scala 128:30]
|
||||
wire _T_27 = leak_one_f_d1 & io_dec_tlu_flush_lower_wb; // @[el2_ifu_bp_ctl.scala 133:93]
|
||||
wire leak_one_f = _T_26 | _T_27; // @[el2_ifu_bp_ctl.scala 133:76]
|
||||
wire _T = ~leak_one_f; // @[el2_ifu_bp_ctl.scala 67:43]
|
||||
wire exu_mp_valid = io_exu_mp_pkt_misp & _T; // @[el2_ifu_bp_ctl.scala 67:41]
|
||||
wire [7:0] _T_3 = io_ifc_fetch_addr_f[9:2] ^ io_ifc_fetch_addr_f[17:10]; // @[el2_lib.scala 182:42]
|
||||
wire [7:0] btb_rd_addr_f = _T_3 ^ io_ifc_fetch_addr_f[25:18]; // @[el2_lib.scala 182:76]
|
||||
wire [31:0] fetch_addr_p1_f = io_ifc_fetch_addr_f + 32'h4; // @[el2_ifu_bp_ctl.scala 106:45]
|
||||
wire [7:0] _T_8 = fetch_addr_p1_f[9:2] ^ fetch_addr_p1_f[17:10]; // @[el2_lib.scala 182:42]
|
||||
wire [7:0] btb_rd_addr_p1_f = _T_8 ^ fetch_addr_p1_f[25:18]; // @[el2_lib.scala 182:76]
|
||||
wire _T_129 = ~io_ifc_fetch_addr_f[1]; // @[el2_ifu_bp_ctl.scala 180:40]
|
||||
wire _T_18 = io_exu_mp_btag == 5'h0; // @[el2_ifu_bp_ctl.scala 125:46]
|
||||
wire _T_19 = _T_18 & exu_mp_valid; // @[el2_ifu_bp_ctl.scala 125:66]
|
||||
wire _T_20 = _T_19 & io_ifc_fetch_req_f; // @[el2_ifu_bp_ctl.scala 125:81]
|
||||
wire [7:0] _GEN_2 = {{1'd0}, io_exu_mp_index}; // @[el2_ifu_bp_ctl.scala 125:117]
|
||||
wire _T_21 = _GEN_2 == btb_rd_addr_f; // @[el2_ifu_bp_ctl.scala 125:117]
|
||||
wire fetch_mp_collision_f = _T_20 & _T_21; // @[el2_ifu_bp_ctl.scala 125:102]
|
||||
wire _T_25 = _GEN_2 == btb_rd_addr_p1_f; // @[el2_ifu_bp_ctl.scala 126:123]
|
||||
wire fetch_mp_collision_p1_f = _T_20 & _T_25; // @[el2_ifu_bp_ctl.scala 126:108]
|
||||
reg exu_mp_way_f; // @[el2_ifu_bp_ctl.scala 130:29]
|
||||
reg exu_flush_final_d1; // @[el2_ifu_bp_ctl.scala 131:35]
|
||||
wire [127:0] mp_wrindex_dec = 128'h0 << io_exu_mp_index; // @[el2_ifu_bp_ctl.scala 184:38]
|
||||
wire [255:0] fetch_wrindex_dec = 256'h0 << btb_rd_addr_f; // @[el2_ifu_bp_ctl.scala 185:41]
|
||||
wire [255:0] fetch_wrindex_p1_dec = 256'h0 << btb_rd_addr_p1_f; // @[el2_ifu_bp_ctl.scala 186:44]
|
||||
wire [255:0] _T_135 = exu_mp_valid ? 256'hffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffff : 256'h0; // @[Bitwise.scala 72:12]
|
||||
wire [255:0] _GEN_4 = {{128'd0}, mp_wrindex_dec}; // @[el2_ifu_bp_ctl.scala 187:36]
|
||||
wire [255:0] mp_wrlru_b0 = _GEN_4 & _T_135; // @[el2_ifu_bp_ctl.scala 187:36]
|
||||
wire [255:0] btb_lru_b0_hold = ~mp_wrlru_b0; // @[el2_ifu_bp_ctl.scala 196:25]
|
||||
wire _T_161 = ~io_exu_mp_pkt_way; // @[el2_ifu_bp_ctl.scala 200:33]
|
||||
wire [255:0] _T_164 = _T_161 ? mp_wrlru_b0 : 256'h0; // @[Mux.scala 27:72]
|
||||
reg [255:0] btb_lru_b0_f; // @[Reg.scala 27:20]
|
||||
wire [255:0] _T_170 = btb_lru_b0_hold & btb_lru_b0_f; // @[el2_ifu_bp_ctl.scala 202:71]
|
||||
wire [255:0] btb_lru_b0_ns = _T_164 | _T_170; // @[el2_ifu_bp_ctl.scala 202:53]
|
||||
wire [255:0] _T_172 = fetch_wrindex_dec & btb_lru_b0_f; // @[el2_ifu_bp_ctl.scala 204:78]
|
||||
wire _T_173 = |_T_172; // @[el2_ifu_bp_ctl.scala 204:94]
|
||||
wire btb_lru_rd_f = fetch_mp_collision_f ? exu_mp_way_f : _T_173; // @[el2_ifu_bp_ctl.scala 204:25]
|
||||
wire [255:0] _T_175 = fetch_wrindex_p1_dec & btb_lru_b0_f; // @[el2_ifu_bp_ctl.scala 205:87]
|
||||
wire _T_176 = |_T_175; // @[el2_ifu_bp_ctl.scala 205:103]
|
||||
wire btb_lru_rd_p1_f = fetch_mp_collision_p1_f ? exu_mp_way_f : _T_176; // @[el2_ifu_bp_ctl.scala 205:28]
|
||||
wire [1:0] _T_179 = {btb_lru_rd_f,btb_lru_rd_f}; // @[Cat.scala 29:58]
|
||||
wire [1:0] _T_182 = {btb_lru_rd_p1_f,btb_lru_rd_f}; // @[Cat.scala 29:58]
|
||||
wire [1:0] _T_183 = _T_129 ? _T_179 : 2'h0; // @[Mux.scala 27:72]
|
||||
wire [1:0] _T_184 = io_ifc_fetch_addr_f[1] ? _T_182 : 2'h0; // @[Mux.scala 27:72]
|
||||
wire _T_199 = io_ifc_fetch_req_f | exu_mp_valid; // @[el2_ifu_bp_ctl.scala 215:75]
|
||||
wire _T_223 = ~leak_one_f_d1; // @[el2_ifu_bp_ctl.scala 229:79]
|
||||
reg [7:0] fghr; // @[el2_ifu_bp_ctl.scala 277:18]
|
||||
wire _T_307 = ~exu_flush_final_d1; // @[el2_ifu_bp_ctl.scala 274:6]
|
||||
wire _T_308 = _T_307 & io_ifc_fetch_req_f; // @[el2_ifu_bp_ctl.scala 274:26]
|
||||
wire _T_309 = _T_308 & io_ic_hit_f; // @[el2_ifu_bp_ctl.scala 274:47]
|
||||
wire _T_311 = _T_309 & _T_223; // @[el2_ifu_bp_ctl.scala 274:61]
|
||||
wire _T_314 = io_ifc_fetch_req_f & io_ic_hit_f; // @[el2_ifu_bp_ctl.scala 275:49]
|
||||
wire _T_316 = _T_314 & _T_223; // @[el2_ifu_bp_ctl.scala 275:63]
|
||||
wire _T_317 = ~_T_316; // @[el2_ifu_bp_ctl.scala 275:28]
|
||||
wire _T_318 = _T_307 & _T_317; // @[el2_ifu_bp_ctl.scala 275:26]
|
||||
wire [7:0] _T_320 = exu_flush_final_d1 ? io_exu_mp_fghr : 8'h0; // @[Mux.scala 27:72]
|
||||
wire [7:0] _T_321 = _T_311 ? fghr : 8'h0; // @[Mux.scala 27:72]
|
||||
wire [7:0] _T_322 = _T_318 ? fghr : 8'h0; // @[Mux.scala 27:72]
|
||||
wire [7:0] _T_323 = _T_320 | _T_321; // @[Mux.scala 27:72]
|
||||
wire [7:0] fghr_ns = _T_323 | _T_322; // @[Mux.scala 27:72]
|
||||
assign io_ifu_bp_hit_taken_f = 1'h0; // @[el2_ifu_bp_ctl.scala 42:25]
|
||||
assign io_ifu_bp_btb_target_f = 31'h0; // @[el2_ifu_bp_ctl.scala 43:26]
|
||||
assign io_ifu_bp_inst_mask_f = 1'h0; // @[el2_ifu_bp_ctl.scala 44:25]
|
||||
assign io_ifu_bp_fghr_f = 8'h0; // @[el2_ifu_bp_ctl.scala 45:20]
|
||||
assign io_ifu_bp_way_f = 2'h0; // @[el2_ifu_bp_ctl.scala 46:19]
|
||||
assign io_ifu_bp_ret_f = 2'h0; // @[el2_ifu_bp_ctl.scala 47:19]
|
||||
assign io_ifu_bp_hist1_f = 2'h0; // @[el2_ifu_bp_ctl.scala 48:21]
|
||||
assign io_ifu_bp_hist0_f = 2'h0; // @[el2_ifu_bp_ctl.scala 49:21]
|
||||
assign io_ifu_bp_pc4_f = 2'h0; // @[el2_ifu_bp_ctl.scala 50:19]
|
||||
assign io_ifu_bp_valid_f = 2'h0; // @[el2_ifu_bp_ctl.scala 51:21]
|
||||
assign io_ifu_bp_fghr_f = fghr; // @[el2_ifu_bp_ctl.scala 45:20 el2_ifu_bp_ctl.scala 278:20]
|
||||
assign io_ifu_bp_way_f = _T_183 | _T_184; // @[el2_ifu_bp_ctl.scala 46:19 el2_ifu_bp_ctl.scala 280:19]
|
||||
assign io_ifu_bp_ret_f = 2'h0; // @[el2_ifu_bp_ctl.scala 47:19 el2_ifu_bp_ctl.scala 286:19]
|
||||
assign io_ifu_bp_hist1_f = 2'h0; // @[el2_ifu_bp_ctl.scala 48:21 el2_ifu_bp_ctl.scala 281:21]
|
||||
assign io_ifu_bp_hist0_f = 2'h0; // @[el2_ifu_bp_ctl.scala 49:21 el2_ifu_bp_ctl.scala 282:21]
|
||||
assign io_ifu_bp_pc4_f = 2'h0; // @[el2_ifu_bp_ctl.scala 50:19 el2_ifu_bp_ctl.scala 283:19]
|
||||
assign io_ifu_bp_valid_f = 2'h0; // @[el2_ifu_bp_ctl.scala 51:21 el2_ifu_bp_ctl.scala 285:21]
|
||||
assign io_ifu_bp_poffset_f = 12'h0; // @[el2_ifu_bp_ctl.scala 52:23]
|
||||
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
||||
`define RANDOMIZE
|
||||
`endif
|
||||
`ifdef RANDOMIZE_INVALID_ASSIGN
|
||||
`define RANDOMIZE
|
||||
`endif
|
||||
`ifdef RANDOMIZE_REG_INIT
|
||||
`define RANDOMIZE
|
||||
`endif
|
||||
`ifdef RANDOMIZE_MEM_INIT
|
||||
`define RANDOMIZE
|
||||
`endif
|
||||
`ifndef RANDOM
|
||||
`define RANDOM $random
|
||||
`endif
|
||||
`ifdef RANDOMIZE_MEM_INIT
|
||||
integer initvar;
|
||||
`endif
|
||||
`ifndef SYNTHESIS
|
||||
`ifdef FIRRTL_BEFORE_INITIAL
|
||||
`FIRRTL_BEFORE_INITIAL
|
||||
`endif
|
||||
initial begin
|
||||
`ifdef RANDOMIZE
|
||||
`ifdef INIT_RANDOM
|
||||
`INIT_RANDOM
|
||||
`endif
|
||||
`ifndef VERILATOR
|
||||
`ifdef RANDOMIZE_DELAY
|
||||
#`RANDOMIZE_DELAY begin end
|
||||
`else
|
||||
#0.002 begin end
|
||||
`endif
|
||||
`endif
|
||||
`ifdef RANDOMIZE_REG_INIT
|
||||
_RAND_0 = {1{`RANDOM}};
|
||||
leak_one_f_d1 = _RAND_0[0:0];
|
||||
_RAND_1 = {1{`RANDOM}};
|
||||
exu_mp_way_f = _RAND_1[0:0];
|
||||
_RAND_2 = {1{`RANDOM}};
|
||||
exu_flush_final_d1 = _RAND_2[0:0];
|
||||
_RAND_3 = {8{`RANDOM}};
|
||||
btb_lru_b0_f = _RAND_3[255:0];
|
||||
_RAND_4 = {1{`RANDOM}};
|
||||
fghr = _RAND_4[7:0];
|
||||
`endif // RANDOMIZE_REG_INIT
|
||||
`endif // RANDOMIZE
|
||||
end // initial
|
||||
`ifdef FIRRTL_AFTER_INITIAL
|
||||
`FIRRTL_AFTER_INITIAL
|
||||
`endif
|
||||
`endif // SYNTHESIS
|
||||
always @(posedge clock) begin
|
||||
if (reset) begin
|
||||
leak_one_f_d1 <= 1'h0;
|
||||
end else begin
|
||||
leak_one_f_d1 <= leak_one_f;
|
||||
end
|
||||
if (reset) begin
|
||||
exu_mp_way_f <= 1'h0;
|
||||
end else begin
|
||||
exu_mp_way_f <= io_exu_mp_pkt_way;
|
||||
end
|
||||
if (reset) begin
|
||||
exu_flush_final_d1 <= 1'h0;
|
||||
end else begin
|
||||
exu_flush_final_d1 <= io_exu_flush_final;
|
||||
end
|
||||
if (reset) begin
|
||||
btb_lru_b0_f <= 256'h0;
|
||||
end else if (_T_199) begin
|
||||
btb_lru_b0_f <= btb_lru_b0_ns;
|
||||
end
|
||||
if (reset) begin
|
||||
fghr <= 8'h0;
|
||||
end else begin
|
||||
fghr <= fghr_ns;
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,187 +1,145 @@
|
|||
module el2_ifu_compress_ctl(
|
||||
input clock,
|
||||
input reset,
|
||||
input [15:0] io_in,
|
||||
input [31:0] io_in,
|
||||
output [31:0] io_out
|
||||
);
|
||||
wire _T_4 = ~io_in[14]; // @[el2_ifu_compress_ctl.scala 18:34]
|
||||
wire _T_5 = io_in[15] & _T_4; // @[el2_ifu_compress_ctl.scala 18:32]
|
||||
wire _T_7 = ~io_in[13]; // @[el2_ifu_compress_ctl.scala 18:47]
|
||||
wire _T_8 = _T_5 & _T_7; // @[el2_ifu_compress_ctl.scala 18:45]
|
||||
wire _T_10 = _T_8 & io_in[10]; // @[el2_ifu_compress_ctl.scala 18:58]
|
||||
wire _T_12 = ~io_in[6]; // @[el2_ifu_compress_ctl.scala 18:70]
|
||||
wire _T_13 = _T_10 & _T_12; // @[el2_ifu_compress_ctl.scala 18:68]
|
||||
wire _T_15 = ~io_in[5]; // @[el2_ifu_compress_ctl.scala 18:82]
|
||||
wire _T_16 = _T_13 & _T_15; // @[el2_ifu_compress_ctl.scala 18:80]
|
||||
wire _T_18 = _T_16 & io_in[0]; // @[el2_ifu_compress_ctl.scala 18:92]
|
||||
wire _T_22 = io_in[14] & _T_4; // @[el2_ifu_compress_ctl.scala 19:27]
|
||||
wire _T_25 = _T_22 & _T_7; // @[el2_ifu_compress_ctl.scala 19:40]
|
||||
wire _T_27 = ~io_in[11]; // @[el2_ifu_compress_ctl.scala 19:55]
|
||||
wire _T_28 = _T_25 & _T_27; // @[el2_ifu_compress_ctl.scala 19:53]
|
||||
wire _T_30 = _T_28 & io_in[10]; // @[el2_ifu_compress_ctl.scala 19:66]
|
||||
wire _T_32 = _T_30 & io_in[0]; // @[el2_ifu_compress_ctl.scala 19:76]
|
||||
wire _T_33 = _T_18 | _T_32; // @[el2_ifu_compress_ctl.scala 19:15]
|
||||
wire _T_38 = _T_4 & io_in[12]; // @[el2_ifu_compress_ctl.scala 20:25]
|
||||
wire _T_41 = _T_38 & _T_27; // @[el2_ifu_compress_ctl.scala 20:35]
|
||||
wire _T_43 = ~io_in[10]; // @[el2_ifu_compress_ctl.scala 20:50]
|
||||
wire _T_44 = _T_41 & _T_43; // @[el2_ifu_compress_ctl.scala 20:48]
|
||||
wire _T_46 = ~io_in[9]; // @[el2_ifu_compress_ctl.scala 20:63]
|
||||
wire _T_47 = _T_44 & _T_46; // @[el2_ifu_compress_ctl.scala 20:61]
|
||||
wire _T_49 = ~io_in[8]; // @[el2_ifu_compress_ctl.scala 20:75]
|
||||
wire _T_50 = _T_47 & _T_49; // @[el2_ifu_compress_ctl.scala 20:73]
|
||||
wire _T_52 = ~io_in[7]; // @[el2_ifu_compress_ctl.scala 20:87]
|
||||
wire _T_53 = _T_50 & _T_52; // @[el2_ifu_compress_ctl.scala 20:85]
|
||||
wire _T_56 = _T_53 & _T_12; // @[el2_ifu_compress_ctl.scala 20:97]
|
||||
wire _T_59 = _T_56 & _T_15; // @[el2_ifu_compress_ctl.scala 20:109]
|
||||
wire _T_61 = ~io_in[4]; // @[el2_ifu_compress_ctl.scala 21:16]
|
||||
wire _T_62 = _T_59 & _T_61; // @[el2_ifu_compress_ctl.scala 20:121]
|
||||
wire _T_64 = ~io_in[3]; // @[el2_ifu_compress_ctl.scala 21:28]
|
||||
wire _T_65 = _T_62 & _T_64; // @[el2_ifu_compress_ctl.scala 21:26]
|
||||
wire _T_67 = ~io_in[2]; // @[el2_ifu_compress_ctl.scala 21:40]
|
||||
wire _T_68 = _T_65 & _T_67; // @[el2_ifu_compress_ctl.scala 21:38]
|
||||
wire _T_70 = _T_68 & io_in[1]; // @[el2_ifu_compress_ctl.scala 21:50]
|
||||
wire _T_81 = _T_8 & _T_27; // @[el2_ifu_compress_ctl.scala 22:50]
|
||||
wire _T_83 = _T_81 & io_in[0]; // @[el2_ifu_compress_ctl.scala 22:63]
|
||||
wire _T_93 = _T_8 & _T_43; // @[el2_ifu_compress_ctl.scala 23:51]
|
||||
wire _T_95 = _T_93 & io_in[0]; // @[el2_ifu_compress_ctl.scala 23:64]
|
||||
wire _T_96 = _T_83 | _T_95; // @[el2_ifu_compress_ctl.scala 23:15]
|
||||
wire _T_105 = _T_8 & io_in[6]; // @[el2_ifu_compress_ctl.scala 24:51]
|
||||
wire _T_107 = _T_105 & io_in[0]; // @[el2_ifu_compress_ctl.scala 24:60]
|
||||
wire _T_108 = _T_96 | _T_107; // @[el2_ifu_compress_ctl.scala 24:15]
|
||||
wire _T_117 = _T_8 & io_in[5]; // @[el2_ifu_compress_ctl.scala 25:51]
|
||||
wire _T_119 = _T_117 & io_in[0]; // @[el2_ifu_compress_ctl.scala 25:60]
|
||||
wire _T_120 = _T_108 | _T_119; // @[el2_ifu_compress_ctl.scala 25:15]
|
||||
wire _T_131 = _T_105 & io_in[5]; // @[el2_ifu_compress_ctl.scala 26:59]
|
||||
wire _T_133 = _T_131 & io_in[0]; // @[el2_ifu_compress_ctl.scala 26:68]
|
||||
wire _T_146 = _T_133 | _T_83; // @[el2_ifu_compress_ctl.scala 27:15]
|
||||
wire _T_159 = _T_146 | _T_95; // @[el2_ifu_compress_ctl.scala 28:15]
|
||||
wire _T_161 = ~io_in[15]; // @[el2_ifu_compress_ctl.scala 29:17]
|
||||
wire _T_164 = _T_161 & _T_4; // @[el2_ifu_compress_ctl.scala 29:28]
|
||||
wire _T_166 = _T_164 & io_in[1]; // @[el2_ifu_compress_ctl.scala 29:41]
|
||||
wire _T_167 = _T_159 | _T_166; // @[el2_ifu_compress_ctl.scala 29:15]
|
||||
wire _T_170 = io_in[15] & io_in[14]; // @[el2_ifu_compress_ctl.scala 29:62]
|
||||
wire _T_172 = _T_170 & io_in[13]; // @[el2_ifu_compress_ctl.scala 29:72]
|
||||
wire _T_173 = _T_167 | _T_172; // @[el2_ifu_compress_ctl.scala 29:51]
|
||||
wire _T_234 = _T_5 & _T_12; // @[el2_ifu_compress_ctl.scala 34:37]
|
||||
wire _T_237 = _T_234 & _T_15; // @[el2_ifu_compress_ctl.scala 34:49]
|
||||
wire _T_240 = _T_237 & _T_61; // @[el2_ifu_compress_ctl.scala 34:61]
|
||||
wire _T_243 = _T_240 & _T_64; // @[el2_ifu_compress_ctl.scala 34:73]
|
||||
wire _T_246 = _T_243 & _T_67; // @[el2_ifu_compress_ctl.scala 34:85]
|
||||
wire _T_248 = ~io_in[0]; // @[el2_ifu_compress_ctl.scala 34:99]
|
||||
wire _T_249 = _T_246 & _T_248; // @[el2_ifu_compress_ctl.scala 34:97]
|
||||
wire _T_253 = _T_4 & io_in[13]; // @[el2_ifu_compress_ctl.scala 35:28]
|
||||
wire _T_254 = _T_249 | _T_253; // @[el2_ifu_compress_ctl.scala 35:15]
|
||||
wire _T_259 = _T_170 & io_in[0]; // @[el2_ifu_compress_ctl.scala 35:60]
|
||||
wire _T_260 = _T_254 | _T_259; // @[el2_ifu_compress_ctl.scala 35:39]
|
||||
wire _T_264 = io_in[15] & _T_248; // @[el2_ifu_compress_ctl.scala 35:80]
|
||||
wire _T_267 = io_in[15] & io_in[11]; // @[el2_ifu_compress_ctl.scala 36:25]
|
||||
wire _T_269 = _T_267 & io_in[10]; // @[el2_ifu_compress_ctl.scala 36:35]
|
||||
wire _T_270 = _T_264 | _T_269; // @[el2_ifu_compress_ctl.scala 36:15]
|
||||
wire _T_274 = io_in[13] & _T_49; // @[el2_ifu_compress_ctl.scala 36:57]
|
||||
wire _T_275 = _T_270 | _T_274; // @[el2_ifu_compress_ctl.scala 36:46]
|
||||
wire _T_280 = _T_275 | _T_274; // @[el2_ifu_compress_ctl.scala 37:15]
|
||||
wire _T_283 = io_in[13] & io_in[7]; // @[el2_ifu_compress_ctl.scala 37:47]
|
||||
wire _T_284 = _T_280 | _T_283; // @[el2_ifu_compress_ctl.scala 37:37]
|
||||
wire _T_287 = io_in[13] & io_in[9]; // @[el2_ifu_compress_ctl.scala 37:66]
|
||||
wire _T_288 = _T_284 | _T_287; // @[el2_ifu_compress_ctl.scala 37:56]
|
||||
wire _T_291 = io_in[13] & io_in[10]; // @[el2_ifu_compress_ctl.scala 37:85]
|
||||
wire _T_292 = _T_288 | _T_291; // @[el2_ifu_compress_ctl.scala 37:75]
|
||||
wire _T_295 = io_in[13] & io_in[11]; // @[el2_ifu_compress_ctl.scala 38:25]
|
||||
wire _T_296 = _T_292 | _T_295; // @[el2_ifu_compress_ctl.scala 38:15]
|
||||
wire _T_300 = io_in[13] & _T_4; // @[el2_ifu_compress_ctl.scala 38:45]
|
||||
wire _T_301 = _T_296 | _T_300; // @[el2_ifu_compress_ctl.scala 38:35]
|
||||
wire _T_304 = io_in[14] & io_in[15]; // @[el2_ifu_compress_ctl.scala 38:68]
|
||||
wire _T_305 = _T_301 | _T_304; // @[el2_ifu_compress_ctl.scala 38:58]
|
||||
wire _T_310 = _T_4 & _T_27; // @[el2_ifu_compress_ctl.scala 39:25]
|
||||
wire _T_313 = _T_310 & _T_43; // @[el2_ifu_compress_ctl.scala 39:38]
|
||||
wire _T_316 = _T_313 & _T_46; // @[el2_ifu_compress_ctl.scala 39:51]
|
||||
wire _T_319 = _T_316 & _T_49; // @[el2_ifu_compress_ctl.scala 39:63]
|
||||
wire _T_322 = _T_319 & _T_52; // @[el2_ifu_compress_ctl.scala 39:75]
|
||||
wire _T_325 = _T_322 & _T_248; // @[el2_ifu_compress_ctl.scala 39:87]
|
||||
wire _T_333 = _T_164 & _T_248; // @[el2_ifu_compress_ctl.scala 40:41]
|
||||
wire _T_334 = _T_325 | _T_333; // @[el2_ifu_compress_ctl.scala 40:15]
|
||||
wire _T_338 = _T_4 & io_in[6]; // @[el2_ifu_compress_ctl.scala 40:66]
|
||||
wire _T_341 = _T_338 & _T_248; // @[el2_ifu_compress_ctl.scala 40:75]
|
||||
wire _T_342 = _T_334 | _T_341; // @[el2_ifu_compress_ctl.scala 40:53]
|
||||
wire _T_346 = _T_161 & io_in[14]; // @[el2_ifu_compress_ctl.scala 41:28]
|
||||
wire _T_348 = _T_346 & io_in[0]; // @[el2_ifu_compress_ctl.scala 41:38]
|
||||
wire _T_349 = _T_342 | _T_348; // @[el2_ifu_compress_ctl.scala 41:15]
|
||||
wire _T_353 = _T_4 & io_in[5]; // @[el2_ifu_compress_ctl.scala 41:60]
|
||||
wire _T_356 = _T_353 & _T_248; // @[el2_ifu_compress_ctl.scala 41:69]
|
||||
wire _T_357 = _T_349 | _T_356; // @[el2_ifu_compress_ctl.scala 41:47]
|
||||
wire _T_361 = _T_4 & io_in[4]; // @[el2_ifu_compress_ctl.scala 42:28]
|
||||
wire _T_364 = _T_361 & _T_248; // @[el2_ifu_compress_ctl.scala 42:37]
|
||||
wire _T_365 = _T_357 | _T_364; // @[el2_ifu_compress_ctl.scala 42:15]
|
||||
wire _T_370 = _T_4 & _T_7; // @[el2_ifu_compress_ctl.scala 42:64]
|
||||
wire _T_372 = _T_370 & io_in[0]; // @[el2_ifu_compress_ctl.scala 42:77]
|
||||
wire _T_373 = _T_365 | _T_372; // @[el2_ifu_compress_ctl.scala 42:50]
|
||||
wire _T_377 = _T_4 & io_in[3]; // @[el2_ifu_compress_ctl.scala 43:28]
|
||||
wire _T_380 = _T_377 & _T_248; // @[el2_ifu_compress_ctl.scala 43:37]
|
||||
wire _T_381 = _T_373 | _T_380; // @[el2_ifu_compress_ctl.scala 43:15]
|
||||
wire _T_385 = _T_4 & io_in[2]; // @[el2_ifu_compress_ctl.scala 43:64]
|
||||
wire _T_388 = _T_385 & _T_248; // @[el2_ifu_compress_ctl.scala 43:73]
|
||||
wire _T_389 = _T_381 | _T_388; // @[el2_ifu_compress_ctl.scala 43:50]
|
||||
wire _T_399 = _T_38 & io_in[11]; // @[el2_ifu_compress_ctl.scala 45:35]
|
||||
wire _T_402 = _T_399 & _T_12; // @[el2_ifu_compress_ctl.scala 45:45]
|
||||
wire _T_405 = _T_402 & _T_15; // @[el2_ifu_compress_ctl.scala 45:57]
|
||||
wire _T_408 = _T_405 & _T_61; // @[el2_ifu_compress_ctl.scala 45:69]
|
||||
wire _T_411 = _T_408 & _T_64; // @[el2_ifu_compress_ctl.scala 45:81]
|
||||
wire _T_414 = _T_411 & _T_67; // @[el2_ifu_compress_ctl.scala 45:93]
|
||||
wire _T_416 = _T_414 & io_in[1]; // @[el2_ifu_compress_ctl.scala 45:105]
|
||||
wire _T_422 = _T_38 & io_in[10]; // @[el2_ifu_compress_ctl.scala 46:38]
|
||||
wire _T_425 = _T_422 & _T_12; // @[el2_ifu_compress_ctl.scala 46:48]
|
||||
wire _T_428 = _T_425 & _T_15; // @[el2_ifu_compress_ctl.scala 46:60]
|
||||
wire _T_431 = _T_428 & _T_61; // @[el2_ifu_compress_ctl.scala 46:72]
|
||||
wire _T_434 = _T_431 & _T_64; // @[el2_ifu_compress_ctl.scala 46:84]
|
||||
wire _T_437 = _T_434 & _T_67; // @[el2_ifu_compress_ctl.scala 46:96]
|
||||
wire _T_439 = _T_437 & io_in[1]; // @[el2_ifu_compress_ctl.scala 46:108]
|
||||
wire _T_440 = _T_416 | _T_439; // @[el2_ifu_compress_ctl.scala 46:15]
|
||||
wire _T_446 = _T_38 & io_in[9]; // @[el2_ifu_compress_ctl.scala 47:38]
|
||||
wire _T_449 = _T_446 & _T_12; // @[el2_ifu_compress_ctl.scala 47:47]
|
||||
wire _T_452 = _T_449 & _T_15; // @[el2_ifu_compress_ctl.scala 47:59]
|
||||
wire _T_455 = _T_452 & _T_61; // @[el2_ifu_compress_ctl.scala 47:71]
|
||||
wire _T_458 = _T_455 & _T_64; // @[el2_ifu_compress_ctl.scala 47:83]
|
||||
wire _T_461 = _T_458 & _T_67; // @[el2_ifu_compress_ctl.scala 47:95]
|
||||
wire _T_463 = _T_461 & io_in[1]; // @[el2_ifu_compress_ctl.scala 47:107]
|
||||
wire _T_464 = _T_440 | _T_463; // @[el2_ifu_compress_ctl.scala 47:15]
|
||||
wire _T_470 = _T_38 & io_in[8]; // @[el2_ifu_compress_ctl.scala 48:38]
|
||||
wire _T_473 = _T_470 & _T_12; // @[el2_ifu_compress_ctl.scala 48:47]
|
||||
wire _T_476 = _T_473 & _T_15; // @[el2_ifu_compress_ctl.scala 48:59]
|
||||
wire _T_479 = _T_476 & _T_61; // @[el2_ifu_compress_ctl.scala 48:71]
|
||||
wire _T_482 = _T_479 & _T_64; // @[el2_ifu_compress_ctl.scala 48:83]
|
||||
wire _T_485 = _T_482 & _T_67; // @[el2_ifu_compress_ctl.scala 48:95]
|
||||
wire _T_487 = _T_485 & io_in[1]; // @[el2_ifu_compress_ctl.scala 48:107]
|
||||
wire _T_488 = _T_464 | _T_487; // @[el2_ifu_compress_ctl.scala 48:15]
|
||||
wire _T_494 = _T_38 & io_in[7]; // @[el2_ifu_compress_ctl.scala 49:38]
|
||||
wire _T_497 = _T_494 & _T_12; // @[el2_ifu_compress_ctl.scala 49:47]
|
||||
wire _T_500 = _T_497 & _T_15; // @[el2_ifu_compress_ctl.scala 49:59]
|
||||
wire _T_503 = _T_500 & _T_61; // @[el2_ifu_compress_ctl.scala 49:71]
|
||||
wire _T_506 = _T_503 & _T_64; // @[el2_ifu_compress_ctl.scala 49:83]
|
||||
wire _T_509 = _T_506 & _T_67; // @[el2_ifu_compress_ctl.scala 49:95]
|
||||
wire _T_511 = _T_509 & io_in[1]; // @[el2_ifu_compress_ctl.scala 49:107]
|
||||
wire _T_512 = _T_488 | _T_511; // @[el2_ifu_compress_ctl.scala 49:15]
|
||||
wire _T_518 = ~io_in[12]; // @[el2_ifu_compress_ctl.scala 50:40]
|
||||
wire _T_519 = _T_5 & _T_518; // @[el2_ifu_compress_ctl.scala 50:38]
|
||||
wire _T_522 = _T_519 & _T_12; // @[el2_ifu_compress_ctl.scala 50:51]
|
||||
wire _T_525 = _T_522 & _T_15; // @[el2_ifu_compress_ctl.scala 50:63]
|
||||
wire _T_528 = _T_525 & _T_61; // @[el2_ifu_compress_ctl.scala 50:75]
|
||||
wire _T_531 = _T_528 & _T_64; // @[el2_ifu_compress_ctl.scala 50:87]
|
||||
wire _T_534 = _T_531 & _T_67; // @[el2_ifu_compress_ctl.scala 50:99]
|
||||
wire _T_537 = _T_534 & _T_248; // @[el2_ifu_compress_ctl.scala 50:111]
|
||||
wire _T_538 = _T_512 | _T_537; // @[el2_ifu_compress_ctl.scala 50:15]
|
||||
wire _T_542 = _T_161 & io_in[13]; // @[el2_ifu_compress_ctl.scala 51:28]
|
||||
wire _T_545 = _T_542 & _T_49; // @[el2_ifu_compress_ctl.scala 51:38]
|
||||
wire _T_546 = _T_538 | _T_545; // @[el2_ifu_compress_ctl.scala 51:15]
|
||||
wire _T_552 = _T_542 & io_in[7]; // @[el2_ifu_compress_ctl.scala 51:75]
|
||||
wire _T_553 = _T_546 | _T_552; // @[el2_ifu_compress_ctl.scala 51:51]
|
||||
wire _T_559 = _T_542 & io_in[9]; // @[el2_ifu_compress_ctl.scala 51:109]
|
||||
wire _T_560 = _T_553 | _T_559; // @[el2_ifu_compress_ctl.scala 51:85]
|
||||
wire _T_566 = _T_542 & io_in[10]; // @[el2_ifu_compress_ctl.scala 52:38]
|
||||
wire _T_567 = _T_560 | _T_566; // @[el2_ifu_compress_ctl.scala 52:15]
|
||||
wire _T_573 = _T_542 & io_in[11]; // @[el2_ifu_compress_ctl.scala 52:73]
|
||||
wire _T_574 = _T_567 | _T_573; // @[el2_ifu_compress_ctl.scala 52:49]
|
||||
wire _T_579 = _T_574 | _T_253; // @[el2_ifu_compress_ctl.scala 52:84]
|
||||
wire [11:0] _T_586 = {5'h0,_T_260,_T_305,_T_389,_T_253,_T_579,2'h3}; // @[Cat.scala 29:58]
|
||||
wire [19:0] _T_593 = {1'h0,_T_33,9'h0,_T_70,5'h0,_T_120,_T_173,_T_173}; // @[Cat.scala 29:58]
|
||||
assign io_out = {_T_593,_T_586}; // @[el2_ifu_compress_ctl.scala 111:10]
|
||||
wire _T_1 = io_in[1:0] != 2'h3; // @[el2_ifu_compress_ctl.scala 192:26]
|
||||
wire _T_3 = |io_in[12:5]; // @[el2_ifu_compress_ctl.scala 48:29]
|
||||
wire [6:0] _T_4 = _T_3 ? 7'h13 : 7'h1f; // @[el2_ifu_compress_ctl.scala 48:20]
|
||||
wire [29:0] _T_18 = {io_in[10:7],io_in[12:11],io_in[5],io_in[6],2'h0,5'h2,3'h0,2'h1,io_in[4:2],_T_4}; // @[Cat.scala 29:58]
|
||||
wire [7:0] _T_28 = {io_in[6:5],io_in[12:10],3'h0}; // @[Cat.scala 29:58]
|
||||
wire [27:0] _T_36 = {io_in[6:5],io_in[12:10],3'h0,2'h1,io_in[9:7],3'h3,2'h1,io_in[4:2],7'h7}; // @[Cat.scala 29:58]
|
||||
wire [6:0] _T_50 = {io_in[5],io_in[12:10],io_in[6],2'h0}; // @[Cat.scala 29:58]
|
||||
wire [26:0] _T_58 = {io_in[5],io_in[12:10],io_in[6],2'h0,2'h1,io_in[9:7],3'h2,2'h1,io_in[4:2],7'h3}; // @[Cat.scala 29:58]
|
||||
wire [27:0] _T_78 = {io_in[6:5],io_in[12:10],3'h0,2'h1,io_in[9:7],3'h3,2'h1,io_in[4:2],7'h3}; // @[Cat.scala 29:58]
|
||||
wire [26:0] _T_109 = {_T_50[6:5],2'h1,io_in[4:2],2'h1,io_in[9:7],3'h2,_T_50[4:0],7'h3f}; // @[Cat.scala 29:58]
|
||||
wire [27:0] _T_136 = {_T_28[7:5],2'h1,io_in[4:2],2'h1,io_in[9:7],3'h3,_T_28[4:0],7'h27}; // @[Cat.scala 29:58]
|
||||
wire [26:0] _T_167 = {_T_50[6:5],2'h1,io_in[4:2],2'h1,io_in[9:7],3'h2,_T_50[4:0],7'h23}; // @[Cat.scala 29:58]
|
||||
wire [27:0] _T_194 = {_T_28[7:5],2'h1,io_in[4:2],2'h1,io_in[9:7],3'h3,_T_28[4:0],7'h23}; // @[Cat.scala 29:58]
|
||||
wire [6:0] _T_205 = io_in[12] ? 7'h7f : 7'h0; // @[Bitwise.scala 72:12]
|
||||
wire [11:0] _T_207 = {_T_205,io_in[6:2]}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_213 = {_T_205,io_in[6:2],io_in[11:7],3'h0,io_in[11:7],7'h13}; // @[Cat.scala 29:58]
|
||||
wire _T_221 = |io_in[11:7]; // @[el2_ifu_compress_ctl.scala 72:24]
|
||||
wire [6:0] _T_222 = _T_221 ? 7'h1b : 7'h1f; // @[el2_ifu_compress_ctl.scala 72:20]
|
||||
wire [31:0] _T_233 = {_T_205,io_in[6:2],io_in[11:7],3'h0,io_in[11:7],_T_222}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_249 = {_T_205,io_in[6:2],5'h0,3'h0,io_in[11:7],7'h13}; // @[Cat.scala 29:58]
|
||||
wire _T_260 = |_T_207; // @[el2_ifu_compress_ctl.scala 85:29]
|
||||
wire [6:0] _T_261 = _T_260 ? 7'h37 : 7'h3f; // @[el2_ifu_compress_ctl.scala 85:20]
|
||||
wire [14:0] _T_264 = io_in[12] ? 15'h7fff : 15'h0; // @[Bitwise.scala 72:12]
|
||||
wire [31:0] _T_267 = {_T_264,io_in[6:2],12'h0}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_271 = {_T_267[31:12],io_in[11:7],_T_261}; // @[Cat.scala 29:58]
|
||||
wire _T_279 = io_in[11:7] == 5'h0; // @[el2_ifu_compress_ctl.scala 87:14]
|
||||
wire _T_281 = io_in[11:7] == 5'h2; // @[el2_ifu_compress_ctl.scala 87:27]
|
||||
wire _T_282 = _T_279 | _T_281; // @[el2_ifu_compress_ctl.scala 87:21]
|
||||
wire [6:0] _T_289 = _T_260 ? 7'h13 : 7'h1f; // @[el2_ifu_compress_ctl.scala 81:20]
|
||||
wire [2:0] _T_292 = io_in[12] ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12]
|
||||
wire [31:0] _T_307 = {_T_292,io_in[4:3],io_in[5],io_in[2],io_in[6],4'h0,io_in[11:7],3'h0,io_in[11:7],_T_289}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_314_bits = _T_282 ? _T_307 : _T_271; // @[el2_ifu_compress_ctl.scala 87:10]
|
||||
wire [25:0] _T_325 = {io_in[12],io_in[6:2],2'h1,io_in[9:7],3'h5,2'h1,io_in[9:7],7'h13}; // @[Cat.scala 29:58]
|
||||
wire [30:0] _GEN_172 = {{5'd0}, _T_325}; // @[el2_ifu_compress_ctl.scala 94:23]
|
||||
wire [30:0] _T_337 = _GEN_172 | 31'h40000000; // @[el2_ifu_compress_ctl.scala 94:23]
|
||||
wire [31:0] _T_350 = {_T_205,io_in[6:2],2'h1,io_in[9:7],3'h7,2'h1,io_in[9:7],7'h13}; // @[Cat.scala 29:58]
|
||||
wire [2:0] _T_354 = {io_in[12],io_in[6:5]}; // @[Cat.scala 29:58]
|
||||
wire _T_356 = io_in[6:5] == 2'h0; // @[el2_ifu_compress_ctl.scala 98:30]
|
||||
wire [30:0] _T_357 = _T_356 ? 31'h40000000 : 31'h0; // @[el2_ifu_compress_ctl.scala 98:22]
|
||||
wire [6:0] _T_359 = io_in[12] ? 7'h3b : 7'h33; // @[el2_ifu_compress_ctl.scala 99:22]
|
||||
wire [2:0] _GEN_1 = 3'h1 == _T_354 ? 3'h4 : 3'h0; // @[Cat.scala 29:58]
|
||||
wire [2:0] _GEN_2 = 3'h2 == _T_354 ? 3'h6 : _GEN_1; // @[Cat.scala 29:58]
|
||||
wire [2:0] _GEN_3 = 3'h3 == _T_354 ? 3'h7 : _GEN_2; // @[Cat.scala 29:58]
|
||||
wire [2:0] _GEN_4 = 3'h4 == _T_354 ? 3'h0 : _GEN_3; // @[Cat.scala 29:58]
|
||||
wire [2:0] _GEN_5 = 3'h5 == _T_354 ? 3'h0 : _GEN_4; // @[Cat.scala 29:58]
|
||||
wire [2:0] _GEN_6 = 3'h6 == _T_354 ? 3'h2 : _GEN_5; // @[Cat.scala 29:58]
|
||||
wire [2:0] _GEN_7 = 3'h7 == _T_354 ? 3'h3 : _GEN_6; // @[Cat.scala 29:58]
|
||||
wire [24:0] _T_369 = {2'h1,io_in[4:2],2'h1,io_in[9:7],_GEN_7,2'h1,io_in[9:7],_T_359}; // @[Cat.scala 29:58]
|
||||
wire [30:0] _GEN_173 = {{6'd0}, _T_369}; // @[el2_ifu_compress_ctl.scala 100:43]
|
||||
wire [30:0] _T_370 = _GEN_173 | _T_357; // @[el2_ifu_compress_ctl.scala 100:43]
|
||||
wire [31:0] _T_371_0 = {{6'd0}, _T_325}; // @[el2_ifu_compress_ctl.scala 102:19 el2_ifu_compress_ctl.scala 102:19]
|
||||
wire [31:0] _T_371_1 = {{1'd0}, _T_337}; // @[el2_ifu_compress_ctl.scala 102:19 el2_ifu_compress_ctl.scala 102:19]
|
||||
wire [31:0] _GEN_9 = 2'h1 == io_in[11:10] ? _T_371_1 : _T_371_0; // @[el2_ifu_compress_ctl.scala 17:14]
|
||||
wire [31:0] _GEN_10 = 2'h2 == io_in[11:10] ? _T_350 : _GEN_9; // @[el2_ifu_compress_ctl.scala 17:14]
|
||||
wire [31:0] _T_371_3 = {{1'd0}, _T_370}; // @[el2_ifu_compress_ctl.scala 102:19 el2_ifu_compress_ctl.scala 102:19]
|
||||
wire [31:0] _GEN_11 = 2'h3 == io_in[11:10] ? _T_371_3 : _GEN_10; // @[el2_ifu_compress_ctl.scala 17:14]
|
||||
wire [9:0] _T_383 = io_in[12] ? 10'h3ff : 10'h0; // @[Bitwise.scala 72:12]
|
||||
wire [20:0] _T_398 = {_T_383,io_in[8],io_in[10:9],io_in[6],io_in[7],io_in[2],io_in[11],io_in[5:3],1'h0}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_461 = {_T_398[20],_T_398[10:1],_T_398[11],_T_398[19:12],5'h0,7'h6f}; // @[Cat.scala 29:58]
|
||||
wire [4:0] _T_470 = io_in[12] ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12]
|
||||
wire [12:0] _T_479 = {_T_470,io_in[6:5],io_in[2],io_in[11:10],io_in[4:3],1'h0}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_528 = {_T_479[12],_T_479[10:5],5'h0,2'h1,io_in[9:7],3'h0,_T_479[4:1],_T_479[11],7'h63}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_595 = {_T_479[12],_T_479[10:5],5'h0,2'h1,io_in[9:7],3'h1,_T_479[4:1],_T_479[11],7'h63}; // @[Cat.scala 29:58]
|
||||
wire [6:0] _T_602 = _T_221 ? 7'h3 : 7'h1f; // @[el2_ifu_compress_ctl.scala 108:23]
|
||||
wire [25:0] _T_611 = {io_in[12],io_in[6:2],io_in[11:7],3'h1,io_in[11:7],7'h13}; // @[Cat.scala 29:58]
|
||||
wire [28:0] _T_627 = {io_in[4:2],io_in[12],io_in[6:5],3'h0,5'h2,3'h3,io_in[11:7],7'h7}; // @[Cat.scala 29:58]
|
||||
wire [27:0] _T_642 = {io_in[3:2],io_in[12],io_in[6:4],2'h0,5'h2,3'h2,io_in[11:7],_T_602}; // @[Cat.scala 29:58]
|
||||
wire [28:0] _T_657 = {io_in[4:2],io_in[12],io_in[6:5],3'h0,5'h2,3'h3,io_in[11:7],_T_602}; // @[Cat.scala 29:58]
|
||||
wire [24:0] _T_667 = {io_in[6:2],5'h0,3'h0,io_in[11:7],7'h33}; // @[Cat.scala 29:58]
|
||||
wire [24:0] _T_678 = {io_in[6:2],io_in[11:7],3'h0,io_in[11:7],7'h33}; // @[Cat.scala 29:58]
|
||||
wire [24:0] _T_689 = {io_in[6:2],io_in[11:7],3'h0,12'h67}; // @[Cat.scala 29:58]
|
||||
wire [24:0] _T_691 = {_T_689[24:7],7'h1f}; // @[Cat.scala 29:58]
|
||||
wire [24:0] _T_694 = _T_221 ? _T_689 : _T_691; // @[el2_ifu_compress_ctl.scala 129:33]
|
||||
wire _T_700 = |io_in[6:2]; // @[el2_ifu_compress_ctl.scala 130:27]
|
||||
wire [31:0] _T_671_bits = {{7'd0}, _T_667}; // @[el2_ifu_compress_ctl.scala 16:19 el2_ifu_compress_ctl.scala 17:14]
|
||||
wire [31:0] _T_698_bits = {{7'd0}, _T_694}; // @[el2_ifu_compress_ctl.scala 16:19 el2_ifu_compress_ctl.scala 17:14]
|
||||
wire [31:0] _T_701_bits = _T_700 ? _T_671_bits : _T_698_bits; // @[el2_ifu_compress_ctl.scala 130:22]
|
||||
wire [24:0] _T_707 = {io_in[6:2],io_in[11:7],3'h0,12'he7}; // @[Cat.scala 29:58]
|
||||
wire [24:0] _T_709 = {_T_689[24:7],7'h73}; // @[Cat.scala 29:58]
|
||||
wire [24:0] _T_710 = _T_709 | 25'h100000; // @[el2_ifu_compress_ctl.scala 132:46]
|
||||
wire [24:0] _T_713 = _T_221 ? _T_707 : _T_710; // @[el2_ifu_compress_ctl.scala 133:33]
|
||||
wire [31:0] _T_683_bits = {{7'd0}, _T_678}; // @[el2_ifu_compress_ctl.scala 16:19 el2_ifu_compress_ctl.scala 17:14]
|
||||
wire [31:0] _T_717_bits = {{7'd0}, _T_713}; // @[el2_ifu_compress_ctl.scala 16:19 el2_ifu_compress_ctl.scala 17:14]
|
||||
wire [31:0] _T_720_bits = _T_700 ? _T_683_bits : _T_717_bits; // @[el2_ifu_compress_ctl.scala 134:25]
|
||||
wire [31:0] _T_722_bits = io_in[12] ? _T_720_bits : _T_701_bits; // @[el2_ifu_compress_ctl.scala 135:10]
|
||||
wire [8:0] _T_726 = {io_in[9:7],io_in[12:10],3'h0}; // @[Cat.scala 29:58]
|
||||
wire [28:0] _T_738 = {_T_726[8:5],io_in[6:2],5'h2,3'h3,_T_726[4:0],7'h27}; // @[Cat.scala 29:58]
|
||||
wire [7:0] _T_746 = {io_in[8:7],io_in[12:9],2'h0}; // @[Cat.scala 29:58]
|
||||
wire [27:0] _T_758 = {_T_746[7:5],io_in[6:2],5'h2,3'h2,_T_746[4:0],7'h23}; // @[Cat.scala 29:58]
|
||||
wire [28:0] _T_778 = {_T_726[8:5],io_in[6:2],5'h2,3'h3,_T_726[4:0],7'h23}; // @[Cat.scala 29:58]
|
||||
wire [4:0] _T_826 = {io_in[1:0],io_in[15:13]}; // @[Cat.scala 29:58]
|
||||
wire [31:0] _T_24_bits = {{2'd0}, _T_18}; // @[el2_ifu_compress_ctl.scala 16:19 el2_ifu_compress_ctl.scala 17:14]
|
||||
wire [31:0] _T_44_bits = {{4'd0}, _T_36}; // @[el2_ifu_compress_ctl.scala 16:19 el2_ifu_compress_ctl.scala 17:14]
|
||||
wire [31:0] _GEN_17 = 5'h1 == _T_826 ? _T_44_bits : _T_24_bits; // @[el2_ifu_compress_ctl.scala 195:18]
|
||||
wire [31:0] _T_66_bits = {{5'd0}, _T_58}; // @[el2_ifu_compress_ctl.scala 16:19 el2_ifu_compress_ctl.scala 17:14]
|
||||
wire [31:0] _GEN_22 = 5'h2 == _T_826 ? _T_66_bits : _GEN_17; // @[el2_ifu_compress_ctl.scala 195:18]
|
||||
wire [31:0] _T_86_bits = {{4'd0}, _T_78}; // @[el2_ifu_compress_ctl.scala 16:19 el2_ifu_compress_ctl.scala 17:14]
|
||||
wire [31:0] _GEN_27 = 5'h3 == _T_826 ? _T_86_bits : _GEN_22; // @[el2_ifu_compress_ctl.scala 195:18]
|
||||
wire [31:0] _T_117_bits = {{5'd0}, _T_109}; // @[el2_ifu_compress_ctl.scala 16:19 el2_ifu_compress_ctl.scala 17:14]
|
||||
wire [31:0] _GEN_32 = 5'h4 == _T_826 ? _T_117_bits : _GEN_27; // @[el2_ifu_compress_ctl.scala 195:18]
|
||||
wire [31:0] _T_144_bits = {{4'd0}, _T_136}; // @[el2_ifu_compress_ctl.scala 16:19 el2_ifu_compress_ctl.scala 17:14]
|
||||
wire [31:0] _GEN_37 = 5'h5 == _T_826 ? _T_144_bits : _GEN_32; // @[el2_ifu_compress_ctl.scala 195:18]
|
||||
wire [31:0] _T_175_bits = {{5'd0}, _T_167}; // @[el2_ifu_compress_ctl.scala 16:19 el2_ifu_compress_ctl.scala 17:14]
|
||||
wire [31:0] _GEN_42 = 5'h6 == _T_826 ? _T_175_bits : _GEN_37; // @[el2_ifu_compress_ctl.scala 195:18]
|
||||
wire [31:0] _T_202_bits = {{4'd0}, _T_194}; // @[el2_ifu_compress_ctl.scala 16:19 el2_ifu_compress_ctl.scala 17:14]
|
||||
wire [31:0] _GEN_47 = 5'h7 == _T_826 ? _T_202_bits : _GEN_42; // @[el2_ifu_compress_ctl.scala 195:18]
|
||||
wire [31:0] _GEN_52 = 5'h8 == _T_826 ? _T_213 : _GEN_47; // @[el2_ifu_compress_ctl.scala 195:18]
|
||||
wire [31:0] _GEN_57 = 5'h9 == _T_826 ? _T_233 : _GEN_52; // @[el2_ifu_compress_ctl.scala 195:18]
|
||||
wire [31:0] _GEN_62 = 5'ha == _T_826 ? _T_249 : _GEN_57; // @[el2_ifu_compress_ctl.scala 195:18]
|
||||
wire [31:0] _GEN_67 = 5'hb == _T_826 ? _T_314_bits : _GEN_62; // @[el2_ifu_compress_ctl.scala 195:18]
|
||||
wire [31:0] _GEN_72 = 5'hc == _T_826 ? _GEN_11 : _GEN_67; // @[el2_ifu_compress_ctl.scala 195:18]
|
||||
wire [31:0] _GEN_77 = 5'hd == _T_826 ? _T_461 : _GEN_72; // @[el2_ifu_compress_ctl.scala 195:18]
|
||||
wire [31:0] _GEN_82 = 5'he == _T_826 ? _T_528 : _GEN_77; // @[el2_ifu_compress_ctl.scala 195:18]
|
||||
wire [31:0] _GEN_87 = 5'hf == _T_826 ? _T_595 : _GEN_82; // @[el2_ifu_compress_ctl.scala 195:18]
|
||||
wire [31:0] _T_616_bits = {{6'd0}, _T_611}; // @[el2_ifu_compress_ctl.scala 16:19 el2_ifu_compress_ctl.scala 17:14]
|
||||
wire [31:0] _GEN_92 = 5'h10 == _T_826 ? _T_616_bits : _GEN_87; // @[el2_ifu_compress_ctl.scala 195:18]
|
||||
wire [31:0] _T_631_bits = {{3'd0}, _T_627}; // @[el2_ifu_compress_ctl.scala 16:19 el2_ifu_compress_ctl.scala 17:14]
|
||||
wire [31:0] _GEN_97 = 5'h11 == _T_826 ? _T_631_bits : _GEN_92; // @[el2_ifu_compress_ctl.scala 195:18]
|
||||
wire [31:0] _T_646_bits = {{4'd0}, _T_642}; // @[el2_ifu_compress_ctl.scala 16:19 el2_ifu_compress_ctl.scala 17:14]
|
||||
wire [31:0] _GEN_102 = 5'h12 == _T_826 ? _T_646_bits : _GEN_97; // @[el2_ifu_compress_ctl.scala 195:18]
|
||||
wire [31:0] _T_661_bits = {{3'd0}, _T_657}; // @[el2_ifu_compress_ctl.scala 16:19 el2_ifu_compress_ctl.scala 17:14]
|
||||
wire [31:0] _GEN_107 = 5'h13 == _T_826 ? _T_661_bits : _GEN_102; // @[el2_ifu_compress_ctl.scala 195:18]
|
||||
wire [31:0] _GEN_112 = 5'h14 == _T_826 ? _T_722_bits : _GEN_107; // @[el2_ifu_compress_ctl.scala 195:18]
|
||||
wire [31:0] _T_742_bits = {{3'd0}, _T_738}; // @[el2_ifu_compress_ctl.scala 16:19 el2_ifu_compress_ctl.scala 17:14]
|
||||
wire [31:0] _GEN_117 = 5'h15 == _T_826 ? _T_742_bits : _GEN_112; // @[el2_ifu_compress_ctl.scala 195:18]
|
||||
wire [31:0] _T_762_bits = {{4'd0}, _T_758}; // @[el2_ifu_compress_ctl.scala 16:19 el2_ifu_compress_ctl.scala 17:14]
|
||||
wire [31:0] _GEN_122 = 5'h16 == _T_826 ? _T_762_bits : _GEN_117; // @[el2_ifu_compress_ctl.scala 195:18]
|
||||
wire [31:0] _T_782_bits = {{3'd0}, _T_778}; // @[el2_ifu_compress_ctl.scala 16:19 el2_ifu_compress_ctl.scala 17:14]
|
||||
wire [31:0] _GEN_127 = 5'h17 == _T_826 ? _T_782_bits : _GEN_122; // @[el2_ifu_compress_ctl.scala 195:18]
|
||||
wire [31:0] _GEN_132 = 5'h18 == _T_826 ? io_in : _GEN_127; // @[el2_ifu_compress_ctl.scala 195:18]
|
||||
wire [31:0] _GEN_137 = 5'h19 == _T_826 ? io_in : _GEN_132; // @[el2_ifu_compress_ctl.scala 195:18]
|
||||
wire [31:0] _GEN_142 = 5'h1a == _T_826 ? io_in : _GEN_137; // @[el2_ifu_compress_ctl.scala 195:18]
|
||||
wire [31:0] _GEN_147 = 5'h1b == _T_826 ? io_in : _GEN_142; // @[el2_ifu_compress_ctl.scala 195:18]
|
||||
wire [31:0] _GEN_152 = 5'h1c == _T_826 ? io_in : _GEN_147; // @[el2_ifu_compress_ctl.scala 195:18]
|
||||
wire [31:0] _GEN_157 = 5'h1d == _T_826 ? io_in : _GEN_152; // @[el2_ifu_compress_ctl.scala 195:18]
|
||||
wire [31:0] _GEN_162 = 5'h1e == _T_826 ? io_in : _GEN_157; // @[el2_ifu_compress_ctl.scala 195:18]
|
||||
wire [31:0] _GEN_167 = 5'h1f == _T_826 ? io_in : _GEN_162; // @[el2_ifu_compress_ctl.scala 195:18]
|
||||
assign io_out = _T_1 ? 32'h0 : _GEN_167; // @[el2_ifu_compress_ctl.scala 195:12]
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -95,7 +95,7 @@ class el2_ifu_aln_ctl extends Module with el2_lib {
|
|||
|
||||
val aligndata = Mux1H(Seq(f0val(0).asBool -> q0final, (~f0val(1) & f0val(0)).asBool -> Cat(q1final,q0final)))
|
||||
|
||||
val decompressed = Module(new el2_ifu_compress(32, true))
|
||||
val decompressed = Module(new el2_ifu_compress_ctl(32, true))
|
||||
|
||||
decompressed.io.in := aligndata
|
||||
|
||||
|
|
|
|||
|
|
@ -175,10 +175,10 @@ class el2_ifu_bp_ctl extends Module with el2_lib {
|
|||
|
||||
// Making virtual banks, made bit 1 of the pc to check
|
||||
val btb_vbank0_rd_data_f = Mux1H(Seq(~io.ifc_fetch_addr_f(1)->btb_bank0e_rd_data_f,
|
||||
io.ifc_fetch_addr_f(1)->btb_bank0o_rd_data_f))
|
||||
io.ifc_fetch_addr_f(1)->btb_bank0o_rd_data_f))
|
||||
|
||||
val btb_vbank1_rd_data_f = Mux1H(Seq(~io.ifc_fetch_addr_f(0)->btb_bank0o_rd_data_f,
|
||||
io.ifc_fetch_addr_f(0)->btb_bank0e_rd_data_p1_f))
|
||||
val btb_vbank1_rd_data_f = Mux1H(Seq(~io.ifc_fetch_addr_f(1)->btb_bank0o_rd_data_f,
|
||||
io.ifc_fetch_addr_f(1)->btb_bank0e_rd_data_p1_f))
|
||||
|
||||
// Implimenting the LRU for a 2-way BTB
|
||||
val mp_wrindex_dec = 1.U(LRU_SIZE) << exu_mp_addr
|
||||
|
|
@ -198,20 +198,113 @@ class el2_ifu_bp_ctl extends Module with el2_lib {
|
|||
val use_mp_way_p1 = fetch_mp_collision_p1_f
|
||||
|
||||
val btb_lru_b0_ns = Mux1H(Seq(~exu_mp_way.asBool->mp_wrlru_b0,
|
||||
tag_match_way0_f.asBool->fetch_wrlru_b0,tag_match_way0_p1_f.asBool->fetch_wrlru_p1_b0)) | btb_lru_b0_hold & btb_lru_b0_f
|
||||
tag_match_way0_f.asBool->fetch_wrlru_b0,
|
||||
tag_match_way0_p1_f.asBool->fetch_wrlru_p1_b0)) | btb_lru_b0_hold & btb_lru_b0_f
|
||||
|
||||
val btb_lru_rd_f = Mux(use_mp_way.asBool, exu_mp_way_f, (fetch_wrindex_dec & btb_lru_b0_f).orR)
|
||||
val btb_lru_rd_p1_f = Mux(use_mp_way_p1.asBool, exu_mp_way_f, (fetch_wrindex_p1_dec & btb_lru_b0_f).orR)
|
||||
|
||||
val btb_vlru_rd_f = Mux1H(Seq(~io.ifc_fetch_addr_f(1).asBool->Cat(btb_lru_rd_f, btb_lru_rd_f),
|
||||
io.ifc_fetch_addr_f(1).asBool->Cat(btb_lru_rd_p1_f, btb_lru_rd_f)))
|
||||
val btb_vlru_rd_f = Mux1H(Seq(!io.ifc_fetch_addr_f(1) -> Cat(btb_lru_rd_f, btb_lru_rd_f),
|
||||
io.ifc_fetch_addr_f(1).asBool -> Cat(btb_lru_rd_p1_f, btb_lru_rd_f)))
|
||||
|
||||
val tag_match_vway1_expanded_f = Mux1H(Seq(~io.ifc_fetch_addr_f(1).asBool->tag_match_way1_expanded_f,
|
||||
io.ifc_fetch_addr_f(1).asBool->Cat(tag_match_way1_expanded_p1_f(0),tag_match_way1_expanded_f(1))))
|
||||
|
||||
val way_raw = tag_match_vway1_expanded_f | (~vwayhit_f & btb_vlru_rd_f)
|
||||
|
||||
//val btb_lru_b0_f = RegNext(btb_lru_b0_ns, init = 0.U)
|
||||
btb_lru_b0_f := RegEnable(btb_lru_b0_ns, init = 0.U, (io.ifc_fetch_req_f|exu_mp_valid).asBool)
|
||||
|
||||
val eoc_near = io.ifc_fetch_addr_f(ICACHE_BEAT_ADDR_HI, 3).andR
|
||||
eoc_mask := !eoc_near | !io.ifc_fetch_addr_f(2,1).orR()
|
||||
val btb_sel_data_f = WireInit(UInt(17.W), init = 0.U)
|
||||
val hist1_raw = WireInit(UInt(2.W), init = 0.U)
|
||||
val btb_rd_tgt_f = btb_sel_data_f(16,5)
|
||||
val btb_rd_pc4_f = btb_sel_data_f(4)
|
||||
val btb_rd_call_f = btb_sel_data_f(2)
|
||||
val btb_rd_ret_f = btb_sel_data_f(1)
|
||||
|
||||
btb_sel_data_f := Mux1H(Seq(btb_sel_f(1).asBool->Cat(btb_vbank1_rd_data_f(16,1),0.U),
|
||||
btb_sel_f(0).asBool->Cat(btb_vbank1_rd_data_f(16,1),0.U)))
|
||||
|
||||
val ifu_bp_hit_taken_f = (vwayhit_f & hist1_raw).orR & io.ifc_fetch_req_f & ~leak_one_f_d1 & ~io.dec_tlu_bpred_disable
|
||||
|
||||
val bht_force_taken_f = Cat( btb_vbank1_rd_data_f(CALL) | btb_vbank1_rd_data_f(RET) ,
|
||||
btb_vbank0_rd_data_f(CALL) | btb_vbank0_rd_data_f(RET))
|
||||
|
||||
val bht_valid_f = vwayhit_f
|
||||
|
||||
val bht_bank1_rd_data_f =WireInit(UInt(2.W), 0.U)
|
||||
val bht_bank0_rd_data_f =WireInit(UInt(2.W), 0.U)
|
||||
val bht_bank0_rd_data_p1_f =WireInit(UInt(2.W), 0.U)
|
||||
|
||||
val bht_vbank0_rd_data_f = Mux1H(Seq(!io.ifc_fetch_addr_f(1).asBool->bht_bank0_rd_data_f,
|
||||
io.ifc_fetch_addr_f(1).asBool->bht_bank1_rd_data_f))
|
||||
|
||||
val bht_vbank1_rd_data_f = Mux1H(Seq(!io.ifc_fetch_addr_f(1).asBool->bht_bank1_rd_data_f,
|
||||
io.ifc_fetch_addr_f(1).asBool->bht_bank0_rd_data_p1_f))
|
||||
bht_dir_f := Cat((bht_force_taken_f(1) | bht_vbank1_rd_data_f(1)) & bht_valid_f(1),
|
||||
(bht_force_taken_f(0) | bht_vbank0_rd_data_f(1)) & bht_valid_f(0))
|
||||
|
||||
val ifu_bp_inst_mask_f = (ifu_bp_hit_taken_f & btb_sel_f(1)) | ~ifu_bp_hit_taken_f
|
||||
// Bank explination
|
||||
|
||||
hist1_raw := bht_force_taken_f | Cat(bht_vbank1_rd_data_f(1), bht_vbank0_rd_data_f(1))
|
||||
|
||||
val hist0_raw = Cat(bht_vbank1_rd_data_f(0), bht_vbank0_rd_data_f(0))
|
||||
|
||||
val pc4_raw = Cat(vwayhit_f(1) & btb_vbank1_rd_data_f(PC4),
|
||||
vwayhit_f(0) & btb_vbank0_rd_data_f(PC4))
|
||||
|
||||
val pret_raw = Cat(vwayhit_f(1) & ~btb_vbank1_rd_data_f(CALL) & btb_vbank1_rd_data_f(RET),
|
||||
vwayhit_f(0) & ~btb_vbank0_rd_data_f(CALL) & btb_vbank0_rd_data_f(RET))
|
||||
|
||||
//GHR
|
||||
val num_valids = bht_valid_f(1) +& bht_valid_f(0)
|
||||
|
||||
val final_h = (btb_sel_f & bht_dir_f).andR
|
||||
|
||||
val fghr = WireInit(UInt(BHT_GHR_SIZE.W), 0.U)
|
||||
val merged_ghr = Mux1H(Seq((num_valids===2.U).asBool->Cat(fghr(BHT_GHR_SIZE-3,0), 0.U, final_h),
|
||||
(num_valids===1.U).asBool->Cat(fghr(BHT_GHR_SIZE-2,0), final_h),
|
||||
(num_valids===0.U).asBool->Cat(fghr(BHT_GHR_SIZE-1,0))))
|
||||
|
||||
val exu_flush_ghr = io.exu_mp_fghr
|
||||
|
||||
val fghr_ns = Mux1H(Seq(exu_flush_final_d1.asBool->exu_flush_ghr,
|
||||
(~exu_flush_final_d1 & io.ifc_fetch_req_f & io.ic_hit_f & ~leak_one_f_d1).asBool -> merged_ghr,
|
||||
(~exu_flush_final_d1 & ~(io.ifc_fetch_req_f & io.ic_hit_f & ~leak_one_f_d1)).asBool -> fghr))
|
||||
|
||||
fghr := RegNext(fghr_ns, init = 0.U)
|
||||
io.ifu_bp_fghr_f := fghr
|
||||
|
||||
io.ifu_bp_way_f := way_raw
|
||||
io.ifu_bp_hist1_f := hist1_raw
|
||||
io.ifu_bp_hist0_f := hist0_raw
|
||||
io.ifu_bp_pc4_f := pc4_raw
|
||||
|
||||
io.ifu_bp_valid_f := vwayhit_f & ~Fill(2, io.dec_tlu_bpred_disable)
|
||||
io.ifu_bp_ret_f := pret_raw
|
||||
|
||||
val bloc_f = Cat((bht_dir_f(0) & !fetch_start_f(0)) | (!bht_dir_f(0) & fetch_start_f(0)),
|
||||
(bht_dir_f(0) & fetch_start_f(0)) | (!bht_dir_f(0) & !fetch_start_f(0)))
|
||||
|
||||
val use_fa_plus = !bht_dir_f(0) & io.ifc_fetch_addr_f(0) & !btb_rd_pc4_f
|
||||
|
||||
val btb_fg_crossing_f = fetch_start_f(0) & btb_sel_f(0) & btb_rd_pc4_f
|
||||
val bp_total_branch_offset_f = bloc_f(1)^btb_rd_pc4_f
|
||||
|
||||
val ifc_fetch_adder_prior = RegEnable(io.ifc_fetch_addr_f, 0.U, (io.ifc_fetch_req_f & ~ifu_bp_hit_taken_f & io.ic_hit_f).asBool)
|
||||
|
||||
val ifu_bp_poffset_f = btb_rd_tgt_f
|
||||
val adder_pc_in_f = Mux1H(Seq(use_fa_plus.asBool->fetch_addr_p1_f,
|
||||
btb_fg_crossing_f.asBool->ifc_fetch_adder_prior,
|
||||
(!btb_fg_crossing_f & !use_fa_plus).asBool->io.ifc_fetch_addr_f(31,2)))
|
||||
|
||||
val bp_btb_target_adder_f = rvbradder(Cat(adder_pc_in_f(31,2),bp_total_branch_offset_f, 0.U), btb_rd_tgt_f)
|
||||
|
||||
|
||||
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -180,8 +180,8 @@ class RVCDecoder(x: UInt, xLen: Int) {
|
|||
class el2_ifu_compress_ctl( val XLen: Int, val usingCompressed: Boolean) extends Module {
|
||||
val io = IO(new Bundle {
|
||||
val in = Input(UInt(32.W))
|
||||
val out = Output(new ExpandedInstruction)
|
||||
val rvc = Output(Bool())
|
||||
val out = Output(UInt(32.W))
|
||||
//val rvc = Output(Bool())
|
||||
//val legal = Output(Bool())
|
||||
//val waleed_out = Output(UInt(32.W))
|
||||
//val q1_Out = Output(new ExpandedInstruction)
|
||||
|
|
@ -189,9 +189,14 @@ class el2_ifu_compress_ctl( val XLen: Int, val usingCompressed: Boolean) extends
|
|||
//val q3_Out = Output(new ExpandedInstruction)
|
||||
})
|
||||
if (usingCompressed) {
|
||||
io.rvc := io.in(1,0) =/= 3.U
|
||||
val rvc = io.in(1,0) =/= 3.U
|
||||
val inst = new RVCDecoder(io.in, XLen)
|
||||
io.out := inst.decode
|
||||
val decoded = inst.decode
|
||||
io.out := Mux(rvc, 0.U, decoded.bits)
|
||||
//io.out.rd := 0.U
|
||||
//io.out.rs1 := 0.U
|
||||
//io.out.rs2 := 0.U
|
||||
//io.out.rs3 := 0.U
|
||||
/*io.legal := (!io.in(13))&(!io.in(12))&(io.in(11))&io.in(1)&(!io.in(0)) |
|
||||
(!io.in(13))&(!io.in(12))&(io.in(6))&io.in(1)&(!io.in(0)) |
|
||||
(!io.in(15))&(!io.in(13))&io.in(11)(!io.in(1)) |
|
||||
|
|
@ -215,7 +220,7 @@ class el2_ifu_compress_ctl( val XLen: Int, val usingCompressed: Boolean) extends
|
|||
io.in(14)&(!io.in(13))&(!io.in(0))
|
||||
io.waleed_out := Mux(io.legal,io.out.bits,0.U)*/
|
||||
} else {
|
||||
io.rvc := false.B
|
||||
//io.rvc := false.B
|
||||
io.out := new RVCDecoder(io.in, XLen).passthrough
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -195,6 +195,16 @@ trait el2_lib extends param{
|
|||
def rveven_paritygen(data_in : UInt) =
|
||||
data_in.xorR.asUInt
|
||||
|
||||
def rvbradder (pc:UInt, offset:UInt) = {
|
||||
val dout_lower = pc(12,1) +& offset(12,1)
|
||||
val pc_inc = pc(31,13)+1.U
|
||||
val pc_dec = pc(31,13)+1.U
|
||||
val sign = offset(offset.getWidth-1)
|
||||
Cat(Mux1H(Seq((sign ^ !dout_lower(dout_lower.getWidth-1)).asBool -> pc(31,13),
|
||||
(!sign & dout_lower(dout_lower.getWidth-1)).asBool -> (pc(31,13)+1.U),
|
||||
(sign & !dout_lower(dout_lower.getWidth-1)).asBool -> (pc(31,13)-1.U))) , dout_lower(12,1), 0.U)
|
||||
}
|
||||
|
||||
// RV range
|
||||
def rvrangecheck(CCM_SADR:Long, CCM_SIZE:Int, addr:UInt) = {
|
||||
val REGION_BITS = 4;
|
||||
|
|
|
|||
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Reference in New Issue