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Merge branch 'ifu' of github.com:waleedbinehsan-lm/SweRV-Chislified into ifu

This commit is contained in:
waleed-lm 2020-09-25 12:24:54 +05:00
parent 0228097e51 dc47141916
commit e0e32412bc
1 changed files with 3 additions and 3 deletions
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6
src/main/scala/ifu/el2_ifu_compress.scala → src/main/scala/ifu/el2_ifu_compress_ctl.scala
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@ -177,7 +177,7 @@ class RVCDecoder(x: UInt, xLen: Int) {
def ret_q3 = q3
}
class el2_ifu_compress( val XLen: Int, val usingCompressed: Boolean) extends Module {
class el2_ifu_compress_ctl( val XLen: Int, val usingCompressed: Boolean) extends Module {
val io = IO(new Bundle {
val in = Input(UInt(32.W))
val out = Output(new ExpandedInstruction)
@ -221,5 +221,5 @@ class el2_ifu_compress( val XLen: Int, val usingCompressed: Boolean) extends Mod
}
object ifu_compress extends App {
println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu_compress(64, true)))
}
println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu_compress_ctl(64, true)))
}