colin
/
quasar
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

vwayhit corrected

This commit is contained in:
​Laraib Khan 2021-01-22 12:38:12 +05:00
parent f2bbfb2e20
commit 5ec570e847
6 changed files with 1543 additions and 1542 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2592
ifu_bp_ctl.fir
View File

File diff suppressed because it is too large Load Diff

490
ifu_bp_ctl.v
View File

@ -245,198 +245,198 @@ module ifu_bp_ctl(
wire [9:0] _T_580 = {btb_rd_addr_f,2'h0}; // @[Cat.scala 29:58] wire [9:0] _T_580 = {btb_rd_addr_f,2'h0}; // @[Cat.scala 29:58]
reg [7:0] fghr; // @[Reg.scala 27:20] reg [7:0] fghr; // @[Reg.scala 27:20]
wire [7:0] bht_rd_addr_hashed_f = _T_580[9:2] ^ fghr; // @[lib.scala 56:35] wire [7:0] bht_rd_addr_hashed_f = _T_580[9:2] ^ fghr; // @[lib.scala 56:35]
wire _T_1946 = bht_rd_addr_hashed_f == 8'h0; // @[ifu_bp_ctl.scala 539:79] wire _T_1946 = bht_rd_addr_hashed_f == 8'h0; // @[ifu_bp_ctl.scala 540:79]
reg [1:0] bht_bank_rd_data_out_1_0; // @[Reg.scala 27:20] reg [1:0] bht_bank_rd_data_out_1_0; // @[Reg.scala 27:20]
wire [1:0] _T_1978 = _T_1946 ? bht_bank_rd_data_out_1_0 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_1978 = _T_1946 ? bht_bank_rd_data_out_1_0 : 2'h0; // @[Mux.scala 27:72]
wire _T_1948 = bht_rd_addr_hashed_f == 8'h1; // @[ifu_bp_ctl.scala 539:79] wire _T_1948 = bht_rd_addr_hashed_f == 8'h1; // @[ifu_bp_ctl.scala 540:79]
reg [1:0] bht_bank_rd_data_out_1_1; // @[Reg.scala 27:20] reg [1:0] bht_bank_rd_data_out_1_1; // @[Reg.scala 27:20]
wire [1:0] _T_1979 = _T_1948 ? bht_bank_rd_data_out_1_1 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_1979 = _T_1948 ? bht_bank_rd_data_out_1_1 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_1994 = _T_1978 | _T_1979; // @[Mux.scala 27:72] wire [1:0] _T_1994 = _T_1978 | _T_1979; // @[Mux.scala 27:72]
wire _T_1950 = bht_rd_addr_hashed_f == 8'h2; // @[ifu_bp_ctl.scala 539:79] wire _T_1950 = bht_rd_addr_hashed_f == 8'h2; // @[ifu_bp_ctl.scala 540:79]
reg [1:0] bht_bank_rd_data_out_1_2; // @[Reg.scala 27:20] reg [1:0] bht_bank_rd_data_out_1_2; // @[Reg.scala 27:20]
wire [1:0] _T_1980 = _T_1950 ? bht_bank_rd_data_out_1_2 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_1980 = _T_1950 ? bht_bank_rd_data_out_1_2 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_1995 = _T_1994 | _T_1980; // @[Mux.scala 27:72] wire [1:0] _T_1995 = _T_1994 | _T_1980; // @[Mux.scala 27:72]
wire _T_1952 = bht_rd_addr_hashed_f == 8'h3; // @[ifu_bp_ctl.scala 539:79] wire _T_1952 = bht_rd_addr_hashed_f == 8'h3; // @[ifu_bp_ctl.scala 540:79]
reg [1:0] bht_bank_rd_data_out_1_3; // @[Reg.scala 27:20] reg [1:0] bht_bank_rd_data_out_1_3; // @[Reg.scala 27:20]
wire [1:0] _T_1981 = _T_1952 ? bht_bank_rd_data_out_1_3 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_1981 = _T_1952 ? bht_bank_rd_data_out_1_3 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_1996 = _T_1995 | _T_1981; // @[Mux.scala 27:72] wire [1:0] _T_1996 = _T_1995 | _T_1981; // @[Mux.scala 27:72]
wire _T_1954 = bht_rd_addr_hashed_f == 8'h4; // @[ifu_bp_ctl.scala 539:79] wire _T_1954 = bht_rd_addr_hashed_f == 8'h4; // @[ifu_bp_ctl.scala 540:79]
reg [1:0] bht_bank_rd_data_out_1_4; // @[Reg.scala 27:20] reg [1:0] bht_bank_rd_data_out_1_4; // @[Reg.scala 27:20]
wire [1:0] _T_1982 = _T_1954 ? bht_bank_rd_data_out_1_4 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_1982 = _T_1954 ? bht_bank_rd_data_out_1_4 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_1997 = _T_1996 | _T_1982; // @[Mux.scala 27:72] wire [1:0] _T_1997 = _T_1996 | _T_1982; // @[Mux.scala 27:72]
wire _T_1956 = bht_rd_addr_hashed_f == 8'h5; // @[ifu_bp_ctl.scala 539:79] wire _T_1956 = bht_rd_addr_hashed_f == 8'h5; // @[ifu_bp_ctl.scala 540:79]
reg [1:0] bht_bank_rd_data_out_1_5; // @[Reg.scala 27:20] reg [1:0] bht_bank_rd_data_out_1_5; // @[Reg.scala 27:20]
wire [1:0] _T_1983 = _T_1956 ? bht_bank_rd_data_out_1_5 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_1983 = _T_1956 ? bht_bank_rd_data_out_1_5 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_1998 = _T_1997 | _T_1983; // @[Mux.scala 27:72] wire [1:0] _T_1998 = _T_1997 | _T_1983; // @[Mux.scala 27:72]
wire _T_1958 = bht_rd_addr_hashed_f == 8'h6; // @[ifu_bp_ctl.scala 539:79] wire _T_1958 = bht_rd_addr_hashed_f == 8'h6; // @[ifu_bp_ctl.scala 540:79]
reg [1:0] bht_bank_rd_data_out_1_6; // @[Reg.scala 27:20] reg [1:0] bht_bank_rd_data_out_1_6; // @[Reg.scala 27:20]
wire [1:0] _T_1984 = _T_1958 ? bht_bank_rd_data_out_1_6 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_1984 = _T_1958 ? bht_bank_rd_data_out_1_6 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_1999 = _T_1998 | _T_1984; // @[Mux.scala 27:72] wire [1:0] _T_1999 = _T_1998 | _T_1984; // @[Mux.scala 27:72]
wire _T_1960 = bht_rd_addr_hashed_f == 8'h7; // @[ifu_bp_ctl.scala 539:79] wire _T_1960 = bht_rd_addr_hashed_f == 8'h7; // @[ifu_bp_ctl.scala 540:79]
reg [1:0] bht_bank_rd_data_out_1_7; // @[Reg.scala 27:20] reg [1:0] bht_bank_rd_data_out_1_7; // @[Reg.scala 27:20]
wire [1:0] _T_1985 = _T_1960 ? bht_bank_rd_data_out_1_7 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_1985 = _T_1960 ? bht_bank_rd_data_out_1_7 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_2000 = _T_1999 | _T_1985; // @[Mux.scala 27:72] wire [1:0] _T_2000 = _T_1999 | _T_1985; // @[Mux.scala 27:72]
wire _T_1962 = bht_rd_addr_hashed_f == 8'h8; // @[ifu_bp_ctl.scala 539:79] wire _T_1962 = bht_rd_addr_hashed_f == 8'h8; // @[ifu_bp_ctl.scala 540:79]
reg [1:0] bht_bank_rd_data_out_1_8; // @[Reg.scala 27:20] reg [1:0] bht_bank_rd_data_out_1_8; // @[Reg.scala 27:20]
wire [1:0] _T_1986 = _T_1962 ? bht_bank_rd_data_out_1_8 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_1986 = _T_1962 ? bht_bank_rd_data_out_1_8 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_2001 = _T_2000 | _T_1986; // @[Mux.scala 27:72] wire [1:0] _T_2001 = _T_2000 | _T_1986; // @[Mux.scala 27:72]
wire _T_1964 = bht_rd_addr_hashed_f == 8'h9; // @[ifu_bp_ctl.scala 539:79] wire _T_1964 = bht_rd_addr_hashed_f == 8'h9; // @[ifu_bp_ctl.scala 540:79]
reg [1:0] bht_bank_rd_data_out_1_9; // @[Reg.scala 27:20] reg [1:0] bht_bank_rd_data_out_1_9; // @[Reg.scala 27:20]
wire [1:0] _T_1987 = _T_1964 ? bht_bank_rd_data_out_1_9 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_1987 = _T_1964 ? bht_bank_rd_data_out_1_9 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_2002 = _T_2001 | _T_1987; // @[Mux.scala 27:72] wire [1:0] _T_2002 = _T_2001 | _T_1987; // @[Mux.scala 27:72]
wire _T_1966 = bht_rd_addr_hashed_f == 8'ha; // @[ifu_bp_ctl.scala 539:79] wire _T_1966 = bht_rd_addr_hashed_f == 8'ha; // @[ifu_bp_ctl.scala 540:79]
reg [1:0] bht_bank_rd_data_out_1_10; // @[Reg.scala 27:20] reg [1:0] bht_bank_rd_data_out_1_10; // @[Reg.scala 27:20]
wire [1:0] _T_1988 = _T_1966 ? bht_bank_rd_data_out_1_10 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_1988 = _T_1966 ? bht_bank_rd_data_out_1_10 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_2003 = _T_2002 | _T_1988; // @[Mux.scala 27:72] wire [1:0] _T_2003 = _T_2002 | _T_1988; // @[Mux.scala 27:72]
wire _T_1968 = bht_rd_addr_hashed_f == 8'hb; // @[ifu_bp_ctl.scala 539:79] wire _T_1968 = bht_rd_addr_hashed_f == 8'hb; // @[ifu_bp_ctl.scala 540:79]
reg [1:0] bht_bank_rd_data_out_1_11; // @[Reg.scala 27:20] reg [1:0] bht_bank_rd_data_out_1_11; // @[Reg.scala 27:20]
wire [1:0] _T_1989 = _T_1968 ? bht_bank_rd_data_out_1_11 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_1989 = _T_1968 ? bht_bank_rd_data_out_1_11 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_2004 = _T_2003 | _T_1989; // @[Mux.scala 27:72] wire [1:0] _T_2004 = _T_2003 | _T_1989; // @[Mux.scala 27:72]
wire _T_1970 = bht_rd_addr_hashed_f == 8'hc; // @[ifu_bp_ctl.scala 539:79] wire _T_1970 = bht_rd_addr_hashed_f == 8'hc; // @[ifu_bp_ctl.scala 540:79]
reg [1:0] bht_bank_rd_data_out_1_12; // @[Reg.scala 27:20] reg [1:0] bht_bank_rd_data_out_1_12; // @[Reg.scala 27:20]
wire [1:0] _T_1990 = _T_1970 ? bht_bank_rd_data_out_1_12 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_1990 = _T_1970 ? bht_bank_rd_data_out_1_12 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_2005 = _T_2004 | _T_1990; // @[Mux.scala 27:72] wire [1:0] _T_2005 = _T_2004 | _T_1990; // @[Mux.scala 27:72]
wire _T_1972 = bht_rd_addr_hashed_f == 8'hd; // @[ifu_bp_ctl.scala 539:79] wire _T_1972 = bht_rd_addr_hashed_f == 8'hd; // @[ifu_bp_ctl.scala 540:79]
reg [1:0] bht_bank_rd_data_out_1_13; // @[Reg.scala 27:20] reg [1:0] bht_bank_rd_data_out_1_13; // @[Reg.scala 27:20]
wire [1:0] _T_1991 = _T_1972 ? bht_bank_rd_data_out_1_13 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_1991 = _T_1972 ? bht_bank_rd_data_out_1_13 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_2006 = _T_2005 | _T_1991; // @[Mux.scala 27:72] wire [1:0] _T_2006 = _T_2005 | _T_1991; // @[Mux.scala 27:72]
wire _T_1974 = bht_rd_addr_hashed_f == 8'he; // @[ifu_bp_ctl.scala 539:79] wire _T_1974 = bht_rd_addr_hashed_f == 8'he; // @[ifu_bp_ctl.scala 540:79]
reg [1:0] bht_bank_rd_data_out_1_14; // @[Reg.scala 27:20] reg [1:0] bht_bank_rd_data_out_1_14; // @[Reg.scala 27:20]
wire [1:0] _T_1992 = _T_1974 ? bht_bank_rd_data_out_1_14 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_1992 = _T_1974 ? bht_bank_rd_data_out_1_14 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_2007 = _T_2006 | _T_1992; // @[Mux.scala 27:72] wire [1:0] _T_2007 = _T_2006 | _T_1992; // @[Mux.scala 27:72]
wire _T_1976 = bht_rd_addr_hashed_f == 8'hf; // @[ifu_bp_ctl.scala 539:79] wire _T_1976 = bht_rd_addr_hashed_f == 8'hf; // @[ifu_bp_ctl.scala 540:79]
reg [1:0] bht_bank_rd_data_out_1_15; // @[Reg.scala 27:20] reg [1:0] bht_bank_rd_data_out_1_15; // @[Reg.scala 27:20]
wire [1:0] _T_1993 = _T_1976 ? bht_bank_rd_data_out_1_15 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_1993 = _T_1976 ? bht_bank_rd_data_out_1_15 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] bht_bank1_rd_data_f = _T_2007 | _T_1993; // @[Mux.scala 27:72] wire [1:0] bht_bank1_rd_data_f = _T_2007 | _T_1993; // @[Mux.scala 27:72]
wire [1:0] _T_251 = _T_248 ? bht_bank1_rd_data_f : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_251 = _T_248 ? bht_bank1_rd_data_f : 2'h0; // @[Mux.scala 27:72]
wire [9:0] _T_583 = {btb_rd_addr_p1_f,2'h0}; // @[Cat.scala 29:58] wire [9:0] _T_583 = {btb_rd_addr_p1_f,2'h0}; // @[Cat.scala 29:58]
wire [7:0] bht_rd_addr_hashed_p1_f = _T_583[9:2] ^ fghr; // @[lib.scala 56:35] wire [7:0] bht_rd_addr_hashed_p1_f = _T_583[9:2] ^ fghr; // @[lib.scala 56:35]
wire _T_2010 = bht_rd_addr_hashed_p1_f == 8'h0; // @[ifu_bp_ctl.scala 540:85] wire _T_2010 = bht_rd_addr_hashed_p1_f == 8'h0; // @[ifu_bp_ctl.scala 541:85]
reg [1:0] bht_bank_rd_data_out_0_0; // @[Reg.scala 27:20] reg [1:0] bht_bank_rd_data_out_0_0; // @[Reg.scala 27:20]
wire [1:0] _T_2042 = _T_2010 ? bht_bank_rd_data_out_0_0 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_2042 = _T_2010 ? bht_bank_rd_data_out_0_0 : 2'h0; // @[Mux.scala 27:72]
wire _T_2012 = bht_rd_addr_hashed_p1_f == 8'h1; // @[ifu_bp_ctl.scala 540:85] wire _T_2012 = bht_rd_addr_hashed_p1_f == 8'h1; // @[ifu_bp_ctl.scala 541:85]
reg [1:0] bht_bank_rd_data_out_0_1; // @[Reg.scala 27:20] reg [1:0] bht_bank_rd_data_out_0_1; // @[Reg.scala 27:20]
wire [1:0] _T_2043 = _T_2012 ? bht_bank_rd_data_out_0_1 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_2043 = _T_2012 ? bht_bank_rd_data_out_0_1 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_2058 = _T_2042 | _T_2043; // @[Mux.scala 27:72] wire [1:0] _T_2058 = _T_2042 | _T_2043; // @[Mux.scala 27:72]
wire _T_2014 = bht_rd_addr_hashed_p1_f == 8'h2; // @[ifu_bp_ctl.scala 540:85] wire _T_2014 = bht_rd_addr_hashed_p1_f == 8'h2; // @[ifu_bp_ctl.scala 541:85]
reg [1:0] bht_bank_rd_data_out_0_2; // @[Reg.scala 27:20] reg [1:0] bht_bank_rd_data_out_0_2; // @[Reg.scala 27:20]
wire [1:0] _T_2044 = _T_2014 ? bht_bank_rd_data_out_0_2 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_2044 = _T_2014 ? bht_bank_rd_data_out_0_2 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_2059 = _T_2058 | _T_2044; // @[Mux.scala 27:72] wire [1:0] _T_2059 = _T_2058 | _T_2044; // @[Mux.scala 27:72]
wire _T_2016 = bht_rd_addr_hashed_p1_f == 8'h3; // @[ifu_bp_ctl.scala 540:85] wire _T_2016 = bht_rd_addr_hashed_p1_f == 8'h3; // @[ifu_bp_ctl.scala 541:85]
reg [1:0] bht_bank_rd_data_out_0_3; // @[Reg.scala 27:20] reg [1:0] bht_bank_rd_data_out_0_3; // @[Reg.scala 27:20]
wire [1:0] _T_2045 = _T_2016 ? bht_bank_rd_data_out_0_3 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_2045 = _T_2016 ? bht_bank_rd_data_out_0_3 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_2060 = _T_2059 | _T_2045; // @[Mux.scala 27:72] wire [1:0] _T_2060 = _T_2059 | _T_2045; // @[Mux.scala 27:72]
wire _T_2018 = bht_rd_addr_hashed_p1_f == 8'h4; // @[ifu_bp_ctl.scala 540:85] wire _T_2018 = bht_rd_addr_hashed_p1_f == 8'h4; // @[ifu_bp_ctl.scala 541:85]
reg [1:0] bht_bank_rd_data_out_0_4; // @[Reg.scala 27:20] reg [1:0] bht_bank_rd_data_out_0_4; // @[Reg.scala 27:20]
wire [1:0] _T_2046 = _T_2018 ? bht_bank_rd_data_out_0_4 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_2046 = _T_2018 ? bht_bank_rd_data_out_0_4 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_2061 = _T_2060 | _T_2046; // @[Mux.scala 27:72] wire [1:0] _T_2061 = _T_2060 | _T_2046; // @[Mux.scala 27:72]
wire _T_2020 = bht_rd_addr_hashed_p1_f == 8'h5; // @[ifu_bp_ctl.scala 540:85] wire _T_2020 = bht_rd_addr_hashed_p1_f == 8'h5; // @[ifu_bp_ctl.scala 541:85]
reg [1:0] bht_bank_rd_data_out_0_5; // @[Reg.scala 27:20] reg [1:0] bht_bank_rd_data_out_0_5; // @[Reg.scala 27:20]
wire [1:0] _T_2047 = _T_2020 ? bht_bank_rd_data_out_0_5 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_2047 = _T_2020 ? bht_bank_rd_data_out_0_5 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_2062 = _T_2061 | _T_2047; // @[Mux.scala 27:72] wire [1:0] _T_2062 = _T_2061 | _T_2047; // @[Mux.scala 27:72]
wire _T_2022 = bht_rd_addr_hashed_p1_f == 8'h6; // @[ifu_bp_ctl.scala 540:85] wire _T_2022 = bht_rd_addr_hashed_p1_f == 8'h6; // @[ifu_bp_ctl.scala 541:85]
reg [1:0] bht_bank_rd_data_out_0_6; // @[Reg.scala 27:20] reg [1:0] bht_bank_rd_data_out_0_6; // @[Reg.scala 27:20]
wire [1:0] _T_2048 = _T_2022 ? bht_bank_rd_data_out_0_6 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_2048 = _T_2022 ? bht_bank_rd_data_out_0_6 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_2063 = _T_2062 | _T_2048; // @[Mux.scala 27:72] wire [1:0] _T_2063 = _T_2062 | _T_2048; // @[Mux.scala 27:72]
wire _T_2024 = bht_rd_addr_hashed_p1_f == 8'h7; // @[ifu_bp_ctl.scala 540:85] wire _T_2024 = bht_rd_addr_hashed_p1_f == 8'h7; // @[ifu_bp_ctl.scala 541:85]
reg [1:0] bht_bank_rd_data_out_0_7; // @[Reg.scala 27:20] reg [1:0] bht_bank_rd_data_out_0_7; // @[Reg.scala 27:20]
wire [1:0] _T_2049 = _T_2024 ? bht_bank_rd_data_out_0_7 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_2049 = _T_2024 ? bht_bank_rd_data_out_0_7 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_2064 = _T_2063 | _T_2049; // @[Mux.scala 27:72] wire [1:0] _T_2064 = _T_2063 | _T_2049; // @[Mux.scala 27:72]
wire _T_2026 = bht_rd_addr_hashed_p1_f == 8'h8; // @[ifu_bp_ctl.scala 540:85] wire _T_2026 = bht_rd_addr_hashed_p1_f == 8'h8; // @[ifu_bp_ctl.scala 541:85]
reg [1:0] bht_bank_rd_data_out_0_8; // @[Reg.scala 27:20] reg [1:0] bht_bank_rd_data_out_0_8; // @[Reg.scala 27:20]
wire [1:0] _T_2050 = _T_2026 ? bht_bank_rd_data_out_0_8 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_2050 = _T_2026 ? bht_bank_rd_data_out_0_8 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_2065 = _T_2064 | _T_2050; // @[Mux.scala 27:72] wire [1:0] _T_2065 = _T_2064 | _T_2050; // @[Mux.scala 27:72]
wire _T_2028 = bht_rd_addr_hashed_p1_f == 8'h9; // @[ifu_bp_ctl.scala 540:85] wire _T_2028 = bht_rd_addr_hashed_p1_f == 8'h9; // @[ifu_bp_ctl.scala 541:85]
reg [1:0] bht_bank_rd_data_out_0_9; // @[Reg.scala 27:20] reg [1:0] bht_bank_rd_data_out_0_9; // @[Reg.scala 27:20]
wire [1:0] _T_2051 = _T_2028 ? bht_bank_rd_data_out_0_9 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_2051 = _T_2028 ? bht_bank_rd_data_out_0_9 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_2066 = _T_2065 | _T_2051; // @[Mux.scala 27:72] wire [1:0] _T_2066 = _T_2065 | _T_2051; // @[Mux.scala 27:72]
wire _T_2030 = bht_rd_addr_hashed_p1_f == 8'ha; // @[ifu_bp_ctl.scala 540:85] wire _T_2030 = bht_rd_addr_hashed_p1_f == 8'ha; // @[ifu_bp_ctl.scala 541:85]
reg [1:0] bht_bank_rd_data_out_0_10; // @[Reg.scala 27:20] reg [1:0] bht_bank_rd_data_out_0_10; // @[Reg.scala 27:20]
wire [1:0] _T_2052 = _T_2030 ? bht_bank_rd_data_out_0_10 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_2052 = _T_2030 ? bht_bank_rd_data_out_0_10 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_2067 = _T_2066 | _T_2052; // @[Mux.scala 27:72] wire [1:0] _T_2067 = _T_2066 | _T_2052; // @[Mux.scala 27:72]
wire _T_2032 = bht_rd_addr_hashed_p1_f == 8'hb; // @[ifu_bp_ctl.scala 540:85] wire _T_2032 = bht_rd_addr_hashed_p1_f == 8'hb; // @[ifu_bp_ctl.scala 541:85]
reg [1:0] bht_bank_rd_data_out_0_11; // @[Reg.scala 27:20] reg [1:0] bht_bank_rd_data_out_0_11; // @[Reg.scala 27:20]
wire [1:0] _T_2053 = _T_2032 ? bht_bank_rd_data_out_0_11 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_2053 = _T_2032 ? bht_bank_rd_data_out_0_11 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_2068 = _T_2067 | _T_2053; // @[Mux.scala 27:72] wire [1:0] _T_2068 = _T_2067 | _T_2053; // @[Mux.scala 27:72]
wire _T_2034 = bht_rd_addr_hashed_p1_f == 8'hc; // @[ifu_bp_ctl.scala 540:85] wire _T_2034 = bht_rd_addr_hashed_p1_f == 8'hc; // @[ifu_bp_ctl.scala 541:85]
reg [1:0] bht_bank_rd_data_out_0_12; // @[Reg.scala 27:20] reg [1:0] bht_bank_rd_data_out_0_12; // @[Reg.scala 27:20]
wire [1:0] _T_2054 = _T_2034 ? bht_bank_rd_data_out_0_12 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_2054 = _T_2034 ? bht_bank_rd_data_out_0_12 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_2069 = _T_2068 | _T_2054; // @[Mux.scala 27:72] wire [1:0] _T_2069 = _T_2068 | _T_2054; // @[Mux.scala 27:72]
wire _T_2036 = bht_rd_addr_hashed_p1_f == 8'hd; // @[ifu_bp_ctl.scala 540:85] wire _T_2036 = bht_rd_addr_hashed_p1_f == 8'hd; // @[ifu_bp_ctl.scala 541:85]
reg [1:0] bht_bank_rd_data_out_0_13; // @[Reg.scala 27:20] reg [1:0] bht_bank_rd_data_out_0_13; // @[Reg.scala 27:20]
wire [1:0] _T_2055 = _T_2036 ? bht_bank_rd_data_out_0_13 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_2055 = _T_2036 ? bht_bank_rd_data_out_0_13 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_2070 = _T_2069 | _T_2055; // @[Mux.scala 27:72] wire [1:0] _T_2070 = _T_2069 | _T_2055; // @[Mux.scala 27:72]
wire _T_2038 = bht_rd_addr_hashed_p1_f == 8'he; // @[ifu_bp_ctl.scala 540:85] wire _T_2038 = bht_rd_addr_hashed_p1_f == 8'he; // @[ifu_bp_ctl.scala 541:85]
reg [1:0] bht_bank_rd_data_out_0_14; // @[Reg.scala 27:20] reg [1:0] bht_bank_rd_data_out_0_14; // @[Reg.scala 27:20]
wire [1:0] _T_2056 = _T_2038 ? bht_bank_rd_data_out_0_14 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_2056 = _T_2038 ? bht_bank_rd_data_out_0_14 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_2071 = _T_2070 | _T_2056; // @[Mux.scala 27:72] wire [1:0] _T_2071 = _T_2070 | _T_2056; // @[Mux.scala 27:72]
wire _T_2040 = bht_rd_addr_hashed_p1_f == 8'hf; // @[ifu_bp_ctl.scala 540:85] wire _T_2040 = bht_rd_addr_hashed_p1_f == 8'hf; // @[ifu_bp_ctl.scala 541:85]
reg [1:0] bht_bank_rd_data_out_0_15; // @[Reg.scala 27:20] reg [1:0] bht_bank_rd_data_out_0_15; // @[Reg.scala 27:20]
wire [1:0] _T_2057 = _T_2040 ? bht_bank_rd_data_out_0_15 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_2057 = _T_2040 ? bht_bank_rd_data_out_0_15 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] bht_bank0_rd_data_p1_f = _T_2071 | _T_2057; // @[Mux.scala 27:72] wire [1:0] bht_bank0_rd_data_p1_f = _T_2071 | _T_2057; // @[Mux.scala 27:72]
wire [1:0] _T_252 = io_ifc_fetch_addr_f[0] ? bht_bank0_rd_data_p1_f : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_252 = io_ifc_fetch_addr_f[0] ? bht_bank0_rd_data_p1_f : 2'h0; // @[Mux.scala 27:72]
wire [1:0] bht_vbank1_rd_data_f = _T_251 | _T_252; // @[Mux.scala 27:72] wire [1:0] bht_vbank1_rd_data_f = _T_251 | _T_252; // @[Mux.scala 27:72]
wire [1:0] _T_599 = io_ifc_fetch_addr_f[0] ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] wire [1:0] _T_599 = io_ifc_fetch_addr_f[0] ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire _T_708 = btb_rd_addr_f == 8'h0; // @[ifu_bp_ctl.scala 444:80] wire _T_708 = btb_rd_addr_f == 8'h0; // @[ifu_bp_ctl.scala 445:80]
reg [21:0] btb_bank0_rd_data_way0_out_0; // @[Reg.scala 27:20] reg [21:0] btb_bank0_rd_data_way0_out_0; // @[Reg.scala 27:20]
wire [21:0] _T_740 = _T_708 ? btb_bank0_rd_data_way0_out_0 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_740 = _T_708 ? btb_bank0_rd_data_way0_out_0 : 22'h0; // @[Mux.scala 27:72]
wire _T_710 = btb_rd_addr_f == 8'h1; // @[ifu_bp_ctl.scala 444:80] wire _T_710 = btb_rd_addr_f == 8'h1; // @[ifu_bp_ctl.scala 445:80]
reg [21:0] btb_bank0_rd_data_way0_out_1; // @[Reg.scala 27:20] reg [21:0] btb_bank0_rd_data_way0_out_1; // @[Reg.scala 27:20]
wire [21:0] _T_741 = _T_710 ? btb_bank0_rd_data_way0_out_1 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_741 = _T_710 ? btb_bank0_rd_data_way0_out_1 : 22'h0; // @[Mux.scala 27:72]
wire [21:0] _T_756 = _T_740 | _T_741; // @[Mux.scala 27:72] wire [21:0] _T_756 = _T_740 | _T_741; // @[Mux.scala 27:72]
wire _T_712 = btb_rd_addr_f == 8'h2; // @[ifu_bp_ctl.scala 444:80] wire _T_712 = btb_rd_addr_f == 8'h2; // @[ifu_bp_ctl.scala 445:80]
reg [21:0] btb_bank0_rd_data_way0_out_2; // @[Reg.scala 27:20] reg [21:0] btb_bank0_rd_data_way0_out_2; // @[Reg.scala 27:20]
wire [21:0] _T_742 = _T_712 ? btb_bank0_rd_data_way0_out_2 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_742 = _T_712 ? btb_bank0_rd_data_way0_out_2 : 22'h0; // @[Mux.scala 27:72]
wire [21:0] _T_757 = _T_756 | _T_742; // @[Mux.scala 27:72] wire [21:0] _T_757 = _T_756 | _T_742; // @[Mux.scala 27:72]
wire _T_714 = btb_rd_addr_f == 8'h3; // @[ifu_bp_ctl.scala 444:80] wire _T_714 = btb_rd_addr_f == 8'h3; // @[ifu_bp_ctl.scala 445:80]
reg [21:0] btb_bank0_rd_data_way0_out_3; // @[Reg.scala 27:20] reg [21:0] btb_bank0_rd_data_way0_out_3; // @[Reg.scala 27:20]
wire [21:0] _T_743 = _T_714 ? btb_bank0_rd_data_way0_out_3 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_743 = _T_714 ? btb_bank0_rd_data_way0_out_3 : 22'h0; // @[Mux.scala 27:72]
wire [21:0] _T_758 = _T_757 | _T_743; // @[Mux.scala 27:72] wire [21:0] _T_758 = _T_757 | _T_743; // @[Mux.scala 27:72]
wire _T_716 = btb_rd_addr_f == 8'h4; // @[ifu_bp_ctl.scala 444:80] wire _T_716 = btb_rd_addr_f == 8'h4; // @[ifu_bp_ctl.scala 445:80]
reg [21:0] btb_bank0_rd_data_way0_out_4; // @[Reg.scala 27:20] reg [21:0] btb_bank0_rd_data_way0_out_4; // @[Reg.scala 27:20]
wire [21:0] _T_744 = _T_716 ? btb_bank0_rd_data_way0_out_4 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_744 = _T_716 ? btb_bank0_rd_data_way0_out_4 : 22'h0; // @[Mux.scala 27:72]
wire [21:0] _T_759 = _T_758 | _T_744; // @[Mux.scala 27:72] wire [21:0] _T_759 = _T_758 | _T_744; // @[Mux.scala 27:72]
wire _T_718 = btb_rd_addr_f == 8'h5; // @[ifu_bp_ctl.scala 444:80] wire _T_718 = btb_rd_addr_f == 8'h5; // @[ifu_bp_ctl.scala 445:80]
reg [21:0] btb_bank0_rd_data_way0_out_5; // @[Reg.scala 27:20] reg [21:0] btb_bank0_rd_data_way0_out_5; // @[Reg.scala 27:20]
wire [21:0] _T_745 = _T_718 ? btb_bank0_rd_data_way0_out_5 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_745 = _T_718 ? btb_bank0_rd_data_way0_out_5 : 22'h0; // @[Mux.scala 27:72]
wire [21:0] _T_760 = _T_759 | _T_745; // @[Mux.scala 27:72] wire [21:0] _T_760 = _T_759 | _T_745; // @[Mux.scala 27:72]
wire _T_720 = btb_rd_addr_f == 8'h6; // @[ifu_bp_ctl.scala 444:80] wire _T_720 = btb_rd_addr_f == 8'h6; // @[ifu_bp_ctl.scala 445:80]
reg [21:0] btb_bank0_rd_data_way0_out_6; // @[Reg.scala 27:20] reg [21:0] btb_bank0_rd_data_way0_out_6; // @[Reg.scala 27:20]
wire [21:0] _T_746 = _T_720 ? btb_bank0_rd_data_way0_out_6 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_746 = _T_720 ? btb_bank0_rd_data_way0_out_6 : 22'h0; // @[Mux.scala 27:72]
wire [21:0] _T_761 = _T_760 | _T_746; // @[Mux.scala 27:72] wire [21:0] _T_761 = _T_760 | _T_746; // @[Mux.scala 27:72]
wire _T_722 = btb_rd_addr_f == 8'h7; // @[ifu_bp_ctl.scala 444:80] wire _T_722 = btb_rd_addr_f == 8'h7; // @[ifu_bp_ctl.scala 445:80]
reg [21:0] btb_bank0_rd_data_way0_out_7; // @[Reg.scala 27:20] reg [21:0] btb_bank0_rd_data_way0_out_7; // @[Reg.scala 27:20]
wire [21:0] _T_747 = _T_722 ? btb_bank0_rd_data_way0_out_7 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_747 = _T_722 ? btb_bank0_rd_data_way0_out_7 : 22'h0; // @[Mux.scala 27:72]
wire [21:0] _T_762 = _T_761 | _T_747; // @[Mux.scala 27:72] wire [21:0] _T_762 = _T_761 | _T_747; // @[Mux.scala 27:72]
wire _T_724 = btb_rd_addr_f == 8'h8; // @[ifu_bp_ctl.scala 444:80] wire _T_724 = btb_rd_addr_f == 8'h8; // @[ifu_bp_ctl.scala 445:80]
reg [21:0] btb_bank0_rd_data_way0_out_8; // @[Reg.scala 27:20] reg [21:0] btb_bank0_rd_data_way0_out_8; // @[Reg.scala 27:20]
wire [21:0] _T_748 = _T_724 ? btb_bank0_rd_data_way0_out_8 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_748 = _T_724 ? btb_bank0_rd_data_way0_out_8 : 22'h0; // @[Mux.scala 27:72]
wire [21:0] _T_763 = _T_762 | _T_748; // @[Mux.scala 27:72] wire [21:0] _T_763 = _T_762 | _T_748; // @[Mux.scala 27:72]
wire _T_726 = btb_rd_addr_f == 8'h9; // @[ifu_bp_ctl.scala 444:80] wire _T_726 = btb_rd_addr_f == 8'h9; // @[ifu_bp_ctl.scala 445:80]
reg [21:0] btb_bank0_rd_data_way0_out_9; // @[Reg.scala 27:20] reg [21:0] btb_bank0_rd_data_way0_out_9; // @[Reg.scala 27:20]
wire [21:0] _T_749 = _T_726 ? btb_bank0_rd_data_way0_out_9 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_749 = _T_726 ? btb_bank0_rd_data_way0_out_9 : 22'h0; // @[Mux.scala 27:72]
wire [21:0] _T_764 = _T_763 | _T_749; // @[Mux.scala 27:72] wire [21:0] _T_764 = _T_763 | _T_749; // @[Mux.scala 27:72]
wire _T_728 = btb_rd_addr_f == 8'ha; // @[ifu_bp_ctl.scala 444:80] wire _T_728 = btb_rd_addr_f == 8'ha; // @[ifu_bp_ctl.scala 445:80]
reg [21:0] btb_bank0_rd_data_way0_out_10; // @[Reg.scala 27:20] reg [21:0] btb_bank0_rd_data_way0_out_10; // @[Reg.scala 27:20]
wire [21:0] _T_750 = _T_728 ? btb_bank0_rd_data_way0_out_10 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_750 = _T_728 ? btb_bank0_rd_data_way0_out_10 : 22'h0; // @[Mux.scala 27:72]
wire [21:0] _T_765 = _T_764 | _T_750; // @[Mux.scala 27:72] wire [21:0] _T_765 = _T_764 | _T_750; // @[Mux.scala 27:72]
wire _T_730 = btb_rd_addr_f == 8'hb; // @[ifu_bp_ctl.scala 444:80] wire _T_730 = btb_rd_addr_f == 8'hb; // @[ifu_bp_ctl.scala 445:80]
reg [21:0] btb_bank0_rd_data_way0_out_11; // @[Reg.scala 27:20] reg [21:0] btb_bank0_rd_data_way0_out_11; // @[Reg.scala 27:20]
wire [21:0] _T_751 = _T_730 ? btb_bank0_rd_data_way0_out_11 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_751 = _T_730 ? btb_bank0_rd_data_way0_out_11 : 22'h0; // @[Mux.scala 27:72]
wire [21:0] _T_766 = _T_765 | _T_751; // @[Mux.scala 27:72] wire [21:0] _T_766 = _T_765 | _T_751; // @[Mux.scala 27:72]
wire _T_732 = btb_rd_addr_f == 8'hc; // @[ifu_bp_ctl.scala 444:80] wire _T_732 = btb_rd_addr_f == 8'hc; // @[ifu_bp_ctl.scala 445:80]
reg [21:0] btb_bank0_rd_data_way0_out_12; // @[Reg.scala 27:20] reg [21:0] btb_bank0_rd_data_way0_out_12; // @[Reg.scala 27:20]
wire [21:0] _T_752 = _T_732 ? btb_bank0_rd_data_way0_out_12 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_752 = _T_732 ? btb_bank0_rd_data_way0_out_12 : 22'h0; // @[Mux.scala 27:72]
wire [21:0] _T_767 = _T_766 | _T_752; // @[Mux.scala 27:72] wire [21:0] _T_767 = _T_766 | _T_752; // @[Mux.scala 27:72]
wire _T_734 = btb_rd_addr_f == 8'hd; // @[ifu_bp_ctl.scala 444:80] wire _T_734 = btb_rd_addr_f == 8'hd; // @[ifu_bp_ctl.scala 445:80]
reg [21:0] btb_bank0_rd_data_way0_out_13; // @[Reg.scala 27:20] reg [21:0] btb_bank0_rd_data_way0_out_13; // @[Reg.scala 27:20]
wire [21:0] _T_753 = _T_734 ? btb_bank0_rd_data_way0_out_13 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_753 = _T_734 ? btb_bank0_rd_data_way0_out_13 : 22'h0; // @[Mux.scala 27:72]
wire [21:0] _T_768 = _T_767 | _T_753; // @[Mux.scala 27:72] wire [21:0] _T_768 = _T_767 | _T_753; // @[Mux.scala 27:72]
wire _T_736 = btb_rd_addr_f == 8'he; // @[ifu_bp_ctl.scala 444:80] wire _T_736 = btb_rd_addr_f == 8'he; // @[ifu_bp_ctl.scala 445:80]
reg [21:0] btb_bank0_rd_data_way0_out_14; // @[Reg.scala 27:20] reg [21:0] btb_bank0_rd_data_way0_out_14; // @[Reg.scala 27:20]
wire [21:0] _T_754 = _T_736 ? btb_bank0_rd_data_way0_out_14 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_754 = _T_736 ? btb_bank0_rd_data_way0_out_14 : 22'h0; // @[Mux.scala 27:72]
wire [21:0] _T_769 = _T_768 | _T_754; // @[Mux.scala 27:72] wire [21:0] _T_769 = _T_768 | _T_754; // @[Mux.scala 27:72]
wire _T_738 = btb_rd_addr_f == 8'hf; // @[ifu_bp_ctl.scala 444:80] wire _T_738 = btb_rd_addr_f == 8'hf; // @[ifu_bp_ctl.scala 445:80]
reg [21:0] btb_bank0_rd_data_way0_out_15; // @[Reg.scala 27:20] reg [21:0] btb_bank0_rd_data_way0_out_15; // @[Reg.scala 27:20]
wire [21:0] _T_755 = _T_738 ? btb_bank0_rd_data_way0_out_15 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_755 = _T_738 ? btb_bank0_rd_data_way0_out_15 : 22'h0; // @[Mux.scala 27:72]
wire [21:0] btb_bank0_rd_data_way0_f = _T_769 | _T_755; // @[Mux.scala 27:72] wire [21:0] btb_bank0_rd_data_way0_f = _T_769 | _T_755; // @[Mux.scala 27:72]
@ -515,53 +515,53 @@ module ifu_bp_ctl(
wire _T_97 = tag_match_way1_f & _T_96; // @[ifu_bp_ctl.scala 163:22] wire _T_97 = tag_match_way1_f & _T_96; // @[ifu_bp_ctl.scala 163:22]
wire [1:0] tag_match_way1_expanded_f = {_T_92,_T_97}; // @[Cat.scala 29:58] wire [1:0] tag_match_way1_expanded_f = {_T_92,_T_97}; // @[Cat.scala 29:58]
wire [1:0] wayhit_f = tag_match_way0_expanded_f | tag_match_way1_expanded_f; // @[ifu_bp_ctl.scala 172:41] wire [1:0] wayhit_f = tag_match_way0_expanded_f | tag_match_way1_expanded_f; // @[ifu_bp_ctl.scala 172:41]
wire [1:0] _T_601 = _T_599 & wayhit_f; // @[ifu_bp_ctl.scala 439:49] wire [1:0] _T_601 = _T_599 & wayhit_f; // @[ifu_bp_ctl.scala 440:48]
wire [1:0] _T_604 = io_ifc_fetch_addr_f[1] ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] wire [1:0] _T_604 = io_ifc_fetch_addr_f[1] ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
wire _T_836 = btb_rd_addr_p1_f == 8'h0; // @[ifu_bp_ctl.scala 448:86] wire _T_836 = btb_rd_addr_p1_f == 8'h0; // @[ifu_bp_ctl.scala 449:86]
wire [21:0] _T_868 = _T_836 ? btb_bank0_rd_data_way0_out_0 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_868 = _T_836 ? btb_bank0_rd_data_way0_out_0 : 22'h0; // @[Mux.scala 27:72]
wire _T_838 = btb_rd_addr_p1_f == 8'h1; // @[ifu_bp_ctl.scala 448:86] wire _T_838 = btb_rd_addr_p1_f == 8'h1; // @[ifu_bp_ctl.scala 449:86]
wire [21:0] _T_869 = _T_838 ? btb_bank0_rd_data_way0_out_1 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_869 = _T_838 ? btb_bank0_rd_data_way0_out_1 : 22'h0; // @[Mux.scala 27:72]
wire [21:0] _T_884 = _T_868 | _T_869; // @[Mux.scala 27:72] wire [21:0] _T_884 = _T_868 | _T_869; // @[Mux.scala 27:72]
wire _T_840 = btb_rd_addr_p1_f == 8'h2; // @[ifu_bp_ctl.scala 448:86] wire _T_840 = btb_rd_addr_p1_f == 8'h2; // @[ifu_bp_ctl.scala 449:86]
wire [21:0] _T_870 = _T_840 ? btb_bank0_rd_data_way0_out_2 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_870 = _T_840 ? btb_bank0_rd_data_way0_out_2 : 22'h0; // @[Mux.scala 27:72]
wire [21:0] _T_885 = _T_884 | _T_870; // @[Mux.scala 27:72] wire [21:0] _T_885 = _T_884 | _T_870; // @[Mux.scala 27:72]
wire _T_842 = btb_rd_addr_p1_f == 8'h3; // @[ifu_bp_ctl.scala 448:86] wire _T_842 = btb_rd_addr_p1_f == 8'h3; // @[ifu_bp_ctl.scala 449:86]
wire [21:0] _T_871 = _T_842 ? btb_bank0_rd_data_way0_out_3 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_871 = _T_842 ? btb_bank0_rd_data_way0_out_3 : 22'h0; // @[Mux.scala 27:72]
wire [21:0] _T_886 = _T_885 | _T_871; // @[Mux.scala 27:72] wire [21:0] _T_886 = _T_885 | _T_871; // @[Mux.scala 27:72]
wire _T_844 = btb_rd_addr_p1_f == 8'h4; // @[ifu_bp_ctl.scala 448:86] wire _T_844 = btb_rd_addr_p1_f == 8'h4; // @[ifu_bp_ctl.scala 449:86]
wire [21:0] _T_872 = _T_844 ? btb_bank0_rd_data_way0_out_4 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_872 = _T_844 ? btb_bank0_rd_data_way0_out_4 : 22'h0; // @[Mux.scala 27:72]
wire [21:0] _T_887 = _T_886 | _T_872; // @[Mux.scala 27:72] wire [21:0] _T_887 = _T_886 | _T_872; // @[Mux.scala 27:72]
wire _T_846 = btb_rd_addr_p1_f == 8'h5; // @[ifu_bp_ctl.scala 448:86] wire _T_846 = btb_rd_addr_p1_f == 8'h5; // @[ifu_bp_ctl.scala 449:86]
wire [21:0] _T_873 = _T_846 ? btb_bank0_rd_data_way0_out_5 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_873 = _T_846 ? btb_bank0_rd_data_way0_out_5 : 22'h0; // @[Mux.scala 27:72]
wire [21:0] _T_888 = _T_887 | _T_873; // @[Mux.scala 27:72] wire [21:0] _T_888 = _T_887 | _T_873; // @[Mux.scala 27:72]
wire _T_848 = btb_rd_addr_p1_f == 8'h6; // @[ifu_bp_ctl.scala 448:86] wire _T_848 = btb_rd_addr_p1_f == 8'h6; // @[ifu_bp_ctl.scala 449:86]
wire [21:0] _T_874 = _T_848 ? btb_bank0_rd_data_way0_out_6 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_874 = _T_848 ? btb_bank0_rd_data_way0_out_6 : 22'h0; // @[Mux.scala 27:72]
wire [21:0] _T_889 = _T_888 | _T_874; // @[Mux.scala 27:72] wire [21:0] _T_889 = _T_888 | _T_874; // @[Mux.scala 27:72]
wire _T_850 = btb_rd_addr_p1_f == 8'h7; // @[ifu_bp_ctl.scala 448:86] wire _T_850 = btb_rd_addr_p1_f == 8'h7; // @[ifu_bp_ctl.scala 449:86]
wire [21:0] _T_875 = _T_850 ? btb_bank0_rd_data_way0_out_7 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_875 = _T_850 ? btb_bank0_rd_data_way0_out_7 : 22'h0; // @[Mux.scala 27:72]
wire [21:0] _T_890 = _T_889 | _T_875; // @[Mux.scala 27:72] wire [21:0] _T_890 = _T_889 | _T_875; // @[Mux.scala 27:72]
wire _T_852 = btb_rd_addr_p1_f == 8'h8; // @[ifu_bp_ctl.scala 448:86] wire _T_852 = btb_rd_addr_p1_f == 8'h8; // @[ifu_bp_ctl.scala 449:86]
wire [21:0] _T_876 = _T_852 ? btb_bank0_rd_data_way0_out_8 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_876 = _T_852 ? btb_bank0_rd_data_way0_out_8 : 22'h0; // @[Mux.scala 27:72]
wire [21:0] _T_891 = _T_890 | _T_876; // @[Mux.scala 27:72] wire [21:0] _T_891 = _T_890 | _T_876; // @[Mux.scala 27:72]
wire _T_854 = btb_rd_addr_p1_f == 8'h9; // @[ifu_bp_ctl.scala 448:86] wire _T_854 = btb_rd_addr_p1_f == 8'h9; // @[ifu_bp_ctl.scala 449:86]
wire [21:0] _T_877 = _T_854 ? btb_bank0_rd_data_way0_out_9 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_877 = _T_854 ? btb_bank0_rd_data_way0_out_9 : 22'h0; // @[Mux.scala 27:72]
wire [21:0] _T_892 = _T_891 | _T_877; // @[Mux.scala 27:72] wire [21:0] _T_892 = _T_891 | _T_877; // @[Mux.scala 27:72]
wire _T_856 = btb_rd_addr_p1_f == 8'ha; // @[ifu_bp_ctl.scala 448:86] wire _T_856 = btb_rd_addr_p1_f == 8'ha; // @[ifu_bp_ctl.scala 449:86]
wire [21:0] _T_878 = _T_856 ? btb_bank0_rd_data_way0_out_10 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_878 = _T_856 ? btb_bank0_rd_data_way0_out_10 : 22'h0; // @[Mux.scala 27:72]
wire [21:0] _T_893 = _T_892 | _T_878; // @[Mux.scala 27:72] wire [21:0] _T_893 = _T_892 | _T_878; // @[Mux.scala 27:72]
wire _T_858 = btb_rd_addr_p1_f == 8'hb; // @[ifu_bp_ctl.scala 448:86] wire _T_858 = btb_rd_addr_p1_f == 8'hb; // @[ifu_bp_ctl.scala 449:86]
wire [21:0] _T_879 = _T_858 ? btb_bank0_rd_data_way0_out_11 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_879 = _T_858 ? btb_bank0_rd_data_way0_out_11 : 22'h0; // @[Mux.scala 27:72]
wire [21:0] _T_894 = _T_893 | _T_879; // @[Mux.scala 27:72] wire [21:0] _T_894 = _T_893 | _T_879; // @[Mux.scala 27:72]
wire _T_860 = btb_rd_addr_p1_f == 8'hc; // @[ifu_bp_ctl.scala 448:86] wire _T_860 = btb_rd_addr_p1_f == 8'hc; // @[ifu_bp_ctl.scala 449:86]
wire [21:0] _T_880 = _T_860 ? btb_bank0_rd_data_way0_out_12 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_880 = _T_860 ? btb_bank0_rd_data_way0_out_12 : 22'h0; // @[Mux.scala 27:72]
wire [21:0] _T_895 = _T_894 | _T_880; // @[Mux.scala 27:72] wire [21:0] _T_895 = _T_894 | _T_880; // @[Mux.scala 27:72]
wire _T_862 = btb_rd_addr_p1_f == 8'hd; // @[ifu_bp_ctl.scala 448:86] wire _T_862 = btb_rd_addr_p1_f == 8'hd; // @[ifu_bp_ctl.scala 449:86]
wire [21:0] _T_881 = _T_862 ? btb_bank0_rd_data_way0_out_13 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_881 = _T_862 ? btb_bank0_rd_data_way0_out_13 : 22'h0; // @[Mux.scala 27:72]
wire [21:0] _T_896 = _T_895 | _T_881; // @[Mux.scala 27:72] wire [21:0] _T_896 = _T_895 | _T_881; // @[Mux.scala 27:72]
wire _T_864 = btb_rd_addr_p1_f == 8'he; // @[ifu_bp_ctl.scala 448:86] wire _T_864 = btb_rd_addr_p1_f == 8'he; // @[ifu_bp_ctl.scala 449:86]
wire [21:0] _T_882 = _T_864 ? btb_bank0_rd_data_way0_out_14 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_882 = _T_864 ? btb_bank0_rd_data_way0_out_14 : 22'h0; // @[Mux.scala 27:72]
wire [21:0] _T_897 = _T_896 | _T_882; // @[Mux.scala 27:72] wire [21:0] _T_897 = _T_896 | _T_882; // @[Mux.scala 27:72]
wire _T_866 = btb_rd_addr_p1_f == 8'hf; // @[ifu_bp_ctl.scala 448:86] wire _T_866 = btb_rd_addr_p1_f == 8'hf; // @[ifu_bp_ctl.scala 449:86]
wire [21:0] _T_883 = _T_866 ? btb_bank0_rd_data_way0_out_15 : 22'h0; // @[Mux.scala 27:72] wire [21:0] _T_883 = _T_866 ? btb_bank0_rd_data_way0_out_15 : 22'h0; // @[Mux.scala 27:72]
wire [21:0] btb_bank0_rd_data_way0_p1_f = _T_897 | _T_883; // @[Mux.scala 27:72] wire [21:0] btb_bank0_rd_data_way0_p1_f = _T_897 | _T_883; // @[Mux.scala 27:72]
wire [4:0] _T_35 = _T_8[13:9] ^ _T_8[18:14]; // @[lib.scala 42:111] wire [4:0] _T_35 = _T_8[13:9] ^ _T_8[18:14]; // @[lib.scala 42:111]
@ -624,15 +624,15 @@ module ifu_bp_ctl(
wire [1:0] tag_match_way1_expanded_p1_f = {_T_110,_T_115}; // @[Cat.scala 29:58] wire [1:0] tag_match_way1_expanded_p1_f = {_T_110,_T_115}; // @[Cat.scala 29:58]
wire [1:0] wayhit_p1_f = tag_match_way0_expanded_p1_f | tag_match_way1_expanded_p1_f; // @[ifu_bp_ctl.scala 174:47] wire [1:0] wayhit_p1_f = tag_match_way0_expanded_p1_f | tag_match_way1_expanded_p1_f; // @[ifu_bp_ctl.scala 174:47]
wire [1:0] _T_607 = {wayhit_p1_f[0],wayhit_f[1]}; // @[Cat.scala 29:58] wire [1:0] _T_607 = {wayhit_p1_f[0],wayhit_f[1]}; // @[Cat.scala 29:58]
wire [1:0] _T_608 = _T_604 & _T_607; // @[ifu_bp_ctl.scala 439:100] wire [1:0] _T_608 = _T_604 & _T_607; // @[ifu_bp_ctl.scala 440:100]
wire [1:0] _T_609 = _T_601 | _T_608; // @[ifu_bp_ctl.scala 439:66]
wire eoc_near = &io_ifc_fetch_addr_f[4:2]; // @[ifu_bp_ctl.scala 257:64] wire eoc_near = &io_ifc_fetch_addr_f[4:2]; // @[ifu_bp_ctl.scala 257:64]
wire _T_210 = ~eoc_near; // @[ifu_bp_ctl.scala 259:15] wire _T_210 = ~eoc_near; // @[ifu_bp_ctl.scala 259:15]
wire [1:0] _T_212 = ~io_ifc_fetch_addr_f[1:0]; // @[ifu_bp_ctl.scala 259:28] wire [1:0] _T_212 = ~io_ifc_fetch_addr_f[1:0]; // @[ifu_bp_ctl.scala 259:28]
wire _T_213 = |_T_212; // @[ifu_bp_ctl.scala 259:58] wire _T_213 = |_T_212; // @[ifu_bp_ctl.scala 259:58]
wire eoc_mask = _T_210 | _T_213; // @[ifu_bp_ctl.scala 259:25] wire eoc_mask = _T_210 | _T_213; // @[ifu_bp_ctl.scala 259:25]
wire [1:0] _T_610 = {eoc_mask,1'h1}; // @[Cat.scala 29:58] wire [1:0] _T_609 = {eoc_mask,1'h1}; // @[Cat.scala 29:58]
wire [1:0] vwayhit_f = _T_609 & _T_610; // @[ifu_bp_ctl.scala 439:136] wire [1:0] _T_610 = _T_608 & _T_609; // @[ifu_bp_ctl.scala 440:135]
wire [1:0] vwayhit_f = _T_601 | _T_610; // @[ifu_bp_ctl.scala 440:65]
wire _T_258 = bht_vbank1_rd_data_f[1] & vwayhit_f[1]; // @[ifu_bp_ctl.scala 296:69] wire _T_258 = bht_vbank1_rd_data_f[1] & vwayhit_f[1]; // @[ifu_bp_ctl.scala 296:69]
wire [1:0] _T_1914 = _T_1946 ? bht_bank_rd_data_out_0_0 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_1914 = _T_1946 ? bht_bank_rd_data_out_0_0 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_1915 = _T_1948 ? bht_bank_rd_data_out_0_1 : 2'h0; // @[Mux.scala 27:72] wire [1:0] _T_1915 = _T_1948 ? bht_bank_rd_data_out_0_1 : 2'h0; // @[Mux.scala 27:72]
@ -811,182 +811,182 @@ module ifu_bp_ctl(
wire _T_595 = io_dec_bp_dec_tlu_br0_r_pkt_bits_way & dec_tlu_error_wb; // @[ifu_bp_ctl.scala 435:98] wire _T_595 = io_dec_bp_dec_tlu_br0_r_pkt_bits_way & dec_tlu_error_wb; // @[ifu_bp_ctl.scala 435:98]
wire btb_wr_en_way1 = _T_594 | _T_595; // @[ifu_bp_ctl.scala 435:80] wire btb_wr_en_way1 = _T_594 | _T_595; // @[ifu_bp_ctl.scala 435:80]
wire [7:0] btb_wr_addr = dec_tlu_error_wb ? io_exu_bp_exu_i0_br_index_r : io_exu_bp_exu_mp_index; // @[ifu_bp_ctl.scala 438:24] wire [7:0] btb_wr_addr = dec_tlu_error_wb ? io_exu_bp_exu_i0_br_index_r : io_exu_bp_exu_mp_index; // @[ifu_bp_ctl.scala 438:24]
wire _T_612 = btb_wr_addr == 8'h0; // @[ifu_bp_ctl.scala 441:98] wire _T_612 = btb_wr_addr == 8'h0; // @[ifu_bp_ctl.scala 442:98]
wire _T_613 = _T_612 & btb_wr_en_way0; // @[ifu_bp_ctl.scala 441:107] wire _T_613 = _T_612 & btb_wr_en_way0; // @[ifu_bp_ctl.scala 442:107]
wire _T_615 = btb_wr_addr == 8'h1; // @[ifu_bp_ctl.scala 441:98] wire _T_615 = btb_wr_addr == 8'h1; // @[ifu_bp_ctl.scala 442:98]
wire _T_616 = _T_615 & btb_wr_en_way0; // @[ifu_bp_ctl.scala 441:107] wire _T_616 = _T_615 & btb_wr_en_way0; // @[ifu_bp_ctl.scala 442:107]
wire _T_618 = btb_wr_addr == 8'h2; // @[ifu_bp_ctl.scala 441:98] wire _T_618 = btb_wr_addr == 8'h2; // @[ifu_bp_ctl.scala 442:98]
wire _T_619 = _T_618 & btb_wr_en_way0; // @[ifu_bp_ctl.scala 441:107] wire _T_619 = _T_618 & btb_wr_en_way0; // @[ifu_bp_ctl.scala 442:107]
wire _T_621 = btb_wr_addr == 8'h3; // @[ifu_bp_ctl.scala 441:98] wire _T_621 = btb_wr_addr == 8'h3; // @[ifu_bp_ctl.scala 442:98]
wire _T_622 = _T_621 & btb_wr_en_way0; // @[ifu_bp_ctl.scala 441:107] wire _T_622 = _T_621 & btb_wr_en_way0; // @[ifu_bp_ctl.scala 442:107]
wire _T_624 = btb_wr_addr == 8'h4; // @[ifu_bp_ctl.scala 441:98] wire _T_624 = btb_wr_addr == 8'h4; // @[ifu_bp_ctl.scala 442:98]
wire _T_625 = _T_624 & btb_wr_en_way0; // @[ifu_bp_ctl.scala 441:107] wire _T_625 = _T_624 & btb_wr_en_way0; // @[ifu_bp_ctl.scala 442:107]
wire _T_627 = btb_wr_addr == 8'h5; // @[ifu_bp_ctl.scala 441:98] wire _T_627 = btb_wr_addr == 8'h5; // @[ifu_bp_ctl.scala 442:98]
wire _T_628 = _T_627 & btb_wr_en_way0; // @[ifu_bp_ctl.scala 441:107] wire _T_628 = _T_627 & btb_wr_en_way0; // @[ifu_bp_ctl.scala 442:107]
wire _T_630 = btb_wr_addr == 8'h6; // @[ifu_bp_ctl.scala 441:98] wire _T_630 = btb_wr_addr == 8'h6; // @[ifu_bp_ctl.scala 442:98]
wire _T_631 = _T_630 & btb_wr_en_way0; // @[ifu_bp_ctl.scala 441:107] wire _T_631 = _T_630 & btb_wr_en_way0; // @[ifu_bp_ctl.scala 442:107]
wire _T_633 = btb_wr_addr == 8'h7; // @[ifu_bp_ctl.scala 441:98] wire _T_633 = btb_wr_addr == 8'h7; // @[ifu_bp_ctl.scala 442:98]
wire _T_634 = _T_633 & btb_wr_en_way0; // @[ifu_bp_ctl.scala 441:107] wire _T_634 = _T_633 & btb_wr_en_way0; // @[ifu_bp_ctl.scala 442:107]
wire _T_636 = btb_wr_addr == 8'h8; // @[ifu_bp_ctl.scala 441:98] wire _T_636 = btb_wr_addr == 8'h8; // @[ifu_bp_ctl.scala 442:98]
wire _T_637 = _T_636 & btb_wr_en_way0; // @[ifu_bp_ctl.scala 441:107] wire _T_637 = _T_636 & btb_wr_en_way0; // @[ifu_bp_ctl.scala 442:107]
wire _T_639 = btb_wr_addr == 8'h9; // @[ifu_bp_ctl.scala 441:98] wire _T_639 = btb_wr_addr == 8'h9; // @[ifu_bp_ctl.scala 442:98]
wire _T_640 = _T_639 & btb_wr_en_way0; // @[ifu_bp_ctl.scala 441:107] wire _T_640 = _T_639 & btb_wr_en_way0; // @[ifu_bp_ctl.scala 442:107]
wire _T_642 = btb_wr_addr == 8'ha; // @[ifu_bp_ctl.scala 441:98] wire _T_642 = btb_wr_addr == 8'ha; // @[ifu_bp_ctl.scala 442:98]
wire _T_643 = _T_642 & btb_wr_en_way0; // @[ifu_bp_ctl.scala 441:107] wire _T_643 = _T_642 & btb_wr_en_way0; // @[ifu_bp_ctl.scala 442:107]
wire _T_645 = btb_wr_addr == 8'hb; // @[ifu_bp_ctl.scala 441:98] wire _T_645 = btb_wr_addr == 8'hb; // @[ifu_bp_ctl.scala 442:98]
wire _T_646 = _T_645 & btb_wr_en_way0; // @[ifu_bp_ctl.scala 441:107] wire _T_646 = _T_645 & btb_wr_en_way0; // @[ifu_bp_ctl.scala 442:107]
wire _T_648 = btb_wr_addr == 8'hc; // @[ifu_bp_ctl.scala 441:98] wire _T_648 = btb_wr_addr == 8'hc; // @[ifu_bp_ctl.scala 442:98]
wire _T_649 = _T_648 & btb_wr_en_way0; // @[ifu_bp_ctl.scala 441:107] wire _T_649 = _T_648 & btb_wr_en_way0; // @[ifu_bp_ctl.scala 442:107]
wire _T_651 = btb_wr_addr == 8'hd; // @[ifu_bp_ctl.scala 441:98] wire _T_651 = btb_wr_addr == 8'hd; // @[ifu_bp_ctl.scala 442:98]
wire _T_652 = _T_651 & btb_wr_en_way0; // @[ifu_bp_ctl.scala 441:107] wire _T_652 = _T_651 & btb_wr_en_way0; // @[ifu_bp_ctl.scala 442:107]
wire _T_654 = btb_wr_addr == 8'he; // @[ifu_bp_ctl.scala 441:98] wire _T_654 = btb_wr_addr == 8'he; // @[ifu_bp_ctl.scala 442:98]
wire _T_655 = _T_654 & btb_wr_en_way0; // @[ifu_bp_ctl.scala 441:107] wire _T_655 = _T_654 & btb_wr_en_way0; // @[ifu_bp_ctl.scala 442:107]
wire _T_657 = btb_wr_addr == 8'hf; // @[ifu_bp_ctl.scala 441:98] wire _T_657 = btb_wr_addr == 8'hf; // @[ifu_bp_ctl.scala 442:98]
wire _T_658 = _T_657 & btb_wr_en_way0; // @[ifu_bp_ctl.scala 441:107] wire _T_658 = _T_657 & btb_wr_en_way0; // @[ifu_bp_ctl.scala 442:107]
wire _T_661 = _T_612 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 442:107] wire _T_661 = _T_612 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 443:107]
wire _T_664 = _T_615 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 442:107] wire _T_664 = _T_615 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 443:107]
wire _T_667 = _T_618 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 442:107] wire _T_667 = _T_618 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 443:107]
wire _T_670 = _T_621 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 442:107] wire _T_670 = _T_621 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 443:107]
wire _T_673 = _T_624 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 442:107] wire _T_673 = _T_624 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 443:107]
wire _T_676 = _T_627 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 442:107] wire _T_676 = _T_627 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 443:107]
wire _T_679 = _T_630 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 442:107] wire _T_679 = _T_630 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 443:107]
wire _T_682 = _T_633 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 442:107] wire _T_682 = _T_633 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 443:107]
wire _T_685 = _T_636 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 442:107] wire _T_685 = _T_636 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 443:107]
wire _T_688 = _T_639 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 442:107] wire _T_688 = _T_639 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 443:107]
wire _T_691 = _T_642 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 442:107] wire _T_691 = _T_642 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 443:107]
wire _T_694 = _T_645 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 442:107] wire _T_694 = _T_645 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 443:107]
wire _T_697 = _T_648 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 442:107] wire _T_697 = _T_648 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 443:107]
wire _T_700 = _T_651 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 442:107] wire _T_700 = _T_651 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 443:107]
wire _T_703 = _T_654 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 442:107] wire _T_703 = _T_654 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 443:107]
wire _T_706 = _T_657 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 442:107] wire _T_706 = _T_657 & btb_wr_en_way1; // @[ifu_bp_ctl.scala 443:107]
wire _T_966 = mp_hashed == 8'h0; // @[ifu_bp_ctl.scala 514:109] wire _T_966 = mp_hashed == 8'h0; // @[ifu_bp_ctl.scala 515:109]
wire _T_971 = br0_hashed_wb == 8'h0; // @[ifu_bp_ctl.scala 515:109] wire _T_971 = br0_hashed_wb == 8'h0; // @[ifu_bp_ctl.scala 516:109]
wire _T_989 = bht_wr_en2[0] & _T_971; // @[ifu_bp_ctl.scala 520:23] wire _T_989 = bht_wr_en2[0] & _T_971; // @[ifu_bp_ctl.scala 521:23]
wire _T_997 = br0_hashed_wb == 8'h1; // @[ifu_bp_ctl.scala 520:74] wire _T_997 = br0_hashed_wb == 8'h1; // @[ifu_bp_ctl.scala 521:74]
wire _T_998 = bht_wr_en2[0] & _T_997; // @[ifu_bp_ctl.scala 520:23] wire _T_998 = bht_wr_en2[0] & _T_997; // @[ifu_bp_ctl.scala 521:23]
wire _T_1006 = br0_hashed_wb == 8'h2; // @[ifu_bp_ctl.scala 520:74] wire _T_1006 = br0_hashed_wb == 8'h2; // @[ifu_bp_ctl.scala 521:74]
wire _T_1007 = bht_wr_en2[0] & _T_1006; // @[ifu_bp_ctl.scala 520:23] wire _T_1007 = bht_wr_en2[0] & _T_1006; // @[ifu_bp_ctl.scala 521:23]
wire _T_1015 = br0_hashed_wb == 8'h3; // @[ifu_bp_ctl.scala 520:74] wire _T_1015 = br0_hashed_wb == 8'h3; // @[ifu_bp_ctl.scala 521:74]
wire _T_1016 = bht_wr_en2[0] & _T_1015; // @[ifu_bp_ctl.scala 520:23] wire _T_1016 = bht_wr_en2[0] & _T_1015; // @[ifu_bp_ctl.scala 521:23]
wire _T_1024 = br0_hashed_wb == 8'h4; // @[ifu_bp_ctl.scala 520:74] wire _T_1024 = br0_hashed_wb == 8'h4; // @[ifu_bp_ctl.scala 521:74]
wire _T_1025 = bht_wr_en2[0] & _T_1024; // @[ifu_bp_ctl.scala 520:23] wire _T_1025 = bht_wr_en2[0] & _T_1024; // @[ifu_bp_ctl.scala 521:23]
wire _T_1033 = br0_hashed_wb == 8'h5; // @[ifu_bp_ctl.scala 520:74] wire _T_1033 = br0_hashed_wb == 8'h5; // @[ifu_bp_ctl.scala 521:74]
wire _T_1034 = bht_wr_en2[0] & _T_1033; // @[ifu_bp_ctl.scala 520:23] wire _T_1034 = bht_wr_en2[0] & _T_1033; // @[ifu_bp_ctl.scala 521:23]
wire _T_1042 = br0_hashed_wb == 8'h6; // @[ifu_bp_ctl.scala 520:74] wire _T_1042 = br0_hashed_wb == 8'h6; // @[ifu_bp_ctl.scala 521:74]
wire _T_1043 = bht_wr_en2[0] & _T_1042; // @[ifu_bp_ctl.scala 520:23] wire _T_1043 = bht_wr_en2[0] & _T_1042; // @[ifu_bp_ctl.scala 521:23]
wire _T_1051 = br0_hashed_wb == 8'h7; // @[ifu_bp_ctl.scala 520:74] wire _T_1051 = br0_hashed_wb == 8'h7; // @[ifu_bp_ctl.scala 521:74]
wire _T_1052 = bht_wr_en2[0] & _T_1051; // @[ifu_bp_ctl.scala 520:23] wire _T_1052 = bht_wr_en2[0] & _T_1051; // @[ifu_bp_ctl.scala 521:23]
wire _T_1060 = br0_hashed_wb == 8'h8; // @[ifu_bp_ctl.scala 520:74] wire _T_1060 = br0_hashed_wb == 8'h8; // @[ifu_bp_ctl.scala 521:74]
wire _T_1061 = bht_wr_en2[0] & _T_1060; // @[ifu_bp_ctl.scala 520:23] wire _T_1061 = bht_wr_en2[0] & _T_1060; // @[ifu_bp_ctl.scala 521:23]
wire _T_1069 = br0_hashed_wb == 8'h9; // @[ifu_bp_ctl.scala 520:74] wire _T_1069 = br0_hashed_wb == 8'h9; // @[ifu_bp_ctl.scala 521:74]
wire _T_1070 = bht_wr_en2[0] & _T_1069; // @[ifu_bp_ctl.scala 520:23] wire _T_1070 = bht_wr_en2[0] & _T_1069; // @[ifu_bp_ctl.scala 521:23]
wire _T_1078 = br0_hashed_wb == 8'ha; // @[ifu_bp_ctl.scala 520:74] wire _T_1078 = br0_hashed_wb == 8'ha; // @[ifu_bp_ctl.scala 521:74]
wire _T_1079 = bht_wr_en2[0] & _T_1078; // @[ifu_bp_ctl.scala 520:23] wire _T_1079 = bht_wr_en2[0] & _T_1078; // @[ifu_bp_ctl.scala 521:23]
wire _T_1087 = br0_hashed_wb == 8'hb; // @[ifu_bp_ctl.scala 520:74] wire _T_1087 = br0_hashed_wb == 8'hb; // @[ifu_bp_ctl.scala 521:74]
wire _T_1088 = bht_wr_en2[0] & _T_1087; // @[ifu_bp_ctl.scala 520:23] wire _T_1088 = bht_wr_en2[0] & _T_1087; // @[ifu_bp_ctl.scala 521:23]
wire _T_1096 = br0_hashed_wb == 8'hc; // @[ifu_bp_ctl.scala 520:74] wire _T_1096 = br0_hashed_wb == 8'hc; // @[ifu_bp_ctl.scala 521:74]
wire _T_1097 = bht_wr_en2[0] & _T_1096; // @[ifu_bp_ctl.scala 520:23] wire _T_1097 = bht_wr_en2[0] & _T_1096; // @[ifu_bp_ctl.scala 521:23]
wire _T_1105 = br0_hashed_wb == 8'hd; // @[ifu_bp_ctl.scala 520:74] wire _T_1105 = br0_hashed_wb == 8'hd; // @[ifu_bp_ctl.scala 521:74]
wire _T_1106 = bht_wr_en2[0] & _T_1105; // @[ifu_bp_ctl.scala 520:23] wire _T_1106 = bht_wr_en2[0] & _T_1105; // @[ifu_bp_ctl.scala 521:23]
wire _T_1114 = br0_hashed_wb == 8'he; // @[ifu_bp_ctl.scala 520:74] wire _T_1114 = br0_hashed_wb == 8'he; // @[ifu_bp_ctl.scala 521:74]
wire _T_1115 = bht_wr_en2[0] & _T_1114; // @[ifu_bp_ctl.scala 520:23] wire _T_1115 = bht_wr_en2[0] & _T_1114; // @[ifu_bp_ctl.scala 521:23]
wire _T_1123 = br0_hashed_wb == 8'hf; // @[ifu_bp_ctl.scala 520:74] wire _T_1123 = br0_hashed_wb == 8'hf; // @[ifu_bp_ctl.scala 521:74]
wire _T_1124 = bht_wr_en2[0] & _T_1123; // @[ifu_bp_ctl.scala 520:23] wire _T_1124 = bht_wr_en2[0] & _T_1123; // @[ifu_bp_ctl.scala 521:23]
wire _T_1133 = bht_wr_en2[1] & _T_971; // @[ifu_bp_ctl.scala 520:23] wire _T_1133 = bht_wr_en2[1] & _T_971; // @[ifu_bp_ctl.scala 521:23]
wire _T_1142 = bht_wr_en2[1] & _T_997; // @[ifu_bp_ctl.scala 520:23] wire _T_1142 = bht_wr_en2[1] & _T_997; // @[ifu_bp_ctl.scala 521:23]
wire _T_1151 = bht_wr_en2[1] & _T_1006; // @[ifu_bp_ctl.scala 520:23] wire _T_1151 = bht_wr_en2[1] & _T_1006; // @[ifu_bp_ctl.scala 521:23]
wire _T_1160 = bht_wr_en2[1] & _T_1015; // @[ifu_bp_ctl.scala 520:23] wire _T_1160 = bht_wr_en2[1] & _T_1015; // @[ifu_bp_ctl.scala 521:23]
wire _T_1169 = bht_wr_en2[1] & _T_1024; // @[ifu_bp_ctl.scala 520:23] wire _T_1169 = bht_wr_en2[1] & _T_1024; // @[ifu_bp_ctl.scala 521:23]
wire _T_1178 = bht_wr_en2[1] & _T_1033; // @[ifu_bp_ctl.scala 520:23] wire _T_1178 = bht_wr_en2[1] & _T_1033; // @[ifu_bp_ctl.scala 521:23]
wire _T_1187 = bht_wr_en2[1] & _T_1042; // @[ifu_bp_ctl.scala 520:23] wire _T_1187 = bht_wr_en2[1] & _T_1042; // @[ifu_bp_ctl.scala 521:23]
wire _T_1196 = bht_wr_en2[1] & _T_1051; // @[ifu_bp_ctl.scala 520:23] wire _T_1196 = bht_wr_en2[1] & _T_1051; // @[ifu_bp_ctl.scala 521:23]
wire _T_1205 = bht_wr_en2[1] & _T_1060; // @[ifu_bp_ctl.scala 520:23] wire _T_1205 = bht_wr_en2[1] & _T_1060; // @[ifu_bp_ctl.scala 521:23]
wire _T_1214 = bht_wr_en2[1] & _T_1069; // @[ifu_bp_ctl.scala 520:23] wire _T_1214 = bht_wr_en2[1] & _T_1069; // @[ifu_bp_ctl.scala 521:23]
wire _T_1223 = bht_wr_en2[1] & _T_1078; // @[ifu_bp_ctl.scala 520:23] wire _T_1223 = bht_wr_en2[1] & _T_1078; // @[ifu_bp_ctl.scala 521:23]
wire _T_1232 = bht_wr_en2[1] & _T_1087; // @[ifu_bp_ctl.scala 520:23] wire _T_1232 = bht_wr_en2[1] & _T_1087; // @[ifu_bp_ctl.scala 521:23]
wire _T_1241 = bht_wr_en2[1] & _T_1096; // @[ifu_bp_ctl.scala 520:23] wire _T_1241 = bht_wr_en2[1] & _T_1096; // @[ifu_bp_ctl.scala 521:23]
wire _T_1250 = bht_wr_en2[1] & _T_1105; // @[ifu_bp_ctl.scala 520:23] wire _T_1250 = bht_wr_en2[1] & _T_1105; // @[ifu_bp_ctl.scala 521:23]
wire _T_1259 = bht_wr_en2[1] & _T_1114; // @[ifu_bp_ctl.scala 520:23] wire _T_1259 = bht_wr_en2[1] & _T_1114; // @[ifu_bp_ctl.scala 521:23]
wire _T_1268 = bht_wr_en2[1] & _T_1123; // @[ifu_bp_ctl.scala 520:23] wire _T_1268 = bht_wr_en2[1] & _T_1123; // @[ifu_bp_ctl.scala 521:23]
wire _T_1277 = bht_wr_en0[0] & _T_966; // @[ifu_bp_ctl.scala 528:45] wire _T_1277 = bht_wr_en0[0] & _T_966; // @[ifu_bp_ctl.scala 529:45]
wire bht_bank_sel_0_0_0 = _T_1277 | _T_989; // @[ifu_bp_ctl.scala 528:223] wire bht_bank_sel_0_0_0 = _T_1277 | _T_989; // @[ifu_bp_ctl.scala 529:223]
wire _T_1293 = mp_hashed == 8'h1; // @[ifu_bp_ctl.scala 528:97] wire _T_1293 = mp_hashed == 8'h1; // @[ifu_bp_ctl.scala 529:97]
wire _T_1294 = bht_wr_en0[0] & _T_1293; // @[ifu_bp_ctl.scala 528:45] wire _T_1294 = bht_wr_en0[0] & _T_1293; // @[ifu_bp_ctl.scala 529:45]
wire bht_bank_sel_0_0_1 = _T_1294 | _T_998; // @[ifu_bp_ctl.scala 528:223] wire bht_bank_sel_0_0_1 = _T_1294 | _T_998; // @[ifu_bp_ctl.scala 529:223]
wire _T_1310 = mp_hashed == 8'h2; // @[ifu_bp_ctl.scala 528:97] wire _T_1310 = mp_hashed == 8'h2; // @[ifu_bp_ctl.scala 529:97]
wire _T_1311 = bht_wr_en0[0] & _T_1310; // @[ifu_bp_ctl.scala 528:45] wire _T_1311 = bht_wr_en0[0] & _T_1310; // @[ifu_bp_ctl.scala 529:45]
wire bht_bank_sel_0_0_2 = _T_1311 | _T_1007; // @[ifu_bp_ctl.scala 528:223] wire bht_bank_sel_0_0_2 = _T_1311 | _T_1007; // @[ifu_bp_ctl.scala 529:223]
wire _T_1327 = mp_hashed == 8'h3; // @[ifu_bp_ctl.scala 528:97] wire _T_1327 = mp_hashed == 8'h3; // @[ifu_bp_ctl.scala 529:97]
wire _T_1328 = bht_wr_en0[0] & _T_1327; // @[ifu_bp_ctl.scala 528:45] wire _T_1328 = bht_wr_en0[0] & _T_1327; // @[ifu_bp_ctl.scala 529:45]
wire bht_bank_sel_0_0_3 = _T_1328 | _T_1016; // @[ifu_bp_ctl.scala 528:223] wire bht_bank_sel_0_0_3 = _T_1328 | _T_1016; // @[ifu_bp_ctl.scala 529:223]
wire _T_1344 = mp_hashed == 8'h4; // @[ifu_bp_ctl.scala 528:97] wire _T_1344 = mp_hashed == 8'h4; // @[ifu_bp_ctl.scala 529:97]
wire _T_1345 = bht_wr_en0[0] & _T_1344; // @[ifu_bp_ctl.scala 528:45] wire _T_1345 = bht_wr_en0[0] & _T_1344; // @[ifu_bp_ctl.scala 529:45]
wire bht_bank_sel_0_0_4 = _T_1345 | _T_1025; // @[ifu_bp_ctl.scala 528:223] wire bht_bank_sel_0_0_4 = _T_1345 | _T_1025; // @[ifu_bp_ctl.scala 529:223]
wire _T_1361 = mp_hashed == 8'h5; // @[ifu_bp_ctl.scala 528:97] wire _T_1361 = mp_hashed == 8'h5; // @[ifu_bp_ctl.scala 529:97]
wire _T_1362 = bht_wr_en0[0] & _T_1361; // @[ifu_bp_ctl.scala 528:45] wire _T_1362 = bht_wr_en0[0] & _T_1361; // @[ifu_bp_ctl.scala 529:45]
wire bht_bank_sel_0_0_5 = _T_1362 | _T_1034; // @[ifu_bp_ctl.scala 528:223] wire bht_bank_sel_0_0_5 = _T_1362 | _T_1034; // @[ifu_bp_ctl.scala 529:223]
wire _T_1378 = mp_hashed == 8'h6; // @[ifu_bp_ctl.scala 528:97] wire _T_1378 = mp_hashed == 8'h6; // @[ifu_bp_ctl.scala 529:97]
wire _T_1379 = bht_wr_en0[0] & _T_1378; // @[ifu_bp_ctl.scala 528:45] wire _T_1379 = bht_wr_en0[0] & _T_1378; // @[ifu_bp_ctl.scala 529:45]
wire bht_bank_sel_0_0_6 = _T_1379 | _T_1043; // @[ifu_bp_ctl.scala 528:223] wire bht_bank_sel_0_0_6 = _T_1379 | _T_1043; // @[ifu_bp_ctl.scala 529:223]
wire _T_1395 = mp_hashed == 8'h7; // @[ifu_bp_ctl.scala 528:97] wire _T_1395 = mp_hashed == 8'h7; // @[ifu_bp_ctl.scala 529:97]
wire _T_1396 = bht_wr_en0[0] & _T_1395; // @[ifu_bp_ctl.scala 528:45] wire _T_1396 = bht_wr_en0[0] & _T_1395; // @[ifu_bp_ctl.scala 529:45]
wire bht_bank_sel_0_0_7 = _T_1396 | _T_1052; // @[ifu_bp_ctl.scala 528:223] wire bht_bank_sel_0_0_7 = _T_1396 | _T_1052; // @[ifu_bp_ctl.scala 529:223]
wire _T_1412 = mp_hashed == 8'h8; // @[ifu_bp_ctl.scala 528:97] wire _T_1412 = mp_hashed == 8'h8; // @[ifu_bp_ctl.scala 529:97]
wire _T_1413 = bht_wr_en0[0] & _T_1412; // @[ifu_bp_ctl.scala 528:45] wire _T_1413 = bht_wr_en0[0] & _T_1412; // @[ifu_bp_ctl.scala 529:45]
wire bht_bank_sel_0_0_8 = _T_1413 | _T_1061; // @[ifu_bp_ctl.scala 528:223] wire bht_bank_sel_0_0_8 = _T_1413 | _T_1061; // @[ifu_bp_ctl.scala 529:223]
wire _T_1429 = mp_hashed == 8'h9; // @[ifu_bp_ctl.scala 528:97] wire _T_1429 = mp_hashed == 8'h9; // @[ifu_bp_ctl.scala 529:97]
wire _T_1430 = bht_wr_en0[0] & _T_1429; // @[ifu_bp_ctl.scala 528:45] wire _T_1430 = bht_wr_en0[0] & _T_1429; // @[ifu_bp_ctl.scala 529:45]
wire bht_bank_sel_0_0_9 = _T_1430 | _T_1070; // @[ifu_bp_ctl.scala 528:223] wire bht_bank_sel_0_0_9 = _T_1430 | _T_1070; // @[ifu_bp_ctl.scala 529:223]
wire _T_1446 = mp_hashed == 8'ha; // @[ifu_bp_ctl.scala 528:97] wire _T_1446 = mp_hashed == 8'ha; // @[ifu_bp_ctl.scala 529:97]
wire _T_1447 = bht_wr_en0[0] & _T_1446; // @[ifu_bp_ctl.scala 528:45] wire _T_1447 = bht_wr_en0[0] & _T_1446; // @[ifu_bp_ctl.scala 529:45]
wire bht_bank_sel_0_0_10 = _T_1447 | _T_1079; // @[ifu_bp_ctl.scala 528:223] wire bht_bank_sel_0_0_10 = _T_1447 | _T_1079; // @[ifu_bp_ctl.scala 529:223]
wire _T_1463 = mp_hashed == 8'hb; // @[ifu_bp_ctl.scala 528:97] wire _T_1463 = mp_hashed == 8'hb; // @[ifu_bp_ctl.scala 529:97]
wire _T_1464 = bht_wr_en0[0] & _T_1463; // @[ifu_bp_ctl.scala 528:45] wire _T_1464 = bht_wr_en0[0] & _T_1463; // @[ifu_bp_ctl.scala 529:45]
wire bht_bank_sel_0_0_11 = _T_1464 | _T_1088; // @[ifu_bp_ctl.scala 528:223] wire bht_bank_sel_0_0_11 = _T_1464 | _T_1088; // @[ifu_bp_ctl.scala 529:223]
wire _T_1480 = mp_hashed == 8'hc; // @[ifu_bp_ctl.scala 528:97] wire _T_1480 = mp_hashed == 8'hc; // @[ifu_bp_ctl.scala 529:97]
wire _T_1481 = bht_wr_en0[0] & _T_1480; // @[ifu_bp_ctl.scala 528:45] wire _T_1481 = bht_wr_en0[0] & _T_1480; // @[ifu_bp_ctl.scala 529:45]
wire bht_bank_sel_0_0_12 = _T_1481 | _T_1097; // @[ifu_bp_ctl.scala 528:223] wire bht_bank_sel_0_0_12 = _T_1481 | _T_1097; // @[ifu_bp_ctl.scala 529:223]
wire _T_1497 = mp_hashed == 8'hd; // @[ifu_bp_ctl.scala 528:97] wire _T_1497 = mp_hashed == 8'hd; // @[ifu_bp_ctl.scala 529:97]
wire _T_1498 = bht_wr_en0[0] & _T_1497; // @[ifu_bp_ctl.scala 528:45] wire _T_1498 = bht_wr_en0[0] & _T_1497; // @[ifu_bp_ctl.scala 529:45]
wire bht_bank_sel_0_0_13 = _T_1498 | _T_1106; // @[ifu_bp_ctl.scala 528:223] wire bht_bank_sel_0_0_13 = _T_1498 | _T_1106; // @[ifu_bp_ctl.scala 529:223]
wire _T_1514 = mp_hashed == 8'he; // @[ifu_bp_ctl.scala 528:97] wire _T_1514 = mp_hashed == 8'he; // @[ifu_bp_ctl.scala 529:97]
wire _T_1515 = bht_wr_en0[0] & _T_1514; // @[ifu_bp_ctl.scala 528:45] wire _T_1515 = bht_wr_en0[0] & _T_1514; // @[ifu_bp_ctl.scala 529:45]
wire bht_bank_sel_0_0_14 = _T_1515 | _T_1115; // @[ifu_bp_ctl.scala 528:223] wire bht_bank_sel_0_0_14 = _T_1515 | _T_1115; // @[ifu_bp_ctl.scala 529:223]
wire _T_1531 = mp_hashed == 8'hf; // @[ifu_bp_ctl.scala 528:97] wire _T_1531 = mp_hashed == 8'hf; // @[ifu_bp_ctl.scala 529:97]
wire _T_1532 = bht_wr_en0[0] & _T_1531; // @[ifu_bp_ctl.scala 528:45] wire _T_1532 = bht_wr_en0[0] & _T_1531; // @[ifu_bp_ctl.scala 529:45]
wire bht_bank_sel_0_0_15 = _T_1532 | _T_1124; // @[ifu_bp_ctl.scala 528:223] wire bht_bank_sel_0_0_15 = _T_1532 | _T_1124; // @[ifu_bp_ctl.scala 529:223]
wire _T_1549 = bht_wr_en0[1] & _T_966; // @[ifu_bp_ctl.scala 528:45] wire _T_1549 = bht_wr_en0[1] & _T_966; // @[ifu_bp_ctl.scala 529:45]
wire bht_bank_sel_1_0_0 = _T_1549 | _T_1133; // @[ifu_bp_ctl.scala 528:223] wire bht_bank_sel_1_0_0 = _T_1549 | _T_1133; // @[ifu_bp_ctl.scala 529:223]
wire _T_1566 = bht_wr_en0[1] & _T_1293; // @[ifu_bp_ctl.scala 528:45] wire _T_1566 = bht_wr_en0[1] & _T_1293; // @[ifu_bp_ctl.scala 529:45]
wire bht_bank_sel_1_0_1 = _T_1566 | _T_1142; // @[ifu_bp_ctl.scala 528:223] wire bht_bank_sel_1_0_1 = _T_1566 | _T_1142; // @[ifu_bp_ctl.scala 529:223]
wire _T_1583 = bht_wr_en0[1] & _T_1310; // @[ifu_bp_ctl.scala 528:45] wire _T_1583 = bht_wr_en0[1] & _T_1310; // @[ifu_bp_ctl.scala 529:45]
wire bht_bank_sel_1_0_2 = _T_1583 | _T_1151; // @[ifu_bp_ctl.scala 528:223] wire bht_bank_sel_1_0_2 = _T_1583 | _T_1151; // @[ifu_bp_ctl.scala 529:223]
wire _T_1600 = bht_wr_en0[1] & _T_1327; // @[ifu_bp_ctl.scala 528:45] wire _T_1600 = bht_wr_en0[1] & _T_1327; // @[ifu_bp_ctl.scala 529:45]
wire bht_bank_sel_1_0_3 = _T_1600 | _T_1160; // @[ifu_bp_ctl.scala 528:223] wire bht_bank_sel_1_0_3 = _T_1600 | _T_1160; // @[ifu_bp_ctl.scala 529:223]
wire _T_1617 = bht_wr_en0[1] & _T_1344; // @[ifu_bp_ctl.scala 528:45] wire _T_1617 = bht_wr_en0[1] & _T_1344; // @[ifu_bp_ctl.scala 529:45]
wire bht_bank_sel_1_0_4 = _T_1617 | _T_1169; // @[ifu_bp_ctl.scala 528:223] wire bht_bank_sel_1_0_4 = _T_1617 | _T_1169; // @[ifu_bp_ctl.scala 529:223]
wire _T_1634 = bht_wr_en0[1] & _T_1361; // @[ifu_bp_ctl.scala 528:45] wire _T_1634 = bht_wr_en0[1] & _T_1361; // @[ifu_bp_ctl.scala 529:45]
wire bht_bank_sel_1_0_5 = _T_1634 | _T_1178; // @[ifu_bp_ctl.scala 528:223] wire bht_bank_sel_1_0_5 = _T_1634 | _T_1178; // @[ifu_bp_ctl.scala 529:223]
wire _T_1651 = bht_wr_en0[1] & _T_1378; // @[ifu_bp_ctl.scala 528:45] wire _T_1651 = bht_wr_en0[1] & _T_1378; // @[ifu_bp_ctl.scala 529:45]
wire bht_bank_sel_1_0_6 = _T_1651 | _T_1187; // @[ifu_bp_ctl.scala 528:223] wire bht_bank_sel_1_0_6 = _T_1651 | _T_1187; // @[ifu_bp_ctl.scala 529:223]
wire _T_1668 = bht_wr_en0[1] & _T_1395; // @[ifu_bp_ctl.scala 528:45] wire _T_1668 = bht_wr_en0[1] & _T_1395; // @[ifu_bp_ctl.scala 529:45]
wire bht_bank_sel_1_0_7 = _T_1668 | _T_1196; // @[ifu_bp_ctl.scala 528:223] wire bht_bank_sel_1_0_7 = _T_1668 | _T_1196; // @[ifu_bp_ctl.scala 529:223]
wire _T_1685 = bht_wr_en0[1] & _T_1412; // @[ifu_bp_ctl.scala 528:45] wire _T_1685 = bht_wr_en0[1] & _T_1412; // @[ifu_bp_ctl.scala 529:45]
wire bht_bank_sel_1_0_8 = _T_1685 | _T_1205; // @[ifu_bp_ctl.scala 528:223] wire bht_bank_sel_1_0_8 = _T_1685 | _T_1205; // @[ifu_bp_ctl.scala 529:223]
wire _T_1702 = bht_wr_en0[1] & _T_1429; // @[ifu_bp_ctl.scala 528:45] wire _T_1702 = bht_wr_en0[1] & _T_1429; // @[ifu_bp_ctl.scala 529:45]
wire bht_bank_sel_1_0_9 = _T_1702 | _T_1214; // @[ifu_bp_ctl.scala 528:223] wire bht_bank_sel_1_0_9 = _T_1702 | _T_1214; // @[ifu_bp_ctl.scala 529:223]
wire _T_1719 = bht_wr_en0[1] & _T_1446; // @[ifu_bp_ctl.scala 528:45] wire _T_1719 = bht_wr_en0[1] & _T_1446; // @[ifu_bp_ctl.scala 529:45]
wire bht_bank_sel_1_0_10 = _T_1719 | _T_1223; // @[ifu_bp_ctl.scala 528:223] wire bht_bank_sel_1_0_10 = _T_1719 | _T_1223; // @[ifu_bp_ctl.scala 529:223]
wire _T_1736 = bht_wr_en0[1] & _T_1463; // @[ifu_bp_ctl.scala 528:45] wire _T_1736 = bht_wr_en0[1] & _T_1463; // @[ifu_bp_ctl.scala 529:45]
wire bht_bank_sel_1_0_11 = _T_1736 | _T_1232; // @[ifu_bp_ctl.scala 528:223] wire bht_bank_sel_1_0_11 = _T_1736 | _T_1232; // @[ifu_bp_ctl.scala 529:223]
wire _T_1753 = bht_wr_en0[1] & _T_1480; // @[ifu_bp_ctl.scala 528:45] wire _T_1753 = bht_wr_en0[1] & _T_1480; // @[ifu_bp_ctl.scala 529:45]
wire bht_bank_sel_1_0_12 = _T_1753 | _T_1241; // @[ifu_bp_ctl.scala 528:223] wire bht_bank_sel_1_0_12 = _T_1753 | _T_1241; // @[ifu_bp_ctl.scala 529:223]
wire _T_1770 = bht_wr_en0[1] & _T_1497; // @[ifu_bp_ctl.scala 528:45] wire _T_1770 = bht_wr_en0[1] & _T_1497; // @[ifu_bp_ctl.scala 529:45]
wire bht_bank_sel_1_0_13 = _T_1770 | _T_1250; // @[ifu_bp_ctl.scala 528:223] wire bht_bank_sel_1_0_13 = _T_1770 | _T_1250; // @[ifu_bp_ctl.scala 529:223]
wire _T_1787 = bht_wr_en0[1] & _T_1514; // @[ifu_bp_ctl.scala 528:45] wire _T_1787 = bht_wr_en0[1] & _T_1514; // @[ifu_bp_ctl.scala 529:45]
wire bht_bank_sel_1_0_14 = _T_1787 | _T_1259; // @[ifu_bp_ctl.scala 528:223] wire bht_bank_sel_1_0_14 = _T_1787 | _T_1259; // @[ifu_bp_ctl.scala 529:223]
wire _T_1804 = bht_wr_en0[1] & _T_1531; // @[ifu_bp_ctl.scala 528:45] wire _T_1804 = bht_wr_en0[1] & _T_1531; // @[ifu_bp_ctl.scala 529:45]
wire bht_bank_sel_1_0_15 = _T_1804 | _T_1268; // @[ifu_bp_ctl.scala 528:223] wire bht_bank_sel_1_0_15 = _T_1804 | _T_1268; // @[ifu_bp_ctl.scala 529:223]
rvclkhdr rvclkhdr ( // @[lib.scala 399:23] rvclkhdr rvclkhdr ( // @[lib.scala 399:23]
.io_clk(rvclkhdr_io_clk), .io_clk(rvclkhdr_io_clk),
.io_en(rvclkhdr_io_en) .io_en(rvclkhdr_io_en)

3
src/main/scala/ifu/ifu_bp_ctl.scala
View File

@ -436,7 +436,8 @@ if(!BTB_FULLYA) {
// Writing is always done from dec or exu check if the dec have a valid data // Writing is always done from dec or exu check if the dec have a valid data
val btb_wr_addr = Mux(dec_tlu_error_wb.asBool, btb_error_addr_wb, exu_mp_addr) val btb_wr_addr = Mux(dec_tlu_error_wb.asBool, btb_error_addr_wb, exu_mp_addr)
vwayhit_f := ((Fill(2,io.ifc_fetch_addr_f(0)) & wayhit_f(1,0)) | (Fill(2,io.ifc_fetch_addr_f(1)) & Cat(wayhit_p1_f(0),wayhit_f(1)))) & Cat(eoc_mask,1.U)
vwayhit_f := (Fill(2,io.ifc_fetch_addr_f(0)) & wayhit_f(1,0)) | ((Fill(2,io.ifc_fetch_addr_f(1)) & Cat(wayhit_p1_f(0),wayhit_f(1))) & Cat(eoc_mask,1.U))
val btb_bank0_rd_data_way0_out = (0 until LRU_SIZE).map(i => rvdffe(btb_wr_data, ((btb_wr_addr === i.U) & btb_wr_en_way0).asBool, clock, io.scan_mode)) val btb_bank0_rd_data_way0_out = (0 until LRU_SIZE).map(i => rvdffe(btb_wr_data, ((btb_wr_addr === i.U) & btb_wr_en_way0).asBool, clock, io.scan_mode))
val btb_bank0_rd_data_way1_out = (0 until LRU_SIZE).map(i => rvdffe(btb_wr_data, ((btb_wr_addr === i.U) & btb_wr_en_way1).asBool, clock, io.scan_mode)) val btb_bank0_rd_data_way1_out = (0 until LRU_SIZE).map(i => rvdffe(btb_wr_data, ((btb_wr_addr === i.U) & btb_wr_en_way1).asBool, clock, io.scan_mode))

BIN
target/scala-2.12/classes/ifu/bp$.class
View File

Binary file not shown.

BIN
target/scala-2.12/classes/ifu/bp$delayedInit$body.class
View File

Binary file not shown.

BIN
target/scala-2.12/classes/ifu/ifu_bp_ctl.class
View File

Binary file not shown.