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i0 legal corrected

This commit is contained in:
​Laraib Khan 2021-01-28 12:16:34 +05:00
parent 80ac7ee439
commit 630c544fb1
7 changed files with 1494 additions and 1481 deletions
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@ -2075,7 +2075,7 @@ module dec_decode_ctl(
wire i0_pcall_12b_offset = i0_pcall_imm[11] ? _T_383 : _T_385; // @[dec_decode_ctl.scala 454:33] wire i0_pcall_12b_offset = i0_pcall_imm[11] ? _T_383 : _T_385; // @[dec_decode_ctl.scala 454:33]
wire i0_dp_raw_imm20 = i0_dec_io_out_imm20; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12] wire i0_dp_raw_imm20 = i0_dec_io_out_imm20; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
wire _T_386 = i0_pcall_12b_offset & i0_dp_raw_imm20; // @[dec_decode_ctl.scala 455:47] wire _T_386 = i0_pcall_12b_offset & i0_dp_raw_imm20; // @[dec_decode_ctl.scala 455:47]
wire [4:0] i0r_rd = io_dec_i0_instr_d[11:7]; // @[dec_decode_ctl.scala 680:16] wire [4:0] i0r_rd = io_dec_i0_instr_d[11:7]; // @[dec_decode_ctl.scala 678:16]
wire _T_387 = i0r_rd == 5'h1; // @[dec_decode_ctl.scala 455:76] wire _T_387 = i0r_rd == 5'h1; // @[dec_decode_ctl.scala 455:76]
wire _T_388 = i0r_rd == 5'h5; // @[dec_decode_ctl.scala 455:98] wire _T_388 = i0r_rd == 5'h5; // @[dec_decode_ctl.scala 455:98]
wire _T_389 = _T_387 | _T_388; // @[dec_decode_ctl.scala 455:89] wire _T_389 = _T_387 | _T_388; // @[dec_decode_ctl.scala 455:89]
@ -2090,7 +2090,7 @@ module dec_decode_ctl(
wire _T_410 = i0_dp_raw_jal & i0_dp_raw_imm12; // @[dec_decode_ctl.scala 463:37] wire _T_410 = i0_dp_raw_jal & i0_dp_raw_imm12; // @[dec_decode_ctl.scala 463:37]
wire _T_411 = i0r_rd == 5'h0; // @[dec_decode_ctl.scala 463:65] wire _T_411 = i0r_rd == 5'h0; // @[dec_decode_ctl.scala 463:65]
wire _T_412 = _T_410 & _T_411; // @[dec_decode_ctl.scala 463:55] wire _T_412 = _T_410 & _T_411; // @[dec_decode_ctl.scala 463:55]
wire [4:0] i0r_rs1 = io_dec_i0_instr_d[19:15]; // @[dec_decode_ctl.scala 678:16] wire [4:0] i0r_rs1 = io_dec_i0_instr_d[19:15]; // @[dec_decode_ctl.scala 676:16]
wire _T_413 = i0r_rs1 == 5'h1; // @[dec_decode_ctl.scala 463:89] wire _T_413 = i0r_rs1 == 5'h1; // @[dec_decode_ctl.scala 463:89]
wire _T_414 = i0r_rs1 == 5'h5; // @[dec_decode_ctl.scala 463:111] wire _T_414 = i0r_rs1 == 5'h5; // @[dec_decode_ctl.scala 463:111]
wire _T_415 = _T_413 | _T_414; // @[dec_decode_ctl.scala 463:101] wire _T_415 = _T_413 | _T_414; // @[dec_decode_ctl.scala 463:101]
@ -2124,16 +2124,44 @@ module dec_decode_ctl(
wire _T_429 = ~io_dec_debug_fence_d; // @[dec_decode_ctl.scala 521:42] wire _T_429 = ~io_dec_debug_fence_d; // @[dec_decode_ctl.scala 521:42]
wire i0_csr_write = i0_dp_csr_write & _T_429; // @[dec_decode_ctl.scala 521:40] wire i0_csr_write = i0_dp_csr_write & _T_429; // @[dec_decode_ctl.scala 521:40]
wire any_csr_d = i0_dp_csr_read | i0_csr_write; // @[dec_decode_ctl.scala 529:34] wire any_csr_d = i0_dp_csr_read | i0_csr_write; // @[dec_decode_ctl.scala 529:34]
wire _T_544 = ~any_csr_d; // @[dec_decode_ctl.scala 592:40] wire _T_544 = ~any_csr_d; // @[dec_decode_ctl.scala 590:40]
wire _T_545 = _T_544 | io_dec_csr_legal_d; // @[dec_decode_ctl.scala 592:51] wire _T_545 = _T_544 | io_dec_csr_legal_d; // @[dec_decode_ctl.scala 590:51]
wire i0_legal = i0_dp_legal & _T_545; // @[dec_decode_ctl.scala 592:37] wire _T_546 = i0_dp_legal & _T_545; // @[dec_decode_ctl.scala 590:37]
wire _T_563 = ~i0_legal; // @[dec_decode_ctl.scala 596:49] wire i0_dp_raw_zbe = i0_dec_io_out_zbe; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
wire shift_illegal = io_dec_i0_decode_d & _T_563; // @[dec_decode_ctl.scala 596:47] wire i0_dp_zbe = _T_80 ? 1'h0 : i0_dp_raw_zbe; // @[dec_decode_ctl.scala 282:50]
wire bitmanip_zbe_legal = ~i0_dp_zbe; // @[dec_decode_ctl.scala 723:32]
wire i0_dp_raw_zbc = i0_dec_io_out_zbc; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
wire i0_dp_zbc = _T_80 ? 1'h0 : i0_dp_raw_zbc; // @[dec_decode_ctl.scala 282:50]
wire bitmanip_zbc_legal = ~i0_dp_zbc; // @[dec_decode_ctl.scala 728:32]
wire _T_801 = bitmanip_zbe_legal & bitmanip_zbc_legal; // @[dec_decode_ctl.scala 755:83]
wire i0_dp_raw_zbp = i0_dec_io_out_zbp; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
wire i0_dp_zbp = _T_80 ? 1'h0 : i0_dp_raw_zbp; // @[dec_decode_ctl.scala 282:50]
wire i0_dp_raw_zbb = i0_dec_io_out_zbb; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
wire i0_dp_zbb = _T_80 ? 1'h0 : i0_dp_raw_zbb; // @[dec_decode_ctl.scala 282:50]
wire _T_793 = ~i0_dp_zbb; // @[dec_decode_ctl.scala 733:46]
wire _T_794 = i0_dp_zbp & _T_793; // @[dec_decode_ctl.scala 733:44]
wire bitmanip_zbp_legal = ~_T_794; // @[dec_decode_ctl.scala 733:32]
wire _T_802 = _T_801 & bitmanip_zbp_legal; // @[dec_decode_ctl.scala 755:104]
wire i0_dp_raw_zbr = i0_dec_io_out_zbr; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
wire i0_dp_zbr = _T_80 ? 1'h0 : i0_dp_raw_zbr; // @[dec_decode_ctl.scala 282:50]
wire bitmanip_zbr_legal = ~i0_dp_zbr; // @[dec_decode_ctl.scala 738:32]
wire _T_803 = _T_802 & bitmanip_zbr_legal; // @[dec_decode_ctl.scala 755:125]
wire i0_dp_raw_zbf = i0_dec_io_out_zbf; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
wire i0_dp_zbf = _T_80 ? 1'h0 : i0_dp_raw_zbf; // @[dec_decode_ctl.scala 282:50]
wire bitmanip_zbf_legal = ~i0_dp_zbf; // @[dec_decode_ctl.scala 743:32]
wire _T_804 = _T_803 & bitmanip_zbf_legal; // @[dec_decode_ctl.scala 755:146]
wire i0_dp_raw_zba = i0_dec_io_out_zba; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
wire i0_dp_zba = _T_80 ? 1'h0 : i0_dp_raw_zba; // @[dec_decode_ctl.scala 282:50]
wire bitmanip_zba_legal = ~i0_dp_zba; // @[dec_decode_ctl.scala 748:32]
wire bitmanip_legal = _T_804 & bitmanip_zba_legal; // @[dec_decode_ctl.scala 755:167]
wire i0_legal = _T_546 & bitmanip_legal; // @[dec_decode_ctl.scala 590:73]
wire _T_564 = ~i0_legal; // @[dec_decode_ctl.scala 594:49]
wire shift_illegal = io_dec_i0_decode_d & _T_564; // @[dec_decode_ctl.scala 594:47]
reg illegal_lockout; // @[Reg.scala 27:20] reg illegal_lockout; // @[Reg.scala 27:20]
wire _T_566 = shift_illegal | illegal_lockout; // @[dec_decode_ctl.scala 599:40] wire _T_567 = shift_illegal | illegal_lockout; // @[dec_decode_ctl.scala 597:40]
reg flush_final_r; // @[Reg.scala 27:20] reg flush_final_r; // @[Reg.scala 27:20]
wire _T_567 = ~flush_final_r; // @[dec_decode_ctl.scala 599:61] wire _T_568 = ~flush_final_r; // @[dec_decode_ctl.scala 597:61]
wire illegal_lockout_in = _T_566 & _T_567; // @[dec_decode_ctl.scala 599:59] wire illegal_lockout_in = _T_567 & _T_568; // @[dec_decode_ctl.scala 597:59]
wire _T_26 = illegal_lockout_in ^ illegal_lockout; // @[lib.scala 448:21] wire _T_26 = illegal_lockout_in ^ illegal_lockout; // @[lib.scala 448:21]
wire _T_27 = |_T_26; // @[lib.scala 448:29] wire _T_27 = |_T_26; // @[lib.scala 448:29]
wire i0_dp_raw_postsync = i0_dec_io_out_postsync; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12] wire i0_dp_raw_postsync = i0_dec_io_out_postsync; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
@ -2146,12 +2174,12 @@ module dec_decode_ctl(
wire _T_542 = io_dec_i0_instr_d[31:20] == 12'h7c2; // @[dec_decode_ctl.scala 588:112] wire _T_542 = io_dec_i0_instr_d[31:20] == 12'h7c2; // @[dec_decode_ctl.scala 588:112]
wire _T_543 = i0_csr_write_only_d & _T_542; // @[dec_decode_ctl.scala 588:99] wire _T_543 = i0_csr_write_only_d & _T_542; // @[dec_decode_ctl.scala 588:99]
wire i0_postsync = _T_540 | _T_543; // @[dec_decode_ctl.scala 588:76] wire i0_postsync = _T_540 | _T_543; // @[dec_decode_ctl.scala 588:76]
wire _T_605 = i0_postsync | _T_563; // @[dec_decode_ctl.scala 630:54] wire _T_606 = i0_postsync | _T_564; // @[dec_decode_ctl.scala 628:54]
wire _T_606 = io_dec_i0_decode_d & _T_605; // @[dec_decode_ctl.scala 630:39] wire _T_607 = io_dec_i0_decode_d & _T_606; // @[dec_decode_ctl.scala 628:39]
reg postsync_stall; // @[Reg.scala 27:20] reg postsync_stall; // @[Reg.scala 27:20]
reg x_d_valid; // @[Reg.scala 27:20] reg x_d_valid; // @[Reg.scala 27:20]
wire _T_607 = postsync_stall & x_d_valid; // @[dec_decode_ctl.scala 630:88] wire _T_608 = postsync_stall & x_d_valid; // @[dec_decode_ctl.scala 628:88]
wire ps_stall_in = _T_606 | _T_607; // @[dec_decode_ctl.scala 630:69] wire ps_stall_in = _T_607 | _T_608; // @[dec_decode_ctl.scala 628:69]
wire _T_30 = ps_stall_in ^ postsync_stall; // @[lib.scala 448:21] wire _T_30 = ps_stall_in ^ postsync_stall; // @[lib.scala 448:21]
wire _T_31 = |_T_30; // @[lib.scala 448:29] wire _T_31 = |_T_30; // @[lib.scala 448:29]
reg [3:0] lsu_trigger_match_r; // @[Reg.scala 27:20] reg [3:0] lsu_trigger_match_r; // @[Reg.scala 27:20]
@ -2160,42 +2188,42 @@ module dec_decode_ctl(
reg lsu_pmu_misaligned_r; // @[Reg.scala 27:20] reg lsu_pmu_misaligned_r; // @[Reg.scala 27:20]
wire _T_36 = io_lsu_pmu_misaligned_m ^ lsu_pmu_misaligned_r; // @[lib.scala 470:21] wire _T_36 = io_lsu_pmu_misaligned_m ^ lsu_pmu_misaligned_r; // @[lib.scala 470:21]
wire _T_37 = |_T_36; // @[lib.scala 470:29] wire _T_37 = |_T_36; // @[lib.scala 470:29]
wire i0_legal_decode_d = io_dec_i0_decode_d & i0_legal; // @[dec_decode_ctl.scala 758:46] wire i0_legal_decode_d = io_dec_i0_decode_d & i0_legal; // @[dec_decode_ctl.scala 756:46]
wire i0_dp_raw_div = i0_dec_io_out_div; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12] wire i0_dp_raw_div = i0_dec_io_out_div; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
wire i0_dp_div = _T_80 ? 1'h0 : i0_dp_raw_div; // @[dec_decode_ctl.scala 282:50] wire i0_dp_div = _T_80 ? 1'h0 : i0_dp_raw_div; // @[dec_decode_ctl.scala 282:50]
wire i0_div_decode_d = i0_legal_decode_d & i0_dp_div; // @[dec_decode_ctl.scala 845:55] wire i0_div_decode_d = i0_legal_decode_d & i0_dp_div; // @[dec_decode_ctl.scala 843:55]
wire _T_934 = ~io_exu_div_wren; // @[dec_decode_ctl.scala 847:59] wire _T_935 = ~io_exu_div_wren; // @[dec_decode_ctl.scala 845:59]
wire _T_935 = io_dec_div_active & _T_934; // @[dec_decode_ctl.scala 847:57] wire _T_936 = io_dec_div_active & _T_935; // @[dec_decode_ctl.scala 845:57]
reg x_d_bits_i0div; // @[Reg.scala 27:20] reg x_d_bits_i0div; // @[Reg.scala 27:20]
wire _T_918 = x_d_bits_i0div & x_d_valid; // @[dec_decode_ctl.scala 835:48] wire _T_919 = x_d_bits_i0div & x_d_valid; // @[dec_decode_ctl.scala 833:48]
reg [4:0] x_d_bits_i0rd; // @[Reg.scala 27:20] reg [4:0] x_d_bits_i0rd; // @[Reg.scala 27:20]
wire _T_919 = x_d_bits_i0rd == 5'h0; // @[dec_decode_ctl.scala 835:77] wire _T_920 = x_d_bits_i0rd == 5'h0; // @[dec_decode_ctl.scala 833:77]
wire _T_920 = _T_918 & _T_919; // @[dec_decode_ctl.scala 835:60] wire _T_921 = _T_919 & _T_920; // @[dec_decode_ctl.scala 833:60]
wire _T_922 = _T_918 & io_dec_tlu_flush_lower_r; // @[dec_decode_ctl.scala 836:33] wire _T_923 = _T_919 & io_dec_tlu_flush_lower_r; // @[dec_decode_ctl.scala 834:33]
wire _T_923 = _T_920 | _T_922; // @[dec_decode_ctl.scala 835:94] wire _T_924 = _T_921 | _T_923; // @[dec_decode_ctl.scala 833:94]
reg r_d_bits_i0div; // @[Reg.scala 27:20] reg r_d_bits_i0div; // @[Reg.scala 27:20]
reg r_d_valid; // @[Reg.scala 27:20] reg r_d_valid; // @[Reg.scala 27:20]
wire _T_924 = r_d_bits_i0div & r_d_valid; // @[dec_decode_ctl.scala 837:21] wire _T_925 = r_d_bits_i0div & r_d_valid; // @[dec_decode_ctl.scala 835:21]
wire _T_925 = _T_924 & io_dec_tlu_flush_lower_r; // @[dec_decode_ctl.scala 837:33] wire _T_926 = _T_925 & io_dec_tlu_flush_lower_r; // @[dec_decode_ctl.scala 835:33]
wire _T_926 = _T_925 & io_dec_tlu_i0_kill_writeb_r; // @[dec_decode_ctl.scala 837:60] wire _T_927 = _T_926 & io_dec_tlu_i0_kill_writeb_r; // @[dec_decode_ctl.scala 835:60]
wire div_flush = _T_923 | _T_926; // @[dec_decode_ctl.scala 836:62] wire div_flush = _T_924 | _T_927; // @[dec_decode_ctl.scala 834:62]
wire _T_927 = io_dec_div_active & div_flush; // @[dec_decode_ctl.scala 841:51] wire _T_928 = io_dec_div_active & div_flush; // @[dec_decode_ctl.scala 839:51]
wire div_e1_to_r = _T_918 | _T_924; // @[dec_decode_ctl.scala 833:58] wire div_e1_to_r = _T_919 | _T_925; // @[dec_decode_ctl.scala 831:58]
wire _T_928 = ~div_e1_to_r; // @[dec_decode_ctl.scala 842:26] wire _T_929 = ~div_e1_to_r; // @[dec_decode_ctl.scala 840:26]
wire _T_929 = io_dec_div_active & _T_928; // @[dec_decode_ctl.scala 842:24] wire _T_930 = io_dec_div_active & _T_929; // @[dec_decode_ctl.scala 840:24]
reg [4:0] r_d_bits_i0rd; // @[Reg.scala 27:20] reg [4:0] r_d_bits_i0rd; // @[Reg.scala 27:20]
wire _T_930 = r_d_bits_i0rd == io_div_waddr_wb; // @[dec_decode_ctl.scala 842:56] wire _T_931 = r_d_bits_i0rd == io_div_waddr_wb; // @[dec_decode_ctl.scala 840:56]
wire _T_931 = _T_929 & _T_930; // @[dec_decode_ctl.scala 842:39] wire _T_932 = _T_930 & _T_931; // @[dec_decode_ctl.scala 840:39]
reg r_d_bits_i0v; // @[Reg.scala 27:20] reg r_d_bits_i0v; // @[Reg.scala 27:20]
wire _T_857 = ~io_dec_tlu_flush_lower_wb; // @[dec_decode_ctl.scala 800:51] wire _T_858 = ~io_dec_tlu_flush_lower_wb; // @[dec_decode_ctl.scala 798:51]
wire r_d_in_bits_i0v = r_d_bits_i0v & _T_857; // @[dec_decode_ctl.scala 800:49] wire r_d_in_bits_i0v = r_d_bits_i0v & _T_858; // @[dec_decode_ctl.scala 798:49]
wire _T_868 = ~io_dec_tlu_i0_kill_writeb_r; // @[dec_decode_ctl.scala 808:47] wire _T_869 = ~io_dec_tlu_i0_kill_writeb_r; // @[dec_decode_ctl.scala 806:47]
wire i0_wen_r = r_d_in_bits_i0v & _T_868; // @[dec_decode_ctl.scala 808:45] wire i0_wen_r = r_d_in_bits_i0v & _T_869; // @[dec_decode_ctl.scala 806:45]
wire _T_932 = _T_931 & i0_wen_r; // @[dec_decode_ctl.scala 842:77] wire _T_933 = _T_932 & i0_wen_r; // @[dec_decode_ctl.scala 840:77]
wire nonblock_div_cancel = _T_927 | _T_932; // @[dec_decode_ctl.scala 841:65] wire nonblock_div_cancel = _T_928 | _T_933; // @[dec_decode_ctl.scala 839:65]
wire _T_936 = ~nonblock_div_cancel; // @[dec_decode_ctl.scala 847:78] wire _T_937 = ~nonblock_div_cancel; // @[dec_decode_ctl.scala 845:78]
wire _T_937 = _T_935 & _T_936; // @[dec_decode_ctl.scala 847:76] wire _T_938 = _T_936 & _T_937; // @[dec_decode_ctl.scala 845:76]
wire div_active_in = i0_div_decode_d | _T_937; // @[dec_decode_ctl.scala 847:36] wire div_active_in = i0_div_decode_d | _T_938; // @[dec_decode_ctl.scala 845:36]
reg _T_42; // @[Reg.scala 27:20] reg _T_42; // @[Reg.scala 27:20]
wire _T_40 = div_active_in ^ _T_42; // @[lib.scala 470:21] wire _T_40 = div_active_in ^ _T_42; // @[lib.scala 470:21]
wire _T_41 = |_T_40; // @[lib.scala 470:29] wire _T_41 = |_T_40; // @[lib.scala 470:29]
@ -2274,33 +2302,21 @@ module dec_decode_ctl(
wire i0_dp_rs1 = _T_80 | i0_dp_raw_rs1; // @[dec_decode_ctl.scala 282:50] wire i0_dp_rs1 = _T_80 | i0_dp_raw_rs1; // @[dec_decode_ctl.scala 282:50]
wire i0_dp_raw_alu = i0_dec_io_out_alu; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12] wire i0_dp_raw_alu = i0_dec_io_out_alu; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
wire i0_dp_alu = _T_80 | i0_dp_raw_alu; // @[dec_decode_ctl.scala 282:50] wire i0_dp_alu = _T_80 | i0_dp_raw_alu; // @[dec_decode_ctl.scala 282:50]
wire i0_dp_raw_zba = i0_dec_io_out_zba; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
wire i0_dp_zba = _T_80 ? 1'h0 : i0_dp_raw_zba; // @[dec_decode_ctl.scala 282:50]
wire i0_dp_raw_sh3add = i0_dec_io_out_sh3add; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12] wire i0_dp_raw_sh3add = i0_dec_io_out_sh3add; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
wire i0_dp_raw_sh2add = i0_dec_io_out_sh2add; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12] wire i0_dp_raw_sh2add = i0_dec_io_out_sh2add; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
wire i0_dp_raw_sh1add = i0_dec_io_out_sh1add; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12] wire i0_dp_raw_sh1add = i0_dec_io_out_sh1add; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
wire i0_dp_raw_zbf = i0_dec_io_out_zbf; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
wire i0_dp_zbf = _T_80 ? 1'h0 : i0_dp_raw_zbf; // @[dec_decode_ctl.scala 282:50]
wire i0_dp_raw_bfp = i0_dec_io_out_bfp; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12] wire i0_dp_raw_bfp = i0_dec_io_out_bfp; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
wire i0_dp_raw_zbr = i0_dec_io_out_zbr; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
wire i0_dp_zbr = _T_80 ? 1'h0 : i0_dp_raw_zbr; // @[dec_decode_ctl.scala 282:50]
wire i0_dp_raw_crc32c_w = i0_dec_io_out_crc32c_w; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12] wire i0_dp_raw_crc32c_w = i0_dec_io_out_crc32c_w; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
wire i0_dp_raw_crc32c_h = i0_dec_io_out_crc32c_h; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12] wire i0_dp_raw_crc32c_h = i0_dec_io_out_crc32c_h; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
wire i0_dp_raw_crc32c_b = i0_dec_io_out_crc32c_b; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12] wire i0_dp_raw_crc32c_b = i0_dec_io_out_crc32c_b; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
wire i0_dp_raw_crc32_w = i0_dec_io_out_crc32_w; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12] wire i0_dp_raw_crc32_w = i0_dec_io_out_crc32_w; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
wire i0_dp_raw_crc32_h = i0_dec_io_out_crc32_h; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12] wire i0_dp_raw_crc32_h = i0_dec_io_out_crc32_h; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
wire i0_dp_raw_crc32_b = i0_dec_io_out_crc32_b; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12] wire i0_dp_raw_crc32_b = i0_dec_io_out_crc32_b; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
wire i0_dp_raw_zbp = i0_dec_io_out_zbp; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
wire i0_dp_zbp = _T_80 ? 1'h0 : i0_dp_raw_zbp; // @[dec_decode_ctl.scala 282:50]
wire i0_dp_raw_unshfl = i0_dec_io_out_unshfl; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12] wire i0_dp_raw_unshfl = i0_dec_io_out_unshfl; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
wire i0_dp_raw_shfl = i0_dec_io_out_shfl; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12] wire i0_dp_raw_shfl = i0_dec_io_out_shfl; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
wire i0_dp_raw_zbc = i0_dec_io_out_zbc; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
wire i0_dp_zbc = _T_80 ? 1'h0 : i0_dp_raw_zbc; // @[dec_decode_ctl.scala 282:50]
wire i0_dp_raw_clmulr = i0_dec_io_out_clmulr; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12] wire i0_dp_raw_clmulr = i0_dec_io_out_clmulr; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
wire i0_dp_raw_clmulh = i0_dec_io_out_clmulh; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12] wire i0_dp_raw_clmulh = i0_dec_io_out_clmulh; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
wire i0_dp_raw_clmul = i0_dec_io_out_clmul; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12] wire i0_dp_raw_clmul = i0_dec_io_out_clmul; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
wire i0_dp_raw_zbe = i0_dec_io_out_zbe; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
wire i0_dp_zbe = _T_80 ? 1'h0 : i0_dp_raw_zbe; // @[dec_decode_ctl.scala 282:50]
wire i0_dp_raw_bdep = i0_dec_io_out_bdep; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12] wire i0_dp_raw_bdep = i0_dec_io_out_bdep; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
wire i0_dp_raw_bext = i0_dec_io_out_bext; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12] wire i0_dp_raw_bext = i0_dec_io_out_bext; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
wire i0_dp_raw_zbs = i0_dec_io_out_zbs; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12] wire i0_dp_raw_zbs = i0_dec_io_out_zbs; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
@ -2309,8 +2325,6 @@ module dec_decode_ctl(
wire i0_dp_raw_sbinv = i0_dec_io_out_sbinv; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12] wire i0_dp_raw_sbinv = i0_dec_io_out_sbinv; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
wire i0_dp_raw_sbclr = i0_dec_io_out_sbclr; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12] wire i0_dp_raw_sbclr = i0_dec_io_out_sbclr; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
wire i0_dp_raw_sbset = i0_dec_io_out_sbset; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12] wire i0_dp_raw_sbset = i0_dec_io_out_sbset; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
wire i0_dp_raw_zbb = i0_dec_io_out_zbb; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
wire i0_dp_zbb = _T_80 ? 1'h0 : i0_dp_raw_zbb; // @[dec_decode_ctl.scala 282:50]
wire i0_dp_raw_gorc = i0_dec_io_out_gorc; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12] wire i0_dp_raw_gorc = i0_dec_io_out_gorc; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
wire i0_dp_raw_grev = i0_dec_io_out_grev; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12] wire i0_dp_raw_grev = i0_dec_io_out_grev; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
wire i0_dp_raw_ror = i0_dec_io_out_ror; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12] wire i0_dp_raw_ror = i0_dec_io_out_ror; // @[dec_decode_ctl.scala 147:37 dec_decode_ctl.scala 442:12]
@ -2386,10 +2400,10 @@ module dec_decode_ctl(
wire [3:0] cam_wen = _GEN_262 | _T_123; // @[Mux.scala 27:72] wire [3:0] cam_wen = _GEN_262 | _T_123; // @[Mux.scala 27:72]
reg x_d_bits_i0load; // @[Reg.scala 27:20] reg x_d_bits_i0load; // @[Reg.scala 27:20]
wire [4:0] nonblock_load_rd = x_d_bits_i0load ? x_d_bits_i0rd : 5'h0; // @[dec_decode_ctl.scala 361:31] wire [4:0] nonblock_load_rd = x_d_bits_i0load ? x_d_bits_i0rd : 5'h0; // @[dec_decode_ctl.scala 361:31]
reg [2:0] _T_815; // @[dec_decode_ctl.scala 766:72] reg [2:0] _T_816; // @[dec_decode_ctl.scala 764:72]
wire [3:0] i0_pipe_en = {io_dec_i0_decode_d,_T_815}; // @[Cat.scala 29:58] wire [3:0] i0_pipe_en = {io_dec_i0_decode_d,_T_816}; // @[Cat.scala 29:58]
wire _T_821 = |i0_pipe_en[2:1]; // @[dec_decode_ctl.scala 769:49] wire _T_822 = |i0_pipe_en[2:1]; // @[dec_decode_ctl.scala 767:49]
wire i0_r_ctl_en = _T_821 | io_clk_override; // @[dec_decode_ctl.scala 769:53] wire i0_r_ctl_en = _T_822 | io_clk_override; // @[dec_decode_ctl.scala 767:53]
reg nonblock_load_valid_m_delay; // @[Reg.scala 27:20] reg nonblock_load_valid_m_delay; // @[Reg.scala 27:20]
reg r_d_bits_i0load; // @[Reg.scala 27:20] reg r_d_bits_i0load; // @[Reg.scala 27:20]
wire i0_load_kill_wen_r = nonblock_load_valid_m_delay & r_d_bits_i0load; // @[dec_decode_ctl.scala 366:56] wire i0_load_kill_wen_r = nonblock_load_valid_m_delay & r_d_bits_i0load; // @[dec_decode_ctl.scala 366:56]
@ -2520,7 +2534,7 @@ module dec_decode_ctl(
wire _T_282 = nonblock_load_rd == i0r_rs1; // @[dec_decode_ctl.scala 402:54] wire _T_282 = nonblock_load_rd == i0r_rs1; // @[dec_decode_ctl.scala 402:54]
wire _T_283 = _T_282 & io_dctl_busbuff_lsu_nonblock_load_valid_m; // @[dec_decode_ctl.scala 402:66] wire _T_283 = _T_282 & io_dctl_busbuff_lsu_nonblock_load_valid_m; // @[dec_decode_ctl.scala 402:66]
wire _T_284 = _T_283 & io_decode_exu_dec_i0_rs1_en_d; // @[dec_decode_ctl.scala 402:110] wire _T_284 = _T_283 & io_decode_exu_dec_i0_rs1_en_d; // @[dec_decode_ctl.scala 402:110]
wire [4:0] i0r_rs2 = io_dec_i0_instr_d[24:20]; // @[dec_decode_ctl.scala 679:16] wire [4:0] i0r_rs2 = io_dec_i0_instr_d[24:20]; // @[dec_decode_ctl.scala 677:16]
wire _T_285 = nonblock_load_rd == i0r_rs2; // @[dec_decode_ctl.scala 402:161] wire _T_285 = nonblock_load_rd == i0r_rs2; // @[dec_decode_ctl.scala 402:161]
wire _T_286 = _T_285 & io_dctl_busbuff_lsu_nonblock_load_valid_m; // @[dec_decode_ctl.scala 402:173] wire _T_286 = _T_285 & io_dctl_busbuff_lsu_nonblock_load_valid_m; // @[dec_decode_ctl.scala 402:173]
wire _T_287 = _T_286 & io_decode_exu_dec_i0_rs2_en_d; // @[dec_decode_ctl.scala 402:217] wire _T_287 = _T_286 & io_decode_exu_dec_i0_rs2_en_d; // @[dec_decode_ctl.scala 402:217]
@ -2606,35 +2620,35 @@ module dec_decode_ctl(
wire _T_421 = _T_419 & _T_420; // @[dec_decode_ctl.scala 466:50] wire _T_421 = _T_419 & _T_420; // @[dec_decode_ctl.scala 466:50]
wire _T_422 = ~i0_pret_case; // @[dec_decode_ctl.scala 466:67] wire _T_422 = ~i0_pret_case; // @[dec_decode_ctl.scala 466:67]
wire _T_425 = i0r_rs1 == 5'h2; // @[dec_decode_ctl.scala 510:41] wire _T_425 = i0r_rs1 == 5'h2; // @[dec_decode_ctl.scala 510:41]
wire lsu_decode_d = i0_legal_decode_d & i0_dp_lsu; // @[dec_decode_ctl.scala 635:40] wire lsu_decode_d = i0_legal_decode_d & i0_dp_lsu; // @[dec_decode_ctl.scala 633:40]
wire _T_1018 = i0_dp_load | i0_dp_store; // @[dec_decode_ctl.scala 903:43] wire _T_1019 = i0_dp_load | i0_dp_store; // @[dec_decode_ctl.scala 901:43]
reg x_d_bits_i0v; // @[Reg.scala 27:20] reg x_d_bits_i0v; // @[Reg.scala 27:20]
wire _T_992 = io_decode_exu_dec_i0_rs1_en_d & x_d_bits_i0v; // @[dec_decode_ctl.scala 883:59] wire _T_993 = io_decode_exu_dec_i0_rs1_en_d & x_d_bits_i0v; // @[dec_decode_ctl.scala 881:59]
wire _T_993 = x_d_bits_i0rd == i0r_rs1; // @[dec_decode_ctl.scala 883:91] wire _T_994 = x_d_bits_i0rd == i0r_rs1; // @[dec_decode_ctl.scala 881:91]
wire i0_rs1_depend_i0_x = _T_992 & _T_993; // @[dec_decode_ctl.scala 883:74] wire i0_rs1_depend_i0_x = _T_993 & _T_994; // @[dec_decode_ctl.scala 881:74]
wire _T_994 = io_decode_exu_dec_i0_rs1_en_d & r_d_bits_i0v; // @[dec_decode_ctl.scala 884:59] wire _T_995 = io_decode_exu_dec_i0_rs1_en_d & r_d_bits_i0v; // @[dec_decode_ctl.scala 882:59]
wire _T_995 = r_d_bits_i0rd == i0r_rs1; // @[dec_decode_ctl.scala 884:91] wire _T_996 = r_d_bits_i0rd == i0r_rs1; // @[dec_decode_ctl.scala 882:91]
wire i0_rs1_depend_i0_r = _T_994 & _T_995; // @[dec_decode_ctl.scala 884:74] wire i0_rs1_depend_i0_r = _T_995 & _T_996; // @[dec_decode_ctl.scala 882:74]
wire [1:0] _T_1007 = i0_rs1_depend_i0_r ? 2'h2 : 2'h0; // @[dec_decode_ctl.scala 890:63] wire [1:0] _T_1008 = i0_rs1_depend_i0_r ? 2'h2 : 2'h0; // @[dec_decode_ctl.scala 888:63]
wire [1:0] i0_rs1_depth_d = i0_rs1_depend_i0_x ? 2'h1 : _T_1007; // @[dec_decode_ctl.scala 890:24] wire [1:0] i0_rs1_depth_d = i0_rs1_depend_i0_x ? 2'h1 : _T_1008; // @[dec_decode_ctl.scala 888:24]
wire _T_1020 = _T_1018 & i0_rs1_depth_d[0]; // @[dec_decode_ctl.scala 903:58] wire _T_1021 = _T_1019 & i0_rs1_depth_d[0]; // @[dec_decode_ctl.scala 901:58]
reg i0_x_c_load; // @[Reg.scala 27:20] reg i0_x_c_load; // @[Reg.scala 27:20]
reg i0_r_c_load; // @[Reg.scala 27:20] reg i0_r_c_load; // @[Reg.scala 27:20]
wire _T_1003_load = i0_rs1_depend_i0_r & i0_r_c_load; // @[dec_decode_ctl.scala 889:61] wire _T_1004_load = i0_rs1_depend_i0_r & i0_r_c_load; // @[dec_decode_ctl.scala 887:61]
wire i0_rs1_class_d_load = i0_rs1_depend_i0_x ? i0_x_c_load : _T_1003_load; // @[dec_decode_ctl.scala 889:24] wire i0_rs1_class_d_load = i0_rs1_depend_i0_x ? i0_x_c_load : _T_1004_load; // @[dec_decode_ctl.scala 887:24]
wire load_ldst_bypass_d = _T_1020 & i0_rs1_class_d_load; // @[dec_decode_ctl.scala 903:78] wire load_ldst_bypass_d = _T_1021 & i0_rs1_class_d_load; // @[dec_decode_ctl.scala 901:78]
wire _T_996 = io_decode_exu_dec_i0_rs2_en_d & x_d_bits_i0v; // @[dec_decode_ctl.scala 886:59] wire _T_997 = io_decode_exu_dec_i0_rs2_en_d & x_d_bits_i0v; // @[dec_decode_ctl.scala 884:59]
wire _T_997 = x_d_bits_i0rd == i0r_rs2; // @[dec_decode_ctl.scala 886:91] wire _T_998 = x_d_bits_i0rd == i0r_rs2; // @[dec_decode_ctl.scala 884:91]
wire i0_rs2_depend_i0_x = _T_996 & _T_997; // @[dec_decode_ctl.scala 886:74] wire i0_rs2_depend_i0_x = _T_997 & _T_998; // @[dec_decode_ctl.scala 884:74]
wire _T_998 = io_decode_exu_dec_i0_rs2_en_d & r_d_bits_i0v; // @[dec_decode_ctl.scala 887:59] wire _T_999 = io_decode_exu_dec_i0_rs2_en_d & r_d_bits_i0v; // @[dec_decode_ctl.scala 885:59]
wire _T_999 = r_d_bits_i0rd == i0r_rs2; // @[dec_decode_ctl.scala 887:91] wire _T_1000 = r_d_bits_i0rd == i0r_rs2; // @[dec_decode_ctl.scala 885:91]
wire i0_rs2_depend_i0_r = _T_998 & _T_999; // @[dec_decode_ctl.scala 887:74] wire i0_rs2_depend_i0_r = _T_999 & _T_1000; // @[dec_decode_ctl.scala 885:74]
wire [1:0] _T_1016 = i0_rs2_depend_i0_r ? 2'h2 : 2'h0; // @[dec_decode_ctl.scala 892:63] wire [1:0] _T_1017 = i0_rs2_depend_i0_r ? 2'h2 : 2'h0; // @[dec_decode_ctl.scala 890:63]
wire [1:0] i0_rs2_depth_d = i0_rs2_depend_i0_x ? 2'h1 : _T_1016; // @[dec_decode_ctl.scala 892:24] wire [1:0] i0_rs2_depth_d = i0_rs2_depend_i0_x ? 2'h1 : _T_1017; // @[dec_decode_ctl.scala 890:24]
wire _T_1023 = i0_dp_store & i0_rs2_depth_d[0]; // @[dec_decode_ctl.scala 904:43] wire _T_1024 = i0_dp_store & i0_rs2_depth_d[0]; // @[dec_decode_ctl.scala 902:43]
wire _T_1012_load = i0_rs2_depend_i0_r & i0_r_c_load; // @[dec_decode_ctl.scala 891:61] wire _T_1013_load = i0_rs2_depend_i0_r & i0_r_c_load; // @[dec_decode_ctl.scala 889:61]
wire i0_rs2_class_d_load = i0_rs2_depend_i0_x ? i0_x_c_load : _T_1012_load; // @[dec_decode_ctl.scala 891:24] wire i0_rs2_class_d_load = i0_rs2_depend_i0_x ? i0_x_c_load : _T_1013_load; // @[dec_decode_ctl.scala 889:24]
wire store_data_bypass_d = _T_1023 & i0_rs2_class_d_load; // @[dec_decode_ctl.scala 904:63] wire store_data_bypass_d = _T_1024 & i0_rs2_class_d_load; // @[dec_decode_ctl.scala 902:63]
wire _T_435 = i0_dp_csr_clr | i0_dp_csr_set; // @[dec_decode_ctl.scala 527:42] wire _T_435 = i0_dp_csr_clr | i0_dp_csr_set; // @[dec_decode_ctl.scala 527:42]
wire _T_436 = _T_435 | i0_csr_write; // @[dec_decode_ctl.scala 527:58] wire _T_436 = _T_435 | i0_csr_write; // @[dec_decode_ctl.scala 527:58]
wire [11:0] _T_440 = io_dec_csr_any_unq_d ? 12'hfff : 12'h0; // @[Bitwise.scala 72:12] wire [11:0] _T_440 = io_dec_csr_any_unq_d ? 12'hfff : 12'h0; // @[Bitwise.scala 72:12]
@ -2653,7 +2667,7 @@ module dec_decode_ctl(
reg csr_set_x; // @[dec_decode_ctl.scala 543:51] reg csr_set_x; // @[dec_decode_ctl.scala 543:51]
reg csr_write_x; // @[dec_decode_ctl.scala 544:53] reg csr_write_x; // @[dec_decode_ctl.scala 544:53]
reg csr_imm_x; // @[dec_decode_ctl.scala 545:51] reg csr_imm_x; // @[dec_decode_ctl.scala 545:51]
wire i0_x_data_en = i0_pipe_en[3] | io_clk_override; // @[dec_decode_ctl.scala 771:50] wire i0_x_data_en = i0_pipe_en[3] | io_clk_override; // @[dec_decode_ctl.scala 769:50]
wire _T_459 = i0_x_data_en & any_csr_d; // @[dec_decode_ctl.scala 548:48] wire _T_459 = i0_x_data_en & any_csr_d; // @[dec_decode_ctl.scala 548:48]
reg [4:0] csrimm_x; // @[Reg.scala 27:20] reg [4:0] csrimm_x; // @[Reg.scala 27:20]
reg [31:0] csr_rddata_x; // @[Reg.scala 27:20] reg [31:0] csr_rddata_x; // @[Reg.scala 27:20]
@ -2681,9 +2695,9 @@ module dec_decode_ctl(
wire csr_data_wen = _T_527 | pause_stall; // @[dec_decode_ctl.scala 569:99] wire csr_data_wen = _T_527 | pause_stall; // @[dec_decode_ctl.scala 569:99]
reg r_d_bits_csrwonly; // @[Reg.scala 27:20] reg r_d_bits_csrwonly; // @[Reg.scala 27:20]
wire _T_529 = r_d_bits_csrwonly & r_d_valid; // @[dec_decode_ctl.scala 576:50] wire _T_529 = r_d_bits_csrwonly & r_d_valid; // @[dec_decode_ctl.scala 576:50]
wire _T_881 = r_d_bits_i0v & r_d_bits_i0load; // @[dec_decode_ctl.scala 824:42] wire _T_882 = r_d_bits_i0v & r_d_bits_i0load; // @[dec_decode_ctl.scala 822:42]
reg [31:0] i0_result_r_raw; // @[Reg.scala 27:20] reg [31:0] i0_result_r_raw; // @[Reg.scala 27:20]
wire [31:0] i0_result_corr_r = _T_881 ? io_lsu_result_corr_r : i0_result_r_raw; // @[dec_decode_ctl.scala 824:27] wire [31:0] i0_result_corr_r = _T_882 ? io_lsu_result_corr_r : i0_result_r_raw; // @[dec_decode_ctl.scala 822:27]
reg x_d_bits_csrwonly; // @[Reg.scala 27:20] reg x_d_bits_csrwonly; // @[Reg.scala 27:20]
wire _T_532 = x_d_bits_csrwonly | r_d_bits_csrwonly; // @[dec_decode_ctl.scala 578:43] wire _T_532 = x_d_bits_csrwonly | r_d_bits_csrwonly; // @[dec_decode_ctl.scala 578:43]
reg wbd_bits_csrwonly; // @[Reg.scala 27:20] reg wbd_bits_csrwonly; // @[Reg.scala 27:20]
@ -2694,59 +2708,59 @@ module dec_decode_ctl(
wire _T_537 = _T_536 | debug_fence_i; // @[dec_decode_ctl.scala 585:57] wire _T_537 = _T_536 | debug_fence_i; // @[dec_decode_ctl.scala 585:57]
wire _T_538 = _T_537 | debug_fence_raw; // @[dec_decode_ctl.scala 585:73] wire _T_538 = _T_537 | debug_fence_raw; // @[dec_decode_ctl.scala 585:73]
wire i0_presync = _T_538 | io_dec_tlu_pipelining_disable; // @[dec_decode_ctl.scala 585:91] wire i0_presync = _T_538 | io_dec_tlu_pipelining_disable; // @[dec_decode_ctl.scala 585:91]
wire [31:0] _T_562 = {16'h0,io_dec_aln_ifu_i0_cinst}; // @[Cat.scala 29:58] wire [31:0] _T_563 = {16'h0,io_dec_aln_ifu_i0_cinst}; // @[Cat.scala 29:58]
wire _T_564 = ~illegal_lockout; // @[dec_decode_ctl.scala 597:44] wire _T_565 = ~illegal_lockout; // @[dec_decode_ctl.scala 595:44]
wire illegal_inst_en = shift_illegal & _T_564; // @[dec_decode_ctl.scala 597:42] wire illegal_inst_en = shift_illegal & _T_565; // @[dec_decode_ctl.scala 595:42]
reg [31:0] _T_565; // @[Reg.scala 27:20] reg [31:0] _T_566; // @[Reg.scala 27:20]
wire i0_div_prior_div_stall = i0_dp_div & io_dec_div_active; // @[dec_decode_ctl.scala 600:42] wire i0_div_prior_div_stall = i0_dp_div & io_dec_div_active; // @[dec_decode_ctl.scala 598:42]
wire _T_569 = i0_dp_csr_read & prior_csr_write; // @[dec_decode_ctl.scala 602:40] wire _T_570 = i0_dp_csr_read & prior_csr_write; // @[dec_decode_ctl.scala 600:40]
wire _T_570 = _T_569 | io_decode_exu_dec_extint_stall; // @[dec_decode_ctl.scala 602:59] wire _T_571 = _T_570 | io_decode_exu_dec_extint_stall; // @[dec_decode_ctl.scala 600:59]
wire _T_571 = _T_570 | pause_stall; // @[dec_decode_ctl.scala 602:92] wire _T_572 = _T_571 | pause_stall; // @[dec_decode_ctl.scala 600:92]
wire _T_572 = _T_571 | leak1_i0_stall; // @[dec_decode_ctl.scala 602:106] wire _T_573 = _T_572 | leak1_i0_stall; // @[dec_decode_ctl.scala 600:106]
wire _T_573 = _T_572 | io_dec_tlu_debug_stall; // @[dec_decode_ctl.scala 603:20] wire _T_574 = _T_573 | io_dec_tlu_debug_stall; // @[dec_decode_ctl.scala 601:20]
wire _T_574 = _T_573 | postsync_stall; // @[dec_decode_ctl.scala 603:45] wire _T_575 = _T_574 | postsync_stall; // @[dec_decode_ctl.scala 601:45]
wire prior_inflight = x_d_valid | r_d_valid; // @[dec_decode_ctl.scala 625:41] wire prior_inflight = x_d_valid | r_d_valid; // @[dec_decode_ctl.scala 623:41]
wire prior_inflight_eff = i0_dp_div ? x_d_valid : prior_inflight; // @[dec_decode_ctl.scala 626:31] wire prior_inflight_eff = i0_dp_div ? x_d_valid : prior_inflight; // @[dec_decode_ctl.scala 624:31]
wire presync_stall = i0_presync & prior_inflight_eff; // @[dec_decode_ctl.scala 628:37] wire presync_stall = i0_presync & prior_inflight_eff; // @[dec_decode_ctl.scala 626:37]
wire _T_575 = _T_574 | presync_stall; // @[dec_decode_ctl.scala 603:62] wire _T_576 = _T_575 | presync_stall; // @[dec_decode_ctl.scala 601:62]
wire _T_576 = i0_dp_fence | debug_fence; // @[dec_decode_ctl.scala 604:19] wire _T_577 = i0_dp_fence | debug_fence; // @[dec_decode_ctl.scala 602:19]
wire _T_577 = ~lsu_idle; // @[dec_decode_ctl.scala 604:36] wire _T_578 = ~lsu_idle; // @[dec_decode_ctl.scala 602:36]
wire _T_578 = _T_576 & _T_577; // @[dec_decode_ctl.scala 604:34] wire _T_579 = _T_577 & _T_578; // @[dec_decode_ctl.scala 602:34]
wire _T_579 = _T_575 | _T_578; // @[dec_decode_ctl.scala 603:79] wire _T_580 = _T_576 | _T_579; // @[dec_decode_ctl.scala 601:79]
wire _T_580 = _T_579 | i0_nonblock_load_stall; // @[dec_decode_ctl.scala 604:47] wire _T_581 = _T_580 | i0_nonblock_load_stall; // @[dec_decode_ctl.scala 602:47]
wire _T_939 = io_decode_exu_dec_i0_rs1_en_d & io_dec_div_active; // @[dec_decode_ctl.scala 852:60] wire _T_940 = io_decode_exu_dec_i0_rs1_en_d & io_dec_div_active; // @[dec_decode_ctl.scala 850:60]
wire _T_940 = io_div_waddr_wb == i0r_rs1; // @[dec_decode_ctl.scala 852:99] wire _T_941 = io_div_waddr_wb == i0r_rs1; // @[dec_decode_ctl.scala 850:99]
wire _T_941 = _T_939 & _T_940; // @[dec_decode_ctl.scala 852:80] wire _T_942 = _T_940 & _T_941; // @[dec_decode_ctl.scala 850:80]
wire _T_942 = io_decode_exu_dec_i0_rs2_en_d & io_dec_div_active; // @[dec_decode_ctl.scala 853:36] wire _T_943 = io_decode_exu_dec_i0_rs2_en_d & io_dec_div_active; // @[dec_decode_ctl.scala 851:36]
wire _T_943 = io_div_waddr_wb == i0r_rs2; // @[dec_decode_ctl.scala 853:75] wire _T_944 = io_div_waddr_wb == i0r_rs2; // @[dec_decode_ctl.scala 851:75]
wire _T_944 = _T_942 & _T_943; // @[dec_decode_ctl.scala 853:56] wire _T_945 = _T_943 & _T_944; // @[dec_decode_ctl.scala 851:56]
wire i0_nonblock_div_stall = _T_941 | _T_944; // @[dec_decode_ctl.scala 852:113] wire i0_nonblock_div_stall = _T_942 | _T_945; // @[dec_decode_ctl.scala 850:113]
wire _T_582 = _T_580 | i0_nonblock_div_stall; // @[dec_decode_ctl.scala 605:21] wire _T_583 = _T_581 | i0_nonblock_div_stall; // @[dec_decode_ctl.scala 603:21]
wire i0_block_raw_d = _T_582 | i0_div_prior_div_stall; // @[dec_decode_ctl.scala 605:45] wire i0_block_raw_d = _T_583 | i0_div_prior_div_stall; // @[dec_decode_ctl.scala 603:45]
wire _T_583 = io_lsu_store_stall_any | io_dctl_dma_dma_dccm_stall_any; // @[dec_decode_ctl.scala 607:65] wire _T_584 = io_lsu_store_stall_any | io_dctl_dma_dma_dccm_stall_any; // @[dec_decode_ctl.scala 605:65]
wire i0_store_stall_d = i0_dp_store & _T_583; // @[dec_decode_ctl.scala 607:39] wire i0_store_stall_d = i0_dp_store & _T_584; // @[dec_decode_ctl.scala 605:39]
wire _T_584 = io_lsu_load_stall_any | io_dctl_dma_dma_dccm_stall_any; // @[dec_decode_ctl.scala 608:63] wire _T_585 = io_lsu_load_stall_any | io_dctl_dma_dma_dccm_stall_any; // @[dec_decode_ctl.scala 606:63]
wire i0_load_stall_d = i0_dp_load & _T_584; // @[dec_decode_ctl.scala 608:38] wire i0_load_stall_d = i0_dp_load & _T_585; // @[dec_decode_ctl.scala 606:38]
wire _T_585 = i0_block_raw_d | i0_store_stall_d; // @[dec_decode_ctl.scala 609:38] wire _T_586 = i0_block_raw_d | i0_store_stall_d; // @[dec_decode_ctl.scala 607:38]
wire i0_block_d = _T_585 | i0_load_stall_d; // @[dec_decode_ctl.scala 609:57] wire i0_block_d = _T_586 | i0_load_stall_d; // @[dec_decode_ctl.scala 607:57]
wire _T_586 = ~i0_block_d; // @[dec_decode_ctl.scala 613:46] wire _T_587 = ~i0_block_d; // @[dec_decode_ctl.scala 611:46]
wire _T_587 = io_dec_ib0_valid_d & _T_586; // @[dec_decode_ctl.scala 613:44] wire _T_588 = io_dec_ib0_valid_d & _T_587; // @[dec_decode_ctl.scala 611:44]
wire _T_589 = _T_587 & _T_367; // @[dec_decode_ctl.scala 613:61] wire _T_590 = _T_588 & _T_367; // @[dec_decode_ctl.scala 611:61]
wire _T_592 = ~i0_block_raw_d; // @[dec_decode_ctl.scala 614:46] wire _T_593 = ~i0_block_raw_d; // @[dec_decode_ctl.scala 612:46]
wire _T_593 = io_dec_ib0_valid_d & _T_592; // @[dec_decode_ctl.scala 614:44] wire _T_594 = io_dec_ib0_valid_d & _T_593; // @[dec_decode_ctl.scala 612:44]
wire _T_595 = _T_593 & _T_367; // @[dec_decode_ctl.scala 614:61] wire _T_596 = _T_594 & _T_367; // @[dec_decode_ctl.scala 612:61]
wire i0_exudecode_d = _T_595 & _T_567; // @[dec_decode_ctl.scala 614:89] wire i0_exudecode_d = _T_596 & _T_568; // @[dec_decode_ctl.scala 612:89]
wire i0_exulegal_decode_d = i0_exudecode_d & i0_legal; // @[dec_decode_ctl.scala 615:46] wire i0_exulegal_decode_d = i0_exudecode_d & i0_legal; // @[dec_decode_ctl.scala 613:46]
wire _T_597 = ~io_dec_i0_decode_d; // @[dec_decode_ctl.scala 619:51] wire _T_598 = ~io_dec_i0_decode_d; // @[dec_decode_ctl.scala 617:51]
wire _T_610 = i0_dp_condbr | i0_dp_jal; // @[dec_decode_ctl.scala 633:53] wire _T_611 = i0_dp_condbr | i0_dp_jal; // @[dec_decode_ctl.scala 631:53]
wire d_t_icaf = i0_icaf_d & i0_legal_decode_d; // @[dec_decode_ctl.scala 643:40] wire d_t_icaf = i0_icaf_d & i0_legal_decode_d; // @[dec_decode_ctl.scala 641:40]
wire d_t_icaf_second = io_dec_i0_icaf_second_d & i0_legal_decode_d; // @[dec_decode_ctl.scala 644:58] wire d_t_icaf_second = io_dec_i0_icaf_second_d & i0_legal_decode_d; // @[dec_decode_ctl.scala 642:58]
wire _T_619 = i0_dp_fence_i | debug_fence_i; // @[dec_decode_ctl.scala 647:44] wire _T_620 = i0_dp_fence_i | debug_fence_i; // @[dec_decode_ctl.scala 645:44]
wire d_t_fence_i = _T_619 & i0_legal_decode_d; // @[dec_decode_ctl.scala 647:61] wire d_t_fence_i = _T_620 & i0_legal_decode_d; // @[dec_decode_ctl.scala 645:61]
wire [3:0] _T_624 = {io_dec_i0_decode_d,io_dec_i0_decode_d,io_dec_i0_decode_d,io_dec_i0_decode_d}; // @[Cat.scala 29:58] wire [3:0] _T_625 = {io_dec_i0_decode_d,io_dec_i0_decode_d,io_dec_i0_decode_d,io_dec_i0_decode_d}; // @[Cat.scala 29:58]
wire [3:0] d_t_i0trigger = io_dec_i0_trigger_match_d & _T_624; // @[dec_decode_ctl.scala 654:56] wire [3:0] d_t_i0trigger = io_dec_i0_trigger_match_d & _T_625; // @[dec_decode_ctl.scala 652:56]
wire _T_818 = |i0_pipe_en[3:2]; // @[dec_decode_ctl.scala 768:49] wire _T_819 = |i0_pipe_en[3:2]; // @[dec_decode_ctl.scala 766:49]
wire i0_x_ctl_en = _T_818 | io_clk_override; // @[dec_decode_ctl.scala 768:53] wire i0_x_ctl_en = _T_819 | io_clk_override; // @[dec_decode_ctl.scala 766:53]
reg x_t_legal; // @[Reg.scala 27:20] reg x_t_legal; // @[Reg.scala 27:20]
reg x_t_icaf; // @[Reg.scala 27:20] reg x_t_icaf; // @[Reg.scala 27:20]
reg x_t_icaf_second; // @[Reg.scala 27:20] reg x_t_icaf_second; // @[Reg.scala 27:20]
@ -2755,9 +2769,9 @@ module dec_decode_ctl(
reg [3:0] x_t_i0trigger; // @[Reg.scala 27:20] reg [3:0] x_t_i0trigger; // @[Reg.scala 27:20]
reg [3:0] x_t_pmu_i0_itype; // @[Reg.scala 27:20] reg [3:0] x_t_pmu_i0_itype; // @[Reg.scala 27:20]
reg x_t_pmu_i0_br_unpred; // @[Reg.scala 27:20] reg x_t_pmu_i0_br_unpred; // @[Reg.scala 27:20]
wire [3:0] _T_632 = {io_dec_tlu_flush_lower_wb,io_dec_tlu_flush_lower_wb,io_dec_tlu_flush_lower_wb,io_dec_tlu_flush_lower_wb}; // @[Cat.scala 29:58] wire [3:0] _T_633 = {io_dec_tlu_flush_lower_wb,io_dec_tlu_flush_lower_wb,io_dec_tlu_flush_lower_wb,io_dec_tlu_flush_lower_wb}; // @[Cat.scala 29:58]
wire [3:0] _T_633 = ~_T_632; // @[dec_decode_ctl.scala 660:39] wire [3:0] _T_634 = ~_T_633; // @[dec_decode_ctl.scala 658:39]
wire [3:0] x_t_in_i0trigger = x_t_i0trigger & _T_633; // @[dec_decode_ctl.scala 660:37] wire [3:0] x_t_in_i0trigger = x_t_i0trigger & _T_634; // @[dec_decode_ctl.scala 658:37]
reg r_t_legal; // @[Reg.scala 27:20] reg r_t_legal; // @[Reg.scala 27:20]
reg r_t_icaf; // @[Reg.scala 27:20] reg r_t_icaf; // @[Reg.scala 27:20]
reg r_t_icaf_second; // @[Reg.scala 27:20] reg r_t_icaf_second; // @[Reg.scala 27:20]
@ -2767,146 +2781,146 @@ module dec_decode_ctl(
reg [3:0] r_t_pmu_i0_itype; // @[Reg.scala 27:20] reg [3:0] r_t_pmu_i0_itype; // @[Reg.scala 27:20]
reg r_t_pmu_i0_br_unpred; // @[Reg.scala 27:20] reg r_t_pmu_i0_br_unpred; // @[Reg.scala 27:20]
reg r_d_bits_i0store; // @[Reg.scala 27:20] reg r_d_bits_i0store; // @[Reg.scala 27:20]
wire _T_638 = r_d_bits_i0load | r_d_bits_i0store; // @[dec_decode_ctl.scala 666:61] wire _T_639 = r_d_bits_i0load | r_d_bits_i0store; // @[dec_decode_ctl.scala 664:61]
wire [3:0] _T_642 = {_T_638,_T_638,_T_638,_T_638}; // @[Cat.scala 29:58] wire [3:0] _T_643 = {_T_639,_T_639,_T_639,_T_639}; // @[Cat.scala 29:58]
wire [3:0] _T_643 = _T_642 & lsu_trigger_match_r; // @[dec_decode_ctl.scala 666:82] wire [3:0] _T_644 = _T_643 & lsu_trigger_match_r; // @[dec_decode_ctl.scala 664:82]
wire [3:0] _T_644 = _T_643 | r_t_i0trigger; // @[dec_decode_ctl.scala 666:105] wire [3:0] _T_645 = _T_644 | r_t_i0trigger; // @[dec_decode_ctl.scala 664:105]
wire _T_657 = i0r_rs1 != 5'h0; // @[dec_decode_ctl.scala 682:60] wire _T_658 = i0r_rs1 != 5'h0; // @[dec_decode_ctl.scala 680:60]
wire _T_659 = i0r_rs2 != 5'h0; // @[dec_decode_ctl.scala 683:60] wire _T_660 = i0r_rs2 != 5'h0; // @[dec_decode_ctl.scala 681:60]
wire _T_661 = i0r_rd != 5'h0; // @[dec_decode_ctl.scala 684:48] wire _T_662 = i0r_rd != 5'h0; // @[dec_decode_ctl.scala 682:48]
wire i0_rd_en_d = i0_dp_rd & _T_661; // @[dec_decode_ctl.scala 684:37] wire i0_rd_en_d = i0_dp_rd & _T_662; // @[dec_decode_ctl.scala 682:37]
wire i0_jalimm20 = i0_dp_jal & i0_dp_imm20; // @[dec_decode_ctl.scala 688:38] wire i0_jalimm20 = i0_dp_jal & i0_dp_imm20; // @[dec_decode_ctl.scala 686:38]
wire _T_662 = ~i0_dp_jal; // @[dec_decode_ctl.scala 689:27] wire _T_663 = ~i0_dp_jal; // @[dec_decode_ctl.scala 687:27]
wire i0_uiimm20 = _T_662 & i0_dp_imm20; // @[dec_decode_ctl.scala 689:38] wire i0_uiimm20 = _T_663 & i0_dp_imm20; // @[dec_decode_ctl.scala 687:38]
wire [9:0] _T_673 = {io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31]}; // @[Cat.scala 29:58] wire [9:0] _T_674 = {io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31]}; // @[Cat.scala 29:58]
wire [18:0] _T_682 = {_T_673,io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31]}; // @[Cat.scala 29:58] wire [18:0] _T_683 = {_T_674,io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31]}; // @[Cat.scala 29:58]
wire [31:0] _T_685 = {_T_682,io_dec_i0_instr_d[31],io_dec_i0_instr_d[31:20]}; // @[Cat.scala 29:58] wire [31:0] _T_686 = {_T_683,io_dec_i0_instr_d[31],io_dec_i0_instr_d[31:20]}; // @[Cat.scala 29:58]
wire [31:0] _T_714 = {27'h0,i0r_rs2}; // @[Cat.scala 29:58] wire [31:0] _T_715 = {27'h0,i0r_rs2}; // @[Cat.scala 29:58]
wire [31:0] _T_734 = {_T_673,io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[19:12],io_dec_i0_instr_d[20],io_dec_i0_instr_d[30:21],1'h0}; // @[Cat.scala 29:58] wire [31:0] _T_735 = {_T_674,io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[19:12],io_dec_i0_instr_d[20],io_dec_i0_instr_d[30:21],1'h0}; // @[Cat.scala 29:58]
wire [31:0] _T_748 = {io_dec_i0_instr_d[31:12],12'h0}; // @[Cat.scala 29:58] wire [31:0] _T_749 = {io_dec_i0_instr_d[31:12],12'h0}; // @[Cat.scala 29:58]
wire _T_749 = i0_csr_write_only_d & i0_dp_csr_imm; // @[dec_decode_ctl.scala 700:26] wire _T_750 = i0_csr_write_only_d & i0_dp_csr_imm; // @[dec_decode_ctl.scala 698:26]
wire [31:0] _T_779 = {27'h0,i0r_rs1}; // @[Cat.scala 29:58] wire [31:0] _T_780 = {27'h0,i0r_rs1}; // @[Cat.scala 29:58]
wire [31:0] _T_780 = i0_dp_imm12 ? _T_685 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_781 = i0_dp_imm12 ? _T_686 : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_781 = i0_dp_shimm5 ? _T_714 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_782 = i0_dp_shimm5 ? _T_715 : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_782 = i0_jalimm20 ? _T_734 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_783 = i0_jalimm20 ? _T_735 : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_783 = i0_uiimm20 ? _T_748 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_784 = i0_uiimm20 ? _T_749 : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_784 = _T_749 ? _T_779 : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_785 = _T_750 ? _T_780 : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_785 = _T_780 | _T_781; // @[Mux.scala 27:72] wire [31:0] _T_786 = _T_781 | _T_782; // @[Mux.scala 27:72]
wire [31:0] _T_786 = _T_785 | _T_782; // @[Mux.scala 27:72]
wire [31:0] _T_787 = _T_786 | _T_783; // @[Mux.scala 27:72] wire [31:0] _T_787 = _T_786 | _T_783; // @[Mux.scala 27:72]
wire i0_d_c_mul = i0_dp_mul & i0_legal_decode_d; // @[dec_decode_ctl.scala 760:44] wire [31:0] _T_788 = _T_787 | _T_784; // @[Mux.scala 27:72]
wire i0_d_c_load = i0_dp_load & i0_legal_decode_d; // @[dec_decode_ctl.scala 761:44] wire i0_d_c_mul = i0_dp_mul & i0_legal_decode_d; // @[dec_decode_ctl.scala 758:44]
wire i0_d_c_alu = i0_dp_alu & i0_legal_decode_d; // @[dec_decode_ctl.scala 762:44] wire i0_d_c_load = i0_dp_load & i0_legal_decode_d; // @[dec_decode_ctl.scala 759:44]
wire i0_d_c_alu = i0_dp_alu & i0_legal_decode_d; // @[dec_decode_ctl.scala 760:44]
reg i0_x_c_mul; // @[Reg.scala 27:20] reg i0_x_c_mul; // @[Reg.scala 27:20]
reg i0_x_c_alu; // @[Reg.scala 27:20] reg i0_x_c_alu; // @[Reg.scala 27:20]
reg i0_r_c_mul; // @[Reg.scala 27:20] reg i0_r_c_mul; // @[Reg.scala 27:20]
reg i0_r_c_alu; // @[Reg.scala 27:20] reg i0_r_c_alu; // @[Reg.scala 27:20]
wire _T_824 = |i0_pipe_en[1:0]; // @[dec_decode_ctl.scala 770:49] wire _T_825 = |i0_pipe_en[1:0]; // @[dec_decode_ctl.scala 768:49]
wire i0_wb_ctl_en = _T_824 | io_clk_override; // @[dec_decode_ctl.scala 770:53] wire i0_wb_ctl_en = _T_825 | io_clk_override; // @[dec_decode_ctl.scala 768:53]
wire i0_r_data_en = i0_pipe_en[2] | io_clk_override; // @[dec_decode_ctl.scala 772:50] wire i0_r_data_en = i0_pipe_en[2] | io_clk_override; // @[dec_decode_ctl.scala 770:50]
wire i0_wb_data_en = i0_pipe_en[1] | io_clk_override; // @[dec_decode_ctl.scala 773:50] wire i0_wb_data_en = i0_pipe_en[1] | io_clk_override; // @[dec_decode_ctl.scala 771:50]
wire d_d_bits_i0v = i0_rd_en_d & i0_legal_decode_d; // @[dec_decode_ctl.scala 779:50] wire d_d_bits_i0v = i0_rd_en_d & i0_legal_decode_d; // @[dec_decode_ctl.scala 777:50]
wire d_d_bits_i0store = i0_dp_store & i0_legal_decode_d; // @[dec_decode_ctl.scala 783:50] wire d_d_bits_i0store = i0_dp_store & i0_legal_decode_d; // @[dec_decode_ctl.scala 781:50]
wire d_d_bits_i0div = i0_dp_div & i0_legal_decode_d; // @[dec_decode_ctl.scala 784:50] wire d_d_bits_i0div = i0_dp_div & i0_legal_decode_d; // @[dec_decode_ctl.scala 782:50]
wire d_d_bits_csrwen = io_dec_csr_wen_unq_d & i0_legal_decode_d; // @[dec_decode_ctl.scala 786:61] wire d_d_bits_csrwen = io_dec_csr_wen_unq_d & i0_legal_decode_d; // @[dec_decode_ctl.scala 784:61]
wire d_d_bits_csrwonly = i0_csr_write_only_d & io_dec_i0_decode_d; // @[dec_decode_ctl.scala 787:58] wire d_d_bits_csrwonly = i0_csr_write_only_d & io_dec_i0_decode_d; // @[dec_decode_ctl.scala 785:58]
reg x_d_bits_i0store; // @[Reg.scala 27:20] reg x_d_bits_i0store; // @[Reg.scala 27:20]
reg x_d_bits_csrwen; // @[Reg.scala 27:20] reg x_d_bits_csrwen; // @[Reg.scala 27:20]
reg [11:0] x_d_bits_csrwaddr; // @[Reg.scala 27:20] reg [11:0] x_d_bits_csrwaddr; // @[Reg.scala 27:20]
wire _T_847 = x_d_bits_i0v & _T_857; // @[dec_decode_ctl.scala 793:47] wire _T_848 = x_d_bits_i0v & _T_858; // @[dec_decode_ctl.scala 791:47]
wire x_d_in_bits_i0v = _T_847 & _T_367; // @[dec_decode_ctl.scala 793:76] wire x_d_in_bits_i0v = _T_848 & _T_367; // @[dec_decode_ctl.scala 791:76]
wire _T_851 = x_d_valid & _T_857; // @[dec_decode_ctl.scala 794:33] wire _T_852 = x_d_valid & _T_858; // @[dec_decode_ctl.scala 792:33]
wire x_d_in_valid = _T_851 & _T_367; // @[dec_decode_ctl.scala 794:62] wire x_d_in_valid = _T_852 & _T_367; // @[dec_decode_ctl.scala 792:62]
wire _T_870 = ~r_d_bits_i0div; // @[dec_decode_ctl.scala 809:49] wire _T_871 = ~r_d_bits_i0div; // @[dec_decode_ctl.scala 807:49]
wire _T_871 = i0_wen_r & _T_870; // @[dec_decode_ctl.scala 809:47] wire _T_872 = i0_wen_r & _T_871; // @[dec_decode_ctl.scala 807:47]
wire _T_872 = ~i0_load_kill_wen_r; // @[dec_decode_ctl.scala 809:70] wire _T_873 = ~i0_load_kill_wen_r; // @[dec_decode_ctl.scala 807:70]
wire _T_874 = x_d_bits_i0v | x_d_bits_csrwen; // @[dec_decode_ctl.scala 813:74] wire _T_875 = x_d_bits_i0v | x_d_bits_csrwen; // @[dec_decode_ctl.scala 811:74]
wire _T_875 = _T_874 | debug_valid_x; // @[dec_decode_ctl.scala 813:92] wire _T_876 = _T_875 | debug_valid_x; // @[dec_decode_ctl.scala 811:92]
wire _T_876 = i0_r_data_en & _T_875; // @[dec_decode_ctl.scala 813:58] wire _T_877 = i0_r_data_en & _T_876; // @[dec_decode_ctl.scala 811:58]
wire _T_878 = x_d_bits_i0v & x_d_bits_i0load; // @[dec_decode_ctl.scala 819:47] wire _T_879 = x_d_bits_i0v & x_d_bits_i0load; // @[dec_decode_ctl.scala 817:47]
wire _T_885 = io_decode_exu_i0_ap_predict_nt & _T_662; // @[dec_decode_ctl.scala 825:71] wire _T_886 = io_decode_exu_i0_ap_predict_nt & _T_663; // @[dec_decode_ctl.scala 823:71]
wire [11:0] _T_898 = {10'h0,io_dec_i0_pc4_d,i0_ap_pc2}; // @[Cat.scala 29:58] wire [11:0] _T_899 = {10'h0,io_dec_i0_pc4_d,i0_ap_pc2}; // @[Cat.scala 29:58]
reg [11:0] last_br_immed_x; // @[Reg.scala 27:20] reg [11:0] last_br_immed_x; // @[Reg.scala 27:20]
wire trace_enable = ~io_dec_tlu_trace_disable; // @[dec_decode_ctl.scala 860:22] wire trace_enable = ~io_dec_tlu_trace_disable; // @[dec_decode_ctl.scala 858:22]
reg [4:0] _T_947; // @[Reg.scala 27:20] reg [4:0] _T_948; // @[Reg.scala 27:20]
wire _T_948 = i0_x_data_en & trace_enable; // @[dec_decode_ctl.scala 864:50] wire _T_949 = i0_x_data_en & trace_enable; // @[dec_decode_ctl.scala 862:50]
reg [31:0] i0_inst_x; // @[Reg.scala 27:20] reg [31:0] i0_inst_x; // @[Reg.scala 27:20]
wire _T_950 = i0_r_data_en & trace_enable; // @[dec_decode_ctl.scala 865:50] wire _T_951 = i0_r_data_en & trace_enable; // @[dec_decode_ctl.scala 863:50]
reg [31:0] i0_inst_r; // @[Reg.scala 27:20] reg [31:0] i0_inst_r; // @[Reg.scala 27:20]
wire _T_952 = i0_wb_data_en & trace_enable; // @[dec_decode_ctl.scala 867:51] wire _T_953 = i0_wb_data_en & trace_enable; // @[dec_decode_ctl.scala 865:51]
reg [31:0] i0_inst_wb; // @[Reg.scala 27:20] reg [31:0] i0_inst_wb; // @[Reg.scala 27:20]
reg [30:0] i0_pc_wb; // @[Reg.scala 27:20] reg [30:0] i0_pc_wb; // @[Reg.scala 27:20]
reg [30:0] dec_i0_pc_r; // @[Reg.scala 27:20] reg [30:0] dec_i0_pc_r; // @[Reg.scala 27:20]
wire [31:0] _T_958 = {io_dec_alu_exu_i0_pc_x,1'h0}; // @[Cat.scala 29:58] wire [31:0] _T_959 = {io_dec_alu_exu_i0_pc_x,1'h0}; // @[Cat.scala 29:58]
wire [12:0] _T_959 = {last_br_immed_x,1'h0}; // @[Cat.scala 29:58] wire [12:0] _T_960 = {last_br_immed_x,1'h0}; // @[Cat.scala 29:58]
wire [12:0] _T_962 = _T_958[12:1] + _T_959[12:1]; // @[lib.scala 68:31] wire [12:0] _T_963 = _T_959[12:1] + _T_960[12:1]; // @[lib.scala 68:31]
wire [18:0] _T_965 = _T_958[31:13] + 19'h1; // @[lib.scala 69:27] wire [18:0] _T_966 = _T_959[31:13] + 19'h1; // @[lib.scala 69:27]
wire [18:0] _T_968 = _T_958[31:13] - 19'h1; // @[lib.scala 70:27] wire [18:0] _T_969 = _T_959[31:13] - 19'h1; // @[lib.scala 70:27]
wire _T_971 = ~_T_962[12]; // @[lib.scala 72:28] wire _T_972 = ~_T_963[12]; // @[lib.scala 72:28]
wire _T_972 = _T_959[12] ^ _T_971; // @[lib.scala 72:26] wire _T_973 = _T_960[12] ^ _T_972; // @[lib.scala 72:26]
wire _T_975 = ~_T_959[12]; // @[lib.scala 73:20] wire _T_976 = ~_T_960[12]; // @[lib.scala 73:20]
wire _T_977 = _T_975 & _T_962[12]; // @[lib.scala 73:26] wire _T_978 = _T_976 & _T_963[12]; // @[lib.scala 73:26]
wire _T_981 = _T_959[12] & _T_971; // @[lib.scala 74:26] wire _T_982 = _T_960[12] & _T_972; // @[lib.scala 74:26]
wire [18:0] _T_983 = _T_972 ? _T_958[31:13] : 19'h0; // @[Mux.scala 27:72] wire [18:0] _T_984 = _T_973 ? _T_959[31:13] : 19'h0; // @[Mux.scala 27:72]
wire [18:0] _T_984 = _T_977 ? _T_965 : 19'h0; // @[Mux.scala 27:72] wire [18:0] _T_985 = _T_978 ? _T_966 : 19'h0; // @[Mux.scala 27:72]
wire [18:0] _T_985 = _T_981 ? _T_968 : 19'h0; // @[Mux.scala 27:72] wire [18:0] _T_986 = _T_982 ? _T_969 : 19'h0; // @[Mux.scala 27:72]
wire [18:0] _T_986 = _T_983 | _T_984; // @[Mux.scala 27:72] wire [18:0] _T_987 = _T_984 | _T_985; // @[Mux.scala 27:72]
wire [18:0] _T_987 = _T_986 | _T_985; // @[Mux.scala 27:72] wire [18:0] _T_988 = _T_987 | _T_986; // @[Mux.scala 27:72]
wire [31:0] temp_pred_correct_npc_x = {_T_987,_T_962[11:0],1'h0}; // @[Cat.scala 29:58] wire [31:0] temp_pred_correct_npc_x = {_T_988,_T_963[11:0],1'h0}; // @[Cat.scala 29:58]
wire _T_1003_mul = i0_rs1_depend_i0_r & i0_r_c_mul; // @[dec_decode_ctl.scala 889:61] wire _T_1004_mul = i0_rs1_depend_i0_r & i0_r_c_mul; // @[dec_decode_ctl.scala 887:61]
wire _T_1003_alu = i0_rs1_depend_i0_r & i0_r_c_alu; // @[dec_decode_ctl.scala 889:61] wire _T_1004_alu = i0_rs1_depend_i0_r & i0_r_c_alu; // @[dec_decode_ctl.scala 887:61]
wire i0_rs1_class_d_mul = i0_rs1_depend_i0_x ? i0_x_c_mul : _T_1003_mul; // @[dec_decode_ctl.scala 889:24] wire i0_rs1_class_d_mul = i0_rs1_depend_i0_x ? i0_x_c_mul : _T_1004_mul; // @[dec_decode_ctl.scala 887:24]
wire i0_rs1_class_d_alu = i0_rs1_depend_i0_x ? i0_x_c_alu : _T_1003_alu; // @[dec_decode_ctl.scala 889:24] wire i0_rs1_class_d_alu = i0_rs1_depend_i0_x ? i0_x_c_alu : _T_1004_alu; // @[dec_decode_ctl.scala 887:24]
wire _T_1012_mul = i0_rs2_depend_i0_r & i0_r_c_mul; // @[dec_decode_ctl.scala 891:61] wire _T_1013_mul = i0_rs2_depend_i0_r & i0_r_c_mul; // @[dec_decode_ctl.scala 889:61]
wire _T_1012_alu = i0_rs2_depend_i0_r & i0_r_c_alu; // @[dec_decode_ctl.scala 891:61] wire _T_1013_alu = i0_rs2_depend_i0_r & i0_r_c_alu; // @[dec_decode_ctl.scala 889:61]
wire i0_rs2_class_d_mul = i0_rs2_depend_i0_x ? i0_x_c_mul : _T_1012_mul; // @[dec_decode_ctl.scala 891:24] wire i0_rs2_class_d_mul = i0_rs2_depend_i0_x ? i0_x_c_mul : _T_1013_mul; // @[dec_decode_ctl.scala 889:24]
wire i0_rs2_class_d_alu = i0_rs2_depend_i0_x ? i0_x_c_alu : _T_1012_alu; // @[dec_decode_ctl.scala 891:24] wire i0_rs2_class_d_alu = i0_rs2_depend_i0_x ? i0_x_c_alu : _T_1013_alu; // @[dec_decode_ctl.scala 889:24]
wire _T_1025 = io_decode_exu_dec_i0_rs1_en_d & io_dec_nonblock_load_wen; // @[dec_decode_ctl.scala 909:73] wire _T_1026 = io_decode_exu_dec_i0_rs1_en_d & io_dec_nonblock_load_wen; // @[dec_decode_ctl.scala 907:73]
wire _T_1026 = io_dec_nonblock_load_waddr == i0r_rs1; // @[dec_decode_ctl.scala 909:130] wire _T_1027 = io_dec_nonblock_load_waddr == i0r_rs1; // @[dec_decode_ctl.scala 907:130]
wire i0_rs1_nonblock_load_bypass_en_d = _T_1025 & _T_1026; // @[dec_decode_ctl.scala 909:100] wire i0_rs1_nonblock_load_bypass_en_d = _T_1026 & _T_1027; // @[dec_decode_ctl.scala 907:100]
wire _T_1027 = io_decode_exu_dec_i0_rs2_en_d & io_dec_nonblock_load_wen; // @[dec_decode_ctl.scala 911:73] wire _T_1028 = io_decode_exu_dec_i0_rs2_en_d & io_dec_nonblock_load_wen; // @[dec_decode_ctl.scala 909:73]
wire _T_1028 = io_dec_nonblock_load_waddr == i0r_rs2; // @[dec_decode_ctl.scala 911:130] wire _T_1029 = io_dec_nonblock_load_waddr == i0r_rs2; // @[dec_decode_ctl.scala 909:130]
wire i0_rs2_nonblock_load_bypass_en_d = _T_1027 & _T_1028; // @[dec_decode_ctl.scala 911:100] wire i0_rs2_nonblock_load_bypass_en_d = _T_1028 & _T_1029; // @[dec_decode_ctl.scala 909:100]
wire _T_1030 = i0_rs1_class_d_alu | i0_rs1_class_d_mul; // @[dec_decode_ctl.scala 914:66] wire _T_1031 = i0_rs1_class_d_alu | i0_rs1_class_d_mul; // @[dec_decode_ctl.scala 912:66]
wire _T_1031 = i0_rs1_depth_d[0] & _T_1030; // @[dec_decode_ctl.scala 914:45] wire _T_1032 = i0_rs1_depth_d[0] & _T_1031; // @[dec_decode_ctl.scala 912:45]
wire _T_1033 = i0_rs1_depth_d[0] & i0_rs1_class_d_load; // @[dec_decode_ctl.scala 914:108] wire _T_1034 = i0_rs1_depth_d[0] & i0_rs1_class_d_load; // @[dec_decode_ctl.scala 912:108]
wire _T_1036 = _T_1030 | i0_rs1_class_d_load; // @[dec_decode_ctl.scala 914:196] wire _T_1037 = _T_1031 | i0_rs1_class_d_load; // @[dec_decode_ctl.scala 912:196]
wire _T_1037 = i0_rs1_depth_d[1] & _T_1036; // @[dec_decode_ctl.scala 914:153] wire _T_1038 = i0_rs1_depth_d[1] & _T_1037; // @[dec_decode_ctl.scala 912:153]
wire [2:0] i0_rs1bypass = {_T_1031,_T_1033,_T_1037}; // @[Cat.scala 29:58] wire [2:0] i0_rs1bypass = {_T_1032,_T_1034,_T_1038}; // @[Cat.scala 29:58]
wire _T_1041 = i0_rs2_class_d_alu | i0_rs2_class_d_mul; // @[dec_decode_ctl.scala 916:67] wire _T_1042 = i0_rs2_class_d_alu | i0_rs2_class_d_mul; // @[dec_decode_ctl.scala 914:67]
wire _T_1042 = i0_rs2_depth_d[0] & _T_1041; // @[dec_decode_ctl.scala 916:45] wire _T_1043 = i0_rs2_depth_d[0] & _T_1042; // @[dec_decode_ctl.scala 914:45]
wire _T_1044 = i0_rs2_depth_d[0] & i0_rs2_class_d_load; // @[dec_decode_ctl.scala 916:109] wire _T_1045 = i0_rs2_depth_d[0] & i0_rs2_class_d_load; // @[dec_decode_ctl.scala 914:109]
wire _T_1047 = _T_1041 | i0_rs2_class_d_load; // @[dec_decode_ctl.scala 916:196] wire _T_1048 = _T_1042 | i0_rs2_class_d_load; // @[dec_decode_ctl.scala 914:196]
wire _T_1048 = i0_rs2_depth_d[1] & _T_1047; // @[dec_decode_ctl.scala 916:153] wire _T_1049 = i0_rs2_depth_d[1] & _T_1048; // @[dec_decode_ctl.scala 914:153]
wire [2:0] i0_rs2bypass = {_T_1042,_T_1044,_T_1048}; // @[Cat.scala 29:58] wire [2:0] i0_rs2bypass = {_T_1043,_T_1045,_T_1049}; // @[Cat.scala 29:58]
wire _T_1052 = ~i0_rs1bypass[0]; // @[dec_decode_ctl.scala 918:53] wire _T_1053 = ~i0_rs1bypass[0]; // @[dec_decode_ctl.scala 916:53]
wire _T_1054 = ~i0_rs1bypass[1]; // @[dec_decode_ctl.scala 918:72] wire _T_1055 = ~i0_rs1bypass[1]; // @[dec_decode_ctl.scala 916:72]
wire _T_1055 = _T_1052 & _T_1054; // @[dec_decode_ctl.scala 918:70] wire _T_1056 = _T_1053 & _T_1055; // @[dec_decode_ctl.scala 916:70]
wire _T_1057 = ~i0_rs1bypass[2]; // @[dec_decode_ctl.scala 918:91] wire _T_1058 = ~i0_rs1bypass[2]; // @[dec_decode_ctl.scala 916:91]
wire _T_1058 = _T_1055 & _T_1057; // @[dec_decode_ctl.scala 918:89] wire _T_1059 = _T_1056 & _T_1058; // @[dec_decode_ctl.scala 916:89]
wire _T_1059 = _T_1058 & i0_rs1_nonblock_load_bypass_en_d; // @[dec_decode_ctl.scala 918:108] wire _T_1060 = _T_1059 & i0_rs1_nonblock_load_bypass_en_d; // @[dec_decode_ctl.scala 916:108]
wire [1:0] _T_1063 = {i0_rs1bypass[1],i0_rs1bypass[0]}; // @[Cat.scala 29:58] wire [1:0] _T_1064 = {i0_rs1bypass[1],i0_rs1bypass[0]}; // @[Cat.scala 29:58]
wire [1:0] _T_1064 = {_T_1059,i0_rs1bypass[2]}; // @[Cat.scala 29:58] wire [1:0] _T_1065 = {_T_1060,i0_rs1bypass[2]}; // @[Cat.scala 29:58]
wire _T_1067 = ~i0_rs2bypass[0]; // @[dec_decode_ctl.scala 919:53] wire _T_1068 = ~i0_rs2bypass[0]; // @[dec_decode_ctl.scala 917:53]
wire _T_1069 = ~i0_rs2bypass[1]; // @[dec_decode_ctl.scala 919:72] wire _T_1070 = ~i0_rs2bypass[1]; // @[dec_decode_ctl.scala 917:72]
wire _T_1070 = _T_1067 & _T_1069; // @[dec_decode_ctl.scala 919:70] wire _T_1071 = _T_1068 & _T_1070; // @[dec_decode_ctl.scala 917:70]
wire _T_1072 = ~i0_rs2bypass[2]; // @[dec_decode_ctl.scala 919:91] wire _T_1073 = ~i0_rs2bypass[2]; // @[dec_decode_ctl.scala 917:91]
wire _T_1073 = _T_1070 & _T_1072; // @[dec_decode_ctl.scala 919:89] wire _T_1074 = _T_1071 & _T_1073; // @[dec_decode_ctl.scala 917:89]
wire _T_1074 = _T_1073 & i0_rs2_nonblock_load_bypass_en_d; // @[dec_decode_ctl.scala 919:108] wire _T_1075 = _T_1074 & i0_rs2_nonblock_load_bypass_en_d; // @[dec_decode_ctl.scala 917:108]
wire [1:0] _T_1078 = {i0_rs2bypass[1],i0_rs2bypass[0]}; // @[Cat.scala 29:58] wire [1:0] _T_1079 = {i0_rs2bypass[1],i0_rs2bypass[0]}; // @[Cat.scala 29:58]
wire [1:0] _T_1079 = {_T_1074,i0_rs2bypass[2]}; // @[Cat.scala 29:58] wire [1:0] _T_1080 = {_T_1075,i0_rs2bypass[2]}; // @[Cat.scala 29:58]
wire _T_1081 = i0_dp_raw_load | i0_dp_raw_store; // @[dec_decode_ctl.scala 923:68] wire _T_1082 = i0_dp_raw_load | i0_dp_raw_store; // @[dec_decode_ctl.scala 921:68]
wire _T_1082 = io_dec_ib0_valid_d & _T_1081; // @[dec_decode_ctl.scala 923:50] wire _T_1083 = io_dec_ib0_valid_d & _T_1082; // @[dec_decode_ctl.scala 921:50]
wire _T_1083 = ~io_dctl_dma_dma_dccm_stall_any; // @[dec_decode_ctl.scala 923:89] wire _T_1084 = ~io_dctl_dma_dma_dccm_stall_any; // @[dec_decode_ctl.scala 921:89]
wire _T_1084 = _T_1082 & _T_1083; // @[dec_decode_ctl.scala 923:87] wire _T_1085 = _T_1083 & _T_1084; // @[dec_decode_ctl.scala 921:87]
wire _T_1086 = _T_1084 & _T_592; // @[dec_decode_ctl.scala 923:121] wire _T_1087 = _T_1085 & _T_593; // @[dec_decode_ctl.scala 921:121]
wire _T_1088 = ~io_decode_exu_dec_extint_stall; // @[dec_decode_ctl.scala 925:6] wire _T_1089 = ~io_decode_exu_dec_extint_stall; // @[dec_decode_ctl.scala 923:6]
wire _T_1089 = _T_1088 & i0_dp_lsu; // @[dec_decode_ctl.scala 925:38] wire _T_1090 = _T_1089 & i0_dp_lsu; // @[dec_decode_ctl.scala 923:38]
wire _T_1090 = _T_1089 & i0_dp_load; // @[dec_decode_ctl.scala 925:50] wire _T_1091 = _T_1090 & i0_dp_load; // @[dec_decode_ctl.scala 923:50]
wire _T_1095 = _T_1089 & i0_dp_store; // @[dec_decode_ctl.scala 926:50] wire _T_1096 = _T_1090 & i0_dp_store; // @[dec_decode_ctl.scala 924:50]
wire [11:0] _T_1099 = {io_dec_i0_instr_d[31:25],i0r_rd}; // @[Cat.scala 29:58] wire [11:0] _T_1100 = {io_dec_i0_instr_d[31:25],i0r_rd}; // @[Cat.scala 29:58]
wire [11:0] _T_1100 = _T_1090 ? io_dec_i0_instr_d[31:20] : 12'h0; // @[Mux.scala 27:72] wire [11:0] _T_1101 = _T_1091 ? io_dec_i0_instr_d[31:20] : 12'h0; // @[Mux.scala 27:72]
wire [11:0] _T_1101 = _T_1095 ? _T_1099 : 12'h0; // @[Mux.scala 27:72] wire [11:0] _T_1102 = _T_1096 ? _T_1100 : 12'h0; // @[Mux.scala 27:72]
dec_dec_ctl i0_dec ( // @[dec_decode_ctl.scala 440:22] dec_dec_ctl i0_dec ( // @[dec_decode_ctl.scala 440:22]
.io_ins(i0_dec_io_ins), .io_ins(i0_dec_io_ins),
.io_out_clz(i0_dec_io_out_clz), .io_out_clz(i0_dec_io_out_clz),
@ -3049,8 +3063,8 @@ module dec_decode_ctl(
.io_clk(rvclkhdr_10_io_clk), .io_clk(rvclkhdr_10_io_clk),
.io_en(rvclkhdr_10_io_en) .io_en(rvclkhdr_10_io_en)
); );
assign io_decode_exu_dec_data_en = {i0_x_data_en,i0_r_data_en}; // @[dec_decode_ctl.scala 775:38] assign io_decode_exu_dec_data_en = {i0_x_data_en,i0_r_data_en}; // @[dec_decode_ctl.scala 773:38]
assign io_decode_exu_dec_ctl_en = {i0_x_ctl_en,i0_r_ctl_en}; // @[dec_decode_ctl.scala 776:38] assign io_decode_exu_dec_ctl_en = {i0_x_ctl_en,i0_r_ctl_en}; // @[dec_decode_ctl.scala 774:38]
assign io_decode_exu_i0_ap_clz = _T_80 ? 1'h0 : i0_dp_raw_clz; // @[dec_decode_ctl.scala 319:33] assign io_decode_exu_i0_ap_clz = _T_80 ? 1'h0 : i0_dp_raw_clz; // @[dec_decode_ctl.scala 319:33]
assign io_decode_exu_i0_ap_ctz = _T_80 ? 1'h0 : i0_dp_raw_ctz; // @[dec_decode_ctl.scala 320:33] assign io_decode_exu_i0_ap_ctz = _T_80 ? 1'h0 : i0_dp_raw_ctz; // @[dec_decode_ctl.scala 320:33]
assign io_decode_exu_i0_ap_pcnt = _T_80 ? 1'h0 : i0_dp_raw_pcnt; // @[dec_decode_ctl.scala 321:33] assign io_decode_exu_i0_ap_pcnt = _T_80 ? 1'h0 : i0_dp_raw_pcnt; // @[dec_decode_ctl.scala 321:33]
@ -3109,15 +3123,15 @@ module dec_decode_ctl(
assign io_decode_exu_i0_predict_fghr_d = io_dec_i0_bp_fghr; // @[dec_decode_ctl.scala 247:58] assign io_decode_exu_i0_predict_fghr_d = io_dec_i0_bp_fghr; // @[dec_decode_ctl.scala 247:58]
assign io_decode_exu_i0_predict_index_d = io_dec_i0_bp_index; // @[dec_decode_ctl.scala 243:58] assign io_decode_exu_i0_predict_index_d = io_dec_i0_bp_index; // @[dec_decode_ctl.scala 243:58]
assign io_decode_exu_i0_predict_btag_d = io_dec_i0_bp_btag; // @[dec_decode_ctl.scala 244:58] assign io_decode_exu_i0_predict_btag_d = io_dec_i0_bp_btag; // @[dec_decode_ctl.scala 244:58]
assign io_decode_exu_dec_i0_rs1_en_d = i0_dp_rs1 & _T_657; // @[dec_decode_ctl.scala 682:35] assign io_decode_exu_dec_i0_rs1_en_d = i0_dp_rs1 & _T_658; // @[dec_decode_ctl.scala 680:35]
assign io_decode_exu_dec_i0_branch_d = _T_610 | i0_br_error_all; // @[dec_decode_ctl.scala 633:37] assign io_decode_exu_dec_i0_branch_d = _T_611 | i0_br_error_all; // @[dec_decode_ctl.scala 631:37]
assign io_decode_exu_dec_i0_rs2_en_d = i0_dp_rs2 & _T_659; // @[dec_decode_ctl.scala 683:35] assign io_decode_exu_dec_i0_rs2_en_d = i0_dp_rs2 & _T_660; // @[dec_decode_ctl.scala 681:35]
assign io_decode_exu_dec_i0_immed_d = _T_787 | _T_784; // @[dec_decode_ctl.scala 695:32] assign io_decode_exu_dec_i0_immed_d = _T_788 | _T_785; // @[dec_decode_ctl.scala 693:32]
assign io_decode_exu_dec_i0_result_r = i0_result_r_raw; // @[dec_decode_ctl.scala 921:41] assign io_decode_exu_dec_i0_result_r = i0_result_r_raw; // @[dec_decode_ctl.scala 919:41]
assign io_decode_exu_dec_qual_lsu_d = _T_80 ? 1'h0 : i0_dp_raw_lsu; // @[dec_decode_ctl.scala 638:32] assign io_decode_exu_dec_qual_lsu_d = _T_80 ? 1'h0 : i0_dp_raw_lsu; // @[dec_decode_ctl.scala 636:32]
assign io_decode_exu_dec_i0_select_pc_d = _T_80 ? 1'h0 : i0_dp_raw_pc; // @[dec_decode_ctl.scala 293:36] assign io_decode_exu_dec_i0_select_pc_d = _T_80 ? 1'h0 : i0_dp_raw_pc; // @[dec_decode_ctl.scala 293:36]
assign io_decode_exu_dec_i0_rs1_bypass_en_d = {_T_1064,_T_1063}; // @[dec_decode_ctl.scala 918:45] assign io_decode_exu_dec_i0_rs1_bypass_en_d = {_T_1065,_T_1064}; // @[dec_decode_ctl.scala 916:45]
assign io_decode_exu_dec_i0_rs2_bypass_en_d = {_T_1079,_T_1078}; // @[dec_decode_ctl.scala 919:45] assign io_decode_exu_dec_i0_rs2_bypass_en_d = {_T_1080,_T_1079}; // @[dec_decode_ctl.scala 917:45]
assign io_decode_exu_mul_p_valid = i0_exulegal_decode_d & i0_dp_mul; // @[dec_decode_ctl.scala 118:25 dec_decode_ctl.scala 473:32] assign io_decode_exu_mul_p_valid = i0_exulegal_decode_d & i0_dp_mul; // @[dec_decode_ctl.scala 118:25 dec_decode_ctl.scala 473:32]
assign io_decode_exu_mul_p_bits_rs1_sign = _T_80 ? 1'h0 : i0_dp_raw_rs1_sign; // @[dec_decode_ctl.scala 118:25 dec_decode_ctl.scala 474:37] assign io_decode_exu_mul_p_bits_rs1_sign = _T_80 ? 1'h0 : i0_dp_raw_rs1_sign; // @[dec_decode_ctl.scala 118:25 dec_decode_ctl.scala 474:37]
assign io_decode_exu_mul_p_bits_rs2_sign = _T_80 ? 1'h0 : i0_dp_raw_rs2_sign; // @[dec_decode_ctl.scala 118:25 dec_decode_ctl.scala 475:37] assign io_decode_exu_mul_p_bits_rs2_sign = _T_80 ? 1'h0 : i0_dp_raw_rs2_sign; // @[dec_decode_ctl.scala 118:25 dec_decode_ctl.scala 475:37]
@ -3138,22 +3152,22 @@ module dec_decode_ctl(
assign io_decode_exu_mul_p_bits_crc32c_h = _T_80 ? 1'h0 : i0_dp_raw_crc32c_h; // @[dec_decode_ctl.scala 118:25 dec_decode_ctl.scala 490:37] assign io_decode_exu_mul_p_bits_crc32c_h = _T_80 ? 1'h0 : i0_dp_raw_crc32c_h; // @[dec_decode_ctl.scala 118:25 dec_decode_ctl.scala 490:37]
assign io_decode_exu_mul_p_bits_crc32c_w = _T_80 ? 1'h0 : i0_dp_raw_crc32c_w; // @[dec_decode_ctl.scala 118:25 dec_decode_ctl.scala 491:37] assign io_decode_exu_mul_p_bits_crc32c_w = _T_80 ? 1'h0 : i0_dp_raw_crc32c_w; // @[dec_decode_ctl.scala 118:25 dec_decode_ctl.scala 491:37]
assign io_decode_exu_mul_p_bits_bfp = _T_80 ? 1'h0 : i0_dp_raw_bfp; // @[dec_decode_ctl.scala 118:25 dec_decode_ctl.scala 492:37] assign io_decode_exu_mul_p_bits_bfp = _T_80 ? 1'h0 : i0_dp_raw_bfp; // @[dec_decode_ctl.scala 118:25 dec_decode_ctl.scala 492:37]
assign io_decode_exu_pred_correct_npc_x = temp_pred_correct_npc_x[31:1]; // @[dec_decode_ctl.scala 879:36] assign io_decode_exu_pred_correct_npc_x = temp_pred_correct_npc_x[31:1]; // @[dec_decode_ctl.scala 877:36]
assign io_decode_exu_dec_extint_stall = _T_12; // @[dec_decode_ctl.scala 210:35] assign io_decode_exu_dec_extint_stall = _T_12; // @[dec_decode_ctl.scala 210:35]
assign io_dec_alu_dec_i0_alu_decode_d = i0_exulegal_decode_d & i0_dp_alu; // @[dec_decode_ctl.scala 632:34] assign io_dec_alu_dec_i0_alu_decode_d = i0_exulegal_decode_d & i0_dp_alu; // @[dec_decode_ctl.scala 630:34]
assign io_dec_alu_dec_csr_ren_d = i0_dp_csr_read & io_dec_ib0_valid_d; // @[dec_decode_ctl.scala 518:29] assign io_dec_alu_dec_csr_ren_d = i0_dp_csr_read & io_dec_ib0_valid_d; // @[dec_decode_ctl.scala 518:29]
assign io_dec_alu_dec_i0_br_immed_d = _T_885 ? i0_br_offset : _T_898; // @[dec_decode_ctl.scala 825:32] assign io_dec_alu_dec_i0_br_immed_d = _T_886 ? i0_br_offset : _T_899; // @[dec_decode_ctl.scala 823:32]
assign io_dec_div_div_p_valid = i0_exulegal_decode_d & i0_dp_div; // @[dec_decode_ctl.scala 469:29] assign io_dec_div_div_p_valid = i0_exulegal_decode_d & i0_dp_div; // @[dec_decode_ctl.scala 469:29]
assign io_dec_div_div_p_bits_unsign = _T_80 ? 1'h0 : i0_dp_raw_unsign; // @[dec_decode_ctl.scala 470:34] assign io_dec_div_div_p_bits_unsign = _T_80 ? 1'h0 : i0_dp_raw_unsign; // @[dec_decode_ctl.scala 470:34]
assign io_dec_div_div_p_bits_rem = _T_80 ? 1'h0 : i0_dp_raw_rem; // @[dec_decode_ctl.scala 471:34] assign io_dec_div_div_p_bits_rem = _T_80 ? 1'h0 : i0_dp_raw_rem; // @[dec_decode_ctl.scala 471:34]
assign io_dec_div_dec_div_cancel = _T_927 | _T_932; // @[dec_decode_ctl.scala 844:37] assign io_dec_div_dec_div_cancel = _T_928 | _T_933; // @[dec_decode_ctl.scala 842:37]
assign io_dec_i0_inst_wb = i0_inst_wb; // @[dec_decode_ctl.scala 870:21] assign io_dec_i0_inst_wb = i0_inst_wb; // @[dec_decode_ctl.scala 868:21]
assign io_dec_i0_pc_wb = i0_pc_wb; // @[dec_decode_ctl.scala 871:19] assign io_dec_i0_pc_wb = i0_pc_wb; // @[dec_decode_ctl.scala 869:19]
assign io_dec_i0_rs1_d = io_dec_i0_instr_d[19:15]; // @[dec_decode_ctl.scala 685:19] assign io_dec_i0_rs1_d = io_dec_i0_instr_d[19:15]; // @[dec_decode_ctl.scala 683:19]
assign io_dec_i0_rs2_d = io_dec_i0_instr_d[24:20]; // @[dec_decode_ctl.scala 686:19] assign io_dec_i0_rs2_d = io_dec_i0_instr_d[24:20]; // @[dec_decode_ctl.scala 684:19]
assign io_dec_i0_waddr_r = r_d_bits_i0rd; // @[dec_decode_ctl.scala 807:27] assign io_dec_i0_waddr_r = r_d_bits_i0rd; // @[dec_decode_ctl.scala 805:27]
assign io_dec_i0_wen_r = _T_871 & _T_872; // @[dec_decode_ctl.scala 809:32] assign io_dec_i0_wen_r = _T_872 & _T_873; // @[dec_decode_ctl.scala 807:32]
assign io_dec_i0_wdata_r = _T_881 ? io_lsu_result_corr_r : i0_result_r_raw; // @[dec_decode_ctl.scala 810:26] assign io_dec_i0_wdata_r = _T_882 ? io_lsu_result_corr_r : i0_result_r_raw; // @[dec_decode_ctl.scala 808:26]
assign io_lsu_p_valid = io_decode_exu_dec_extint_stall | lsu_decode_d; // @[dec_decode_ctl.scala 495:12 dec_decode_ctl.scala 500:24 dec_decode_ctl.scala 504:35] assign io_lsu_p_valid = io_decode_exu_dec_extint_stall | lsu_decode_d; // @[dec_decode_ctl.scala 495:12 dec_decode_ctl.scala 500:24 dec_decode_ctl.scala 504:35]
assign io_lsu_p_bits_fast_int = io_decode_exu_dec_extint_stall; // @[dec_decode_ctl.scala 495:12 dec_decode_ctl.scala 499:29] assign io_lsu_p_bits_fast_int = io_decode_exu_dec_extint_stall; // @[dec_decode_ctl.scala 495:12 dec_decode_ctl.scala 499:29]
assign io_lsu_p_bits_stack = io_decode_exu_dec_extint_stall ? 1'h0 : _T_425; // @[dec_decode_ctl.scala 495:12 dec_decode_ctl.scala 510:29] assign io_lsu_p_bits_stack = io_decode_exu_dec_extint_stall ? 1'h0 : _T_425; // @[dec_decode_ctl.scala 495:12 dec_decode_ctl.scala 510:29]
@ -3165,39 +3179,39 @@ module dec_decode_ctl(
assign io_lsu_p_bits_unsign = io_decode_exu_dec_extint_stall ? 1'h0 : i0_dp_unsign; // @[dec_decode_ctl.scala 495:12 dec_decode_ctl.scala 514:40] assign io_lsu_p_bits_unsign = io_decode_exu_dec_extint_stall ? 1'h0 : i0_dp_unsign; // @[dec_decode_ctl.scala 495:12 dec_decode_ctl.scala 514:40]
assign io_lsu_p_bits_store_data_bypass_d = io_decode_exu_dec_extint_stall ? 1'h0 : store_data_bypass_d; // @[dec_decode_ctl.scala 495:12 dec_decode_ctl.scala 512:40] assign io_lsu_p_bits_store_data_bypass_d = io_decode_exu_dec_extint_stall ? 1'h0 : store_data_bypass_d; // @[dec_decode_ctl.scala 495:12 dec_decode_ctl.scala 512:40]
assign io_lsu_p_bits_load_ldst_bypass_d = io_decode_exu_dec_extint_stall ? 1'h0 : load_ldst_bypass_d; // @[dec_decode_ctl.scala 495:12 dec_decode_ctl.scala 511:40] assign io_lsu_p_bits_load_ldst_bypass_d = io_decode_exu_dec_extint_stall ? 1'h0 : load_ldst_bypass_d; // @[dec_decode_ctl.scala 495:12 dec_decode_ctl.scala 511:40]
assign io_div_waddr_wb = _T_947; // @[dec_decode_ctl.scala 862:19] assign io_div_waddr_wb = _T_948; // @[dec_decode_ctl.scala 860:19]
assign io_dec_lsu_valid_raw_d = _T_1086 | io_decode_exu_dec_extint_stall; // @[dec_decode_ctl.scala 923:26] assign io_dec_lsu_valid_raw_d = _T_1087 | io_decode_exu_dec_extint_stall; // @[dec_decode_ctl.scala 921:26]
assign io_dec_lsu_offset_d = _T_1100 | _T_1101; // @[dec_decode_ctl.scala 924:23] assign io_dec_lsu_offset_d = _T_1101 | _T_1102; // @[dec_decode_ctl.scala 922:23]
assign io_dec_csr_wen_unq_d = _T_436 & io_dec_ib0_valid_d; // @[dec_decode_ctl.scala 527:24] assign io_dec_csr_wen_unq_d = _T_436 & io_dec_ib0_valid_d; // @[dec_decode_ctl.scala 527:24]
assign io_dec_csr_any_unq_d = any_csr_d & io_dec_ib0_valid_d; // @[dec_decode_ctl.scala 530:24] assign io_dec_csr_any_unq_d = any_csr_d & io_dec_ib0_valid_d; // @[dec_decode_ctl.scala 530:24]
assign io_dec_csr_rdaddr_d = _T_440 & io_dec_i0_instr_d[31:20]; // @[dec_decode_ctl.scala 531:24] assign io_dec_csr_rdaddr_d = _T_440 & io_dec_i0_instr_d[31:20]; // @[dec_decode_ctl.scala 531:24]
assign io_dec_csr_wen_r = _T_443 & _T_868; // @[dec_decode_ctl.scala 536:20] assign io_dec_csr_wen_r = _T_443 & _T_869; // @[dec_decode_ctl.scala 536:20]
assign io_dec_csr_wraddr_r = _T_445 & r_d_bits_csrwaddr; // @[dec_decode_ctl.scala 532:24] assign io_dec_csr_wraddr_r = _T_445 & r_d_bits_csrwaddr; // @[dec_decode_ctl.scala 532:24]
assign io_dec_csr_wrdata_r = _T_529 ? i0_result_corr_r : write_csr_data; // @[dec_decode_ctl.scala 576:24] assign io_dec_csr_wrdata_r = _T_529 ? i0_result_corr_r : write_csr_data; // @[dec_decode_ctl.scala 576:24]
assign io_dec_csr_stall_int_ff = _T_454 & _T_455; // @[dec_decode_ctl.scala 539:27] assign io_dec_csr_stall_int_ff = _T_454 & _T_455; // @[dec_decode_ctl.scala 539:27]
assign io_dec_tlu_i0_valid_r = r_d_valid & _T_857; // @[dec_decode_ctl.scala 639:29] assign io_dec_tlu_i0_valid_r = r_d_valid & _T_858; // @[dec_decode_ctl.scala 637:29]
assign io_dec_tlu_packet_r_legal = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_legal; // @[dec_decode_ctl.scala 671:39] assign io_dec_tlu_packet_r_legal = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_legal; // @[dec_decode_ctl.scala 669:39]
assign io_dec_tlu_packet_r_icaf = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_icaf; // @[dec_decode_ctl.scala 671:39] assign io_dec_tlu_packet_r_icaf = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_icaf; // @[dec_decode_ctl.scala 669:39]
assign io_dec_tlu_packet_r_icaf_second = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_icaf_second; // @[dec_decode_ctl.scala 671:39] assign io_dec_tlu_packet_r_icaf_second = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_icaf_second; // @[dec_decode_ctl.scala 669:39]
assign io_dec_tlu_packet_r_icaf_type = io_dec_tlu_flush_lower_wb ? 2'h0 : r_t_icaf_type; // @[dec_decode_ctl.scala 671:39] assign io_dec_tlu_packet_r_icaf_type = io_dec_tlu_flush_lower_wb ? 2'h0 : r_t_icaf_type; // @[dec_decode_ctl.scala 669:39]
assign io_dec_tlu_packet_r_fence_i = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_fence_i; // @[dec_decode_ctl.scala 671:39] assign io_dec_tlu_packet_r_fence_i = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_fence_i; // @[dec_decode_ctl.scala 669:39]
assign io_dec_tlu_packet_r_i0trigger = io_dec_tlu_flush_lower_wb ? 4'h0 : _T_644; // @[dec_decode_ctl.scala 671:39] assign io_dec_tlu_packet_r_i0trigger = io_dec_tlu_flush_lower_wb ? 4'h0 : _T_645; // @[dec_decode_ctl.scala 669:39]
assign io_dec_tlu_packet_r_pmu_i0_itype = io_dec_tlu_flush_lower_wb ? 4'h0 : r_t_pmu_i0_itype; // @[dec_decode_ctl.scala 671:39] assign io_dec_tlu_packet_r_pmu_i0_itype = io_dec_tlu_flush_lower_wb ? 4'h0 : r_t_pmu_i0_itype; // @[dec_decode_ctl.scala 669:39]
assign io_dec_tlu_packet_r_pmu_i0_br_unpred = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_pmu_i0_br_unpred; // @[dec_decode_ctl.scala 671:39] assign io_dec_tlu_packet_r_pmu_i0_br_unpred = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_pmu_i0_br_unpred; // @[dec_decode_ctl.scala 669:39]
assign io_dec_tlu_packet_r_pmu_divide = r_d_bits_i0div & r_d_valid; // @[dec_decode_ctl.scala 671:39 dec_decode_ctl.scala 672:39] assign io_dec_tlu_packet_r_pmu_divide = r_d_bits_i0div & r_d_valid; // @[dec_decode_ctl.scala 669:39 dec_decode_ctl.scala 670:39]
assign io_dec_tlu_packet_r_pmu_lsu_misaligned = io_dec_tlu_flush_lower_wb ? 1'h0 : lsu_pmu_misaligned_r; // @[dec_decode_ctl.scala 671:39] assign io_dec_tlu_packet_r_pmu_lsu_misaligned = io_dec_tlu_flush_lower_wb ? 1'h0 : lsu_pmu_misaligned_r; // @[dec_decode_ctl.scala 669:39]
assign io_dec_tlu_i0_pc_r = dec_i0_pc_r; // @[dec_decode_ctl.scala 874:27] assign io_dec_tlu_i0_pc_r = dec_i0_pc_r; // @[dec_decode_ctl.scala 872:27]
assign io_dec_illegal_inst = _T_565; // @[dec_decode_ctl.scala 598:23] assign io_dec_illegal_inst = _T_566; // @[dec_decode_ctl.scala 596:23]
assign io_dec_pmu_instr_decoded = io_dec_i0_decode_d; // @[dec_decode_ctl.scala 618:28] assign io_dec_pmu_instr_decoded = io_dec_i0_decode_d; // @[dec_decode_ctl.scala 616:28]
assign io_dec_pmu_decode_stall = io_dec_ib0_valid_d & _T_597; // @[dec_decode_ctl.scala 619:27] assign io_dec_pmu_decode_stall = io_dec_ib0_valid_d & _T_598; // @[dec_decode_ctl.scala 617:27]
assign io_dec_pmu_presync_stall = presync_stall & io_dec_ib0_valid_d; // @[dec_decode_ctl.scala 621:29] assign io_dec_pmu_presync_stall = presync_stall & io_dec_ib0_valid_d; // @[dec_decode_ctl.scala 619:29]
assign io_dec_pmu_postsync_stall = postsync_stall & io_dec_ib0_valid_d; // @[dec_decode_ctl.scala 620:29] assign io_dec_pmu_postsync_stall = postsync_stall & io_dec_ib0_valid_d; // @[dec_decode_ctl.scala 618:29]
assign io_dec_nonblock_load_wen = _T_279 & _T_280; // @[dec_decode_ctl.scala 401:28] assign io_dec_nonblock_load_wen = _T_279 & _T_280; // @[dec_decode_ctl.scala 401:28]
assign io_dec_nonblock_load_waddr = _T_325 | _T_317; // @[dec_decode_ctl.scala 398:29 dec_decode_ctl.scala 408:29] assign io_dec_nonblock_load_waddr = _T_325 | _T_317; // @[dec_decode_ctl.scala 398:29 dec_decode_ctl.scala 408:29]
assign io_dec_pause_state = pause_stall; // @[dec_decode_ctl.scala 562:22] assign io_dec_pause_state = pause_stall; // @[dec_decode_ctl.scala 562:22]
assign io_dec_pause_state_cg = pause_stall & _T_519; // @[dec_decode_ctl.scala 564:25] assign io_dec_pause_state_cg = pause_stall & _T_519; // @[dec_decode_ctl.scala 564:25]
assign io_dec_div_active = _T_42; // @[dec_decode_ctl.scala 219:35] assign io_dec_div_active = _T_42; // @[dec_decode_ctl.scala 219:35]
assign io_dec_i0_decode_d = _T_589 & _T_567; // @[dec_decode_ctl.scala 613:22 dec_decode_ctl.scala 676:22] assign io_dec_i0_decode_d = _T_590 & _T_568; // @[dec_decode_ctl.scala 611:22 dec_decode_ctl.scala 674:22]
assign i0_dec_io_ins = io_dec_i0_instr_d; // @[dec_decode_ctl.scala 441:16] assign i0_dec_io_ins = io_dec_i0_instr_d; // @[dec_decode_ctl.scala 441:16]
assign rvclkhdr_io_clk = clock; // @[lib.scala 406:18] assign rvclkhdr_io_clk = clock; // @[lib.scala 406:18]
assign rvclkhdr_io_en = i0_x_data_en & any_csr_d; // @[lib.scala 407:17] assign rvclkhdr_io_en = i0_x_data_en & any_csr_d; // @[lib.scala 407:17]
@ -3206,9 +3220,9 @@ module dec_decode_ctl(
assign rvclkhdr_2_io_clk = io_free_l2clk; // @[lib.scala 406:18] assign rvclkhdr_2_io_clk = io_free_l2clk; // @[lib.scala 406:18]
assign rvclkhdr_2_io_en = _T_527 | pause_stall; // @[lib.scala 407:17] assign rvclkhdr_2_io_en = _T_527 | pause_stall; // @[lib.scala 407:17]
assign rvclkhdr_3_io_clk = clock; // @[lib.scala 406:18] assign rvclkhdr_3_io_clk = clock; // @[lib.scala 406:18]
assign rvclkhdr_3_io_en = shift_illegal & _T_564; // @[lib.scala 407:17] assign rvclkhdr_3_io_en = shift_illegal & _T_565; // @[lib.scala 407:17]
assign rvclkhdr_4_io_clk = clock; // @[lib.scala 406:18] assign rvclkhdr_4_io_clk = clock; // @[lib.scala 406:18]
assign rvclkhdr_4_io_en = i0_r_data_en & _T_875; // @[lib.scala 407:17] assign rvclkhdr_4_io_en = i0_r_data_en & _T_876; // @[lib.scala 407:17]
assign rvclkhdr_5_io_clk = clock; // @[lib.scala 406:18] assign rvclkhdr_5_io_clk = clock; // @[lib.scala 406:18]
assign rvclkhdr_5_io_en = i0_pipe_en[3] | io_clk_override; // @[lib.scala 407:17] assign rvclkhdr_5_io_en = i0_pipe_en[3] | io_clk_override; // @[lib.scala 407:17]
assign rvclkhdr_6_io_clk = clock; // @[lib.scala 406:18] assign rvclkhdr_6_io_clk = clock; // @[lib.scala 406:18]
@ -3317,7 +3331,7 @@ initial begin
_RAND_29 = {1{`RANDOM}}; _RAND_29 = {1{`RANDOM}};
x_d_bits_i0load = _RAND_29[0:0]; x_d_bits_i0load = _RAND_29[0:0];
_RAND_30 = {1{`RANDOM}}; _RAND_30 = {1{`RANDOM}};
_T_815 = _RAND_30[2:0]; _T_816 = _RAND_30[2:0];
_RAND_31 = {1{`RANDOM}}; _RAND_31 = {1{`RANDOM}};
nonblock_load_valid_m_delay = _RAND_31[0:0]; nonblock_load_valid_m_delay = _RAND_31[0:0];
_RAND_32 = {1{`RANDOM}}; _RAND_32 = {1{`RANDOM}};
@ -3373,7 +3387,7 @@ initial begin
_RAND_57 = {1{`RANDOM}}; _RAND_57 = {1{`RANDOM}};
wbd_bits_csrwonly = _RAND_57[0:0]; wbd_bits_csrwonly = _RAND_57[0:0];
_RAND_58 = {1{`RANDOM}}; _RAND_58 = {1{`RANDOM}};
_T_565 = _RAND_58[31:0]; _T_566 = _RAND_58[31:0];
_RAND_59 = {1{`RANDOM}}; _RAND_59 = {1{`RANDOM}};
x_t_legal = _RAND_59[0:0]; x_t_legal = _RAND_59[0:0];
_RAND_60 = {1{`RANDOM}}; _RAND_60 = {1{`RANDOM}};
@ -3425,7 +3439,7 @@ initial begin
_RAND_83 = {1{`RANDOM}}; _RAND_83 = {1{`RANDOM}};
last_br_immed_x = _RAND_83[11:0]; last_br_immed_x = _RAND_83[11:0];
_RAND_84 = {1{`RANDOM}}; _RAND_84 = {1{`RANDOM}};
_T_947 = _RAND_84[4:0]; _T_948 = _RAND_84[4:0];
_RAND_85 = {1{`RANDOM}}; _RAND_85 = {1{`RANDOM}};
i0_inst_x = _RAND_85[31:0]; i0_inst_x = _RAND_85[31:0];
_RAND_86 = {1{`RANDOM}}; _RAND_86 = {1{`RANDOM}};
@ -3528,7 +3542,7 @@ initial begin
x_d_bits_i0load = 1'h0; x_d_bits_i0load = 1'h0;
end end
if (reset) begin if (reset) begin
_T_815 = 3'h0; _T_816 = 3'h0;
end end
if (reset) begin if (reset) begin
nonblock_load_valid_m_delay = 1'h0; nonblock_load_valid_m_delay = 1'h0;
@ -3612,7 +3626,7 @@ initial begin
wbd_bits_csrwonly = 1'h0; wbd_bits_csrwonly = 1'h0;
end end
if (reset) begin if (reset) begin
_T_565 = 32'h0; _T_566 = 32'h0;
end end
if (reset) begin if (reset) begin
x_t_legal = 1'h0; x_t_legal = 1'h0;
@ -3690,7 +3704,7 @@ initial begin
last_br_immed_x = 12'h0; last_br_immed_x = 12'h0;
end end
if (reset) begin if (reset) begin
_T_947 = 5'h0; _T_948 = 5'h0;
end end
if (reset) begin if (reset) begin
i0_inst_x = 32'h0; i0_inst_x = 32'h0;
@ -3963,9 +3977,9 @@ end // initial
end end
always @(posedge io_active_clk or posedge reset) begin always @(posedge io_active_clk or posedge reset) begin
if (reset) begin if (reset) begin
_T_815 <= 3'h0; _T_816 <= 3'h0;
end else begin end else begin
_T_815 <= i0_pipe_en[3:1]; _T_816 <= i0_pipe_en[3:1];
end end
end end
always @(posedge io_active_clk or posedge reset) begin always @(posedge io_active_clk or posedge reset) begin
@ -4173,8 +4187,8 @@ end // initial
always @(posedge clock or posedge reset) begin always @(posedge clock or posedge reset) begin
if (reset) begin if (reset) begin
i0_result_r_raw <= 32'h0; i0_result_r_raw <= 32'h0;
end else if (_T_876) begin end else if (_T_877) begin
if (_T_878) begin if (_T_879) begin
i0_result_r_raw <= io_lsu_result_m; i0_result_r_raw <= io_lsu_result_m;
end else begin end else begin
i0_result_r_raw <= io_decode_exu_exu_i0_result_x; i0_result_r_raw <= io_decode_exu_exu_i0_result_x;
@ -4197,12 +4211,12 @@ end // initial
end end
always @(posedge clock or posedge reset) begin always @(posedge clock or posedge reset) begin
if (reset) begin if (reset) begin
_T_565 <= 32'h0; _T_566 <= 32'h0;
end else if (illegal_inst_en) begin end else if (illegal_inst_en) begin
if (io_dec_i0_pc4_d) begin if (io_dec_i0_pc4_d) begin
_T_565 <= io_dec_i0_instr_d; _T_566 <= io_dec_i0_instr_d;
end else begin end else begin
_T_565 <= _T_562; _T_566 <= _T_563;
end end
end end
end end
@ -4383,7 +4397,7 @@ end // initial
last_br_immed_x <= 12'h0; last_br_immed_x <= 12'h0;
end else if (i0_x_data_en) begin end else if (i0_x_data_en) begin
if (io_decode_exu_i0_ap_predict_nt) begin if (io_decode_exu_i0_ap_predict_nt) begin
last_br_immed_x <= _T_898; last_br_immed_x <= _T_899;
end else if (_T_399) begin end else if (_T_399) begin
last_br_immed_x <= i0_pcall_imm[11:0]; last_br_immed_x <= i0_pcall_imm[11:0];
end else begin end else begin
@ -4393,40 +4407,40 @@ end // initial
end end
always @(posedge clock or posedge reset) begin always @(posedge clock or posedge reset) begin
if (reset) begin if (reset) begin
_T_947 <= 5'h0; _T_948 <= 5'h0;
end else if (i0_div_decode_d) begin end else if (i0_div_decode_d) begin
_T_947 <= i0r_rd; _T_948 <= i0r_rd;
end end
end end
always @(posedge clock or posedge reset) begin always @(posedge clock or posedge reset) begin
if (reset) begin if (reset) begin
i0_inst_x <= 32'h0; i0_inst_x <= 32'h0;
end else if (_T_948) begin end else if (_T_949) begin
if (io_dec_i0_pc4_d) begin if (io_dec_i0_pc4_d) begin
i0_inst_x <= io_dec_i0_instr_d; i0_inst_x <= io_dec_i0_instr_d;
end else begin end else begin
i0_inst_x <= _T_562; i0_inst_x <= _T_563;
end end
end end
end end
always @(posedge clock or posedge reset) begin always @(posedge clock or posedge reset) begin
if (reset) begin if (reset) begin
i0_inst_r <= 32'h0; i0_inst_r <= 32'h0;
end else if (_T_950) begin end else if (_T_951) begin
i0_inst_r <= i0_inst_x; i0_inst_r <= i0_inst_x;
end end
end end
always @(posedge clock or posedge reset) begin always @(posedge clock or posedge reset) begin
if (reset) begin if (reset) begin
i0_inst_wb <= 32'h0; i0_inst_wb <= 32'h0;
end else if (_T_952) begin end else if (_T_953) begin
i0_inst_wb <= i0_inst_r; i0_inst_wb <= i0_inst_r;
end end
end end
always @(posedge clock or posedge reset) begin always @(posedge clock or posedge reset) begin
if (reset) begin if (reset) begin
i0_pc_wb <= 31'h0; i0_pc_wb <= 31'h0;
end else if (_T_952) begin end else if (_T_953) begin
i0_pc_wb <= io_dec_tlu_i0_pc_r; i0_pc_wb <= io_dec_tlu_i0_pc_r;
end end
end end
@ -9632,15 +9646,15 @@ module csr_tlu(
assign io_dec_tlu_perfcnt1 = perf_csrs_io_dec_tlu_perfcnt1; // @[dec_tlu_ctl.scala 2437:29] assign io_dec_tlu_perfcnt1 = perf_csrs_io_dec_tlu_perfcnt1; // @[dec_tlu_ctl.scala 2437:29]
assign io_dec_tlu_perfcnt2 = perf_csrs_io_dec_tlu_perfcnt2; // @[dec_tlu_ctl.scala 2438:29] assign io_dec_tlu_perfcnt2 = perf_csrs_io_dec_tlu_perfcnt2; // @[dec_tlu_ctl.scala 2438:29]
assign io_dec_tlu_perfcnt3 = perf_csrs_io_dec_tlu_perfcnt3; // @[dec_tlu_ctl.scala 2439:29] assign io_dec_tlu_perfcnt3 = perf_csrs_io_dec_tlu_perfcnt3; // @[dec_tlu_ctl.scala 2439:29]
assign io_dec_tlu_misc_clk_override = mcgc[8]; // @[dec_tlu_ctl.scala 1757:38] assign io_dec_tlu_misc_clk_override = mcgc[8]; // @[dec_tlu_ctl.scala 1757:39]
assign io_dec_tlu_picio_clk_override = mcgc[9]; // @[dec_tlu_ctl.scala 1756:39] assign io_dec_tlu_picio_clk_override = mcgc[9]; // @[dec_tlu_ctl.scala 1756:39]
assign io_dec_tlu_dec_clk_override = mcgc[7]; // @[dec_tlu_ctl.scala 1758:38] assign io_dec_tlu_dec_clk_override = mcgc[7]; // @[dec_tlu_ctl.scala 1758:39]
assign io_dec_tlu_ifu_clk_override = mcgc[5]; // @[dec_tlu_ctl.scala 1759:38] assign io_dec_tlu_ifu_clk_override = mcgc[5]; // @[dec_tlu_ctl.scala 1759:39]
assign io_dec_tlu_lsu_clk_override = mcgc[4]; // @[dec_tlu_ctl.scala 1760:38] assign io_dec_tlu_lsu_clk_override = mcgc[4]; // @[dec_tlu_ctl.scala 1760:39]
assign io_dec_tlu_bus_clk_override = mcgc[3]; // @[dec_tlu_ctl.scala 1761:38] assign io_dec_tlu_bus_clk_override = mcgc[3]; // @[dec_tlu_ctl.scala 1761:39]
assign io_dec_tlu_pic_clk_override = mcgc[2]; // @[dec_tlu_ctl.scala 1762:38] assign io_dec_tlu_pic_clk_override = mcgc[2]; // @[dec_tlu_ctl.scala 1762:39]
assign io_dec_tlu_dccm_clk_override = mcgc[1]; // @[dec_tlu_ctl.scala 1763:38] assign io_dec_tlu_dccm_clk_override = mcgc[1]; // @[dec_tlu_ctl.scala 1763:39]
assign io_dec_tlu_icm_clk_override = mcgc[0]; // @[dec_tlu_ctl.scala 1764:38] assign io_dec_tlu_icm_clk_override = mcgc[0]; // @[dec_tlu_ctl.scala 1764:39]
assign io_dec_csr_rddata_d = _T_1434 | _T_1380; // @[dec_tlu_ctl.scala 2485:28] assign io_dec_csr_rddata_d = _T_1434 | _T_1380; // @[dec_tlu_ctl.scala 2485:28]
assign io_dec_tlu_pipelining_disable = mfdc[0]; // @[dec_tlu_ctl.scala 1813:46] assign io_dec_tlu_pipelining_disable = mfdc[0]; // @[dec_tlu_ctl.scala 1813:46]
assign io_dec_tlu_wr_pause_r = _T_426 & _T_427; // @[dec_tlu_ctl.scala 1822:31] assign io_dec_tlu_wr_pause_r = _T_426 & _T_427; // @[dec_tlu_ctl.scala 1822:31]

2
src/main/scala/dec/dec.scala
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@ -84,7 +84,7 @@ class dec_IO extends Bundle with lib {
val dec_tlu_perfcnt1 = Output(Bool()) // toggles when slot0 perf counter 1 has an event inc val dec_tlu_perfcnt1 = Output(Bool()) // toggles when slot0 perf counter 1 has an event inc
val dec_tlu_perfcnt2 = Output(Bool()) // toggles when slot0 perf counter 2 has an event inc val dec_tlu_perfcnt2 = Output(Bool()) // toggles when slot0 perf counter 2 has an event inc
val dec_tlu_perfcnt3 = Output(Bool()) // toggles when slot0 perf counter 3 has an event inc val dec_tlu_perfcnt3 = Output(Bool()) // toggles when slot0 perf counter 3 has an event inc
val dec_tlu_flush_lower_wb = Output(Bool()) val dec_tlu_flush_lower_wb = Output(Bool())
val dec_lsu_valid_raw_d = Output(Bool()) val dec_lsu_valid_raw_d = Output(Bool())
val trace_rv_trace_pkt = Output(new trace_pkt_t) // trace packet val trace_rv_trace_pkt = Output(new trace_pkt_t) // trace packet

8
src/main/scala/dec/dec_decode_ctl.scala
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@ -586,10 +586,8 @@ class dec_decode_ctl extends Module with lib with RequireAsyncReset{
// some CSR writes need to be postsync'd // some CSR writes need to be postsync'd
val i0_postsync = i0_dp.postsync | io.dec_tlu_postsync_d | debug_fence_i | (i0_csr_write_only_d & (i0(31,20) === "h7c2".U)) val i0_postsync = i0_dp.postsync | io.dec_tlu_postsync_d | debug_fence_i | (i0_csr_write_only_d & (i0(31,20) === "h7c2".U))
val bitmanip_legal = WireInit(Bool(),0.B)
val i0_legal = i0_dp.legal & (!any_csr_d | io.dec_csr_legal_d) & bitmanip_legal
val i0_legal = i0_dp.legal & (!any_csr_d | io.dec_csr_legal_d)
val i0_inst_d = Mux(io.dec_i0_pc4_d,i0,Cat(repl(16,0.U), io.dec_aln.ifu_i0_cinst)) val i0_inst_d = Mux(io.dec_i0_pc4_d,i0,Cat(repl(16,0.U), io.dec_aln.ifu_i0_cinst))
// illegal inst handling // illegal inst handling
@ -708,7 +706,7 @@ class dec_decode_ctl extends Module with lib with RequireAsyncReset{
val bitmanip_zbf_legal = WireInit(Bool(),0.B) val bitmanip_zbf_legal = WireInit(Bool(),0.B)
val bitmanip_zba_legal = WireInit(Bool(),0.B) val bitmanip_zba_legal = WireInit(Bool(),0.B)
val bitmanip_zbb_zbp_legal = WireInit(Bool(),0.B) val bitmanip_zbb_zbp_legal = WireInit(Bool(),0.B)
val bitmanip_legal = WireInit(Bool(),0.B)
if (BITMANIP_ZBB == 1) if (BITMANIP_ZBB == 1)
bitmanip_zbb_legal := 1.B bitmanip_zbb_legal := 1.B
else else

16
src/main/scala/dec/dec_tlu_ctl.scala
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@ -1754,14 +1754,14 @@ class csr_tlu extends Module with lib with CSRs with RequireAsyncReset {
mcgc_int := rvdffe(mcgc_ns,wr_mcgc_r.asBool,clock,io.scan_mode) mcgc_int := rvdffe(mcgc_ns,wr_mcgc_r.asBool,clock,io.scan_mode)
val mcgc = Cat(~mcgc_int(9), mcgc_int(8,0)) val mcgc = Cat(~mcgc_int(9), mcgc_int(8,0))
io.dec_tlu_picio_clk_override := mcgc(9) io.dec_tlu_picio_clk_override := mcgc(9)
io.dec_tlu_misc_clk_override := mcgc(8) io.dec_tlu_misc_clk_override := mcgc(8)
io.dec_tlu_dec_clk_override := mcgc(7) io.dec_tlu_dec_clk_override := mcgc(7)
io.dec_tlu_ifu_clk_override := mcgc(5) io.dec_tlu_ifu_clk_override := mcgc(5)
io.dec_tlu_lsu_clk_override := mcgc(4) io.dec_tlu_lsu_clk_override := mcgc(4)
io.dec_tlu_bus_clk_override := mcgc(3) io.dec_tlu_bus_clk_override := mcgc(3)
io.dec_tlu_pic_clk_override := mcgc(2) io.dec_tlu_pic_clk_override := mcgc(2)
io.dec_tlu_dccm_clk_override := mcgc(1) io.dec_tlu_dccm_clk_override := mcgc(1)
io.dec_tlu_icm_clk_override := mcgc(0) io.dec_tlu_icm_clk_override := mcgc(0)
// ---------------------------------------------------------------------- // ----------------------------------------------------------------------
// MFDC (RW) Feature Disable Control // MFDC (RW) Feature Disable Control

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target/scala-2.12/classes/dec/csr_tlu.class
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target/scala-2.12/classes/dec/dec_decode_ctl.class
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