Bus-buffer testing start
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b4a84e2c47
commit
63b7686462
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@ -71,6 +71,15 @@
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"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_nonblock_load_data_error"
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"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_nonblock_load_data_error"
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]
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]
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},
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_test",
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"sources":[
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"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ldst_dual_r",
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"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_busreq_r",
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"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_busreq_m"
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]
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},
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{
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{
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"class":"firrtl.transforms.CombinationalPath",
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_imprecise_error_addr_any",
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"sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_imprecise_error_addr_any",
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File diff suppressed because it is too large
Load Diff
1971
el2_lsu_bus_buffer.v
1971
el2_lsu_bus_buffer.v
File diff suppressed because it is too large
Load Diff
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@ -105,7 +105,7 @@ class el2_lsu_bus_buffer extends Module with RequireAsyncReset with el2_lib {
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val lsu_axi_arprot = Output(UInt(3.W))
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val lsu_axi_arprot = Output(UInt(3.W))
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val lsu_axi_arqos = Output(UInt(4.W))
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val lsu_axi_arqos = Output(UInt(4.W))
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val lsu_axi_rready = Output(Bool())
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val lsu_axi_rready = Output(Bool())
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val test = Output(UInt())
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})
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})
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def indexing(in : UInt, index : UInt) = Mux1H((0 until math.pow(2, index.getWidth).asInstanceOf[Int]).map(i=>(index===i.U)->in(i)))
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def indexing(in : UInt, index : UInt) = Mux1H((0 until math.pow(2, index.getWidth).asInstanceOf[Int]).map(i=>(index===i.U)->in(i)))
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def indexing(in : Vec[UInt], index : UInt) = Mux1H((0 until math.pow(2, index.getWidth).asInstanceOf[Int]).map(i=>(index===i.U)->in(i)))
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def indexing(in : Vec[UInt], index : UInt) = Mux1H((0 until math.pow(2, index.getWidth).asInstanceOf[Int]).map(i=>(index===i.U)->in(i)))
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@ -395,6 +395,7 @@ class el2_lsu_bus_buffer extends Module with RequireAsyncReset with el2_lib {
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val found_array2 = (0 until DEPTH).map(i=>((buf_state(i)===idle_C) & !((ibuf_valid & (ibuf_tag===i.U)) |
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val found_array2 = (0 until DEPTH).map(i=>((buf_state(i)===idle_C) & !((ibuf_valid & (ibuf_tag===i.U)) |
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(io.lsu_busreq_m & (WrPtr0_m===i.U)) | (io.lsu_busreq_r & (WrPtr0_r === i.U)) | (io.ldst_dual_r & (WrPtr1_r===i.U))))->i.U)
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(io.lsu_busreq_m & (WrPtr0_m===i.U)) | (io.lsu_busreq_r & (WrPtr0_r === i.U)) | (io.ldst_dual_r & (WrPtr1_r===i.U))))->i.U)
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val WrPtr1_m = MuxCase(0.U, found_array2)
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val WrPtr1_m = MuxCase(0.U, found_array2)
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io.test := WrPtr1_m
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val buf_age = Wire(Vec(DEPTH, UInt(DEPTH.W)))
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val buf_age = Wire(Vec(DEPTH, UInt(DEPTH.W)))
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buf_age := buf_age.map(i=> 0.U)
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buf_age := buf_age.map(i=> 0.U)
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val CmdPtr0Dec = (0 until DEPTH).map(i=> (!(buf_age(i).orR) & (buf_state(i)===cmd_C) & !buf_cmd_state_bus_en(i)).asUInt).reverse.reduce(Cat(_,_))
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val CmdPtr0Dec = (0 until DEPTH).map(i=> (!(buf_age(i).orR) & (buf_state(i)===cmd_C) & !buf_cmd_state_bus_en(i)).asUInt).reverse.reduce(Cat(_,_))
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