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2 bit divider

This commit is contained in:
​Laraib Khan 2021-01-06 09:32:46 +05:00
parent a4474e1299
commit 65d5369d1e
132 changed files with 20779 additions and 4672 deletions
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1
.idea/modules.xml
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@ -4,6 +4,7 @@
<modules> <modules>
<module fileurl="file://$PROJECT_DIR$/.idea/modules/Quasar.iml" filepath="$PROJECT_DIR$/.idea/modules/Quasar.iml" /> <module fileurl="file://$PROJECT_DIR$/.idea/modules/Quasar.iml" filepath="$PROJECT_DIR$/.idea/modules/Quasar.iml" />
<module fileurl="file://$PROJECT_DIR$/.idea/modules/Quasar-build.iml" filepath="$PROJECT_DIR$/.idea/modules/Quasar-build.iml" /> <module fileurl="file://$PROJECT_DIR$/.idea/modules/Quasar-build.iml" filepath="$PROJECT_DIR$/.idea/modules/Quasar-build.iml" />
<module fileurl="file://$PROJECT_DIR$/untitled/untitled.iml" filepath="$PROJECT_DIR$/untitled/untitled.iml" />
</modules> </modules>
</component> </component>
</project> </project>

30
el2_exu_div_existing_1bit_cheapshortq.anno.json Normal file
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@ -0,0 +1,30 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_exu_div_existing_1bit_cheapshortq|el2_exu_div_existing_1bit_cheapshortq>io_valid_out",
"sources":[
"~el2_exu_div_existing_1bit_cheapshortq|el2_exu_div_existing_1bit_cheapshortq>io_cancel"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"el2_exu_div_existing_1bit_cheapshortq.gated_latch",
"resourceId":"/vsrc/gated_latch.sv"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"el2_exu_div_existing_1bit_cheapshortq"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

2244
el2_exu_div_existing_1bit_cheapshortq.fir Normal file
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File diff suppressed because it is too large Load Diff

938
el2_exu_div_existing_1bit_cheapshortq.v Normal file
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@ -0,0 +1,938 @@
module rvclkhdr(
input io_clk,
input io_en
);
wire clkhdr_Q; // @[lib.scala 334:26]
wire clkhdr_CK; // @[lib.scala 334:26]
wire clkhdr_EN; // @[lib.scala 334:26]
wire clkhdr_SE; // @[lib.scala 334:26]
gated_latch clkhdr ( // @[lib.scala 334:26]
.Q(clkhdr_Q),
.CK(clkhdr_CK),
.EN(clkhdr_EN),
.SE(clkhdr_SE)
);
assign clkhdr_CK = io_clk; // @[lib.scala 336:18]
assign clkhdr_EN = io_en; // @[lib.scala 337:18]
assign clkhdr_SE = 1'h0; // @[lib.scala 338:18]
endmodule
module el2_exu_div_existing_1bit_cheapshortq(
input clock,
input reset,
input io_scan_mode,
input io_cancel,
input io_valid_in,
input io_signed_in,
input io_rem_in,
input [31:0] io_dividend_in,
input [31:0] io_divisor_in,
output [31:0] io_data_out,
output io_valid_out
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [63:0] _RAND_1;
reg [63:0] _RAND_2;
reg [31:0] _RAND_3;
reg [31:0] _RAND_4;
reg [31:0] _RAND_5;
reg [31:0] _RAND_6;
reg [31:0] _RAND_7;
reg [31:0] _RAND_8;
reg [31:0] _RAND_9;
reg [31:0] _RAND_10;
reg [63:0] _RAND_11;
reg [31:0] _RAND_12;
reg [31:0] _RAND_13;
reg [31:0] _RAND_14;
`endif // RANDOMIZE_REG_INIT
wire rvclkhdr_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_io_en; // @[lib.scala 390:23]
wire rvclkhdr_1_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_1_io_en; // @[lib.scala 390:23]
wire rvclkhdr_2_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_2_io_en; // @[lib.scala 390:23]
wire rvclkhdr_3_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_3_io_en; // @[lib.scala 390:23]
wire rvclkhdr_4_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_4_io_en; // @[lib.scala 390:23]
wire rvclkhdr_5_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_5_io_en; // @[lib.scala 390:23]
wire rvclkhdr_6_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_6_io_en; // @[lib.scala 390:23]
wire rvclkhdr_7_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_7_io_en; // @[lib.scala 390:23]
wire rvclkhdr_8_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_8_io_en; // @[lib.scala 390:23]
wire rvclkhdr_9_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_9_io_en; // @[lib.scala 390:23]
wire rvclkhdr_10_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_10_io_en; // @[lib.scala 390:23]
wire rvclkhdr_11_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_11_io_en; // @[lib.scala 390:23]
wire rvclkhdr_12_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_12_io_en; // @[lib.scala 390:23]
wire rvclkhdr_13_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_13_io_en; // @[lib.scala 390:23]
wire rvclkhdr_14_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_14_io_en; // @[lib.scala 390:23]
wire _T = ~io_cancel; // @[exu_div_ctl.scala 127:30]
reg valid_ff_x; // @[Reg.scala 27:20]
wire valid_x = valid_ff_x & _T; // @[exu_div_ctl.scala 127:28]
reg [32:0] q_ff; // @[Reg.scala 27:20]
wire _T_2 = q_ff[31:4] == 28'h0; // @[exu_div_ctl.scala 133:34]
reg [32:0] m_ff; // @[Reg.scala 27:20]
wire _T_4 = m_ff[31:4] == 28'h0; // @[exu_div_ctl.scala 133:57]
wire _T_5 = _T_2 & _T_4; // @[exu_div_ctl.scala 133:43]
wire _T_7 = m_ff[31:0] != 32'h0; // @[exu_div_ctl.scala 133:80]
wire _T_8 = _T_5 & _T_7; // @[exu_div_ctl.scala 133:66]
reg rem_ff; // @[Reg.scala 27:20]
wire _T_9 = ~rem_ff; // @[exu_div_ctl.scala 133:91]
wire _T_10 = _T_8 & _T_9; // @[exu_div_ctl.scala 133:89]
wire _T_11 = _T_10 & valid_x; // @[exu_div_ctl.scala 133:99]
wire _T_13 = q_ff[31:0] == 32'h0; // @[exu_div_ctl.scala 134:18]
wire _T_16 = _T_13 & _T_7; // @[exu_div_ctl.scala 134:27]
wire _T_18 = _T_16 & _T_9; // @[exu_div_ctl.scala 134:50]
wire _T_19 = _T_18 & valid_x; // @[exu_div_ctl.scala 134:60]
wire smallnum_case = _T_11 | _T_19; // @[exu_div_ctl.scala 133:110]
wire _T_23 = ~m_ff[3]; // @[exu_div_ctl.scala 138:69]
wire _T_25 = ~m_ff[2]; // @[exu_div_ctl.scala 138:69]
wire _T_27 = ~m_ff[1]; // @[exu_div_ctl.scala 138:69]
wire _T_28 = _T_23 & _T_25; // @[exu_div_ctl.scala 138:94]
wire _T_29 = _T_28 & _T_27; // @[exu_div_ctl.scala 138:94]
wire _T_30 = q_ff[3] & _T_29; // @[exu_div_ctl.scala 139:10]
wire _T_37 = q_ff[3] & _T_28; // @[exu_div_ctl.scala 139:10]
wire _T_39 = ~m_ff[0]; // @[exu_div_ctl.scala 145:32]
wire _T_40 = _T_37 & _T_39; // @[exu_div_ctl.scala 145:30]
wire _T_50 = q_ff[2] & _T_29; // @[exu_div_ctl.scala 139:10]
wire _T_51 = _T_40 | _T_50; // @[exu_div_ctl.scala 145:41]
wire _T_54 = q_ff[3] & q_ff[2]; // @[exu_div_ctl.scala 137:94]
wire _T_60 = _T_54 & _T_28; // @[exu_div_ctl.scala 139:10]
wire _T_61 = _T_51 | _T_60; // @[exu_div_ctl.scala 145:73]
wire _T_68 = q_ff[2] & _T_28; // @[exu_div_ctl.scala 139:10]
wire _T_71 = _T_68 & _T_39; // @[exu_div_ctl.scala 147:30]
wire _T_81 = q_ff[1] & _T_29; // @[exu_div_ctl.scala 139:10]
wire _T_82 = _T_71 | _T_81; // @[exu_div_ctl.scala 147:41]
wire _T_88 = _T_23 & _T_27; // @[exu_div_ctl.scala 138:94]
wire _T_89 = q_ff[3] & _T_88; // @[exu_div_ctl.scala 139:10]
wire _T_92 = _T_89 & _T_39; // @[exu_div_ctl.scala 147:103]
wire _T_93 = _T_82 | _T_92; // @[exu_div_ctl.scala 147:76]
wire _T_96 = ~q_ff[2]; // @[exu_div_ctl.scala 137:69]
wire _T_97 = q_ff[3] & _T_96; // @[exu_div_ctl.scala 137:94]
wire _T_105 = _T_28 & m_ff[1]; // @[exu_div_ctl.scala 138:94]
wire _T_106 = _T_105 & m_ff[0]; // @[exu_div_ctl.scala 138:94]
wire _T_107 = _T_97 & _T_106; // @[exu_div_ctl.scala 139:10]
wire _T_108 = _T_93 | _T_107; // @[exu_div_ctl.scala 147:114]
wire _T_110 = ~q_ff[3]; // @[exu_div_ctl.scala 137:69]
wire _T_113 = _T_110 & q_ff[2]; // @[exu_div_ctl.scala 137:94]
wire _T_114 = _T_113 & q_ff[1]; // @[exu_div_ctl.scala 137:94]
wire _T_120 = _T_114 & _T_28; // @[exu_div_ctl.scala 139:10]
wire _T_121 = _T_108 | _T_120; // @[exu_div_ctl.scala 148:43]
wire _T_127 = _T_54 & _T_23; // @[exu_div_ctl.scala 139:10]
wire _T_130 = _T_127 & _T_39; // @[exu_div_ctl.scala 148:104]
wire _T_131 = _T_121 | _T_130; // @[exu_div_ctl.scala 148:78]
wire _T_140 = _T_23 & m_ff[2]; // @[exu_div_ctl.scala 138:94]
wire _T_141 = _T_140 & _T_27; // @[exu_div_ctl.scala 138:94]
wire _T_142 = _T_54 & _T_141; // @[exu_div_ctl.scala 139:10]
wire _T_143 = _T_131 | _T_142; // @[exu_div_ctl.scala 148:116]
wire _T_146 = q_ff[3] & q_ff[1]; // @[exu_div_ctl.scala 137:94]
wire _T_152 = _T_146 & _T_88; // @[exu_div_ctl.scala 139:10]
wire _T_153 = _T_143 | _T_152; // @[exu_div_ctl.scala 149:43]
wire _T_158 = _T_54 & q_ff[1]; // @[exu_div_ctl.scala 137:94]
wire _T_163 = _T_158 & _T_140; // @[exu_div_ctl.scala 139:10]
wire _T_164 = _T_153 | _T_163; // @[exu_div_ctl.scala 149:77]
wire _T_168 = q_ff[2] & q_ff[1]; // @[exu_div_ctl.scala 137:94]
wire _T_169 = _T_168 & q_ff[0]; // @[exu_div_ctl.scala 137:94]
wire _T_175 = _T_169 & _T_88; // @[exu_div_ctl.scala 139:10]
wire _T_181 = _T_97 & q_ff[0]; // @[exu_div_ctl.scala 137:94]
wire _T_186 = _T_23 & m_ff[1]; // @[exu_div_ctl.scala 138:94]
wire _T_187 = _T_186 & m_ff[0]; // @[exu_div_ctl.scala 138:94]
wire _T_188 = _T_181 & _T_187; // @[exu_div_ctl.scala 139:10]
wire _T_189 = _T_175 | _T_188; // @[exu_div_ctl.scala 151:44]
wire _T_196 = q_ff[2] & _T_88; // @[exu_div_ctl.scala 139:10]
wire _T_199 = _T_196 & _T_39; // @[exu_div_ctl.scala 151:111]
wire _T_200 = _T_189 | _T_199; // @[exu_div_ctl.scala 151:84]
wire _T_207 = q_ff[1] & _T_28; // @[exu_div_ctl.scala 139:10]
wire _T_210 = _T_207 & _T_39; // @[exu_div_ctl.scala 152:32]
wire _T_211 = _T_200 | _T_210; // @[exu_div_ctl.scala 151:126]
wire _T_221 = q_ff[0] & _T_29; // @[exu_div_ctl.scala 139:10]
wire _T_222 = _T_211 | _T_221; // @[exu_div_ctl.scala 152:46]
wire _T_227 = ~q_ff[1]; // @[exu_div_ctl.scala 137:69]
wire _T_229 = _T_113 & _T_227; // @[exu_div_ctl.scala 137:94]
wire _T_239 = _T_229 & _T_106; // @[exu_div_ctl.scala 139:10]
wire _T_240 = _T_222 | _T_239; // @[exu_div_ctl.scala 152:86]
wire _T_249 = _T_114 & _T_23; // @[exu_div_ctl.scala 139:10]
wire _T_252 = _T_249 & _T_39; // @[exu_div_ctl.scala 153:35]
wire _T_253 = _T_240 | _T_252; // @[exu_div_ctl.scala 152:128]
wire _T_259 = _T_25 & _T_27; // @[exu_div_ctl.scala 138:94]
wire _T_260 = q_ff[3] & _T_259; // @[exu_div_ctl.scala 139:10]
wire _T_263 = _T_260 & _T_39; // @[exu_div_ctl.scala 153:74]
wire _T_264 = _T_253 | _T_263; // @[exu_div_ctl.scala 153:46]
wire _T_274 = _T_140 & m_ff[1]; // @[exu_div_ctl.scala 138:94]
wire _T_275 = _T_97 & _T_274; // @[exu_div_ctl.scala 139:10]
wire _T_276 = _T_264 | _T_275; // @[exu_div_ctl.scala 153:86]
wire _T_290 = _T_114 & _T_141; // @[exu_div_ctl.scala 139:10]
wire _T_291 = _T_276 | _T_290; // @[exu_div_ctl.scala 153:128]
wire _T_297 = _T_113 & q_ff[0]; // @[exu_div_ctl.scala 137:94]
wire _T_303 = _T_297 & _T_88; // @[exu_div_ctl.scala 139:10]
wire _T_304 = _T_291 | _T_303; // @[exu_div_ctl.scala 154:46]
wire _T_311 = _T_97 & _T_227; // @[exu_div_ctl.scala 137:94]
wire _T_317 = _T_140 & m_ff[0]; // @[exu_div_ctl.scala 138:94]
wire _T_318 = _T_311 & _T_317; // @[exu_div_ctl.scala 139:10]
wire _T_319 = _T_304 | _T_318; // @[exu_div_ctl.scala 154:86]
wire _T_324 = _T_96 & q_ff[1]; // @[exu_div_ctl.scala 137:94]
wire _T_325 = _T_324 & q_ff[0]; // @[exu_div_ctl.scala 137:94]
wire _T_331 = _T_325 & _T_28; // @[exu_div_ctl.scala 139:10]
wire _T_332 = _T_319 | _T_331; // @[exu_div_ctl.scala 154:128]
wire _T_338 = _T_54 & _T_27; // @[exu_div_ctl.scala 139:10]
wire _T_341 = _T_338 & _T_39; // @[exu_div_ctl.scala 155:73]
wire _T_342 = _T_332 | _T_341; // @[exu_div_ctl.scala 155:46]
wire _T_350 = _T_114 & q_ff[0]; // @[exu_div_ctl.scala 137:94]
wire _T_355 = _T_350 & _T_140; // @[exu_div_ctl.scala 139:10]
wire _T_356 = _T_342 | _T_355; // @[exu_div_ctl.scala 155:86]
wire _T_363 = m_ff[3] & _T_25; // @[exu_div_ctl.scala 138:94]
wire _T_364 = _T_54 & _T_363; // @[exu_div_ctl.scala 139:10]
wire _T_365 = _T_356 | _T_364; // @[exu_div_ctl.scala 155:128]
wire _T_375 = _T_363 & _T_27; // @[exu_div_ctl.scala 138:94]
wire _T_376 = _T_146 & _T_375; // @[exu_div_ctl.scala 139:10]
wire _T_377 = _T_365 | _T_376; // @[exu_div_ctl.scala 156:46]
wire _T_380 = q_ff[3] & q_ff[0]; // @[exu_div_ctl.scala 137:94]
wire _T_386 = _T_380 & _T_259; // @[exu_div_ctl.scala 139:10]
wire _T_387 = _T_377 | _T_386; // @[exu_div_ctl.scala 156:86]
wire _T_391 = q_ff[3] & _T_227; // @[exu_div_ctl.scala 137:94]
wire _T_399 = _T_274 & m_ff[0]; // @[exu_div_ctl.scala 138:94]
wire _T_400 = _T_391 & _T_399; // @[exu_div_ctl.scala 139:10]
wire _T_401 = _T_387 | _T_400; // @[exu_div_ctl.scala 156:128]
wire _T_408 = _T_158 & m_ff[3]; // @[exu_div_ctl.scala 139:10]
wire _T_411 = _T_408 & _T_39; // @[exu_div_ctl.scala 157:75]
wire _T_412 = _T_401 | _T_411; // @[exu_div_ctl.scala 157:46]
wire _T_421 = m_ff[3] & _T_27; // @[exu_div_ctl.scala 138:94]
wire _T_422 = _T_158 & _T_421; // @[exu_div_ctl.scala 139:10]
wire _T_423 = _T_412 | _T_422; // @[exu_div_ctl.scala 157:86]
wire _T_428 = _T_54 & q_ff[0]; // @[exu_div_ctl.scala 137:94]
wire _T_433 = _T_428 & _T_421; // @[exu_div_ctl.scala 139:10]
wire _T_434 = _T_423 | _T_433; // @[exu_div_ctl.scala 157:128]
wire _T_440 = _T_97 & q_ff[1]; // @[exu_div_ctl.scala 137:94]
wire _T_445 = _T_440 & _T_186; // @[exu_div_ctl.scala 139:10]
wire _T_446 = _T_434 | _T_445; // @[exu_div_ctl.scala 158:46]
wire _T_451 = _T_146 & q_ff[0]; // @[exu_div_ctl.scala 137:94]
wire _T_454 = _T_451 & _T_25; // @[exu_div_ctl.scala 139:10]
wire _T_455 = _T_446 | _T_454; // @[exu_div_ctl.scala 158:86]
wire _T_462 = _T_158 & q_ff[0]; // @[exu_div_ctl.scala 137:94]
wire _T_464 = _T_462 & m_ff[3]; // @[exu_div_ctl.scala 139:10]
wire _T_465 = _T_455 | _T_464; // @[exu_div_ctl.scala 158:128]
wire _T_471 = _T_146 & _T_25; // @[exu_div_ctl.scala 139:10]
wire _T_474 = _T_471 & _T_39; // @[exu_div_ctl.scala 159:72]
wire _T_475 = _T_465 | _T_474; // @[exu_div_ctl.scala 159:46]
wire [3:0] smallnum = {_T_30,_T_61,_T_164,_T_475}; // @[Cat.scala 29:58]
reg sign_ff; // @[Reg.scala 27:20]
wire _T_479 = sign_ff & q_ff[31]; // @[exu_div_ctl.scala 168:34]
wire [32:0] short_dividend = {_T_479,q_ff[31:0]}; // @[Cat.scala 29:58]
wire _T_484 = ~short_dividend[32]; // @[exu_div_ctl.scala 173:7]
wire _T_487 = short_dividend[31:24] != 8'h0; // @[exu_div_ctl.scala 173:60]
wire _T_492 = short_dividend[31:23] != 9'h1ff; // @[exu_div_ctl.scala 174:59]
wire _T_493 = _T_484 & _T_487; // @[Mux.scala 27:72]
wire _T_494 = short_dividend[32] & _T_492; // @[Mux.scala 27:72]
wire _T_495 = _T_493 | _T_494; // @[Mux.scala 27:72]
wire _T_502 = short_dividend[23:16] != 8'h0; // @[exu_div_ctl.scala 177:60]
wire _T_507 = short_dividend[22:15] != 8'hff; // @[exu_div_ctl.scala 178:59]
wire _T_508 = _T_484 & _T_502; // @[Mux.scala 27:72]
wire _T_509 = short_dividend[32] & _T_507; // @[Mux.scala 27:72]
wire _T_510 = _T_508 | _T_509; // @[Mux.scala 27:72]
wire _T_517 = short_dividend[15:8] != 8'h0; // @[exu_div_ctl.scala 181:59]
wire _T_522 = short_dividend[14:7] != 8'hff; // @[exu_div_ctl.scala 182:58]
wire _T_523 = _T_484 & _T_517; // @[Mux.scala 27:72]
wire _T_524 = short_dividend[32] & _T_522; // @[Mux.scala 27:72]
wire _T_525 = _T_523 | _T_524; // @[Mux.scala 27:72]
wire [4:0] a_cls = {2'h0,_T_495,_T_510,_T_525}; // @[Cat.scala 29:58]
wire _T_531 = ~m_ff[32]; // @[exu_div_ctl.scala 187:7]
wire _T_534 = m_ff[31:24] != 8'h0; // @[exu_div_ctl.scala 187:40]
wire _T_539 = m_ff[31:24] != 8'hff; // @[exu_div_ctl.scala 188:39]
wire _T_540 = _T_531 & _T_534; // @[Mux.scala 27:72]
wire _T_541 = m_ff[32] & _T_539; // @[Mux.scala 27:72]
wire _T_542 = _T_540 | _T_541; // @[Mux.scala 27:72]
wire _T_549 = m_ff[23:16] != 8'h0; // @[exu_div_ctl.scala 191:40]
wire _T_554 = m_ff[23:16] != 8'hff; // @[exu_div_ctl.scala 192:39]
wire _T_555 = _T_531 & _T_549; // @[Mux.scala 27:72]
wire _T_556 = m_ff[32] & _T_554; // @[Mux.scala 27:72]
wire _T_557 = _T_555 | _T_556; // @[Mux.scala 27:72]
wire _T_564 = m_ff[15:8] != 8'h0; // @[exu_div_ctl.scala 195:39]
wire _T_569 = m_ff[15:8] != 8'hff; // @[exu_div_ctl.scala 196:38]
wire _T_570 = _T_531 & _T_564; // @[Mux.scala 27:72]
wire _T_571 = m_ff[32] & _T_569; // @[Mux.scala 27:72]
wire _T_572 = _T_570 | _T_571; // @[Mux.scala 27:72]
wire [4:0] b_cls = {2'h0,_T_542,_T_557,_T_572}; // @[Cat.scala 29:58]
wire _T_577 = a_cls[2:1] == 2'h1; // @[exu_div_ctl.scala 200:19]
wire _T_580 = _T_577 & b_cls[2]; // @[exu_div_ctl.scala 200:34]
wire _T_582 = a_cls[2:0] == 3'h1; // @[exu_div_ctl.scala 201:21]
wire _T_585 = _T_582 & b_cls[2]; // @[exu_div_ctl.scala 201:36]
wire _T_586 = _T_580 | _T_585; // @[exu_div_ctl.scala 200:65]
wire _T_588 = a_cls[2:0] == 3'h0; // @[exu_div_ctl.scala 202:21]
wire _T_591 = _T_588 & b_cls[2]; // @[exu_div_ctl.scala 202:36]
wire _T_592 = _T_586 | _T_591; // @[exu_div_ctl.scala 201:67]
wire _T_596 = b_cls[2:1] == 2'h1; // @[exu_div_ctl.scala 203:50]
wire _T_597 = _T_582 & _T_596; // @[exu_div_ctl.scala 203:36]
wire _T_598 = _T_592 | _T_597; // @[exu_div_ctl.scala 202:67]
wire _T_603 = _T_588 & _T_596; // @[exu_div_ctl.scala 204:36]
wire _T_604 = _T_598 | _T_603; // @[exu_div_ctl.scala 203:67]
wire _T_608 = b_cls[2:0] == 3'h1; // @[exu_div_ctl.scala 205:50]
wire _T_609 = _T_588 & _T_608; // @[exu_div_ctl.scala 205:36]
wire _T_610 = _T_604 | _T_609; // @[exu_div_ctl.scala 204:67]
wire _T_615 = a_cls[2] & b_cls[2]; // @[exu_div_ctl.scala 207:34]
wire _T_620 = _T_577 & _T_596; // @[exu_div_ctl.scala 208:36]
wire _T_621 = _T_615 | _T_620; // @[exu_div_ctl.scala 207:65]
wire _T_626 = _T_582 & _T_608; // @[exu_div_ctl.scala 209:36]
wire _T_627 = _T_621 | _T_626; // @[exu_div_ctl.scala 208:67]
wire _T_631 = b_cls[2:0] == 3'h0; // @[exu_div_ctl.scala 210:50]
wire _T_632 = _T_588 & _T_631; // @[exu_div_ctl.scala 210:36]
wire _T_633 = _T_627 | _T_632; // @[exu_div_ctl.scala 209:67]
wire _T_638 = a_cls[2] & _T_596; // @[exu_div_ctl.scala 212:34]
wire _T_643 = _T_577 & _T_608; // @[exu_div_ctl.scala 213:36]
wire _T_644 = _T_638 | _T_643; // @[exu_div_ctl.scala 212:65]
wire _T_649 = _T_582 & _T_631; // @[exu_div_ctl.scala 214:36]
wire _T_650 = _T_644 | _T_649; // @[exu_div_ctl.scala 213:67]
wire _T_655 = a_cls[2] & _T_608; // @[exu_div_ctl.scala 216:34]
wire _T_660 = _T_577 & _T_631; // @[exu_div_ctl.scala 217:36]
wire _T_661 = _T_655 | _T_660; // @[exu_div_ctl.scala 216:65]
wire [3:0] shortq_raw = {_T_610,_T_633,_T_650,_T_661}; // @[Cat.scala 29:58]
wire _T_666 = valid_ff_x & _T_7; // @[exu_div_ctl.scala 220:35]
wire _T_667 = shortq_raw != 4'h0; // @[exu_div_ctl.scala 220:78]
wire shortq_enable = _T_666 & _T_667; // @[exu_div_ctl.scala 220:64]
wire [3:0] _T_669 = shortq_enable ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
wire [3:0] _T_670 = _T_669 & shortq_raw; // @[exu_div_ctl.scala 221:57]
wire [5:0] shortq_shift = {2'h0,_T_670}; // @[Cat.scala 29:58]
reg [5:0] _T_1520; // @[Reg.scala 27:20]
wire [3:0] shortq_shift_xx = _T_1520[3:0]; // @[exu_div_ctl.scala 277:21]
wire [4:0] _T_679 = shortq_shift_xx[3] ? 5'h1f : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_680 = shortq_shift_xx[2] ? 5'h18 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_681 = shortq_shift_xx[1] ? 5'h10 : 5'h0; // @[Mux.scala 27:72]
wire [3:0] _T_682 = shortq_shift_xx[0] ? 4'h8 : 4'h0; // @[Mux.scala 27:72]
wire [4:0] _T_683 = _T_679 | _T_680; // @[Mux.scala 27:72]
wire [4:0] _T_684 = _T_683 | _T_681; // @[Mux.scala 27:72]
wire [4:0] _GEN_15 = {{1'd0}, _T_682}; // @[Mux.scala 27:72]
wire [4:0] _T_685 = _T_684 | _GEN_15; // @[Mux.scala 27:72]
wire [5:0] shortq_shift_ff = {1'h0,_T_685}; // @[Cat.scala 29:58]
reg [5:0] count; // @[Reg.scala 27:20]
wire _T_688 = count == 6'h20; // @[exu_div_ctl.scala 230:55]
wire _T_689 = count == 6'h21; // @[exu_div_ctl.scala 230:76]
wire _T_690 = _T_9 ? _T_688 : _T_689; // @[exu_div_ctl.scala 230:39]
wire finish = smallnum_case | _T_690; // @[exu_div_ctl.scala 230:34]
reg run_state; // @[Reg.scala 27:20]
wire _T_691 = io_valid_in | run_state; // @[exu_div_ctl.scala 231:32]
wire _T_692 = _T_691 | finish; // @[exu_div_ctl.scala 231:44]
reg finish_ff; // @[Reg.scala 27:20]
wire div_clken = _T_692 | finish_ff; // @[exu_div_ctl.scala 231:53]
wire _T_694 = ~finish; // @[exu_div_ctl.scala 232:48]
wire _T_695 = _T_691 & _T_694; // @[exu_div_ctl.scala 232:46]
wire run_in = _T_695 & _T; // @[exu_div_ctl.scala 232:56]
wire _T_698 = run_state & _T_694; // @[exu_div_ctl.scala 233:35]
wire _T_700 = _T_698 & _T; // @[exu_div_ctl.scala 233:45]
wire _T_701 = ~shortq_enable; // @[exu_div_ctl.scala 233:60]
wire _T_702 = _T_700 & _T_701; // @[exu_div_ctl.scala 233:58]
wire [5:0] _T_704 = _T_702 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12]
wire [5:0] _T_706 = {1'h0,shortq_shift_ff[4:0]}; // @[Cat.scala 29:58]
wire [5:0] _T_708 = count + _T_706; // @[exu_div_ctl.scala 233:86]
wire [5:0] _T_710 = _T_708 + 6'h1; // @[exu_div_ctl.scala 233:118]
wire [5:0] count_in = _T_704 & _T_710; // @[exu_div_ctl.scala 233:77]
wire _T_714 = io_divisor_in != 32'h0; // @[exu_div_ctl.scala 235:50]
wire sign_eff = io_signed_in & _T_714; // @[exu_div_ctl.scala 235:33]
wire _T_715 = ~run_state; // @[exu_div_ctl.scala 238:6]
wire [32:0] _T_717 = {1'h0,io_dividend_in}; // @[Cat.scala 29:58]
reg shortq_enable_ff; // @[Reg.scala 27:20]
wire _T_718 = valid_ff_x | shortq_enable_ff; // @[exu_div_ctl.scala 239:30]
wire _T_719 = run_state & _T_718; // @[exu_div_ctl.scala 239:16]
reg dividend_neg_ff; // @[Reg.scala 27:20]
wire _T_743 = sign_ff & dividend_neg_ff; // @[exu_div_ctl.scala 243:32]
wire _T_928 = |q_ff[30:0]; // @[lib.scala 428:35]
wire _T_930 = ~q_ff[31]; // @[lib.scala 428:40]
wire _T_932 = _T_928 ? _T_930 : q_ff[31]; // @[lib.scala 428:23]
wire _T_922 = |q_ff[29:0]; // @[lib.scala 428:35]
wire _T_924 = ~q_ff[30]; // @[lib.scala 428:40]
wire _T_926 = _T_922 ? _T_924 : q_ff[30]; // @[lib.scala 428:23]
wire _T_916 = |q_ff[28:0]; // @[lib.scala 428:35]
wire _T_918 = ~q_ff[29]; // @[lib.scala 428:40]
wire _T_920 = _T_916 ? _T_918 : q_ff[29]; // @[lib.scala 428:23]
wire _T_910 = |q_ff[27:0]; // @[lib.scala 428:35]
wire _T_912 = ~q_ff[28]; // @[lib.scala 428:40]
wire _T_914 = _T_910 ? _T_912 : q_ff[28]; // @[lib.scala 428:23]
wire _T_904 = |q_ff[26:0]; // @[lib.scala 428:35]
wire _T_906 = ~q_ff[27]; // @[lib.scala 428:40]
wire _T_908 = _T_904 ? _T_906 : q_ff[27]; // @[lib.scala 428:23]
wire _T_898 = |q_ff[25:0]; // @[lib.scala 428:35]
wire _T_900 = ~q_ff[26]; // @[lib.scala 428:40]
wire _T_902 = _T_898 ? _T_900 : q_ff[26]; // @[lib.scala 428:23]
wire _T_892 = |q_ff[24:0]; // @[lib.scala 428:35]
wire _T_894 = ~q_ff[25]; // @[lib.scala 428:40]
wire _T_896 = _T_892 ? _T_894 : q_ff[25]; // @[lib.scala 428:23]
wire _T_886 = |q_ff[23:0]; // @[lib.scala 428:35]
wire _T_888 = ~q_ff[24]; // @[lib.scala 428:40]
wire _T_890 = _T_886 ? _T_888 : q_ff[24]; // @[lib.scala 428:23]
wire _T_880 = |q_ff[22:0]; // @[lib.scala 428:35]
wire _T_882 = ~q_ff[23]; // @[lib.scala 428:40]
wire _T_884 = _T_880 ? _T_882 : q_ff[23]; // @[lib.scala 428:23]
wire _T_874 = |q_ff[21:0]; // @[lib.scala 428:35]
wire _T_876 = ~q_ff[22]; // @[lib.scala 428:40]
wire _T_878 = _T_874 ? _T_876 : q_ff[22]; // @[lib.scala 428:23]
wire _T_868 = |q_ff[20:0]; // @[lib.scala 428:35]
wire _T_870 = ~q_ff[21]; // @[lib.scala 428:40]
wire _T_872 = _T_868 ? _T_870 : q_ff[21]; // @[lib.scala 428:23]
wire _T_862 = |q_ff[19:0]; // @[lib.scala 428:35]
wire _T_864 = ~q_ff[20]; // @[lib.scala 428:40]
wire _T_866 = _T_862 ? _T_864 : q_ff[20]; // @[lib.scala 428:23]
wire _T_856 = |q_ff[18:0]; // @[lib.scala 428:35]
wire _T_858 = ~q_ff[19]; // @[lib.scala 428:40]
wire _T_860 = _T_856 ? _T_858 : q_ff[19]; // @[lib.scala 428:23]
wire _T_850 = |q_ff[17:0]; // @[lib.scala 428:35]
wire _T_852 = ~q_ff[18]; // @[lib.scala 428:40]
wire _T_854 = _T_850 ? _T_852 : q_ff[18]; // @[lib.scala 428:23]
wire _T_844 = |q_ff[16:0]; // @[lib.scala 428:35]
wire _T_846 = ~q_ff[17]; // @[lib.scala 428:40]
wire _T_848 = _T_844 ? _T_846 : q_ff[17]; // @[lib.scala 428:23]
wire _T_838 = |q_ff[15:0]; // @[lib.scala 428:35]
wire _T_840 = ~q_ff[16]; // @[lib.scala 428:40]
wire _T_842 = _T_838 ? _T_840 : q_ff[16]; // @[lib.scala 428:23]
wire [7:0] _T_953 = {_T_884,_T_878,_T_872,_T_866,_T_860,_T_854,_T_848,_T_842}; // @[lib.scala 430:14]
wire _T_832 = |q_ff[14:0]; // @[lib.scala 428:35]
wire _T_834 = ~q_ff[15]; // @[lib.scala 428:40]
wire _T_836 = _T_832 ? _T_834 : q_ff[15]; // @[lib.scala 428:23]
wire _T_826 = |q_ff[13:0]; // @[lib.scala 428:35]
wire _T_828 = ~q_ff[14]; // @[lib.scala 428:40]
wire _T_830 = _T_826 ? _T_828 : q_ff[14]; // @[lib.scala 428:23]
wire _T_820 = |q_ff[12:0]; // @[lib.scala 428:35]
wire _T_822 = ~q_ff[13]; // @[lib.scala 428:40]
wire _T_824 = _T_820 ? _T_822 : q_ff[13]; // @[lib.scala 428:23]
wire _T_814 = |q_ff[11:0]; // @[lib.scala 428:35]
wire _T_816 = ~q_ff[12]; // @[lib.scala 428:40]
wire _T_818 = _T_814 ? _T_816 : q_ff[12]; // @[lib.scala 428:23]
wire _T_808 = |q_ff[10:0]; // @[lib.scala 428:35]
wire _T_810 = ~q_ff[11]; // @[lib.scala 428:40]
wire _T_812 = _T_808 ? _T_810 : q_ff[11]; // @[lib.scala 428:23]
wire _T_802 = |q_ff[9:0]; // @[lib.scala 428:35]
wire _T_804 = ~q_ff[10]; // @[lib.scala 428:40]
wire _T_806 = _T_802 ? _T_804 : q_ff[10]; // @[lib.scala 428:23]
wire _T_796 = |q_ff[8:0]; // @[lib.scala 428:35]
wire _T_798 = ~q_ff[9]; // @[lib.scala 428:40]
wire _T_800 = _T_796 ? _T_798 : q_ff[9]; // @[lib.scala 428:23]
wire _T_790 = |q_ff[7:0]; // @[lib.scala 428:35]
wire _T_792 = ~q_ff[8]; // @[lib.scala 428:40]
wire _T_794 = _T_790 ? _T_792 : q_ff[8]; // @[lib.scala 428:23]
wire _T_784 = |q_ff[6:0]; // @[lib.scala 428:35]
wire _T_786 = ~q_ff[7]; // @[lib.scala 428:40]
wire _T_788 = _T_784 ? _T_786 : q_ff[7]; // @[lib.scala 428:23]
wire _T_778 = |q_ff[5:0]; // @[lib.scala 428:35]
wire _T_780 = ~q_ff[6]; // @[lib.scala 428:40]
wire _T_782 = _T_778 ? _T_780 : q_ff[6]; // @[lib.scala 428:23]
wire _T_772 = |q_ff[4:0]; // @[lib.scala 428:35]
wire _T_774 = ~q_ff[5]; // @[lib.scala 428:40]
wire _T_776 = _T_772 ? _T_774 : q_ff[5]; // @[lib.scala 428:23]
wire _T_766 = |q_ff[3:0]; // @[lib.scala 428:35]
wire _T_768 = ~q_ff[4]; // @[lib.scala 428:40]
wire _T_770 = _T_766 ? _T_768 : q_ff[4]; // @[lib.scala 428:23]
wire _T_760 = |q_ff[2:0]; // @[lib.scala 428:35]
wire _T_762 = ~q_ff[3]; // @[lib.scala 428:40]
wire _T_764 = _T_760 ? _T_762 : q_ff[3]; // @[lib.scala 428:23]
wire _T_754 = |q_ff[1:0]; // @[lib.scala 428:35]
wire _T_756 = ~q_ff[2]; // @[lib.scala 428:40]
wire _T_758 = _T_754 ? _T_756 : q_ff[2]; // @[lib.scala 428:23]
wire _T_748 = |q_ff[0]; // @[lib.scala 428:35]
wire _T_750 = ~q_ff[1]; // @[lib.scala 428:40]
wire _T_752 = _T_748 ? _T_750 : q_ff[1]; // @[lib.scala 428:23]
wire [6:0] _T_938 = {_T_788,_T_782,_T_776,_T_770,_T_764,_T_758,_T_752}; // @[lib.scala 430:14]
wire [14:0] _T_946 = {_T_836,_T_830,_T_824,_T_818,_T_812,_T_806,_T_800,_T_794,_T_938}; // @[lib.scala 430:14]
wire [30:0] _T_962 = {_T_932,_T_926,_T_920,_T_914,_T_908,_T_902,_T_896,_T_890,_T_953,_T_946}; // @[lib.scala 430:14]
wire [31:0] _T_964 = {_T_962,q_ff[0]}; // @[Cat.scala 29:58]
wire [31:0] dividend_eff = _T_743 ? _T_964 : q_ff[31:0]; // @[exu_div_ctl.scala 243:22]
wire [32:0] _T_1000 = run_state ? 33'h1ffffffff : 33'h0; // @[Bitwise.scala 72:12]
wire _T_1012 = _T_689 & rem_ff; // @[exu_div_ctl.scala 257:41]
reg [32:0] a_ff; // @[Reg.scala 27:20]
wire rem_correct = _T_1012 & a_ff[32]; // @[exu_div_ctl.scala 257:50]
wire [32:0] _T_985 = rem_correct ? a_ff : 33'h0; // @[Mux.scala 27:72]
wire _T_974 = ~rem_correct; // @[exu_div_ctl.scala 248:6]
wire _T_975 = ~shortq_enable_ff; // @[exu_div_ctl.scala 248:21]
wire _T_976 = _T_974 & _T_975; // @[exu_div_ctl.scala 248:19]
wire [32:0] _T_980 = {a_ff[31:0],q_ff[32]}; // @[Cat.scala 29:58]
wire [32:0] _T_986 = _T_976 ? _T_980 : 33'h0; // @[Mux.scala 27:72]
wire [32:0] _T_988 = _T_985 | _T_986; // @[Mux.scala 27:72]
wire _T_982 = _T_974 & shortq_enable_ff; // @[exu_div_ctl.scala 249:19]
wire [64:0] _T_970 = {33'h0,dividend_eff}; // @[Cat.scala 29:58]
wire [95:0] _GEN_16 = {{31'd0}, _T_970}; // @[exu_div_ctl.scala 245:47]
wire [95:0] _T_972 = _GEN_16 << shortq_shift_ff[4:0]; // @[exu_div_ctl.scala 245:47]
wire [64:0] a_eff_shift = _T_972[64:0]; // @[exu_div_ctl.scala 245:15]
wire [32:0] _T_987 = _T_982 ? a_eff_shift[64:32] : 33'h0; // @[Mux.scala 27:72]
wire [32:0] a_eff = _T_988 | _T_987; // @[Mux.scala 27:72]
wire [32:0] a_shift = _T_1000 & a_eff; // @[exu_div_ctl.scala 252:33]
wire _T_1009 = a_ff[32] | rem_correct; // @[exu_div_ctl.scala 256:21]
reg divisor_neg_ff; // @[Reg.scala 27:20]
wire m_already_comp = divisor_neg_ff & sign_ff; // @[exu_div_ctl.scala 254:48]
wire add = _T_1009 ^ m_already_comp; // @[exu_div_ctl.scala 256:36]
wire [32:0] _T_968 = ~m_ff; // @[exu_div_ctl.scala 244:35]
wire [32:0] m_eff = add ? m_ff : _T_968; // @[exu_div_ctl.scala 244:15]
wire [32:0] _T_1002 = a_shift + m_eff; // @[exu_div_ctl.scala 253:41]
wire _T_1003 = ~add; // @[exu_div_ctl.scala 253:65]
wire [32:0] _T_1004 = {32'h0,_T_1003}; // @[Cat.scala 29:58]
wire [32:0] _T_1006 = _T_1002 + _T_1004; // @[exu_div_ctl.scala 253:49]
wire [32:0] a_in = _T_1000 & _T_1006; // @[exu_div_ctl.scala 253:30]
wire _T_723 = ~a_in[32]; // @[exu_div_ctl.scala 239:85]
wire [32:0] _T_724 = {dividend_eff,_T_723}; // @[Cat.scala 29:58]
wire [63:0] _GEN_17 = {{31'd0}, _T_724}; // @[exu_div_ctl.scala 239:96]
wire [63:0] _T_726 = _GEN_17 << shortq_shift_ff[4:0]; // @[exu_div_ctl.scala 239:96]
wire _T_728 = ~_T_718; // @[exu_div_ctl.scala 240:18]
wire _T_729 = run_state & _T_728; // @[exu_div_ctl.scala 240:16]
wire [32:0] _T_734 = {q_ff[31:0],_T_723}; // @[Cat.scala 29:58]
wire [32:0] _T_735 = _T_715 ? _T_717 : 33'h0; // @[Mux.scala 27:72]
wire [63:0] _T_736 = _T_719 ? _T_726 : 64'h0; // @[Mux.scala 27:72]
wire [32:0] _T_737 = _T_729 ? _T_734 : 33'h0; // @[Mux.scala 27:72]
wire [63:0] _GEN_18 = {{31'd0}, _T_735}; // @[Mux.scala 27:72]
wire [63:0] _T_738 = _GEN_18 | _T_736; // @[Mux.scala 27:72]
wire [63:0] _GEN_19 = {{31'd0}, _T_737}; // @[Mux.scala 27:72]
wire [63:0] _T_739 = _T_738 | _GEN_19; // @[Mux.scala 27:72]
wire _T_742 = run_state & _T_701; // @[exu_div_ctl.scala 242:48]
wire qff_enable = io_valid_in | _T_742; // @[exu_div_ctl.scala 242:35]
wire _T_993 = count != 6'h21; // @[exu_div_ctl.scala 251:73]
wire _T_994 = _T_742 & _T_993; // @[exu_div_ctl.scala 251:64]
wire _T_995 = io_valid_in | _T_994; // @[exu_div_ctl.scala 251:34]
wire aff_enable = _T_995 | rem_correct; // @[exu_div_ctl.scala 251:89]
wire _T_1015 = dividend_neg_ff ^ divisor_neg_ff; // @[exu_div_ctl.scala 258:50]
wire _T_1016 = sign_ff & _T_1015; // @[exu_div_ctl.scala 258:31]
wire [31:0] q_ff_eff = _T_1016 ? _T_964 : q_ff[31:0]; // @[exu_div_ctl.scala 258:21]
wire _T_1244 = |a_ff[0]; // @[lib.scala 428:35]
wire _T_1246 = ~a_ff[1]; // @[lib.scala 428:40]
wire _T_1248 = _T_1244 ? _T_1246 : a_ff[1]; // @[lib.scala 428:23]
wire _T_1250 = |a_ff[1:0]; // @[lib.scala 428:35]
wire _T_1252 = ~a_ff[2]; // @[lib.scala 428:40]
wire _T_1254 = _T_1250 ? _T_1252 : a_ff[2]; // @[lib.scala 428:23]
wire _T_1256 = |a_ff[2:0]; // @[lib.scala 428:35]
wire _T_1258 = ~a_ff[3]; // @[lib.scala 428:40]
wire _T_1260 = _T_1256 ? _T_1258 : a_ff[3]; // @[lib.scala 428:23]
wire _T_1262 = |a_ff[3:0]; // @[lib.scala 428:35]
wire _T_1264 = ~a_ff[4]; // @[lib.scala 428:40]
wire _T_1266 = _T_1262 ? _T_1264 : a_ff[4]; // @[lib.scala 428:23]
wire _T_1268 = |a_ff[4:0]; // @[lib.scala 428:35]
wire _T_1270 = ~a_ff[5]; // @[lib.scala 428:40]
wire _T_1272 = _T_1268 ? _T_1270 : a_ff[5]; // @[lib.scala 428:23]
wire _T_1274 = |a_ff[5:0]; // @[lib.scala 428:35]
wire _T_1276 = ~a_ff[6]; // @[lib.scala 428:40]
wire _T_1278 = _T_1274 ? _T_1276 : a_ff[6]; // @[lib.scala 428:23]
wire _T_1280 = |a_ff[6:0]; // @[lib.scala 428:35]
wire _T_1282 = ~a_ff[7]; // @[lib.scala 428:40]
wire _T_1284 = _T_1280 ? _T_1282 : a_ff[7]; // @[lib.scala 428:23]
wire _T_1286 = |a_ff[7:0]; // @[lib.scala 428:35]
wire _T_1288 = ~a_ff[8]; // @[lib.scala 428:40]
wire _T_1290 = _T_1286 ? _T_1288 : a_ff[8]; // @[lib.scala 428:23]
wire _T_1292 = |a_ff[8:0]; // @[lib.scala 428:35]
wire _T_1294 = ~a_ff[9]; // @[lib.scala 428:40]
wire _T_1296 = _T_1292 ? _T_1294 : a_ff[9]; // @[lib.scala 428:23]
wire _T_1298 = |a_ff[9:0]; // @[lib.scala 428:35]
wire _T_1300 = ~a_ff[10]; // @[lib.scala 428:40]
wire _T_1302 = _T_1298 ? _T_1300 : a_ff[10]; // @[lib.scala 428:23]
wire _T_1304 = |a_ff[10:0]; // @[lib.scala 428:35]
wire _T_1306 = ~a_ff[11]; // @[lib.scala 428:40]
wire _T_1308 = _T_1304 ? _T_1306 : a_ff[11]; // @[lib.scala 428:23]
wire _T_1310 = |a_ff[11:0]; // @[lib.scala 428:35]
wire _T_1312 = ~a_ff[12]; // @[lib.scala 428:40]
wire _T_1314 = _T_1310 ? _T_1312 : a_ff[12]; // @[lib.scala 428:23]
wire _T_1316 = |a_ff[12:0]; // @[lib.scala 428:35]
wire _T_1318 = ~a_ff[13]; // @[lib.scala 428:40]
wire _T_1320 = _T_1316 ? _T_1318 : a_ff[13]; // @[lib.scala 428:23]
wire _T_1322 = |a_ff[13:0]; // @[lib.scala 428:35]
wire _T_1324 = ~a_ff[14]; // @[lib.scala 428:40]
wire _T_1326 = _T_1322 ? _T_1324 : a_ff[14]; // @[lib.scala 428:23]
wire _T_1328 = |a_ff[14:0]; // @[lib.scala 428:35]
wire _T_1330 = ~a_ff[15]; // @[lib.scala 428:40]
wire _T_1332 = _T_1328 ? _T_1330 : a_ff[15]; // @[lib.scala 428:23]
wire _T_1334 = |a_ff[15:0]; // @[lib.scala 428:35]
wire _T_1336 = ~a_ff[16]; // @[lib.scala 428:40]
wire _T_1338 = _T_1334 ? _T_1336 : a_ff[16]; // @[lib.scala 428:23]
wire _T_1340 = |a_ff[16:0]; // @[lib.scala 428:35]
wire _T_1342 = ~a_ff[17]; // @[lib.scala 428:40]
wire _T_1344 = _T_1340 ? _T_1342 : a_ff[17]; // @[lib.scala 428:23]
wire _T_1346 = |a_ff[17:0]; // @[lib.scala 428:35]
wire _T_1348 = ~a_ff[18]; // @[lib.scala 428:40]
wire _T_1350 = _T_1346 ? _T_1348 : a_ff[18]; // @[lib.scala 428:23]
wire _T_1352 = |a_ff[18:0]; // @[lib.scala 428:35]
wire _T_1354 = ~a_ff[19]; // @[lib.scala 428:40]
wire _T_1356 = _T_1352 ? _T_1354 : a_ff[19]; // @[lib.scala 428:23]
wire _T_1358 = |a_ff[19:0]; // @[lib.scala 428:35]
wire _T_1360 = ~a_ff[20]; // @[lib.scala 428:40]
wire _T_1362 = _T_1358 ? _T_1360 : a_ff[20]; // @[lib.scala 428:23]
wire _T_1364 = |a_ff[20:0]; // @[lib.scala 428:35]
wire _T_1366 = ~a_ff[21]; // @[lib.scala 428:40]
wire _T_1368 = _T_1364 ? _T_1366 : a_ff[21]; // @[lib.scala 428:23]
wire _T_1370 = |a_ff[21:0]; // @[lib.scala 428:35]
wire _T_1372 = ~a_ff[22]; // @[lib.scala 428:40]
wire _T_1374 = _T_1370 ? _T_1372 : a_ff[22]; // @[lib.scala 428:23]
wire _T_1376 = |a_ff[22:0]; // @[lib.scala 428:35]
wire _T_1378 = ~a_ff[23]; // @[lib.scala 428:40]
wire _T_1380 = _T_1376 ? _T_1378 : a_ff[23]; // @[lib.scala 428:23]
wire _T_1382 = |a_ff[23:0]; // @[lib.scala 428:35]
wire _T_1384 = ~a_ff[24]; // @[lib.scala 428:40]
wire _T_1386 = _T_1382 ? _T_1384 : a_ff[24]; // @[lib.scala 428:23]
wire _T_1388 = |a_ff[24:0]; // @[lib.scala 428:35]
wire _T_1390 = ~a_ff[25]; // @[lib.scala 428:40]
wire _T_1392 = _T_1388 ? _T_1390 : a_ff[25]; // @[lib.scala 428:23]
wire _T_1394 = |a_ff[25:0]; // @[lib.scala 428:35]
wire _T_1396 = ~a_ff[26]; // @[lib.scala 428:40]
wire _T_1398 = _T_1394 ? _T_1396 : a_ff[26]; // @[lib.scala 428:23]
wire _T_1400 = |a_ff[26:0]; // @[lib.scala 428:35]
wire _T_1402 = ~a_ff[27]; // @[lib.scala 428:40]
wire _T_1404 = _T_1400 ? _T_1402 : a_ff[27]; // @[lib.scala 428:23]
wire _T_1406 = |a_ff[27:0]; // @[lib.scala 428:35]
wire _T_1408 = ~a_ff[28]; // @[lib.scala 428:40]
wire _T_1410 = _T_1406 ? _T_1408 : a_ff[28]; // @[lib.scala 428:23]
wire _T_1412 = |a_ff[28:0]; // @[lib.scala 428:35]
wire _T_1414 = ~a_ff[29]; // @[lib.scala 428:40]
wire _T_1416 = _T_1412 ? _T_1414 : a_ff[29]; // @[lib.scala 428:23]
wire _T_1418 = |a_ff[29:0]; // @[lib.scala 428:35]
wire _T_1420 = ~a_ff[30]; // @[lib.scala 428:40]
wire _T_1422 = _T_1418 ? _T_1420 : a_ff[30]; // @[lib.scala 428:23]
wire _T_1424 = |a_ff[30:0]; // @[lib.scala 428:35]
wire _T_1426 = ~a_ff[31]; // @[lib.scala 428:40]
wire _T_1428 = _T_1424 ? _T_1426 : a_ff[31]; // @[lib.scala 428:23]
wire [6:0] _T_1434 = {_T_1284,_T_1278,_T_1272,_T_1266,_T_1260,_T_1254,_T_1248}; // @[lib.scala 430:14]
wire [14:0] _T_1442 = {_T_1332,_T_1326,_T_1320,_T_1314,_T_1308,_T_1302,_T_1296,_T_1290,_T_1434}; // @[lib.scala 430:14]
wire [7:0] _T_1449 = {_T_1380,_T_1374,_T_1368,_T_1362,_T_1356,_T_1350,_T_1344,_T_1338}; // @[lib.scala 430:14]
wire [30:0] _T_1458 = {_T_1428,_T_1422,_T_1416,_T_1410,_T_1404,_T_1398,_T_1392,_T_1386,_T_1449,_T_1442}; // @[lib.scala 430:14]
wire [31:0] _T_1460 = {_T_1458,a_ff[0]}; // @[Cat.scala 29:58]
wire [31:0] a_ff_eff = _T_743 ? _T_1460 : a_ff[31:0]; // @[exu_div_ctl.scala 259:21]
reg smallnum_case_ff; // @[Reg.scala 27:20]
reg [3:0] smallnum_ff; // @[Reg.scala 27:20]
wire [31:0] _T_1463 = {28'h0,smallnum_ff}; // @[Cat.scala 29:58]
wire _T_1465 = ~smallnum_case_ff; // @[exu_div_ctl.scala 264:6]
wire _T_1467 = _T_1465 & _T_9; // @[exu_div_ctl.scala 264:24]
wire [31:0] _T_1469 = smallnum_case_ff ? _T_1463 : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_1470 = rem_ff ? a_ff_eff : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_1471 = _T_1467 ? q_ff_eff : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_1472 = _T_1469 | _T_1470; // @[Mux.scala 27:72]
wire _T_1476 = io_valid_in & _T; // @[exu_div_ctl.scala 266:38]
wire _T_1480 = finish & _T; // @[exu_div_ctl.scala 267:32]
wire _T_1488 = io_valid_in & io_dividend_in[31]; // @[exu_div_ctl.scala 270:44]
wire _T_1489 = ~io_valid_in; // @[exu_div_ctl.scala 270:69]
wire _T_1490 = _T_1489 & dividend_neg_ff; // @[exu_div_ctl.scala 270:82]
wire _T_1491 = _T_1488 | _T_1490; // @[exu_div_ctl.scala 270:66]
wire _T_1495 = io_valid_in & io_divisor_in[31]; // @[exu_div_ctl.scala 271:43]
wire _T_1497 = _T_1489 & divisor_neg_ff; // @[exu_div_ctl.scala 271:80]
wire _T_1498 = _T_1495 | _T_1497; // @[exu_div_ctl.scala 271:64]
wire _T_1501 = io_valid_in & sign_eff; // @[exu_div_ctl.scala 272:36]
wire _T_1503 = _T_1489 & sign_ff; // @[exu_div_ctl.scala 272:64]
wire _T_1504 = _T_1501 | _T_1503; // @[exu_div_ctl.scala 272:48]
wire _T_1507 = io_valid_in & io_rem_in; // @[exu_div_ctl.scala 273:35]
wire _T_1509 = _T_1489 & rem_ff; // @[exu_div_ctl.scala 273:64]
wire _T_1510 = _T_1507 | _T_1509; // @[exu_div_ctl.scala 273:48]
wire [32:0] q_in = _T_739[32:0]; // @[exu_div_ctl.scala 237:8]
wire _T_1526 = io_signed_in & io_divisor_in[31]; // @[exu_div_ctl.scala 281:35]
wire [32:0] _T_1528 = {_T_1526,io_divisor_in}; // @[Cat.scala 29:58]
rvclkhdr rvclkhdr ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_io_clk),
.io_en(rvclkhdr_io_en)
);
rvclkhdr rvclkhdr_1 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_1_io_clk),
.io_en(rvclkhdr_1_io_en)
);
rvclkhdr rvclkhdr_2 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_2_io_clk),
.io_en(rvclkhdr_2_io_en)
);
rvclkhdr rvclkhdr_3 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_3_io_clk),
.io_en(rvclkhdr_3_io_en)
);
rvclkhdr rvclkhdr_4 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_4_io_clk),
.io_en(rvclkhdr_4_io_en)
);
rvclkhdr rvclkhdr_5 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_5_io_clk),
.io_en(rvclkhdr_5_io_en)
);
rvclkhdr rvclkhdr_6 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_6_io_clk),
.io_en(rvclkhdr_6_io_en)
);
rvclkhdr rvclkhdr_7 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_7_io_clk),
.io_en(rvclkhdr_7_io_en)
);
rvclkhdr rvclkhdr_8 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_8_io_clk),
.io_en(rvclkhdr_8_io_en)
);
rvclkhdr rvclkhdr_9 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_9_io_clk),
.io_en(rvclkhdr_9_io_en)
);
rvclkhdr rvclkhdr_10 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_10_io_clk),
.io_en(rvclkhdr_10_io_en)
);
rvclkhdr rvclkhdr_11 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_11_io_clk),
.io_en(rvclkhdr_11_io_en)
);
rvclkhdr rvclkhdr_12 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_12_io_clk),
.io_en(rvclkhdr_12_io_en)
);
rvclkhdr rvclkhdr_13 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_13_io_clk),
.io_en(rvclkhdr_13_io_en)
);
rvclkhdr rvclkhdr_14 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_14_io_clk),
.io_en(rvclkhdr_14_io_en)
);
assign io_data_out = _T_1472 | _T_1471; // @[exu_div_ctl.scala 261:15]
assign io_valid_out = finish_ff & _T; // @[exu_div_ctl.scala 234:17]
assign rvclkhdr_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_io_en = _T_692 | finish_ff; // @[lib.scala 393:17]
assign rvclkhdr_1_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_1_io_en = _T_692 | finish_ff; // @[lib.scala 393:17]
assign rvclkhdr_2_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_2_io_en = _T_692 | finish_ff; // @[lib.scala 393:17]
assign rvclkhdr_3_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_3_io_en = _T_692 | finish_ff; // @[lib.scala 393:17]
assign rvclkhdr_4_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_4_io_en = _T_692 | finish_ff; // @[lib.scala 393:17]
assign rvclkhdr_5_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_5_io_en = _T_692 | finish_ff; // @[lib.scala 393:17]
assign rvclkhdr_6_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_6_io_en = _T_692 | finish_ff; // @[lib.scala 393:17]
assign rvclkhdr_7_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_7_io_en = _T_692 | finish_ff; // @[lib.scala 393:17]
assign rvclkhdr_8_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_8_io_en = _T_692 | finish_ff; // @[lib.scala 393:17]
assign rvclkhdr_9_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_9_io_en = _T_692 | finish_ff; // @[lib.scala 393:17]
assign rvclkhdr_10_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_10_io_en = _T_692 | finish_ff; // @[lib.scala 393:17]
assign rvclkhdr_11_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_11_io_en = _T_692 | finish_ff; // @[lib.scala 393:17]
assign rvclkhdr_12_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_12_io_en = io_valid_in | _T_742; // @[lib.scala 393:17]
assign rvclkhdr_13_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_13_io_en = _T_995 | rem_correct; // @[lib.scala 393:17]
assign rvclkhdr_14_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_14_io_en = io_valid_in; // @[lib.scala 393:17]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
valid_ff_x = _RAND_0[0:0];
_RAND_1 = {2{`RANDOM}};
q_ff = _RAND_1[32:0];
_RAND_2 = {2{`RANDOM}};
m_ff = _RAND_2[32:0];
_RAND_3 = {1{`RANDOM}};
rem_ff = _RAND_3[0:0];
_RAND_4 = {1{`RANDOM}};
sign_ff = _RAND_4[0:0];
_RAND_5 = {1{`RANDOM}};
_T_1520 = _RAND_5[5:0];
_RAND_6 = {1{`RANDOM}};
count = _RAND_6[5:0];
_RAND_7 = {1{`RANDOM}};
run_state = _RAND_7[0:0];
_RAND_8 = {1{`RANDOM}};
finish_ff = _RAND_8[0:0];
_RAND_9 = {1{`RANDOM}};
shortq_enable_ff = _RAND_9[0:0];
_RAND_10 = {1{`RANDOM}};
dividend_neg_ff = _RAND_10[0:0];
_RAND_11 = {2{`RANDOM}};
a_ff = _RAND_11[32:0];
_RAND_12 = {1{`RANDOM}};
divisor_neg_ff = _RAND_12[0:0];
_RAND_13 = {1{`RANDOM}};
smallnum_case_ff = _RAND_13[0:0];
_RAND_14 = {1{`RANDOM}};
smallnum_ff = _RAND_14[3:0];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
valid_ff_x = 1'h0;
end
if (reset) begin
q_ff = 33'h0;
end
if (reset) begin
m_ff = 33'h0;
end
if (reset) begin
rem_ff = 1'h0;
end
if (reset) begin
sign_ff = 1'h0;
end
if (reset) begin
_T_1520 = 6'h0;
end
if (reset) begin
count = 6'h0;
end
if (reset) begin
run_state = 1'h0;
end
if (reset) begin
finish_ff = 1'h0;
end
if (reset) begin
shortq_enable_ff = 1'h0;
end
if (reset) begin
dividend_neg_ff = 1'h0;
end
if (reset) begin
a_ff = 33'h0;
end
if (reset) begin
divisor_neg_ff = 1'h0;
end
if (reset) begin
smallnum_case_ff = 1'h0;
end
if (reset) begin
smallnum_ff = 4'h0;
end
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
always @(posedge clock or posedge reset) begin
if (reset) begin
valid_ff_x <= 1'h0;
end else if (div_clken) begin
valid_ff_x <= _T_1476;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
q_ff <= 33'h0;
end else if (qff_enable) begin
q_ff <= q_in;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
m_ff <= 33'h0;
end else if (io_valid_in) begin
m_ff <= _T_1528;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
rem_ff <= 1'h0;
end else if (div_clken) begin
rem_ff <= _T_1510;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
sign_ff <= 1'h0;
end else if (div_clken) begin
sign_ff <= _T_1504;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
_T_1520 <= 6'h0;
end else if (div_clken) begin
_T_1520 <= shortq_shift;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
count <= 6'h0;
end else if (div_clken) begin
count <= count_in;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
run_state <= 1'h0;
end else if (div_clken) begin
run_state <= run_in;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
finish_ff <= 1'h0;
end else if (div_clken) begin
finish_ff <= _T_1480;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
shortq_enable_ff <= 1'h0;
end else if (div_clken) begin
shortq_enable_ff <= shortq_enable;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
dividend_neg_ff <= 1'h0;
end else if (div_clken) begin
dividend_neg_ff <= _T_1491;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
a_ff <= 33'h0;
end else if (aff_enable) begin
a_ff <= a_in;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
divisor_neg_ff <= 1'h0;
end else if (div_clken) begin
divisor_neg_ff <= _T_1498;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
smallnum_case_ff <= 1'h0;
end else if (div_clken) begin
smallnum_case_ff <= smallnum_case;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
smallnum_ff <= 4'h0;
end else if (div_clken) begin
smallnum_ff <= smallnum;
end
end
endmodule

30
el2_exu_div_new_1bit_fullshortq.anno.json Normal file
View File

@ -0,0 +1,30 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_exu_div_new_1bit_fullshortq|el2_exu_div_new_1bit_fullshortq>io_valid_out",
"sources":[
"~el2_exu_div_new_1bit_fullshortq|el2_exu_div_new_1bit_fullshortq>io_cancel"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"el2_exu_div_new_1bit_fullshortq.gated_latch",
"resourceId":"/vsrc/gated_latch.sv"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"el2_exu_div_new_1bit_fullshortq"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

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el2_exu_div_new_1bit_fullshortq.fir Normal file
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el2_exu_div_new_1bit_fullshortq.v Normal file
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module el2_exu_div_cls(
input [32:0] io_operand,
output [4:0] io_cls
);
wire _T_3 = io_operand[31:30] == 2'h1; // @[exu_div_ctl.scala 511:63]
wire _T_5 = io_operand[31:29] == 3'h1; // @[exu_div_ctl.scala 511:63]
wire _T_7 = io_operand[31:28] == 4'h1; // @[exu_div_ctl.scala 511:63]
wire _T_9 = io_operand[31:27] == 5'h1; // @[exu_div_ctl.scala 511:63]
wire _T_11 = io_operand[31:26] == 6'h1; // @[exu_div_ctl.scala 511:63]
wire _T_13 = io_operand[31:25] == 7'h1; // @[exu_div_ctl.scala 511:63]
wire _T_15 = io_operand[31:24] == 8'h1; // @[exu_div_ctl.scala 511:63]
wire _T_17 = io_operand[31:23] == 9'h1; // @[exu_div_ctl.scala 511:63]
wire _T_19 = io_operand[31:22] == 10'h1; // @[exu_div_ctl.scala 511:63]
wire _T_21 = io_operand[31:21] == 11'h1; // @[exu_div_ctl.scala 511:63]
wire _T_23 = io_operand[31:20] == 12'h1; // @[exu_div_ctl.scala 511:63]
wire _T_25 = io_operand[31:19] == 13'h1; // @[exu_div_ctl.scala 511:63]
wire _T_27 = io_operand[31:18] == 14'h1; // @[exu_div_ctl.scala 511:63]
wire _T_29 = io_operand[31:17] == 15'h1; // @[exu_div_ctl.scala 511:63]
wire _T_31 = io_operand[31:16] == 16'h1; // @[exu_div_ctl.scala 511:63]
wire _T_33 = io_operand[31:15] == 17'h1; // @[exu_div_ctl.scala 511:63]
wire _T_35 = io_operand[31:14] == 18'h1; // @[exu_div_ctl.scala 511:63]
wire _T_37 = io_operand[31:13] == 19'h1; // @[exu_div_ctl.scala 511:63]
wire _T_39 = io_operand[31:12] == 20'h1; // @[exu_div_ctl.scala 511:63]
wire _T_41 = io_operand[31:11] == 21'h1; // @[exu_div_ctl.scala 511:63]
wire _T_43 = io_operand[31:10] == 22'h1; // @[exu_div_ctl.scala 511:63]
wire _T_45 = io_operand[31:9] == 23'h1; // @[exu_div_ctl.scala 511:63]
wire _T_47 = io_operand[31:8] == 24'h1; // @[exu_div_ctl.scala 511:63]
wire _T_49 = io_operand[31:7] == 25'h1; // @[exu_div_ctl.scala 511:63]
wire _T_51 = io_operand[31:6] == 26'h1; // @[exu_div_ctl.scala 511:63]
wire _T_53 = io_operand[31:5] == 27'h1; // @[exu_div_ctl.scala 511:63]
wire _T_55 = io_operand[31:4] == 28'h1; // @[exu_div_ctl.scala 511:63]
wire _T_57 = io_operand[31:3] == 29'h1; // @[exu_div_ctl.scala 511:63]
wire _T_59 = io_operand[31:2] == 30'h1; // @[exu_div_ctl.scala 511:63]
wire _T_61 = io_operand[31:1] == 31'h1; // @[exu_div_ctl.scala 511:63]
wire _T_63 = io_operand[31:0] == 32'h1; // @[exu_div_ctl.scala 511:63]
wire [1:0] _T_66 = _T_5 ? 2'h2 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_67 = _T_7 ? 2'h3 : 2'h0; // @[Mux.scala 27:72]
wire [2:0] _T_68 = _T_9 ? 3'h4 : 3'h0; // @[Mux.scala 27:72]
wire [2:0] _T_69 = _T_11 ? 3'h5 : 3'h0; // @[Mux.scala 27:72]
wire [2:0] _T_70 = _T_13 ? 3'h6 : 3'h0; // @[Mux.scala 27:72]
wire [2:0] _T_71 = _T_15 ? 3'h7 : 3'h0; // @[Mux.scala 27:72]
wire [3:0] _T_72 = _T_17 ? 4'h8 : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_73 = _T_19 ? 4'h9 : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_74 = _T_21 ? 4'ha : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_75 = _T_23 ? 4'hb : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_76 = _T_25 ? 4'hc : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_77 = _T_27 ? 4'hd : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_78 = _T_29 ? 4'he : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_79 = _T_31 ? 4'hf : 4'h0; // @[Mux.scala 27:72]
wire [4:0] _T_80 = _T_33 ? 5'h10 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_81 = _T_35 ? 5'h11 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_82 = _T_37 ? 5'h12 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_83 = _T_39 ? 5'h13 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_84 = _T_41 ? 5'h14 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_85 = _T_43 ? 5'h15 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_86 = _T_45 ? 5'h16 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_87 = _T_47 ? 5'h17 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_88 = _T_49 ? 5'h18 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_89 = _T_51 ? 5'h19 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_90 = _T_53 ? 5'h1a : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_91 = _T_55 ? 5'h1b : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_92 = _T_57 ? 5'h1c : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_93 = _T_59 ? 5'h1d : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_94 = _T_61 ? 5'h1e : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_95 = _T_63 ? 5'h1f : 5'h0; // @[Mux.scala 27:72]
wire [1:0] _GEN_1 = {{1'd0}, _T_3}; // @[Mux.scala 27:72]
wire [1:0] _T_97 = _GEN_1 | _T_66; // @[Mux.scala 27:72]
wire [1:0] _T_98 = _T_97 | _T_67; // @[Mux.scala 27:72]
wire [2:0] _GEN_2 = {{1'd0}, _T_98}; // @[Mux.scala 27:72]
wire [2:0] _T_99 = _GEN_2 | _T_68; // @[Mux.scala 27:72]
wire [2:0] _T_100 = _T_99 | _T_69; // @[Mux.scala 27:72]
wire [2:0] _T_101 = _T_100 | _T_70; // @[Mux.scala 27:72]
wire [2:0] _T_102 = _T_101 | _T_71; // @[Mux.scala 27:72]
wire [3:0] _GEN_3 = {{1'd0}, _T_102}; // @[Mux.scala 27:72]
wire [3:0] _T_103 = _GEN_3 | _T_72; // @[Mux.scala 27:72]
wire [3:0] _T_104 = _T_103 | _T_73; // @[Mux.scala 27:72]
wire [3:0] _T_105 = _T_104 | _T_74; // @[Mux.scala 27:72]
wire [3:0] _T_106 = _T_105 | _T_75; // @[Mux.scala 27:72]
wire [3:0] _T_107 = _T_106 | _T_76; // @[Mux.scala 27:72]
wire [3:0] _T_108 = _T_107 | _T_77; // @[Mux.scala 27:72]
wire [3:0] _T_109 = _T_108 | _T_78; // @[Mux.scala 27:72]
wire [3:0] _T_110 = _T_109 | _T_79; // @[Mux.scala 27:72]
wire [4:0] _GEN_4 = {{1'd0}, _T_110}; // @[Mux.scala 27:72]
wire [4:0] _T_111 = _GEN_4 | _T_80; // @[Mux.scala 27:72]
wire [4:0] _T_112 = _T_111 | _T_81; // @[Mux.scala 27:72]
wire [4:0] _T_113 = _T_112 | _T_82; // @[Mux.scala 27:72]
wire [4:0] _T_114 = _T_113 | _T_83; // @[Mux.scala 27:72]
wire [4:0] _T_115 = _T_114 | _T_84; // @[Mux.scala 27:72]
wire [4:0] _T_116 = _T_115 | _T_85; // @[Mux.scala 27:72]
wire [4:0] _T_117 = _T_116 | _T_86; // @[Mux.scala 27:72]
wire [4:0] _T_118 = _T_117 | _T_87; // @[Mux.scala 27:72]
wire [4:0] _T_119 = _T_118 | _T_88; // @[Mux.scala 27:72]
wire [4:0] _T_120 = _T_119 | _T_89; // @[Mux.scala 27:72]
wire [4:0] _T_121 = _T_120 | _T_90; // @[Mux.scala 27:72]
wire [4:0] _T_122 = _T_121 | _T_91; // @[Mux.scala 27:72]
wire [4:0] _T_123 = _T_122 | _T_92; // @[Mux.scala 27:72]
wire [4:0] _T_124 = _T_123 | _T_93; // @[Mux.scala 27:72]
wire [4:0] _T_125 = _T_124 | _T_94; // @[Mux.scala 27:72]
wire [4:0] cls_zeros = _T_125 | _T_95; // @[Mux.scala 27:72]
wire _T_128 = io_operand == 33'hffffffff; // @[exu_div_ctl.scala 513:19]
wire _T_136 = io_operand[31:29] == 3'h6; // @[exu_div_ctl.scala 514:76]
wire _T_141 = io_operand[31:28] == 4'he; // @[exu_div_ctl.scala 514:76]
wire _T_146 = io_operand[31:27] == 5'h1e; // @[exu_div_ctl.scala 514:76]
wire _T_151 = io_operand[31:26] == 6'h3e; // @[exu_div_ctl.scala 514:76]
wire _T_156 = io_operand[31:25] == 7'h7e; // @[exu_div_ctl.scala 514:76]
wire _T_161 = io_operand[31:24] == 8'hfe; // @[exu_div_ctl.scala 514:76]
wire _T_166 = io_operand[31:23] == 9'h1fe; // @[exu_div_ctl.scala 514:76]
wire _T_171 = io_operand[31:22] == 10'h3fe; // @[exu_div_ctl.scala 514:76]
wire _T_176 = io_operand[31:21] == 11'h7fe; // @[exu_div_ctl.scala 514:76]
wire _T_181 = io_operand[31:20] == 12'hffe; // @[exu_div_ctl.scala 514:76]
wire _T_186 = io_operand[31:19] == 13'h1ffe; // @[exu_div_ctl.scala 514:76]
wire _T_191 = io_operand[31:18] == 14'h3ffe; // @[exu_div_ctl.scala 514:76]
wire _T_196 = io_operand[31:17] == 15'h7ffe; // @[exu_div_ctl.scala 514:76]
wire _T_201 = io_operand[31:16] == 16'hfffe; // @[exu_div_ctl.scala 514:76]
wire _T_206 = io_operand[31:15] == 17'h1fffe; // @[exu_div_ctl.scala 514:76]
wire _T_211 = io_operand[31:14] == 18'h3fffe; // @[exu_div_ctl.scala 514:76]
wire _T_216 = io_operand[31:13] == 19'h7fffe; // @[exu_div_ctl.scala 514:76]
wire _T_221 = io_operand[31:12] == 20'hffffe; // @[exu_div_ctl.scala 514:76]
wire _T_226 = io_operand[31:11] == 21'h1ffffe; // @[exu_div_ctl.scala 514:76]
wire _T_231 = io_operand[31:10] == 22'h3ffffe; // @[exu_div_ctl.scala 514:76]
wire _T_236 = io_operand[31:9] == 23'h7ffffe; // @[exu_div_ctl.scala 514:76]
wire _T_241 = io_operand[31:8] == 24'hfffffe; // @[exu_div_ctl.scala 514:76]
wire _T_246 = io_operand[31:7] == 25'h1fffffe; // @[exu_div_ctl.scala 514:76]
wire _T_251 = io_operand[31:6] == 26'h3fffffe; // @[exu_div_ctl.scala 514:76]
wire _T_256 = io_operand[31:5] == 27'h7fffffe; // @[exu_div_ctl.scala 514:76]
wire _T_261 = io_operand[31:4] == 28'hffffffe; // @[exu_div_ctl.scala 514:76]
wire _T_266 = io_operand[31:3] == 29'h1ffffffe; // @[exu_div_ctl.scala 514:76]
wire _T_271 = io_operand[31:2] == 30'h3ffffffe; // @[exu_div_ctl.scala 514:76]
wire _T_276 = io_operand[31:1] == 31'h7ffffffe; // @[exu_div_ctl.scala 514:76]
wire _T_281 = io_operand[31:0] == 32'hfffffffe; // @[exu_div_ctl.scala 514:76]
wire [1:0] _T_285 = _T_141 ? 2'h2 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_286 = _T_146 ? 2'h3 : 2'h0; // @[Mux.scala 27:72]
wire [2:0] _T_287 = _T_151 ? 3'h4 : 3'h0; // @[Mux.scala 27:72]
wire [2:0] _T_288 = _T_156 ? 3'h5 : 3'h0; // @[Mux.scala 27:72]
wire [2:0] _T_289 = _T_161 ? 3'h6 : 3'h0; // @[Mux.scala 27:72]
wire [2:0] _T_290 = _T_166 ? 3'h7 : 3'h0; // @[Mux.scala 27:72]
wire [3:0] _T_291 = _T_171 ? 4'h8 : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_292 = _T_176 ? 4'h9 : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_293 = _T_181 ? 4'ha : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_294 = _T_186 ? 4'hb : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_295 = _T_191 ? 4'hc : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_296 = _T_196 ? 4'hd : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_297 = _T_201 ? 4'he : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_298 = _T_206 ? 4'hf : 4'h0; // @[Mux.scala 27:72]
wire [4:0] _T_299 = _T_211 ? 5'h10 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_300 = _T_216 ? 5'h11 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_301 = _T_221 ? 5'h12 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_302 = _T_226 ? 5'h13 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_303 = _T_231 ? 5'h14 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_304 = _T_236 ? 5'h15 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_305 = _T_241 ? 5'h16 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_306 = _T_246 ? 5'h17 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_307 = _T_251 ? 5'h18 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_308 = _T_256 ? 5'h19 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_309 = _T_261 ? 5'h1a : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_310 = _T_266 ? 5'h1b : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_311 = _T_271 ? 5'h1c : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_312 = _T_276 ? 5'h1d : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_313 = _T_281 ? 5'h1e : 5'h0; // @[Mux.scala 27:72]
wire [1:0] _GEN_5 = {{1'd0}, _T_136}; // @[Mux.scala 27:72]
wire [1:0] _T_315 = _GEN_5 | _T_285; // @[Mux.scala 27:72]
wire [1:0] _T_316 = _T_315 | _T_286; // @[Mux.scala 27:72]
wire [2:0] _GEN_6 = {{1'd0}, _T_316}; // @[Mux.scala 27:72]
wire [2:0] _T_317 = _GEN_6 | _T_287; // @[Mux.scala 27:72]
wire [2:0] _T_318 = _T_317 | _T_288; // @[Mux.scala 27:72]
wire [2:0] _T_319 = _T_318 | _T_289; // @[Mux.scala 27:72]
wire [2:0] _T_320 = _T_319 | _T_290; // @[Mux.scala 27:72]
wire [3:0] _GEN_7 = {{1'd0}, _T_320}; // @[Mux.scala 27:72]
wire [3:0] _T_321 = _GEN_7 | _T_291; // @[Mux.scala 27:72]
wire [3:0] _T_322 = _T_321 | _T_292; // @[Mux.scala 27:72]
wire [3:0] _T_323 = _T_322 | _T_293; // @[Mux.scala 27:72]
wire [3:0] _T_324 = _T_323 | _T_294; // @[Mux.scala 27:72]
wire [3:0] _T_325 = _T_324 | _T_295; // @[Mux.scala 27:72]
wire [3:0] _T_326 = _T_325 | _T_296; // @[Mux.scala 27:72]
wire [3:0] _T_327 = _T_326 | _T_297; // @[Mux.scala 27:72]
wire [3:0] _T_328 = _T_327 | _T_298; // @[Mux.scala 27:72]
wire [4:0] _GEN_8 = {{1'd0}, _T_328}; // @[Mux.scala 27:72]
wire [4:0] _T_329 = _GEN_8 | _T_299; // @[Mux.scala 27:72]
wire [4:0] _T_330 = _T_329 | _T_300; // @[Mux.scala 27:72]
wire [4:0] _T_331 = _T_330 | _T_301; // @[Mux.scala 27:72]
wire [4:0] _T_332 = _T_331 | _T_302; // @[Mux.scala 27:72]
wire [4:0] _T_333 = _T_332 | _T_303; // @[Mux.scala 27:72]
wire [4:0] _T_334 = _T_333 | _T_304; // @[Mux.scala 27:72]
wire [4:0] _T_335 = _T_334 | _T_305; // @[Mux.scala 27:72]
wire [4:0] _T_336 = _T_335 | _T_306; // @[Mux.scala 27:72]
wire [4:0] _T_337 = _T_336 | _T_307; // @[Mux.scala 27:72]
wire [4:0] _T_338 = _T_337 | _T_308; // @[Mux.scala 27:72]
wire [4:0] _T_339 = _T_338 | _T_309; // @[Mux.scala 27:72]
wire [4:0] _T_340 = _T_339 | _T_310; // @[Mux.scala 27:72]
wire [4:0] _T_341 = _T_340 | _T_311; // @[Mux.scala 27:72]
wire [4:0] _T_342 = _T_341 | _T_312; // @[Mux.scala 27:72]
wire [4:0] _T_343 = _T_342 | _T_313; // @[Mux.scala 27:72]
wire [4:0] cls_ones = _T_128 ? 5'h1f : _T_343; // @[exu_div_ctl.scala 513:38]
assign io_cls = io_operand[32] ? cls_ones : cls_zeros; // @[exu_div_ctl.scala 515:10]
endmodule
module rvclkhdr(
input io_clk,
input io_en
);
wire clkhdr_Q; // @[lib.scala 334:26]
wire clkhdr_CK; // @[lib.scala 334:26]
wire clkhdr_EN; // @[lib.scala 334:26]
wire clkhdr_SE; // @[lib.scala 334:26]
gated_latch clkhdr ( // @[lib.scala 334:26]
.Q(clkhdr_Q),
.CK(clkhdr_CK),
.EN(clkhdr_EN),
.SE(clkhdr_SE)
);
assign clkhdr_CK = io_clk; // @[lib.scala 336:18]
assign clkhdr_EN = io_en; // @[lib.scala 337:18]
assign clkhdr_SE = 1'h0; // @[lib.scala 338:18]
endmodule
module el2_exu_div_new_1bit_fullshortq(
input clock,
input reset,
input io_scan_mode,
input io_cancel,
input io_valid_in,
input io_signed_in,
input io_rem_in,
input [31:0] io_dividend_in,
input [31:0] io_divisor_in,
output [31:0] io_data_out,
output io_valid_out
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [63:0] _RAND_1;
reg [31:0] _RAND_2;
reg [31:0] _RAND_3;
reg [31:0] _RAND_4;
reg [31:0] _RAND_5;
reg [31:0] _RAND_6;
reg [31:0] _RAND_7;
reg [31:0] _RAND_8;
reg [31:0] _RAND_9;
reg [31:0] _RAND_10;
`endif // RANDOMIZE_REG_INIT
wire [32:0] a_enc_io_operand; // @[exu_div_ctl.scala 429:21]
wire [4:0] a_enc_io_cls; // @[exu_div_ctl.scala 429:21]
wire [32:0] b_enc_io_operand; // @[exu_div_ctl.scala 432:21]
wire [4:0] b_enc_io_cls; // @[exu_div_ctl.scala 432:21]
wire rvclkhdr_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_io_en; // @[lib.scala 390:23]
wire rvclkhdr_1_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_1_io_en; // @[lib.scala 390:23]
wire rvclkhdr_2_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_2_io_en; // @[lib.scala 390:23]
wire rvclkhdr_3_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_3_io_en; // @[lib.scala 390:23]
wire rvclkhdr_4_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_4_io_en; // @[lib.scala 390:23]
wire rvclkhdr_5_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_5_io_en; // @[lib.scala 390:23]
wire rvclkhdr_6_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_6_io_en; // @[lib.scala 390:23]
wire rvclkhdr_7_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_7_io_en; // @[lib.scala 390:23]
wire rvclkhdr_8_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_8_io_en; // @[lib.scala 390:23]
wire rvclkhdr_9_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_9_io_en; // @[lib.scala 390:23]
wire rvclkhdr_10_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_10_io_en; // @[lib.scala 390:23]
reg [2:0] control_ff; // @[Reg.scala 27:20]
wire dividend_sign_ff = control_ff[2]; // @[exu_div_ctl.scala 343:40]
wire divisor_sign_ff = control_ff[1]; // @[exu_div_ctl.scala 344:40]
wire rem_ff = control_ff[0]; // @[exu_div_ctl.scala 345:40]
reg [32:0] b_ff; // @[Reg.scala 27:20]
wire _T_1 = b_ff[31:0] == 32'h0; // @[exu_div_ctl.scala 346:54]
reg valid_ff; // @[Reg.scala 27:20]
wire by_zero_case = valid_ff & _T_1; // @[exu_div_ctl.scala 346:40]
reg [31:0] a_ff; // @[Reg.scala 27:20]
wire _T_3 = a_ff[31:4] == 28'h0; // @[exu_div_ctl.scala 347:37]
wire _T_5 = b_ff[31:4] == 28'h0; // @[exu_div_ctl.scala 347:60]
wire _T_6 = _T_3 & _T_5; // @[exu_div_ctl.scala 347:46]
wire _T_7 = ~by_zero_case; // @[exu_div_ctl.scala 347:71]
wire _T_8 = _T_6 & _T_7; // @[exu_div_ctl.scala 347:69]
wire _T_9 = ~rem_ff; // @[exu_div_ctl.scala 347:87]
wire _T_10 = _T_8 & _T_9; // @[exu_div_ctl.scala 347:85]
wire _T_11 = _T_10 & valid_ff; // @[exu_div_ctl.scala 347:95]
wire _T_12 = ~io_cancel; // @[exu_div_ctl.scala 347:108]
wire _T_13 = _T_11 & _T_12; // @[exu_div_ctl.scala 347:106]
wire _T_15 = a_ff == 32'h0; // @[exu_div_ctl.scala 348:18]
wire _T_17 = _T_15 & _T_7; // @[exu_div_ctl.scala 348:27]
wire _T_19 = _T_17 & _T_9; // @[exu_div_ctl.scala 348:43]
wire _T_20 = _T_19 & valid_ff; // @[exu_div_ctl.scala 348:53]
wire _T_22 = _T_20 & _T_12; // @[exu_div_ctl.scala 348:64]
wire smallnum_case = _T_13 | _T_22; // @[exu_div_ctl.scala 347:120]
wire valid_ff_in = io_valid_in & _T_12; // @[exu_div_ctl.scala 349:43]
wire _T_24 = ~io_valid_in; // @[exu_div_ctl.scala 350:35]
wire _T_26 = _T_24 & dividend_sign_ff; // @[exu_div_ctl.scala 350:48]
wire _T_27 = io_valid_in & io_signed_in; // @[exu_div_ctl.scala 350:80]
wire _T_29 = _T_27 & io_dividend_in[31]; // @[exu_div_ctl.scala 350:96]
wire _T_30 = _T_26 | _T_29; // @[exu_div_ctl.scala 350:65]
wire _T_33 = _T_24 & divisor_sign_ff; // @[exu_div_ctl.scala 350:133]
wire _T_36 = _T_27 & io_divisor_in[31]; // @[exu_div_ctl.scala 350:181]
wire _T_37 = _T_33 | _T_36; // @[exu_div_ctl.scala 350:150]
wire _T_40 = _T_24 & rem_ff; // @[exu_div_ctl.scala 350:218]
wire _T_41 = io_valid_in & io_rem_in; // @[exu_div_ctl.scala 350:250]
wire _T_42 = _T_40 | _T_41; // @[exu_div_ctl.scala 350:235]
wire [2:0] control_in = {_T_30,_T_37,_T_42}; // @[Cat.scala 29:58]
reg [6:0] count_ff; // @[Reg.scala 27:20]
wire _T_44 = |count_ff; // @[exu_div_ctl.scala 351:42]
reg shortq_enable_ff; // @[Reg.scala 27:20]
wire running_state = _T_44 | shortq_enable_ff; // @[exu_div_ctl.scala 351:45]
wire _T_45 = io_valid_in | valid_ff; // @[exu_div_ctl.scala 352:43]
wire _T_46 = _T_45 | io_cancel; // @[exu_div_ctl.scala 352:54]
wire _T_47 = _T_46 | running_state; // @[exu_div_ctl.scala 352:66]
reg finish_ff; // @[Reg.scala 27:20]
wire misc_enable = _T_47 | finish_ff; // @[exu_div_ctl.scala 352:82]
wire _T_48 = smallnum_case | by_zero_case; // @[exu_div_ctl.scala 353:45]
wire _T_49 = count_ff == 7'h20; // @[exu_div_ctl.scala 353:72]
wire finish_raw = _T_48 | _T_49; // @[exu_div_ctl.scala 353:60]
wire finish = finish_raw & _T_12; // @[exu_div_ctl.scala 354:41]
wire _T_51 = valid_ff | running_state; // @[exu_div_ctl.scala 355:40]
wire _T_52 = ~finish; // @[exu_div_ctl.scala 355:59]
wire _T_53 = _T_51 & _T_52; // @[exu_div_ctl.scala 355:57]
wire _T_54 = ~finish_ff; // @[exu_div_ctl.scala 355:69]
wire _T_55 = _T_53 & _T_54; // @[exu_div_ctl.scala 355:67]
wire _T_57 = _T_55 & _T_12; // @[exu_div_ctl.scala 355:80]
wire [6:0] _T_841 = {1'h0,1'h0,b_enc_io_cls}; // @[Cat.scala 29:58]
wire [6:0] _T_842 = {1'h0,1'h0,a_enc_io_cls}; // @[Cat.scala 29:58]
wire [6:0] _T_844 = _T_841 - _T_842; // @[exu_div_ctl.scala 437:41]
wire [7:0] _T_847 = {{1'd0}, _T_844}; // @[exu_div_ctl.scala 437:61]
wire [6:0] dw_shortq_raw = _T_847[6:0]; // @[exu_div_ctl.scala 437:61]
wire [5:0] shortq = dw_shortq_raw[6] ? 6'h0 : dw_shortq_raw[5:0]; // @[exu_div_ctl.scala 438:19]
wire _T_852 = ~shortq[5]; // @[exu_div_ctl.scala 439:31]
wire _T_853 = valid_ff & _T_852; // @[exu_div_ctl.scala 439:29]
wire _T_855 = shortq[4:1] == 4'hf; // @[exu_div_ctl.scala 439:58]
wire _T_856 = ~_T_855; // @[exu_div_ctl.scala 439:44]
wire _T_857 = _T_853 & _T_856; // @[exu_div_ctl.scala 439:42]
wire shortq_enable = _T_857 & _T_12; // @[exu_div_ctl.scala 439:74]
wire _T_58 = ~shortq_enable; // @[exu_div_ctl.scala 355:95]
wire count_enable = _T_57 & _T_58; // @[exu_div_ctl.scala 355:93]
wire [6:0] _T_60 = count_enable ? 7'h7f : 7'h0; // @[Bitwise.scala 72:12]
wire [6:0] _T_63 = count_ff + 7'h1; // @[exu_div_ctl.scala 356:63]
reg [4:0] shortq_shift_ff; // @[Reg.scala 27:20]
wire [6:0] _T_64 = {2'h0,shortq_shift_ff}; // @[Cat.scala 29:58]
wire [6:0] _T_66 = _T_63 + _T_64; // @[exu_div_ctl.scala 356:83]
wire [6:0] count_in = _T_60 & _T_66; // @[exu_div_ctl.scala 356:51]
wire a_enable = io_valid_in | running_state; // @[exu_div_ctl.scala 357:43]
wire _T_67 = ~shortq_enable_ff; // @[exu_div_ctl.scala 358:47]
wire a_shift = running_state & _T_67; // @[exu_div_ctl.scala 358:45]
wire [31:0] _T_69 = dividend_sign_ff ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
wire [63:0] _T_70 = {_T_69,a_ff}; // @[Cat.scala 29:58]
wire [94:0] _GEN_11 = {{31'd0}, _T_70}; // @[exu_div_ctl.scala 359:68]
wire [94:0] _T_71 = _GEN_11 << shortq_shift_ff; // @[exu_div_ctl.scala 359:68]
wire _T_72 = dividend_sign_ff ^ divisor_sign_ff; // @[exu_div_ctl.scala 360:61]
wire _T_73 = ~_T_72; // @[exu_div_ctl.scala 360:42]
wire b_twos_comp = valid_ff & _T_73; // @[exu_div_ctl.scala 360:40]
wire _T_76 = ~valid_ff; // @[exu_div_ctl.scala 362:30]
wire _T_78 = _T_76 & _T_9; // @[exu_div_ctl.scala 362:40]
wire _T_80 = _T_78 & _T_72; // @[exu_div_ctl.scala 362:50]
reg by_zero_case_ff; // @[Reg.scala 27:20]
wire _T_81 = ~by_zero_case_ff; // @[exu_div_ctl.scala 362:92]
wire twos_comp_q_sel = _T_80 & _T_81; // @[exu_div_ctl.scala 362:90]
wire b_enable = io_valid_in | b_twos_comp; // @[exu_div_ctl.scala 363:43]
wire rq_enable = _T_45 | running_state; // @[exu_div_ctl.scala 364:54]
wire _T_83 = valid_ff & dividend_sign_ff; // @[exu_div_ctl.scala 365:40]
wire r_sign_sel = _T_83 & _T_7; // @[exu_div_ctl.scala 365:59]
reg [31:0] r_ff; // @[Reg.scala 27:20]
wire [32:0] _T_360 = {r_ff,a_ff[31]}; // @[Cat.scala 29:58]
wire [32:0] adder_out = _T_360 + b_ff; // @[exu_div_ctl.scala 395:35]
wire _T_364 = ~adder_out[32]; // @[exu_div_ctl.scala 396:20]
wire _T_365 = _T_364 ^ dividend_sign_ff; // @[exu_div_ctl.scala 396:35]
wire _T_367 = a_ff[30:0] == 31'h0; // @[exu_div_ctl.scala 396:70]
wire _T_368 = adder_out == 33'h0; // @[exu_div_ctl.scala 396:92]
wire _T_369 = _T_367 & _T_368; // @[exu_div_ctl.scala 396:79]
wire quotient_set = _T_365 | _T_369; // @[exu_div_ctl.scala 396:55]
wire _T_85 = ~quotient_set; // @[exu_div_ctl.scala 366:47]
wire _T_86 = running_state & _T_85; // @[exu_div_ctl.scala 366:45]
wire r_restore_sel = _T_86 & _T_67; // @[exu_div_ctl.scala 366:61]
wire _T_88 = running_state & quotient_set; // @[exu_div_ctl.scala 367:45]
wire r_adder_sel = _T_88 & _T_67; // @[exu_div_ctl.scala 367:61]
reg [31:0] q_ff; // @[Reg.scala 27:20]
wire [31:0] _T_91 = twos_comp_q_sel ? q_ff : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_92 = b_twos_comp ? b_ff[31:0] : 32'h0; // @[Mux.scala 27:72]
wire [31:0] twos_comp_in = _T_91 | _T_92; // @[Mux.scala 27:72]
wire _T_96 = |twos_comp_in[0]; // @[lib.scala 428:35]
wire _T_98 = ~twos_comp_in[1]; // @[lib.scala 428:40]
wire _T_100 = _T_96 ? _T_98 : twos_comp_in[1]; // @[lib.scala 428:23]
wire _T_102 = |twos_comp_in[1:0]; // @[lib.scala 428:35]
wire _T_104 = ~twos_comp_in[2]; // @[lib.scala 428:40]
wire _T_106 = _T_102 ? _T_104 : twos_comp_in[2]; // @[lib.scala 428:23]
wire _T_108 = |twos_comp_in[2:0]; // @[lib.scala 428:35]
wire _T_110 = ~twos_comp_in[3]; // @[lib.scala 428:40]
wire _T_112 = _T_108 ? _T_110 : twos_comp_in[3]; // @[lib.scala 428:23]
wire _T_114 = |twos_comp_in[3:0]; // @[lib.scala 428:35]
wire _T_116 = ~twos_comp_in[4]; // @[lib.scala 428:40]
wire _T_118 = _T_114 ? _T_116 : twos_comp_in[4]; // @[lib.scala 428:23]
wire _T_120 = |twos_comp_in[4:0]; // @[lib.scala 428:35]
wire _T_122 = ~twos_comp_in[5]; // @[lib.scala 428:40]
wire _T_124 = _T_120 ? _T_122 : twos_comp_in[5]; // @[lib.scala 428:23]
wire _T_126 = |twos_comp_in[5:0]; // @[lib.scala 428:35]
wire _T_128 = ~twos_comp_in[6]; // @[lib.scala 428:40]
wire _T_130 = _T_126 ? _T_128 : twos_comp_in[6]; // @[lib.scala 428:23]
wire _T_132 = |twos_comp_in[6:0]; // @[lib.scala 428:35]
wire _T_134 = ~twos_comp_in[7]; // @[lib.scala 428:40]
wire _T_136 = _T_132 ? _T_134 : twos_comp_in[7]; // @[lib.scala 428:23]
wire _T_138 = |twos_comp_in[7:0]; // @[lib.scala 428:35]
wire _T_140 = ~twos_comp_in[8]; // @[lib.scala 428:40]
wire _T_142 = _T_138 ? _T_140 : twos_comp_in[8]; // @[lib.scala 428:23]
wire _T_144 = |twos_comp_in[8:0]; // @[lib.scala 428:35]
wire _T_146 = ~twos_comp_in[9]; // @[lib.scala 428:40]
wire _T_148 = _T_144 ? _T_146 : twos_comp_in[9]; // @[lib.scala 428:23]
wire _T_150 = |twos_comp_in[9:0]; // @[lib.scala 428:35]
wire _T_152 = ~twos_comp_in[10]; // @[lib.scala 428:40]
wire _T_154 = _T_150 ? _T_152 : twos_comp_in[10]; // @[lib.scala 428:23]
wire _T_156 = |twos_comp_in[10:0]; // @[lib.scala 428:35]
wire _T_158 = ~twos_comp_in[11]; // @[lib.scala 428:40]
wire _T_160 = _T_156 ? _T_158 : twos_comp_in[11]; // @[lib.scala 428:23]
wire _T_162 = |twos_comp_in[11:0]; // @[lib.scala 428:35]
wire _T_164 = ~twos_comp_in[12]; // @[lib.scala 428:40]
wire _T_166 = _T_162 ? _T_164 : twos_comp_in[12]; // @[lib.scala 428:23]
wire _T_168 = |twos_comp_in[12:0]; // @[lib.scala 428:35]
wire _T_170 = ~twos_comp_in[13]; // @[lib.scala 428:40]
wire _T_172 = _T_168 ? _T_170 : twos_comp_in[13]; // @[lib.scala 428:23]
wire _T_174 = |twos_comp_in[13:0]; // @[lib.scala 428:35]
wire _T_176 = ~twos_comp_in[14]; // @[lib.scala 428:40]
wire _T_178 = _T_174 ? _T_176 : twos_comp_in[14]; // @[lib.scala 428:23]
wire _T_180 = |twos_comp_in[14:0]; // @[lib.scala 428:35]
wire _T_182 = ~twos_comp_in[15]; // @[lib.scala 428:40]
wire _T_184 = _T_180 ? _T_182 : twos_comp_in[15]; // @[lib.scala 428:23]
wire _T_186 = |twos_comp_in[15:0]; // @[lib.scala 428:35]
wire _T_188 = ~twos_comp_in[16]; // @[lib.scala 428:40]
wire _T_190 = _T_186 ? _T_188 : twos_comp_in[16]; // @[lib.scala 428:23]
wire _T_192 = |twos_comp_in[16:0]; // @[lib.scala 428:35]
wire _T_194 = ~twos_comp_in[17]; // @[lib.scala 428:40]
wire _T_196 = _T_192 ? _T_194 : twos_comp_in[17]; // @[lib.scala 428:23]
wire _T_198 = |twos_comp_in[17:0]; // @[lib.scala 428:35]
wire _T_200 = ~twos_comp_in[18]; // @[lib.scala 428:40]
wire _T_202 = _T_198 ? _T_200 : twos_comp_in[18]; // @[lib.scala 428:23]
wire _T_204 = |twos_comp_in[18:0]; // @[lib.scala 428:35]
wire _T_206 = ~twos_comp_in[19]; // @[lib.scala 428:40]
wire _T_208 = _T_204 ? _T_206 : twos_comp_in[19]; // @[lib.scala 428:23]
wire _T_210 = |twos_comp_in[19:0]; // @[lib.scala 428:35]
wire _T_212 = ~twos_comp_in[20]; // @[lib.scala 428:40]
wire _T_214 = _T_210 ? _T_212 : twos_comp_in[20]; // @[lib.scala 428:23]
wire _T_216 = |twos_comp_in[20:0]; // @[lib.scala 428:35]
wire _T_218 = ~twos_comp_in[21]; // @[lib.scala 428:40]
wire _T_220 = _T_216 ? _T_218 : twos_comp_in[21]; // @[lib.scala 428:23]
wire _T_222 = |twos_comp_in[21:0]; // @[lib.scala 428:35]
wire _T_224 = ~twos_comp_in[22]; // @[lib.scala 428:40]
wire _T_226 = _T_222 ? _T_224 : twos_comp_in[22]; // @[lib.scala 428:23]
wire _T_228 = |twos_comp_in[22:0]; // @[lib.scala 428:35]
wire _T_230 = ~twos_comp_in[23]; // @[lib.scala 428:40]
wire _T_232 = _T_228 ? _T_230 : twos_comp_in[23]; // @[lib.scala 428:23]
wire _T_234 = |twos_comp_in[23:0]; // @[lib.scala 428:35]
wire _T_236 = ~twos_comp_in[24]; // @[lib.scala 428:40]
wire _T_238 = _T_234 ? _T_236 : twos_comp_in[24]; // @[lib.scala 428:23]
wire _T_240 = |twos_comp_in[24:0]; // @[lib.scala 428:35]
wire _T_242 = ~twos_comp_in[25]; // @[lib.scala 428:40]
wire _T_244 = _T_240 ? _T_242 : twos_comp_in[25]; // @[lib.scala 428:23]
wire _T_246 = |twos_comp_in[25:0]; // @[lib.scala 428:35]
wire _T_248 = ~twos_comp_in[26]; // @[lib.scala 428:40]
wire _T_250 = _T_246 ? _T_248 : twos_comp_in[26]; // @[lib.scala 428:23]
wire _T_252 = |twos_comp_in[26:0]; // @[lib.scala 428:35]
wire _T_254 = ~twos_comp_in[27]; // @[lib.scala 428:40]
wire _T_256 = _T_252 ? _T_254 : twos_comp_in[27]; // @[lib.scala 428:23]
wire _T_258 = |twos_comp_in[27:0]; // @[lib.scala 428:35]
wire _T_260 = ~twos_comp_in[28]; // @[lib.scala 428:40]
wire _T_262 = _T_258 ? _T_260 : twos_comp_in[28]; // @[lib.scala 428:23]
wire _T_264 = |twos_comp_in[28:0]; // @[lib.scala 428:35]
wire _T_266 = ~twos_comp_in[29]; // @[lib.scala 428:40]
wire _T_268 = _T_264 ? _T_266 : twos_comp_in[29]; // @[lib.scala 428:23]
wire _T_270 = |twos_comp_in[29:0]; // @[lib.scala 428:35]
wire _T_272 = ~twos_comp_in[30]; // @[lib.scala 428:40]
wire _T_274 = _T_270 ? _T_272 : twos_comp_in[30]; // @[lib.scala 428:23]
wire _T_276 = |twos_comp_in[30:0]; // @[lib.scala 428:35]
wire _T_278 = ~twos_comp_in[31]; // @[lib.scala 428:40]
wire _T_280 = _T_276 ? _T_278 : twos_comp_in[31]; // @[lib.scala 428:23]
wire [6:0] _T_286 = {_T_136,_T_130,_T_124,_T_118,_T_112,_T_106,_T_100}; // @[lib.scala 430:14]
wire [14:0] _T_294 = {_T_184,_T_178,_T_172,_T_166,_T_160,_T_154,_T_148,_T_142,_T_286}; // @[lib.scala 430:14]
wire [7:0] _T_301 = {_T_232,_T_226,_T_220,_T_214,_T_208,_T_202,_T_196,_T_190}; // @[lib.scala 430:14]
wire [30:0] _T_310 = {_T_280,_T_274,_T_268,_T_262,_T_256,_T_250,_T_244,_T_238,_T_301,_T_294}; // @[lib.scala 430:14]
wire [31:0] twos_comp_out = {_T_310,twos_comp_in[0]}; // @[Cat.scala 29:58]
wire _T_312 = ~a_shift; // @[exu_div_ctl.scala 375:6]
wire _T_314 = _T_312 & _T_67; // @[exu_div_ctl.scala 375:15]
wire [31:0] _T_317 = {a_ff[30:0],1'h0}; // @[Cat.scala 29:58]
wire [63:0] ar_shifted = _T_71[63:0]; // @[exu_div_ctl.scala 359:28]
wire [31:0] _T_319 = _T_314 ? io_dividend_in : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_320 = a_shift ? _T_317 : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_321 = shortq_enable_ff ? ar_shifted[31:0] : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_322 = _T_319 | _T_320; // @[Mux.scala 27:72]
wire [31:0] a_in = _T_322 | _T_321; // @[Mux.scala 27:72]
wire _T_324 = ~b_twos_comp; // @[exu_div_ctl.scala 380:5]
wire _T_326 = io_signed_in & io_divisor_in[31]; // @[exu_div_ctl.scala 380:63]
wire [32:0] _T_328 = {_T_326,io_divisor_in}; // @[Cat.scala 29:58]
wire _T_329 = ~divisor_sign_ff; // @[exu_div_ctl.scala 381:50]
wire [32:0] _T_331 = {_T_329,_T_310,twos_comp_in[0]}; // @[Cat.scala 29:58]
wire [32:0] _T_332 = _T_324 ? _T_328 : 33'h0; // @[Mux.scala 27:72]
wire [32:0] _T_333 = b_twos_comp ? _T_331 : 33'h0; // @[Mux.scala 27:72]
wire [32:0] b_in = _T_332 | _T_333; // @[Mux.scala 27:72]
wire [31:0] _T_337 = {r_ff[30:0],a_ff[31]}; // @[Cat.scala 29:58]
wire [31:0] _T_340 = r_sign_sel ? 32'hffffffff : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_341 = r_restore_sel ? _T_337 : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_342 = r_adder_sel ? adder_out[31:0] : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_343 = shortq_enable_ff ? ar_shifted[63:32] : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_344 = by_zero_case ? a_ff : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_345 = _T_340 | _T_341; // @[Mux.scala 27:72]
wire [31:0] _T_346 = _T_345 | _T_342; // @[Mux.scala 27:72]
wire [31:0] _T_347 = _T_346 | _T_343; // @[Mux.scala 27:72]
wire [31:0] r_in = _T_347 | _T_344; // @[Mux.scala 27:72]
wire [31:0] _T_351 = {q_ff[30:0],quotient_set}; // @[Cat.scala 29:58]
wire _T_385 = ~b_ff[3]; // @[exu_div_ctl.scala 405:70]
wire _T_387 = ~b_ff[2]; // @[exu_div_ctl.scala 405:70]
wire _T_390 = _T_385 & _T_387; // @[exu_div_ctl.scala 405:95]
wire _T_389 = ~b_ff[1]; // @[exu_div_ctl.scala 405:70]
wire _T_391 = _T_390 & _T_389; // @[exu_div_ctl.scala 405:95]
wire _T_392 = a_ff[3] & _T_391; // @[exu_div_ctl.scala 406:11]
wire _T_399 = a_ff[3] & _T_390; // @[exu_div_ctl.scala 406:11]
wire _T_401 = ~b_ff[0]; // @[exu_div_ctl.scala 412:33]
wire _T_402 = _T_399 & _T_401; // @[exu_div_ctl.scala 412:31]
wire _T_412 = a_ff[2] & _T_391; // @[exu_div_ctl.scala 406:11]
wire _T_413 = _T_402 | _T_412; // @[exu_div_ctl.scala 412:42]
wire _T_416 = a_ff[3] & a_ff[2]; // @[exu_div_ctl.scala 404:95]
wire _T_422 = _T_416 & _T_390; // @[exu_div_ctl.scala 406:11]
wire _T_423 = _T_413 | _T_422; // @[exu_div_ctl.scala 412:75]
wire _T_430 = a_ff[2] & _T_390; // @[exu_div_ctl.scala 406:11]
wire _T_433 = _T_430 & _T_401; // @[exu_div_ctl.scala 414:31]
wire _T_443 = a_ff[1] & _T_391; // @[exu_div_ctl.scala 406:11]
wire _T_444 = _T_433 | _T_443; // @[exu_div_ctl.scala 414:42]
wire _T_450 = _T_385 & _T_389; // @[exu_div_ctl.scala 405:95]
wire _T_451 = a_ff[3] & _T_450; // @[exu_div_ctl.scala 406:11]
wire _T_454 = _T_451 & _T_401; // @[exu_div_ctl.scala 414:106]
wire _T_455 = _T_444 | _T_454; // @[exu_div_ctl.scala 414:78]
wire _T_458 = ~a_ff[2]; // @[exu_div_ctl.scala 404:70]
wire _T_459 = a_ff[3] & _T_458; // @[exu_div_ctl.scala 404:95]
wire _T_467 = _T_390 & b_ff[1]; // @[exu_div_ctl.scala 405:95]
wire _T_468 = _T_467 & b_ff[0]; // @[exu_div_ctl.scala 405:95]
wire _T_469 = _T_459 & _T_468; // @[exu_div_ctl.scala 406:11]
wire _T_470 = _T_455 | _T_469; // @[exu_div_ctl.scala 414:117]
wire _T_472 = ~a_ff[3]; // @[exu_div_ctl.scala 404:70]
wire _T_475 = _T_472 & a_ff[2]; // @[exu_div_ctl.scala 404:95]
wire _T_476 = _T_475 & a_ff[1]; // @[exu_div_ctl.scala 404:95]
wire _T_482 = _T_476 & _T_390; // @[exu_div_ctl.scala 406:11]
wire _T_483 = _T_470 | _T_482; // @[exu_div_ctl.scala 415:44]
wire _T_489 = _T_416 & _T_385; // @[exu_div_ctl.scala 406:11]
wire _T_492 = _T_489 & _T_401; // @[exu_div_ctl.scala 415:107]
wire _T_493 = _T_483 | _T_492; // @[exu_div_ctl.scala 415:80]
wire _T_502 = _T_385 & b_ff[2]; // @[exu_div_ctl.scala 405:95]
wire _T_503 = _T_502 & _T_389; // @[exu_div_ctl.scala 405:95]
wire _T_504 = _T_416 & _T_503; // @[exu_div_ctl.scala 406:11]
wire _T_505 = _T_493 | _T_504; // @[exu_div_ctl.scala 415:119]
wire _T_508 = a_ff[3] & a_ff[1]; // @[exu_div_ctl.scala 404:95]
wire _T_514 = _T_508 & _T_450; // @[exu_div_ctl.scala 406:11]
wire _T_515 = _T_505 | _T_514; // @[exu_div_ctl.scala 416:44]
wire _T_520 = _T_416 & a_ff[1]; // @[exu_div_ctl.scala 404:95]
wire _T_525 = _T_520 & _T_502; // @[exu_div_ctl.scala 406:11]
wire _T_526 = _T_515 | _T_525; // @[exu_div_ctl.scala 416:79]
wire _T_530 = a_ff[2] & a_ff[1]; // @[exu_div_ctl.scala 404:95]
wire _T_531 = _T_530 & a_ff[0]; // @[exu_div_ctl.scala 404:95]
wire _T_537 = _T_531 & _T_450; // @[exu_div_ctl.scala 406:11]
wire _T_543 = _T_459 & a_ff[0]; // @[exu_div_ctl.scala 404:95]
wire _T_548 = _T_385 & b_ff[1]; // @[exu_div_ctl.scala 405:95]
wire _T_549 = _T_548 & b_ff[0]; // @[exu_div_ctl.scala 405:95]
wire _T_550 = _T_543 & _T_549; // @[exu_div_ctl.scala 406:11]
wire _T_551 = _T_537 | _T_550; // @[exu_div_ctl.scala 418:45]
wire _T_558 = a_ff[2] & _T_450; // @[exu_div_ctl.scala 406:11]
wire _T_561 = _T_558 & _T_401; // @[exu_div_ctl.scala 418:114]
wire _T_562 = _T_551 | _T_561; // @[exu_div_ctl.scala 418:86]
wire _T_569 = a_ff[1] & _T_390; // @[exu_div_ctl.scala 406:11]
wire _T_572 = _T_569 & _T_401; // @[exu_div_ctl.scala 419:33]
wire _T_573 = _T_562 | _T_572; // @[exu_div_ctl.scala 418:129]
wire _T_583 = a_ff[0] & _T_391; // @[exu_div_ctl.scala 406:11]
wire _T_584 = _T_573 | _T_583; // @[exu_div_ctl.scala 419:47]
wire _T_589 = ~a_ff[1]; // @[exu_div_ctl.scala 404:70]
wire _T_591 = _T_475 & _T_589; // @[exu_div_ctl.scala 404:95]
wire _T_601 = _T_591 & _T_468; // @[exu_div_ctl.scala 406:11]
wire _T_602 = _T_584 | _T_601; // @[exu_div_ctl.scala 419:88]
wire _T_611 = _T_476 & _T_385; // @[exu_div_ctl.scala 406:11]
wire _T_614 = _T_611 & _T_401; // @[exu_div_ctl.scala 420:36]
wire _T_615 = _T_602 | _T_614; // @[exu_div_ctl.scala 419:131]
wire _T_621 = _T_387 & _T_389; // @[exu_div_ctl.scala 405:95]
wire _T_622 = a_ff[3] & _T_621; // @[exu_div_ctl.scala 406:11]
wire _T_625 = _T_622 & _T_401; // @[exu_div_ctl.scala 420:76]
wire _T_626 = _T_615 | _T_625; // @[exu_div_ctl.scala 420:47]
wire _T_636 = _T_502 & b_ff[1]; // @[exu_div_ctl.scala 405:95]
wire _T_637 = _T_459 & _T_636; // @[exu_div_ctl.scala 406:11]
wire _T_638 = _T_626 | _T_637; // @[exu_div_ctl.scala 420:88]
wire _T_652 = _T_476 & _T_503; // @[exu_div_ctl.scala 406:11]
wire _T_653 = _T_638 | _T_652; // @[exu_div_ctl.scala 420:131]
wire _T_659 = _T_475 & a_ff[0]; // @[exu_div_ctl.scala 404:95]
wire _T_665 = _T_659 & _T_450; // @[exu_div_ctl.scala 406:11]
wire _T_666 = _T_653 | _T_665; // @[exu_div_ctl.scala 421:47]
wire _T_673 = _T_459 & _T_589; // @[exu_div_ctl.scala 404:95]
wire _T_679 = _T_502 & b_ff[0]; // @[exu_div_ctl.scala 405:95]
wire _T_680 = _T_673 & _T_679; // @[exu_div_ctl.scala 406:11]
wire _T_681 = _T_666 | _T_680; // @[exu_div_ctl.scala 421:88]
wire _T_686 = _T_458 & a_ff[1]; // @[exu_div_ctl.scala 404:95]
wire _T_687 = _T_686 & a_ff[0]; // @[exu_div_ctl.scala 404:95]
wire _T_693 = _T_687 & _T_390; // @[exu_div_ctl.scala 406:11]
wire _T_694 = _T_681 | _T_693; // @[exu_div_ctl.scala 421:131]
wire _T_700 = _T_416 & _T_389; // @[exu_div_ctl.scala 406:11]
wire _T_703 = _T_700 & _T_401; // @[exu_div_ctl.scala 422:75]
wire _T_704 = _T_694 | _T_703; // @[exu_div_ctl.scala 422:47]
wire _T_712 = _T_476 & a_ff[0]; // @[exu_div_ctl.scala 404:95]
wire _T_717 = _T_712 & _T_502; // @[exu_div_ctl.scala 406:11]
wire _T_718 = _T_704 | _T_717; // @[exu_div_ctl.scala 422:88]
wire _T_725 = b_ff[3] & _T_387; // @[exu_div_ctl.scala 405:95]
wire _T_726 = _T_416 & _T_725; // @[exu_div_ctl.scala 406:11]
wire _T_727 = _T_718 | _T_726; // @[exu_div_ctl.scala 422:131]
wire _T_737 = _T_725 & _T_389; // @[exu_div_ctl.scala 405:95]
wire _T_738 = _T_508 & _T_737; // @[exu_div_ctl.scala 406:11]
wire _T_739 = _T_727 | _T_738; // @[exu_div_ctl.scala 423:47]
wire _T_742 = a_ff[3] & a_ff[0]; // @[exu_div_ctl.scala 404:95]
wire _T_748 = _T_742 & _T_621; // @[exu_div_ctl.scala 406:11]
wire _T_749 = _T_739 | _T_748; // @[exu_div_ctl.scala 423:88]
wire _T_753 = a_ff[3] & _T_589; // @[exu_div_ctl.scala 404:95]
wire _T_761 = _T_636 & b_ff[0]; // @[exu_div_ctl.scala 405:95]
wire _T_762 = _T_753 & _T_761; // @[exu_div_ctl.scala 406:11]
wire _T_763 = _T_749 | _T_762; // @[exu_div_ctl.scala 423:131]
wire _T_770 = _T_520 & b_ff[3]; // @[exu_div_ctl.scala 406:11]
wire _T_773 = _T_770 & _T_401; // @[exu_div_ctl.scala 424:77]
wire _T_774 = _T_763 | _T_773; // @[exu_div_ctl.scala 424:47]
wire _T_783 = b_ff[3] & _T_389; // @[exu_div_ctl.scala 405:95]
wire _T_784 = _T_520 & _T_783; // @[exu_div_ctl.scala 406:11]
wire _T_785 = _T_774 | _T_784; // @[exu_div_ctl.scala 424:88]
wire _T_790 = _T_416 & a_ff[0]; // @[exu_div_ctl.scala 404:95]
wire _T_795 = _T_790 & _T_783; // @[exu_div_ctl.scala 406:11]
wire _T_796 = _T_785 | _T_795; // @[exu_div_ctl.scala 424:131]
wire _T_802 = _T_459 & a_ff[1]; // @[exu_div_ctl.scala 404:95]
wire _T_807 = _T_802 & _T_548; // @[exu_div_ctl.scala 406:11]
wire _T_808 = _T_796 | _T_807; // @[exu_div_ctl.scala 425:47]
wire _T_813 = _T_508 & a_ff[0]; // @[exu_div_ctl.scala 404:95]
wire _T_816 = _T_813 & _T_387; // @[exu_div_ctl.scala 406:11]
wire _T_817 = _T_808 | _T_816; // @[exu_div_ctl.scala 425:88]
wire _T_824 = _T_520 & a_ff[0]; // @[exu_div_ctl.scala 404:95]
wire _T_826 = _T_824 & b_ff[3]; // @[exu_div_ctl.scala 406:11]
wire _T_827 = _T_817 | _T_826; // @[exu_div_ctl.scala 425:131]
wire _T_833 = _T_508 & _T_387; // @[exu_div_ctl.scala 406:11]
wire _T_836 = _T_833 & _T_401; // @[exu_div_ctl.scala 426:74]
wire _T_837 = _T_827 | _T_836; // @[exu_div_ctl.scala 426:47]
wire [31:0] _T_352 = {28'h0,_T_392,_T_423,_T_526,_T_837}; // @[Cat.scala 29:58]
wire [31:0] _T_354 = _T_76 ? _T_351 : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_355 = smallnum_case ? _T_352 : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_356 = by_zero_case ? 32'hffffffff : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_357 = _T_354 | _T_355; // @[Mux.scala 27:72]
wire [31:0] q_in = _T_357 | _T_356; // @[Mux.scala 27:72]
wire _T_374 = ~twos_comp_q_sel; // @[exu_div_ctl.scala 399:16]
wire _T_375 = _T_9 & _T_374; // @[exu_div_ctl.scala 399:14]
wire [31:0] _T_377 = _T_375 ? q_ff : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_378 = rem_ff ? r_ff : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_379 = twos_comp_q_sel ? twos_comp_out : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_380 = _T_377 | _T_378; // @[Mux.scala 27:72]
wire [4:0] _T_863 = 5'h1f - shortq[4:0]; // @[exu_div_ctl.scala 440:57]
el2_exu_div_cls a_enc ( // @[exu_div_ctl.scala 429:21]
.io_operand(a_enc_io_operand),
.io_cls(a_enc_io_cls)
);
el2_exu_div_cls b_enc ( // @[exu_div_ctl.scala 432:21]
.io_operand(b_enc_io_operand),
.io_cls(b_enc_io_cls)
);
rvclkhdr rvclkhdr ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_io_clk),
.io_en(rvclkhdr_io_en)
);
rvclkhdr rvclkhdr_1 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_1_io_clk),
.io_en(rvclkhdr_1_io_en)
);
rvclkhdr rvclkhdr_2 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_2_io_clk),
.io_en(rvclkhdr_2_io_en)
);
rvclkhdr rvclkhdr_3 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_3_io_clk),
.io_en(rvclkhdr_3_io_en)
);
rvclkhdr rvclkhdr_4 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_4_io_clk),
.io_en(rvclkhdr_4_io_en)
);
rvclkhdr rvclkhdr_5 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_5_io_clk),
.io_en(rvclkhdr_5_io_en)
);
rvclkhdr rvclkhdr_6 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_6_io_clk),
.io_en(rvclkhdr_6_io_en)
);
rvclkhdr rvclkhdr_7 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_7_io_clk),
.io_en(rvclkhdr_7_io_en)
);
rvclkhdr rvclkhdr_8 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_8_io_clk),
.io_en(rvclkhdr_8_io_en)
);
rvclkhdr rvclkhdr_9 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_9_io_clk),
.io_en(rvclkhdr_9_io_en)
);
rvclkhdr rvclkhdr_10 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_10_io_clk),
.io_en(rvclkhdr_10_io_en)
);
assign io_data_out = _T_380 | _T_379; // @[exu_div_ctl.scala 398:15]
assign io_valid_out = finish_ff & _T_12; // @[exu_div_ctl.scala 397:16]
assign a_enc_io_operand = {dividend_sign_ff,a_ff}; // @[exu_div_ctl.scala 430:20]
assign b_enc_io_operand = b_ff; // @[exu_div_ctl.scala 433:20]
assign rvclkhdr_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_io_en = _T_47 | finish_ff; // @[lib.scala 393:17]
assign rvclkhdr_1_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_1_io_en = _T_47 | finish_ff; // @[lib.scala 393:17]
assign rvclkhdr_2_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_2_io_en = _T_47 | finish_ff; // @[lib.scala 393:17]
assign rvclkhdr_3_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_3_io_en = _T_47 | finish_ff; // @[lib.scala 393:17]
assign rvclkhdr_4_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_4_io_en = _T_47 | finish_ff; // @[lib.scala 393:17]
assign rvclkhdr_5_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_5_io_en = _T_47 | finish_ff; // @[lib.scala 393:17]
assign rvclkhdr_6_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_6_io_en = _T_47 | finish_ff; // @[lib.scala 393:17]
assign rvclkhdr_7_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_7_io_en = io_valid_in | running_state; // @[lib.scala 393:17]
assign rvclkhdr_8_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_8_io_en = io_valid_in | b_twos_comp; // @[lib.scala 393:17]
assign rvclkhdr_9_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_9_io_en = _T_45 | running_state; // @[lib.scala 393:17]
assign rvclkhdr_10_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_10_io_en = _T_45 | running_state; // @[lib.scala 393:17]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
control_ff = _RAND_0[2:0];
_RAND_1 = {2{`RANDOM}};
b_ff = _RAND_1[32:0];
_RAND_2 = {1{`RANDOM}};
valid_ff = _RAND_2[0:0];
_RAND_3 = {1{`RANDOM}};
a_ff = _RAND_3[31:0];
_RAND_4 = {1{`RANDOM}};
count_ff = _RAND_4[6:0];
_RAND_5 = {1{`RANDOM}};
shortq_enable_ff = _RAND_5[0:0];
_RAND_6 = {1{`RANDOM}};
finish_ff = _RAND_6[0:0];
_RAND_7 = {1{`RANDOM}};
shortq_shift_ff = _RAND_7[4:0];
_RAND_8 = {1{`RANDOM}};
by_zero_case_ff = _RAND_8[0:0];
_RAND_9 = {1{`RANDOM}};
r_ff = _RAND_9[31:0];
_RAND_10 = {1{`RANDOM}};
q_ff = _RAND_10[31:0];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
control_ff = 3'h0;
end
if (reset) begin
b_ff = 33'h0;
end
if (reset) begin
valid_ff = 1'h0;
end
if (reset) begin
a_ff = 32'h0;
end
if (reset) begin
count_ff = 7'h0;
end
if (reset) begin
shortq_enable_ff = 1'h0;
end
if (reset) begin
finish_ff = 1'h0;
end
if (reset) begin
shortq_shift_ff = 5'h0;
end
if (reset) begin
by_zero_case_ff = 1'h0;
end
if (reset) begin
r_ff = 32'h0;
end
if (reset) begin
q_ff = 32'h0;
end
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
always @(posedge clock or posedge reset) begin
if (reset) begin
control_ff <= 3'h0;
end else if (misc_enable) begin
control_ff <= control_in;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
b_ff <= 33'h0;
end else if (b_enable) begin
b_ff <= b_in;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
valid_ff <= 1'h0;
end else if (misc_enable) begin
valid_ff <= valid_ff_in;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
a_ff <= 32'h0;
end else if (a_enable) begin
a_ff <= a_in;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
count_ff <= 7'h0;
end else if (misc_enable) begin
count_ff <= count_in;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
shortq_enable_ff <= 1'h0;
end else if (misc_enable) begin
shortq_enable_ff <= shortq_enable;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
finish_ff <= 1'h0;
end else if (misc_enable) begin
finish_ff <= finish;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
shortq_shift_ff <= 5'h0;
end else if (misc_enable) begin
if (_T_58) begin
shortq_shift_ff <= 5'h0;
end else begin
shortq_shift_ff <= _T_863;
end
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
by_zero_case_ff <= 1'h0;
end else if (misc_enable) begin
by_zero_case_ff <= by_zero_case;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
r_ff <= 32'h0;
end else if (rq_enable) begin
r_ff <= r_in;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
q_ff <= 32'h0;
end else if (rq_enable) begin
q_ff <= q_in;
end
end
endmodule

38
exu_div_ctl.anno.json Normal file
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@ -0,0 +1,38 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~exu_div_ctl|exu_div_ctl>io_exu_div_wren",
"sources":[
"~exu_div_ctl|exu_div_ctl>io_dec_div_dec_div_cancel"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~exu_div_ctl|exu_div_ctl>io_exu_div_result",
"sources":[
"~exu_div_ctl|exu_div_ctl>io_exu_div_wren",
"~exu_div_ctl|exu_div_ctl>io_dec_div_dec_div_cancel"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"exu_div_ctl.gated_latch",
"resourceId":"/vsrc/gated_latch.sv"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"exu_div_ctl"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

2270
exu_div_ctl.fir Normal file
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File diff suppressed because it is too large Load Diff

986
exu_div_ctl.v Normal file
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@ -0,0 +1,986 @@
module rvclkhdr(
input io_clk,
input io_en
);
wire clkhdr_Q; // @[lib.scala 334:26]
wire clkhdr_CK; // @[lib.scala 334:26]
wire clkhdr_EN; // @[lib.scala 334:26]
wire clkhdr_SE; // @[lib.scala 334:26]
gated_latch clkhdr ( // @[lib.scala 334:26]
.Q(clkhdr_Q),
.CK(clkhdr_CK),
.EN(clkhdr_EN),
.SE(clkhdr_SE)
);
assign clkhdr_CK = io_clk; // @[lib.scala 336:18]
assign clkhdr_EN = io_en; // @[lib.scala 337:18]
assign clkhdr_SE = 1'h0; // @[lib.scala 338:18]
endmodule
module el2_exu_div_existing_1bit_cheapshortq(
input clock,
input reset,
input io_cancel,
input io_valid_in,
input io_signed_in,
input io_rem_in,
input [31:0] io_dividend_in,
input [31:0] io_divisor_in,
output [31:0] io_data_out,
output io_valid_out
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [63:0] _RAND_1;
reg [63:0] _RAND_2;
reg [31:0] _RAND_3;
reg [31:0] _RAND_4;
reg [31:0] _RAND_5;
reg [31:0] _RAND_6;
reg [31:0] _RAND_7;
reg [31:0] _RAND_8;
reg [31:0] _RAND_9;
reg [31:0] _RAND_10;
reg [63:0] _RAND_11;
reg [31:0] _RAND_12;
reg [31:0] _RAND_13;
reg [31:0] _RAND_14;
`endif // RANDOMIZE_REG_INIT
wire rvclkhdr_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_io_en; // @[lib.scala 390:23]
wire rvclkhdr_1_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_1_io_en; // @[lib.scala 390:23]
wire rvclkhdr_2_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_2_io_en; // @[lib.scala 390:23]
wire rvclkhdr_3_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_3_io_en; // @[lib.scala 390:23]
wire rvclkhdr_4_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_4_io_en; // @[lib.scala 390:23]
wire rvclkhdr_5_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_5_io_en; // @[lib.scala 390:23]
wire rvclkhdr_6_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_6_io_en; // @[lib.scala 390:23]
wire rvclkhdr_7_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_7_io_en; // @[lib.scala 390:23]
wire rvclkhdr_8_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_8_io_en; // @[lib.scala 390:23]
wire rvclkhdr_9_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_9_io_en; // @[lib.scala 390:23]
wire rvclkhdr_10_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_10_io_en; // @[lib.scala 390:23]
wire rvclkhdr_11_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_11_io_en; // @[lib.scala 390:23]
wire rvclkhdr_12_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_12_io_en; // @[lib.scala 390:23]
wire rvclkhdr_13_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_13_io_en; // @[lib.scala 390:23]
wire rvclkhdr_14_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_14_io_en; // @[lib.scala 390:23]
wire _T = ~io_cancel; // @[exu_div_ctl.scala 127:30]
reg valid_ff_x; // @[Reg.scala 27:20]
wire valid_x = valid_ff_x & _T; // @[exu_div_ctl.scala 127:28]
reg [32:0] q_ff; // @[Reg.scala 27:20]
wire _T_2 = q_ff[31:4] == 28'h0; // @[exu_div_ctl.scala 133:34]
reg [32:0] m_ff; // @[Reg.scala 27:20]
wire _T_4 = m_ff[31:4] == 28'h0; // @[exu_div_ctl.scala 133:57]
wire _T_5 = _T_2 & _T_4; // @[exu_div_ctl.scala 133:43]
wire _T_7 = m_ff[31:0] != 32'h0; // @[exu_div_ctl.scala 133:80]
wire _T_8 = _T_5 & _T_7; // @[exu_div_ctl.scala 133:66]
reg rem_ff; // @[Reg.scala 27:20]
wire _T_9 = ~rem_ff; // @[exu_div_ctl.scala 133:91]
wire _T_10 = _T_8 & _T_9; // @[exu_div_ctl.scala 133:89]
wire _T_11 = _T_10 & valid_x; // @[exu_div_ctl.scala 133:99]
wire _T_13 = q_ff[31:0] == 32'h0; // @[exu_div_ctl.scala 134:18]
wire _T_16 = _T_13 & _T_7; // @[exu_div_ctl.scala 134:27]
wire _T_18 = _T_16 & _T_9; // @[exu_div_ctl.scala 134:50]
wire _T_19 = _T_18 & valid_x; // @[exu_div_ctl.scala 134:60]
wire smallnum_case = _T_11 | _T_19; // @[exu_div_ctl.scala 133:110]
wire _T_23 = ~m_ff[3]; // @[exu_div_ctl.scala 138:69]
wire _T_25 = ~m_ff[2]; // @[exu_div_ctl.scala 138:69]
wire _T_27 = ~m_ff[1]; // @[exu_div_ctl.scala 138:69]
wire _T_28 = _T_23 & _T_25; // @[exu_div_ctl.scala 138:94]
wire _T_29 = _T_28 & _T_27; // @[exu_div_ctl.scala 138:94]
wire _T_30 = q_ff[3] & _T_29; // @[exu_div_ctl.scala 139:10]
wire _T_37 = q_ff[3] & _T_28; // @[exu_div_ctl.scala 139:10]
wire _T_39 = ~m_ff[0]; // @[exu_div_ctl.scala 145:32]
wire _T_40 = _T_37 & _T_39; // @[exu_div_ctl.scala 145:30]
wire _T_50 = q_ff[2] & _T_29; // @[exu_div_ctl.scala 139:10]
wire _T_51 = _T_40 | _T_50; // @[exu_div_ctl.scala 145:41]
wire _T_54 = q_ff[3] & q_ff[2]; // @[exu_div_ctl.scala 137:94]
wire _T_60 = _T_54 & _T_28; // @[exu_div_ctl.scala 139:10]
wire _T_61 = _T_51 | _T_60; // @[exu_div_ctl.scala 145:73]
wire _T_68 = q_ff[2] & _T_28; // @[exu_div_ctl.scala 139:10]
wire _T_71 = _T_68 & _T_39; // @[exu_div_ctl.scala 147:30]
wire _T_81 = q_ff[1] & _T_29; // @[exu_div_ctl.scala 139:10]
wire _T_82 = _T_71 | _T_81; // @[exu_div_ctl.scala 147:41]
wire _T_88 = _T_23 & _T_27; // @[exu_div_ctl.scala 138:94]
wire _T_89 = q_ff[3] & _T_88; // @[exu_div_ctl.scala 139:10]
wire _T_92 = _T_89 & _T_39; // @[exu_div_ctl.scala 147:103]
wire _T_93 = _T_82 | _T_92; // @[exu_div_ctl.scala 147:76]
wire _T_96 = ~q_ff[2]; // @[exu_div_ctl.scala 137:69]
wire _T_97 = q_ff[3] & _T_96; // @[exu_div_ctl.scala 137:94]
wire _T_105 = _T_28 & m_ff[1]; // @[exu_div_ctl.scala 138:94]
wire _T_106 = _T_105 & m_ff[0]; // @[exu_div_ctl.scala 138:94]
wire _T_107 = _T_97 & _T_106; // @[exu_div_ctl.scala 139:10]
wire _T_108 = _T_93 | _T_107; // @[exu_div_ctl.scala 147:114]
wire _T_110 = ~q_ff[3]; // @[exu_div_ctl.scala 137:69]
wire _T_113 = _T_110 & q_ff[2]; // @[exu_div_ctl.scala 137:94]
wire _T_114 = _T_113 & q_ff[1]; // @[exu_div_ctl.scala 137:94]
wire _T_120 = _T_114 & _T_28; // @[exu_div_ctl.scala 139:10]
wire _T_121 = _T_108 | _T_120; // @[exu_div_ctl.scala 148:43]
wire _T_127 = _T_54 & _T_23; // @[exu_div_ctl.scala 139:10]
wire _T_130 = _T_127 & _T_39; // @[exu_div_ctl.scala 148:104]
wire _T_131 = _T_121 | _T_130; // @[exu_div_ctl.scala 148:78]
wire _T_140 = _T_23 & m_ff[2]; // @[exu_div_ctl.scala 138:94]
wire _T_141 = _T_140 & _T_27; // @[exu_div_ctl.scala 138:94]
wire _T_142 = _T_54 & _T_141; // @[exu_div_ctl.scala 139:10]
wire _T_143 = _T_131 | _T_142; // @[exu_div_ctl.scala 148:116]
wire _T_146 = q_ff[3] & q_ff[1]; // @[exu_div_ctl.scala 137:94]
wire _T_152 = _T_146 & _T_88; // @[exu_div_ctl.scala 139:10]
wire _T_153 = _T_143 | _T_152; // @[exu_div_ctl.scala 149:43]
wire _T_158 = _T_54 & q_ff[1]; // @[exu_div_ctl.scala 137:94]
wire _T_163 = _T_158 & _T_140; // @[exu_div_ctl.scala 139:10]
wire _T_164 = _T_153 | _T_163; // @[exu_div_ctl.scala 149:77]
wire _T_168 = q_ff[2] & q_ff[1]; // @[exu_div_ctl.scala 137:94]
wire _T_169 = _T_168 & q_ff[0]; // @[exu_div_ctl.scala 137:94]
wire _T_175 = _T_169 & _T_88; // @[exu_div_ctl.scala 139:10]
wire _T_181 = _T_97 & q_ff[0]; // @[exu_div_ctl.scala 137:94]
wire _T_186 = _T_23 & m_ff[1]; // @[exu_div_ctl.scala 138:94]
wire _T_187 = _T_186 & m_ff[0]; // @[exu_div_ctl.scala 138:94]
wire _T_188 = _T_181 & _T_187; // @[exu_div_ctl.scala 139:10]
wire _T_189 = _T_175 | _T_188; // @[exu_div_ctl.scala 151:44]
wire _T_196 = q_ff[2] & _T_88; // @[exu_div_ctl.scala 139:10]
wire _T_199 = _T_196 & _T_39; // @[exu_div_ctl.scala 151:111]
wire _T_200 = _T_189 | _T_199; // @[exu_div_ctl.scala 151:84]
wire _T_207 = q_ff[1] & _T_28; // @[exu_div_ctl.scala 139:10]
wire _T_210 = _T_207 & _T_39; // @[exu_div_ctl.scala 152:32]
wire _T_211 = _T_200 | _T_210; // @[exu_div_ctl.scala 151:126]
wire _T_221 = q_ff[0] & _T_29; // @[exu_div_ctl.scala 139:10]
wire _T_222 = _T_211 | _T_221; // @[exu_div_ctl.scala 152:46]
wire _T_227 = ~q_ff[1]; // @[exu_div_ctl.scala 137:69]
wire _T_229 = _T_113 & _T_227; // @[exu_div_ctl.scala 137:94]
wire _T_239 = _T_229 & _T_106; // @[exu_div_ctl.scala 139:10]
wire _T_240 = _T_222 | _T_239; // @[exu_div_ctl.scala 152:86]
wire _T_249 = _T_114 & _T_23; // @[exu_div_ctl.scala 139:10]
wire _T_252 = _T_249 & _T_39; // @[exu_div_ctl.scala 153:35]
wire _T_253 = _T_240 | _T_252; // @[exu_div_ctl.scala 152:128]
wire _T_259 = _T_25 & _T_27; // @[exu_div_ctl.scala 138:94]
wire _T_260 = q_ff[3] & _T_259; // @[exu_div_ctl.scala 139:10]
wire _T_263 = _T_260 & _T_39; // @[exu_div_ctl.scala 153:74]
wire _T_264 = _T_253 | _T_263; // @[exu_div_ctl.scala 153:46]
wire _T_274 = _T_140 & m_ff[1]; // @[exu_div_ctl.scala 138:94]
wire _T_275 = _T_97 & _T_274; // @[exu_div_ctl.scala 139:10]
wire _T_276 = _T_264 | _T_275; // @[exu_div_ctl.scala 153:86]
wire _T_290 = _T_114 & _T_141; // @[exu_div_ctl.scala 139:10]
wire _T_291 = _T_276 | _T_290; // @[exu_div_ctl.scala 153:128]
wire _T_297 = _T_113 & q_ff[0]; // @[exu_div_ctl.scala 137:94]
wire _T_303 = _T_297 & _T_88; // @[exu_div_ctl.scala 139:10]
wire _T_304 = _T_291 | _T_303; // @[exu_div_ctl.scala 154:46]
wire _T_311 = _T_97 & _T_227; // @[exu_div_ctl.scala 137:94]
wire _T_317 = _T_140 & m_ff[0]; // @[exu_div_ctl.scala 138:94]
wire _T_318 = _T_311 & _T_317; // @[exu_div_ctl.scala 139:10]
wire _T_319 = _T_304 | _T_318; // @[exu_div_ctl.scala 154:86]
wire _T_324 = _T_96 & q_ff[1]; // @[exu_div_ctl.scala 137:94]
wire _T_325 = _T_324 & q_ff[0]; // @[exu_div_ctl.scala 137:94]
wire _T_331 = _T_325 & _T_28; // @[exu_div_ctl.scala 139:10]
wire _T_332 = _T_319 | _T_331; // @[exu_div_ctl.scala 154:128]
wire _T_338 = _T_54 & _T_27; // @[exu_div_ctl.scala 139:10]
wire _T_341 = _T_338 & _T_39; // @[exu_div_ctl.scala 155:73]
wire _T_342 = _T_332 | _T_341; // @[exu_div_ctl.scala 155:46]
wire _T_350 = _T_114 & q_ff[0]; // @[exu_div_ctl.scala 137:94]
wire _T_355 = _T_350 & _T_140; // @[exu_div_ctl.scala 139:10]
wire _T_356 = _T_342 | _T_355; // @[exu_div_ctl.scala 155:86]
wire _T_363 = m_ff[3] & _T_25; // @[exu_div_ctl.scala 138:94]
wire _T_364 = _T_54 & _T_363; // @[exu_div_ctl.scala 139:10]
wire _T_365 = _T_356 | _T_364; // @[exu_div_ctl.scala 155:128]
wire _T_375 = _T_363 & _T_27; // @[exu_div_ctl.scala 138:94]
wire _T_376 = _T_146 & _T_375; // @[exu_div_ctl.scala 139:10]
wire _T_377 = _T_365 | _T_376; // @[exu_div_ctl.scala 156:46]
wire _T_380 = q_ff[3] & q_ff[0]; // @[exu_div_ctl.scala 137:94]
wire _T_386 = _T_380 & _T_259; // @[exu_div_ctl.scala 139:10]
wire _T_387 = _T_377 | _T_386; // @[exu_div_ctl.scala 156:86]
wire _T_391 = q_ff[3] & _T_227; // @[exu_div_ctl.scala 137:94]
wire _T_399 = _T_274 & m_ff[0]; // @[exu_div_ctl.scala 138:94]
wire _T_400 = _T_391 & _T_399; // @[exu_div_ctl.scala 139:10]
wire _T_401 = _T_387 | _T_400; // @[exu_div_ctl.scala 156:128]
wire _T_408 = _T_158 & m_ff[3]; // @[exu_div_ctl.scala 139:10]
wire _T_411 = _T_408 & _T_39; // @[exu_div_ctl.scala 157:75]
wire _T_412 = _T_401 | _T_411; // @[exu_div_ctl.scala 157:46]
wire _T_421 = m_ff[3] & _T_27; // @[exu_div_ctl.scala 138:94]
wire _T_422 = _T_158 & _T_421; // @[exu_div_ctl.scala 139:10]
wire _T_423 = _T_412 | _T_422; // @[exu_div_ctl.scala 157:86]
wire _T_428 = _T_54 & q_ff[0]; // @[exu_div_ctl.scala 137:94]
wire _T_433 = _T_428 & _T_421; // @[exu_div_ctl.scala 139:10]
wire _T_434 = _T_423 | _T_433; // @[exu_div_ctl.scala 157:128]
wire _T_440 = _T_97 & q_ff[1]; // @[exu_div_ctl.scala 137:94]
wire _T_445 = _T_440 & _T_186; // @[exu_div_ctl.scala 139:10]
wire _T_446 = _T_434 | _T_445; // @[exu_div_ctl.scala 158:46]
wire _T_451 = _T_146 & q_ff[0]; // @[exu_div_ctl.scala 137:94]
wire _T_454 = _T_451 & _T_25; // @[exu_div_ctl.scala 139:10]
wire _T_455 = _T_446 | _T_454; // @[exu_div_ctl.scala 158:86]
wire _T_462 = _T_158 & q_ff[0]; // @[exu_div_ctl.scala 137:94]
wire _T_464 = _T_462 & m_ff[3]; // @[exu_div_ctl.scala 139:10]
wire _T_465 = _T_455 | _T_464; // @[exu_div_ctl.scala 158:128]
wire _T_471 = _T_146 & _T_25; // @[exu_div_ctl.scala 139:10]
wire _T_474 = _T_471 & _T_39; // @[exu_div_ctl.scala 159:72]
wire _T_475 = _T_465 | _T_474; // @[exu_div_ctl.scala 159:46]
wire [3:0] smallnum = {_T_30,_T_61,_T_164,_T_475}; // @[Cat.scala 29:58]
reg sign_ff; // @[Reg.scala 27:20]
wire _T_479 = sign_ff & q_ff[31]; // @[exu_div_ctl.scala 168:34]
wire [32:0] short_dividend = {_T_479,q_ff[31:0]}; // @[Cat.scala 29:58]
wire _T_484 = ~short_dividend[32]; // @[exu_div_ctl.scala 173:7]
wire _T_487 = short_dividend[31:24] != 8'h0; // @[exu_div_ctl.scala 173:60]
wire _T_492 = short_dividend[31:23] != 9'h1ff; // @[exu_div_ctl.scala 174:59]
wire _T_493 = _T_484 & _T_487; // @[Mux.scala 27:72]
wire _T_494 = short_dividend[32] & _T_492; // @[Mux.scala 27:72]
wire _T_495 = _T_493 | _T_494; // @[Mux.scala 27:72]
wire _T_502 = short_dividend[23:16] != 8'h0; // @[exu_div_ctl.scala 177:60]
wire _T_507 = short_dividend[22:15] != 8'hff; // @[exu_div_ctl.scala 178:59]
wire _T_508 = _T_484 & _T_502; // @[Mux.scala 27:72]
wire _T_509 = short_dividend[32] & _T_507; // @[Mux.scala 27:72]
wire _T_510 = _T_508 | _T_509; // @[Mux.scala 27:72]
wire _T_517 = short_dividend[15:8] != 8'h0; // @[exu_div_ctl.scala 181:59]
wire _T_522 = short_dividend[14:7] != 8'hff; // @[exu_div_ctl.scala 182:58]
wire _T_523 = _T_484 & _T_517; // @[Mux.scala 27:72]
wire _T_524 = short_dividend[32] & _T_522; // @[Mux.scala 27:72]
wire _T_525 = _T_523 | _T_524; // @[Mux.scala 27:72]
wire [4:0] a_cls = {2'h0,_T_495,_T_510,_T_525}; // @[Cat.scala 29:58]
wire _T_531 = ~m_ff[32]; // @[exu_div_ctl.scala 187:7]
wire _T_534 = m_ff[31:24] != 8'h0; // @[exu_div_ctl.scala 187:40]
wire _T_539 = m_ff[31:24] != 8'hff; // @[exu_div_ctl.scala 188:39]
wire _T_540 = _T_531 & _T_534; // @[Mux.scala 27:72]
wire _T_541 = m_ff[32] & _T_539; // @[Mux.scala 27:72]
wire _T_542 = _T_540 | _T_541; // @[Mux.scala 27:72]
wire _T_549 = m_ff[23:16] != 8'h0; // @[exu_div_ctl.scala 191:40]
wire _T_554 = m_ff[23:16] != 8'hff; // @[exu_div_ctl.scala 192:39]
wire _T_555 = _T_531 & _T_549; // @[Mux.scala 27:72]
wire _T_556 = m_ff[32] & _T_554; // @[Mux.scala 27:72]
wire _T_557 = _T_555 | _T_556; // @[Mux.scala 27:72]
wire _T_564 = m_ff[15:8] != 8'h0; // @[exu_div_ctl.scala 195:39]
wire _T_569 = m_ff[15:8] != 8'hff; // @[exu_div_ctl.scala 196:38]
wire _T_570 = _T_531 & _T_564; // @[Mux.scala 27:72]
wire _T_571 = m_ff[32] & _T_569; // @[Mux.scala 27:72]
wire _T_572 = _T_570 | _T_571; // @[Mux.scala 27:72]
wire [4:0] b_cls = {2'h0,_T_542,_T_557,_T_572}; // @[Cat.scala 29:58]
wire _T_577 = a_cls[2:1] == 2'h1; // @[exu_div_ctl.scala 200:19]
wire _T_580 = _T_577 & b_cls[2]; // @[exu_div_ctl.scala 200:34]
wire _T_582 = a_cls[2:0] == 3'h1; // @[exu_div_ctl.scala 201:21]
wire _T_585 = _T_582 & b_cls[2]; // @[exu_div_ctl.scala 201:36]
wire _T_586 = _T_580 | _T_585; // @[exu_div_ctl.scala 200:65]
wire _T_588 = a_cls[2:0] == 3'h0; // @[exu_div_ctl.scala 202:21]
wire _T_591 = _T_588 & b_cls[2]; // @[exu_div_ctl.scala 202:36]
wire _T_592 = _T_586 | _T_591; // @[exu_div_ctl.scala 201:67]
wire _T_596 = b_cls[2:1] == 2'h1; // @[exu_div_ctl.scala 203:50]
wire _T_597 = _T_582 & _T_596; // @[exu_div_ctl.scala 203:36]
wire _T_598 = _T_592 | _T_597; // @[exu_div_ctl.scala 202:67]
wire _T_603 = _T_588 & _T_596; // @[exu_div_ctl.scala 204:36]
wire _T_604 = _T_598 | _T_603; // @[exu_div_ctl.scala 203:67]
wire _T_608 = b_cls[2:0] == 3'h1; // @[exu_div_ctl.scala 205:50]
wire _T_609 = _T_588 & _T_608; // @[exu_div_ctl.scala 205:36]
wire _T_610 = _T_604 | _T_609; // @[exu_div_ctl.scala 204:67]
wire _T_615 = a_cls[2] & b_cls[2]; // @[exu_div_ctl.scala 207:34]
wire _T_620 = _T_577 & _T_596; // @[exu_div_ctl.scala 208:36]
wire _T_621 = _T_615 | _T_620; // @[exu_div_ctl.scala 207:65]
wire _T_626 = _T_582 & _T_608; // @[exu_div_ctl.scala 209:36]
wire _T_627 = _T_621 | _T_626; // @[exu_div_ctl.scala 208:67]
wire _T_631 = b_cls[2:0] == 3'h0; // @[exu_div_ctl.scala 210:50]
wire _T_632 = _T_588 & _T_631; // @[exu_div_ctl.scala 210:36]
wire _T_633 = _T_627 | _T_632; // @[exu_div_ctl.scala 209:67]
wire _T_638 = a_cls[2] & _T_596; // @[exu_div_ctl.scala 212:34]
wire _T_643 = _T_577 & _T_608; // @[exu_div_ctl.scala 213:36]
wire _T_644 = _T_638 | _T_643; // @[exu_div_ctl.scala 212:65]
wire _T_649 = _T_582 & _T_631; // @[exu_div_ctl.scala 214:36]
wire _T_650 = _T_644 | _T_649; // @[exu_div_ctl.scala 213:67]
wire _T_655 = a_cls[2] & _T_608; // @[exu_div_ctl.scala 216:34]
wire _T_660 = _T_577 & _T_631; // @[exu_div_ctl.scala 217:36]
wire _T_661 = _T_655 | _T_660; // @[exu_div_ctl.scala 216:65]
wire [3:0] shortq_raw = {_T_610,_T_633,_T_650,_T_661}; // @[Cat.scala 29:58]
wire _T_666 = valid_ff_x & _T_7; // @[exu_div_ctl.scala 220:35]
wire _T_667 = shortq_raw != 4'h0; // @[exu_div_ctl.scala 220:78]
wire shortq_enable = _T_666 & _T_667; // @[exu_div_ctl.scala 220:64]
wire [3:0] _T_669 = shortq_enable ? 4'hf : 4'h0; // @[Bitwise.scala 72:12]
wire [3:0] _T_670 = _T_669 & shortq_raw; // @[exu_div_ctl.scala 221:57]
wire [5:0] shortq_shift = {2'h0,_T_670}; // @[Cat.scala 29:58]
reg [5:0] _T_1521; // @[Reg.scala 27:20]
wire [3:0] shortq_shift_xx = _T_1521[3:0]; // @[exu_div_ctl.scala 277:21]
wire [4:0] _T_679 = shortq_shift_xx[3] ? 5'h1f : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_680 = shortq_shift_xx[2] ? 5'h18 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_681 = shortq_shift_xx[1] ? 5'h10 : 5'h0; // @[Mux.scala 27:72]
wire [3:0] _T_682 = shortq_shift_xx[0] ? 4'h8 : 4'h0; // @[Mux.scala 27:72]
wire [4:0] _T_683 = _T_679 | _T_680; // @[Mux.scala 27:72]
wire [4:0] _T_684 = _T_683 | _T_681; // @[Mux.scala 27:72]
wire [4:0] _GEN_15 = {{1'd0}, _T_682}; // @[Mux.scala 27:72]
wire [4:0] _T_685 = _T_684 | _GEN_15; // @[Mux.scala 27:72]
wire [5:0] shortq_shift_ff = {1'h0,_T_685}; // @[Cat.scala 29:58]
reg [5:0] count; // @[Reg.scala 27:20]
wire _T_688 = count == 6'h20; // @[exu_div_ctl.scala 230:55]
wire _T_689 = count == 6'h21; // @[exu_div_ctl.scala 230:76]
wire _T_690 = _T_9 ? _T_688 : _T_689; // @[exu_div_ctl.scala 230:39]
wire finish = smallnum_case | _T_690; // @[exu_div_ctl.scala 230:34]
reg run_state; // @[Reg.scala 27:20]
wire _T_691 = io_valid_in | run_state; // @[exu_div_ctl.scala 231:32]
wire _T_692 = _T_691 | finish; // @[exu_div_ctl.scala 231:44]
reg finish_ff; // @[Reg.scala 27:20]
wire div_clken = _T_692 | finish_ff; // @[exu_div_ctl.scala 231:53]
wire _T_694 = ~finish; // @[exu_div_ctl.scala 232:48]
wire _T_695 = _T_691 & _T_694; // @[exu_div_ctl.scala 232:46]
wire run_in = _T_695 & _T; // @[exu_div_ctl.scala 232:56]
wire _T_698 = run_state & _T_694; // @[exu_div_ctl.scala 233:35]
wire _T_700 = _T_698 & _T; // @[exu_div_ctl.scala 233:45]
wire _T_701 = ~shortq_enable; // @[exu_div_ctl.scala 233:60]
wire _T_702 = _T_700 & _T_701; // @[exu_div_ctl.scala 233:58]
wire [5:0] _T_704 = _T_702 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12]
wire [5:0] _T_706 = {1'h0,shortq_shift_ff[4:0]}; // @[Cat.scala 29:58]
wire [5:0] _T_708 = count + _T_706; // @[exu_div_ctl.scala 233:86]
wire [5:0] _T_710 = _T_708 + 6'h1; // @[exu_div_ctl.scala 233:118]
wire [5:0] count_in = _T_704 & _T_710; // @[exu_div_ctl.scala 233:77]
wire _T_714 = ~io_signed_in; // @[exu_div_ctl.scala 235:20]
wire _T_715 = io_divisor_in != 32'h0; // @[exu_div_ctl.scala 235:51]
wire sign_eff = _T_714 & _T_715; // @[exu_div_ctl.scala 235:34]
wire _T_716 = ~run_state; // @[exu_div_ctl.scala 238:6]
wire [32:0] _T_718 = {1'h0,io_dividend_in}; // @[Cat.scala 29:58]
reg shortq_enable_ff; // @[Reg.scala 27:20]
wire _T_719 = valid_ff_x | shortq_enable_ff; // @[exu_div_ctl.scala 239:30]
wire _T_720 = run_state & _T_719; // @[exu_div_ctl.scala 239:16]
reg dividend_neg_ff; // @[Reg.scala 27:20]
wire _T_744 = sign_ff & dividend_neg_ff; // @[exu_div_ctl.scala 243:32]
wire _T_929 = |q_ff[30:0]; // @[lib.scala 428:35]
wire _T_931 = ~q_ff[31]; // @[lib.scala 428:40]
wire _T_933 = _T_929 ? _T_931 : q_ff[31]; // @[lib.scala 428:23]
wire _T_923 = |q_ff[29:0]; // @[lib.scala 428:35]
wire _T_925 = ~q_ff[30]; // @[lib.scala 428:40]
wire _T_927 = _T_923 ? _T_925 : q_ff[30]; // @[lib.scala 428:23]
wire _T_917 = |q_ff[28:0]; // @[lib.scala 428:35]
wire _T_919 = ~q_ff[29]; // @[lib.scala 428:40]
wire _T_921 = _T_917 ? _T_919 : q_ff[29]; // @[lib.scala 428:23]
wire _T_911 = |q_ff[27:0]; // @[lib.scala 428:35]
wire _T_913 = ~q_ff[28]; // @[lib.scala 428:40]
wire _T_915 = _T_911 ? _T_913 : q_ff[28]; // @[lib.scala 428:23]
wire _T_905 = |q_ff[26:0]; // @[lib.scala 428:35]
wire _T_907 = ~q_ff[27]; // @[lib.scala 428:40]
wire _T_909 = _T_905 ? _T_907 : q_ff[27]; // @[lib.scala 428:23]
wire _T_899 = |q_ff[25:0]; // @[lib.scala 428:35]
wire _T_901 = ~q_ff[26]; // @[lib.scala 428:40]
wire _T_903 = _T_899 ? _T_901 : q_ff[26]; // @[lib.scala 428:23]
wire _T_893 = |q_ff[24:0]; // @[lib.scala 428:35]
wire _T_895 = ~q_ff[25]; // @[lib.scala 428:40]
wire _T_897 = _T_893 ? _T_895 : q_ff[25]; // @[lib.scala 428:23]
wire _T_887 = |q_ff[23:0]; // @[lib.scala 428:35]
wire _T_889 = ~q_ff[24]; // @[lib.scala 428:40]
wire _T_891 = _T_887 ? _T_889 : q_ff[24]; // @[lib.scala 428:23]
wire _T_881 = |q_ff[22:0]; // @[lib.scala 428:35]
wire _T_883 = ~q_ff[23]; // @[lib.scala 428:40]
wire _T_885 = _T_881 ? _T_883 : q_ff[23]; // @[lib.scala 428:23]
wire _T_875 = |q_ff[21:0]; // @[lib.scala 428:35]
wire _T_877 = ~q_ff[22]; // @[lib.scala 428:40]
wire _T_879 = _T_875 ? _T_877 : q_ff[22]; // @[lib.scala 428:23]
wire _T_869 = |q_ff[20:0]; // @[lib.scala 428:35]
wire _T_871 = ~q_ff[21]; // @[lib.scala 428:40]
wire _T_873 = _T_869 ? _T_871 : q_ff[21]; // @[lib.scala 428:23]
wire _T_863 = |q_ff[19:0]; // @[lib.scala 428:35]
wire _T_865 = ~q_ff[20]; // @[lib.scala 428:40]
wire _T_867 = _T_863 ? _T_865 : q_ff[20]; // @[lib.scala 428:23]
wire _T_857 = |q_ff[18:0]; // @[lib.scala 428:35]
wire _T_859 = ~q_ff[19]; // @[lib.scala 428:40]
wire _T_861 = _T_857 ? _T_859 : q_ff[19]; // @[lib.scala 428:23]
wire _T_851 = |q_ff[17:0]; // @[lib.scala 428:35]
wire _T_853 = ~q_ff[18]; // @[lib.scala 428:40]
wire _T_855 = _T_851 ? _T_853 : q_ff[18]; // @[lib.scala 428:23]
wire _T_845 = |q_ff[16:0]; // @[lib.scala 428:35]
wire _T_847 = ~q_ff[17]; // @[lib.scala 428:40]
wire _T_849 = _T_845 ? _T_847 : q_ff[17]; // @[lib.scala 428:23]
wire _T_839 = |q_ff[15:0]; // @[lib.scala 428:35]
wire _T_841 = ~q_ff[16]; // @[lib.scala 428:40]
wire _T_843 = _T_839 ? _T_841 : q_ff[16]; // @[lib.scala 428:23]
wire [7:0] _T_954 = {_T_885,_T_879,_T_873,_T_867,_T_861,_T_855,_T_849,_T_843}; // @[lib.scala 430:14]
wire _T_833 = |q_ff[14:0]; // @[lib.scala 428:35]
wire _T_835 = ~q_ff[15]; // @[lib.scala 428:40]
wire _T_837 = _T_833 ? _T_835 : q_ff[15]; // @[lib.scala 428:23]
wire _T_827 = |q_ff[13:0]; // @[lib.scala 428:35]
wire _T_829 = ~q_ff[14]; // @[lib.scala 428:40]
wire _T_831 = _T_827 ? _T_829 : q_ff[14]; // @[lib.scala 428:23]
wire _T_821 = |q_ff[12:0]; // @[lib.scala 428:35]
wire _T_823 = ~q_ff[13]; // @[lib.scala 428:40]
wire _T_825 = _T_821 ? _T_823 : q_ff[13]; // @[lib.scala 428:23]
wire _T_815 = |q_ff[11:0]; // @[lib.scala 428:35]
wire _T_817 = ~q_ff[12]; // @[lib.scala 428:40]
wire _T_819 = _T_815 ? _T_817 : q_ff[12]; // @[lib.scala 428:23]
wire _T_809 = |q_ff[10:0]; // @[lib.scala 428:35]
wire _T_811 = ~q_ff[11]; // @[lib.scala 428:40]
wire _T_813 = _T_809 ? _T_811 : q_ff[11]; // @[lib.scala 428:23]
wire _T_803 = |q_ff[9:0]; // @[lib.scala 428:35]
wire _T_805 = ~q_ff[10]; // @[lib.scala 428:40]
wire _T_807 = _T_803 ? _T_805 : q_ff[10]; // @[lib.scala 428:23]
wire _T_797 = |q_ff[8:0]; // @[lib.scala 428:35]
wire _T_799 = ~q_ff[9]; // @[lib.scala 428:40]
wire _T_801 = _T_797 ? _T_799 : q_ff[9]; // @[lib.scala 428:23]
wire _T_791 = |q_ff[7:0]; // @[lib.scala 428:35]
wire _T_793 = ~q_ff[8]; // @[lib.scala 428:40]
wire _T_795 = _T_791 ? _T_793 : q_ff[8]; // @[lib.scala 428:23]
wire _T_785 = |q_ff[6:0]; // @[lib.scala 428:35]
wire _T_787 = ~q_ff[7]; // @[lib.scala 428:40]
wire _T_789 = _T_785 ? _T_787 : q_ff[7]; // @[lib.scala 428:23]
wire _T_779 = |q_ff[5:0]; // @[lib.scala 428:35]
wire _T_781 = ~q_ff[6]; // @[lib.scala 428:40]
wire _T_783 = _T_779 ? _T_781 : q_ff[6]; // @[lib.scala 428:23]
wire _T_773 = |q_ff[4:0]; // @[lib.scala 428:35]
wire _T_775 = ~q_ff[5]; // @[lib.scala 428:40]
wire _T_777 = _T_773 ? _T_775 : q_ff[5]; // @[lib.scala 428:23]
wire _T_767 = |q_ff[3:0]; // @[lib.scala 428:35]
wire _T_769 = ~q_ff[4]; // @[lib.scala 428:40]
wire _T_771 = _T_767 ? _T_769 : q_ff[4]; // @[lib.scala 428:23]
wire _T_761 = |q_ff[2:0]; // @[lib.scala 428:35]
wire _T_763 = ~q_ff[3]; // @[lib.scala 428:40]
wire _T_765 = _T_761 ? _T_763 : q_ff[3]; // @[lib.scala 428:23]
wire _T_755 = |q_ff[1:0]; // @[lib.scala 428:35]
wire _T_757 = ~q_ff[2]; // @[lib.scala 428:40]
wire _T_759 = _T_755 ? _T_757 : q_ff[2]; // @[lib.scala 428:23]
wire _T_749 = |q_ff[0]; // @[lib.scala 428:35]
wire _T_751 = ~q_ff[1]; // @[lib.scala 428:40]
wire _T_753 = _T_749 ? _T_751 : q_ff[1]; // @[lib.scala 428:23]
wire [6:0] _T_939 = {_T_789,_T_783,_T_777,_T_771,_T_765,_T_759,_T_753}; // @[lib.scala 430:14]
wire [14:0] _T_947 = {_T_837,_T_831,_T_825,_T_819,_T_813,_T_807,_T_801,_T_795,_T_939}; // @[lib.scala 430:14]
wire [30:0] _T_963 = {_T_933,_T_927,_T_921,_T_915,_T_909,_T_903,_T_897,_T_891,_T_954,_T_947}; // @[lib.scala 430:14]
wire [31:0] _T_965 = {_T_963,q_ff[0]}; // @[Cat.scala 29:58]
wire [31:0] dividend_eff = _T_744 ? _T_965 : q_ff[31:0]; // @[exu_div_ctl.scala 243:22]
wire [32:0] _T_1001 = run_state ? 33'h1ffffffff : 33'h0; // @[Bitwise.scala 72:12]
wire _T_1013 = _T_689 & rem_ff; // @[exu_div_ctl.scala 257:41]
reg [32:0] a_ff; // @[Reg.scala 27:20]
wire rem_correct = _T_1013 & a_ff[32]; // @[exu_div_ctl.scala 257:50]
wire [32:0] _T_986 = rem_correct ? a_ff : 33'h0; // @[Mux.scala 27:72]
wire _T_975 = ~rem_correct; // @[exu_div_ctl.scala 248:6]
wire _T_976 = ~shortq_enable_ff; // @[exu_div_ctl.scala 248:21]
wire _T_977 = _T_975 & _T_976; // @[exu_div_ctl.scala 248:19]
wire [32:0] _T_981 = {a_ff[31:0],q_ff[32]}; // @[Cat.scala 29:58]
wire [32:0] _T_987 = _T_977 ? _T_981 : 33'h0; // @[Mux.scala 27:72]
wire [32:0] _T_989 = _T_986 | _T_987; // @[Mux.scala 27:72]
wire _T_983 = _T_975 & shortq_enable_ff; // @[exu_div_ctl.scala 249:19]
wire [64:0] _T_971 = {33'h0,dividend_eff}; // @[Cat.scala 29:58]
wire [95:0] _GEN_16 = {{31'd0}, _T_971}; // @[exu_div_ctl.scala 245:47]
wire [95:0] _T_973 = _GEN_16 << shortq_shift_ff[4:0]; // @[exu_div_ctl.scala 245:47]
wire [64:0] a_eff_shift = _T_973[64:0]; // @[exu_div_ctl.scala 245:15]
wire [32:0] _T_988 = _T_983 ? a_eff_shift[64:32] : 33'h0; // @[Mux.scala 27:72]
wire [32:0] a_eff = _T_989 | _T_988; // @[Mux.scala 27:72]
wire [32:0] a_shift = _T_1001 & a_eff; // @[exu_div_ctl.scala 252:33]
wire _T_1010 = a_ff[32] | rem_correct; // @[exu_div_ctl.scala 256:21]
reg divisor_neg_ff; // @[Reg.scala 27:20]
wire m_already_comp = divisor_neg_ff & sign_ff; // @[exu_div_ctl.scala 254:48]
wire add = _T_1010 ^ m_already_comp; // @[exu_div_ctl.scala 256:36]
wire [32:0] _T_969 = ~m_ff; // @[exu_div_ctl.scala 244:35]
wire [32:0] m_eff = add ? m_ff : _T_969; // @[exu_div_ctl.scala 244:15]
wire [32:0] _T_1003 = a_shift + m_eff; // @[exu_div_ctl.scala 253:41]
wire _T_1004 = ~add; // @[exu_div_ctl.scala 253:65]
wire [32:0] _T_1005 = {32'h0,_T_1004}; // @[Cat.scala 29:58]
wire [32:0] _T_1007 = _T_1003 + _T_1005; // @[exu_div_ctl.scala 253:49]
wire [32:0] a_in = _T_1001 & _T_1007; // @[exu_div_ctl.scala 253:30]
wire _T_724 = ~a_in[32]; // @[exu_div_ctl.scala 239:85]
wire [32:0] _T_725 = {dividend_eff,_T_724}; // @[Cat.scala 29:58]
wire [63:0] _GEN_17 = {{31'd0}, _T_725}; // @[exu_div_ctl.scala 239:96]
wire [63:0] _T_727 = _GEN_17 << shortq_shift_ff[4:0]; // @[exu_div_ctl.scala 239:96]
wire _T_729 = ~_T_719; // @[exu_div_ctl.scala 240:18]
wire _T_730 = run_state & _T_729; // @[exu_div_ctl.scala 240:16]
wire [32:0] _T_735 = {q_ff[31:0],_T_724}; // @[Cat.scala 29:58]
wire [32:0] _T_736 = _T_716 ? _T_718 : 33'h0; // @[Mux.scala 27:72]
wire [63:0] _T_737 = _T_720 ? _T_727 : 64'h0; // @[Mux.scala 27:72]
wire [32:0] _T_738 = _T_730 ? _T_735 : 33'h0; // @[Mux.scala 27:72]
wire [63:0] _GEN_18 = {{31'd0}, _T_736}; // @[Mux.scala 27:72]
wire [63:0] _T_739 = _GEN_18 | _T_737; // @[Mux.scala 27:72]
wire [63:0] _GEN_19 = {{31'd0}, _T_738}; // @[Mux.scala 27:72]
wire [63:0] _T_740 = _T_739 | _GEN_19; // @[Mux.scala 27:72]
wire _T_743 = run_state & _T_701; // @[exu_div_ctl.scala 242:48]
wire qff_enable = io_valid_in | _T_743; // @[exu_div_ctl.scala 242:35]
wire _T_994 = count != 6'h21; // @[exu_div_ctl.scala 251:73]
wire _T_995 = _T_743 & _T_994; // @[exu_div_ctl.scala 251:64]
wire _T_996 = io_valid_in | _T_995; // @[exu_div_ctl.scala 251:34]
wire aff_enable = _T_996 | rem_correct; // @[exu_div_ctl.scala 251:89]
wire _T_1016 = dividend_neg_ff ^ divisor_neg_ff; // @[exu_div_ctl.scala 258:50]
wire _T_1017 = sign_ff & _T_1016; // @[exu_div_ctl.scala 258:31]
wire [31:0] q_ff_eff = _T_1017 ? _T_965 : q_ff[31:0]; // @[exu_div_ctl.scala 258:21]
wire _T_1245 = |a_ff[0]; // @[lib.scala 428:35]
wire _T_1247 = ~a_ff[1]; // @[lib.scala 428:40]
wire _T_1249 = _T_1245 ? _T_1247 : a_ff[1]; // @[lib.scala 428:23]
wire _T_1251 = |a_ff[1:0]; // @[lib.scala 428:35]
wire _T_1253 = ~a_ff[2]; // @[lib.scala 428:40]
wire _T_1255 = _T_1251 ? _T_1253 : a_ff[2]; // @[lib.scala 428:23]
wire _T_1257 = |a_ff[2:0]; // @[lib.scala 428:35]
wire _T_1259 = ~a_ff[3]; // @[lib.scala 428:40]
wire _T_1261 = _T_1257 ? _T_1259 : a_ff[3]; // @[lib.scala 428:23]
wire _T_1263 = |a_ff[3:0]; // @[lib.scala 428:35]
wire _T_1265 = ~a_ff[4]; // @[lib.scala 428:40]
wire _T_1267 = _T_1263 ? _T_1265 : a_ff[4]; // @[lib.scala 428:23]
wire _T_1269 = |a_ff[4:0]; // @[lib.scala 428:35]
wire _T_1271 = ~a_ff[5]; // @[lib.scala 428:40]
wire _T_1273 = _T_1269 ? _T_1271 : a_ff[5]; // @[lib.scala 428:23]
wire _T_1275 = |a_ff[5:0]; // @[lib.scala 428:35]
wire _T_1277 = ~a_ff[6]; // @[lib.scala 428:40]
wire _T_1279 = _T_1275 ? _T_1277 : a_ff[6]; // @[lib.scala 428:23]
wire _T_1281 = |a_ff[6:0]; // @[lib.scala 428:35]
wire _T_1283 = ~a_ff[7]; // @[lib.scala 428:40]
wire _T_1285 = _T_1281 ? _T_1283 : a_ff[7]; // @[lib.scala 428:23]
wire _T_1287 = |a_ff[7:0]; // @[lib.scala 428:35]
wire _T_1289 = ~a_ff[8]; // @[lib.scala 428:40]
wire _T_1291 = _T_1287 ? _T_1289 : a_ff[8]; // @[lib.scala 428:23]
wire _T_1293 = |a_ff[8:0]; // @[lib.scala 428:35]
wire _T_1295 = ~a_ff[9]; // @[lib.scala 428:40]
wire _T_1297 = _T_1293 ? _T_1295 : a_ff[9]; // @[lib.scala 428:23]
wire _T_1299 = |a_ff[9:0]; // @[lib.scala 428:35]
wire _T_1301 = ~a_ff[10]; // @[lib.scala 428:40]
wire _T_1303 = _T_1299 ? _T_1301 : a_ff[10]; // @[lib.scala 428:23]
wire _T_1305 = |a_ff[10:0]; // @[lib.scala 428:35]
wire _T_1307 = ~a_ff[11]; // @[lib.scala 428:40]
wire _T_1309 = _T_1305 ? _T_1307 : a_ff[11]; // @[lib.scala 428:23]
wire _T_1311 = |a_ff[11:0]; // @[lib.scala 428:35]
wire _T_1313 = ~a_ff[12]; // @[lib.scala 428:40]
wire _T_1315 = _T_1311 ? _T_1313 : a_ff[12]; // @[lib.scala 428:23]
wire _T_1317 = |a_ff[12:0]; // @[lib.scala 428:35]
wire _T_1319 = ~a_ff[13]; // @[lib.scala 428:40]
wire _T_1321 = _T_1317 ? _T_1319 : a_ff[13]; // @[lib.scala 428:23]
wire _T_1323 = |a_ff[13:0]; // @[lib.scala 428:35]
wire _T_1325 = ~a_ff[14]; // @[lib.scala 428:40]
wire _T_1327 = _T_1323 ? _T_1325 : a_ff[14]; // @[lib.scala 428:23]
wire _T_1329 = |a_ff[14:0]; // @[lib.scala 428:35]
wire _T_1331 = ~a_ff[15]; // @[lib.scala 428:40]
wire _T_1333 = _T_1329 ? _T_1331 : a_ff[15]; // @[lib.scala 428:23]
wire _T_1335 = |a_ff[15:0]; // @[lib.scala 428:35]
wire _T_1337 = ~a_ff[16]; // @[lib.scala 428:40]
wire _T_1339 = _T_1335 ? _T_1337 : a_ff[16]; // @[lib.scala 428:23]
wire _T_1341 = |a_ff[16:0]; // @[lib.scala 428:35]
wire _T_1343 = ~a_ff[17]; // @[lib.scala 428:40]
wire _T_1345 = _T_1341 ? _T_1343 : a_ff[17]; // @[lib.scala 428:23]
wire _T_1347 = |a_ff[17:0]; // @[lib.scala 428:35]
wire _T_1349 = ~a_ff[18]; // @[lib.scala 428:40]
wire _T_1351 = _T_1347 ? _T_1349 : a_ff[18]; // @[lib.scala 428:23]
wire _T_1353 = |a_ff[18:0]; // @[lib.scala 428:35]
wire _T_1355 = ~a_ff[19]; // @[lib.scala 428:40]
wire _T_1357 = _T_1353 ? _T_1355 : a_ff[19]; // @[lib.scala 428:23]
wire _T_1359 = |a_ff[19:0]; // @[lib.scala 428:35]
wire _T_1361 = ~a_ff[20]; // @[lib.scala 428:40]
wire _T_1363 = _T_1359 ? _T_1361 : a_ff[20]; // @[lib.scala 428:23]
wire _T_1365 = |a_ff[20:0]; // @[lib.scala 428:35]
wire _T_1367 = ~a_ff[21]; // @[lib.scala 428:40]
wire _T_1369 = _T_1365 ? _T_1367 : a_ff[21]; // @[lib.scala 428:23]
wire _T_1371 = |a_ff[21:0]; // @[lib.scala 428:35]
wire _T_1373 = ~a_ff[22]; // @[lib.scala 428:40]
wire _T_1375 = _T_1371 ? _T_1373 : a_ff[22]; // @[lib.scala 428:23]
wire _T_1377 = |a_ff[22:0]; // @[lib.scala 428:35]
wire _T_1379 = ~a_ff[23]; // @[lib.scala 428:40]
wire _T_1381 = _T_1377 ? _T_1379 : a_ff[23]; // @[lib.scala 428:23]
wire _T_1383 = |a_ff[23:0]; // @[lib.scala 428:35]
wire _T_1385 = ~a_ff[24]; // @[lib.scala 428:40]
wire _T_1387 = _T_1383 ? _T_1385 : a_ff[24]; // @[lib.scala 428:23]
wire _T_1389 = |a_ff[24:0]; // @[lib.scala 428:35]
wire _T_1391 = ~a_ff[25]; // @[lib.scala 428:40]
wire _T_1393 = _T_1389 ? _T_1391 : a_ff[25]; // @[lib.scala 428:23]
wire _T_1395 = |a_ff[25:0]; // @[lib.scala 428:35]
wire _T_1397 = ~a_ff[26]; // @[lib.scala 428:40]
wire _T_1399 = _T_1395 ? _T_1397 : a_ff[26]; // @[lib.scala 428:23]
wire _T_1401 = |a_ff[26:0]; // @[lib.scala 428:35]
wire _T_1403 = ~a_ff[27]; // @[lib.scala 428:40]
wire _T_1405 = _T_1401 ? _T_1403 : a_ff[27]; // @[lib.scala 428:23]
wire _T_1407 = |a_ff[27:0]; // @[lib.scala 428:35]
wire _T_1409 = ~a_ff[28]; // @[lib.scala 428:40]
wire _T_1411 = _T_1407 ? _T_1409 : a_ff[28]; // @[lib.scala 428:23]
wire _T_1413 = |a_ff[28:0]; // @[lib.scala 428:35]
wire _T_1415 = ~a_ff[29]; // @[lib.scala 428:40]
wire _T_1417 = _T_1413 ? _T_1415 : a_ff[29]; // @[lib.scala 428:23]
wire _T_1419 = |a_ff[29:0]; // @[lib.scala 428:35]
wire _T_1421 = ~a_ff[30]; // @[lib.scala 428:40]
wire _T_1423 = _T_1419 ? _T_1421 : a_ff[30]; // @[lib.scala 428:23]
wire _T_1425 = |a_ff[30:0]; // @[lib.scala 428:35]
wire _T_1427 = ~a_ff[31]; // @[lib.scala 428:40]
wire _T_1429 = _T_1425 ? _T_1427 : a_ff[31]; // @[lib.scala 428:23]
wire [6:0] _T_1435 = {_T_1285,_T_1279,_T_1273,_T_1267,_T_1261,_T_1255,_T_1249}; // @[lib.scala 430:14]
wire [14:0] _T_1443 = {_T_1333,_T_1327,_T_1321,_T_1315,_T_1309,_T_1303,_T_1297,_T_1291,_T_1435}; // @[lib.scala 430:14]
wire [7:0] _T_1450 = {_T_1381,_T_1375,_T_1369,_T_1363,_T_1357,_T_1351,_T_1345,_T_1339}; // @[lib.scala 430:14]
wire [30:0] _T_1459 = {_T_1429,_T_1423,_T_1417,_T_1411,_T_1405,_T_1399,_T_1393,_T_1387,_T_1450,_T_1443}; // @[lib.scala 430:14]
wire [31:0] _T_1461 = {_T_1459,a_ff[0]}; // @[Cat.scala 29:58]
wire [31:0] a_ff_eff = _T_744 ? _T_1461 : a_ff[31:0]; // @[exu_div_ctl.scala 259:21]
reg smallnum_case_ff; // @[Reg.scala 27:20]
reg [3:0] smallnum_ff; // @[Reg.scala 27:20]
wire [31:0] _T_1464 = {28'h0,smallnum_ff}; // @[Cat.scala 29:58]
wire _T_1466 = ~smallnum_case_ff; // @[exu_div_ctl.scala 264:6]
wire _T_1468 = _T_1466 & _T_9; // @[exu_div_ctl.scala 264:24]
wire [31:0] _T_1470 = smallnum_case_ff ? _T_1464 : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_1471 = rem_ff ? a_ff_eff : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_1472 = _T_1468 ? q_ff_eff : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_1473 = _T_1470 | _T_1471; // @[Mux.scala 27:72]
wire _T_1477 = io_valid_in & _T; // @[exu_div_ctl.scala 266:38]
wire _T_1481 = finish & _T; // @[exu_div_ctl.scala 267:32]
wire _T_1489 = io_valid_in & io_dividend_in[31]; // @[exu_div_ctl.scala 270:44]
wire _T_1490 = ~io_valid_in; // @[exu_div_ctl.scala 270:69]
wire _T_1491 = _T_1490 & dividend_neg_ff; // @[exu_div_ctl.scala 270:82]
wire _T_1492 = _T_1489 | _T_1491; // @[exu_div_ctl.scala 270:66]
wire _T_1496 = io_valid_in & io_divisor_in[31]; // @[exu_div_ctl.scala 271:43]
wire _T_1498 = _T_1490 & divisor_neg_ff; // @[exu_div_ctl.scala 271:80]
wire _T_1499 = _T_1496 | _T_1498; // @[exu_div_ctl.scala 271:64]
wire _T_1502 = io_valid_in & sign_eff; // @[exu_div_ctl.scala 272:36]
wire _T_1504 = _T_1490 & sign_ff; // @[exu_div_ctl.scala 272:64]
wire _T_1505 = _T_1502 | _T_1504; // @[exu_div_ctl.scala 272:48]
wire _T_1508 = io_valid_in & io_rem_in; // @[exu_div_ctl.scala 273:37]
wire _T_1510 = _T_1490 & rem_ff; // @[exu_div_ctl.scala 273:66]
wire _T_1511 = _T_1508 | _T_1510; // @[exu_div_ctl.scala 273:50]
wire [32:0] q_in = _T_740[32:0]; // @[exu_div_ctl.scala 237:8]
wire _T_1527 = io_signed_in & io_divisor_in[31]; // @[exu_div_ctl.scala 281:35]
wire [32:0] _T_1529 = {_T_1527,io_divisor_in}; // @[Cat.scala 29:58]
rvclkhdr rvclkhdr ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_io_clk),
.io_en(rvclkhdr_io_en)
);
rvclkhdr rvclkhdr_1 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_1_io_clk),
.io_en(rvclkhdr_1_io_en)
);
rvclkhdr rvclkhdr_2 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_2_io_clk),
.io_en(rvclkhdr_2_io_en)
);
rvclkhdr rvclkhdr_3 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_3_io_clk),
.io_en(rvclkhdr_3_io_en)
);
rvclkhdr rvclkhdr_4 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_4_io_clk),
.io_en(rvclkhdr_4_io_en)
);
rvclkhdr rvclkhdr_5 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_5_io_clk),
.io_en(rvclkhdr_5_io_en)
);
rvclkhdr rvclkhdr_6 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_6_io_clk),
.io_en(rvclkhdr_6_io_en)
);
rvclkhdr rvclkhdr_7 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_7_io_clk),
.io_en(rvclkhdr_7_io_en)
);
rvclkhdr rvclkhdr_8 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_8_io_clk),
.io_en(rvclkhdr_8_io_en)
);
rvclkhdr rvclkhdr_9 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_9_io_clk),
.io_en(rvclkhdr_9_io_en)
);
rvclkhdr rvclkhdr_10 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_10_io_clk),
.io_en(rvclkhdr_10_io_en)
);
rvclkhdr rvclkhdr_11 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_11_io_clk),
.io_en(rvclkhdr_11_io_en)
);
rvclkhdr rvclkhdr_12 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_12_io_clk),
.io_en(rvclkhdr_12_io_en)
);
rvclkhdr rvclkhdr_13 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_13_io_clk),
.io_en(rvclkhdr_13_io_en)
);
rvclkhdr rvclkhdr_14 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_14_io_clk),
.io_en(rvclkhdr_14_io_en)
);
assign io_data_out = _T_1473 | _T_1472; // @[exu_div_ctl.scala 261:15]
assign io_valid_out = finish_ff & _T; // @[exu_div_ctl.scala 234:17]
assign rvclkhdr_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_io_en = _T_692 | finish_ff; // @[lib.scala 393:17]
assign rvclkhdr_1_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_1_io_en = _T_692 | finish_ff; // @[lib.scala 393:17]
assign rvclkhdr_2_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_2_io_en = _T_692 | finish_ff; // @[lib.scala 393:17]
assign rvclkhdr_3_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_3_io_en = _T_692 | finish_ff; // @[lib.scala 393:17]
assign rvclkhdr_4_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_4_io_en = _T_692 | finish_ff; // @[lib.scala 393:17]
assign rvclkhdr_5_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_5_io_en = _T_692 | finish_ff; // @[lib.scala 393:17]
assign rvclkhdr_6_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_6_io_en = _T_692 | finish_ff; // @[lib.scala 393:17]
assign rvclkhdr_7_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_7_io_en = _T_692 | finish_ff; // @[lib.scala 393:17]
assign rvclkhdr_8_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_8_io_en = _T_692 | finish_ff; // @[lib.scala 393:17]
assign rvclkhdr_9_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_9_io_en = _T_692 | finish_ff; // @[lib.scala 393:17]
assign rvclkhdr_10_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_10_io_en = _T_692 | finish_ff; // @[lib.scala 393:17]
assign rvclkhdr_11_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_11_io_en = _T_692 | finish_ff; // @[lib.scala 393:17]
assign rvclkhdr_12_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_12_io_en = io_valid_in | _T_743; // @[lib.scala 393:17]
assign rvclkhdr_13_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_13_io_en = _T_996 | rem_correct; // @[lib.scala 393:17]
assign rvclkhdr_14_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_14_io_en = io_valid_in; // @[lib.scala 393:17]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
valid_ff_x = _RAND_0[0:0];
_RAND_1 = {2{`RANDOM}};
q_ff = _RAND_1[32:0];
_RAND_2 = {2{`RANDOM}};
m_ff = _RAND_2[32:0];
_RAND_3 = {1{`RANDOM}};
rem_ff = _RAND_3[0:0];
_RAND_4 = {1{`RANDOM}};
sign_ff = _RAND_4[0:0];
_RAND_5 = {1{`RANDOM}};
_T_1521 = _RAND_5[5:0];
_RAND_6 = {1{`RANDOM}};
count = _RAND_6[5:0];
_RAND_7 = {1{`RANDOM}};
run_state = _RAND_7[0:0];
_RAND_8 = {1{`RANDOM}};
finish_ff = _RAND_8[0:0];
_RAND_9 = {1{`RANDOM}};
shortq_enable_ff = _RAND_9[0:0];
_RAND_10 = {1{`RANDOM}};
dividend_neg_ff = _RAND_10[0:0];
_RAND_11 = {2{`RANDOM}};
a_ff = _RAND_11[32:0];
_RAND_12 = {1{`RANDOM}};
divisor_neg_ff = _RAND_12[0:0];
_RAND_13 = {1{`RANDOM}};
smallnum_case_ff = _RAND_13[0:0];
_RAND_14 = {1{`RANDOM}};
smallnum_ff = _RAND_14[3:0];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
valid_ff_x = 1'h0;
end
if (reset) begin
q_ff = 33'h0;
end
if (reset) begin
m_ff = 33'h0;
end
if (reset) begin
rem_ff = 1'h0;
end
if (reset) begin
sign_ff = 1'h0;
end
if (reset) begin
_T_1521 = 6'h0;
end
if (reset) begin
count = 6'h0;
end
if (reset) begin
run_state = 1'h0;
end
if (reset) begin
finish_ff = 1'h0;
end
if (reset) begin
shortq_enable_ff = 1'h0;
end
if (reset) begin
dividend_neg_ff = 1'h0;
end
if (reset) begin
a_ff = 33'h0;
end
if (reset) begin
divisor_neg_ff = 1'h0;
end
if (reset) begin
smallnum_case_ff = 1'h0;
end
if (reset) begin
smallnum_ff = 4'h0;
end
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
always @(posedge clock or posedge reset) begin
if (reset) begin
valid_ff_x <= 1'h0;
end else if (div_clken) begin
valid_ff_x <= _T_1477;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
q_ff <= 33'h0;
end else if (qff_enable) begin
q_ff <= q_in;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
m_ff <= 33'h0;
end else if (io_valid_in) begin
m_ff <= _T_1529;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
rem_ff <= 1'h0;
end else if (div_clken) begin
rem_ff <= _T_1511;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
sign_ff <= 1'h0;
end else if (div_clken) begin
sign_ff <= _T_1505;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
_T_1521 <= 6'h0;
end else if (div_clken) begin
_T_1521 <= shortq_shift;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
count <= 6'h0;
end else if (div_clken) begin
count <= count_in;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
run_state <= 1'h0;
end else if (div_clken) begin
run_state <= run_in;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
finish_ff <= 1'h0;
end else if (div_clken) begin
finish_ff <= _T_1481;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
shortq_enable_ff <= 1'h0;
end else if (div_clken) begin
shortq_enable_ff <= shortq_enable;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
dividend_neg_ff <= 1'h0;
end else if (div_clken) begin
dividend_neg_ff <= _T_1492;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
a_ff <= 33'h0;
end else if (aff_enable) begin
a_ff <= a_in;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
divisor_neg_ff <= 1'h0;
end else if (div_clken) begin
divisor_neg_ff <= _T_1499;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
smallnum_case_ff <= 1'h0;
end else if (div_clken) begin
smallnum_case_ff <= smallnum_case;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
smallnum_ff <= 4'h0;
end else if (div_clken) begin
smallnum_ff <= smallnum;
end
end
endmodule
module exu_div_ctl(
input clock,
input reset,
input io_scan_mode,
input [31:0] io_dividend,
input [31:0] io_divisor,
output [31:0] io_exu_div_result,
output io_exu_div_wren,
input io_dec_div_div_p_valid,
input io_dec_div_div_p_bits_unsign,
input io_dec_div_div_p_bits_rem,
input io_dec_div_dec_div_cancel
);
wire divider_old_clock; // @[exu_div_ctl.scala 23:27]
wire divider_old_reset; // @[exu_div_ctl.scala 23:27]
wire divider_old_io_cancel; // @[exu_div_ctl.scala 23:27]
wire divider_old_io_valid_in; // @[exu_div_ctl.scala 23:27]
wire divider_old_io_signed_in; // @[exu_div_ctl.scala 23:27]
wire divider_old_io_rem_in; // @[exu_div_ctl.scala 23:27]
wire [31:0] divider_old_io_dividend_in; // @[exu_div_ctl.scala 23:27]
wire [31:0] divider_old_io_divisor_in; // @[exu_div_ctl.scala 23:27]
wire [31:0] divider_old_io_data_out; // @[exu_div_ctl.scala 23:27]
wire divider_old_io_valid_out; // @[exu_div_ctl.scala 23:27]
wire [31:0] _T_1 = io_exu_div_wren ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
wire [31:0] out_raw = divider_old_io_data_out; // @[exu_div_ctl.scala 31:27]
el2_exu_div_existing_1bit_cheapshortq divider_old ( // @[exu_div_ctl.scala 23:27]
.clock(divider_old_clock),
.reset(divider_old_reset),
.io_cancel(divider_old_io_cancel),
.io_valid_in(divider_old_io_valid_in),
.io_signed_in(divider_old_io_signed_in),
.io_rem_in(divider_old_io_rem_in),
.io_dividend_in(divider_old_io_dividend_in),
.io_divisor_in(divider_old_io_divisor_in),
.io_data_out(divider_old_io_data_out),
.io_valid_out(divider_old_io_valid_out)
);
assign io_exu_div_result = _T_1 & out_raw; // @[exu_div_ctl.scala 21:21]
assign io_exu_div_wren = divider_old_io_valid_out; // @[exu_div_ctl.scala 32:27]
assign divider_old_clock = clock;
assign divider_old_reset = reset;
assign divider_old_io_cancel = io_dec_div_dec_div_cancel; // @[exu_div_ctl.scala 25:31]
assign divider_old_io_valid_in = io_dec_div_div_p_valid; // @[exu_div_ctl.scala 26:31]
assign divider_old_io_signed_in = ~io_dec_div_div_p_bits_unsign; // @[exu_div_ctl.scala 27:31]
assign divider_old_io_rem_in = io_dec_div_div_p_bits_rem; // @[exu_div_ctl.scala 28:31]
assign divider_old_io_dividend_in = io_dividend; // @[exu_div_ctl.scala 29:31]
assign divider_old_io_divisor_in = io_divisor; // @[exu_div_ctl.scala 30:31]
endmodule

30
exu_div_new_1bit_fullshortq.anno.json Normal file
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@ -0,0 +1,30 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~exu_div_new_1bit_fullshortq|exu_div_new_1bit_fullshortq>io_valid_out",
"sources":[
"~exu_div_new_1bit_fullshortq|exu_div_new_1bit_fullshortq>io_cancel"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"exu_div_new_1bit_fullshortq.gated_latch",
"resourceId":"/vsrc/gated_latch.sv"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"exu_div_new_1bit_fullshortq"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

2110
exu_div_new_1bit_fullshortq.fir Normal file
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File diff suppressed because it is too large Load Diff

904
exu_div_new_1bit_fullshortq.v Normal file
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@ -0,0 +1,904 @@
module exu_div_cls(
input [32:0] io_operand,
output [4:0] io_cls
);
wire _T_3 = io_operand[31:30] == 2'h1; // @[exu_div_ctl.scala 510:63]
wire _T_5 = io_operand[31:29] == 3'h1; // @[exu_div_ctl.scala 510:63]
wire _T_7 = io_operand[31:28] == 4'h1; // @[exu_div_ctl.scala 510:63]
wire _T_9 = io_operand[31:27] == 5'h1; // @[exu_div_ctl.scala 510:63]
wire _T_11 = io_operand[31:26] == 6'h1; // @[exu_div_ctl.scala 510:63]
wire _T_13 = io_operand[31:25] == 7'h1; // @[exu_div_ctl.scala 510:63]
wire _T_15 = io_operand[31:24] == 8'h1; // @[exu_div_ctl.scala 510:63]
wire _T_17 = io_operand[31:23] == 9'h1; // @[exu_div_ctl.scala 510:63]
wire _T_19 = io_operand[31:22] == 10'h1; // @[exu_div_ctl.scala 510:63]
wire _T_21 = io_operand[31:21] == 11'h1; // @[exu_div_ctl.scala 510:63]
wire _T_23 = io_operand[31:20] == 12'h1; // @[exu_div_ctl.scala 510:63]
wire _T_25 = io_operand[31:19] == 13'h1; // @[exu_div_ctl.scala 510:63]
wire _T_27 = io_operand[31:18] == 14'h1; // @[exu_div_ctl.scala 510:63]
wire _T_29 = io_operand[31:17] == 15'h1; // @[exu_div_ctl.scala 510:63]
wire _T_31 = io_operand[31:16] == 16'h1; // @[exu_div_ctl.scala 510:63]
wire _T_33 = io_operand[31:15] == 17'h1; // @[exu_div_ctl.scala 510:63]
wire _T_35 = io_operand[31:14] == 18'h1; // @[exu_div_ctl.scala 510:63]
wire _T_37 = io_operand[31:13] == 19'h1; // @[exu_div_ctl.scala 510:63]
wire _T_39 = io_operand[31:12] == 20'h1; // @[exu_div_ctl.scala 510:63]
wire _T_41 = io_operand[31:11] == 21'h1; // @[exu_div_ctl.scala 510:63]
wire _T_43 = io_operand[31:10] == 22'h1; // @[exu_div_ctl.scala 510:63]
wire _T_45 = io_operand[31:9] == 23'h1; // @[exu_div_ctl.scala 510:63]
wire _T_47 = io_operand[31:8] == 24'h1; // @[exu_div_ctl.scala 510:63]
wire _T_49 = io_operand[31:7] == 25'h1; // @[exu_div_ctl.scala 510:63]
wire _T_51 = io_operand[31:6] == 26'h1; // @[exu_div_ctl.scala 510:63]
wire _T_53 = io_operand[31:5] == 27'h1; // @[exu_div_ctl.scala 510:63]
wire _T_55 = io_operand[31:4] == 28'h1; // @[exu_div_ctl.scala 510:63]
wire _T_57 = io_operand[31:3] == 29'h1; // @[exu_div_ctl.scala 510:63]
wire _T_59 = io_operand[31:2] == 30'h1; // @[exu_div_ctl.scala 510:63]
wire _T_61 = io_operand[31:1] == 31'h1; // @[exu_div_ctl.scala 510:63]
wire _T_63 = io_operand[31:0] == 32'h1; // @[exu_div_ctl.scala 510:63]
wire [1:0] _T_66 = _T_5 ? 2'h2 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_67 = _T_7 ? 2'h3 : 2'h0; // @[Mux.scala 27:72]
wire [2:0] _T_68 = _T_9 ? 3'h4 : 3'h0; // @[Mux.scala 27:72]
wire [2:0] _T_69 = _T_11 ? 3'h5 : 3'h0; // @[Mux.scala 27:72]
wire [2:0] _T_70 = _T_13 ? 3'h6 : 3'h0; // @[Mux.scala 27:72]
wire [2:0] _T_71 = _T_15 ? 3'h7 : 3'h0; // @[Mux.scala 27:72]
wire [3:0] _T_72 = _T_17 ? 4'h8 : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_73 = _T_19 ? 4'h9 : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_74 = _T_21 ? 4'ha : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_75 = _T_23 ? 4'hb : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_76 = _T_25 ? 4'hc : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_77 = _T_27 ? 4'hd : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_78 = _T_29 ? 4'he : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_79 = _T_31 ? 4'hf : 4'h0; // @[Mux.scala 27:72]
wire [4:0] _T_80 = _T_33 ? 5'h10 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_81 = _T_35 ? 5'h11 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_82 = _T_37 ? 5'h12 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_83 = _T_39 ? 5'h13 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_84 = _T_41 ? 5'h14 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_85 = _T_43 ? 5'h15 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_86 = _T_45 ? 5'h16 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_87 = _T_47 ? 5'h17 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_88 = _T_49 ? 5'h18 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_89 = _T_51 ? 5'h19 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_90 = _T_53 ? 5'h1a : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_91 = _T_55 ? 5'h1b : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_92 = _T_57 ? 5'h1c : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_93 = _T_59 ? 5'h1d : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_94 = _T_61 ? 5'h1e : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_95 = _T_63 ? 5'h1f : 5'h0; // @[Mux.scala 27:72]
wire [1:0] _GEN_1 = {{1'd0}, _T_3}; // @[Mux.scala 27:72]
wire [1:0] _T_97 = _GEN_1 | _T_66; // @[Mux.scala 27:72]
wire [1:0] _T_98 = _T_97 | _T_67; // @[Mux.scala 27:72]
wire [2:0] _GEN_2 = {{1'd0}, _T_98}; // @[Mux.scala 27:72]
wire [2:0] _T_99 = _GEN_2 | _T_68; // @[Mux.scala 27:72]
wire [2:0] _T_100 = _T_99 | _T_69; // @[Mux.scala 27:72]
wire [2:0] _T_101 = _T_100 | _T_70; // @[Mux.scala 27:72]
wire [2:0] _T_102 = _T_101 | _T_71; // @[Mux.scala 27:72]
wire [3:0] _GEN_3 = {{1'd0}, _T_102}; // @[Mux.scala 27:72]
wire [3:0] _T_103 = _GEN_3 | _T_72; // @[Mux.scala 27:72]
wire [3:0] _T_104 = _T_103 | _T_73; // @[Mux.scala 27:72]
wire [3:0] _T_105 = _T_104 | _T_74; // @[Mux.scala 27:72]
wire [3:0] _T_106 = _T_105 | _T_75; // @[Mux.scala 27:72]
wire [3:0] _T_107 = _T_106 | _T_76; // @[Mux.scala 27:72]
wire [3:0] _T_108 = _T_107 | _T_77; // @[Mux.scala 27:72]
wire [3:0] _T_109 = _T_108 | _T_78; // @[Mux.scala 27:72]
wire [3:0] _T_110 = _T_109 | _T_79; // @[Mux.scala 27:72]
wire [4:0] _GEN_4 = {{1'd0}, _T_110}; // @[Mux.scala 27:72]
wire [4:0] _T_111 = _GEN_4 | _T_80; // @[Mux.scala 27:72]
wire [4:0] _T_112 = _T_111 | _T_81; // @[Mux.scala 27:72]
wire [4:0] _T_113 = _T_112 | _T_82; // @[Mux.scala 27:72]
wire [4:0] _T_114 = _T_113 | _T_83; // @[Mux.scala 27:72]
wire [4:0] _T_115 = _T_114 | _T_84; // @[Mux.scala 27:72]
wire [4:0] _T_116 = _T_115 | _T_85; // @[Mux.scala 27:72]
wire [4:0] _T_117 = _T_116 | _T_86; // @[Mux.scala 27:72]
wire [4:0] _T_118 = _T_117 | _T_87; // @[Mux.scala 27:72]
wire [4:0] _T_119 = _T_118 | _T_88; // @[Mux.scala 27:72]
wire [4:0] _T_120 = _T_119 | _T_89; // @[Mux.scala 27:72]
wire [4:0] _T_121 = _T_120 | _T_90; // @[Mux.scala 27:72]
wire [4:0] _T_122 = _T_121 | _T_91; // @[Mux.scala 27:72]
wire [4:0] _T_123 = _T_122 | _T_92; // @[Mux.scala 27:72]
wire [4:0] _T_124 = _T_123 | _T_93; // @[Mux.scala 27:72]
wire [4:0] _T_125 = _T_124 | _T_94; // @[Mux.scala 27:72]
wire [4:0] cls_zeros = _T_125 | _T_95; // @[Mux.scala 27:72]
wire _T_129 = io_operand[31:0] == 32'hffffffff; // @[exu_div_ctl.scala 512:25]
wire _T_137 = io_operand[31:29] == 3'h6; // @[exu_div_ctl.scala 513:76]
wire _T_142 = io_operand[31:28] == 4'he; // @[exu_div_ctl.scala 513:76]
wire _T_147 = io_operand[31:27] == 5'h1e; // @[exu_div_ctl.scala 513:76]
wire _T_152 = io_operand[31:26] == 6'h3e; // @[exu_div_ctl.scala 513:76]
wire _T_157 = io_operand[31:25] == 7'h7e; // @[exu_div_ctl.scala 513:76]
wire _T_162 = io_operand[31:24] == 8'hfe; // @[exu_div_ctl.scala 513:76]
wire _T_167 = io_operand[31:23] == 9'h1fe; // @[exu_div_ctl.scala 513:76]
wire _T_172 = io_operand[31:22] == 10'h3fe; // @[exu_div_ctl.scala 513:76]
wire _T_177 = io_operand[31:21] == 11'h7fe; // @[exu_div_ctl.scala 513:76]
wire _T_182 = io_operand[31:20] == 12'hffe; // @[exu_div_ctl.scala 513:76]
wire _T_187 = io_operand[31:19] == 13'h1ffe; // @[exu_div_ctl.scala 513:76]
wire _T_192 = io_operand[31:18] == 14'h3ffe; // @[exu_div_ctl.scala 513:76]
wire _T_197 = io_operand[31:17] == 15'h7ffe; // @[exu_div_ctl.scala 513:76]
wire _T_202 = io_operand[31:16] == 16'hfffe; // @[exu_div_ctl.scala 513:76]
wire _T_207 = io_operand[31:15] == 17'h1fffe; // @[exu_div_ctl.scala 513:76]
wire _T_212 = io_operand[31:14] == 18'h3fffe; // @[exu_div_ctl.scala 513:76]
wire _T_217 = io_operand[31:13] == 19'h7fffe; // @[exu_div_ctl.scala 513:76]
wire _T_222 = io_operand[31:12] == 20'hffffe; // @[exu_div_ctl.scala 513:76]
wire _T_227 = io_operand[31:11] == 21'h1ffffe; // @[exu_div_ctl.scala 513:76]
wire _T_232 = io_operand[31:10] == 22'h3ffffe; // @[exu_div_ctl.scala 513:76]
wire _T_237 = io_operand[31:9] == 23'h7ffffe; // @[exu_div_ctl.scala 513:76]
wire _T_242 = io_operand[31:8] == 24'hfffffe; // @[exu_div_ctl.scala 513:76]
wire _T_247 = io_operand[31:7] == 25'h1fffffe; // @[exu_div_ctl.scala 513:76]
wire _T_252 = io_operand[31:6] == 26'h3fffffe; // @[exu_div_ctl.scala 513:76]
wire _T_257 = io_operand[31:5] == 27'h7fffffe; // @[exu_div_ctl.scala 513:76]
wire _T_262 = io_operand[31:4] == 28'hffffffe; // @[exu_div_ctl.scala 513:76]
wire _T_267 = io_operand[31:3] == 29'h1ffffffe; // @[exu_div_ctl.scala 513:76]
wire _T_272 = io_operand[31:2] == 30'h3ffffffe; // @[exu_div_ctl.scala 513:76]
wire _T_277 = io_operand[31:1] == 31'h7ffffffe; // @[exu_div_ctl.scala 513:76]
wire _T_282 = io_operand[31:0] == 32'hfffffffe; // @[exu_div_ctl.scala 513:76]
wire [1:0] _T_286 = _T_142 ? 2'h2 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_287 = _T_147 ? 2'h3 : 2'h0; // @[Mux.scala 27:72]
wire [2:0] _T_288 = _T_152 ? 3'h4 : 3'h0; // @[Mux.scala 27:72]
wire [2:0] _T_289 = _T_157 ? 3'h5 : 3'h0; // @[Mux.scala 27:72]
wire [2:0] _T_290 = _T_162 ? 3'h6 : 3'h0; // @[Mux.scala 27:72]
wire [2:0] _T_291 = _T_167 ? 3'h7 : 3'h0; // @[Mux.scala 27:72]
wire [3:0] _T_292 = _T_172 ? 4'h8 : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_293 = _T_177 ? 4'h9 : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_294 = _T_182 ? 4'ha : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_295 = _T_187 ? 4'hb : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_296 = _T_192 ? 4'hc : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_297 = _T_197 ? 4'hd : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_298 = _T_202 ? 4'he : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_299 = _T_207 ? 4'hf : 4'h0; // @[Mux.scala 27:72]
wire [4:0] _T_300 = _T_212 ? 5'h10 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_301 = _T_217 ? 5'h11 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_302 = _T_222 ? 5'h12 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_303 = _T_227 ? 5'h13 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_304 = _T_232 ? 5'h14 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_305 = _T_237 ? 5'h15 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_306 = _T_242 ? 5'h16 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_307 = _T_247 ? 5'h17 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_308 = _T_252 ? 5'h18 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_309 = _T_257 ? 5'h19 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_310 = _T_262 ? 5'h1a : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_311 = _T_267 ? 5'h1b : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_312 = _T_272 ? 5'h1c : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_313 = _T_277 ? 5'h1d : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_314 = _T_282 ? 5'h1e : 5'h0; // @[Mux.scala 27:72]
wire [1:0] _GEN_5 = {{1'd0}, _T_137}; // @[Mux.scala 27:72]
wire [1:0] _T_316 = _GEN_5 | _T_286; // @[Mux.scala 27:72]
wire [1:0] _T_317 = _T_316 | _T_287; // @[Mux.scala 27:72]
wire [2:0] _GEN_6 = {{1'd0}, _T_317}; // @[Mux.scala 27:72]
wire [2:0] _T_318 = _GEN_6 | _T_288; // @[Mux.scala 27:72]
wire [2:0] _T_319 = _T_318 | _T_289; // @[Mux.scala 27:72]
wire [2:0] _T_320 = _T_319 | _T_290; // @[Mux.scala 27:72]
wire [2:0] _T_321 = _T_320 | _T_291; // @[Mux.scala 27:72]
wire [3:0] _GEN_7 = {{1'd0}, _T_321}; // @[Mux.scala 27:72]
wire [3:0] _T_322 = _GEN_7 | _T_292; // @[Mux.scala 27:72]
wire [3:0] _T_323 = _T_322 | _T_293; // @[Mux.scala 27:72]
wire [3:0] _T_324 = _T_323 | _T_294; // @[Mux.scala 27:72]
wire [3:0] _T_325 = _T_324 | _T_295; // @[Mux.scala 27:72]
wire [3:0] _T_326 = _T_325 | _T_296; // @[Mux.scala 27:72]
wire [3:0] _T_327 = _T_326 | _T_297; // @[Mux.scala 27:72]
wire [3:0] _T_328 = _T_327 | _T_298; // @[Mux.scala 27:72]
wire [3:0] _T_329 = _T_328 | _T_299; // @[Mux.scala 27:72]
wire [4:0] _GEN_8 = {{1'd0}, _T_329}; // @[Mux.scala 27:72]
wire [4:0] _T_330 = _GEN_8 | _T_300; // @[Mux.scala 27:72]
wire [4:0] _T_331 = _T_330 | _T_301; // @[Mux.scala 27:72]
wire [4:0] _T_332 = _T_331 | _T_302; // @[Mux.scala 27:72]
wire [4:0] _T_333 = _T_332 | _T_303; // @[Mux.scala 27:72]
wire [4:0] _T_334 = _T_333 | _T_304; // @[Mux.scala 27:72]
wire [4:0] _T_335 = _T_334 | _T_305; // @[Mux.scala 27:72]
wire [4:0] _T_336 = _T_335 | _T_306; // @[Mux.scala 27:72]
wire [4:0] _T_337 = _T_336 | _T_307; // @[Mux.scala 27:72]
wire [4:0] _T_338 = _T_337 | _T_308; // @[Mux.scala 27:72]
wire [4:0] _T_339 = _T_338 | _T_309; // @[Mux.scala 27:72]
wire [4:0] _T_340 = _T_339 | _T_310; // @[Mux.scala 27:72]
wire [4:0] _T_341 = _T_340 | _T_311; // @[Mux.scala 27:72]
wire [4:0] _T_342 = _T_341 | _T_312; // @[Mux.scala 27:72]
wire [4:0] _T_343 = _T_342 | _T_313; // @[Mux.scala 27:72]
wire [4:0] _T_344 = _T_343 | _T_314; // @[Mux.scala 27:72]
wire [4:0] cls_ones = _T_129 ? 5'h1f : _T_344; // @[exu_div_ctl.scala 512:44]
assign io_cls = io_operand[32] ? cls_ones : cls_zeros; // @[exu_div_ctl.scala 514:10]
endmodule
module rvclkhdr(
input io_clk,
input io_en
);
wire clkhdr_Q; // @[lib.scala 334:26]
wire clkhdr_CK; // @[lib.scala 334:26]
wire clkhdr_EN; // @[lib.scala 334:26]
wire clkhdr_SE; // @[lib.scala 334:26]
gated_latch clkhdr ( // @[lib.scala 334:26]
.Q(clkhdr_Q),
.CK(clkhdr_CK),
.EN(clkhdr_EN),
.SE(clkhdr_SE)
);
assign clkhdr_CK = io_clk; // @[lib.scala 336:18]
assign clkhdr_EN = io_en; // @[lib.scala 337:18]
assign clkhdr_SE = 1'h0; // @[lib.scala 338:18]
endmodule
module exu_div_new_1bit_fullshortq(
input clock,
input reset,
input io_scan_mode,
input io_cancel,
input io_valid_in,
input io_signed_in,
input io_rem_in,
input [31:0] io_dividend_in,
input [31:0] io_divisor_in,
output [31:0] io_data_out,
output io_valid_out
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [63:0] _RAND_1;
reg [31:0] _RAND_2;
reg [31:0] _RAND_3;
reg [31:0] _RAND_4;
reg [31:0] _RAND_5;
reg [31:0] _RAND_6;
reg [31:0] _RAND_7;
reg [31:0] _RAND_8;
reg [31:0] _RAND_9;
reg [31:0] _RAND_10;
`endif // RANDOMIZE_REG_INIT
wire [32:0] a_enc_io_operand; // @[exu_div_ctl.scala 429:21]
wire [4:0] a_enc_io_cls; // @[exu_div_ctl.scala 429:21]
wire [32:0] b_enc_io_operand; // @[exu_div_ctl.scala 432:21]
wire [4:0] b_enc_io_cls; // @[exu_div_ctl.scala 432:21]
wire rvclkhdr_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_io_en; // @[lib.scala 390:23]
wire rvclkhdr_1_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_1_io_en; // @[lib.scala 390:23]
wire rvclkhdr_2_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_2_io_en; // @[lib.scala 390:23]
wire rvclkhdr_3_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_3_io_en; // @[lib.scala 390:23]
wire rvclkhdr_4_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_4_io_en; // @[lib.scala 390:23]
wire rvclkhdr_5_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_5_io_en; // @[lib.scala 390:23]
wire rvclkhdr_6_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_6_io_en; // @[lib.scala 390:23]
wire rvclkhdr_7_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_7_io_en; // @[lib.scala 390:23]
wire rvclkhdr_8_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_8_io_en; // @[lib.scala 390:23]
wire rvclkhdr_9_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_9_io_en; // @[lib.scala 390:23]
wire rvclkhdr_10_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_10_io_en; // @[lib.scala 390:23]
reg [2:0] control_ff; // @[Reg.scala 27:20]
wire dividend_sign_ff = control_ff[2]; // @[exu_div_ctl.scala 343:40]
wire divisor_sign_ff = control_ff[1]; // @[exu_div_ctl.scala 344:40]
wire rem_ff = control_ff[0]; // @[exu_div_ctl.scala 345:40]
reg [32:0] b_ff; // @[Reg.scala 27:20]
wire _T_1 = b_ff[31:0] == 32'h0; // @[exu_div_ctl.scala 346:54]
reg valid_ff; // @[Reg.scala 27:20]
wire by_zero_case = valid_ff & _T_1; // @[exu_div_ctl.scala 346:40]
reg [31:0] a_ff; // @[Reg.scala 27:20]
wire _T_3 = a_ff[31:4] == 28'h0; // @[exu_div_ctl.scala 347:37]
wire _T_5 = b_ff[31:4] == 28'h0; // @[exu_div_ctl.scala 347:60]
wire _T_6 = _T_3 & _T_5; // @[exu_div_ctl.scala 347:46]
wire _T_7 = ~by_zero_case; // @[exu_div_ctl.scala 347:71]
wire _T_8 = _T_6 & _T_7; // @[exu_div_ctl.scala 347:69]
wire _T_9 = ~rem_ff; // @[exu_div_ctl.scala 347:87]
wire _T_10 = _T_8 & _T_9; // @[exu_div_ctl.scala 347:85]
wire _T_11 = _T_10 & valid_ff; // @[exu_div_ctl.scala 347:95]
wire _T_12 = ~io_cancel; // @[exu_div_ctl.scala 347:108]
wire _T_13 = _T_11 & _T_12; // @[exu_div_ctl.scala 347:106]
wire _T_15 = a_ff == 32'h0; // @[exu_div_ctl.scala 348:18]
wire _T_17 = _T_15 & _T_7; // @[exu_div_ctl.scala 348:27]
wire _T_19 = _T_17 & _T_9; // @[exu_div_ctl.scala 348:43]
wire _T_20 = _T_19 & valid_ff; // @[exu_div_ctl.scala 348:53]
wire _T_22 = _T_20 & _T_12; // @[exu_div_ctl.scala 348:64]
wire smallnum_case = _T_13 | _T_22; // @[exu_div_ctl.scala 347:120]
wire valid_ff_in = io_valid_in & _T_12; // @[exu_div_ctl.scala 349:43]
wire _T_24 = ~io_valid_in; // @[exu_div_ctl.scala 350:35]
wire _T_26 = _T_24 & dividend_sign_ff; // @[exu_div_ctl.scala 350:48]
wire _T_27 = io_valid_in & io_signed_in; // @[exu_div_ctl.scala 350:80]
wire _T_29 = _T_27 & io_dividend_in[31]; // @[exu_div_ctl.scala 350:96]
wire _T_30 = _T_26 | _T_29; // @[exu_div_ctl.scala 350:65]
wire _T_33 = _T_24 & divisor_sign_ff; // @[exu_div_ctl.scala 350:133]
wire _T_36 = _T_27 & io_divisor_in[31]; // @[exu_div_ctl.scala 350:181]
wire _T_37 = _T_33 | _T_36; // @[exu_div_ctl.scala 350:150]
wire _T_40 = _T_24 & rem_ff; // @[exu_div_ctl.scala 350:218]
wire _T_41 = io_valid_in & io_rem_in; // @[exu_div_ctl.scala 350:250]
wire _T_42 = _T_40 | _T_41; // @[exu_div_ctl.scala 350:235]
wire [2:0] control_in = {_T_30,_T_37,_T_42}; // @[Cat.scala 29:58]
reg [6:0] count_ff; // @[Reg.scala 27:20]
wire _T_44 = |count_ff; // @[exu_div_ctl.scala 351:42]
reg shortq_enable_ff; // @[Reg.scala 27:20]
wire running_state = _T_44 | shortq_enable_ff; // @[exu_div_ctl.scala 351:45]
wire _T_45 = io_valid_in | valid_ff; // @[exu_div_ctl.scala 352:43]
wire _T_46 = _T_45 | io_cancel; // @[exu_div_ctl.scala 352:54]
wire _T_47 = _T_46 | running_state; // @[exu_div_ctl.scala 352:66]
reg finish_ff; // @[Reg.scala 27:20]
wire misc_enable = _T_47 | finish_ff; // @[exu_div_ctl.scala 352:82]
wire _T_48 = smallnum_case | by_zero_case; // @[exu_div_ctl.scala 353:45]
wire _T_49 = count_ff == 7'h20; // @[exu_div_ctl.scala 353:72]
wire finish_raw = _T_48 | _T_49; // @[exu_div_ctl.scala 353:60]
wire finish = finish_raw & _T_12; // @[exu_div_ctl.scala 354:41]
wire _T_51 = valid_ff | running_state; // @[exu_div_ctl.scala 355:40]
wire _T_52 = ~finish; // @[exu_div_ctl.scala 355:59]
wire _T_53 = _T_51 & _T_52; // @[exu_div_ctl.scala 355:57]
wire _T_54 = ~finish_ff; // @[exu_div_ctl.scala 355:69]
wire _T_55 = _T_53 & _T_54; // @[exu_div_ctl.scala 355:67]
wire _T_57 = _T_55 & _T_12; // @[exu_div_ctl.scala 355:80]
wire [6:0] _T_841 = {1'h0,1'h0,b_enc_io_cls}; // @[Cat.scala 29:58]
wire [6:0] _T_842 = {1'h0,1'h0,a_enc_io_cls}; // @[Cat.scala 29:58]
wire [6:0] _T_844 = _T_841 - _T_842; // @[exu_div_ctl.scala 437:41]
wire [6:0] dw_shortq_raw = _T_844 + 7'h1; // @[exu_div_ctl.scala 437:61]
wire [5:0] shortq = dw_shortq_raw[6] ? 6'h0 : dw_shortq_raw[5:0]; // @[exu_div_ctl.scala 438:19]
wire _T_850 = ~shortq[5]; // @[exu_div_ctl.scala 439:31]
wire _T_851 = valid_ff & _T_850; // @[exu_div_ctl.scala 439:29]
wire _T_853 = shortq[4:1] == 4'hf; // @[exu_div_ctl.scala 439:58]
wire _T_854 = ~_T_853; // @[exu_div_ctl.scala 439:44]
wire _T_855 = _T_851 & _T_854; // @[exu_div_ctl.scala 439:42]
wire shortq_enable = _T_855 & _T_12; // @[exu_div_ctl.scala 439:74]
wire _T_58 = ~shortq_enable; // @[exu_div_ctl.scala 355:95]
wire count_enable = _T_57 & _T_58; // @[exu_div_ctl.scala 355:93]
wire [6:0] _T_60 = count_enable ? 7'h7f : 7'h0; // @[Bitwise.scala 72:12]
wire [6:0] _T_63 = count_ff + 7'h1; // @[exu_div_ctl.scala 356:63]
reg [4:0] shortq_shift_ff; // @[Reg.scala 27:20]
wire [6:0] _T_64 = {2'h0,shortq_shift_ff}; // @[Cat.scala 29:58]
wire [6:0] _T_66 = _T_63 + _T_64; // @[exu_div_ctl.scala 356:83]
wire [6:0] count_in = _T_60 & _T_66; // @[exu_div_ctl.scala 356:51]
wire a_enable = io_valid_in | running_state; // @[exu_div_ctl.scala 357:43]
wire _T_67 = ~shortq_enable_ff; // @[exu_div_ctl.scala 358:47]
wire a_shift = running_state & _T_67; // @[exu_div_ctl.scala 358:45]
wire [31:0] _T_69 = dividend_sign_ff ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
wire [63:0] _T_70 = {_T_69,a_ff}; // @[Cat.scala 29:58]
wire [94:0] _GEN_11 = {{31'd0}, _T_70}; // @[exu_div_ctl.scala 359:68]
wire [94:0] _T_71 = _GEN_11 << shortq_shift_ff; // @[exu_div_ctl.scala 359:68]
wire _T_72 = dividend_sign_ff ^ divisor_sign_ff; // @[exu_div_ctl.scala 360:61]
wire _T_73 = ~_T_72; // @[exu_div_ctl.scala 360:42]
wire b_twos_comp = valid_ff & _T_73; // @[exu_div_ctl.scala 360:40]
wire _T_76 = ~valid_ff; // @[exu_div_ctl.scala 362:30]
wire _T_78 = _T_76 & _T_9; // @[exu_div_ctl.scala 362:40]
wire _T_80 = _T_78 & _T_72; // @[exu_div_ctl.scala 362:50]
reg by_zero_case_ff; // @[Reg.scala 27:20]
wire _T_81 = ~by_zero_case_ff; // @[exu_div_ctl.scala 362:92]
wire twos_comp_q_sel = _T_80 & _T_81; // @[exu_div_ctl.scala 362:90]
wire b_enable = io_valid_in | b_twos_comp; // @[exu_div_ctl.scala 363:43]
wire rq_enable = _T_45 | running_state; // @[exu_div_ctl.scala 364:54]
wire _T_83 = valid_ff & dividend_sign_ff; // @[exu_div_ctl.scala 365:40]
wire r_sign_sel = _T_83 & _T_7; // @[exu_div_ctl.scala 365:59]
reg [31:0] r_ff; // @[Reg.scala 27:20]
wire [32:0] _T_360 = {r_ff,a_ff[31]}; // @[Cat.scala 29:58]
wire [32:0] adder_out = _T_360 + b_ff; // @[exu_div_ctl.scala 395:35]
wire _T_364 = ~adder_out[32]; // @[exu_div_ctl.scala 396:20]
wire _T_365 = _T_364 ^ dividend_sign_ff; // @[exu_div_ctl.scala 396:35]
wire _T_367 = a_ff[30:0] == 31'h0; // @[exu_div_ctl.scala 396:70]
wire _T_368 = adder_out == 33'h0; // @[exu_div_ctl.scala 396:92]
wire _T_369 = _T_367 & _T_368; // @[exu_div_ctl.scala 396:79]
wire quotient_set = _T_365 | _T_369; // @[exu_div_ctl.scala 396:55]
wire _T_85 = ~quotient_set; // @[exu_div_ctl.scala 366:47]
wire _T_86 = running_state & _T_85; // @[exu_div_ctl.scala 366:45]
wire r_restore_sel = _T_86 & _T_67; // @[exu_div_ctl.scala 366:61]
wire _T_88 = running_state & quotient_set; // @[exu_div_ctl.scala 367:45]
wire r_adder_sel = _T_88 & _T_67; // @[exu_div_ctl.scala 367:61]
reg [31:0] q_ff; // @[Reg.scala 27:20]
wire [31:0] _T_91 = twos_comp_q_sel ? q_ff : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_92 = b_twos_comp ? b_ff[31:0] : 32'h0; // @[Mux.scala 27:72]
wire [31:0] twos_comp_in = _T_91 | _T_92; // @[Mux.scala 27:72]
wire _T_96 = |twos_comp_in[0]; // @[lib.scala 428:35]
wire _T_98 = ~twos_comp_in[1]; // @[lib.scala 428:40]
wire _T_100 = _T_96 ? _T_98 : twos_comp_in[1]; // @[lib.scala 428:23]
wire _T_102 = |twos_comp_in[1:0]; // @[lib.scala 428:35]
wire _T_104 = ~twos_comp_in[2]; // @[lib.scala 428:40]
wire _T_106 = _T_102 ? _T_104 : twos_comp_in[2]; // @[lib.scala 428:23]
wire _T_108 = |twos_comp_in[2:0]; // @[lib.scala 428:35]
wire _T_110 = ~twos_comp_in[3]; // @[lib.scala 428:40]
wire _T_112 = _T_108 ? _T_110 : twos_comp_in[3]; // @[lib.scala 428:23]
wire _T_114 = |twos_comp_in[3:0]; // @[lib.scala 428:35]
wire _T_116 = ~twos_comp_in[4]; // @[lib.scala 428:40]
wire _T_118 = _T_114 ? _T_116 : twos_comp_in[4]; // @[lib.scala 428:23]
wire _T_120 = |twos_comp_in[4:0]; // @[lib.scala 428:35]
wire _T_122 = ~twos_comp_in[5]; // @[lib.scala 428:40]
wire _T_124 = _T_120 ? _T_122 : twos_comp_in[5]; // @[lib.scala 428:23]
wire _T_126 = |twos_comp_in[5:0]; // @[lib.scala 428:35]
wire _T_128 = ~twos_comp_in[6]; // @[lib.scala 428:40]
wire _T_130 = _T_126 ? _T_128 : twos_comp_in[6]; // @[lib.scala 428:23]
wire _T_132 = |twos_comp_in[6:0]; // @[lib.scala 428:35]
wire _T_134 = ~twos_comp_in[7]; // @[lib.scala 428:40]
wire _T_136 = _T_132 ? _T_134 : twos_comp_in[7]; // @[lib.scala 428:23]
wire _T_138 = |twos_comp_in[7:0]; // @[lib.scala 428:35]
wire _T_140 = ~twos_comp_in[8]; // @[lib.scala 428:40]
wire _T_142 = _T_138 ? _T_140 : twos_comp_in[8]; // @[lib.scala 428:23]
wire _T_144 = |twos_comp_in[8:0]; // @[lib.scala 428:35]
wire _T_146 = ~twos_comp_in[9]; // @[lib.scala 428:40]
wire _T_148 = _T_144 ? _T_146 : twos_comp_in[9]; // @[lib.scala 428:23]
wire _T_150 = |twos_comp_in[9:0]; // @[lib.scala 428:35]
wire _T_152 = ~twos_comp_in[10]; // @[lib.scala 428:40]
wire _T_154 = _T_150 ? _T_152 : twos_comp_in[10]; // @[lib.scala 428:23]
wire _T_156 = |twos_comp_in[10:0]; // @[lib.scala 428:35]
wire _T_158 = ~twos_comp_in[11]; // @[lib.scala 428:40]
wire _T_160 = _T_156 ? _T_158 : twos_comp_in[11]; // @[lib.scala 428:23]
wire _T_162 = |twos_comp_in[11:0]; // @[lib.scala 428:35]
wire _T_164 = ~twos_comp_in[12]; // @[lib.scala 428:40]
wire _T_166 = _T_162 ? _T_164 : twos_comp_in[12]; // @[lib.scala 428:23]
wire _T_168 = |twos_comp_in[12:0]; // @[lib.scala 428:35]
wire _T_170 = ~twos_comp_in[13]; // @[lib.scala 428:40]
wire _T_172 = _T_168 ? _T_170 : twos_comp_in[13]; // @[lib.scala 428:23]
wire _T_174 = |twos_comp_in[13:0]; // @[lib.scala 428:35]
wire _T_176 = ~twos_comp_in[14]; // @[lib.scala 428:40]
wire _T_178 = _T_174 ? _T_176 : twos_comp_in[14]; // @[lib.scala 428:23]
wire _T_180 = |twos_comp_in[14:0]; // @[lib.scala 428:35]
wire _T_182 = ~twos_comp_in[15]; // @[lib.scala 428:40]
wire _T_184 = _T_180 ? _T_182 : twos_comp_in[15]; // @[lib.scala 428:23]
wire _T_186 = |twos_comp_in[15:0]; // @[lib.scala 428:35]
wire _T_188 = ~twos_comp_in[16]; // @[lib.scala 428:40]
wire _T_190 = _T_186 ? _T_188 : twos_comp_in[16]; // @[lib.scala 428:23]
wire _T_192 = |twos_comp_in[16:0]; // @[lib.scala 428:35]
wire _T_194 = ~twos_comp_in[17]; // @[lib.scala 428:40]
wire _T_196 = _T_192 ? _T_194 : twos_comp_in[17]; // @[lib.scala 428:23]
wire _T_198 = |twos_comp_in[17:0]; // @[lib.scala 428:35]
wire _T_200 = ~twos_comp_in[18]; // @[lib.scala 428:40]
wire _T_202 = _T_198 ? _T_200 : twos_comp_in[18]; // @[lib.scala 428:23]
wire _T_204 = |twos_comp_in[18:0]; // @[lib.scala 428:35]
wire _T_206 = ~twos_comp_in[19]; // @[lib.scala 428:40]
wire _T_208 = _T_204 ? _T_206 : twos_comp_in[19]; // @[lib.scala 428:23]
wire _T_210 = |twos_comp_in[19:0]; // @[lib.scala 428:35]
wire _T_212 = ~twos_comp_in[20]; // @[lib.scala 428:40]
wire _T_214 = _T_210 ? _T_212 : twos_comp_in[20]; // @[lib.scala 428:23]
wire _T_216 = |twos_comp_in[20:0]; // @[lib.scala 428:35]
wire _T_218 = ~twos_comp_in[21]; // @[lib.scala 428:40]
wire _T_220 = _T_216 ? _T_218 : twos_comp_in[21]; // @[lib.scala 428:23]
wire _T_222 = |twos_comp_in[21:0]; // @[lib.scala 428:35]
wire _T_224 = ~twos_comp_in[22]; // @[lib.scala 428:40]
wire _T_226 = _T_222 ? _T_224 : twos_comp_in[22]; // @[lib.scala 428:23]
wire _T_228 = |twos_comp_in[22:0]; // @[lib.scala 428:35]
wire _T_230 = ~twos_comp_in[23]; // @[lib.scala 428:40]
wire _T_232 = _T_228 ? _T_230 : twos_comp_in[23]; // @[lib.scala 428:23]
wire _T_234 = |twos_comp_in[23:0]; // @[lib.scala 428:35]
wire _T_236 = ~twos_comp_in[24]; // @[lib.scala 428:40]
wire _T_238 = _T_234 ? _T_236 : twos_comp_in[24]; // @[lib.scala 428:23]
wire _T_240 = |twos_comp_in[24:0]; // @[lib.scala 428:35]
wire _T_242 = ~twos_comp_in[25]; // @[lib.scala 428:40]
wire _T_244 = _T_240 ? _T_242 : twos_comp_in[25]; // @[lib.scala 428:23]
wire _T_246 = |twos_comp_in[25:0]; // @[lib.scala 428:35]
wire _T_248 = ~twos_comp_in[26]; // @[lib.scala 428:40]
wire _T_250 = _T_246 ? _T_248 : twos_comp_in[26]; // @[lib.scala 428:23]
wire _T_252 = |twos_comp_in[26:0]; // @[lib.scala 428:35]
wire _T_254 = ~twos_comp_in[27]; // @[lib.scala 428:40]
wire _T_256 = _T_252 ? _T_254 : twos_comp_in[27]; // @[lib.scala 428:23]
wire _T_258 = |twos_comp_in[27:0]; // @[lib.scala 428:35]
wire _T_260 = ~twos_comp_in[28]; // @[lib.scala 428:40]
wire _T_262 = _T_258 ? _T_260 : twos_comp_in[28]; // @[lib.scala 428:23]
wire _T_264 = |twos_comp_in[28:0]; // @[lib.scala 428:35]
wire _T_266 = ~twos_comp_in[29]; // @[lib.scala 428:40]
wire _T_268 = _T_264 ? _T_266 : twos_comp_in[29]; // @[lib.scala 428:23]
wire _T_270 = |twos_comp_in[29:0]; // @[lib.scala 428:35]
wire _T_272 = ~twos_comp_in[30]; // @[lib.scala 428:40]
wire _T_274 = _T_270 ? _T_272 : twos_comp_in[30]; // @[lib.scala 428:23]
wire _T_276 = |twos_comp_in[30:0]; // @[lib.scala 428:35]
wire _T_278 = ~twos_comp_in[31]; // @[lib.scala 428:40]
wire _T_280 = _T_276 ? _T_278 : twos_comp_in[31]; // @[lib.scala 428:23]
wire [6:0] _T_286 = {_T_136,_T_130,_T_124,_T_118,_T_112,_T_106,_T_100}; // @[lib.scala 430:14]
wire [14:0] _T_294 = {_T_184,_T_178,_T_172,_T_166,_T_160,_T_154,_T_148,_T_142,_T_286}; // @[lib.scala 430:14]
wire [7:0] _T_301 = {_T_232,_T_226,_T_220,_T_214,_T_208,_T_202,_T_196,_T_190}; // @[lib.scala 430:14]
wire [30:0] _T_310 = {_T_280,_T_274,_T_268,_T_262,_T_256,_T_250,_T_244,_T_238,_T_301,_T_294}; // @[lib.scala 430:14]
wire [31:0] twos_comp_out = {_T_310,twos_comp_in[0]}; // @[Cat.scala 29:58]
wire _T_312 = ~a_shift; // @[exu_div_ctl.scala 375:6]
wire _T_314 = _T_312 & _T_67; // @[exu_div_ctl.scala 375:15]
wire [31:0] _T_317 = {a_ff[30:0],1'h0}; // @[Cat.scala 29:58]
wire [63:0] ar_shifted = _T_71[63:0]; // @[exu_div_ctl.scala 359:28]
wire [31:0] _T_319 = _T_314 ? io_dividend_in : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_320 = a_shift ? _T_317 : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_321 = shortq_enable_ff ? ar_shifted[31:0] : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_322 = _T_319 | _T_320; // @[Mux.scala 27:72]
wire [31:0] a_in = _T_322 | _T_321; // @[Mux.scala 27:72]
wire _T_324 = ~b_twos_comp; // @[exu_div_ctl.scala 380:5]
wire _T_326 = io_signed_in & io_divisor_in[31]; // @[exu_div_ctl.scala 380:63]
wire [32:0] _T_328 = {_T_326,io_divisor_in}; // @[Cat.scala 29:58]
wire _T_329 = ~divisor_sign_ff; // @[exu_div_ctl.scala 381:50]
wire [32:0] _T_331 = {_T_329,_T_310,twos_comp_in[0]}; // @[Cat.scala 29:58]
wire [32:0] _T_332 = _T_324 ? _T_328 : 33'h0; // @[Mux.scala 27:72]
wire [32:0] _T_333 = b_twos_comp ? _T_331 : 33'h0; // @[Mux.scala 27:72]
wire [32:0] b_in = _T_332 | _T_333; // @[Mux.scala 27:72]
wire [31:0] _T_337 = {r_ff[30:0],a_ff[31]}; // @[Cat.scala 29:58]
wire [31:0] _T_340 = r_sign_sel ? 32'hffffffff : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_341 = r_restore_sel ? _T_337 : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_342 = r_adder_sel ? adder_out[31:0] : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_343 = shortq_enable_ff ? ar_shifted[63:32] : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_344 = by_zero_case ? a_ff : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_345 = _T_340 | _T_341; // @[Mux.scala 27:72]
wire [31:0] _T_346 = _T_345 | _T_342; // @[Mux.scala 27:72]
wire [31:0] _T_347 = _T_346 | _T_343; // @[Mux.scala 27:72]
wire [31:0] r_in = _T_347 | _T_344; // @[Mux.scala 27:72]
wire [31:0] _T_351 = {q_ff[30:0],quotient_set}; // @[Cat.scala 29:58]
wire _T_385 = ~b_ff[3]; // @[exu_div_ctl.scala 405:70]
wire _T_387 = ~b_ff[2]; // @[exu_div_ctl.scala 405:70]
wire _T_390 = _T_385 & _T_387; // @[exu_div_ctl.scala 405:95]
wire _T_389 = ~b_ff[1]; // @[exu_div_ctl.scala 405:70]
wire _T_391 = _T_390 & _T_389; // @[exu_div_ctl.scala 405:95]
wire _T_392 = a_ff[3] & _T_391; // @[exu_div_ctl.scala 406:11]
wire _T_399 = a_ff[3] & _T_390; // @[exu_div_ctl.scala 406:11]
wire _T_401 = ~b_ff[0]; // @[exu_div_ctl.scala 412:33]
wire _T_402 = _T_399 & _T_401; // @[exu_div_ctl.scala 412:31]
wire _T_412 = a_ff[2] & _T_391; // @[exu_div_ctl.scala 406:11]
wire _T_413 = _T_402 | _T_412; // @[exu_div_ctl.scala 412:42]
wire _T_416 = a_ff[3] & a_ff[2]; // @[exu_div_ctl.scala 404:95]
wire _T_422 = _T_416 & _T_390; // @[exu_div_ctl.scala 406:11]
wire _T_423 = _T_413 | _T_422; // @[exu_div_ctl.scala 412:75]
wire _T_430 = a_ff[2] & _T_390; // @[exu_div_ctl.scala 406:11]
wire _T_433 = _T_430 & _T_401; // @[exu_div_ctl.scala 414:31]
wire _T_443 = a_ff[1] & _T_391; // @[exu_div_ctl.scala 406:11]
wire _T_444 = _T_433 | _T_443; // @[exu_div_ctl.scala 414:42]
wire _T_450 = _T_385 & _T_389; // @[exu_div_ctl.scala 405:95]
wire _T_451 = a_ff[3] & _T_450; // @[exu_div_ctl.scala 406:11]
wire _T_454 = _T_451 & _T_401; // @[exu_div_ctl.scala 414:106]
wire _T_455 = _T_444 | _T_454; // @[exu_div_ctl.scala 414:78]
wire _T_458 = ~a_ff[2]; // @[exu_div_ctl.scala 404:70]
wire _T_459 = a_ff[3] & _T_458; // @[exu_div_ctl.scala 404:95]
wire _T_467 = _T_390 & b_ff[1]; // @[exu_div_ctl.scala 405:95]
wire _T_468 = _T_467 & b_ff[0]; // @[exu_div_ctl.scala 405:95]
wire _T_469 = _T_459 & _T_468; // @[exu_div_ctl.scala 406:11]
wire _T_470 = _T_455 | _T_469; // @[exu_div_ctl.scala 414:117]
wire _T_472 = ~a_ff[3]; // @[exu_div_ctl.scala 404:70]
wire _T_475 = _T_472 & a_ff[2]; // @[exu_div_ctl.scala 404:95]
wire _T_476 = _T_475 & a_ff[1]; // @[exu_div_ctl.scala 404:95]
wire _T_482 = _T_476 & _T_390; // @[exu_div_ctl.scala 406:11]
wire _T_483 = _T_470 | _T_482; // @[exu_div_ctl.scala 415:44]
wire _T_489 = _T_416 & _T_385; // @[exu_div_ctl.scala 406:11]
wire _T_492 = _T_489 & _T_401; // @[exu_div_ctl.scala 415:107]
wire _T_493 = _T_483 | _T_492; // @[exu_div_ctl.scala 415:80]
wire _T_502 = _T_385 & b_ff[2]; // @[exu_div_ctl.scala 405:95]
wire _T_503 = _T_502 & _T_389; // @[exu_div_ctl.scala 405:95]
wire _T_504 = _T_416 & _T_503; // @[exu_div_ctl.scala 406:11]
wire _T_505 = _T_493 | _T_504; // @[exu_div_ctl.scala 415:119]
wire _T_508 = a_ff[3] & a_ff[1]; // @[exu_div_ctl.scala 404:95]
wire _T_514 = _T_508 & _T_450; // @[exu_div_ctl.scala 406:11]
wire _T_515 = _T_505 | _T_514; // @[exu_div_ctl.scala 416:44]
wire _T_520 = _T_416 & a_ff[1]; // @[exu_div_ctl.scala 404:95]
wire _T_525 = _T_520 & _T_502; // @[exu_div_ctl.scala 406:11]
wire _T_526 = _T_515 | _T_525; // @[exu_div_ctl.scala 416:79]
wire _T_530 = a_ff[2] & a_ff[1]; // @[exu_div_ctl.scala 404:95]
wire _T_531 = _T_530 & a_ff[0]; // @[exu_div_ctl.scala 404:95]
wire _T_537 = _T_531 & _T_450; // @[exu_div_ctl.scala 406:11]
wire _T_543 = _T_459 & a_ff[0]; // @[exu_div_ctl.scala 404:95]
wire _T_548 = _T_385 & b_ff[1]; // @[exu_div_ctl.scala 405:95]
wire _T_549 = _T_548 & b_ff[0]; // @[exu_div_ctl.scala 405:95]
wire _T_550 = _T_543 & _T_549; // @[exu_div_ctl.scala 406:11]
wire _T_551 = _T_537 | _T_550; // @[exu_div_ctl.scala 418:45]
wire _T_558 = a_ff[2] & _T_450; // @[exu_div_ctl.scala 406:11]
wire _T_561 = _T_558 & _T_401; // @[exu_div_ctl.scala 418:114]
wire _T_562 = _T_551 | _T_561; // @[exu_div_ctl.scala 418:86]
wire _T_569 = a_ff[1] & _T_390; // @[exu_div_ctl.scala 406:11]
wire _T_572 = _T_569 & _T_401; // @[exu_div_ctl.scala 419:33]
wire _T_573 = _T_562 | _T_572; // @[exu_div_ctl.scala 418:129]
wire _T_583 = a_ff[0] & _T_391; // @[exu_div_ctl.scala 406:11]
wire _T_584 = _T_573 | _T_583; // @[exu_div_ctl.scala 419:47]
wire _T_589 = ~a_ff[1]; // @[exu_div_ctl.scala 404:70]
wire _T_591 = _T_475 & _T_589; // @[exu_div_ctl.scala 404:95]
wire _T_601 = _T_591 & _T_468; // @[exu_div_ctl.scala 406:11]
wire _T_602 = _T_584 | _T_601; // @[exu_div_ctl.scala 419:88]
wire _T_611 = _T_476 & _T_385; // @[exu_div_ctl.scala 406:11]
wire _T_614 = _T_611 & _T_401; // @[exu_div_ctl.scala 420:36]
wire _T_615 = _T_602 | _T_614; // @[exu_div_ctl.scala 419:131]
wire _T_621 = _T_387 & _T_389; // @[exu_div_ctl.scala 405:95]
wire _T_622 = a_ff[3] & _T_621; // @[exu_div_ctl.scala 406:11]
wire _T_625 = _T_622 & _T_401; // @[exu_div_ctl.scala 420:76]
wire _T_626 = _T_615 | _T_625; // @[exu_div_ctl.scala 420:47]
wire _T_636 = _T_502 & b_ff[1]; // @[exu_div_ctl.scala 405:95]
wire _T_637 = _T_459 & _T_636; // @[exu_div_ctl.scala 406:11]
wire _T_638 = _T_626 | _T_637; // @[exu_div_ctl.scala 420:88]
wire _T_652 = _T_476 & _T_503; // @[exu_div_ctl.scala 406:11]
wire _T_653 = _T_638 | _T_652; // @[exu_div_ctl.scala 420:131]
wire _T_659 = _T_475 & a_ff[0]; // @[exu_div_ctl.scala 404:95]
wire _T_665 = _T_659 & _T_450; // @[exu_div_ctl.scala 406:11]
wire _T_666 = _T_653 | _T_665; // @[exu_div_ctl.scala 421:47]
wire _T_673 = _T_459 & _T_589; // @[exu_div_ctl.scala 404:95]
wire _T_679 = _T_502 & b_ff[0]; // @[exu_div_ctl.scala 405:95]
wire _T_680 = _T_673 & _T_679; // @[exu_div_ctl.scala 406:11]
wire _T_681 = _T_666 | _T_680; // @[exu_div_ctl.scala 421:88]
wire _T_686 = _T_458 & a_ff[1]; // @[exu_div_ctl.scala 404:95]
wire _T_687 = _T_686 & a_ff[0]; // @[exu_div_ctl.scala 404:95]
wire _T_693 = _T_687 & _T_390; // @[exu_div_ctl.scala 406:11]
wire _T_694 = _T_681 | _T_693; // @[exu_div_ctl.scala 421:131]
wire _T_700 = _T_416 & _T_389; // @[exu_div_ctl.scala 406:11]
wire _T_703 = _T_700 & _T_401; // @[exu_div_ctl.scala 422:75]
wire _T_704 = _T_694 | _T_703; // @[exu_div_ctl.scala 422:47]
wire _T_712 = _T_476 & a_ff[0]; // @[exu_div_ctl.scala 404:95]
wire _T_717 = _T_712 & _T_502; // @[exu_div_ctl.scala 406:11]
wire _T_718 = _T_704 | _T_717; // @[exu_div_ctl.scala 422:88]
wire _T_725 = b_ff[3] & _T_387; // @[exu_div_ctl.scala 405:95]
wire _T_726 = _T_416 & _T_725; // @[exu_div_ctl.scala 406:11]
wire _T_727 = _T_718 | _T_726; // @[exu_div_ctl.scala 422:131]
wire _T_737 = _T_725 & _T_389; // @[exu_div_ctl.scala 405:95]
wire _T_738 = _T_508 & _T_737; // @[exu_div_ctl.scala 406:11]
wire _T_739 = _T_727 | _T_738; // @[exu_div_ctl.scala 423:47]
wire _T_742 = a_ff[3] & a_ff[0]; // @[exu_div_ctl.scala 404:95]
wire _T_748 = _T_742 & _T_621; // @[exu_div_ctl.scala 406:11]
wire _T_749 = _T_739 | _T_748; // @[exu_div_ctl.scala 423:88]
wire _T_753 = a_ff[3] & _T_589; // @[exu_div_ctl.scala 404:95]
wire _T_761 = _T_636 & b_ff[0]; // @[exu_div_ctl.scala 405:95]
wire _T_762 = _T_753 & _T_761; // @[exu_div_ctl.scala 406:11]
wire _T_763 = _T_749 | _T_762; // @[exu_div_ctl.scala 423:131]
wire _T_770 = _T_520 & b_ff[3]; // @[exu_div_ctl.scala 406:11]
wire _T_773 = _T_770 & _T_401; // @[exu_div_ctl.scala 424:77]
wire _T_774 = _T_763 | _T_773; // @[exu_div_ctl.scala 424:47]
wire _T_783 = b_ff[3] & _T_389; // @[exu_div_ctl.scala 405:95]
wire _T_784 = _T_520 & _T_783; // @[exu_div_ctl.scala 406:11]
wire _T_785 = _T_774 | _T_784; // @[exu_div_ctl.scala 424:88]
wire _T_790 = _T_416 & a_ff[0]; // @[exu_div_ctl.scala 404:95]
wire _T_795 = _T_790 & _T_783; // @[exu_div_ctl.scala 406:11]
wire _T_796 = _T_785 | _T_795; // @[exu_div_ctl.scala 424:131]
wire _T_802 = _T_459 & a_ff[1]; // @[exu_div_ctl.scala 404:95]
wire _T_807 = _T_802 & _T_548; // @[exu_div_ctl.scala 406:11]
wire _T_808 = _T_796 | _T_807; // @[exu_div_ctl.scala 425:47]
wire _T_813 = _T_508 & a_ff[0]; // @[exu_div_ctl.scala 404:95]
wire _T_816 = _T_813 & _T_387; // @[exu_div_ctl.scala 406:11]
wire _T_817 = _T_808 | _T_816; // @[exu_div_ctl.scala 425:88]
wire _T_824 = _T_520 & a_ff[0]; // @[exu_div_ctl.scala 404:95]
wire _T_826 = _T_824 & b_ff[3]; // @[exu_div_ctl.scala 406:11]
wire _T_827 = _T_817 | _T_826; // @[exu_div_ctl.scala 425:131]
wire _T_833 = _T_508 & _T_387; // @[exu_div_ctl.scala 406:11]
wire _T_836 = _T_833 & _T_401; // @[exu_div_ctl.scala 426:74]
wire _T_837 = _T_827 | _T_836; // @[exu_div_ctl.scala 426:47]
wire [31:0] _T_352 = {28'h0,_T_392,_T_423,_T_526,_T_837}; // @[Cat.scala 29:58]
wire [31:0] _T_354 = _T_76 ? _T_351 : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_355 = smallnum_case ? _T_352 : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_356 = by_zero_case ? 32'hffffffff : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_357 = _T_354 | _T_355; // @[Mux.scala 27:72]
wire [31:0] q_in = _T_357 | _T_356; // @[Mux.scala 27:72]
wire _T_374 = ~twos_comp_q_sel; // @[exu_div_ctl.scala 399:16]
wire _T_375 = _T_9 & _T_374; // @[exu_div_ctl.scala 399:14]
wire [31:0] _T_377 = _T_375 ? q_ff : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_378 = rem_ff ? r_ff : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_379 = twos_comp_q_sel ? twos_comp_out : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_380 = _T_377 | _T_378; // @[Mux.scala 27:72]
wire [4:0] _T_861 = 5'h1f - shortq[4:0]; // @[exu_div_ctl.scala 440:57]
exu_div_cls a_enc ( // @[exu_div_ctl.scala 429:21]
.io_operand(a_enc_io_operand),
.io_cls(a_enc_io_cls)
);
exu_div_cls b_enc ( // @[exu_div_ctl.scala 432:21]
.io_operand(b_enc_io_operand),
.io_cls(b_enc_io_cls)
);
rvclkhdr rvclkhdr ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_io_clk),
.io_en(rvclkhdr_io_en)
);
rvclkhdr rvclkhdr_1 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_1_io_clk),
.io_en(rvclkhdr_1_io_en)
);
rvclkhdr rvclkhdr_2 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_2_io_clk),
.io_en(rvclkhdr_2_io_en)
);
rvclkhdr rvclkhdr_3 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_3_io_clk),
.io_en(rvclkhdr_3_io_en)
);
rvclkhdr rvclkhdr_4 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_4_io_clk),
.io_en(rvclkhdr_4_io_en)
);
rvclkhdr rvclkhdr_5 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_5_io_clk),
.io_en(rvclkhdr_5_io_en)
);
rvclkhdr rvclkhdr_6 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_6_io_clk),
.io_en(rvclkhdr_6_io_en)
);
rvclkhdr rvclkhdr_7 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_7_io_clk),
.io_en(rvclkhdr_7_io_en)
);
rvclkhdr rvclkhdr_8 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_8_io_clk),
.io_en(rvclkhdr_8_io_en)
);
rvclkhdr rvclkhdr_9 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_9_io_clk),
.io_en(rvclkhdr_9_io_en)
);
rvclkhdr rvclkhdr_10 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_10_io_clk),
.io_en(rvclkhdr_10_io_en)
);
assign io_data_out = _T_380 | _T_379; // @[exu_div_ctl.scala 398:15]
assign io_valid_out = finish_ff & _T_12; // @[exu_div_ctl.scala 397:16]
assign a_enc_io_operand = {dividend_sign_ff,a_ff}; // @[exu_div_ctl.scala 430:20]
assign b_enc_io_operand = b_ff; // @[exu_div_ctl.scala 433:20]
assign rvclkhdr_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_io_en = _T_47 | finish_ff; // @[lib.scala 393:17]
assign rvclkhdr_1_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_1_io_en = _T_47 | finish_ff; // @[lib.scala 393:17]
assign rvclkhdr_2_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_2_io_en = _T_47 | finish_ff; // @[lib.scala 393:17]
assign rvclkhdr_3_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_3_io_en = _T_47 | finish_ff; // @[lib.scala 393:17]
assign rvclkhdr_4_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_4_io_en = _T_47 | finish_ff; // @[lib.scala 393:17]
assign rvclkhdr_5_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_5_io_en = _T_47 | finish_ff; // @[lib.scala 393:17]
assign rvclkhdr_6_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_6_io_en = _T_47 | finish_ff; // @[lib.scala 393:17]
assign rvclkhdr_7_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_7_io_en = io_valid_in | running_state; // @[lib.scala 393:17]
assign rvclkhdr_8_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_8_io_en = io_valid_in | b_twos_comp; // @[lib.scala 393:17]
assign rvclkhdr_9_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_9_io_en = _T_45 | running_state; // @[lib.scala 393:17]
assign rvclkhdr_10_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_10_io_en = _T_45 | running_state; // @[lib.scala 393:17]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
control_ff = _RAND_0[2:0];
_RAND_1 = {2{`RANDOM}};
b_ff = _RAND_1[32:0];
_RAND_2 = {1{`RANDOM}};
valid_ff = _RAND_2[0:0];
_RAND_3 = {1{`RANDOM}};
a_ff = _RAND_3[31:0];
_RAND_4 = {1{`RANDOM}};
count_ff = _RAND_4[6:0];
_RAND_5 = {1{`RANDOM}};
shortq_enable_ff = _RAND_5[0:0];
_RAND_6 = {1{`RANDOM}};
finish_ff = _RAND_6[0:0];
_RAND_7 = {1{`RANDOM}};
shortq_shift_ff = _RAND_7[4:0];
_RAND_8 = {1{`RANDOM}};
by_zero_case_ff = _RAND_8[0:0];
_RAND_9 = {1{`RANDOM}};
r_ff = _RAND_9[31:0];
_RAND_10 = {1{`RANDOM}};
q_ff = _RAND_10[31:0];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
control_ff = 3'h0;
end
if (reset) begin
b_ff = 33'h0;
end
if (reset) begin
valid_ff = 1'h0;
end
if (reset) begin
a_ff = 32'h0;
end
if (reset) begin
count_ff = 7'h0;
end
if (reset) begin
shortq_enable_ff = 1'h0;
end
if (reset) begin
finish_ff = 1'h0;
end
if (reset) begin
shortq_shift_ff = 5'h0;
end
if (reset) begin
by_zero_case_ff = 1'h0;
end
if (reset) begin
r_ff = 32'h0;
end
if (reset) begin
q_ff = 32'h0;
end
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
always @(posedge clock or posedge reset) begin
if (reset) begin
control_ff <= 3'h0;
end else if (misc_enable) begin
control_ff <= control_in;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
b_ff <= 33'h0;
end else if (b_enable) begin
b_ff <= b_in;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
valid_ff <= 1'h0;
end else if (misc_enable) begin
valid_ff <= valid_ff_in;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
a_ff <= 32'h0;
end else if (a_enable) begin
a_ff <= a_in;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
count_ff <= 7'h0;
end else if (misc_enable) begin
count_ff <= count_in;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
shortq_enable_ff <= 1'h0;
end else if (misc_enable) begin
shortq_enable_ff <= shortq_enable;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
finish_ff <= 1'h0;
end else if (misc_enable) begin
finish_ff <= finish;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
shortq_shift_ff <= 5'h0;
end else if (misc_enable) begin
if (_T_58) begin
shortq_shift_ff <= 5'h0;
end else begin
shortq_shift_ff <= _T_861;
end
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
by_zero_case_ff <= 1'h0;
end else if (misc_enable) begin
by_zero_case_ff <= by_zero_case;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
r_ff <= 32'h0;
end else if (rq_enable) begin
r_ff <= r_in;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
q_ff <= 32'h0;
end else if (rq_enable) begin
q_ff <= q_in;
end
end
endmodule

30
exu_div_new_2bit_fullshortq.anno.json Normal file
View File

@ -0,0 +1,30 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~exu_div_new_2bit_fullshortq|exu_div_new_2bit_fullshortq>io_valid_out",
"sources":[
"~exu_div_new_2bit_fullshortq|exu_div_new_2bit_fullshortq>io_cancel"
]
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"exu_div_new_2bit_fullshortq.gated_latch",
"resourceId":"/vsrc/gated_latch.sv"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"exu_div_new_2bit_fullshortq"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

2174
exu_div_new_2bit_fullshortq.fir Normal file
View File

File diff suppressed because it is too large Load Diff

788
exu_div_new_2bit_fullshortq.v Normal file
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@ -0,0 +1,788 @@
module exu_div_cls(
input [32:0] io_operand,
output [4:0] io_cls
);
wire _T_3 = io_operand[31:30] == 2'h1; // @[exu_div_ctl.scala 655:63]
wire _T_5 = io_operand[31:29] == 3'h1; // @[exu_div_ctl.scala 655:63]
wire _T_7 = io_operand[31:28] == 4'h1; // @[exu_div_ctl.scala 655:63]
wire _T_9 = io_operand[31:27] == 5'h1; // @[exu_div_ctl.scala 655:63]
wire _T_11 = io_operand[31:26] == 6'h1; // @[exu_div_ctl.scala 655:63]
wire _T_13 = io_operand[31:25] == 7'h1; // @[exu_div_ctl.scala 655:63]
wire _T_15 = io_operand[31:24] == 8'h1; // @[exu_div_ctl.scala 655:63]
wire _T_17 = io_operand[31:23] == 9'h1; // @[exu_div_ctl.scala 655:63]
wire _T_19 = io_operand[31:22] == 10'h1; // @[exu_div_ctl.scala 655:63]
wire _T_21 = io_operand[31:21] == 11'h1; // @[exu_div_ctl.scala 655:63]
wire _T_23 = io_operand[31:20] == 12'h1; // @[exu_div_ctl.scala 655:63]
wire _T_25 = io_operand[31:19] == 13'h1; // @[exu_div_ctl.scala 655:63]
wire _T_27 = io_operand[31:18] == 14'h1; // @[exu_div_ctl.scala 655:63]
wire _T_29 = io_operand[31:17] == 15'h1; // @[exu_div_ctl.scala 655:63]
wire _T_31 = io_operand[31:16] == 16'h1; // @[exu_div_ctl.scala 655:63]
wire _T_33 = io_operand[31:15] == 17'h1; // @[exu_div_ctl.scala 655:63]
wire _T_35 = io_operand[31:14] == 18'h1; // @[exu_div_ctl.scala 655:63]
wire _T_37 = io_operand[31:13] == 19'h1; // @[exu_div_ctl.scala 655:63]
wire _T_39 = io_operand[31:12] == 20'h1; // @[exu_div_ctl.scala 655:63]
wire _T_41 = io_operand[31:11] == 21'h1; // @[exu_div_ctl.scala 655:63]
wire _T_43 = io_operand[31:10] == 22'h1; // @[exu_div_ctl.scala 655:63]
wire _T_45 = io_operand[31:9] == 23'h1; // @[exu_div_ctl.scala 655:63]
wire _T_47 = io_operand[31:8] == 24'h1; // @[exu_div_ctl.scala 655:63]
wire _T_49 = io_operand[31:7] == 25'h1; // @[exu_div_ctl.scala 655:63]
wire _T_51 = io_operand[31:6] == 26'h1; // @[exu_div_ctl.scala 655:63]
wire _T_53 = io_operand[31:5] == 27'h1; // @[exu_div_ctl.scala 655:63]
wire _T_55 = io_operand[31:4] == 28'h1; // @[exu_div_ctl.scala 655:63]
wire _T_57 = io_operand[31:3] == 29'h1; // @[exu_div_ctl.scala 655:63]
wire _T_59 = io_operand[31:2] == 30'h1; // @[exu_div_ctl.scala 655:63]
wire _T_61 = io_operand[31:1] == 31'h1; // @[exu_div_ctl.scala 655:63]
wire _T_63 = io_operand[31:0] == 32'h1; // @[exu_div_ctl.scala 655:63]
wire [1:0] _T_66 = _T_5 ? 2'h2 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_67 = _T_7 ? 2'h3 : 2'h0; // @[Mux.scala 27:72]
wire [2:0] _T_68 = _T_9 ? 3'h4 : 3'h0; // @[Mux.scala 27:72]
wire [2:0] _T_69 = _T_11 ? 3'h5 : 3'h0; // @[Mux.scala 27:72]
wire [2:0] _T_70 = _T_13 ? 3'h6 : 3'h0; // @[Mux.scala 27:72]
wire [2:0] _T_71 = _T_15 ? 3'h7 : 3'h0; // @[Mux.scala 27:72]
wire [3:0] _T_72 = _T_17 ? 4'h8 : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_73 = _T_19 ? 4'h9 : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_74 = _T_21 ? 4'ha : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_75 = _T_23 ? 4'hb : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_76 = _T_25 ? 4'hc : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_77 = _T_27 ? 4'hd : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_78 = _T_29 ? 4'he : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_79 = _T_31 ? 4'hf : 4'h0; // @[Mux.scala 27:72]
wire [4:0] _T_80 = _T_33 ? 5'h10 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_81 = _T_35 ? 5'h11 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_82 = _T_37 ? 5'h12 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_83 = _T_39 ? 5'h13 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_84 = _T_41 ? 5'h14 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_85 = _T_43 ? 5'h15 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_86 = _T_45 ? 5'h16 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_87 = _T_47 ? 5'h17 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_88 = _T_49 ? 5'h18 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_89 = _T_51 ? 5'h19 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_90 = _T_53 ? 5'h1a : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_91 = _T_55 ? 5'h1b : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_92 = _T_57 ? 5'h1c : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_93 = _T_59 ? 5'h1d : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_94 = _T_61 ? 5'h1e : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_95 = _T_63 ? 5'h1f : 5'h0; // @[Mux.scala 27:72]
wire [1:0] _GEN_1 = {{1'd0}, _T_3}; // @[Mux.scala 27:72]
wire [1:0] _T_97 = _GEN_1 | _T_66; // @[Mux.scala 27:72]
wire [1:0] _T_98 = _T_97 | _T_67; // @[Mux.scala 27:72]
wire [2:0] _GEN_2 = {{1'd0}, _T_98}; // @[Mux.scala 27:72]
wire [2:0] _T_99 = _GEN_2 | _T_68; // @[Mux.scala 27:72]
wire [2:0] _T_100 = _T_99 | _T_69; // @[Mux.scala 27:72]
wire [2:0] _T_101 = _T_100 | _T_70; // @[Mux.scala 27:72]
wire [2:0] _T_102 = _T_101 | _T_71; // @[Mux.scala 27:72]
wire [3:0] _GEN_3 = {{1'd0}, _T_102}; // @[Mux.scala 27:72]
wire [3:0] _T_103 = _GEN_3 | _T_72; // @[Mux.scala 27:72]
wire [3:0] _T_104 = _T_103 | _T_73; // @[Mux.scala 27:72]
wire [3:0] _T_105 = _T_104 | _T_74; // @[Mux.scala 27:72]
wire [3:0] _T_106 = _T_105 | _T_75; // @[Mux.scala 27:72]
wire [3:0] _T_107 = _T_106 | _T_76; // @[Mux.scala 27:72]
wire [3:0] _T_108 = _T_107 | _T_77; // @[Mux.scala 27:72]
wire [3:0] _T_109 = _T_108 | _T_78; // @[Mux.scala 27:72]
wire [3:0] _T_110 = _T_109 | _T_79; // @[Mux.scala 27:72]
wire [4:0] _GEN_4 = {{1'd0}, _T_110}; // @[Mux.scala 27:72]
wire [4:0] _T_111 = _GEN_4 | _T_80; // @[Mux.scala 27:72]
wire [4:0] _T_112 = _T_111 | _T_81; // @[Mux.scala 27:72]
wire [4:0] _T_113 = _T_112 | _T_82; // @[Mux.scala 27:72]
wire [4:0] _T_114 = _T_113 | _T_83; // @[Mux.scala 27:72]
wire [4:0] _T_115 = _T_114 | _T_84; // @[Mux.scala 27:72]
wire [4:0] _T_116 = _T_115 | _T_85; // @[Mux.scala 27:72]
wire [4:0] _T_117 = _T_116 | _T_86; // @[Mux.scala 27:72]
wire [4:0] _T_118 = _T_117 | _T_87; // @[Mux.scala 27:72]
wire [4:0] _T_119 = _T_118 | _T_88; // @[Mux.scala 27:72]
wire [4:0] _T_120 = _T_119 | _T_89; // @[Mux.scala 27:72]
wire [4:0] _T_121 = _T_120 | _T_90; // @[Mux.scala 27:72]
wire [4:0] _T_122 = _T_121 | _T_91; // @[Mux.scala 27:72]
wire [4:0] _T_123 = _T_122 | _T_92; // @[Mux.scala 27:72]
wire [4:0] _T_124 = _T_123 | _T_93; // @[Mux.scala 27:72]
wire [4:0] _T_125 = _T_124 | _T_94; // @[Mux.scala 27:72]
wire [4:0] cls_zeros = _T_125 | _T_95; // @[Mux.scala 27:72]
wire _T_129 = io_operand[31:0] == 32'hffffffff; // @[exu_div_ctl.scala 657:25]
wire _T_137 = io_operand[31:29] == 3'h6; // @[exu_div_ctl.scala 658:76]
wire _T_142 = io_operand[31:28] == 4'he; // @[exu_div_ctl.scala 658:76]
wire _T_147 = io_operand[31:27] == 5'h1e; // @[exu_div_ctl.scala 658:76]
wire _T_152 = io_operand[31:26] == 6'h3e; // @[exu_div_ctl.scala 658:76]
wire _T_157 = io_operand[31:25] == 7'h7e; // @[exu_div_ctl.scala 658:76]
wire _T_162 = io_operand[31:24] == 8'hfe; // @[exu_div_ctl.scala 658:76]
wire _T_167 = io_operand[31:23] == 9'h1fe; // @[exu_div_ctl.scala 658:76]
wire _T_172 = io_operand[31:22] == 10'h3fe; // @[exu_div_ctl.scala 658:76]
wire _T_177 = io_operand[31:21] == 11'h7fe; // @[exu_div_ctl.scala 658:76]
wire _T_182 = io_operand[31:20] == 12'hffe; // @[exu_div_ctl.scala 658:76]
wire _T_187 = io_operand[31:19] == 13'h1ffe; // @[exu_div_ctl.scala 658:76]
wire _T_192 = io_operand[31:18] == 14'h3ffe; // @[exu_div_ctl.scala 658:76]
wire _T_197 = io_operand[31:17] == 15'h7ffe; // @[exu_div_ctl.scala 658:76]
wire _T_202 = io_operand[31:16] == 16'hfffe; // @[exu_div_ctl.scala 658:76]
wire _T_207 = io_operand[31:15] == 17'h1fffe; // @[exu_div_ctl.scala 658:76]
wire _T_212 = io_operand[31:14] == 18'h3fffe; // @[exu_div_ctl.scala 658:76]
wire _T_217 = io_operand[31:13] == 19'h7fffe; // @[exu_div_ctl.scala 658:76]
wire _T_222 = io_operand[31:12] == 20'hffffe; // @[exu_div_ctl.scala 658:76]
wire _T_227 = io_operand[31:11] == 21'h1ffffe; // @[exu_div_ctl.scala 658:76]
wire _T_232 = io_operand[31:10] == 22'h3ffffe; // @[exu_div_ctl.scala 658:76]
wire _T_237 = io_operand[31:9] == 23'h7ffffe; // @[exu_div_ctl.scala 658:76]
wire _T_242 = io_operand[31:8] == 24'hfffffe; // @[exu_div_ctl.scala 658:76]
wire _T_247 = io_operand[31:7] == 25'h1fffffe; // @[exu_div_ctl.scala 658:76]
wire _T_252 = io_operand[31:6] == 26'h3fffffe; // @[exu_div_ctl.scala 658:76]
wire _T_257 = io_operand[31:5] == 27'h7fffffe; // @[exu_div_ctl.scala 658:76]
wire _T_262 = io_operand[31:4] == 28'hffffffe; // @[exu_div_ctl.scala 658:76]
wire _T_267 = io_operand[31:3] == 29'h1ffffffe; // @[exu_div_ctl.scala 658:76]
wire _T_272 = io_operand[31:2] == 30'h3ffffffe; // @[exu_div_ctl.scala 658:76]
wire _T_277 = io_operand[31:1] == 31'h7ffffffe; // @[exu_div_ctl.scala 658:76]
wire _T_282 = io_operand[31:0] == 32'hfffffffe; // @[exu_div_ctl.scala 658:76]
wire [1:0] _T_286 = _T_142 ? 2'h2 : 2'h0; // @[Mux.scala 27:72]
wire [1:0] _T_287 = _T_147 ? 2'h3 : 2'h0; // @[Mux.scala 27:72]
wire [2:0] _T_288 = _T_152 ? 3'h4 : 3'h0; // @[Mux.scala 27:72]
wire [2:0] _T_289 = _T_157 ? 3'h5 : 3'h0; // @[Mux.scala 27:72]
wire [2:0] _T_290 = _T_162 ? 3'h6 : 3'h0; // @[Mux.scala 27:72]
wire [2:0] _T_291 = _T_167 ? 3'h7 : 3'h0; // @[Mux.scala 27:72]
wire [3:0] _T_292 = _T_172 ? 4'h8 : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_293 = _T_177 ? 4'h9 : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_294 = _T_182 ? 4'ha : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_295 = _T_187 ? 4'hb : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_296 = _T_192 ? 4'hc : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_297 = _T_197 ? 4'hd : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_298 = _T_202 ? 4'he : 4'h0; // @[Mux.scala 27:72]
wire [3:0] _T_299 = _T_207 ? 4'hf : 4'h0; // @[Mux.scala 27:72]
wire [4:0] _T_300 = _T_212 ? 5'h10 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_301 = _T_217 ? 5'h11 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_302 = _T_222 ? 5'h12 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_303 = _T_227 ? 5'h13 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_304 = _T_232 ? 5'h14 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_305 = _T_237 ? 5'h15 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_306 = _T_242 ? 5'h16 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_307 = _T_247 ? 5'h17 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_308 = _T_252 ? 5'h18 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_309 = _T_257 ? 5'h19 : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_310 = _T_262 ? 5'h1a : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_311 = _T_267 ? 5'h1b : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_312 = _T_272 ? 5'h1c : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_313 = _T_277 ? 5'h1d : 5'h0; // @[Mux.scala 27:72]
wire [4:0] _T_314 = _T_282 ? 5'h1e : 5'h0; // @[Mux.scala 27:72]
wire [1:0] _GEN_5 = {{1'd0}, _T_137}; // @[Mux.scala 27:72]
wire [1:0] _T_316 = _GEN_5 | _T_286; // @[Mux.scala 27:72]
wire [1:0] _T_317 = _T_316 | _T_287; // @[Mux.scala 27:72]
wire [2:0] _GEN_6 = {{1'd0}, _T_317}; // @[Mux.scala 27:72]
wire [2:0] _T_318 = _GEN_6 | _T_288; // @[Mux.scala 27:72]
wire [2:0] _T_319 = _T_318 | _T_289; // @[Mux.scala 27:72]
wire [2:0] _T_320 = _T_319 | _T_290; // @[Mux.scala 27:72]
wire [2:0] _T_321 = _T_320 | _T_291; // @[Mux.scala 27:72]
wire [3:0] _GEN_7 = {{1'd0}, _T_321}; // @[Mux.scala 27:72]
wire [3:0] _T_322 = _GEN_7 | _T_292; // @[Mux.scala 27:72]
wire [3:0] _T_323 = _T_322 | _T_293; // @[Mux.scala 27:72]
wire [3:0] _T_324 = _T_323 | _T_294; // @[Mux.scala 27:72]
wire [3:0] _T_325 = _T_324 | _T_295; // @[Mux.scala 27:72]
wire [3:0] _T_326 = _T_325 | _T_296; // @[Mux.scala 27:72]
wire [3:0] _T_327 = _T_326 | _T_297; // @[Mux.scala 27:72]
wire [3:0] _T_328 = _T_327 | _T_298; // @[Mux.scala 27:72]
wire [3:0] _T_329 = _T_328 | _T_299; // @[Mux.scala 27:72]
wire [4:0] _GEN_8 = {{1'd0}, _T_329}; // @[Mux.scala 27:72]
wire [4:0] _T_330 = _GEN_8 | _T_300; // @[Mux.scala 27:72]
wire [4:0] _T_331 = _T_330 | _T_301; // @[Mux.scala 27:72]
wire [4:0] _T_332 = _T_331 | _T_302; // @[Mux.scala 27:72]
wire [4:0] _T_333 = _T_332 | _T_303; // @[Mux.scala 27:72]
wire [4:0] _T_334 = _T_333 | _T_304; // @[Mux.scala 27:72]
wire [4:0] _T_335 = _T_334 | _T_305; // @[Mux.scala 27:72]
wire [4:0] _T_336 = _T_335 | _T_306; // @[Mux.scala 27:72]
wire [4:0] _T_337 = _T_336 | _T_307; // @[Mux.scala 27:72]
wire [4:0] _T_338 = _T_337 | _T_308; // @[Mux.scala 27:72]
wire [4:0] _T_339 = _T_338 | _T_309; // @[Mux.scala 27:72]
wire [4:0] _T_340 = _T_339 | _T_310; // @[Mux.scala 27:72]
wire [4:0] _T_341 = _T_340 | _T_311; // @[Mux.scala 27:72]
wire [4:0] _T_342 = _T_341 | _T_312; // @[Mux.scala 27:72]
wire [4:0] _T_343 = _T_342 | _T_313; // @[Mux.scala 27:72]
wire [4:0] _T_344 = _T_343 | _T_314; // @[Mux.scala 27:72]
wire [4:0] cls_ones = _T_129 ? 5'h1f : _T_344; // @[exu_div_ctl.scala 657:44]
assign io_cls = io_operand[32] ? cls_ones : cls_zeros; // @[exu_div_ctl.scala 659:10]
endmodule
module rvclkhdr(
input io_clk,
input io_en
);
wire clkhdr_Q; // @[lib.scala 334:26]
wire clkhdr_CK; // @[lib.scala 334:26]
wire clkhdr_EN; // @[lib.scala 334:26]
wire clkhdr_SE; // @[lib.scala 334:26]
gated_latch clkhdr ( // @[lib.scala 334:26]
.Q(clkhdr_Q),
.CK(clkhdr_CK),
.EN(clkhdr_EN),
.SE(clkhdr_SE)
);
assign clkhdr_CK = io_clk; // @[lib.scala 336:18]
assign clkhdr_EN = io_en; // @[lib.scala 337:18]
assign clkhdr_SE = 1'h0; // @[lib.scala 338:18]
endmodule
module exu_div_new_2bit_fullshortq(
input clock,
input reset,
input io_scan_mode,
input io_cancel,
input io_valid_in,
input io_signed_in,
input io_rem_in,
input [31:0] io_dividend_in,
input [31:0] io_divisor_in,
output [31:0] io_data_out,
output io_valid_out
);
`ifdef RANDOMIZE_REG_INIT
reg [31:0] _RAND_0;
reg [63:0] _RAND_1;
reg [31:0] _RAND_2;
reg [31:0] _RAND_3;
reg [31:0] _RAND_4;
reg [31:0] _RAND_5;
reg [31:0] _RAND_6;
reg [31:0] _RAND_7;
reg [31:0] _RAND_8;
reg [31:0] _RAND_9;
reg [31:0] _RAND_10;
`endif // RANDOMIZE_REG_INIT
wire [32:0] a_enc_io_operand; // @[exu_div_ctl.scala 584:21]
wire [4:0] a_enc_io_cls; // @[exu_div_ctl.scala 584:21]
wire [32:0] b_enc_io_operand; // @[exu_div_ctl.scala 587:21]
wire [4:0] b_enc_io_cls; // @[exu_div_ctl.scala 587:21]
wire rvclkhdr_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_io_en; // @[lib.scala 390:23]
wire rvclkhdr_1_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_1_io_en; // @[lib.scala 390:23]
wire rvclkhdr_2_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_2_io_en; // @[lib.scala 390:23]
wire rvclkhdr_3_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_3_io_en; // @[lib.scala 390:23]
wire rvclkhdr_4_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_4_io_en; // @[lib.scala 390:23]
wire rvclkhdr_5_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_5_io_en; // @[lib.scala 390:23]
wire rvclkhdr_6_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_6_io_en; // @[lib.scala 390:23]
wire rvclkhdr_7_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_7_io_en; // @[lib.scala 390:23]
wire rvclkhdr_8_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_8_io_en; // @[lib.scala 390:23]
wire rvclkhdr_9_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_9_io_en; // @[lib.scala 390:23]
wire rvclkhdr_10_io_clk; // @[lib.scala 390:23]
wire rvclkhdr_10_io_en; // @[lib.scala 390:23]
wire _T = ~io_cancel; // @[exu_div_ctl.scala 488:35]
wire valid_ff_in = io_valid_in & _T; // @[exu_div_ctl.scala 488:33]
wire _T_1 = ~io_valid_in; // @[exu_div_ctl.scala 489:35]
reg [2:0] control_ff; // @[Reg.scala 27:20]
wire _T_3 = _T_1 & control_ff[2]; // @[exu_div_ctl.scala 489:48]
wire _T_4 = io_valid_in & io_signed_in; // @[exu_div_ctl.scala 489:80]
wire _T_6 = _T_4 & io_dividend_in[31]; // @[exu_div_ctl.scala 489:96]
wire _T_7 = _T_3 | _T_6; // @[exu_div_ctl.scala 489:65]
wire _T_10 = _T_1 & control_ff[1]; // @[exu_div_ctl.scala 489:133]
wire _T_13 = _T_4 & io_divisor_in[31]; // @[exu_div_ctl.scala 489:181]
wire _T_14 = _T_10 | _T_13; // @[exu_div_ctl.scala 489:150]
wire _T_17 = _T_1 & control_ff[0]; // @[exu_div_ctl.scala 489:218]
wire _T_18 = io_valid_in & io_rem_in; // @[exu_div_ctl.scala 489:250]
wire _T_19 = _T_17 | _T_18; // @[exu_div_ctl.scala 489:235]
wire [2:0] control_in = {_T_7,_T_14,_T_19}; // @[Cat.scala 29:58]
reg [32:0] b_ff1; // @[Reg.scala 27:20]
wire [34:0] b_ff = {b_ff1[32],b_ff1[32],b_ff1}; // @[Cat.scala 29:58]
wire _T_22 = b_ff[31:0] == 32'h0; // @[exu_div_ctl.scala 493:54]
reg valid_ff; // @[Reg.scala 27:20]
wire by_zero_case = valid_ff & _T_22; // @[exu_div_ctl.scala 493:40]
reg [31:0] a_ff; // @[Reg.scala 27:20]
wire _T_25 = ~by_zero_case; // @[exu_div_ctl.scala 496:29]
wire _T_27 = ~control_ff[0]; // @[exu_div_ctl.scala 496:45]
reg [6:0] count_ff; // @[Reg.scala 27:20]
wire _T_32 = |count_ff; // @[exu_div_ctl.scala 497:42]
reg shortq_enable_ff; // @[Reg.scala 27:20]
wire running_state = _T_32 | shortq_enable_ff; // @[exu_div_ctl.scala 497:45]
wire _T_33 = io_valid_in | valid_ff; // @[exu_div_ctl.scala 498:43]
wire _T_34 = _T_33 | io_cancel; // @[exu_div_ctl.scala 498:54]
wire _T_35 = _T_34 | running_state; // @[exu_div_ctl.scala 498:66]
reg finish_ff; // @[Reg.scala 27:20]
wire misc_enable = _T_35 | finish_ff; // @[exu_div_ctl.scala 498:82]
wire _T_37 = count_ff == 7'h20; // @[exu_div_ctl.scala 499:72]
wire finish_raw = by_zero_case | _T_37; // @[exu_div_ctl.scala 499:60]
wire finish = finish_raw & _T; // @[exu_div_ctl.scala 500:41]
wire _T_39 = valid_ff | running_state; // @[exu_div_ctl.scala 501:40]
wire _T_40 = ~finish; // @[exu_div_ctl.scala 501:59]
wire _T_41 = _T_39 & _T_40; // @[exu_div_ctl.scala 501:57]
wire _T_42 = ~finish_ff; // @[exu_div_ctl.scala 501:69]
wire _T_43 = _T_41 & _T_42; // @[exu_div_ctl.scala 501:67]
wire _T_45 = _T_43 & _T; // @[exu_div_ctl.scala 501:80]
wire [6:0] _T_890 = {1'h0,1'h0,b_enc_io_cls}; // @[Cat.scala 29:58]
wire [6:0] _T_891 = {1'h0,1'h0,a_enc_io_cls}; // @[Cat.scala 29:58]
wire [6:0] _T_893 = _T_890 - _T_891; // @[exu_div_ctl.scala 592:41]
wire [6:0] dw_shortq_raw = _T_893 + 7'h1; // @[exu_div_ctl.scala 592:61]
wire [5:0] shortq = dw_shortq_raw[6] ? 6'h0 : dw_shortq_raw[5:0]; // @[exu_div_ctl.scala 593:19]
wire _T_899 = ~shortq[5]; // @[exu_div_ctl.scala 594:31]
wire _T_900 = valid_ff & _T_899; // @[exu_div_ctl.scala 594:29]
wire _T_902 = shortq[4:1] == 4'hf; // @[exu_div_ctl.scala 594:58]
wire _T_903 = ~_T_902; // @[exu_div_ctl.scala 594:44]
wire _T_904 = _T_900 & _T_903; // @[exu_div_ctl.scala 594:42]
wire shortq_enable = _T_904 & _T; // @[exu_div_ctl.scala 594:74]
wire _T_46 = ~shortq_enable; // @[exu_div_ctl.scala 501:95]
wire count_enable = _T_45 & _T_46; // @[exu_div_ctl.scala 501:93]
wire [6:0] _T_48 = count_enable ? 7'h7f : 7'h0; // @[Bitwise.scala 72:12]
wire [6:0] _T_51 = count_ff + 7'h2; // @[exu_div_ctl.scala 502:63]
reg [3:0] shortq_shift_ff; // @[Reg.scala 27:20]
wire [6:0] _T_53 = {2'h0,shortq_shift_ff,1'h0}; // @[Cat.scala 29:58]
wire [6:0] _T_55 = _T_51 + _T_53; // @[exu_div_ctl.scala 502:83]
wire [6:0] count_in = _T_48 & _T_55; // @[exu_div_ctl.scala 502:51]
wire a_enable = io_valid_in | running_state; // @[exu_div_ctl.scala 503:43]
wire _T_56 = ~shortq_enable_ff; // @[exu_div_ctl.scala 504:47]
wire a_shift = running_state & _T_56; // @[exu_div_ctl.scala 504:45]
wire [31:0] _T_58 = control_ff[2] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12]
wire [63:0] _T_59 = {_T_58,a_ff}; // @[Cat.scala 29:58]
wire [4:0] _T_60 = {shortq_shift_ff,1'h0}; // @[Cat.scala 29:58]
wire [94:0] _GEN_11 = {{31'd0}, _T_59}; // @[exu_div_ctl.scala 505:68]
wire [94:0] _T_61 = _GEN_11 << _T_60; // @[exu_div_ctl.scala 505:68]
wire _T_62 = control_ff[2] ^ control_ff[1]; // @[exu_div_ctl.scala 506:61]
wire _T_63 = ~_T_62; // @[exu_div_ctl.scala 506:42]
wire b_twos_comp = valid_ff & _T_63; // @[exu_div_ctl.scala 506:40]
wire _T_66 = ~valid_ff; // @[exu_div_ctl.scala 508:30]
wire _T_68 = _T_66 & _T_27; // @[exu_div_ctl.scala 508:40]
wire _T_70 = _T_68 & _T_62; // @[exu_div_ctl.scala 508:50]
reg by_zero_case_ff; // @[Reg.scala 27:20]
wire _T_71 = ~by_zero_case_ff; // @[exu_div_ctl.scala 508:92]
wire twos_comp_q_sel = _T_70 & _T_71; // @[exu_div_ctl.scala 508:90]
wire b_enable = io_valid_in | b_twos_comp; // @[exu_div_ctl.scala 509:43]
wire rq_enable = _T_33 | running_state; // @[exu_div_ctl.scala 510:54]
wire _T_73 = valid_ff & control_ff[2]; // @[exu_div_ctl.scala 511:40]
wire r_sign_sel = _T_73 & _T_25; // @[exu_div_ctl.scala 511:59]
reg [31:0] r_ff; // @[Reg.scala 27:20]
wire [34:0] _T_102 = {r_ff[31],r_ff,a_ff[31:30]}; // @[Cat.scala 29:58]
wire [34:0] _T_104 = {b_ff[33:0],1'h0}; // @[Cat.scala 29:58]
wire [34:0] _T_106 = _T_102 + _T_104; // @[exu_div_ctl.scala 518:57]
wire [34:0] adder3_out = _T_106 + b_ff; // @[exu_div_ctl.scala 518:79]
wire _T_109 = ~adder3_out[34]; // @[exu_div_ctl.scala 519:24]
wire _T_110 = _T_109 ^ control_ff[2]; // @[exu_div_ctl.scala 519:40]
wire _T_112 = a_ff[29:0] == 30'h0; // @[exu_div_ctl.scala 519:75]
wire _T_113 = adder3_out == 35'h0; // @[exu_div_ctl.scala 519:98]
wire _T_114 = _T_112 & _T_113; // @[exu_div_ctl.scala 519:84]
wire _T_115 = _T_110 | _T_114; // @[exu_div_ctl.scala 519:60]
wire [32:0] _T_94 = {r_ff[30:0],a_ff[31:30]}; // @[Cat.scala 29:58]
wire [33:0] _T_96 = {b_ff[32:0],1'h0}; // @[Cat.scala 29:58]
wire [33:0] _GEN_12 = {{1'd0}, _T_94}; // @[exu_div_ctl.scala 517:48]
wire [33:0] adder2_out = _GEN_12 + _T_96; // @[exu_div_ctl.scala 517:48]
wire _T_117 = ~adder2_out[33]; // @[exu_div_ctl.scala 520:6]
wire _T_118 = _T_117 ^ control_ff[2]; // @[exu_div_ctl.scala 520:22]
wire _T_121 = adder2_out == 34'h0; // @[exu_div_ctl.scala 520:80]
wire _T_122 = _T_112 & _T_121; // @[exu_div_ctl.scala 520:66]
wire _T_123 = _T_118 | _T_122; // @[exu_div_ctl.scala 520:42]
wire [32:0] adder1_out = _T_94 + b_ff[32:0]; // @[exu_div_ctl.scala 516:48]
wire _T_125 = ~adder1_out[32]; // @[exu_div_ctl.scala 521:6]
wire _T_126 = _T_125 ^ control_ff[2]; // @[exu_div_ctl.scala 521:22]
wire _T_129 = adder1_out == 33'h0; // @[exu_div_ctl.scala 521:80]
wire _T_130 = _T_112 & _T_129; // @[exu_div_ctl.scala 521:66]
wire _T_131 = _T_126 | _T_130; // @[exu_div_ctl.scala 521:42]
wire [2:0] quotient_raw = {_T_115,_T_123,_T_131}; // @[Cat.scala 29:58]
wire _T_136 = quotient_raw[2] | quotient_raw[1]; // @[exu_div_ctl.scala 522:41]
wire _T_139 = ~quotient_raw[1]; // @[exu_div_ctl.scala 522:82]
wire _T_141 = _T_139 & quotient_raw[0]; // @[exu_div_ctl.scala 522:99]
wire _T_142 = quotient_raw[2] | _T_141; // @[exu_div_ctl.scala 522:80]
wire [1:0] quotient_new = {_T_136,_T_142}; // @[Cat.scala 29:58]
wire _T_75 = quotient_new == 2'h0; // @[exu_div_ctl.scala 512:61]
wire _T_76 = running_state & _T_75; // @[exu_div_ctl.scala 512:45]
wire r_restore_sel = _T_76 & _T_56; // @[exu_div_ctl.scala 512:70]
wire _T_78 = quotient_new == 2'h1; // @[exu_div_ctl.scala 513:61]
wire _T_79 = running_state & _T_78; // @[exu_div_ctl.scala 513:45]
wire r_adder1_sel = _T_79 & _T_56; // @[exu_div_ctl.scala 513:70]
wire _T_81 = quotient_new == 2'h2; // @[exu_div_ctl.scala 514:61]
wire _T_82 = running_state & _T_81; // @[exu_div_ctl.scala 514:45]
wire r_adder2_sel = _T_82 & _T_56; // @[exu_div_ctl.scala 514:70]
wire _T_84 = quotient_new == 2'h3; // @[exu_div_ctl.scala 515:61]
wire _T_85 = running_state & _T_84; // @[exu_div_ctl.scala 515:45]
wire r_adder3_sel = _T_85 & _T_56; // @[exu_div_ctl.scala 515:70]
reg [31:0] q_ff; // @[Reg.scala 27:20]
wire [31:0] _T_145 = twos_comp_q_sel ? q_ff : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_146 = b_twos_comp ? b_ff[31:0] : 32'h0; // @[Mux.scala 27:72]
wire [31:0] twos_comp_in = _T_145 | _T_146; // @[Mux.scala 27:72]
wire _T_150 = |twos_comp_in[0]; // @[lib.scala 428:35]
wire _T_152 = ~twos_comp_in[1]; // @[lib.scala 428:40]
wire _T_154 = _T_150 ? _T_152 : twos_comp_in[1]; // @[lib.scala 428:23]
wire _T_156 = |twos_comp_in[1:0]; // @[lib.scala 428:35]
wire _T_158 = ~twos_comp_in[2]; // @[lib.scala 428:40]
wire _T_160 = _T_156 ? _T_158 : twos_comp_in[2]; // @[lib.scala 428:23]
wire _T_162 = |twos_comp_in[2:0]; // @[lib.scala 428:35]
wire _T_164 = ~twos_comp_in[3]; // @[lib.scala 428:40]
wire _T_166 = _T_162 ? _T_164 : twos_comp_in[3]; // @[lib.scala 428:23]
wire _T_168 = |twos_comp_in[3:0]; // @[lib.scala 428:35]
wire _T_170 = ~twos_comp_in[4]; // @[lib.scala 428:40]
wire _T_172 = _T_168 ? _T_170 : twos_comp_in[4]; // @[lib.scala 428:23]
wire _T_174 = |twos_comp_in[4:0]; // @[lib.scala 428:35]
wire _T_176 = ~twos_comp_in[5]; // @[lib.scala 428:40]
wire _T_178 = _T_174 ? _T_176 : twos_comp_in[5]; // @[lib.scala 428:23]
wire _T_180 = |twos_comp_in[5:0]; // @[lib.scala 428:35]
wire _T_182 = ~twos_comp_in[6]; // @[lib.scala 428:40]
wire _T_184 = _T_180 ? _T_182 : twos_comp_in[6]; // @[lib.scala 428:23]
wire _T_186 = |twos_comp_in[6:0]; // @[lib.scala 428:35]
wire _T_188 = ~twos_comp_in[7]; // @[lib.scala 428:40]
wire _T_190 = _T_186 ? _T_188 : twos_comp_in[7]; // @[lib.scala 428:23]
wire _T_192 = |twos_comp_in[7:0]; // @[lib.scala 428:35]
wire _T_194 = ~twos_comp_in[8]; // @[lib.scala 428:40]
wire _T_196 = _T_192 ? _T_194 : twos_comp_in[8]; // @[lib.scala 428:23]
wire _T_198 = |twos_comp_in[8:0]; // @[lib.scala 428:35]
wire _T_200 = ~twos_comp_in[9]; // @[lib.scala 428:40]
wire _T_202 = _T_198 ? _T_200 : twos_comp_in[9]; // @[lib.scala 428:23]
wire _T_204 = |twos_comp_in[9:0]; // @[lib.scala 428:35]
wire _T_206 = ~twos_comp_in[10]; // @[lib.scala 428:40]
wire _T_208 = _T_204 ? _T_206 : twos_comp_in[10]; // @[lib.scala 428:23]
wire _T_210 = |twos_comp_in[10:0]; // @[lib.scala 428:35]
wire _T_212 = ~twos_comp_in[11]; // @[lib.scala 428:40]
wire _T_214 = _T_210 ? _T_212 : twos_comp_in[11]; // @[lib.scala 428:23]
wire _T_216 = |twos_comp_in[11:0]; // @[lib.scala 428:35]
wire _T_218 = ~twos_comp_in[12]; // @[lib.scala 428:40]
wire _T_220 = _T_216 ? _T_218 : twos_comp_in[12]; // @[lib.scala 428:23]
wire _T_222 = |twos_comp_in[12:0]; // @[lib.scala 428:35]
wire _T_224 = ~twos_comp_in[13]; // @[lib.scala 428:40]
wire _T_226 = _T_222 ? _T_224 : twos_comp_in[13]; // @[lib.scala 428:23]
wire _T_228 = |twos_comp_in[13:0]; // @[lib.scala 428:35]
wire _T_230 = ~twos_comp_in[14]; // @[lib.scala 428:40]
wire _T_232 = _T_228 ? _T_230 : twos_comp_in[14]; // @[lib.scala 428:23]
wire _T_234 = |twos_comp_in[14:0]; // @[lib.scala 428:35]
wire _T_236 = ~twos_comp_in[15]; // @[lib.scala 428:40]
wire _T_238 = _T_234 ? _T_236 : twos_comp_in[15]; // @[lib.scala 428:23]
wire _T_240 = |twos_comp_in[15:0]; // @[lib.scala 428:35]
wire _T_242 = ~twos_comp_in[16]; // @[lib.scala 428:40]
wire _T_244 = _T_240 ? _T_242 : twos_comp_in[16]; // @[lib.scala 428:23]
wire _T_246 = |twos_comp_in[16:0]; // @[lib.scala 428:35]
wire _T_248 = ~twos_comp_in[17]; // @[lib.scala 428:40]
wire _T_250 = _T_246 ? _T_248 : twos_comp_in[17]; // @[lib.scala 428:23]
wire _T_252 = |twos_comp_in[17:0]; // @[lib.scala 428:35]
wire _T_254 = ~twos_comp_in[18]; // @[lib.scala 428:40]
wire _T_256 = _T_252 ? _T_254 : twos_comp_in[18]; // @[lib.scala 428:23]
wire _T_258 = |twos_comp_in[18:0]; // @[lib.scala 428:35]
wire _T_260 = ~twos_comp_in[19]; // @[lib.scala 428:40]
wire _T_262 = _T_258 ? _T_260 : twos_comp_in[19]; // @[lib.scala 428:23]
wire _T_264 = |twos_comp_in[19:0]; // @[lib.scala 428:35]
wire _T_266 = ~twos_comp_in[20]; // @[lib.scala 428:40]
wire _T_268 = _T_264 ? _T_266 : twos_comp_in[20]; // @[lib.scala 428:23]
wire _T_270 = |twos_comp_in[20:0]; // @[lib.scala 428:35]
wire _T_272 = ~twos_comp_in[21]; // @[lib.scala 428:40]
wire _T_274 = _T_270 ? _T_272 : twos_comp_in[21]; // @[lib.scala 428:23]
wire _T_276 = |twos_comp_in[21:0]; // @[lib.scala 428:35]
wire _T_278 = ~twos_comp_in[22]; // @[lib.scala 428:40]
wire _T_280 = _T_276 ? _T_278 : twos_comp_in[22]; // @[lib.scala 428:23]
wire _T_282 = |twos_comp_in[22:0]; // @[lib.scala 428:35]
wire _T_284 = ~twos_comp_in[23]; // @[lib.scala 428:40]
wire _T_286 = _T_282 ? _T_284 : twos_comp_in[23]; // @[lib.scala 428:23]
wire _T_288 = |twos_comp_in[23:0]; // @[lib.scala 428:35]
wire _T_290 = ~twos_comp_in[24]; // @[lib.scala 428:40]
wire _T_292 = _T_288 ? _T_290 : twos_comp_in[24]; // @[lib.scala 428:23]
wire _T_294 = |twos_comp_in[24:0]; // @[lib.scala 428:35]
wire _T_296 = ~twos_comp_in[25]; // @[lib.scala 428:40]
wire _T_298 = _T_294 ? _T_296 : twos_comp_in[25]; // @[lib.scala 428:23]
wire _T_300 = |twos_comp_in[25:0]; // @[lib.scala 428:35]
wire _T_302 = ~twos_comp_in[26]; // @[lib.scala 428:40]
wire _T_304 = _T_300 ? _T_302 : twos_comp_in[26]; // @[lib.scala 428:23]
wire _T_306 = |twos_comp_in[26:0]; // @[lib.scala 428:35]
wire _T_308 = ~twos_comp_in[27]; // @[lib.scala 428:40]
wire _T_310 = _T_306 ? _T_308 : twos_comp_in[27]; // @[lib.scala 428:23]
wire _T_312 = |twos_comp_in[27:0]; // @[lib.scala 428:35]
wire _T_314 = ~twos_comp_in[28]; // @[lib.scala 428:40]
wire _T_316 = _T_312 ? _T_314 : twos_comp_in[28]; // @[lib.scala 428:23]
wire _T_318 = |twos_comp_in[28:0]; // @[lib.scala 428:35]
wire _T_320 = ~twos_comp_in[29]; // @[lib.scala 428:40]
wire _T_322 = _T_318 ? _T_320 : twos_comp_in[29]; // @[lib.scala 428:23]
wire _T_324 = |twos_comp_in[29:0]; // @[lib.scala 428:35]
wire _T_326 = ~twos_comp_in[30]; // @[lib.scala 428:40]
wire _T_328 = _T_324 ? _T_326 : twos_comp_in[30]; // @[lib.scala 428:23]
wire _T_330 = |twos_comp_in[30:0]; // @[lib.scala 428:35]
wire _T_332 = ~twos_comp_in[31]; // @[lib.scala 428:40]
wire _T_334 = _T_330 ? _T_332 : twos_comp_in[31]; // @[lib.scala 428:23]
wire [6:0] _T_340 = {_T_190,_T_184,_T_178,_T_172,_T_166,_T_160,_T_154}; // @[lib.scala 430:14]
wire [14:0] _T_348 = {_T_238,_T_232,_T_226,_T_220,_T_214,_T_208,_T_202,_T_196,_T_340}; // @[lib.scala 430:14]
wire [7:0] _T_355 = {_T_286,_T_280,_T_274,_T_268,_T_262,_T_256,_T_250,_T_244}; // @[lib.scala 430:14]
wire [30:0] _T_364 = {_T_334,_T_328,_T_322,_T_316,_T_310,_T_304,_T_298,_T_292,_T_355,_T_348}; // @[lib.scala 430:14]
wire [31:0] twos_comp_out = {_T_364,twos_comp_in[0]}; // @[Cat.scala 29:58]
wire _T_366 = ~a_shift; // @[exu_div_ctl.scala 530:6]
wire _T_368 = _T_366 & _T_56; // @[exu_div_ctl.scala 530:15]
wire [31:0] _T_371 = {a_ff[29:0],2'h0}; // @[Cat.scala 29:58]
wire [63:0] ar_shifted = _T_61[63:0]; // @[exu_div_ctl.scala 505:28]
wire [31:0] _T_373 = _T_368 ? io_dividend_in : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_374 = a_shift ? _T_371 : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_375 = shortq_enable_ff ? ar_shifted[31:0] : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_376 = _T_373 | _T_374; // @[Mux.scala 27:72]
wire [31:0] a_in = _T_376 | _T_375; // @[Mux.scala 27:72]
wire _T_378 = ~b_twos_comp; // @[exu_div_ctl.scala 536:5]
wire _T_380 = io_signed_in & io_divisor_in[31]; // @[exu_div_ctl.scala 536:63]
wire [32:0] _T_382 = {_T_380,io_divisor_in}; // @[Cat.scala 29:58]
wire _T_383 = ~control_ff[1]; // @[exu_div_ctl.scala 537:49]
wire [32:0] _T_385 = {_T_383,_T_364,twos_comp_in[0]}; // @[Cat.scala 29:58]
wire [32:0] _T_386 = _T_378 ? _T_382 : 33'h0; // @[Mux.scala 27:72]
wire [32:0] _T_387 = b_twos_comp ? _T_385 : 33'h0; // @[Mux.scala 27:72]
wire [32:0] b_in = _T_386 | _T_387; // @[Mux.scala 27:72]
wire [31:0] _T_391 = {r_ff[29:0],a_ff[31:30]}; // @[Cat.scala 29:58]
wire [31:0] _T_396 = r_sign_sel ? 32'hffffffff : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_397 = r_restore_sel ? _T_391 : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_398 = r_adder1_sel ? adder1_out[31:0] : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_399 = r_adder2_sel ? adder2_out[31:0] : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_400 = r_adder3_sel ? adder3_out[31:0] : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_401 = shortq_enable_ff ? ar_shifted[63:32] : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_402 = by_zero_case ? a_ff : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_403 = _T_396 | _T_397; // @[Mux.scala 27:72]
wire [31:0] _T_404 = _T_403 | _T_398; // @[Mux.scala 27:72]
wire [31:0] _T_405 = _T_404 | _T_399; // @[Mux.scala 27:72]
wire [31:0] _T_406 = _T_405 | _T_400; // @[Mux.scala 27:72]
wire [31:0] _T_407 = _T_406 | _T_401; // @[Mux.scala 27:72]
wire [31:0] r_in = _T_407 | _T_402; // @[Mux.scala 27:72]
wire [31:0] _T_411 = {q_ff[29:0],_T_136,_T_142}; // @[Cat.scala 29:58]
wire [31:0] _T_414 = _T_66 ? _T_411 : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_416 = by_zero_case ? 32'hffffffff : 32'h0; // @[Mux.scala 27:72]
wire [31:0] q_in = _T_414 | _T_416; // @[Mux.scala 27:72]
wire _T_422 = ~twos_comp_q_sel; // @[exu_div_ctl.scala 555:16]
wire _T_423 = _T_27 & _T_422; // @[exu_div_ctl.scala 555:14]
wire [31:0] _T_425 = _T_423 ? q_ff : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_426 = control_ff[0] ? r_ff : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_427 = twos_comp_q_sel ? twos_comp_out : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_428 = _T_425 | _T_426; // @[Mux.scala 27:72]
wire [4:0] _T_910 = 5'h1f - shortq[4:0]; // @[exu_div_ctl.scala 595:57]
wire [4:0] shortq_shift = _T_46 ? 5'h0 : _T_910; // @[exu_div_ctl.scala 595:25]
exu_div_cls a_enc ( // @[exu_div_ctl.scala 584:21]
.io_operand(a_enc_io_operand),
.io_cls(a_enc_io_cls)
);
exu_div_cls b_enc ( // @[exu_div_ctl.scala 587:21]
.io_operand(b_enc_io_operand),
.io_cls(b_enc_io_cls)
);
rvclkhdr rvclkhdr ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_io_clk),
.io_en(rvclkhdr_io_en)
);
rvclkhdr rvclkhdr_1 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_1_io_clk),
.io_en(rvclkhdr_1_io_en)
);
rvclkhdr rvclkhdr_2 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_2_io_clk),
.io_en(rvclkhdr_2_io_en)
);
rvclkhdr rvclkhdr_3 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_3_io_clk),
.io_en(rvclkhdr_3_io_en)
);
rvclkhdr rvclkhdr_4 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_4_io_clk),
.io_en(rvclkhdr_4_io_en)
);
rvclkhdr rvclkhdr_5 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_5_io_clk),
.io_en(rvclkhdr_5_io_en)
);
rvclkhdr rvclkhdr_6 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_6_io_clk),
.io_en(rvclkhdr_6_io_en)
);
rvclkhdr rvclkhdr_7 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_7_io_clk),
.io_en(rvclkhdr_7_io_en)
);
rvclkhdr rvclkhdr_8 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_8_io_clk),
.io_en(rvclkhdr_8_io_en)
);
rvclkhdr rvclkhdr_9 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_9_io_clk),
.io_en(rvclkhdr_9_io_en)
);
rvclkhdr rvclkhdr_10 ( // @[lib.scala 390:23]
.io_clk(rvclkhdr_10_io_clk),
.io_en(rvclkhdr_10_io_en)
);
assign io_data_out = _T_428 | _T_427; // @[exu_div_ctl.scala 554:15]
assign io_valid_out = finish_ff & _T; // @[exu_div_ctl.scala 553:16]
assign a_enc_io_operand = {control_ff[2],a_ff}; // @[exu_div_ctl.scala 585:20]
assign b_enc_io_operand = b_ff[32:0]; // @[exu_div_ctl.scala 588:20]
assign rvclkhdr_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_io_en = _T_35 | finish_ff; // @[lib.scala 393:17]
assign rvclkhdr_1_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_1_io_en = _T_35 | finish_ff; // @[lib.scala 393:17]
assign rvclkhdr_2_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_2_io_en = _T_35 | finish_ff; // @[lib.scala 393:17]
assign rvclkhdr_3_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_3_io_en = _T_35 | finish_ff; // @[lib.scala 393:17]
assign rvclkhdr_4_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_4_io_en = _T_35 | finish_ff; // @[lib.scala 393:17]
assign rvclkhdr_5_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_5_io_en = _T_35 | finish_ff; // @[lib.scala 393:17]
assign rvclkhdr_6_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_6_io_en = _T_35 | finish_ff; // @[lib.scala 393:17]
assign rvclkhdr_7_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_7_io_en = io_valid_in | running_state; // @[lib.scala 393:17]
assign rvclkhdr_8_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_8_io_en = io_valid_in | b_twos_comp; // @[lib.scala 393:17]
assign rvclkhdr_9_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_9_io_en = _T_33 | running_state; // @[lib.scala 393:17]
assign rvclkhdr_10_io_clk = clock; // @[lib.scala 392:18]
assign rvclkhdr_10_io_en = _T_33 | running_state; // @[lib.scala 393:17]
`ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_INVALID_ASSIGN
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif
`ifndef RANDOM
`define RANDOM $random
`endif
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
`endif
`ifndef SYNTHESIS
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif
initial begin
`ifdef RANDOMIZE
`ifdef INIT_RANDOM
`INIT_RANDOM
`endif
`ifndef VERILATOR
`ifdef RANDOMIZE_DELAY
#`RANDOMIZE_DELAY begin end
`else
#0.002 begin end
`endif
`endif
`ifdef RANDOMIZE_REG_INIT
_RAND_0 = {1{`RANDOM}};
control_ff = _RAND_0[2:0];
_RAND_1 = {2{`RANDOM}};
b_ff1 = _RAND_1[32:0];
_RAND_2 = {1{`RANDOM}};
valid_ff = _RAND_2[0:0];
_RAND_3 = {1{`RANDOM}};
a_ff = _RAND_3[31:0];
_RAND_4 = {1{`RANDOM}};
count_ff = _RAND_4[6:0];
_RAND_5 = {1{`RANDOM}};
shortq_enable_ff = _RAND_5[0:0];
_RAND_6 = {1{`RANDOM}};
finish_ff = _RAND_6[0:0];
_RAND_7 = {1{`RANDOM}};
shortq_shift_ff = _RAND_7[3:0];
_RAND_8 = {1{`RANDOM}};
by_zero_case_ff = _RAND_8[0:0];
_RAND_9 = {1{`RANDOM}};
r_ff = _RAND_9[31:0];
_RAND_10 = {1{`RANDOM}};
q_ff = _RAND_10[31:0];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
control_ff = 3'h0;
end
if (reset) begin
b_ff1 = 33'h0;
end
if (reset) begin
valid_ff = 1'h0;
end
if (reset) begin
a_ff = 32'h0;
end
if (reset) begin
count_ff = 7'h0;
end
if (reset) begin
shortq_enable_ff = 1'h0;
end
if (reset) begin
finish_ff = 1'h0;
end
if (reset) begin
shortq_shift_ff = 4'h0;
end
if (reset) begin
by_zero_case_ff = 1'h0;
end
if (reset) begin
r_ff = 32'h0;
end
if (reset) begin
q_ff = 32'h0;
end
`endif // RANDOMIZE
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif
`endif // SYNTHESIS
always @(posedge clock or posedge reset) begin
if (reset) begin
control_ff <= 3'h0;
end else if (misc_enable) begin
control_ff <= control_in;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
b_ff1 <= 33'h0;
end else if (b_enable) begin
b_ff1 <= b_in;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
valid_ff <= 1'h0;
end else if (misc_enable) begin
valid_ff <= valid_ff_in;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
a_ff <= 32'h0;
end else if (a_enable) begin
a_ff <= a_in;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
count_ff <= 7'h0;
end else if (misc_enable) begin
count_ff <= count_in;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
shortq_enable_ff <= 1'h0;
end else if (misc_enable) begin
shortq_enable_ff <= shortq_enable;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
finish_ff <= 1'h0;
end else if (misc_enable) begin
finish_ff <= finish;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
shortq_shift_ff <= 4'h0;
end else if (misc_enable) begin
shortq_shift_ff <= shortq_shift[4:1];
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
by_zero_case_ff <= 1'h0;
end else if (misc_enable) begin
by_zero_case_ff <= by_zero_case;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
r_ff <= 32'h0;
end else if (rq_enable) begin
r_ff <= r_in;
end
end
always @(posedge clock or posedge reset) begin
if (reset) begin
q_ff <= 32'h0;
end else if (rq_enable) begin
q_ff <= q_in;
end
end
endmodule

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sbt.internal.DslEntry

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@ -1,3 +1,3 @@
[debug] "not up to date. inChanged = true, force = false [debug] "not up to date. inChanged = false, force = false
[debug] Updating ProjectRef(uri("file:/home/laraibkhan/Desktop/SweRV-Chislified/project/"), "swerv-chislified-build")... [debug] Updating ProjectRef(uri("file:/home/laraibkhan/Desktop/SweRV-Chislified/project/"), "swerv-chislified-build")...
[debug] Done updating ProjectRef(uri("file:/home/laraibkhan/Desktop/SweRV-Chislified/project/"), "swerv-chislified-build") [debug] Done updating ProjectRef(uri("file:/home/laraibkhan/Desktop/SweRV-Chislified/project/"), "swerv-chislified-build")

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[debug] Full compilation, no sources in previous analysis. [debug] Full compilation, no sources in previous analysis.

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[debug] Copy resource mappings: [debug] Copy resource mappings: 
[debug] [debug]  

553
src/main/scala/exu/exu_div_ctl.scala
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@ -1,6 +1,6 @@
package exu package exu
import chisel3._ import chisel3.{util, _}
import chisel3.experimental.chiselName import chisel3.experimental.chiselName
import chisel3.util._ import chisel3.util._
import include._ import include._
@ -8,14 +8,91 @@ import lib._
@chiselName @chiselName
class exu_div_ctl extends Module with RequireAsyncReset with lib { class exu_div_ctl extends Module with RequireAsyncReset with lib {
val io = IO(new Bundle{ val io = IO(new Bundle {
val scan_mode = Input(Bool()) val scan_mode = Input(Bool())
val dividend = Input(UInt(32.W)) val dividend = Input(UInt(32.W))
val divisor = Input(UInt(32.W)) val divisor = Input(UInt(32.W))
val exu_div_result = Output(UInt(32.W)) val exu_div_result = Output(UInt(32.W))
val exu_div_wren = Output(UInt(1.W)) val exu_div_wren = Output(UInt(1.W))
val dec_div = new dec_div() val dec_div = new dec_div()
}) })
val out_raw =WireInit(0.U(32.W))
io.exu_div_result := Fill(32,io.exu_div_wren) & out_raw
if(!DIV_NEW) {
val divider_old = Module(new exu_div_existing_1bit_cheapshortq())
divider_old.io.scan_mode := io.scan_mode
divider_old.io.cancel := io.dec_div.dec_div_cancel
divider_old.io.valid_in := io.dec_div.div_p.valid
divider_old.io.signed_in := ~io.dec_div.div_p.bits.unsign
divider_old.io.rem_in := io.dec_div.div_p.bits.rem
divider_old.io.dividend_in := io.dividend
divider_old.io.divisor_in := io.divisor
out_raw := divider_old.io.data_out
io.exu_div_wren := divider_old.io.valid_out
}
if(DIV_NEW & DIV_BIT==1) {
val divider_new1 = Module(new exu_div_new_1bit_fullshortq())
divider_new1.io.scan_mode := io.scan_mode
divider_new1.io.cancel := io.dec_div.dec_div_cancel
divider_new1.io.valid_in := io.dec_div.div_p.valid
divider_new1.io.signed_in := ~io.dec_div.div_p.bits.unsign
divider_new1.io.rem_in := io.dec_div.div_p.bits.rem
divider_new1.io.dividend_in := io.dividend
divider_new1.io.divisor_in := io.divisor
out_raw := divider_new1.io.data_out
io.exu_div_wren := divider_new1.io.valid_out
}
if(DIV_NEW & DIV_BIT==2) {
val divider_new2 = Module(new exu_div_new_2bit_fullshortq())
divider_new2.io.scan_mode := io.scan_mode
divider_new2.io.cancel := io.dec_div.dec_div_cancel
divider_new2.io.valid_in := io.dec_div.div_p.valid
divider_new2.io.signed_in := ~io.dec_div.div_p.bits.unsign
divider_new2.io.rem_in := io.dec_div.div_p.bits.rem
divider_new2.io.dividend_in := io.dividend
divider_new2.io.divisor_in := io.divisor
out_raw := divider_new2.io.data_out
io.exu_div_wren := divider_new2.io.valid_out
}
if(DIV_NEW & DIV_BIT==3) {
val divider_new3 = Module(new exu_div_new_3bit_fullshortq())
divider_new3.io.scan_mode := io.scan_mode
divider_new3.io.cancel := io.dec_div.dec_div_cancel
divider_new3.io.valid_in := io.dec_div.div_p.valid
divider_new3.io.signed_in := ~io.dec_div.div_p.bits.unsign
divider_new3.io.rem_in := io.dec_div.div_p.bits.rem
divider_new3.io.dividend_in := io.dividend
divider_new3.io.divisor_in := io.divisor
out_raw := divider_new3.io.data_out
io.exu_div_wren := divider_new3.io.valid_out
}
if(DIV_NEW & DIV_BIT==4) {
val divider_new4 = Module(new exu_div_new_4bit_fullshortq())
divider_new4.io.scan_mode := io.scan_mode
divider_new4.io.cancel := io.dec_div.dec_div_cancel
divider_new4.io.valid_in := io.dec_div.div_p.valid
divider_new4.io.signed_in := ~io.dec_div.div_p.bits.unsign
divider_new4.io.rem_in := io.dec_div.div_p.bits.rem
divider_new4.io.dividend_in := io.dividend
divider_new4.io.divisor_in := io.divisor
out_raw := divider_new4.io.data_out
io.exu_div_wren := divider_new4.io.valid_out
}
}
////////////////////////////////////////// OLD DIVIDER /////////////////////////////////////
class exu_div_existing_1bit_cheapshortq extends Module with RequireAsyncReset with lib {
val io = IO(new Bundle{
val scan_mode = Input(Bool())
val cancel = Input(Bool())
val valid_in = Input(Bool())
val signed_in = Input(Bool())
val rem_in = Input(Bool())
val dividend_in = Input(UInt(32.W))
val divisor_in = Input(UInt(32.W))
val data_out = Output(UInt(32.W))
val valid_out = Output(UInt(1.W))
})
val run_state = WireInit(0.U(1.W)) val run_state = WireInit(0.U(1.W))
val count = WireInit(0.U(6.W)) val count = WireInit(0.U(6.W))
val m_ff = WireInit(0.U(33.W)) val m_ff = WireInit(0.U(33.W))
@ -33,7 +110,7 @@ class exu_div_ctl extends Module with RequireAsyncReset with lib {
val rem_ff = WireInit(0.U(1.W)) val rem_ff = WireInit(0.U(1.W))
val add = WireInit(0.U(1.W)) val add = WireInit(0.U(1.W))
val a_eff = WireInit(0.U(33.W)) val a_eff = WireInit(0.U(33.W))
val a_eff_shift = WireInit(0.U(56.W)) val a_eff_shift = WireInit(0.U(65.W))
val rem_correct = WireInit(0.U(1.W)) val rem_correct = WireInit(0.U(1.W))
val valid_ff_x = WireInit(0.U(1.W)) val valid_ff_x = WireInit(0.U(1.W))
val finish_ff = WireInit(0.U(1.W)) val finish_ff = WireInit(0.U(1.W))
@ -43,7 +120,8 @@ class exu_div_ctl extends Module with RequireAsyncReset with lib {
val count_in = WireInit(0.U(6.W)) val count_in = WireInit(0.U(6.W))
val dividend_eff = WireInit(0.U(32.W)) val dividend_eff = WireInit(0.U(32.W))
val a_shift = WireInit(0.U(33.W)) val a_shift = WireInit(0.U(33.W))
val valid_x = valid_ff_x & !io.dec_div.dec_div_cancel val shortq = WireInit(0.U(6.W))
val valid_x = valid_ff_x & !io.cancel
// START - short circuit logic for small numbers {{ // START - short circuit logic for small numbers {{
// small number divides - any 4b / 4b is done in 1 cycle (divisor != 0) // small number divides - any 4b / 4b is done in 1 cycle (divisor != 0)
@ -53,9 +131,9 @@ class exu_div_ctl extends Module with RequireAsyncReset with lib {
((q_ff(31,0) === 0.U) & (m_ff(31,0) =/= 0.U) & !rem_ff & valid_x) ((q_ff(31,0) === 0.U) & (m_ff(31,0) =/= 0.U) & !rem_ff & valid_x)
def pat(x : List[Int], y : List[Int]) = { def pat(x : List[Int], y : List[Int]) = {
val pat1 = (0 until x.size).map(i=> if(x(i)>=0) q_ff(x(i)) else !q_ff(x(i).abs)).reduce(_&_) val pat_a = (0 until x.size).map(i=> if(x(i)>=0) q_ff(x(i)) else !q_ff(x(i).abs)).reduce(_&_)
val pat2 = (0 until y.size).map(i=> if(y(i)>=0) m_ff(y(i)) else !m_ff(y(i).abs)).reduce(_&_) val pat_b = (0 until y.size).map(i=> if(y(i)>=0) m_ff(y(i)) else !m_ff(y(i).abs)).reduce(_&_)
pat1 & pat2 pat_a & pat_b
} }
val smallnum = Cat( val smallnum = Cat(
@ -87,7 +165,7 @@ class exu_div_ctl extends Module with RequireAsyncReset with lib {
short_dividend := Cat (sign_ff & q_ff(31),q_ff(31,0)) short_dividend := Cat (sign_ff & q_ff(31),q_ff(31,0))
val a_cls = Cat( val a_cls = Cat(0.U(2.W),
Mux1H(Seq ( Mux1H(Seq (
!short_dividend(32).asBool -> (short_dividend(31,24) =/= Fill(8,0.U)), !short_dividend(32).asBool -> (short_dividend(31,24) =/= Fill(8,0.U)),
short_dividend(32).asBool -> (short_dividend(31,23) =/= Fill(9,1.U)) short_dividend(32).asBool -> (short_dividend(31,23) =/= Fill(9,1.U))
@ -101,7 +179,7 @@ class exu_div_ctl extends Module with RequireAsyncReset with lib {
short_dividend(32).asBool -> (short_dividend(14,7) =/= Fill(8,1.U)) short_dividend(32).asBool -> (short_dividend(14,7) =/= Fill(8,1.U))
)) ))
) )
val b_cls = Cat( val b_cls = Cat(0.U(2.W),
Mux1H(Seq ( Mux1H(Seq (
!m_ff(32).asBool -> (m_ff(31,24) =/= Fill(8,0.U)), !m_ff(32).asBool -> (m_ff(31,24) =/= Fill(8,0.U)),
m_ff(32).asBool -> (m_ff(31,24) =/= Fill(8,1.U)) m_ff(32).asBool -> (m_ff(31,24) =/= Fill(8,1.U))
@ -137,43 +215,37 @@ class exu_div_ctl extends Module with RequireAsyncReset with lib {
) )
val shortq_enable = valid_ff_x & (m_ff(31,0) =/= 0.U(32.W)) & (shortq_raw =/= 0.U(4.W)) val shortq_enable = valid_ff_x & (m_ff(31,0) =/= 0.U(32.W)) & (shortq_raw =/= 0.U(4.W))
val shortq_shift = Fill(4,shortq_enable) & shortq_raw val shortq_shift = Cat(0.U(2.W),Fill(4,shortq_enable) & shortq_raw)
val shortq_shift_ff = Cat(0.U(1.W),Mux1H(Seq (
val shortq_shift_ff = Mux1H(Seq (
shortq_shift_xx(3).asBool -> "b11111".U, shortq_shift_xx(3).asBool -> "b11111".U,
shortq_shift_xx(2).asBool -> "b11000".U, shortq_shift_xx(2).asBool -> "b11000".U,
shortq_shift_xx(1).asBool -> "b10000".U, shortq_shift_xx(1).asBool -> "b10000".U,
shortq_shift_xx(0).asBool -> "b01000".U shortq_shift_xx(0).asBool -> "b01000".U
)) )))
// *** End Short *** }} // *** End Short *** }}
val finish = smallnum_case | Mux(!rem_ff ,count === 32.U(6.W) ,count === 33.U(6.W)) val finish = smallnum_case | Mux(!rem_ff ,count === 32.U(6.W) ,count === 33.U(6.W))
val div_clken = io.dec_div.div_p.valid | run_state | finish | finish_ff val div_clken = io.valid_in | run_state | finish | finish_ff
val run_in = (io.dec_div.div_p.valid | run_state) & !finish & !io.dec_div.dec_div_cancel val run_in = (io.valid_in | run_state) & !finish & !io.cancel
count_in := Fill(6,(run_state & !finish & !io.dec_div.dec_div_cancel & !shortq_enable)) & (count + Cat(0.U,shortq_shift_ff) + (1.U)(6.W)) count_in := Fill(6,(run_state & !finish & !io.cancel & !shortq_enable)) & (count + Cat(0.U,shortq_shift_ff(4,0)) + (1.U)(6.W))
//io.test := count_in io.valid_out := finish_ff & !io.cancel
val sign_eff = io.signed_in & (io.divisor_in =/= 0.U(32.W))
io.exu_div_wren := finish_ff & !io.dec_div.dec_div_cancel
val sign_eff = !io.dec_div.div_p.bits.unsign & (io.divisor =/= 0.U(32.W))
q_in := Mux1H(Seq( q_in := Mux1H(Seq(
(!run_state).asBool -> Cat(0.U(1.W),io.dividend) , (!run_state).asBool -> Cat(0.U(1.W),io.dividend_in) ,
(run_state & (valid_ff_x | shortq_enable_ff)).asBool -> (Cat(dividend_eff(31,0),!a_in(32)) << shortq_shift_ff) , (run_state & (valid_ff_x | shortq_enable_ff)).asBool -> (Cat(dividend_eff(31,0),!a_in(32)) << shortq_shift_ff(4,0)) ,
(run_state & !(valid_ff_x | shortq_enable_ff)).asBool -> Cat(q_ff(31,0),!a_in(32)) (run_state & !(valid_ff_x | shortq_enable_ff)).asBool -> Cat(q_ff(31,0),!a_in(32))
)) ))
val qff_enable = io.dec_div.div_p.valid | (run_state & !shortq_enable) val qff_enable = io.valid_in | (run_state & !shortq_enable)
dividend_eff := Mux((sign_ff & dividend_neg_ff).asBool, rvtwoscomp(q_ff(31,0)),q_ff(31,0)) dividend_eff := Mux((sign_ff & dividend_neg_ff).asBool, rvtwoscomp(q_ff(31,0)),q_ff(31,0))
m_eff := Mux(add.asBool , m_ff, ~m_ff ) m_eff := Mux(add.asBool , m_ff, ~m_ff )
a_eff_shift := Cat(0.U(24.W), dividend_eff) << shortq_shift_ff a_eff_shift := Cat(0.U(33.W), dividend_eff) << shortq_shift_ff(4,0)
a_eff := Mux1H(Seq( a_eff := Mux1H(Seq(
rem_correct.asBool -> a_ff , rem_correct.asBool -> a_ff ,
(!rem_correct & !shortq_enable_ff).asBool -> Cat(a_ff(31,0), q_ff(32)) , (!rem_correct & !shortq_enable_ff).asBool -> Cat(a_ff(31,0), q_ff(32)) ,
(!rem_correct & shortq_enable_ff).asBool -> Cat(0.U(9.W),a_eff_shift(55,32)) (!rem_correct & shortq_enable_ff).asBool -> a_eff_shift(64,32)
)) ))
val aff_enable = io.dec_div.div_p.valid | (run_state & !shortq_enable & (count =/= 33.U(6.W))) | rem_correct val aff_enable = io.valid_in | (run_state & !shortq_enable & (count =/= 33.U(6.W))) | rem_correct
a_shift := Fill(33,run_state) & a_eff a_shift := Fill(33,run_state) & a_eff
a_in := Fill(33,run_state) & (a_shift + m_eff + Cat(0.U(32.W),!add)) a_in := Fill(33,run_state) & (a_shift + m_eff + Cat(0.U(32.W),!add))
val m_already_comp = divisor_neg_ff & sign_ff val m_already_comp = divisor_neg_ff & sign_ff
@ -183,29 +255,406 @@ class exu_div_ctl extends Module with RequireAsyncReset with lib {
val q_ff_eff = Mux((sign_ff & (dividend_neg_ff ^ divisor_neg_ff)).asBool,rvtwoscomp(q_ff(31,0)), q_ff(31,0)) val q_ff_eff = Mux((sign_ff & (dividend_neg_ff ^ divisor_neg_ff)).asBool,rvtwoscomp(q_ff(31,0)), q_ff(31,0))
val a_ff_eff = Mux((sign_ff & dividend_neg_ff ).asBool, rvtwoscomp(a_ff(31,0)), a_ff(31,0)) val a_ff_eff = Mux((sign_ff & dividend_neg_ff ).asBool, rvtwoscomp(a_ff(31,0)), a_ff(31,0))
io.exu_div_result := Mux1H(Seq( io.data_out := Mux1H(Seq(
smallnum_case_ff.asBool -> Cat(0.U(28.W), smallnum_ff), smallnum_case_ff.asBool -> Cat(0.U(28.W), smallnum_ff),
rem_ff.asBool -> a_ff_eff , rem_ff.asBool -> a_ff_eff ,
(!smallnum_case_ff & !rem_ff).asBool -> q_ff_eff (!smallnum_case_ff & !rem_ff).asBool -> q_ff_eff
)) ))
valid_ff_x := rvdffe(io.valid_in & !io.cancel, div_clken,clock,io.scan_mode)
finish_ff := rvdffe(finish & !io.cancel, div_clken,clock,io.scan_mode)
run_state := rvdffe(run_in,div_clken,clock,io.scan_mode)
count := rvdffe(count_in, div_clken,clock,io.scan_mode)
dividend_neg_ff := rvdffe((io.valid_in & io.dividend_in(31)) | (!io.valid_in & dividend_neg_ff), div_clken,clock,io.scan_mode)
divisor_neg_ff := rvdffe((io.valid_in & io.divisor_in(31)) | (!io.valid_in & divisor_neg_ff), div_clken,clock,io.scan_mode)
sign_ff := rvdffe((io.valid_in & sign_eff) | (!io.valid_in & sign_ff), div_clken,clock,io.scan_mode)
rem_ff := rvdffe((io.valid_in & io.rem_in) | (!io.valid_in & rem_ff), div_clken,clock,io.scan_mode)
smallnum_case_ff := rvdffe(smallnum_case, div_clken,clock,io.scan_mode)
smallnum_ff := rvdffe(smallnum, div_clken,clock,io.scan_mode)
shortq_enable_ff := rvdffe(shortq_enable, div_clken,clock,io.scan_mode)
shortq_shift_xx := rvdffe(shortq_shift, div_clken,clock,io.scan_mode)
val exu_div_cgc = rvclkhdr(clock,div_clken.asBool,io.scan_mode) q_ff := rvdffe(q_in, qff_enable,clock,io.scan_mode)
a_ff := rvdffe(a_in, aff_enable,clock,io.scan_mode)
m_ff := rvdffe(Cat(io.signed_in & io.divisor_in(31), io.divisor_in(31,0)), io.valid_in,clock,io.scan_mode)
withClock(exu_div_cgc) {
valid_ff_x := RegNext(io.dec_div.div_p.valid & !io.dec_div.dec_div_cancel, 0.U)
finish_ff := RegNext(finish & !io.dec_div.dec_div_cancel, 0.U) }
run_state := RegNext(run_in, 0.U) /////////////////////////////////////////////// 1 BIT FULL DIVIDER//////////////////////////////////
count := RegNext(count_in, 0.U) class exu_div_new_1bit_fullshortq extends Module with RequireAsyncReset with lib {
dividend_neg_ff := RegEnable(io.dividend(31), 0.U, io.dec_div.div_p.valid.asBool) val io = IO(new Bundle{
divisor_neg_ff := RegEnable(io.divisor(31), 0.U, io.dec_div.div_p.valid.asBool) val scan_mode = Input(Bool())
sign_ff := RegEnable(sign_eff, 0.U, io.dec_div.div_p.valid.asBool) val cancel = Input(Bool())
rem_ff := RegEnable(io.dec_div.div_p.bits.rem, 0.U, io.dec_div.div_p.valid.asBool) val valid_in = Input(Bool())
smallnum_case_ff := RegNext(smallnum_case, 0.U) val signed_in = Input(Bool())
smallnum_ff := RegNext(smallnum, 0.U) val rem_in = Input(Bool())
shortq_enable_ff := RegNext(shortq_enable, 0.U) val dividend_in = Input(UInt(32.W))
shortq_shift_xx := RegNext(shortq_shift, 0.U) val divisor_in = Input(UInt(32.W))
val data_out = Output(UInt(32.W))
val valid_out = Output(UInt(1.W))
})
val valid_ff = WireInit(Bool(),init=false.B)
val finish_ff = WireInit(Bool(),init=false.B)
val control_ff = WireInit(0.U(3.W))
val count_ff = WireInit(0.U(7.W))
val smallnum = WireInit(0.U(4.W))
val a_ff = WireInit(0.U(32.W))
val b_ff = WireInit(0.U(33.W))
val q_ff = WireInit(0.U(32.W))
val r_ff = WireInit(0.U(32.W))
val quotient_set = WireInit(Bool(),init=false.B)
val shortq_enable = WireInit(Bool(),init=false.B)
val shortq_enable_ff = WireInit(Bool(),init=false.B)
val by_zero_case_ff = WireInit(Bool(),init=false.B)
val adder_out = WireInit(0.U(33.W))
val ar_shifted = WireInit(0.U(64.W))
val shortq_shift_ff = WireInit(0.U(5.W))
val dividend_sign_ff = control_ff(2)
val divisor_sign_ff = control_ff(1)
val rem_ff = control_ff(0)
val by_zero_case = valid_ff & (b_ff(31,0) === 0.U)
val smallnum_case = ((a_ff(31,4) === 0.U) & (b_ff(31,4) === 0.U) & !by_zero_case & !rem_ff & valid_ff & !io.cancel) |
((a_ff(31,0) === 0.U) & !by_zero_case & !rem_ff & valid_ff & !io.cancel)
val valid_ff_in = io.valid_in & !io.cancel
val control_in = Cat((!io.valid_in & control_ff(2)) | (io.valid_in & io.signed_in & io.dividend_in(31)), (!io.valid_in & control_ff(1)) | (io.valid_in & io.signed_in & io.divisor_in(31)), (!io.valid_in & control_ff(0)) | (io.valid_in & io.rem_in))
val running_state = count_ff.orR() | shortq_enable_ff
val misc_enable = io.valid_in | valid_ff | io.cancel | running_state | finish_ff
val finish_raw = smallnum_case | by_zero_case | (count_ff === 32.U)
val finish = finish_raw & !io.cancel
val count_enable = (valid_ff | running_state) & !finish & !finish_ff & !io.cancel & !shortq_enable
val count_in = Fill(7,count_enable) & (count_ff + Cat(0.U(6.W),1.U) + Cat(0.U(2.W),shortq_shift_ff))
val a_enable = io.valid_in | running_state
val a_shift = running_state & !shortq_enable_ff
ar_shifted := Cat (Fill(32,dividend_sign_ff),a_ff) << shortq_shift_ff
val b_twos_comp = valid_ff & !(dividend_sign_ff ^ divisor_sign_ff)
val twos_comp_b_sel = valid_ff & !(dividend_sign_ff ^ divisor_sign_ff)
val twos_comp_q_sel = !valid_ff & !rem_ff & (dividend_sign_ff ^ divisor_sign_ff) & !by_zero_case_ff
val b_enable = io.valid_in | b_twos_comp
val rq_enable = io.valid_in | valid_ff | running_state
val r_sign_sel = valid_ff & dividend_sign_ff & !by_zero_case
val r_restore_sel = running_state & !quotient_set & !shortq_enable_ff
val r_adder_sel = running_state & quotient_set & !shortq_enable_ff
val twos_comp_in = Mux1H(Seq (
twos_comp_q_sel -> q_ff,
twos_comp_b_sel -> b_ff(31,0)
))
val twos_comp_out = rvtwoscomp(twos_comp_in)
val a_in = Mux1H(Seq (
(!a_shift & !shortq_enable_ff).asBool -> io.dividend_in,
a_shift -> Cat(a_ff(30,0),0.U),
shortq_enable_ff -> ar_shifted(31,0)
))
val b_in = Mux1H(Seq (
!b_twos_comp -> Cat(io.signed_in & io.divisor_in(31),io.divisor_in(31,0)),
b_twos_comp -> Cat(!divisor_sign_ff,twos_comp_out(31,0))
))
val r_in = Mux1H (Seq(
r_sign_sel -> "hffffffff".U(32.W),
r_restore_sel -> Cat(r_ff(30,0),a_ff(31)),
r_adder_sel -> adder_out(31,0),
shortq_enable_ff -> ar_shifted(63,32),
by_zero_case -> a_ff
))
val q_in = Mux1H (Seq(
!valid_ff -> Cat(q_ff(30,0),quotient_set),
smallnum_case -> Cat(0.U(28.W),smallnum),
by_zero_case -> Fill(32,1.U)
))
adder_out := Cat(r_ff,a_ff(31)) + b_ff
quotient_set := (!adder_out(32) ^ dividend_sign_ff) | ((a_ff(30,0) === 0.U) & (adder_out === 0.U))
io.valid_out := finish_ff & !io.cancel
io.data_out := Mux1H(Seq(
(!rem_ff & !twos_comp_q_sel).asBool() -> q_ff,
rem_ff -> r_ff,
twos_comp_q_sel -> twos_comp_out
))
def pat1(x : List[Int], y : List[Int]) = {
val pat_a = (0 until x.size).map(i=> if(x(i)>=0) a_ff(x(i)) else !a_ff(x(i).abs)).reduce(_&_)
val pat_b = (0 until y.size).map(i=> if(y(i)>=0) b_ff(y(i)) else !b_ff(y(i).abs)).reduce(_&_)
pat_a & pat_b
} }
q_ff := rvdffe(q_in, qff_enable.asBool,clock,io.scan_mode)
a_ff := rvdffe(a_in, aff_enable.asBool,clock,io.scan_mode) smallnum := Cat(
m_ff := rvdffe(Cat(!io.dec_div.div_p.bits.unsign & io.divisor(31), io.divisor), io.dec_div.div_p.valid.asBool,clock,io.scan_mode) pat1(List(3),List(-3, -2, -1)),
pat1(List(3),List(-3, -2))& !b_ff(0) | pat1(List(2),List(-3, -2, -1)) | pat1(List(3, 2),List(-3, -2)),
pat1(List(2),List(-3, -2))& !b_ff(0) | pat1(List(1),List(-3, -2, -1)) | pat1(List(3),List(-3, -1))& !b_ff(0) |
pat1(List(3, -2),List(-3, -2, 1, 0)) | pat1(List(-3, 2, 1),List(-3, -2)) | pat1(List(3, 2),List(-3))& !b_ff(0) |
pat1(List(3, 2),List(-3, 2, -1)) | pat1(List(3, 1),List(-3,-1)) | pat1(List(3, 2, 1),List(-3, 2)),
pat1(List(2, 1, 0),List(-3, -1)) | pat1(List(3, -2, 0),List(-3, 1, 0)) | pat1(List(2),List(-3, -1))& !b_ff(0) |
pat1(List(1),List(-3, -2))& !b_ff(0) | pat1(List(0),List(-3, -2, -1)) | pat1(List(-3, 2, -1),List(-3, -2, 1, 0)) |
pat1(List(-3, 2, 1),List(-3))& !b_ff(0) | pat1(List(3),List(-2, -1)) & !b_ff(0) | pat1(List(3, -2),List(-3, 2, 1)) |
pat1(List(-3, 2, 1),List(-3, 2, -1)) | pat1(List(-3, 2, 0),List(-3, -1)) | pat1(List(3, -2, -1),List(-3, 2, 0)) |
pat1(List(-2, 1, 0),List(-3, -2)) | pat1(List(3, 2),List(-1)) & !b_ff(0) | pat1(List(-3, 2, 1, 0),List(-3, 2)) |
pat1(List(3, 2),List(3, -2)) | pat1(List(3, 1),List(3,-2,-1)) | pat1(List(3, 0),List(-2, -1)) |
pat1(List(3, -1),List(-3, 2, 1, 0)) | pat1(List(3, 2, 1),List(3)) & !b_ff(0) | pat1(List(3, 2, 1),List(3, -1)) |
pat1(List(3, 2, 0),List(3, -1)) | pat1(List(3, -2, 1),List(-3, 1)) | pat1(List(3, 1, 0),List(-2)) |
pat1(List(3, 2, 1, 0),List(3)) |pat1(List(3, 1),List(-2)) & !b_ff(0))
val shortq_dividend = Cat(dividend_sign_ff,a_ff)
val a_enc = Module(new exu_div_cls)
a_enc.io.operand := shortq_dividend
val dw_a_enc1 = a_enc.io.cls
val b_enc = Module(new exu_div_cls)
b_enc.io.operand := b_ff
val dw_b_enc1 = b_enc.io.cls
val dw_a_enc = Cat (0.U, dw_a_enc1)
val dw_b_enc = Cat (0.U, dw_b_enc1)
val dw_shortq_raw = Cat(0.U,dw_b_enc) - Cat(0.U,dw_a_enc) + 1.U(7.W)
val shortq = Mux(dw_shortq_raw(6).asBool(),0.U,dw_shortq_raw(5,0))
shortq_enable := valid_ff & !shortq(5) & !(shortq(4,1) === "b1111".U) & !io.cancel
val shortq_shift = Mux(!shortq_enable,0.U,("b11111".U - shortq(4,0)))
valid_ff := rvdffe(valid_ff_in, misc_enable,clock,io.scan_mode)
control_ff := rvdffe(control_in, misc_enable,clock,io.scan_mode)
by_zero_case_ff := rvdffe(by_zero_case,misc_enable,clock,io.scan_mode)
shortq_enable_ff := rvdffe(shortq_enable, misc_enable,clock,io.scan_mode)
shortq_shift_ff := rvdffe(shortq_shift, misc_enable,clock,io.scan_mode)
finish_ff := rvdffe(finish, misc_enable,clock,io.scan_mode)
count_ff := rvdffe(count_in, misc_enable,clock,io.scan_mode)
a_ff := rvdffe(a_in, a_enable,clock,io.scan_mode)
b_ff := rvdffe(b_in, b_enable,clock,io.scan_mode)
r_ff := rvdffe(r_in, rq_enable,clock,io.scan_mode)
q_ff := rvdffe(q_in, rq_enable,clock,io.scan_mode)
}
class exu_div_new_2bit_fullshortq extends Module with RequireAsyncReset with lib {
val io = IO(new Bundle{
val scan_mode = Input(Bool())
val cancel = Input(Bool())
val valid_in = Input(Bool())
val signed_in = Input(Bool())
val rem_in = Input(Bool())
val dividend_in = Input(UInt(32.W))
val divisor_in = Input(UInt(32.W))
val data_out = Output(UInt(32.W))
val valid_out = Output(UInt(1.W))
})
// val valid_ff_in = WireInit(Bool(),init=false.B)
val valid_ff = WireInit(Bool(),init=false.B)
// val finish_raw = WireInit(Bool(),init=false.B)
// val finish = WireInit(Bool(),init=false.B)
val finish_ff = WireInit(Bool(),init=false.B)
// val running_state = WireInit(Bool(),init=false.B)
// val misc_enable = WireInit(Bool(),init=false.B)
// val control_in = WireInit(0.U(3.W))
val control_ff = WireInit(0.U(3.W))
// val dividend_sign_ff = WireInit(Bool(),init=false.B)
// val divisor_sign_ff = WireInit(Bool(),init=false.B)
// val count_enable = WireInit(Bool(),init=false.B)
// val count_in = WireInit(0.U(7.W))
val count_ff = WireInit(0.U(7.W))
val smallnum = WireInit(0.U(4.W))
val smallnum_case = WireInit(Bool(),init=false.B)
// val a_enable = WireInit(Bool(),init=false.B)
// val a_shift = WireInit(Bool(),init=false.B)
// val b_enable = WireInit(Bool(),init=false.B)
// val b_twos_comp = WireInit(Bool(),init=false.B)
// val a_in = WireInit(0.U(32.W))
val a_ff = WireInit(0.U(32.W))
// val b_in = WireInit(0.U(33.W))
val b_ff1 = WireInit(0.U(33.W))
val b_ff = WireInit(0.U(35.W))
// val q_in = WireInit(0.U(32.W))
val q_ff = WireInit(0.U(32.W))
// val r_in = WireInit(0.U(32.W))
val r_ff = WireInit(0.U(32.W))
// val rq_enable = WireInit(Bool(),init=false.B)
// val r_sign_sel = WireInit(Bool(),init=false.B)
// val r_restore_sel = WireInit(Bool(),init=false.B)
// val r_adder1_sel = WireInit(Bool(),init=false.B)
// val r_adder2_sel = WireInit(Bool(),init=false.B)
// val r_adder3_sel = WireInit(Bool(),init=false.B)
// val twos_comp_q_sel = WireInit(Bool(),init=false.B)
// val twos_comp_b_sel = WireInit(Bool(),init=false.B)
val quotient_raw = WireInit(0.U(3.W))
val quotient_new = WireInit(0.U(2.W))
val shortq_enable = WireInit(Bool(),init=false.B)
val shortq_enable_ff = WireInit(Bool(),init=false.B)
// val by_zero_case = WireInit(Bool(),init=false.B)
val by_zero_case_ff = WireInit(Bool(),init=false.B)
// val twos_comp_in = WireInit(0.U(32.W))
// val twos_comp_out = WireInit(0.U(32.W))
// val adder1_out = WireInit(0.U(33.W))
// val adder2_out = WireInit(0.U(34.W))
// val adder3_out = WireInit(0.U(35.W))
val ar_shifted = WireInit(0.U(64.W))
// val shortq = WireInit(0.U(6.W))
// val shortq_shift = WireInit(0.U(5.W))
val shortq_shift_ff = WireInit(0.U(4.W))
// val shortq_dividend = WireInit(0.U(33.W))
val valid_ff_in = io.valid_in & !io.cancel
val control_in = Cat((!io.valid_in & control_ff(2)) | (io.valid_in & io.signed_in & io.dividend_in(31)), (!io.valid_in & control_ff(1)) | (io.valid_in & io.signed_in & io.divisor_in(31)), (!io.valid_in & control_ff(0)) | (io.valid_in & io.rem_in))
val dividend_sign_ff = control_ff(2)
val divisor_sign_ff = control_ff(1)
val rem_ff = control_ff(0)
val by_zero_case = valid_ff & (b_ff(31,0) === 0.U)
// val smallnum_case = ((a_ff(31,4) === 0.U) & (b_ff(31,4) === 0.U) & !by_zero_case & !rem_ff & valid_ff & !io.cancel) |
((a_ff(31,0) === 0.U) & !by_zero_case & !rem_ff & valid_ff & !io.cancel)
val running_state = count_ff.orR() | shortq_enable_ff
val misc_enable = io.valid_in | valid_ff | io.cancel | running_state | finish_ff
val finish_raw = smallnum_case | by_zero_case | (count_ff === 32.U)
val finish = finish_raw & !io.cancel
val count_enable = (valid_ff | running_state) & !finish & !finish_ff & !io.cancel & !shortq_enable
val count_in = Fill(7,count_enable) & (count_ff + Cat(0.U(5.W),2.U) + Cat(0.U(2.W),shortq_shift_ff,0.U))
val a_enable = io.valid_in | running_state
val a_shift = running_state & !shortq_enable_ff
ar_shifted := Cat (Fill(32,dividend_sign_ff),a_ff) << Cat(shortq_shift_ff,0.U)
val b_twos_comp = valid_ff & !(dividend_sign_ff ^ divisor_sign_ff)
val twos_comp_b_sel = valid_ff & !(dividend_sign_ff ^ divisor_sign_ff)
val twos_comp_q_sel = !valid_ff & !rem_ff & (dividend_sign_ff ^ divisor_sign_ff) & !by_zero_case_ff
val b_enable = io.valid_in | b_twos_comp
val rq_enable = io.valid_in | valid_ff | running_state
val r_sign_sel = valid_ff & dividend_sign_ff & !by_zero_case
val r_restore_sel = running_state & (quotient_new === 0.U) & !shortq_enable_ff
val r_adder1_sel = running_state & (quotient_new === 1.U) & !shortq_enable_ff
val r_adder2_sel = running_state & (quotient_new === 2.U) & !shortq_enable_ff
val r_adder3_sel = running_state & (quotient_new === 3.U) & !shortq_enable_ff
val adder1_out = Cat(r_ff(30,0),a_ff(31,30)) + b_ff(32,0)
val adder2_out = Cat(r_ff(30,0),a_ff(31,30)) + Cat(b_ff(32,0),0.U)
val adder3_out = Cat(r_ff(31),r_ff(31,0),a_ff(31,30)) + Cat(b_ff(33,0),0.U) + b_ff
quotient_raw := Cat((!adder3_out(34) ^ dividend_sign_ff) | ((a_ff(29,0) === 0.U) & (adder3_out === 0.U)),
(!adder2_out(33) ^ dividend_sign_ff) | ((a_ff(29,0) === 0.U) & (adder2_out === 0.U)),
(!adder1_out(32) ^ dividend_sign_ff) | ((a_ff(29,0) === 0.U) & (adder1_out === 0.U)))
quotient_new := Cat ((quotient_raw(2) | quotient_raw(1)) , (quotient_raw(2) |(!quotient_raw(1) & quotient_raw(0))))
val twos_comp_in = Mux1H(Seq (
twos_comp_q_sel -> q_ff,
twos_comp_b_sel -> b_ff(31,0)
))
val twos_comp_out = rvtwoscomp(twos_comp_in)
val a_in = Mux1H(Seq (
(!a_shift & !shortq_enable_ff).asBool -> io.dividend_in,
a_shift -> Cat(a_ff(29,0),0.U(2.W)),
shortq_enable_ff -> ar_shifted(31,0)
))
val b_in = Mux1H(Seq (
!b_twos_comp -> Cat(io.signed_in & io.divisor_in(31),io.divisor_in(31,0)),
b_twos_comp -> Cat(!divisor_sign_ff,twos_comp_out(31,0))
))
val r_in = Mux1H (Seq(
r_sign_sel -> "hffffffff".U(32.W),
r_restore_sel -> Cat(r_ff(29,0),a_ff(31,30)),
r_adder1_sel -> adder1_out(31,0),
r_adder2_sel -> adder2_out(31,0),
r_adder3_sel -> adder3_out(31,0),
shortq_enable_ff -> ar_shifted(63,32),
by_zero_case -> a_ff
))
val q_in = Mux1H (Seq(
!valid_ff -> Cat(q_ff(29,0),quotient_new),
smallnum_case -> Cat(0.U(28.W),smallnum),
by_zero_case -> Fill(32,1.U)
))
io.valid_out := finish_ff & !io.cancel
io.data_out := Mux1H(Seq(
(!rem_ff & !twos_comp_q_sel).asBool() -> q_ff,
rem_ff -> r_ff,
twos_comp_q_sel -> twos_comp_out
))
def pat1(x : List[Int], y : List[Int]) = {
val pat_a = (0 until x.size).map(i=> if(x(i)>=0) a_ff(x(i)) else !a_ff(x(i).abs)).reduce(_&_)
val pat_b = (0 until y.size).map(i=> if(y(i)>=0) b_ff(y(i)) else !b_ff(y(i).abs)).reduce(_&_)
pat_a & pat_b
}
smallnum := Cat(
pat1(List(3),List(-3, -2, -1)),
pat1(List(3),List(-3, -2))& !b_ff(0) | pat1(List(2),List(-3, -2, -1)) | pat1(List(3, 2),List(-3, -2)),
pat1(List(2),List(-3, -2))& !b_ff(0) | pat1(List(1),List(-3, -2, -1)) | pat1(List(3),List(-3, -1))& !b_ff(0) |
pat1(List(3, -2),List(-3, -2, 1, 0)) | pat1(List(-3, 2, 1),List(-3, -2)) | pat1(List(3, 2),List(-3))& !b_ff(0) |
pat1(List(3, 2),List(-3, 2, -1)) | pat1(List(3, 1),List(-3,-1)) | pat1(List(3, 2, 1),List(-3, 2)),
pat1(List(2, 1, 0),List(-3, -1)) | pat1(List(3, -2, 0),List(-3, 1, 0)) | pat1(List(2),List(-3, -1))& !b_ff(0) |
pat1(List(1),List(-3, -2))& !b_ff(0) | pat1(List(0),List(-3, -2, -1)) | pat1(List(-3, 2, -1),List(-3, -2, 1, 0)) |
pat1(List(-3, 2, 1),List(-3))& !b_ff(0) | pat1(List(3),List(-2, -1)) & !b_ff(0) | pat1(List(3, -2),List(-3, 2, 1)) |
pat1(List(-3, 2, 1),List(-3, 2, -1)) | pat1(List(-3, 2, 0),List(-3, -1)) | pat1(List(3, -2, -1),List(-3, 2, 0)) |
pat1(List(-2, 1, 0),List(-3, -2)) | pat1(List(3, 2),List(-1)) & !b_ff(0) | pat1(List(-3, 2, 1, 0),List(-3, 2)) |
pat1(List(3, 2),List(3, -2)) | pat1(List(3, 1),List(3,-2,-1)) | pat1(List(3, 0),List(-2, -1)) |
pat1(List(3, -1),List(-3, 2, 1, 0)) | pat1(List(3, 2, 1),List(3)) & !b_ff(0) | pat1(List(3, 2, 1),List(3, -1)) |
pat1(List(3, 2, 0),List(3, -1)) | pat1(List(3, -2, 1),List(-3, 1)) | pat1(List(3, 1, 0),List(-2)) |
pat1(List(3, 2, 1, 0),List(3)) |pat1(List(3, 1),List(-2)) & !b_ff(0))
val shortq_dividend = Cat(dividend_sign_ff,a_ff)
val a_enc = Module(new exu_div_cls)
a_enc.io.operand := shortq_dividend
val dw_a_enc1 = a_enc.io.cls
val b_enc = Module(new exu_div_cls)
b_enc.io.operand := b_ff(32,0)
val dw_b_enc1 = b_enc.io.cls
val dw_a_enc = Cat (0.U, dw_a_enc1)
val dw_b_enc = Cat (0.U, dw_b_enc1)
val dw_shortq_raw = Cat(0.U,dw_b_enc) - Cat(0.U,dw_a_enc) + 1.U(7.W)
val shortq = Mux(dw_shortq_raw(6).asBool(),0.U,dw_shortq_raw(5,0))
shortq_enable := valid_ff & !shortq(5) & !(shortq(4,1) === "b1111".U) & !io.cancel
val shortq_shift = Mux(!shortq_enable,0.U,("b11111".U - shortq(4,0)))
b_ff := Cat(b_ff1(32),b_ff1(32),b_ff1)
valid_ff := rvdffe(valid_ff_in, misc_enable,clock,io.scan_mode)
control_ff := rvdffe(control_in, misc_enable,clock,io.scan_mode)
by_zero_case_ff := rvdffe(by_zero_case,misc_enable,clock,io.scan_mode)
shortq_enable_ff := rvdffe(shortq_enable, misc_enable,clock,io.scan_mode)
shortq_shift_ff := rvdffe(shortq_shift(4,1), misc_enable,clock,io.scan_mode)
finish_ff := rvdffe(finish, misc_enable,clock,io.scan_mode)
count_ff := rvdffe(count_in, misc_enable,clock,io.scan_mode)
a_ff := rvdffe(a_in, a_enable,clock,io.scan_mode)
b_ff1 := rvdffe(b_in(32,0), b_enable,clock,io.scan_mode)
r_ff := rvdffe(r_in, rq_enable,clock,io.scan_mode)
q_ff := rvdffe(q_in, rq_enable,clock,io.scan_mode)
}
object div_main3 extends App {
println((new chisel3.stage.ChiselStage).emitVerilog(new exu_div_new_2bit_fullshortq()))
}
class exu_div_new_3bit_fullshortq extends Module with RequireAsyncReset with lib {
val io = IO(new Bundle{
val scan_mode = Input(Bool())
val cancel = Input(Bool())
val valid_in = Input(Bool())
val signed_in = Input(Bool())
val rem_in = Input(Bool())
val dividend_in = Input(UInt(32.W))
val divisor_in = Input(UInt(32.W))
val data_out = Output(UInt(32.W))
val valid_out = Output(UInt(1.W))
})
io.data_out :=0.U
io.valid_out :=0.U
}
class exu_div_new_4bit_fullshortq extends Module with RequireAsyncReset with lib {
val io = IO(new Bundle{
val scan_mode = Input(Bool())
val cancel = Input(Bool())
val valid_in = Input(Bool())
val signed_in = Input(Bool())
val rem_in = Input(Bool())
val dividend_in = Input(UInt(32.W))
val divisor_in = Input(UInt(32.W))
val data_out = Output(UInt(32.W))
val valid_out = Output(UInt(1.W))
})
io.data_out :=5.U
io.valid_out :=1.U
}
class exu_div_cls extends Module{
val io= IO(new Bundle{
val operand = Input(UInt(33.W))
val cls = Output(UInt(5.W))
})
val cls_zeros = WireInit(0.U(5.W))
val cls_ones = WireInit(0.U(5.W))
cls_zeros := Mux1H((0 until 32).map(i=> (io.operand(31,31-i)===1.U)->i.U))
when(io.operand(31,0) === "hffffffff".U) { cls_ones := 31.U}
.otherwise{cls_ones := Mux1H((1 until 32).map(i=> (io.operand(31,31-i) === Cat(Fill(i,1.U),0.U)).asBool -> (i-1).U ))}
io.cls := Mux(io.operand(32),cls_ones,cls_zeros)
} }

3
src/main/scala/lib/param.scala
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@ -156,4 +156,7 @@ trait param {
val SB_BUS_TAG = 0x1 val SB_BUS_TAG = 0x1
val TIMER_LEGAL_EN = 0x1 val TIMER_LEGAL_EN = 0x1
val RV_FPGA_OPTIMIZE = 0x1 val RV_FPGA_OPTIMIZE = 0x1
val DIV_NEW = 0x1
val DIV_BIT = 0x4
} }

8
src/main/scala/lsu/lsu_bus_buffer.scala
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@ -445,11 +445,13 @@ class lsu_bus_buffer extends Module with RequireAsyncReset with lib {
buf_data_en(i) := buf_state_en(i) buf_data_en(i) := buf_state_en(i)
buf_data_in(i) := Mux((ibuf_drain_vld & (i === ibuf_tag)).asBool(), ibuf_data_out(31, 0), store_data_lo_r(31, 0)) buf_data_in(i) := Mux((ibuf_drain_vld & (i === ibuf_tag)).asBool(), ibuf_data_out(31, 0), store_data_lo_r(31, 0))
buf_cmd_state_bus_en(i) := 0.U buf_cmd_state_bus_en(i) := 0.U
buf_rst(i) := io.dec_tlu_force_halt
} }
is(wait_C) { is(wait_C) {
buf_nxtstate(i) := Mux(io.dec_tlu_force_halt.asBool(), idle_C, cmd_C) buf_nxtstate(i) := Mux(io.dec_tlu_force_halt.asBool(), idle_C, cmd_C)
buf_state_en(i) := io.lsu_bus_clk_en | io.dec_tlu_force_halt buf_state_en(i) := io.lsu_bus_clk_en | io.dec_tlu_force_halt
buf_cmd_state_bus_en(i) := 0.U buf_cmd_state_bus_en(i) := 0.U
buf_rst(i) := io.dec_tlu_force_halt
} }
is(cmd_C) { is(cmd_C) {
buf_nxtstate(i) := Mux(io.dec_tlu_force_halt.asBool(), idle_C, Mux((obuf_nosend & bus_rsp_read & (bus_rsp_read_tag === obuf_rdrsp_tag)), done_wait_C, resp_C)) buf_nxtstate(i) := Mux(io.dec_tlu_force_halt.asBool(), idle_C, Mux((obuf_nosend & bus_rsp_read & (bus_rsp_read_tag === obuf_rdrsp_tag)), done_wait_C, resp_C))
@ -462,7 +464,8 @@ class lsu_bus_buffer extends Module with RequireAsyncReset with lib {
buf_data_en(i) := buf_state_bus_en(i) & io.lsu_bus_clk_en & obuf_nosend & bus_rsp_read buf_data_en(i) := buf_state_bus_en(i) & io.lsu_bus_clk_en & obuf_nosend & bus_rsp_read
buf_error_en(i) := buf_state_bus_en(i) & io.lsu_bus_clk_en & obuf_nosend & bus_rsp_read_error buf_error_en(i) := buf_state_bus_en(i) & io.lsu_bus_clk_en & obuf_nosend & bus_rsp_read_error
buf_data_in(i) := Mux(buf_error_en(i), bus_rsp_rdata(31, 0), Mux(buf_addr(i)(2), bus_rsp_rdata(63, 32), bus_rsp_rdata(31, 0))) buf_data_in(i) := Mux(buf_error_en(i), bus_rsp_rdata(31, 0), Mux(buf_addr(i)(2), bus_rsp_rdata(63, 32), bus_rsp_rdata(31, 0)))
} buf_rst(i) := io.dec_tlu_force_halt
}
is(resp_C) { is(resp_C) {
buf_nxtstate(i) := Mux((io.dec_tlu_force_halt | (buf_write(i) & !bus_rsp_write_error)).asBool(), idle_C, buf_nxtstate(i) := Mux((io.dec_tlu_force_halt | (buf_write(i) & !bus_rsp_write_error)).asBool(), idle_C,
Mux((buf_dual(i) & !buf_samedw(i) & !buf_write(i) & (buf_state(buf_dualtag(i)) =/= done_partial_C)), done_partial_C, Mux((buf_dual(i) & !buf_samedw(i) & !buf_write(i) & (buf_state(buf_dualtag(i)) =/= done_partial_C)), done_partial_C,
@ -479,6 +482,7 @@ class lsu_bus_buffer extends Module with RequireAsyncReset with lib {
(bus_rsp_write_error & (bus_rsp_write_tag === i.asUInt(LSU_BUS_TAG.W)))) (bus_rsp_write_error & (bus_rsp_write_tag === i.asUInt(LSU_BUS_TAG.W))))
buf_data_in(i) := Mux((buf_state_en(i) & !buf_error_en(i)), Mux(buf_addr(i)(2), bus_rsp_rdata(63, 32), bus_rsp_rdata(31, 0)), bus_rsp_rdata(31, 0)) buf_data_in(i) := Mux((buf_state_en(i) & !buf_error_en(i)), Mux(buf_addr(i)(2), bus_rsp_rdata(63, 32), bus_rsp_rdata(31, 0)), bus_rsp_rdata(31, 0))
buf_cmd_state_bus_en(i) := 0.U buf_cmd_state_bus_en(i) := 0.U
buf_rst(i) := io.dec_tlu_force_halt
} }
is(done_partial_C) { // Other part of dual load hasn't returned is(done_partial_C) { // Other part of dual load hasn't returned
buf_nxtstate(i) := Mux(io.dec_tlu_force_halt.asBool(), idle_C, Mux((buf_ldfwd(i) | buf_ldfwd(buf_dualtag(i)) | any_done_wait_state), done_wait_C, done_C)) buf_nxtstate(i) := Mux(io.dec_tlu_force_halt.asBool(), idle_C, Mux((buf_ldfwd(i) | buf_ldfwd(buf_dualtag(i)) | any_done_wait_state), done_wait_C, done_C))
@ -486,11 +490,13 @@ class lsu_bus_buffer extends Module with RequireAsyncReset with lib {
(buf_ldfwd(buf_dualtag(i)) & (bus_rsp_read_tag === buf_ldfwdtag(buf_dualtag(i)).asUInt()))) (buf_ldfwd(buf_dualtag(i)) & (bus_rsp_read_tag === buf_ldfwdtag(buf_dualtag(i)).asUInt())))
buf_state_en(i) := (buf_state_bus_en(i) & io.lsu_bus_clk_en) | io.dec_tlu_force_halt buf_state_en(i) := (buf_state_bus_en(i) & io.lsu_bus_clk_en) | io.dec_tlu_force_halt
buf_cmd_state_bus_en(i) := 0.U buf_cmd_state_bus_en(i) := 0.U
buf_rst(i) := io.dec_tlu_force_halt
} }
is(done_wait_C) { // WAIT state if there are multiple outstanding nb returns is(done_wait_C) { // WAIT state if there are multiple outstanding nb returns
buf_nxtstate(i) := Mux(io.dec_tlu_force_halt.asBool(), idle_C, done_C) buf_nxtstate(i) := Mux(io.dec_tlu_force_halt.asBool(), idle_C, done_C)
buf_state_en(i) := ((RspPtr === i.asUInt(DEPTH_LOG2.W)) | (buf_dual(i) & (buf_dualtag(i) === RspPtr))) | io.dec_tlu_force_halt buf_state_en(i) := ((RspPtr === i.asUInt(DEPTH_LOG2.W)) | (buf_dual(i) & (buf_dualtag(i) === RspPtr))) | io.dec_tlu_force_halt
buf_cmd_state_bus_en(i) := 0.U buf_cmd_state_bus_en(i) := 0.U
buf_rst(i) := io.dec_tlu_force_halt
} }
is(done_C) { is(done_C) {
buf_nxtstate(i) := idle_C buf_nxtstate(i) := idle_C

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target/scala-2.12/classes/dbg/dbg.class
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