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Add clk out for fpga.

This commit is contained in:
colin 2022-03-15 11:38:18 +00:00
parent 85b5ac0f8b
commit 68653daa2c
1 changed files with 2 additions and 1 deletions
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3
soc/soc_sim.sv
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@ -1,7 +1,7 @@
module soc_sim ( module soc_sim (
input bit core_clk input bit core_clk
); );
wire clk_out;
logic rst_l; logic rst_l;
logic dbg_rst_l; logic dbg_rst_l;
@ -363,6 +363,7 @@ module soc_sim (
soc_top rvsoc ( soc_top rvsoc (
.clk(core_clk), .clk(core_clk),
.clk_o(clk_out),
.rst(rst_l), .rst(rst_l),
.dbg_rst(dbg_rst_l), .dbg_rst(dbg_rst_l),